1 /* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: src/sys/pci/if_sis.c,v 1.13.4.24 2003/03/05 18:42:33 njl Exp $ 33 * $DragonFly: src/sys/dev/netif/sis/if_sis.c,v 1.7 2004/01/06 01:40:49 dillon Exp $ 34 * 35 * $FreeBSD: src/sys/pci/if_sis.c,v 1.13.4.24 2003/03/05 18:42:33 njl Exp $ 36 */ 37 38 /* 39 * SiS 900/SiS 7016 fast ethernet PCI NIC driver. Datasheets are 40 * available from http://www.sis.com.tw. 41 * 42 * This driver also supports the NatSemi DP83815. Datasheets are 43 * available from http://www.national.com. 44 * 45 * Written by Bill Paul <wpaul@ee.columbia.edu> 46 * Electrical Engineering Department 47 * Columbia University, New York City 48 */ 49 50 /* 51 * The SiS 900 is a fairly simple chip. It uses bus master DMA with 52 * simple TX and RX descriptors of 3 longwords in size. The receiver 53 * has a single perfect filter entry for the station address and a 54 * 128-bit multicast hash table. The SiS 900 has a built-in MII-based 55 * transceiver while the 7016 requires an external transceiver chip. 56 * Both chips offer the standard bit-bang MII interface as well as 57 * an enchanced PHY interface which simplifies accessing MII registers. 58 * 59 * The only downside to this chipset is that RX descriptors must be 60 * longword aligned. 61 */ 62 63 #include <sys/param.h> 64 #include <sys/systm.h> 65 #include <sys/sockio.h> 66 #include <sys/mbuf.h> 67 #include <sys/malloc.h> 68 #include <sys/kernel.h> 69 #include <sys/socket.h> 70 #include <sys/sysctl.h> 71 72 #include <net/if.h> 73 #include <net/if_arp.h> 74 #include <net/ethernet.h> 75 #include <net/if_dl.h> 76 #include <net/if_media.h> 77 #include <net/if_types.h> 78 #include <net/vlan/if_vlan_var.h> 79 80 #include <net/bpf.h> 81 82 #include <vm/vm.h> /* for vtophys */ 83 #include <vm/pmap.h> /* for vtophys */ 84 #include <machine/clock.h> /* for DELAY */ 85 #include <machine/bus_pio.h> 86 #include <machine/bus_memio.h> 87 #include <machine/bus.h> 88 #include <machine/resource.h> 89 #include <sys/bus.h> 90 #include <sys/rman.h> 91 92 #include "../mii_layer/mii.h" 93 #include "../mii_layer/miivar.h" 94 95 #include <bus/pci/pcireg.h> 96 #include <bus/pci/pcivar.h> 97 98 #define SIS_USEIOSPACE 99 100 #include "if_sisreg.h" 101 102 /* "controller miibus0" required. See GENERIC if you get errors here. */ 103 #include "miibus_if.h" 104 105 /* 106 * Various supported device vendors/types and their names. 107 */ 108 static struct sis_type sis_devs[] = { 109 { SIS_VENDORID, SIS_DEVICEID_900, "SiS 900 10/100BaseTX" }, 110 { SIS_VENDORID, SIS_DEVICEID_7016, "SiS 7016 10/100BaseTX" }, 111 { NS_VENDORID, NS_DEVICEID_DP83815, "NatSemi DP83815 10/100BaseTX" }, 112 { 0, 0, NULL } 113 }; 114 115 static int sis_probe (device_t); 116 static int sis_attach (device_t); 117 static int sis_detach (device_t); 118 119 static int sis_newbuf (struct sis_softc *, 120 struct sis_desc *, 121 struct mbuf *); 122 static int sis_encap (struct sis_softc *, 123 struct mbuf *, u_int32_t *); 124 static void sis_rxeof (struct sis_softc *); 125 static void sis_rxeoc (struct sis_softc *); 126 static void sis_txeof (struct sis_softc *); 127 static void sis_intr (void *); 128 static void sis_tick (void *); 129 static void sis_start (struct ifnet *); 130 static int sis_ioctl (struct ifnet *, u_long, caddr_t); 131 static void sis_init (void *); 132 static void sis_stop (struct sis_softc *); 133 static void sis_watchdog (struct ifnet *); 134 static void sis_shutdown (device_t); 135 static int sis_ifmedia_upd (struct ifnet *); 136 static void sis_ifmedia_sts (struct ifnet *, struct ifmediareq *); 137 138 static u_int16_t sis_reverse (u_int16_t); 139 static void sis_delay (struct sis_softc *); 140 static void sis_eeprom_idle (struct sis_softc *); 141 static void sis_eeprom_putbyte (struct sis_softc *, int); 142 static void sis_eeprom_getword (struct sis_softc *, int, u_int16_t *); 143 static void sis_read_eeprom (struct sis_softc *, caddr_t, int, 144 int, int); 145 #ifdef __i386__ 146 static void sis_read_cmos (struct sis_softc *, device_t, caddr_t, 147 int, int); 148 static void sis_read_mac (struct sis_softc *, device_t, caddr_t); 149 static device_t sis_find_bridge (device_t); 150 #endif 151 152 static void sis_mii_sync (struct sis_softc *); 153 static void sis_mii_send (struct sis_softc *, u_int32_t, int); 154 static int sis_mii_readreg (struct sis_softc *, struct sis_mii_frame *); 155 static int sis_mii_writereg (struct sis_softc *, struct sis_mii_frame *); 156 static int sis_miibus_readreg (device_t, int, int); 157 static int sis_miibus_writereg (device_t, int, int, int); 158 static void sis_miibus_statchg (device_t); 159 160 static void sis_setmulti_sis (struct sis_softc *); 161 static void sis_setmulti_ns (struct sis_softc *); 162 static u_int32_t sis_crc (struct sis_softc *, caddr_t); 163 static void sis_reset (struct sis_softc *); 164 static int sis_list_rx_init (struct sis_softc *); 165 static int sis_list_tx_init (struct sis_softc *); 166 167 #ifdef SIS_USEIOSPACE 168 #define SIS_RES SYS_RES_IOPORT 169 #define SIS_RID SIS_PCI_LOIO 170 #else 171 #define SIS_RES SYS_RES_MEMORY 172 #define SIS_RID SIS_PCI_LOMEM 173 #endif 174 175 static device_method_t sis_methods[] = { 176 /* Device interface */ 177 DEVMETHOD(device_probe, sis_probe), 178 DEVMETHOD(device_attach, sis_attach), 179 DEVMETHOD(device_detach, sis_detach), 180 DEVMETHOD(device_shutdown, sis_shutdown), 181 182 /* bus interface */ 183 DEVMETHOD(bus_print_child, bus_generic_print_child), 184 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 185 186 /* MII interface */ 187 DEVMETHOD(miibus_readreg, sis_miibus_readreg), 188 DEVMETHOD(miibus_writereg, sis_miibus_writereg), 189 DEVMETHOD(miibus_statchg, sis_miibus_statchg), 190 191 { 0, 0 } 192 }; 193 194 static driver_t sis_driver = { 195 "sis", 196 sis_methods, 197 sizeof(struct sis_softc) 198 }; 199 200 static devclass_t sis_devclass; 201 202 DECLARE_DUMMY_MODULE(if_sis); 203 DRIVER_MODULE(if_sis, pci, sis_driver, sis_devclass, 0, 0); 204 DRIVER_MODULE(miibus, sis, miibus_driver, miibus_devclass, 0, 0); 205 206 #define SIS_SETBIT(sc, reg, x) \ 207 CSR_WRITE_4(sc, reg, \ 208 CSR_READ_4(sc, reg) | (x)) 209 210 #define SIS_CLRBIT(sc, reg, x) \ 211 CSR_WRITE_4(sc, reg, \ 212 CSR_READ_4(sc, reg) & ~(x)) 213 214 #define SIO_SET(x) \ 215 CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) | x) 216 217 #define SIO_CLR(x) \ 218 CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) & ~x) 219 220 /* 221 * Routine to reverse the bits in a word. Stolen almost 222 * verbatim from /usr/games/fortune. 223 */ 224 static u_int16_t sis_reverse(n) 225 u_int16_t n; 226 { 227 n = ((n >> 1) & 0x5555) | ((n << 1) & 0xaaaa); 228 n = ((n >> 2) & 0x3333) | ((n << 2) & 0xcccc); 229 n = ((n >> 4) & 0x0f0f) | ((n << 4) & 0xf0f0); 230 n = ((n >> 8) & 0x00ff) | ((n << 8) & 0xff00); 231 232 return(n); 233 } 234 235 static void sis_delay(sc) 236 struct sis_softc *sc; 237 { 238 int idx; 239 240 for (idx = (300 / 33) + 1; idx > 0; idx--) 241 CSR_READ_4(sc, SIS_CSR); 242 243 return; 244 } 245 246 static void sis_eeprom_idle(sc) 247 struct sis_softc *sc; 248 { 249 int i; 250 251 SIO_SET(SIS_EECTL_CSEL); 252 sis_delay(sc); 253 SIO_SET(SIS_EECTL_CLK); 254 sis_delay(sc); 255 256 for (i = 0; i < 25; i++) { 257 SIO_CLR(SIS_EECTL_CLK); 258 sis_delay(sc); 259 SIO_SET(SIS_EECTL_CLK); 260 sis_delay(sc); 261 } 262 263 SIO_CLR(SIS_EECTL_CLK); 264 sis_delay(sc); 265 SIO_CLR(SIS_EECTL_CSEL); 266 sis_delay(sc); 267 CSR_WRITE_4(sc, SIS_EECTL, 0x00000000); 268 269 return; 270 } 271 272 /* 273 * Send a read command and address to the EEPROM, check for ACK. 274 */ 275 static void sis_eeprom_putbyte(sc, addr) 276 struct sis_softc *sc; 277 int addr; 278 { 279 int d, i; 280 281 d = addr | SIS_EECMD_READ; 282 283 /* 284 * Feed in each bit and stobe the clock. 285 */ 286 for (i = 0x400; i; i >>= 1) { 287 if (d & i) { 288 SIO_SET(SIS_EECTL_DIN); 289 } else { 290 SIO_CLR(SIS_EECTL_DIN); 291 } 292 sis_delay(sc); 293 SIO_SET(SIS_EECTL_CLK); 294 sis_delay(sc); 295 SIO_CLR(SIS_EECTL_CLK); 296 sis_delay(sc); 297 } 298 299 return; 300 } 301 302 /* 303 * Read a word of data stored in the EEPROM at address 'addr.' 304 */ 305 static void sis_eeprom_getword(sc, addr, dest) 306 struct sis_softc *sc; 307 int addr; 308 u_int16_t *dest; 309 { 310 int i; 311 u_int16_t word = 0; 312 313 /* Force EEPROM to idle state. */ 314 sis_eeprom_idle(sc); 315 316 /* Enter EEPROM access mode. */ 317 sis_delay(sc); 318 SIO_CLR(SIS_EECTL_CLK); 319 sis_delay(sc); 320 SIO_SET(SIS_EECTL_CSEL); 321 sis_delay(sc); 322 323 /* 324 * Send address of word we want to read. 325 */ 326 sis_eeprom_putbyte(sc, addr); 327 328 /* 329 * Start reading bits from EEPROM. 330 */ 331 for (i = 0x8000; i; i >>= 1) { 332 SIO_SET(SIS_EECTL_CLK); 333 sis_delay(sc); 334 if (CSR_READ_4(sc, SIS_EECTL) & SIS_EECTL_DOUT) 335 word |= i; 336 sis_delay(sc); 337 SIO_CLR(SIS_EECTL_CLK); 338 sis_delay(sc); 339 } 340 341 /* Turn off EEPROM access mode. */ 342 sis_eeprom_idle(sc); 343 344 *dest = word; 345 346 return; 347 } 348 349 /* 350 * Read a sequence of words from the EEPROM. 351 */ 352 static void sis_read_eeprom(sc, dest, off, cnt, swap) 353 struct sis_softc *sc; 354 caddr_t dest; 355 int off; 356 int cnt; 357 int swap; 358 { 359 int i; 360 u_int16_t word = 0, *ptr; 361 362 for (i = 0; i < cnt; i++) { 363 sis_eeprom_getword(sc, off + i, &word); 364 ptr = (u_int16_t *)(dest + (i * 2)); 365 if (swap) 366 *ptr = ntohs(word); 367 else 368 *ptr = word; 369 } 370 371 return; 372 } 373 374 #ifdef __i386__ 375 static device_t sis_find_bridge(dev) 376 device_t dev; 377 { 378 devclass_t pci_devclass; 379 device_t *pci_devices; 380 int pci_count = 0; 381 device_t *pci_children; 382 int pci_childcount = 0; 383 device_t *busp, *childp; 384 device_t child = NULL; 385 int i, j; 386 387 if ((pci_devclass = devclass_find("pci")) == NULL) 388 return(NULL); 389 390 devclass_get_devices(pci_devclass, &pci_devices, &pci_count); 391 392 for (i = 0, busp = pci_devices; i < pci_count; i++, busp++) { 393 pci_childcount = 0; 394 device_get_children(*busp, &pci_children, &pci_childcount); 395 for (j = 0, childp = pci_children; 396 j < pci_childcount; j++, childp++) { 397 if (pci_get_vendor(*childp) == SIS_VENDORID && 398 pci_get_device(*childp) == 0x0008) { 399 child = *childp; 400 goto done; 401 } 402 } 403 } 404 405 done: 406 free(pci_devices, M_TEMP); 407 free(pci_children, M_TEMP); 408 return(child); 409 } 410 411 static void sis_read_cmos(sc, dev, dest, off, cnt) 412 struct sis_softc *sc; 413 device_t dev; 414 caddr_t dest; 415 int off; 416 int cnt; 417 { 418 device_t bridge; 419 u_int8_t reg; 420 int i; 421 bus_space_tag_t btag; 422 423 bridge = sis_find_bridge(dev); 424 if (bridge == NULL) 425 return; 426 reg = pci_read_config(bridge, 0x48, 1); 427 pci_write_config(bridge, 0x48, reg|0x40, 1); 428 429 /* XXX */ 430 btag = I386_BUS_SPACE_IO; 431 432 for (i = 0; i < cnt; i++) { 433 bus_space_write_1(btag, 0x0, 0x70, i + off); 434 *(dest + i) = bus_space_read_1(btag, 0x0, 0x71); 435 } 436 437 pci_write_config(bridge, 0x48, reg & ~0x40, 1); 438 return; 439 } 440 441 static void sis_read_mac(sc, dev, dest) 442 struct sis_softc *sc; 443 device_t dev; 444 caddr_t dest; 445 { 446 u_int32_t filtsave, csrsave; 447 448 filtsave = CSR_READ_4(sc, SIS_RXFILT_CTL); 449 csrsave = CSR_READ_4(sc, SIS_CSR); 450 451 CSR_WRITE_4(sc, SIS_CSR, SIS_CSR_RELOAD | filtsave); 452 CSR_WRITE_4(sc, SIS_CSR, 0); 453 454 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave & ~SIS_RXFILTCTL_ENABLE); 455 456 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR0); 457 ((u_int16_t *)dest)[0] = CSR_READ_2(sc, SIS_RXFILT_DATA); 458 CSR_WRITE_4(sc, SIS_RXFILT_CTL,SIS_FILTADDR_PAR1); 459 ((u_int16_t *)dest)[1] = CSR_READ_2(sc, SIS_RXFILT_DATA); 460 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR2); 461 ((u_int16_t *)dest)[2] = CSR_READ_2(sc, SIS_RXFILT_DATA); 462 463 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave); 464 CSR_WRITE_4(sc, SIS_CSR, csrsave); 465 return; 466 } 467 #endif 468 469 /* 470 * Sync the PHYs by setting data bit and strobing the clock 32 times. 471 */ 472 static void sis_mii_sync(sc) 473 struct sis_softc *sc; 474 { 475 int i; 476 477 SIO_SET(SIS_MII_DIR|SIS_MII_DATA); 478 479 for (i = 0; i < 32; i++) { 480 SIO_SET(SIS_MII_CLK); 481 DELAY(1); 482 SIO_CLR(SIS_MII_CLK); 483 DELAY(1); 484 } 485 486 return; 487 } 488 489 /* 490 * Clock a series of bits through the MII. 491 */ 492 static void sis_mii_send(sc, bits, cnt) 493 struct sis_softc *sc; 494 u_int32_t bits; 495 int cnt; 496 { 497 int i; 498 499 SIO_CLR(SIS_MII_CLK); 500 501 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 502 if (bits & i) { 503 SIO_SET(SIS_MII_DATA); 504 } else { 505 SIO_CLR(SIS_MII_DATA); 506 } 507 DELAY(1); 508 SIO_CLR(SIS_MII_CLK); 509 DELAY(1); 510 SIO_SET(SIS_MII_CLK); 511 } 512 } 513 514 /* 515 * Read an PHY register through the MII. 516 */ 517 static int sis_mii_readreg(sc, frame) 518 struct sis_softc *sc; 519 struct sis_mii_frame *frame; 520 521 { 522 int i, ack, s; 523 524 s = splimp(); 525 526 /* 527 * Set up frame for RX. 528 */ 529 frame->mii_stdelim = SIS_MII_STARTDELIM; 530 frame->mii_opcode = SIS_MII_READOP; 531 frame->mii_turnaround = 0; 532 frame->mii_data = 0; 533 534 /* 535 * Turn on data xmit. 536 */ 537 SIO_SET(SIS_MII_DIR); 538 539 sis_mii_sync(sc); 540 541 /* 542 * Send command/address info. 543 */ 544 sis_mii_send(sc, frame->mii_stdelim, 2); 545 sis_mii_send(sc, frame->mii_opcode, 2); 546 sis_mii_send(sc, frame->mii_phyaddr, 5); 547 sis_mii_send(sc, frame->mii_regaddr, 5); 548 549 /* Idle bit */ 550 SIO_CLR((SIS_MII_CLK|SIS_MII_DATA)); 551 DELAY(1); 552 SIO_SET(SIS_MII_CLK); 553 DELAY(1); 554 555 /* Turn off xmit. */ 556 SIO_CLR(SIS_MII_DIR); 557 558 /* Check for ack */ 559 SIO_CLR(SIS_MII_CLK); 560 DELAY(1); 561 ack = CSR_READ_4(sc, SIS_EECTL) & SIS_MII_DATA; 562 SIO_SET(SIS_MII_CLK); 563 DELAY(1); 564 565 /* 566 * Now try reading data bits. If the ack failed, we still 567 * need to clock through 16 cycles to keep the PHY(s) in sync. 568 */ 569 if (ack) { 570 for(i = 0; i < 16; i++) { 571 SIO_CLR(SIS_MII_CLK); 572 DELAY(1); 573 SIO_SET(SIS_MII_CLK); 574 DELAY(1); 575 } 576 goto fail; 577 } 578 579 for (i = 0x8000; i; i >>= 1) { 580 SIO_CLR(SIS_MII_CLK); 581 DELAY(1); 582 if (!ack) { 583 if (CSR_READ_4(sc, SIS_EECTL) & SIS_MII_DATA) 584 frame->mii_data |= i; 585 DELAY(1); 586 } 587 SIO_SET(SIS_MII_CLK); 588 DELAY(1); 589 } 590 591 fail: 592 593 SIO_CLR(SIS_MII_CLK); 594 DELAY(1); 595 SIO_SET(SIS_MII_CLK); 596 DELAY(1); 597 598 splx(s); 599 600 if (ack) 601 return(1); 602 return(0); 603 } 604 605 /* 606 * Write to a PHY register through the MII. 607 */ 608 static int sis_mii_writereg(sc, frame) 609 struct sis_softc *sc; 610 struct sis_mii_frame *frame; 611 612 { 613 int s; 614 615 s = splimp(); 616 /* 617 * Set up frame for TX. 618 */ 619 620 frame->mii_stdelim = SIS_MII_STARTDELIM; 621 frame->mii_opcode = SIS_MII_WRITEOP; 622 frame->mii_turnaround = SIS_MII_TURNAROUND; 623 624 /* 625 * Turn on data output. 626 */ 627 SIO_SET(SIS_MII_DIR); 628 629 sis_mii_sync(sc); 630 631 sis_mii_send(sc, frame->mii_stdelim, 2); 632 sis_mii_send(sc, frame->mii_opcode, 2); 633 sis_mii_send(sc, frame->mii_phyaddr, 5); 634 sis_mii_send(sc, frame->mii_regaddr, 5); 635 sis_mii_send(sc, frame->mii_turnaround, 2); 636 sis_mii_send(sc, frame->mii_data, 16); 637 638 /* Idle bit. */ 639 SIO_SET(SIS_MII_CLK); 640 DELAY(1); 641 SIO_CLR(SIS_MII_CLK); 642 DELAY(1); 643 644 /* 645 * Turn off xmit. 646 */ 647 SIO_CLR(SIS_MII_DIR); 648 649 splx(s); 650 651 return(0); 652 } 653 654 static int sis_miibus_readreg(dev, phy, reg) 655 device_t dev; 656 int phy, reg; 657 { 658 struct sis_softc *sc; 659 int i, val = 0; 660 struct sis_mii_frame frame; 661 662 sc = device_get_softc(dev); 663 664 if (sc->sis_type == SIS_TYPE_83815) { 665 if (phy != 0) 666 return(0); 667 /* 668 * The NatSemi chip can take a while after 669 * a reset to come ready, during which the BMSR 670 * returns a value of 0. This is *never* supposed 671 * to happen: some of the BMSR bits are meant to 672 * be hardwired in the on position, and this can 673 * confuse the miibus code a bit during the probe 674 * and attach phase. So we make an effort to check 675 * for this condition and wait for it to clear. 676 */ 677 if (!CSR_READ_4(sc, NS_BMSR)) 678 DELAY(1000); 679 return CSR_READ_4(sc, NS_BMCR + (reg * 4)); 680 } 681 /* 682 * Chipsets < SIS_635 seem not to be able to read/write 683 * through mdio. Use the enhanced PHY access register 684 * again for them. 685 */ 686 if (sc->sis_type == SIS_TYPE_900 && 687 sc->sis_rev < SIS_REV_635) { 688 689 if (phy != 0) 690 return(0); 691 692 CSR_WRITE_4(sc, SIS_PHYCTL, 693 (phy << 11) | (reg << 6) | SIS_PHYOP_READ); 694 SIS_SETBIT(sc, SIS_PHYCTL, SIS_PHYCTL_ACCESS); 695 696 for (i = 0; i < SIS_TIMEOUT; i++) { 697 if (!(CSR_READ_4(sc, SIS_PHYCTL) & SIS_PHYCTL_ACCESS)) 698 break; 699 } 700 701 if (i == SIS_TIMEOUT) { 702 printf("sis%d: PHY failed to come ready\n", 703 sc->sis_unit); 704 return(0); 705 } 706 707 val = (CSR_READ_4(sc, SIS_PHYCTL) >> 16) & 0xFFFF; 708 709 if (val == 0xFFFF) 710 return(0); 711 712 return(val); 713 } else { 714 bzero((char *)&frame, sizeof(frame)); 715 frame.mii_phyaddr = phy; 716 frame.mii_regaddr = reg; 717 sis_mii_readreg(sc, &frame); 718 return(frame.mii_data); 719 } 720 } 721 722 static int sis_miibus_writereg(dev, phy, reg, data) 723 device_t dev; 724 int phy, reg, data; 725 { 726 struct sis_softc *sc; 727 int i; 728 struct sis_mii_frame frame; 729 730 sc = device_get_softc(dev); 731 732 if (sc->sis_type == SIS_TYPE_83815) { 733 if (phy != 0) 734 return(0); 735 CSR_WRITE_4(sc, NS_BMCR + (reg * 4), data); 736 return(0); 737 } 738 739 if (sc->sis_type == SIS_TYPE_900 && 740 sc->sis_rev < SIS_REV_635) { 741 742 if (phy != 0) 743 return(0); 744 CSR_WRITE_4(sc, SIS_PHYCTL, (data << 16) | (phy << 11) | 745 (reg << 6) | SIS_PHYOP_WRITE); 746 SIS_SETBIT(sc, SIS_PHYCTL, SIS_PHYCTL_ACCESS); 747 748 for (i = 0; i < SIS_TIMEOUT; i++) { 749 if (!(CSR_READ_4(sc, SIS_PHYCTL) & SIS_PHYCTL_ACCESS)) 750 break; 751 } 752 753 if (i == SIS_TIMEOUT) 754 printf("sis%d: PHY failed to come ready\n", 755 sc->sis_unit); 756 } else { 757 bzero((char *)&frame, sizeof(frame)); 758 759 frame.mii_phyaddr = phy; 760 frame.mii_regaddr = reg; 761 frame.mii_data = data; 762 sis_mii_writereg(sc, &frame); 763 } 764 return(0); 765 } 766 767 static void sis_miibus_statchg(dev) 768 device_t dev; 769 { 770 struct sis_softc *sc; 771 772 sc = device_get_softc(dev); 773 sis_init(sc); 774 775 return; 776 } 777 778 static u_int32_t sis_crc(sc, addr) 779 struct sis_softc *sc; 780 caddr_t addr; 781 { 782 u_int32_t crc, carry; 783 int i, j; 784 u_int8_t c; 785 786 /* Compute CRC for the address value. */ 787 crc = 0xFFFFFFFF; /* initial value */ 788 789 for (i = 0; i < 6; i++) { 790 c = *(addr + i); 791 for (j = 0; j < 8; j++) { 792 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 793 crc <<= 1; 794 c >>= 1; 795 if (carry) 796 crc = (crc ^ 0x04c11db6) | carry; 797 } 798 } 799 800 /* 801 * return the filter bit position 802 * 803 * The NatSemi chip has a 512-bit filter, which is 804 * different than the SiS, so we special-case it. 805 */ 806 if (sc->sis_type == SIS_TYPE_83815) 807 return (crc >> 23); 808 else if (sc->sis_rev >= SIS_REV_635 || 809 sc->sis_rev == SIS_REV_900B) 810 return (crc >> 24); 811 else 812 return (crc >> 25); 813 } 814 815 static void sis_setmulti_ns(sc) 816 struct sis_softc *sc; 817 { 818 struct ifnet *ifp; 819 struct ifmultiaddr *ifma; 820 u_int32_t h = 0, i, filtsave; 821 int bit, index; 822 823 ifp = &sc->arpcom.ac_if; 824 825 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 826 SIS_CLRBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_MCHASH); 827 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLMULTI); 828 return; 829 } 830 831 /* 832 * We have to explicitly enable the multicast hash table 833 * on the NatSemi chip if we want to use it, which we do. 834 */ 835 SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_MCHASH); 836 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLMULTI); 837 838 filtsave = CSR_READ_4(sc, SIS_RXFILT_CTL); 839 840 /* first, zot all the existing hash bits */ 841 for (i = 0; i < 32; i++) { 842 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_FMEM_LO + (i*2)); 843 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 0); 844 } 845 846 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 847 ifma = ifma->ifma_link.le_next) { 848 if (ifma->ifma_addr->sa_family != AF_LINK) 849 continue; 850 h = sis_crc(sc, LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 851 index = h >> 3; 852 bit = h & 0x1F; 853 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_FMEM_LO + index); 854 if (bit > 0xF) 855 bit -= 0x10; 856 SIS_SETBIT(sc, SIS_RXFILT_DATA, (1 << bit)); 857 } 858 859 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave); 860 861 return; 862 } 863 864 static void sis_setmulti_sis(sc) 865 struct sis_softc *sc; 866 { 867 struct ifnet *ifp; 868 struct ifmultiaddr *ifma; 869 u_int32_t h, i, n, ctl; 870 u_int16_t hashes[16]; 871 872 ifp = &sc->arpcom.ac_if; 873 874 /* hash table size */ 875 if (sc->sis_rev >= SIS_REV_635 || 876 sc->sis_rev == SIS_REV_900B) 877 n = 16; 878 else 879 n = 8; 880 881 ctl = CSR_READ_4(sc, SIS_RXFILT_CTL) & SIS_RXFILTCTL_ENABLE; 882 883 if (ifp->if_flags & IFF_BROADCAST) 884 ctl |= SIS_RXFILTCTL_BROAD; 885 886 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 887 ctl |= SIS_RXFILTCTL_ALLMULTI; 888 if (ifp->if_flags & IFF_PROMISC) 889 ctl |= SIS_RXFILTCTL_BROAD|SIS_RXFILTCTL_ALLPHYS; 890 for (i = 0; i < n; i++) 891 hashes[i] = ~0; 892 } else { 893 for (i = 0; i < n; i++) 894 hashes[i] = 0; 895 i = 0; 896 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 897 if (ifma->ifma_addr->sa_family != AF_LINK) 898 continue; 899 h = sis_crc(sc, 900 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 901 hashes[h >> 4] |= 1 << (h & 0xf); 902 i++; 903 } 904 if (i > n) { 905 ctl |= SIS_RXFILTCTL_ALLMULTI; 906 for (i = 0; i < n; i++) 907 hashes[i] = ~0; 908 } 909 } 910 911 for (i = 0; i < n; i++) { 912 CSR_WRITE_4(sc, SIS_RXFILT_CTL, (4 + i) << 16); 913 CSR_WRITE_4(sc, SIS_RXFILT_DATA, hashes[i]); 914 } 915 916 CSR_WRITE_4(sc, SIS_RXFILT_CTL, ctl); 917 } 918 919 static void sis_reset(sc) 920 struct sis_softc *sc; 921 { 922 int i; 923 924 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RESET); 925 926 for (i = 0; i < SIS_TIMEOUT; i++) { 927 if (!(CSR_READ_4(sc, SIS_CSR) & SIS_CSR_RESET)) 928 break; 929 } 930 931 if (i == SIS_TIMEOUT) 932 printf("sis%d: reset never completed\n", sc->sis_unit); 933 934 /* Wait a little while for the chip to get its brains in order. */ 935 DELAY(1000); 936 937 /* 938 * If this is a NetSemi chip, make sure to clear 939 * PME mode. 940 */ 941 if (sc->sis_type == SIS_TYPE_83815) { 942 CSR_WRITE_4(sc, NS_CLKRUN, NS_CLKRUN_PMESTS); 943 CSR_WRITE_4(sc, NS_CLKRUN, 0); 944 } 945 946 return; 947 } 948 949 /* 950 * Probe for an SiS chip. Check the PCI vendor and device 951 * IDs against our list and return a device name if we find a match. 952 */ 953 static int sis_probe(dev) 954 device_t dev; 955 { 956 struct sis_type *t; 957 958 t = sis_devs; 959 960 while(t->sis_name != NULL) { 961 if ((pci_get_vendor(dev) == t->sis_vid) && 962 (pci_get_device(dev) == t->sis_did)) { 963 device_set_desc(dev, t->sis_name); 964 return(0); 965 } 966 t++; 967 } 968 969 return(ENXIO); 970 } 971 972 /* 973 * Attach the interface. Allocate softc structures, do ifmedia 974 * setup and ethernet/BPF attach. 975 */ 976 static int sis_attach(dev) 977 device_t dev; 978 { 979 int s; 980 u_char eaddr[ETHER_ADDR_LEN]; 981 u_int32_t command; 982 struct sis_softc *sc; 983 struct ifnet *ifp; 984 int unit, error, rid, waittime; 985 986 s = splimp(); 987 988 error = waittime = 0; 989 sc = device_get_softc(dev); 990 unit = device_get_unit(dev); 991 bzero(sc, sizeof(struct sis_softc)); 992 993 if (pci_get_device(dev) == SIS_DEVICEID_900) 994 sc->sis_type = SIS_TYPE_900; 995 if (pci_get_device(dev) == SIS_DEVICEID_7016) 996 sc->sis_type = SIS_TYPE_7016; 997 if (pci_get_vendor(dev) == NS_VENDORID) 998 sc->sis_type = SIS_TYPE_83815; 999 1000 sc->sis_rev = pci_read_config(dev, PCIR_REVID, 1); 1001 1002 /* 1003 * Handle power management nonsense. 1004 */ 1005 1006 command = pci_read_config(dev, SIS_PCI_CAPID, 4) & 0x000000FF; 1007 if (command == 0x01) { 1008 1009 command = pci_read_config(dev, SIS_PCI_PWRMGMTCTRL, 4); 1010 if (command & SIS_PSTATE_MASK) { 1011 u_int32_t iobase, membase, irq; 1012 1013 /* Save important PCI config data. */ 1014 iobase = pci_read_config(dev, SIS_PCI_LOIO, 4); 1015 membase = pci_read_config(dev, SIS_PCI_LOMEM, 4); 1016 irq = pci_read_config(dev, SIS_PCI_INTLINE, 4); 1017 1018 /* Reset the power state. */ 1019 printf("sis%d: chip is in D%d power mode " 1020 "-- setting to D0\n", unit, command & SIS_PSTATE_MASK); 1021 command &= 0xFFFFFFFC; 1022 pci_write_config(dev, SIS_PCI_PWRMGMTCTRL, command, 4); 1023 1024 /* Restore PCI config data. */ 1025 pci_write_config(dev, SIS_PCI_LOIO, iobase, 4); 1026 pci_write_config(dev, SIS_PCI_LOMEM, membase, 4); 1027 pci_write_config(dev, SIS_PCI_INTLINE, irq, 4); 1028 } 1029 } 1030 1031 /* 1032 * Map control/status registers. 1033 */ 1034 command = pci_read_config(dev, PCIR_COMMAND, 4); 1035 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 1036 pci_write_config(dev, PCIR_COMMAND, command, 4); 1037 command = pci_read_config(dev, PCIR_COMMAND, 4); 1038 1039 #ifdef SIS_USEIOSPACE 1040 if (!(command & PCIM_CMD_PORTEN)) { 1041 printf("sis%d: failed to enable I/O ports!\n", unit); 1042 error = ENXIO;; 1043 goto fail; 1044 } 1045 #else 1046 if (!(command & PCIM_CMD_MEMEN)) { 1047 printf("sis%d: failed to enable memory mapping!\n", unit); 1048 error = ENXIO;; 1049 goto fail; 1050 } 1051 #endif 1052 1053 rid = SIS_RID; 1054 sc->sis_res = bus_alloc_resource(dev, SIS_RES, &rid, 1055 0, ~0, 1, RF_ACTIVE); 1056 1057 if (sc->sis_res == NULL) { 1058 printf("sis%d: couldn't map ports/memory\n", unit); 1059 error = ENXIO; 1060 goto fail; 1061 } 1062 1063 sc->sis_btag = rman_get_bustag(sc->sis_res); 1064 sc->sis_bhandle = rman_get_bushandle(sc->sis_res); 1065 1066 /* Allocate interrupt */ 1067 rid = 0; 1068 sc->sis_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 1069 RF_SHAREABLE | RF_ACTIVE); 1070 1071 if (sc->sis_irq == NULL) { 1072 printf("sis%d: couldn't map interrupt\n", unit); 1073 bus_release_resource(dev, SIS_RES, SIS_RID, sc->sis_res); 1074 error = ENXIO; 1075 goto fail; 1076 } 1077 1078 error = bus_setup_intr(dev, sc->sis_irq, INTR_TYPE_NET, 1079 sis_intr, sc, &sc->sis_intrhand); 1080 1081 if (error) { 1082 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sis_irq); 1083 bus_release_resource(dev, SIS_RES, SIS_RID, sc->sis_res); 1084 printf("sis%d: couldn't set up irq\n", unit); 1085 goto fail; 1086 } 1087 1088 /* Reset the adapter. */ 1089 sis_reset(sc); 1090 1091 if (sc->sis_type == SIS_TYPE_900 && 1092 (sc->sis_rev == SIS_REV_635 || 1093 sc->sis_rev == SIS_REV_900B)) { 1094 SIO_SET(SIS_CFG_RND_CNT); 1095 SIO_SET(SIS_CFG_PERR_DETECT); 1096 } 1097 1098 /* 1099 * Get station address from the EEPROM. 1100 */ 1101 switch (pci_get_vendor(dev)) { 1102 case NS_VENDORID: 1103 /* 1104 * Reading the MAC address out of the EEPROM on 1105 * the NatSemi chip takes a bit more work than 1106 * you'd expect. The address spans 4 16-bit words, 1107 * with the first word containing only a single bit. 1108 * You have to shift everything over one bit to 1109 * get it aligned properly. Also, the bits are 1110 * stored backwards (the LSB is really the MSB, 1111 * and so on) so you have to reverse them in order 1112 * to get the MAC address into the form we want. 1113 * Why? Who the hell knows. 1114 */ 1115 { 1116 u_int16_t tmp[4]; 1117 1118 sis_read_eeprom(sc, (caddr_t)&tmp, 1119 NS_EE_NODEADDR, 4, 0); 1120 1121 /* Shift everything over one bit. */ 1122 tmp[3] = tmp[3] >> 1; 1123 tmp[3] |= tmp[2] << 15; 1124 tmp[2] = tmp[2] >> 1; 1125 tmp[2] |= tmp[1] << 15; 1126 tmp[1] = tmp[1] >> 1; 1127 tmp[1] |= tmp[0] << 15; 1128 1129 /* Now reverse all the bits. */ 1130 tmp[3] = sis_reverse(tmp[3]); 1131 tmp[2] = sis_reverse(tmp[2]); 1132 tmp[1] = sis_reverse(tmp[1]); 1133 1134 bcopy((char *)&tmp[1], eaddr, ETHER_ADDR_LEN); 1135 } 1136 break; 1137 case SIS_VENDORID: 1138 default: 1139 #ifdef __i386__ 1140 /* 1141 * If this is a SiS 630E chipset with an embedded 1142 * SiS 900 controller, we have to read the MAC address 1143 * from the APC CMOS RAM. Our method for doing this 1144 * is very ugly since we have to reach out and grab 1145 * ahold of hardware for which we cannot properly 1146 * allocate resources. This code is only compiled on 1147 * the i386 architecture since the SiS 630E chipset 1148 * is for x86 motherboards only. Note that there are 1149 * a lot of magic numbers in this hack. These are 1150 * taken from SiS's Linux driver. I'd like to replace 1151 * them with proper symbolic definitions, but that 1152 * requires some datasheets that I don't have access 1153 * to at the moment. 1154 */ 1155 if (sc->sis_rev == SIS_REV_630S || 1156 sc->sis_rev == SIS_REV_630E || 1157 sc->sis_rev == SIS_REV_630EA1) 1158 sis_read_cmos(sc, dev, (caddr_t)&eaddr, 0x9, 6); 1159 1160 else if (sc->sis_rev == SIS_REV_635 || 1161 sc->sis_rev == SIS_REV_630ET) 1162 sis_read_mac(sc, dev, (caddr_t)&eaddr); 1163 else if (sc->sis_rev == SIS_REV_96x) { 1164 /* 1165 * Allow to read EEPROM from LAN. It is shared 1166 * between a 1394 controller and the NIC and each 1167 * time we access it, we need to set SIS_EECMD_REQ. 1168 */ 1169 SIO_SET(SIS_EECMD_REQ); 1170 for (waittime = 0; waittime < SIS_TIMEOUT; 1171 waittime++) { 1172 /* Force EEPROM to idle state. */ 1173 sis_eeprom_idle(sc); 1174 if (CSR_READ_4(sc, SIS_EECTL) & SIS_EECMD_GNT) { 1175 sis_read_eeprom(sc, (caddr_t)&eaddr, 1176 SIS_EE_NODEADDR, 3, 0); 1177 break; 1178 } 1179 DELAY(1); 1180 } 1181 /* 1182 * Set SIS_EECTL_CLK to high, so a other master 1183 * can operate on the i2c bus. 1184 */ 1185 SIO_SET(SIS_EECTL_CLK); 1186 /* Refuse EEPROM access by LAN */ 1187 SIO_SET(SIS_EECMD_DONE); 1188 } else 1189 #endif 1190 sis_read_eeprom(sc, (caddr_t)&eaddr, 1191 SIS_EE_NODEADDR, 3, 0); 1192 break; 1193 } 1194 1195 /* 1196 * A SiS chip was detected. Inform the world. 1197 */ 1198 printf("sis%d: Ethernet address: %6D\n", unit, eaddr, ":"); 1199 1200 sc->sis_unit = unit; 1201 callout_handle_init(&sc->sis_stat_ch); 1202 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 1203 1204 sc->sis_ldata = contigmalloc(sizeof(struct sis_list_data), M_DEVBUF, 1205 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 1206 1207 if (sc->sis_ldata == NULL) { 1208 printf("sis%d: no memory for list buffers!\n", unit); 1209 bus_teardown_intr(dev, sc->sis_irq, sc->sis_intrhand); 1210 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sis_irq); 1211 bus_release_resource(dev, SIS_RES, SIS_RID, sc->sis_res); 1212 error = ENXIO; 1213 goto fail; 1214 } 1215 bzero(sc->sis_ldata, sizeof(struct sis_list_data)); 1216 1217 ifp = &sc->arpcom.ac_if; 1218 ifp->if_softc = sc; 1219 if_initname(ifp, "sis", unit); 1220 ifp->if_mtu = ETHERMTU; 1221 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1222 ifp->if_ioctl = sis_ioctl; 1223 ifp->if_output = ether_output; 1224 ifp->if_start = sis_start; 1225 ifp->if_watchdog = sis_watchdog; 1226 ifp->if_init = sis_init; 1227 ifp->if_baudrate = 10000000; 1228 ifp->if_snd.ifq_maxlen = SIS_TX_LIST_CNT - 1; 1229 1230 /* 1231 * Do MII setup. 1232 */ 1233 if (mii_phy_probe(dev, &sc->sis_miibus, 1234 sis_ifmedia_upd, sis_ifmedia_sts)) { 1235 printf("sis%d: MII without any PHY!\n", sc->sis_unit); 1236 contigfree(sc->sis_ldata, sizeof(struct sis_list_data), 1237 M_DEVBUF); 1238 bus_teardown_intr(dev, sc->sis_irq, sc->sis_intrhand); 1239 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sis_irq); 1240 bus_release_resource(dev, SIS_RES, SIS_RID, sc->sis_res); 1241 error = ENXIO; 1242 goto fail; 1243 } 1244 1245 /* 1246 * Call MI attach routine. 1247 */ 1248 ether_ifattach(ifp, ETHER_BPF_SUPPORTED); 1249 1250 /* 1251 * Tell the upper layer(s) we support long frames. 1252 */ 1253 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1254 1255 callout_handle_init(&sc->sis_stat_ch); 1256 1257 fail: 1258 splx(s); 1259 return(error); 1260 } 1261 1262 static int sis_detach(dev) 1263 device_t dev; 1264 { 1265 struct sis_softc *sc; 1266 struct ifnet *ifp; 1267 int s; 1268 1269 s = splimp(); 1270 1271 sc = device_get_softc(dev); 1272 ifp = &sc->arpcom.ac_if; 1273 1274 sis_reset(sc); 1275 sis_stop(sc); 1276 ether_ifdetach(ifp, ETHER_BPF_SUPPORTED); 1277 1278 bus_generic_detach(dev); 1279 device_delete_child(dev, sc->sis_miibus); 1280 1281 bus_teardown_intr(dev, sc->sis_irq, sc->sis_intrhand); 1282 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sis_irq); 1283 bus_release_resource(dev, SIS_RES, SIS_RID, sc->sis_res); 1284 1285 contigfree(sc->sis_ldata, sizeof(struct sis_list_data), M_DEVBUF); 1286 1287 splx(s); 1288 1289 return(0); 1290 } 1291 1292 /* 1293 * Initialize the transmit descriptors. 1294 */ 1295 static int sis_list_tx_init(sc) 1296 struct sis_softc *sc; 1297 { 1298 struct sis_list_data *ld; 1299 struct sis_ring_data *cd; 1300 int i, nexti; 1301 1302 cd = &sc->sis_cdata; 1303 ld = sc->sis_ldata; 1304 1305 for (i = 0; i < SIS_TX_LIST_CNT; i++) { 1306 nexti = (i == (SIS_TX_LIST_CNT - 1)) ? 0 : i+1; 1307 ld->sis_tx_list[i].sis_nextdesc = 1308 &ld->sis_tx_list[nexti]; 1309 ld->sis_tx_list[i].sis_next = 1310 vtophys(&ld->sis_tx_list[nexti]); 1311 ld->sis_tx_list[i].sis_mbuf = NULL; 1312 ld->sis_tx_list[i].sis_ptr = 0; 1313 ld->sis_tx_list[i].sis_ctl = 0; 1314 } 1315 1316 cd->sis_tx_prod = cd->sis_tx_cons = cd->sis_tx_cnt = 0; 1317 1318 return(0); 1319 } 1320 1321 1322 /* 1323 * Initialize the RX descriptors and allocate mbufs for them. Note that 1324 * we arrange the descriptors in a closed ring, so that the last descriptor 1325 * points back to the first. 1326 */ 1327 static int sis_list_rx_init(sc) 1328 struct sis_softc *sc; 1329 { 1330 struct sis_list_data *ld; 1331 struct sis_ring_data *cd; 1332 int i, nexti; 1333 1334 ld = sc->sis_ldata; 1335 cd = &sc->sis_cdata; 1336 1337 for (i = 0; i < SIS_RX_LIST_CNT; i++) { 1338 if (sis_newbuf(sc, &ld->sis_rx_list[i], NULL) == ENOBUFS) 1339 return(ENOBUFS); 1340 nexti = (i == (SIS_RX_LIST_CNT - 1)) ? 0 : i+1; 1341 ld->sis_rx_list[i].sis_nextdesc = 1342 &ld->sis_rx_list[nexti]; 1343 ld->sis_rx_list[i].sis_next = 1344 vtophys(&ld->sis_rx_list[nexti]); 1345 } 1346 1347 cd->sis_rx_prod = 0; 1348 1349 return(0); 1350 } 1351 1352 /* 1353 * Initialize an RX descriptor and attach an MBUF cluster. 1354 */ 1355 static int sis_newbuf(sc, c, m) 1356 struct sis_softc *sc; 1357 struct sis_desc *c; 1358 struct mbuf *m; 1359 { 1360 1361 if (m == NULL) { 1362 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1363 if (m == NULL) 1364 return(ENOBUFS); 1365 } else { 1366 m->m_data = m->m_ext.ext_buf; 1367 } 1368 1369 c->sis_mbuf = m; 1370 c->sis_ptr = vtophys(mtod(m, caddr_t)); 1371 c->sis_ctl = SIS_RXLEN; 1372 1373 return(0); 1374 } 1375 1376 /* 1377 * A frame has been uploaded: pass the resulting mbuf chain up to 1378 * the higher level protocols. 1379 */ 1380 static void sis_rxeof(sc) 1381 struct sis_softc *sc; 1382 { 1383 struct mbuf *m; 1384 struct ifnet *ifp; 1385 struct sis_desc *cur_rx; 1386 int i, total_len = 0; 1387 u_int32_t rxstat; 1388 1389 ifp = &sc->arpcom.ac_if; 1390 i = sc->sis_cdata.sis_rx_prod; 1391 1392 while(SIS_OWNDESC(&sc->sis_ldata->sis_rx_list[i])) { 1393 1394 #ifdef DEVICE_POLLING 1395 if (ifp->if_ipending & IFF_POLLING) { 1396 if (sc->rxcycles <= 0) 1397 break; 1398 sc->rxcycles--; 1399 } 1400 #endif /* DEVICE_POLLING */ 1401 cur_rx = &sc->sis_ldata->sis_rx_list[i]; 1402 rxstat = cur_rx->sis_rxstat; 1403 m = cur_rx->sis_mbuf; 1404 cur_rx->sis_mbuf = NULL; 1405 total_len = SIS_RXBYTES(cur_rx); 1406 SIS_INC(i, SIS_RX_LIST_CNT); 1407 1408 /* 1409 * If an error occurs, update stats, clear the 1410 * status word and leave the mbuf cluster in place: 1411 * it should simply get re-used next time this descriptor 1412 * comes up in the ring. 1413 */ 1414 if (!(rxstat & SIS_CMDSTS_PKT_OK)) { 1415 ifp->if_ierrors++; 1416 if (rxstat & SIS_RXSTAT_COLL) 1417 ifp->if_collisions++; 1418 sis_newbuf(sc, cur_rx, m); 1419 continue; 1420 } 1421 1422 /* No errors; receive the packet. */ 1423 #ifdef __i386__ 1424 /* 1425 * On the x86 we do not have alignment problems, so try to 1426 * allocate a new buffer for the receive ring, and pass up 1427 * the one where the packet is already, saving the expensive 1428 * copy done in m_devget(). 1429 * If we are on an architecture with alignment problems, or 1430 * if the allocation fails, then use m_devget and leave the 1431 * existing buffer in the receive ring. 1432 */ 1433 if (sis_newbuf(sc, cur_rx, NULL) == 0) 1434 m->m_pkthdr.len = m->m_len = total_len; 1435 else 1436 #endif 1437 { 1438 struct mbuf *m0; 1439 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 1440 total_len + ETHER_ALIGN, 0, ifp, NULL); 1441 sis_newbuf(sc, cur_rx, m); 1442 if (m0 == NULL) { 1443 ifp->if_ierrors++; 1444 continue; 1445 } 1446 m_adj(m0, ETHER_ALIGN); 1447 m = m0; 1448 } 1449 1450 ifp->if_ipackets++; 1451 ether_input(ifp, NULL, m); 1452 } 1453 1454 sc->sis_cdata.sis_rx_prod = i; 1455 1456 return; 1457 } 1458 1459 void sis_rxeoc(sc) 1460 struct sis_softc *sc; 1461 { 1462 sis_rxeof(sc); 1463 /* sis_init(sc); */ 1464 return; 1465 } 1466 1467 /* 1468 * A frame was downloaded to the chip. It's safe for us to clean up 1469 * the list buffers. 1470 */ 1471 1472 static void sis_txeof(sc) 1473 struct sis_softc *sc; 1474 { 1475 struct sis_desc *cur_tx = NULL; 1476 struct ifnet *ifp; 1477 u_int32_t idx; 1478 1479 ifp = &sc->arpcom.ac_if; 1480 1481 /* 1482 * Go through our tx list and free mbufs for those 1483 * frames that have been transmitted. 1484 */ 1485 idx = sc->sis_cdata.sis_tx_cons; 1486 while (idx != sc->sis_cdata.sis_tx_prod) { 1487 cur_tx = &sc->sis_ldata->sis_tx_list[idx]; 1488 1489 if (SIS_OWNDESC(cur_tx)) 1490 break; 1491 1492 if (cur_tx->sis_ctl & SIS_CMDSTS_MORE) { 1493 sc->sis_cdata.sis_tx_cnt--; 1494 SIS_INC(idx, SIS_TX_LIST_CNT); 1495 continue; 1496 } 1497 1498 if (!(cur_tx->sis_ctl & SIS_CMDSTS_PKT_OK)) { 1499 ifp->if_oerrors++; 1500 if (cur_tx->sis_txstat & SIS_TXSTAT_EXCESSCOLLS) 1501 ifp->if_collisions++; 1502 if (cur_tx->sis_txstat & SIS_TXSTAT_OUTOFWINCOLL) 1503 ifp->if_collisions++; 1504 } 1505 1506 ifp->if_collisions += 1507 (cur_tx->sis_txstat & SIS_TXSTAT_COLLCNT) >> 16; 1508 1509 ifp->if_opackets++; 1510 if (cur_tx->sis_mbuf != NULL) { 1511 m_freem(cur_tx->sis_mbuf); 1512 cur_tx->sis_mbuf = NULL; 1513 } 1514 1515 sc->sis_cdata.sis_tx_cnt--; 1516 SIS_INC(idx, SIS_TX_LIST_CNT); 1517 ifp->if_timer = 0; 1518 } 1519 1520 if (idx != sc->sis_cdata.sis_tx_cons) { 1521 sc->sis_cdata.sis_tx_cons = idx; 1522 ifp->if_flags &= ~IFF_OACTIVE; 1523 } 1524 ifp->if_timer = (sc->sis_cdata.sis_tx_cnt == 0) ? 0 : 5; 1525 return; 1526 } 1527 1528 static void sis_tick(xsc) 1529 void *xsc; 1530 { 1531 struct sis_softc *sc; 1532 struct mii_data *mii; 1533 struct ifnet *ifp; 1534 int s; 1535 1536 s = splimp(); 1537 1538 sc = xsc; 1539 ifp = &sc->arpcom.ac_if; 1540 1541 mii = device_get_softc(sc->sis_miibus); 1542 mii_tick(mii); 1543 1544 if (!sc->sis_link) { 1545 mii_pollstat(mii); 1546 if (mii->mii_media_status & IFM_ACTIVE && 1547 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 1548 sc->sis_link++; 1549 if (ifp->if_snd.ifq_head != NULL) 1550 sis_start(ifp); 1551 } 1552 1553 sc->sis_stat_ch = timeout(sis_tick, sc, hz); 1554 1555 splx(s); 1556 1557 return; 1558 } 1559 1560 #ifdef DEVICE_POLLING 1561 static poll_handler_t sis_poll; 1562 1563 static void 1564 sis_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1565 { 1566 struct sis_softc *sc = ifp->if_softc; 1567 1568 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 1569 CSR_WRITE_4(sc, SIS_IER, 1); 1570 return; 1571 } 1572 1573 /* 1574 * On the sis, reading the status register also clears it. 1575 * So before returning to intr mode we must make sure that all 1576 * possible pending sources of interrupts have been served. 1577 * In practice this means run to completion the *eof routines, 1578 * and then call the interrupt routine 1579 */ 1580 sc->rxcycles = count; 1581 sis_rxeof(sc); 1582 sis_txeof(sc); 1583 if (ifp->if_snd.ifq_head != NULL) 1584 sis_start(ifp); 1585 1586 if (sc->rxcycles > 0 || cmd == POLL_AND_CHECK_STATUS) { 1587 u_int32_t status; 1588 1589 /* Reading the ISR register clears all interrupts. */ 1590 status = CSR_READ_4(sc, SIS_ISR); 1591 1592 if (status & (SIS_ISR_RX_ERR|SIS_ISR_RX_OFLOW)) 1593 sis_rxeoc(sc); 1594 1595 if (status & (SIS_ISR_RX_IDLE)) 1596 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE); 1597 1598 if (status & SIS_ISR_SYSERR) { 1599 sis_reset(sc); 1600 sis_init(sc); 1601 } 1602 } 1603 } 1604 #endif /* DEVICE_POLLING */ 1605 1606 static void sis_intr(arg) 1607 void *arg; 1608 { 1609 struct sis_softc *sc; 1610 struct ifnet *ifp; 1611 u_int32_t status; 1612 1613 sc = arg; 1614 ifp = &sc->arpcom.ac_if; 1615 1616 #ifdef DEVICE_POLLING 1617 if (ifp->if_ipending & IFF_POLLING) 1618 return; 1619 if (ether_poll_register(sis_poll, ifp)) { /* ok, disable interrupts */ 1620 CSR_WRITE_4(sc, SIS_IER, 0); 1621 sis_poll(ifp, 0, 1); 1622 return; 1623 } 1624 #endif /* DEVICE_POLLING */ 1625 1626 /* Supress unwanted interrupts */ 1627 if (!(ifp->if_flags & IFF_UP)) { 1628 sis_stop(sc); 1629 return; 1630 } 1631 1632 /* Disable interrupts. */ 1633 CSR_WRITE_4(sc, SIS_IER, 0); 1634 1635 for (;;) { 1636 /* Reading the ISR register clears all interrupts. */ 1637 status = CSR_READ_4(sc, SIS_ISR); 1638 1639 if ((status & SIS_INTRS) == 0) 1640 break; 1641 1642 if (status & 1643 (SIS_ISR_TX_DESC_OK|SIS_ISR_TX_ERR| 1644 SIS_ISR_TX_OK|SIS_ISR_TX_IDLE) ) 1645 sis_txeof(sc); 1646 1647 if (status & (SIS_ISR_RX_DESC_OK|SIS_ISR_RX_OK|SIS_ISR_RX_IDLE)) 1648 sis_rxeof(sc); 1649 1650 if (status & (SIS_ISR_RX_ERR|SIS_ISR_RX_OFLOW)) 1651 sis_rxeoc(sc); 1652 1653 if (status & (SIS_ISR_RX_IDLE)) 1654 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE); 1655 1656 if (status & SIS_ISR_SYSERR) { 1657 sis_reset(sc); 1658 sis_init(sc); 1659 } 1660 } 1661 1662 /* Re-enable interrupts. */ 1663 CSR_WRITE_4(sc, SIS_IER, 1); 1664 1665 if (ifp->if_snd.ifq_head != NULL) 1666 sis_start(ifp); 1667 1668 return; 1669 } 1670 1671 /* 1672 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1673 * pointers to the fragment pointers. 1674 */ 1675 static int sis_encap(sc, m_head, txidx) 1676 struct sis_softc *sc; 1677 struct mbuf *m_head; 1678 u_int32_t *txidx; 1679 { 1680 struct sis_desc *f = NULL; 1681 struct mbuf *m; 1682 int frag, cur, cnt = 0; 1683 1684 /* 1685 * Start packing the mbufs in this chain into 1686 * the fragment pointers. Stop when we run out 1687 * of fragments or hit the end of the mbuf chain. 1688 */ 1689 m = m_head; 1690 cur = frag = *txidx; 1691 1692 for (m = m_head; m != NULL; m = m->m_next) { 1693 if (m->m_len != 0) { 1694 if ((SIS_TX_LIST_CNT - 1695 (sc->sis_cdata.sis_tx_cnt + cnt)) < 2) 1696 return(ENOBUFS); 1697 f = &sc->sis_ldata->sis_tx_list[frag]; 1698 f->sis_ctl = SIS_CMDSTS_MORE | m->m_len; 1699 f->sis_ptr = vtophys(mtod(m, vm_offset_t)); 1700 if (cnt != 0) 1701 f->sis_ctl |= SIS_CMDSTS_OWN; 1702 cur = frag; 1703 SIS_INC(frag, SIS_TX_LIST_CNT); 1704 cnt++; 1705 } 1706 } 1707 1708 if (m != NULL) 1709 return(ENOBUFS); 1710 1711 sc->sis_ldata->sis_tx_list[cur].sis_mbuf = m_head; 1712 sc->sis_ldata->sis_tx_list[cur].sis_ctl &= ~SIS_CMDSTS_MORE; 1713 sc->sis_ldata->sis_tx_list[*txidx].sis_ctl |= SIS_CMDSTS_OWN; 1714 sc->sis_cdata.sis_tx_cnt += cnt; 1715 *txidx = frag; 1716 1717 return(0); 1718 } 1719 1720 /* 1721 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1722 * to the mbuf data regions directly in the transmit lists. We also save a 1723 * copy of the pointers since the transmit list fragment pointers are 1724 * physical addresses. 1725 */ 1726 1727 static void sis_start(ifp) 1728 struct ifnet *ifp; 1729 { 1730 struct sis_softc *sc; 1731 struct mbuf *m_head = NULL; 1732 u_int32_t idx; 1733 1734 sc = ifp->if_softc; 1735 1736 if (!sc->sis_link) 1737 return; 1738 1739 idx = sc->sis_cdata.sis_tx_prod; 1740 1741 if (ifp->if_flags & IFF_OACTIVE) 1742 return; 1743 1744 while(sc->sis_ldata->sis_tx_list[idx].sis_mbuf == NULL) { 1745 IF_DEQUEUE(&ifp->if_snd, m_head); 1746 if (m_head == NULL) 1747 break; 1748 1749 if (sis_encap(sc, m_head, &idx)) { 1750 IF_PREPEND(&ifp->if_snd, m_head); 1751 ifp->if_flags |= IFF_OACTIVE; 1752 break; 1753 } 1754 1755 /* 1756 * If there's a BPF listener, bounce a copy of this frame 1757 * to him. 1758 */ 1759 if (ifp->if_bpf) 1760 bpf_mtap(ifp, m_head); 1761 1762 } 1763 1764 /* Transmit */ 1765 sc->sis_cdata.sis_tx_prod = idx; 1766 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_ENABLE); 1767 1768 /* 1769 * Set a timeout in case the chip goes out to lunch. 1770 */ 1771 ifp->if_timer = 5; 1772 1773 return; 1774 } 1775 1776 static void sis_init(xsc) 1777 void *xsc; 1778 { 1779 struct sis_softc *sc = xsc; 1780 struct ifnet *ifp = &sc->arpcom.ac_if; 1781 struct mii_data *mii; 1782 int s; 1783 1784 s = splimp(); 1785 1786 /* 1787 * Cancel pending I/O and free all RX/TX buffers. 1788 */ 1789 sis_stop(sc); 1790 1791 mii = device_get_softc(sc->sis_miibus); 1792 1793 /* Set MAC address */ 1794 if (sc->sis_type == SIS_TYPE_83815) { 1795 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR0); 1796 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1797 ((u_int16_t *)sc->arpcom.ac_enaddr)[0]); 1798 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR1); 1799 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1800 ((u_int16_t *)sc->arpcom.ac_enaddr)[1]); 1801 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR2); 1802 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1803 ((u_int16_t *)sc->arpcom.ac_enaddr)[2]); 1804 } else { 1805 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR0); 1806 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1807 ((u_int16_t *)sc->arpcom.ac_enaddr)[0]); 1808 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR1); 1809 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1810 ((u_int16_t *)sc->arpcom.ac_enaddr)[1]); 1811 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR2); 1812 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1813 ((u_int16_t *)sc->arpcom.ac_enaddr)[2]); 1814 } 1815 1816 /* Init circular RX list. */ 1817 if (sis_list_rx_init(sc) == ENOBUFS) { 1818 printf("sis%d: initialization failed: no " 1819 "memory for rx buffers\n", sc->sis_unit); 1820 sis_stop(sc); 1821 (void)splx(s); 1822 return; 1823 } 1824 1825 /* 1826 * Init tx descriptors. 1827 */ 1828 sis_list_tx_init(sc); 1829 1830 /* 1831 * For the NatSemi chip, we have to explicitly enable the 1832 * reception of ARP frames, as well as turn on the 'perfect 1833 * match' filter where we store the station address, otherwise 1834 * we won't receive unicasts meant for this host. 1835 */ 1836 if (sc->sis_type == SIS_TYPE_83815) { 1837 SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_ARP); 1838 SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_PERFECT); 1839 } 1840 1841 /* If we want promiscuous mode, set the allframes bit. */ 1842 if (ifp->if_flags & IFF_PROMISC) { 1843 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLPHYS); 1844 } else { 1845 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLPHYS); 1846 } 1847 1848 /* 1849 * Set the capture broadcast bit to capture broadcast frames. 1850 */ 1851 if (ifp->if_flags & IFF_BROADCAST) { 1852 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_BROAD); 1853 } else { 1854 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_BROAD); 1855 } 1856 1857 /* 1858 * Load the multicast filter. 1859 */ 1860 if (sc->sis_type == SIS_TYPE_83815) 1861 sis_setmulti_ns(sc); 1862 else 1863 sis_setmulti_sis(sc); 1864 1865 /* Turn the receive filter on */ 1866 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ENABLE); 1867 1868 /* 1869 * Load the address of the RX and TX lists. 1870 */ 1871 CSR_WRITE_4(sc, SIS_RX_LISTPTR, 1872 vtophys(&sc->sis_ldata->sis_rx_list[0])); 1873 CSR_WRITE_4(sc, SIS_TX_LISTPTR, 1874 vtophys(&sc->sis_ldata->sis_tx_list[0])); 1875 1876 /* SIS_CFG_EDB_MASTER_EN indicates the EDB bus is used instead of 1877 * the PCI bus. When this bit is set, the Max DMA Burst Size 1878 * for TX/RX DMA should be no larger than 16 double words. 1879 */ 1880 if (CSR_READ_4(sc, SIS_CFG) & SIS_CFG_EDB_MASTER_EN) { 1881 CSR_WRITE_4(sc, SIS_RX_CFG, SIS_RXCFG64); 1882 } else { 1883 CSR_WRITE_4(sc, SIS_RX_CFG, SIS_RXCFG256); 1884 } 1885 1886 /* Accept Long Packets for VLAN support */ 1887 SIS_SETBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_JABBER); 1888 1889 /* Set TX configuration */ 1890 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T) { 1891 CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_10); 1892 } else { 1893 CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_100); 1894 } 1895 1896 /* Set full/half duplex mode. */ 1897 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 1898 SIS_SETBIT(sc, SIS_TX_CFG, 1899 (SIS_TXCFG_IGN_HBEAT|SIS_TXCFG_IGN_CARR)); 1900 SIS_SETBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS); 1901 } else { 1902 SIS_CLRBIT(sc, SIS_TX_CFG, 1903 (SIS_TXCFG_IGN_HBEAT|SIS_TXCFG_IGN_CARR)); 1904 SIS_CLRBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS); 1905 } 1906 1907 /* 1908 * Enable interrupts. 1909 */ 1910 CSR_WRITE_4(sc, SIS_IMR, SIS_INTRS); 1911 #ifdef DEVICE_POLLING 1912 /* 1913 * ... only enable interrupts if we are not polling, make sure 1914 * they are off otherwise. 1915 */ 1916 if (ifp->if_ipending & IFF_POLLING) 1917 CSR_WRITE_4(sc, SIS_IER, 0); 1918 else 1919 #endif /* DEVICE_POLLING */ 1920 CSR_WRITE_4(sc, SIS_IER, 1); 1921 1922 /* Enable receiver and transmitter. */ 1923 SIS_CLRBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE|SIS_CSR_RX_DISABLE); 1924 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE); 1925 1926 #ifdef notdef 1927 mii_mediachg(mii); 1928 #endif 1929 1930 /* 1931 * Page 75 of the DP83815 manual recommends the 1932 * following register settings "for optimum 1933 * performance." Note however that at least three 1934 * of the registers are listed as "reserved" in 1935 * the register map, so who knows what they do. 1936 */ 1937 if (sc->sis_type == SIS_TYPE_83815) { 1938 CSR_WRITE_4(sc, NS_PHY_PAGE, 0x0001); 1939 CSR_WRITE_4(sc, NS_PHY_CR, 0x189C); 1940 CSR_WRITE_4(sc, NS_PHY_TDATA, 0x0000); 1941 CSR_WRITE_4(sc, NS_PHY_DSPCFG, 0x5040); 1942 CSR_WRITE_4(sc, NS_PHY_SDCFG, 0x008C); 1943 } 1944 1945 ifp->if_flags |= IFF_RUNNING; 1946 ifp->if_flags &= ~IFF_OACTIVE; 1947 1948 (void)splx(s); 1949 1950 sc->sis_stat_ch = timeout(sis_tick, sc, hz); 1951 1952 return; 1953 } 1954 1955 /* 1956 * Set media options. 1957 */ 1958 static int sis_ifmedia_upd(ifp) 1959 struct ifnet *ifp; 1960 { 1961 struct sis_softc *sc; 1962 struct mii_data *mii; 1963 1964 sc = ifp->if_softc; 1965 1966 mii = device_get_softc(sc->sis_miibus); 1967 sc->sis_link = 0; 1968 if (mii->mii_instance) { 1969 struct mii_softc *miisc; 1970 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 1971 miisc = LIST_NEXT(miisc, mii_list)) 1972 mii_phy_reset(miisc); 1973 } 1974 mii_mediachg(mii); 1975 1976 return(0); 1977 } 1978 1979 /* 1980 * Report current media status. 1981 */ 1982 static void sis_ifmedia_sts(ifp, ifmr) 1983 struct ifnet *ifp; 1984 struct ifmediareq *ifmr; 1985 { 1986 struct sis_softc *sc; 1987 struct mii_data *mii; 1988 1989 sc = ifp->if_softc; 1990 1991 mii = device_get_softc(sc->sis_miibus); 1992 mii_pollstat(mii); 1993 ifmr->ifm_active = mii->mii_media_active; 1994 ifmr->ifm_status = mii->mii_media_status; 1995 1996 return; 1997 } 1998 1999 static int sis_ioctl(ifp, command, data) 2000 struct ifnet *ifp; 2001 u_long command; 2002 caddr_t data; 2003 { 2004 struct sis_softc *sc = ifp->if_softc; 2005 struct ifreq *ifr = (struct ifreq *) data; 2006 struct mii_data *mii; 2007 int s, error = 0; 2008 2009 s = splimp(); 2010 2011 switch(command) { 2012 case SIOCSIFADDR: 2013 case SIOCGIFADDR: 2014 case SIOCSIFMTU: 2015 error = ether_ioctl(ifp, command, data); 2016 break; 2017 case SIOCSIFFLAGS: 2018 if (ifp->if_flags & IFF_UP) { 2019 sis_init(sc); 2020 } else { 2021 if (ifp->if_flags & IFF_RUNNING) 2022 sis_stop(sc); 2023 } 2024 error = 0; 2025 break; 2026 case SIOCADDMULTI: 2027 case SIOCDELMULTI: 2028 if (sc->sis_type == SIS_TYPE_83815) 2029 sis_setmulti_ns(sc); 2030 else 2031 sis_setmulti_sis(sc); 2032 error = 0; 2033 break; 2034 case SIOCGIFMEDIA: 2035 case SIOCSIFMEDIA: 2036 mii = device_get_softc(sc->sis_miibus); 2037 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 2038 break; 2039 default: 2040 error = EINVAL; 2041 break; 2042 } 2043 2044 (void)splx(s); 2045 2046 return(error); 2047 } 2048 2049 static void sis_watchdog(ifp) 2050 struct ifnet *ifp; 2051 { 2052 struct sis_softc *sc; 2053 2054 sc = ifp->if_softc; 2055 2056 ifp->if_oerrors++; 2057 printf("sis%d: watchdog timeout\n", sc->sis_unit); 2058 2059 sis_stop(sc); 2060 sis_reset(sc); 2061 sis_init(sc); 2062 2063 if (ifp->if_snd.ifq_head != NULL) 2064 sis_start(ifp); 2065 2066 return; 2067 } 2068 2069 /* 2070 * Stop the adapter and free any mbufs allocated to the 2071 * RX and TX lists. 2072 */ 2073 static void sis_stop(sc) 2074 struct sis_softc *sc; 2075 { 2076 int i; 2077 struct ifnet *ifp; 2078 2079 ifp = &sc->arpcom.ac_if; 2080 ifp->if_timer = 0; 2081 2082 untimeout(sis_tick, sc, sc->sis_stat_ch); 2083 2084 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2085 #ifdef DEVICE_POLLING 2086 ether_poll_deregister(ifp); 2087 #endif 2088 CSR_WRITE_4(sc, SIS_IER, 0); 2089 CSR_WRITE_4(sc, SIS_IMR, 0); 2090 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE|SIS_CSR_RX_DISABLE); 2091 DELAY(1000); 2092 CSR_WRITE_4(sc, SIS_TX_LISTPTR, 0); 2093 CSR_WRITE_4(sc, SIS_RX_LISTPTR, 0); 2094 2095 sc->sis_link = 0; 2096 2097 /* 2098 * Free data in the RX lists. 2099 */ 2100 for (i = 0; i < SIS_RX_LIST_CNT; i++) { 2101 if (sc->sis_ldata->sis_rx_list[i].sis_mbuf != NULL) { 2102 m_freem(sc->sis_ldata->sis_rx_list[i].sis_mbuf); 2103 sc->sis_ldata->sis_rx_list[i].sis_mbuf = NULL; 2104 } 2105 } 2106 bzero((char *)&sc->sis_ldata->sis_rx_list, 2107 sizeof(sc->sis_ldata->sis_rx_list)); 2108 2109 /* 2110 * Free the TX list buffers. 2111 */ 2112 for (i = 0; i < SIS_TX_LIST_CNT; i++) { 2113 if (sc->sis_ldata->sis_tx_list[i].sis_mbuf != NULL) { 2114 m_freem(sc->sis_ldata->sis_tx_list[i].sis_mbuf); 2115 sc->sis_ldata->sis_tx_list[i].sis_mbuf = NULL; 2116 } 2117 } 2118 2119 bzero((char *)&sc->sis_ldata->sis_tx_list, 2120 sizeof(sc->sis_ldata->sis_tx_list)); 2121 2122 return; 2123 } 2124 2125 /* 2126 * Stop all chip I/O so that the kernel's probe routines don't 2127 * get confused by errant DMAs when rebooting. 2128 */ 2129 static void sis_shutdown(dev) 2130 device_t dev; 2131 { 2132 struct sis_softc *sc; 2133 2134 sc = device_get_softc(dev); 2135 2136 sis_reset(sc); 2137 sis_stop(sc); 2138 2139 return; 2140 } 2141