1 /* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: src/sys/pci/if_sis.c,v 1.13.4.24 2003/03/05 18:42:33 njl Exp $ 33 * $DragonFly: src/sys/dev/netif/sis/if_sis.c,v 1.31 2005/12/31 14:08:00 sephe Exp $ 34 */ 35 36 /* 37 * SiS 900/SiS 7016 fast ethernet PCI NIC driver. Datasheets are 38 * available from http://www.sis.com.tw. 39 * 40 * This driver also supports the NatSemi DP83815. Datasheets are 41 * available from http://www.national.com. 42 * 43 * Written by Bill Paul <wpaul@ee.columbia.edu> 44 * Electrical Engineering Department 45 * Columbia University, New York City 46 */ 47 48 /* 49 * The SiS 900 is a fairly simple chip. It uses bus master DMA with 50 * simple TX and RX descriptors of 3 longwords in size. The receiver 51 * has a single perfect filter entry for the station address and a 52 * 128-bit multicast hash table. The SiS 900 has a built-in MII-based 53 * transceiver while the 7016 requires an external transceiver chip. 54 * Both chips offer the standard bit-bang MII interface as well as 55 * an enchanced PHY interface which simplifies accessing MII registers. 56 * 57 * The only downside to this chipset is that RX descriptors must be 58 * longword aligned. 59 */ 60 61 #include "opt_polling.h" 62 63 #include <sys/param.h> 64 #include <sys/systm.h> 65 #include <sys/sockio.h> 66 #include <sys/mbuf.h> 67 #include <sys/malloc.h> 68 #include <sys/kernel.h> 69 #include <sys/socket.h> 70 #include <sys/sysctl.h> 71 #include <sys/serialize.h> 72 #include <sys/thread2.h> 73 74 #include <net/if.h> 75 #include <net/ifq_var.h> 76 #include <net/if_arp.h> 77 #include <net/ethernet.h> 78 #include <net/if_dl.h> 79 #include <net/if_media.h> 80 #include <net/if_types.h> 81 #include <net/vlan/if_vlan_var.h> 82 83 #include <net/bpf.h> 84 85 #include <machine/bus_pio.h> 86 #include <machine/bus_memio.h> 87 #include <machine/bus.h> 88 #include <machine/resource.h> 89 #include <sys/bus.h> 90 #include <sys/rman.h> 91 92 #include <dev/netif/mii_layer/mii.h> 93 #include <dev/netif/mii_layer/miivar.h> 94 95 #include <bus/pci/pcireg.h> 96 #include <bus/pci/pcivar.h> 97 98 #define SIS_USEIOSPACE 99 100 #include "if_sisreg.h" 101 102 /* "controller miibus0" required. See GENERIC if you get errors here. */ 103 #include "miibus_if.h" 104 105 /* 106 * Various supported device vendors/types and their names. 107 */ 108 static struct sis_type sis_devs[] = { 109 { SIS_VENDORID, SIS_DEVICEID_900, "SiS 900 10/100BaseTX" }, 110 { SIS_VENDORID, SIS_DEVICEID_7016, "SiS 7016 10/100BaseTX" }, 111 { NS_VENDORID, NS_DEVICEID_DP83815, "NatSemi DP8381[56] 10/100BaseTX" }, 112 { 0, 0, NULL } 113 }; 114 115 static int sis_probe(device_t); 116 static int sis_attach(device_t); 117 static int sis_detach(device_t); 118 119 static int sis_newbuf(struct sis_softc *, struct sis_desc *, 120 struct mbuf *); 121 static int sis_encap(struct sis_softc *, struct mbuf *, uint32_t *); 122 static void sis_rxeof(struct sis_softc *); 123 static void sis_rxeoc(struct sis_softc *); 124 static void sis_txeof(struct sis_softc *); 125 static void sis_intr(void *); 126 static void sis_tick(void *); 127 static void sis_start(struct ifnet *); 128 static int sis_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *); 129 static void sis_init(void *); 130 static void sis_stop(struct sis_softc *); 131 static void sis_watchdog(struct ifnet *); 132 static void sis_shutdown(device_t); 133 static int sis_ifmedia_upd(struct ifnet *); 134 static void sis_ifmedia_sts(struct ifnet *, struct ifmediareq *); 135 136 static uint16_t sis_reverse(uint16_t); 137 static void sis_delay(struct sis_softc *); 138 static void sis_eeprom_idle(struct sis_softc *); 139 static void sis_eeprom_putbyte(struct sis_softc *, int); 140 static void sis_eeprom_getword(struct sis_softc *, int, uint16_t *); 141 static void sis_read_eeprom(struct sis_softc *, caddr_t, int, int, int); 142 #ifdef __i386__ 143 static void sis_read_cmos(struct sis_softc *, device_t, caddr_t, int, int); 144 static void sis_read_mac(struct sis_softc *, device_t, caddr_t); 145 static device_t sis_find_bridge(device_t); 146 #endif 147 148 static void sis_mii_sync(struct sis_softc *); 149 static void sis_mii_send(struct sis_softc *, uint32_t, int); 150 static int sis_mii_readreg(struct sis_softc *, struct sis_mii_frame *); 151 static int sis_mii_writereg(struct sis_softc *, struct sis_mii_frame *); 152 static int sis_miibus_readreg(device_t, int, int); 153 static int sis_miibus_writereg(device_t, int, int, int); 154 static void sis_miibus_statchg(device_t); 155 156 static void sis_setmulti_sis(struct sis_softc *); 157 static void sis_setmulti_ns(struct sis_softc *); 158 static uint32_t sis_mchash(struct sis_softc *, const uint8_t *); 159 static void sis_reset(struct sis_softc *); 160 static int sis_list_rx_init(struct sis_softc *); 161 static int sis_list_tx_init(struct sis_softc *); 162 163 static void sis_dma_map_desc_ptr(void *, bus_dma_segment_t *, int, int); 164 static void sis_dma_map_desc_next(void *, bus_dma_segment_t *, int, int); 165 static void sis_dma_map_ring(void *, bus_dma_segment_t *, int, int); 166 #ifdef DEVICE_POLLING 167 static poll_handler_t sis_poll; 168 #endif 169 #ifdef SIS_USEIOSPACE 170 #define SIS_RES SYS_RES_IOPORT 171 #define SIS_RID SIS_PCI_LOIO 172 #else 173 #define SIS_RES SYS_RES_MEMORY 174 #define SIS_RID SIS_PCI_LOMEM 175 #endif 176 177 static device_method_t sis_methods[] = { 178 /* Device interface */ 179 DEVMETHOD(device_probe, sis_probe), 180 DEVMETHOD(device_attach, sis_attach), 181 DEVMETHOD(device_detach, sis_detach), 182 DEVMETHOD(device_shutdown, sis_shutdown), 183 184 /* bus interface */ 185 DEVMETHOD(bus_print_child, bus_generic_print_child), 186 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 187 188 /* MII interface */ 189 DEVMETHOD(miibus_readreg, sis_miibus_readreg), 190 DEVMETHOD(miibus_writereg, sis_miibus_writereg), 191 DEVMETHOD(miibus_statchg, sis_miibus_statchg), 192 193 { 0, 0 } 194 }; 195 196 static driver_t sis_driver = { 197 "sis", 198 sis_methods, 199 sizeof(struct sis_softc) 200 }; 201 202 static devclass_t sis_devclass; 203 204 DECLARE_DUMMY_MODULE(if_sis); 205 DRIVER_MODULE(if_sis, pci, sis_driver, sis_devclass, 0, 0); 206 DRIVER_MODULE(miibus, sis, miibus_driver, miibus_devclass, 0, 0); 207 208 #define SIS_SETBIT(sc, reg, x) \ 209 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x)) 210 211 #define SIS_CLRBIT(sc, reg, x) \ 212 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x)) 213 214 #define SIO_SET(x) \ 215 CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) | x) 216 217 #define SIO_CLR(x) \ 218 CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) & ~x) 219 220 static void 221 sis_dma_map_desc_next(void *arg, bus_dma_segment_t *segs, int nseg, int error) 222 { 223 struct sis_desc *r; 224 225 r = arg; 226 r->sis_next = segs->ds_addr; 227 } 228 229 static void 230 sis_dma_map_desc_ptr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 231 { 232 struct sis_desc *r; 233 234 r = arg; 235 r->sis_ptr = segs->ds_addr; 236 } 237 238 static void 239 sis_dma_map_ring(void *arg, bus_dma_segment_t *segs, int nseg, int error) 240 { 241 uint32_t *p; 242 243 p = arg; 244 *p = segs->ds_addr; 245 } 246 247 /* 248 * Routine to reverse the bits in a word. Stolen almost 249 * verbatim from /usr/games/fortune. 250 */ 251 static uint16_t 252 sis_reverse(uint16_t n) 253 { 254 n = ((n >> 1) & 0x5555) | ((n << 1) & 0xaaaa); 255 n = ((n >> 2) & 0x3333) | ((n << 2) & 0xcccc); 256 n = ((n >> 4) & 0x0f0f) | ((n << 4) & 0xf0f0); 257 n = ((n >> 8) & 0x00ff) | ((n << 8) & 0xff00); 258 259 return(n); 260 } 261 262 static void 263 sis_delay(struct sis_softc *sc) 264 { 265 int idx; 266 267 for (idx = (300 / 33) + 1; idx > 0; idx--) 268 CSR_READ_4(sc, SIS_CSR); 269 } 270 271 static void 272 sis_eeprom_idle(struct sis_softc *sc) 273 { 274 int i; 275 276 SIO_SET(SIS_EECTL_CSEL); 277 sis_delay(sc); 278 SIO_SET(SIS_EECTL_CLK); 279 sis_delay(sc); 280 281 for (i = 0; i < 25; i++) { 282 SIO_CLR(SIS_EECTL_CLK); 283 sis_delay(sc); 284 SIO_SET(SIS_EECTL_CLK); 285 sis_delay(sc); 286 } 287 288 SIO_CLR(SIS_EECTL_CLK); 289 sis_delay(sc); 290 SIO_CLR(SIS_EECTL_CSEL); 291 sis_delay(sc); 292 CSR_WRITE_4(sc, SIS_EECTL, 0x00000000); 293 } 294 295 /* 296 * Send a read command and address to the EEPROM, check for ACK. 297 */ 298 static void 299 sis_eeprom_putbyte(struct sis_softc *sc, int addr) 300 { 301 int d, i; 302 303 d = addr | SIS_EECMD_READ; 304 305 /* 306 * Feed in each bit and stobe the clock. 307 */ 308 for (i = 0x400; i; i >>= 1) { 309 if (d & i) 310 SIO_SET(SIS_EECTL_DIN); 311 else 312 SIO_CLR(SIS_EECTL_DIN); 313 sis_delay(sc); 314 SIO_SET(SIS_EECTL_CLK); 315 sis_delay(sc); 316 SIO_CLR(SIS_EECTL_CLK); 317 sis_delay(sc); 318 } 319 } 320 321 /* 322 * Read a word of data stored in the EEPROM at address 'addr.' 323 */ 324 static void 325 sis_eeprom_getword(struct sis_softc *sc, int addr, uint16_t *dest) 326 { 327 int i; 328 uint16_t word = 0; 329 330 /* Force EEPROM to idle state. */ 331 sis_eeprom_idle(sc); 332 333 /* Enter EEPROM access mode. */ 334 sis_delay(sc); 335 SIO_CLR(SIS_EECTL_CLK); 336 sis_delay(sc); 337 SIO_SET(SIS_EECTL_CSEL); 338 sis_delay(sc); 339 340 /* 341 * Send address of word we want to read. 342 */ 343 sis_eeprom_putbyte(sc, addr); 344 345 /* 346 * Start reading bits from EEPROM. 347 */ 348 for (i = 0x8000; i; i >>= 1) { 349 SIO_SET(SIS_EECTL_CLK); 350 sis_delay(sc); 351 if (CSR_READ_4(sc, SIS_EECTL) & SIS_EECTL_DOUT) 352 word |= i; 353 sis_delay(sc); 354 SIO_CLR(SIS_EECTL_CLK); 355 sis_delay(sc); 356 } 357 358 /* Turn off EEPROM access mode. */ 359 sis_eeprom_idle(sc); 360 361 *dest = word; 362 } 363 364 /* 365 * Read a sequence of words from the EEPROM. 366 */ 367 static void 368 sis_read_eeprom(struct sis_softc *sc, caddr_t dest, int off, int cnt, int swap) 369 { 370 int i; 371 uint16_t word = 0, *ptr; 372 373 for (i = 0; i < cnt; i++) { 374 sis_eeprom_getword(sc, off + i, &word); 375 ptr = (uint16_t *)(dest + (i * 2)); 376 if (swap) 377 *ptr = ntohs(word); 378 else 379 *ptr = word; 380 } 381 } 382 383 #ifdef __i386__ 384 static device_t 385 sis_find_bridge(device_t dev) 386 { 387 devclass_t pci_devclass; 388 device_t *pci_devices; 389 int pci_count = 0; 390 device_t *pci_children; 391 int pci_childcount = 0; 392 device_t *busp, *childp; 393 device_t child = NULL; 394 int i, j; 395 396 if ((pci_devclass = devclass_find("pci")) == NULL) 397 return(NULL); 398 399 devclass_get_devices(pci_devclass, &pci_devices, &pci_count); 400 401 for (i = 0, busp = pci_devices; i < pci_count; i++, busp++) { 402 pci_childcount = 0; 403 device_get_children(*busp, &pci_children, &pci_childcount); 404 for (j = 0, childp = pci_children; j < pci_childcount; 405 j++, childp++) { 406 if (pci_get_vendor(*childp) == SIS_VENDORID && 407 pci_get_device(*childp) == 0x0008) { 408 child = *childp; 409 goto done; 410 } 411 } 412 } 413 414 done: 415 free(pci_devices, M_TEMP); 416 free(pci_children, M_TEMP); 417 return(child); 418 } 419 420 static void 421 sis_read_cmos(struct sis_softc *sc, device_t dev, caddr_t dest, int off, 422 int cnt) 423 { 424 device_t bridge; 425 uint8_t reg; 426 int i; 427 bus_space_tag_t btag; 428 429 bridge = sis_find_bridge(dev); 430 if (bridge == NULL) 431 return; 432 reg = pci_read_config(bridge, 0x48, 1); 433 pci_write_config(bridge, 0x48, reg|0x40, 1); 434 435 /* XXX */ 436 btag = I386_BUS_SPACE_IO; 437 438 for (i = 0; i < cnt; i++) { 439 bus_space_write_1(btag, 0x0, 0x70, i + off); 440 *(dest + i) = bus_space_read_1(btag, 0x0, 0x71); 441 } 442 443 pci_write_config(bridge, 0x48, reg & ~0x40, 1); 444 } 445 446 static void 447 sis_read_mac(struct sis_softc *sc, device_t dev, caddr_t dest) 448 { 449 uint32_t filtsave, csrsave; 450 451 filtsave = CSR_READ_4(sc, SIS_RXFILT_CTL); 452 csrsave = CSR_READ_4(sc, SIS_CSR); 453 454 CSR_WRITE_4(sc, SIS_CSR, SIS_CSR_RELOAD | filtsave); 455 CSR_WRITE_4(sc, SIS_CSR, 0); 456 457 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave & ~SIS_RXFILTCTL_ENABLE); 458 459 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR0); 460 ((uint16_t *)dest)[0] = CSR_READ_2(sc, SIS_RXFILT_DATA); 461 CSR_WRITE_4(sc, SIS_RXFILT_CTL,SIS_FILTADDR_PAR1); 462 ((uint16_t *)dest)[1] = CSR_READ_2(sc, SIS_RXFILT_DATA); 463 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR2); 464 ((uint16_t *)dest)[2] = CSR_READ_2(sc, SIS_RXFILT_DATA); 465 466 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave); 467 CSR_WRITE_4(sc, SIS_CSR, csrsave); 468 } 469 #endif 470 471 /* 472 * Sync the PHYs by setting data bit and strobing the clock 32 times. 473 */ 474 static void 475 sis_mii_sync(struct sis_softc *sc) 476 { 477 int i; 478 479 SIO_SET(SIS_MII_DIR|SIS_MII_DATA); 480 481 for (i = 0; i < 32; i++) { 482 SIO_SET(SIS_MII_CLK); 483 DELAY(1); 484 SIO_CLR(SIS_MII_CLK); 485 DELAY(1); 486 } 487 } 488 489 /* 490 * Clock a series of bits through the MII. 491 */ 492 static void 493 sis_mii_send(struct sis_softc *sc, uint32_t bits, int cnt) 494 { 495 int i; 496 497 SIO_CLR(SIS_MII_CLK); 498 499 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 500 if (bits & i) 501 SIO_SET(SIS_MII_DATA); 502 else 503 SIO_CLR(SIS_MII_DATA); 504 DELAY(1); 505 SIO_CLR(SIS_MII_CLK); 506 DELAY(1); 507 SIO_SET(SIS_MII_CLK); 508 } 509 } 510 511 /* 512 * Read an PHY register through the MII. 513 */ 514 static int 515 sis_mii_readreg(struct sis_softc *sc, struct sis_mii_frame *frame) 516 { 517 int i, ack; 518 519 /* 520 * Set up frame for RX. 521 */ 522 frame->mii_stdelim = SIS_MII_STARTDELIM; 523 frame->mii_opcode = SIS_MII_READOP; 524 frame->mii_turnaround = 0; 525 frame->mii_data = 0; 526 527 /* 528 * Turn on data xmit. 529 */ 530 SIO_SET(SIS_MII_DIR); 531 532 sis_mii_sync(sc); 533 534 /* 535 * Send command/address info. 536 */ 537 sis_mii_send(sc, frame->mii_stdelim, 2); 538 sis_mii_send(sc, frame->mii_opcode, 2); 539 sis_mii_send(sc, frame->mii_phyaddr, 5); 540 sis_mii_send(sc, frame->mii_regaddr, 5); 541 542 /* Idle bit */ 543 SIO_CLR((SIS_MII_CLK|SIS_MII_DATA)); 544 DELAY(1); 545 SIO_SET(SIS_MII_CLK); 546 DELAY(1); 547 548 /* Turn off xmit. */ 549 SIO_CLR(SIS_MII_DIR); 550 551 /* Check for ack */ 552 SIO_CLR(SIS_MII_CLK); 553 DELAY(1); 554 ack = CSR_READ_4(sc, SIS_EECTL) & SIS_MII_DATA; 555 SIO_SET(SIS_MII_CLK); 556 DELAY(1); 557 558 /* 559 * Now try reading data bits. If the ack failed, we still 560 * need to clock through 16 cycles to keep the PHY(s) in sync. 561 */ 562 if (ack) { 563 for(i = 0; i < 16; i++) { 564 SIO_CLR(SIS_MII_CLK); 565 DELAY(1); 566 SIO_SET(SIS_MII_CLK); 567 DELAY(1); 568 } 569 goto fail; 570 } 571 572 for (i = 0x8000; i; i >>= 1) { 573 SIO_CLR(SIS_MII_CLK); 574 DELAY(1); 575 if (!ack) { 576 if (CSR_READ_4(sc, SIS_EECTL) & SIS_MII_DATA) 577 frame->mii_data |= i; 578 DELAY(1); 579 } 580 SIO_SET(SIS_MII_CLK); 581 DELAY(1); 582 } 583 584 fail: 585 586 SIO_CLR(SIS_MII_CLK); 587 DELAY(1); 588 SIO_SET(SIS_MII_CLK); 589 DELAY(1); 590 591 if (ack) 592 return(1); 593 return(0); 594 } 595 596 /* 597 * Write to a PHY register through the MII. 598 */ 599 static int 600 sis_mii_writereg(struct sis_softc *sc, struct sis_mii_frame *frame) 601 { 602 /* 603 * Set up frame for TX. 604 */ 605 606 frame->mii_stdelim = SIS_MII_STARTDELIM; 607 frame->mii_opcode = SIS_MII_WRITEOP; 608 frame->mii_turnaround = SIS_MII_TURNAROUND; 609 610 /* 611 * Turn on data output. 612 */ 613 SIO_SET(SIS_MII_DIR); 614 615 sis_mii_sync(sc); 616 617 sis_mii_send(sc, frame->mii_stdelim, 2); 618 sis_mii_send(sc, frame->mii_opcode, 2); 619 sis_mii_send(sc, frame->mii_phyaddr, 5); 620 sis_mii_send(sc, frame->mii_regaddr, 5); 621 sis_mii_send(sc, frame->mii_turnaround, 2); 622 sis_mii_send(sc, frame->mii_data, 16); 623 624 /* Idle bit. */ 625 SIO_SET(SIS_MII_CLK); 626 DELAY(1); 627 SIO_CLR(SIS_MII_CLK); 628 DELAY(1); 629 630 /* 631 * Turn off xmit. 632 */ 633 SIO_CLR(SIS_MII_DIR); 634 635 return(0); 636 } 637 638 static int 639 sis_miibus_readreg(device_t dev, int phy, int reg) 640 { 641 struct sis_softc *sc; 642 struct sis_mii_frame frame; 643 644 sc = device_get_softc(dev); 645 646 if (sc->sis_type == SIS_TYPE_83815) { 647 if (phy != 0) 648 return(0); 649 /* 650 * The NatSemi chip can take a while after 651 * a reset to come ready, during which the BMSR 652 * returns a value of 0. This is *never* supposed 653 * to happen: some of the BMSR bits are meant to 654 * be hardwired in the on position, and this can 655 * confuse the miibus code a bit during the probe 656 * and attach phase. So we make an effort to check 657 * for this condition and wait for it to clear. 658 */ 659 if (!CSR_READ_4(sc, NS_BMSR)) 660 DELAY(1000); 661 return CSR_READ_4(sc, NS_BMCR + (reg * 4)); 662 } 663 /* 664 * Chipsets < SIS_635 seem not to be able to read/write 665 * through mdio. Use the enhanced PHY access register 666 * again for them. 667 */ 668 if (sc->sis_type == SIS_TYPE_900 && 669 sc->sis_rev < SIS_REV_635) { 670 int i, val = 0; 671 672 if (phy != 0) 673 return(0); 674 675 CSR_WRITE_4(sc, SIS_PHYCTL, 676 (phy << 11) | (reg << 6) | SIS_PHYOP_READ); 677 SIS_SETBIT(sc, SIS_PHYCTL, SIS_PHYCTL_ACCESS); 678 679 for (i = 0; i < SIS_TIMEOUT; i++) { 680 if (!(CSR_READ_4(sc, SIS_PHYCTL) & SIS_PHYCTL_ACCESS)) 681 break; 682 } 683 684 if (i == SIS_TIMEOUT) { 685 device_printf(dev, "PHY failed to come ready\n"); 686 return(0); 687 } 688 689 val = (CSR_READ_4(sc, SIS_PHYCTL) >> 16) & 0xFFFF; 690 691 if (val == 0xFFFF) 692 return(0); 693 694 return(val); 695 } else { 696 bzero((char *)&frame, sizeof(frame)); 697 698 frame.mii_phyaddr = phy; 699 frame.mii_regaddr = reg; 700 sis_mii_readreg(sc, &frame); 701 702 return(frame.mii_data); 703 } 704 } 705 706 static int 707 sis_miibus_writereg(device_t dev, int phy, int reg, int data) 708 { 709 struct sis_softc *sc; 710 struct sis_mii_frame frame; 711 712 sc = device_get_softc(dev); 713 714 if (sc->sis_type == SIS_TYPE_83815) { 715 if (phy != 0) 716 return(0); 717 CSR_WRITE_4(sc, NS_BMCR + (reg * 4), data); 718 return(0); 719 } 720 721 if (sc->sis_type == SIS_TYPE_900 && 722 sc->sis_rev < SIS_REV_635) { 723 int i; 724 725 if (phy != 0) 726 return(0); 727 728 CSR_WRITE_4(sc, SIS_PHYCTL, (data << 16) | (phy << 11) | 729 (reg << 6) | SIS_PHYOP_WRITE); 730 SIS_SETBIT(sc, SIS_PHYCTL, SIS_PHYCTL_ACCESS); 731 732 for (i = 0; i < SIS_TIMEOUT; i++) { 733 if (!(CSR_READ_4(sc, SIS_PHYCTL) & SIS_PHYCTL_ACCESS)) 734 break; 735 } 736 737 if (i == SIS_TIMEOUT) 738 device_printf(dev, "PHY failed to come ready\n"); 739 } else { 740 bzero((char *)&frame, sizeof(frame)); 741 742 frame.mii_phyaddr = phy; 743 frame.mii_regaddr = reg; 744 frame.mii_data = data; 745 sis_mii_writereg(sc, &frame); 746 } 747 return(0); 748 } 749 750 static void sis_miibus_statchg(device_t dev) 751 { 752 struct sis_softc *sc; 753 754 sc = device_get_softc(dev); 755 sis_init(sc); 756 } 757 758 static uint32_t 759 sis_mchash(struct sis_softc *sc, const uint8_t *addr) 760 { 761 uint32_t crc, carry; 762 int i, j; 763 uint8_t c; 764 765 /* Compute CRC for the address value. */ 766 crc = 0xFFFFFFFF; /* initial value */ 767 768 for (i = 0; i < 6; i++) { 769 c = *(addr + i); 770 for (j = 0; j < 8; j++) { 771 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 772 crc <<= 1; 773 c >>= 1; 774 if (carry) 775 crc = (crc ^ 0x04c11db6) | carry; 776 } 777 } 778 779 /* 780 * return the filter bit position 781 * 782 * The NatSemi chip has a 512-bit filter, which is 783 * different than the SiS, so we special-case it. 784 */ 785 if (sc->sis_type == SIS_TYPE_83815) 786 return (crc >> 23); 787 else if (sc->sis_rev >= SIS_REV_635 || sc->sis_rev == SIS_REV_900B) 788 return (crc >> 24); 789 else 790 return (crc >> 25); 791 } 792 793 static void 794 sis_setmulti_ns(struct sis_softc *sc) 795 { 796 struct ifnet *ifp; 797 struct ifmultiaddr *ifma; 798 uint32_t h = 0, i, filtsave; 799 int bit, index; 800 801 ifp = &sc->arpcom.ac_if; 802 803 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 804 SIS_CLRBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_MCHASH); 805 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLMULTI); 806 return; 807 } 808 809 /* 810 * We have to explicitly enable the multicast hash table 811 * on the NatSemi chip if we want to use it, which we do. 812 */ 813 SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_MCHASH); 814 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLMULTI); 815 816 filtsave = CSR_READ_4(sc, SIS_RXFILT_CTL); 817 818 /* first, zot all the existing hash bits */ 819 for (i = 0; i < 32; i++) { 820 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_FMEM_LO + (i*2)); 821 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 0); 822 } 823 824 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 825 if (ifma->ifma_addr->sa_family != AF_LINK) 826 continue; 827 h = sis_mchash(sc, 828 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 829 index = h >> 3; 830 bit = h & 0x1F; 831 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_FMEM_LO + index); 832 if (bit > 0xF) 833 bit -= 0x10; 834 SIS_SETBIT(sc, SIS_RXFILT_DATA, (1 << bit)); 835 } 836 837 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave); 838 } 839 840 static void 841 sis_setmulti_sis(struct sis_softc *sc) 842 { 843 struct ifnet *ifp; 844 struct ifmultiaddr *ifma; 845 uint32_t h, i, n, ctl; 846 uint16_t hashes[16]; 847 848 ifp = &sc->arpcom.ac_if; 849 850 /* hash table size */ 851 if (sc->sis_rev >= SIS_REV_635 || sc->sis_rev == SIS_REV_900B) 852 n = 16; 853 else 854 n = 8; 855 856 ctl = CSR_READ_4(sc, SIS_RXFILT_CTL) & SIS_RXFILTCTL_ENABLE; 857 858 if (ifp->if_flags & IFF_BROADCAST) 859 ctl |= SIS_RXFILTCTL_BROAD; 860 861 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 862 ctl |= SIS_RXFILTCTL_ALLMULTI; 863 if (ifp->if_flags & IFF_PROMISC) 864 ctl |= SIS_RXFILTCTL_BROAD|SIS_RXFILTCTL_ALLPHYS; 865 for (i = 0; i < n; i++) 866 hashes[i] = ~0; 867 } else { 868 for (i = 0; i < n; i++) 869 hashes[i] = 0; 870 i = 0; 871 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 872 if (ifma->ifma_addr->sa_family != AF_LINK) 873 continue; 874 h = sis_mchash(sc, 875 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 876 hashes[h >> 4] |= 1 << (h & 0xf); 877 i++; 878 } 879 if (i > n) { 880 ctl |= SIS_RXFILTCTL_ALLMULTI; 881 for (i = 0; i < n; i++) 882 hashes[i] = ~0; 883 } 884 } 885 886 for (i = 0; i < n; i++) { 887 CSR_WRITE_4(sc, SIS_RXFILT_CTL, (4 + i) << 16); 888 CSR_WRITE_4(sc, SIS_RXFILT_DATA, hashes[i]); 889 } 890 891 CSR_WRITE_4(sc, SIS_RXFILT_CTL, ctl); 892 } 893 894 static void 895 sis_reset(struct sis_softc *sc) 896 { 897 struct ifnet *ifp = &sc->arpcom.ac_if; 898 int i; 899 900 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RESET); 901 902 for (i = 0; i < SIS_TIMEOUT; i++) { 903 if (!(CSR_READ_4(sc, SIS_CSR) & SIS_CSR_RESET)) 904 break; 905 } 906 907 if (i == SIS_TIMEOUT) 908 if_printf(ifp, "reset never completed\n"); 909 910 /* Wait a little while for the chip to get its brains in order. */ 911 DELAY(1000); 912 913 /* 914 * If this is a NetSemi chip, make sure to clear 915 * PME mode. 916 */ 917 if (sc->sis_type == SIS_TYPE_83815) { 918 CSR_WRITE_4(sc, NS_CLKRUN, NS_CLKRUN_PMESTS); 919 CSR_WRITE_4(sc, NS_CLKRUN, 0); 920 } 921 } 922 923 /* 924 * Probe for an SiS chip. Check the PCI vendor and device 925 * IDs against our list and return a device name if we find a match. 926 */ 927 static int 928 sis_probe(device_t dev) 929 { 930 struct sis_type *t; 931 932 t = sis_devs; 933 934 while(t->sis_name != NULL) { 935 if ((pci_get_vendor(dev) == t->sis_vid) && 936 (pci_get_device(dev) == t->sis_did)) { 937 device_set_desc(dev, t->sis_name); 938 return(0); 939 } 940 t++; 941 } 942 943 return(ENXIO); 944 } 945 946 /* 947 * Attach the interface. Allocate softc structures, do ifmedia 948 * setup and ethernet/BPF attach. 949 */ 950 static int 951 sis_attach(device_t dev) 952 { 953 uint8_t eaddr[ETHER_ADDR_LEN]; 954 uint32_t command; 955 struct sis_softc *sc; 956 struct ifnet *ifp; 957 int error, rid, waittime; 958 959 error = waittime = 0; 960 sc = device_get_softc(dev); 961 962 if (pci_get_device(dev) == SIS_DEVICEID_900) 963 sc->sis_type = SIS_TYPE_900; 964 if (pci_get_device(dev) == SIS_DEVICEID_7016) 965 sc->sis_type = SIS_TYPE_7016; 966 if (pci_get_vendor(dev) == NS_VENDORID) 967 sc->sis_type = SIS_TYPE_83815; 968 969 sc->sis_rev = pci_read_config(dev, PCIR_REVID, 1); 970 971 /* 972 * Handle power management nonsense. 973 */ 974 975 command = pci_read_config(dev, SIS_PCI_CAPID, 4) & 0x000000FF; 976 if (command == 0x01) { 977 978 command = pci_read_config(dev, SIS_PCI_PWRMGMTCTRL, 4); 979 if (command & SIS_PSTATE_MASK) { 980 uint32_t iobase, membase, irq; 981 982 /* Save important PCI config data. */ 983 iobase = pci_read_config(dev, SIS_PCI_LOIO, 4); 984 membase = pci_read_config(dev, SIS_PCI_LOMEM, 4); 985 irq = pci_read_config(dev, SIS_PCI_INTLINE, 4); 986 987 /* Reset the power state. */ 988 device_printf(dev, "chip is in D%d power mode " 989 "-- setting to D0\n", command & SIS_PSTATE_MASK); 990 command &= 0xFFFFFFFC; 991 pci_write_config(dev, SIS_PCI_PWRMGMTCTRL, command, 4); 992 993 /* Restore PCI config data. */ 994 pci_write_config(dev, SIS_PCI_LOIO, iobase, 4); 995 pci_write_config(dev, SIS_PCI_LOMEM, membase, 4); 996 pci_write_config(dev, SIS_PCI_INTLINE, irq, 4); 997 } 998 } 999 1000 /* 1001 * Map control/status registers. 1002 */ 1003 command = pci_read_config(dev, PCIR_COMMAND, 4); 1004 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 1005 pci_write_config(dev, PCIR_COMMAND, command, 4); 1006 command = pci_read_config(dev, PCIR_COMMAND, 4); 1007 1008 #ifdef SIS_USEIOSPACE 1009 if (!(command & PCIM_CMD_PORTEN)) { 1010 device_printf(dev, "failed to enable I/O ports!\n"); 1011 error = ENXIO;; 1012 goto fail; 1013 } 1014 #else 1015 if (!(command & PCIM_CMD_MEMEN)) { 1016 device_printf(dev, "failed to enable memory mapping!\n"); 1017 error = ENXIO;; 1018 goto fail; 1019 } 1020 #endif 1021 1022 rid = SIS_RID; 1023 sc->sis_res = bus_alloc_resource_any(dev, SIS_RES, &rid, RF_ACTIVE); 1024 1025 if (sc->sis_res == NULL) { 1026 device_printf(dev, "couldn't map ports/memory\n"); 1027 error = ENXIO; 1028 goto fail; 1029 } 1030 1031 sc->sis_btag = rman_get_bustag(sc->sis_res); 1032 sc->sis_bhandle = rman_get_bushandle(sc->sis_res); 1033 1034 /* Allocate interrupt */ 1035 rid = 0; 1036 sc->sis_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1037 RF_SHAREABLE | RF_ACTIVE); 1038 1039 if (sc->sis_irq == NULL) { 1040 device_printf(dev, "couldn't map interrupt\n"); 1041 error = ENXIO; 1042 goto fail; 1043 } 1044 1045 /* Reset the adapter. */ 1046 sis_reset(sc); 1047 1048 if (sc->sis_type == SIS_TYPE_900 && 1049 (sc->sis_rev == SIS_REV_635 || 1050 sc->sis_rev == SIS_REV_900B)) { 1051 SIO_SET(SIS_CFG_RND_CNT); 1052 SIO_SET(SIS_CFG_PERR_DETECT); 1053 } 1054 1055 /* 1056 * Get station address from the EEPROM. 1057 */ 1058 switch (pci_get_vendor(dev)) { 1059 case NS_VENDORID: 1060 /* 1061 * Reading the MAC address out of the EEPROM on 1062 * the NatSemi chip takes a bit more work than 1063 * you'd expect. The address spans 4 16-bit words, 1064 * with the first word containing only a single bit. 1065 * You have to shift everything over one bit to 1066 * get it aligned properly. Also, the bits are 1067 * stored backwards (the LSB is really the MSB, 1068 * and so on) so you have to reverse them in order 1069 * to get the MAC address into the form we want. 1070 * Why? Who the hell knows. 1071 */ 1072 { 1073 uint16_t tmp[4]; 1074 1075 sis_read_eeprom(sc, (caddr_t)&tmp, 1076 NS_EE_NODEADDR, 4, 0); 1077 1078 /* Shift everything over one bit. */ 1079 tmp[3] = tmp[3] >> 1; 1080 tmp[3] |= tmp[2] << 15; 1081 tmp[2] = tmp[2] >> 1; 1082 tmp[2] |= tmp[1] << 15; 1083 tmp[1] = tmp[1] >> 1; 1084 tmp[1] |= tmp[0] << 15; 1085 1086 /* Now reverse all the bits. */ 1087 tmp[3] = sis_reverse(tmp[3]); 1088 tmp[2] = sis_reverse(tmp[2]); 1089 tmp[1] = sis_reverse(tmp[1]); 1090 1091 bcopy((char *)&tmp[1], eaddr, ETHER_ADDR_LEN); 1092 } 1093 break; 1094 case SIS_VENDORID: 1095 default: 1096 #ifdef __i386__ 1097 /* 1098 * If this is a SiS 630E chipset with an embedded 1099 * SiS 900 controller, we have to read the MAC address 1100 * from the APC CMOS RAM. Our method for doing this 1101 * is very ugly since we have to reach out and grab 1102 * ahold of hardware for which we cannot properly 1103 * allocate resources. This code is only compiled on 1104 * the i386 architecture since the SiS 630E chipset 1105 * is for x86 motherboards only. Note that there are 1106 * a lot of magic numbers in this hack. These are 1107 * taken from SiS's Linux driver. I'd like to replace 1108 * them with proper symbolic definitions, but that 1109 * requires some datasheets that I don't have access 1110 * to at the moment. 1111 */ 1112 if (sc->sis_rev == SIS_REV_630S || 1113 sc->sis_rev == SIS_REV_630E || 1114 sc->sis_rev == SIS_REV_630EA1) 1115 sis_read_cmos(sc, dev, (caddr_t)&eaddr, 0x9, 6); 1116 1117 else if (sc->sis_rev == SIS_REV_635 || 1118 sc->sis_rev == SIS_REV_630ET) 1119 sis_read_mac(sc, dev, (caddr_t)&eaddr); 1120 else if (sc->sis_rev == SIS_REV_96x) { 1121 /* 1122 * Allow to read EEPROM from LAN. It is shared 1123 * between a 1394 controller and the NIC and each 1124 * time we access it, we need to set SIS_EECMD_REQ. 1125 */ 1126 SIO_SET(SIS_EECMD_REQ); 1127 for (waittime = 0; waittime < SIS_TIMEOUT; 1128 waittime++) { 1129 /* Force EEPROM to idle state. */ 1130 sis_eeprom_idle(sc); 1131 if (CSR_READ_4(sc, SIS_EECTL) & SIS_EECMD_GNT) { 1132 sis_read_eeprom(sc, (caddr_t)&eaddr, 1133 SIS_EE_NODEADDR, 3, 0); 1134 break; 1135 } 1136 DELAY(1); 1137 } 1138 /* 1139 * Set SIS_EECTL_CLK to high, so a other master 1140 * can operate on the i2c bus. 1141 */ 1142 SIO_SET(SIS_EECTL_CLK); 1143 /* Refuse EEPROM access by LAN */ 1144 SIO_SET(SIS_EECMD_DONE); 1145 } else 1146 #endif 1147 sis_read_eeprom(sc, (caddr_t)&eaddr, 1148 SIS_EE_NODEADDR, 3, 0); 1149 break; 1150 } 1151 1152 callout_init(&sc->sis_timer); 1153 1154 /* 1155 * Allocate the parent bus DMA tag appropriate for PCI. 1156 */ 1157 #define SIS_NSEG_NEW 32 1158 error = bus_dma_tag_create(NULL, /* parent */ 1159 1, 0, /* alignment, boundary */ 1160 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */ 1161 BUS_SPACE_MAXADDR, /* highaddr */ 1162 NULL, NULL, /* filter, filterarg */ 1163 MAXBSIZE, SIS_NSEG_NEW, /* maxsize, nsegments */ 1164 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1165 BUS_DMA_ALLOCNOW, /* flags */ 1166 &sc->sis_parent_tag); 1167 if (error) 1168 goto fail; 1169 1170 /* 1171 * Now allocate a tag for the DMA descriptor lists and a chunk 1172 * of DMA-able memory based on the tag. Also obtain the physical 1173 * addresses of the RX and TX ring, which we'll need later. 1174 * All of our lists are allocated as a contiguous block of memory. 1175 */ 1176 error = bus_dma_tag_create(sc->sis_parent_tag, /* parent */ 1177 1, 0, /* alignment, boundary */ 1178 BUS_SPACE_MAXADDR, /* lowaddr */ 1179 BUS_SPACE_MAXADDR, /* highaddr */ 1180 NULL, NULL, /* filter, filterarg */ 1181 SIS_RX_LIST_SZ, 1, /* maxsize, nsegments */ 1182 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1183 0, /* flags */ 1184 &sc->sis_ldata.sis_rx_tag); 1185 if (error) 1186 goto fail; 1187 1188 error = bus_dmamem_alloc(sc->sis_ldata.sis_rx_tag, 1189 (void **)&sc->sis_ldata.sis_rx_list, 1190 BUS_DMA_WAITOK | BUS_DMA_ZERO, 1191 &sc->sis_ldata.sis_rx_dmamap); 1192 1193 if (error) { 1194 device_printf(dev, "no memory for rx list buffers!\n"); 1195 bus_dma_tag_destroy(sc->sis_ldata.sis_rx_tag); 1196 sc->sis_ldata.sis_rx_tag = NULL; 1197 goto fail; 1198 } 1199 1200 error = bus_dmamap_load(sc->sis_ldata.sis_rx_tag, 1201 sc->sis_ldata.sis_rx_dmamap, 1202 sc->sis_ldata.sis_rx_list, 1203 sizeof(struct sis_desc), sis_dma_map_ring, 1204 &sc->sis_cdata.sis_rx_paddr, 0); 1205 1206 if (error) { 1207 device_printf(dev, "cannot get address of the rx ring!\n"); 1208 bus_dmamem_free(sc->sis_ldata.sis_rx_tag, 1209 sc->sis_ldata.sis_rx_list, 1210 sc->sis_ldata.sis_rx_dmamap); 1211 bus_dma_tag_destroy(sc->sis_ldata.sis_rx_tag); 1212 sc->sis_ldata.sis_rx_tag = NULL; 1213 goto fail; 1214 } 1215 1216 error = bus_dma_tag_create(sc->sis_parent_tag, /* parent */ 1217 1, 0, /* alignment, boundary */ 1218 BUS_SPACE_MAXADDR, /* lowaddr */ 1219 BUS_SPACE_MAXADDR, /* highaddr */ 1220 NULL, NULL, /* filter, filterarg */ 1221 SIS_TX_LIST_SZ, 1, /* maxsize, nsegments */ 1222 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1223 0, /* flags */ 1224 &sc->sis_ldata.sis_tx_tag); 1225 if (error) 1226 goto fail; 1227 1228 error = bus_dmamem_alloc(sc->sis_ldata.sis_tx_tag, 1229 (void **)&sc->sis_ldata.sis_tx_list, 1230 BUS_DMA_WAITOK | BUS_DMA_ZERO, 1231 &sc->sis_ldata.sis_tx_dmamap); 1232 1233 if (error) { 1234 device_printf(dev, "no memory for tx list buffers!\n"); 1235 bus_dma_tag_destroy(sc->sis_ldata.sis_tx_tag); 1236 sc->sis_ldata.sis_tx_tag = NULL; 1237 goto fail; 1238 } 1239 1240 error = bus_dmamap_load(sc->sis_ldata.sis_tx_tag, 1241 sc->sis_ldata.sis_tx_dmamap, 1242 sc->sis_ldata.sis_tx_list, 1243 sizeof(struct sis_desc), sis_dma_map_ring, 1244 &sc->sis_cdata.sis_tx_paddr, 0); 1245 1246 if (error) { 1247 device_printf(dev, "cannot get address of the tx ring!\n"); 1248 bus_dmamem_free(sc->sis_ldata.sis_tx_tag, 1249 sc->sis_ldata.sis_tx_list, 1250 sc->sis_ldata.sis_tx_dmamap); 1251 bus_dma_tag_destroy(sc->sis_ldata.sis_tx_tag); 1252 sc->sis_ldata.sis_tx_tag = NULL; 1253 goto fail; 1254 } 1255 1256 error = bus_dma_tag_create(sc->sis_parent_tag, /* parent */ 1257 1, 0, /* alignment, boundary */ 1258 BUS_SPACE_MAXADDR, /* lowaddr */ 1259 BUS_SPACE_MAXADDR, /* highaddr */ 1260 NULL, NULL, /* filter, filterarg */ 1261 MCLBYTES, 1, /* maxsize, nsegments */ 1262 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1263 0, /* flags */ 1264 &sc->sis_tag); 1265 if (error) 1266 goto fail; 1267 1268 ifp = &sc->arpcom.ac_if; 1269 ifp->if_softc = sc; 1270 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1271 ifp->if_mtu = ETHERMTU; 1272 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1273 ifp->if_ioctl = sis_ioctl; 1274 ifp->if_start = sis_start; 1275 ifp->if_watchdog = sis_watchdog; 1276 ifp->if_init = sis_init; 1277 ifp->if_baudrate = 10000000; 1278 ifq_set_maxlen(&ifp->if_snd, SIS_TX_LIST_CNT - 1); 1279 ifq_set_ready(&ifp->if_snd); 1280 #ifdef DEVICE_POLLING 1281 ifp->if_poll = sis_poll; 1282 #endif 1283 ifp->if_capenable = ifp->if_capabilities; 1284 1285 /* 1286 * Do MII setup. 1287 */ 1288 if (mii_phy_probe(dev, &sc->sis_miibus, 1289 sis_ifmedia_upd, sis_ifmedia_sts)) { 1290 device_printf(dev, "MII without any PHY!\n"); 1291 error = ENXIO; 1292 goto fail; 1293 } 1294 1295 /* 1296 * Call MI attach routine. 1297 */ 1298 ether_ifattach(ifp, eaddr, NULL); 1299 1300 /* 1301 * Tell the upper layer(s) we support long frames. 1302 */ 1303 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1304 1305 error = bus_setup_intr(dev, sc->sis_irq, INTR_NETSAFE, 1306 sis_intr, sc, 1307 &sc->sis_intrhand, 1308 ifp->if_serializer); 1309 1310 if (error) { 1311 device_printf(dev, "couldn't set up irq\n"); 1312 ether_ifdetach(ifp); 1313 goto fail; 1314 } 1315 1316 fail: 1317 if (error) 1318 sis_detach(dev); 1319 1320 return(error); 1321 } 1322 1323 /* 1324 * Shutdown hardware and free up resources. It is called in both the error case 1325 * and the normal detach case so it needs to be careful about only freeing 1326 * resources that have actually been allocated. 1327 */ 1328 static int 1329 sis_detach(device_t dev) 1330 { 1331 struct sis_softc *sc = device_get_softc(dev); 1332 struct ifnet *ifp = &sc->arpcom.ac_if; 1333 1334 1335 if (device_is_attached(dev)) { 1336 lwkt_serialize_enter(ifp->if_serializer); 1337 sis_reset(sc); 1338 sis_stop(sc); 1339 bus_teardown_intr(dev, sc->sis_irq, sc->sis_intrhand); 1340 lwkt_serialize_exit(ifp->if_serializer); 1341 1342 ether_ifdetach(ifp); 1343 } 1344 if (sc->sis_miibus) 1345 device_delete_child(dev, sc->sis_miibus); 1346 bus_generic_detach(dev); 1347 1348 if (sc->sis_irq) 1349 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sis_irq); 1350 if (sc->sis_res) 1351 bus_release_resource(dev, SIS_RES, SIS_RID, sc->sis_res); 1352 1353 if (sc->sis_ldata.sis_rx_tag) { 1354 bus_dmamap_unload(sc->sis_ldata.sis_rx_tag, 1355 sc->sis_ldata.sis_rx_dmamap); 1356 bus_dmamem_free(sc->sis_ldata.sis_rx_tag, 1357 sc->sis_ldata.sis_rx_list, 1358 sc->sis_ldata.sis_rx_dmamap); 1359 bus_dma_tag_destroy(sc->sis_ldata.sis_rx_tag); 1360 } 1361 1362 if (sc->sis_ldata.sis_tx_tag) { 1363 bus_dmamap_unload(sc->sis_ldata.sis_tx_tag, 1364 sc->sis_ldata.sis_tx_dmamap); 1365 bus_dmamem_free(sc->sis_ldata.sis_tx_tag, 1366 sc->sis_ldata.sis_tx_list, 1367 sc->sis_ldata.sis_tx_dmamap); 1368 bus_dma_tag_destroy(sc->sis_ldata.sis_tx_tag); 1369 } 1370 if (sc->sis_tag) 1371 bus_dma_tag_destroy(sc->sis_tag); 1372 if (sc->sis_parent_tag) 1373 bus_dma_tag_destroy(sc->sis_parent_tag); 1374 1375 return(0); 1376 } 1377 1378 /* 1379 * Initialize the transmit descriptors. 1380 */ 1381 static int 1382 sis_list_tx_init(struct sis_softc *sc) 1383 { 1384 struct sis_list_data *ld; 1385 struct sis_ring_data *cd; 1386 int i, nexti; 1387 1388 cd = &sc->sis_cdata; 1389 ld = &sc->sis_ldata; 1390 1391 for (i = 0; i < SIS_TX_LIST_CNT; i++) { 1392 nexti = (i == (SIS_TX_LIST_CNT - 1)) ? 0 : i+1; 1393 ld->sis_tx_list[i].sis_nextdesc = 1394 &ld->sis_tx_list[nexti]; 1395 bus_dmamap_load(sc->sis_ldata.sis_tx_tag, 1396 sc->sis_ldata.sis_tx_dmamap, 1397 &ld->sis_tx_list[nexti], 1398 sizeof(struct sis_desc), sis_dma_map_desc_next, 1399 &ld->sis_tx_list[i], 0); 1400 ld->sis_tx_list[i].sis_mbuf = NULL; 1401 ld->sis_tx_list[i].sis_ptr = 0; 1402 ld->sis_tx_list[i].sis_ctl = 0; 1403 } 1404 1405 cd->sis_tx_prod = cd->sis_tx_cons = cd->sis_tx_cnt = 0; 1406 1407 bus_dmamap_sync(sc->sis_ldata.sis_tx_tag, sc->sis_ldata.sis_tx_dmamap, 1408 BUS_DMASYNC_PREWRITE); 1409 1410 return(0); 1411 } 1412 1413 /* 1414 * Initialize the RX descriptors and allocate mbufs for them. Note that 1415 * we arrange the descriptors in a closed ring, so that the last descriptor 1416 * points back to the first. 1417 */ 1418 static int 1419 sis_list_rx_init(struct sis_softc *sc) 1420 { 1421 struct sis_list_data *ld; 1422 struct sis_ring_data *cd; 1423 int i, nexti; 1424 1425 ld = &sc->sis_ldata; 1426 cd = &sc->sis_cdata; 1427 1428 for (i = 0; i < SIS_RX_LIST_CNT; i++) { 1429 if (sis_newbuf(sc, &ld->sis_rx_list[i], NULL) == ENOBUFS) 1430 return(ENOBUFS); 1431 nexti = (i == (SIS_RX_LIST_CNT - 1)) ? 0 : i+1; 1432 ld->sis_rx_list[i].sis_nextdesc = 1433 &ld->sis_rx_list[nexti]; 1434 bus_dmamap_load(sc->sis_ldata.sis_rx_tag, 1435 sc->sis_ldata.sis_rx_dmamap, 1436 &ld->sis_rx_list[nexti], 1437 sizeof(struct sis_desc), sis_dma_map_desc_next, 1438 &ld->sis_rx_list[i], 0); 1439 } 1440 1441 bus_dmamap_sync(sc->sis_ldata.sis_rx_tag, sc->sis_ldata.sis_rx_dmamap, 1442 BUS_DMASYNC_PREWRITE); 1443 1444 cd->sis_rx_prod = 0; 1445 1446 return(0); 1447 } 1448 1449 /* 1450 * Initialize an RX descriptor and attach an MBUF cluster. 1451 */ 1452 static int 1453 sis_newbuf(struct sis_softc *sc, struct sis_desc *c, struct mbuf *m) 1454 { 1455 if (m == NULL) { 1456 m = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR); 1457 if (m == NULL) 1458 return(ENOBUFS); 1459 } else { 1460 m->m_data = m->m_ext.ext_buf; 1461 } 1462 1463 c->sis_mbuf = m; 1464 c->sis_ctl = SIS_RXLEN; 1465 1466 bus_dmamap_create(sc->sis_tag, 0, &c->sis_map); 1467 bus_dmamap_load(sc->sis_tag, c->sis_map, mtod(m, void *), MCLBYTES, 1468 sis_dma_map_desc_ptr, c, 0); 1469 bus_dmamap_sync(sc->sis_tag, c->sis_map, BUS_DMASYNC_PREWRITE); 1470 1471 return(0); 1472 } 1473 1474 /* 1475 * A frame has been uploaded: pass the resulting mbuf chain up to 1476 * the higher level protocols. 1477 */ 1478 static void 1479 sis_rxeof(struct sis_softc *sc) 1480 { 1481 struct mbuf *m; 1482 struct ifnet *ifp; 1483 struct sis_desc *cur_rx; 1484 int i, total_len = 0; 1485 uint32_t rxstat; 1486 1487 ifp = &sc->arpcom.ac_if; 1488 i = sc->sis_cdata.sis_rx_prod; 1489 1490 while(SIS_OWNDESC(&sc->sis_ldata.sis_rx_list[i])) { 1491 1492 #ifdef DEVICE_POLLING 1493 if (ifp->if_flags & IFF_POLLING) { 1494 if (sc->rxcycles <= 0) 1495 break; 1496 sc->rxcycles--; 1497 } 1498 #endif /* DEVICE_POLLING */ 1499 cur_rx = &sc->sis_ldata.sis_rx_list[i]; 1500 rxstat = cur_rx->sis_rxstat; 1501 bus_dmamap_sync(sc->sis_tag, cur_rx->sis_map, 1502 BUS_DMASYNC_POSTWRITE); 1503 bus_dmamap_unload(sc->sis_tag, cur_rx->sis_map); 1504 bus_dmamap_destroy(sc->sis_tag, cur_rx->sis_map); 1505 m = cur_rx->sis_mbuf; 1506 cur_rx->sis_mbuf = NULL; 1507 total_len = SIS_RXBYTES(cur_rx); 1508 SIS_INC(i, SIS_RX_LIST_CNT); 1509 1510 /* 1511 * If an error occurs, update stats, clear the 1512 * status word and leave the mbuf cluster in place: 1513 * it should simply get re-used next time this descriptor 1514 * comes up in the ring. 1515 */ 1516 if (!(rxstat & SIS_CMDSTS_PKT_OK)) { 1517 ifp->if_ierrors++; 1518 if (rxstat & SIS_RXSTAT_COLL) 1519 ifp->if_collisions++; 1520 sis_newbuf(sc, cur_rx, m); 1521 continue; 1522 } 1523 1524 /* No errors; receive the packet. */ 1525 #ifdef __i386__ 1526 /* 1527 * On the x86 we do not have alignment problems, so try to 1528 * allocate a new buffer for the receive ring, and pass up 1529 * the one where the packet is already, saving the expensive 1530 * copy done in m_devget(). 1531 * If we are on an architecture with alignment problems, or 1532 * if the allocation fails, then use m_devget and leave the 1533 * existing buffer in the receive ring. 1534 */ 1535 if (sis_newbuf(sc, cur_rx, NULL) == 0) 1536 m->m_pkthdr.len = m->m_len = total_len; 1537 else 1538 #endif 1539 { 1540 struct mbuf *m0; 1541 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 1542 total_len + ETHER_ALIGN, 0, ifp, NULL); 1543 sis_newbuf(sc, cur_rx, m); 1544 if (m0 == NULL) { 1545 ifp->if_ierrors++; 1546 continue; 1547 } 1548 m_adj(m0, ETHER_ALIGN); 1549 m = m0; 1550 } 1551 1552 ifp->if_ipackets++; 1553 ifp->if_input(ifp, m); 1554 } 1555 1556 sc->sis_cdata.sis_rx_prod = i; 1557 } 1558 1559 static void 1560 sis_rxeoc(struct sis_softc *sc) 1561 { 1562 sis_rxeof(sc); 1563 sis_init(sc); 1564 } 1565 1566 /* 1567 * A frame was downloaded to the chip. It's safe for us to clean up 1568 * the list buffers. 1569 */ 1570 1571 static void 1572 sis_txeof(struct sis_softc *sc) 1573 { 1574 struct sis_desc *cur_tx; 1575 struct ifnet *ifp; 1576 uint32_t idx; 1577 1578 ifp = &sc->arpcom.ac_if; 1579 1580 /* 1581 * Go through our tx list and free mbufs for those 1582 * frames that have been transmitted. 1583 */ 1584 for (idx = sc->sis_cdata.sis_tx_cons; sc->sis_cdata.sis_tx_cnt > 0; 1585 sc->sis_cdata.sis_tx_cnt--, SIS_INC(idx, SIS_TX_LIST_CNT) ) { 1586 cur_tx = &sc->sis_ldata.sis_tx_list[idx]; 1587 1588 if (SIS_OWNDESC(cur_tx)) 1589 break; 1590 1591 if (cur_tx->sis_ctl & SIS_CMDSTS_MORE) 1592 continue; 1593 1594 if (!(cur_tx->sis_ctl & SIS_CMDSTS_PKT_OK)) { 1595 ifp->if_oerrors++; 1596 if (cur_tx->sis_txstat & SIS_TXSTAT_EXCESSCOLLS) 1597 ifp->if_collisions++; 1598 if (cur_tx->sis_txstat & SIS_TXSTAT_OUTOFWINCOLL) 1599 ifp->if_collisions++; 1600 } 1601 1602 ifp->if_collisions += 1603 (cur_tx->sis_txstat & SIS_TXSTAT_COLLCNT) >> 16; 1604 1605 ifp->if_opackets++; 1606 if (cur_tx->sis_mbuf != NULL) { 1607 m_freem(cur_tx->sis_mbuf); 1608 cur_tx->sis_mbuf = NULL; 1609 bus_dmamap_unload(sc->sis_tag, cur_tx->sis_map); 1610 bus_dmamap_destroy(sc->sis_tag, cur_tx->sis_map); 1611 } 1612 } 1613 1614 if (idx != sc->sis_cdata.sis_tx_cons) { 1615 /* we freed up some buffers */ 1616 sc->sis_cdata.sis_tx_cons = idx; 1617 ifp->if_flags &= ~IFF_OACTIVE; 1618 } 1619 1620 ifp->if_timer = (sc->sis_cdata.sis_tx_cnt == 0) ? 0 : 5; 1621 } 1622 1623 static void 1624 sis_tick(void *xsc) 1625 { 1626 struct sis_softc *sc = xsc; 1627 struct mii_data *mii; 1628 struct ifnet *ifp = &sc->arpcom.ac_if; 1629 1630 lwkt_serialize_enter(ifp->if_serializer); 1631 1632 mii = device_get_softc(sc->sis_miibus); 1633 mii_tick(mii); 1634 1635 if (!sc->sis_link) { 1636 mii_pollstat(mii); 1637 if (mii->mii_media_status & IFM_ACTIVE && 1638 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 1639 sc->sis_link++; 1640 if (!ifq_is_empty(&ifp->if_snd)) 1641 sis_start(ifp); 1642 } 1643 1644 callout_reset(&sc->sis_timer, hz, sis_tick, sc); 1645 lwkt_serialize_exit(ifp->if_serializer); 1646 } 1647 1648 #ifdef DEVICE_POLLING 1649 1650 static void 1651 sis_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1652 { 1653 struct sis_softc *sc = ifp->if_softc; 1654 1655 switch(cmd) { 1656 case POLL_REGISTER: 1657 /* disable interrupts */ 1658 CSR_WRITE_4(sc, SIS_IER, 0); 1659 break; 1660 case POLL_DEREGISTER: 1661 /* enable interrupts */ 1662 CSR_WRITE_4(sc, SIS_IER, 1); 1663 break; 1664 default: 1665 /* 1666 * On the sis, reading the status register also clears it. 1667 * So before returning to intr mode we must make sure that all 1668 * possible pending sources of interrupts have been served. 1669 * In practice this means run to completion the *eof routines, 1670 * and then call the interrupt routine 1671 */ 1672 sc->rxcycles = count; 1673 sis_rxeof(sc); 1674 sis_txeof(sc); 1675 if (!ifq_is_empty(&ifp->if_snd)) 1676 sis_start(ifp); 1677 1678 if (sc->rxcycles > 0 || cmd == POLL_AND_CHECK_STATUS) { 1679 uint32_t status; 1680 1681 /* Reading the ISR register clears all interrupts. */ 1682 status = CSR_READ_4(sc, SIS_ISR); 1683 1684 if (status & (SIS_ISR_RX_ERR|SIS_ISR_RX_OFLOW)) 1685 sis_rxeoc(sc); 1686 1687 if (status & (SIS_ISR_RX_IDLE)) 1688 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE); 1689 1690 if (status & SIS_ISR_SYSERR) { 1691 sis_reset(sc); 1692 sis_init(sc); 1693 } 1694 } 1695 break; 1696 } 1697 } 1698 #endif /* DEVICE_POLLING */ 1699 1700 static void 1701 sis_intr(void *arg) 1702 { 1703 struct sis_softc *sc; 1704 struct ifnet *ifp; 1705 uint32_t status; 1706 1707 sc = arg; 1708 ifp = &sc->arpcom.ac_if; 1709 1710 /* Supress unwanted interrupts */ 1711 if (!(ifp->if_flags & IFF_UP)) { 1712 sis_stop(sc); 1713 return; 1714 } 1715 1716 /* Disable interrupts. */ 1717 CSR_WRITE_4(sc, SIS_IER, 0); 1718 1719 for (;;) { 1720 /* Reading the ISR register clears all interrupts. */ 1721 status = CSR_READ_4(sc, SIS_ISR); 1722 1723 if ((status & SIS_INTRS) == 0) 1724 break; 1725 1726 if (status & 1727 (SIS_ISR_TX_DESC_OK | SIS_ISR_TX_ERR | SIS_ISR_TX_OK | 1728 SIS_ISR_TX_IDLE) ) 1729 sis_txeof(sc); 1730 1731 if (status & 1732 (SIS_ISR_RX_DESC_OK | SIS_ISR_RX_OK | SIS_ISR_RX_IDLE)) 1733 sis_rxeof(sc); 1734 1735 if (status & (SIS_ISR_RX_ERR | SIS_ISR_RX_OFLOW)) 1736 sis_rxeoc(sc); 1737 1738 if (status & (SIS_ISR_RX_IDLE)) 1739 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE); 1740 1741 if (status & SIS_ISR_SYSERR) { 1742 sis_reset(sc); 1743 sis_init(sc); 1744 } 1745 } 1746 1747 /* Re-enable interrupts. */ 1748 CSR_WRITE_4(sc, SIS_IER, 1); 1749 1750 if (!ifq_is_empty(&ifp->if_snd)) 1751 sis_start(ifp); 1752 } 1753 1754 /* 1755 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1756 * pointers to the fragment pointers. 1757 */ 1758 static int 1759 sis_encap(struct sis_softc *sc, struct mbuf *m_head, uint32_t *txidx) 1760 { 1761 struct sis_desc *f = NULL; 1762 struct mbuf *m; 1763 int frag, cur, cnt = 0; 1764 1765 /* 1766 * If there's no way we can send any packets, return now. 1767 */ 1768 if (SIS_TX_LIST_CNT - sc->sis_cdata.sis_tx_cnt < 2) 1769 return (ENOBUFS); 1770 1771 /* 1772 * Start packing the mbufs in this chain into 1773 * the fragment pointers. Stop when we run out 1774 * of fragments or hit the end of the mbuf chain. 1775 */ 1776 m = m_head; 1777 cur = frag = *txidx; 1778 1779 for (m = m_head; m != NULL; m = m->m_next) { 1780 if (m->m_len != 0) { 1781 if ((SIS_TX_LIST_CNT - 1782 (sc->sis_cdata.sis_tx_cnt + cnt)) < 2) 1783 return(ENOBUFS); 1784 f = &sc->sis_ldata.sis_tx_list[frag]; 1785 f->sis_ctl = SIS_CMDSTS_MORE | m->m_len; 1786 bus_dmamap_create(sc->sis_tag, 0, &f->sis_map); 1787 bus_dmamap_load(sc->sis_tag, f->sis_map, 1788 mtod(m, void *), m->m_len, 1789 sis_dma_map_desc_ptr, f, 0); 1790 bus_dmamap_sync(sc->sis_tag, f->sis_map, 1791 BUS_DMASYNC_PREREAD); 1792 if (cnt != 0) 1793 f->sis_ctl |= SIS_CMDSTS_OWN; 1794 cur = frag; 1795 SIS_INC(frag, SIS_TX_LIST_CNT); 1796 cnt++; 1797 } 1798 } 1799 1800 if (m != NULL) 1801 return(ENOBUFS); 1802 1803 sc->sis_ldata.sis_tx_list[cur].sis_mbuf = m_head; 1804 sc->sis_ldata.sis_tx_list[cur].sis_ctl &= ~SIS_CMDSTS_MORE; 1805 sc->sis_ldata.sis_tx_list[*txidx].sis_ctl |= SIS_CMDSTS_OWN; 1806 sc->sis_cdata.sis_tx_cnt += cnt; 1807 *txidx = frag; 1808 1809 return(0); 1810 } 1811 1812 /* 1813 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1814 * to the mbuf data regions directly in the transmit lists. We also save a 1815 * copy of the pointers since the transmit list fragment pointers are 1816 * physical addresses. 1817 */ 1818 1819 static void 1820 sis_start(struct ifnet *ifp) 1821 { 1822 struct sis_softc *sc; 1823 struct mbuf *m_head = NULL; 1824 uint32_t idx; 1825 int need_trans; 1826 1827 sc = ifp->if_softc; 1828 1829 if (!sc->sis_link) 1830 return; 1831 1832 idx = sc->sis_cdata.sis_tx_prod; 1833 1834 if (ifp->if_flags & IFF_OACTIVE) 1835 return; 1836 1837 need_trans = 0; 1838 while(sc->sis_ldata.sis_tx_list[idx].sis_mbuf == NULL) { 1839 m_head = ifq_poll(&ifp->if_snd); 1840 if (m_head == NULL) 1841 break; 1842 1843 if (sis_encap(sc, m_head, &idx)) { 1844 ifp->if_flags |= IFF_OACTIVE; 1845 break; 1846 } 1847 ifq_dequeue(&ifp->if_snd, m_head); 1848 need_trans = 1; 1849 1850 /* 1851 * If there's a BPF listener, bounce a copy of this frame 1852 * to him. 1853 */ 1854 BPF_MTAP(ifp, m_head); 1855 } 1856 1857 if (!need_trans) 1858 return; 1859 1860 /* Transmit */ 1861 sc->sis_cdata.sis_tx_prod = idx; 1862 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_ENABLE); 1863 1864 /* 1865 * Set a timeout in case the chip goes out to lunch. 1866 */ 1867 ifp->if_timer = 5; 1868 } 1869 1870 static void 1871 sis_init(void *xsc) 1872 { 1873 struct sis_softc *sc = xsc; 1874 struct ifnet *ifp = &sc->arpcom.ac_if; 1875 struct mii_data *mii; 1876 1877 /* 1878 * Cancel pending I/O and free all RX/TX buffers. 1879 */ 1880 sis_stop(sc); 1881 1882 mii = device_get_softc(sc->sis_miibus); 1883 1884 /* Set MAC address */ 1885 if (sc->sis_type == SIS_TYPE_83815) { 1886 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR0); 1887 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1888 ((uint16_t *)sc->arpcom.ac_enaddr)[0]); 1889 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR1); 1890 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1891 ((uint16_t *)sc->arpcom.ac_enaddr)[1]); 1892 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR2); 1893 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1894 ((uint16_t *)sc->arpcom.ac_enaddr)[2]); 1895 } else { 1896 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR0); 1897 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1898 ((uint16_t *)sc->arpcom.ac_enaddr)[0]); 1899 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR1); 1900 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1901 ((uint16_t *)sc->arpcom.ac_enaddr)[1]); 1902 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR2); 1903 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1904 ((uint16_t *)sc->arpcom.ac_enaddr)[2]); 1905 } 1906 1907 /* Init circular RX list. */ 1908 if (sis_list_rx_init(sc) == ENOBUFS) { 1909 if_printf(ifp, "initialization failed: " 1910 "no memory for rx buffers\n"); 1911 sis_stop(sc); 1912 return; 1913 } 1914 1915 /* 1916 * Init tx descriptors. 1917 */ 1918 sis_list_tx_init(sc); 1919 1920 /* 1921 * For the NatSemi chip, we have to explicitly enable the 1922 * reception of ARP frames, as well as turn on the 'perfect 1923 * match' filter where we store the station address, otherwise 1924 * we won't receive unicasts meant for this host. 1925 */ 1926 if (sc->sis_type == SIS_TYPE_83815) { 1927 SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_ARP); 1928 SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_PERFECT); 1929 } 1930 1931 /* If we want promiscuous mode, set the allframes bit. */ 1932 if (ifp->if_flags & IFF_PROMISC) 1933 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLPHYS); 1934 else 1935 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLPHYS); 1936 1937 /* 1938 * Set the capture broadcast bit to capture broadcast frames. 1939 */ 1940 if (ifp->if_flags & IFF_BROADCAST) 1941 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_BROAD); 1942 else 1943 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_BROAD); 1944 1945 /* 1946 * Load the multicast filter. 1947 */ 1948 if (sc->sis_type == SIS_TYPE_83815) 1949 sis_setmulti_ns(sc); 1950 else 1951 sis_setmulti_sis(sc); 1952 1953 /* Turn the receive filter on */ 1954 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ENABLE); 1955 1956 /* 1957 * Load the address of the RX and TX lists. 1958 */ 1959 CSR_WRITE_4(sc, SIS_RX_LISTPTR, sc->sis_cdata.sis_rx_paddr); 1960 CSR_WRITE_4(sc, SIS_TX_LISTPTR, sc->sis_cdata.sis_tx_paddr); 1961 1962 /* SIS_CFG_EDB_MASTER_EN indicates the EDB bus is used instead of 1963 * the PCI bus. When this bit is set, the Max DMA Burst Size 1964 * for TX/RX DMA should be no larger than 16 double words. 1965 */ 1966 if (CSR_READ_4(sc, SIS_CFG) & SIS_CFG_EDB_MASTER_EN) 1967 CSR_WRITE_4(sc, SIS_RX_CFG, SIS_RXCFG64); 1968 else 1969 CSR_WRITE_4(sc, SIS_RX_CFG, SIS_RXCFG256); 1970 1971 /* Accept Long Packets for VLAN support */ 1972 SIS_SETBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_JABBER); 1973 1974 /* Set TX configuration */ 1975 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T) 1976 CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_10); 1977 else 1978 CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_100); 1979 1980 /* Set full/half duplex mode. */ 1981 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 1982 SIS_SETBIT(sc, SIS_TX_CFG, 1983 (SIS_TXCFG_IGN_HBEAT|SIS_TXCFG_IGN_CARR)); 1984 SIS_SETBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS); 1985 } else { 1986 SIS_CLRBIT(sc, SIS_TX_CFG, 1987 (SIS_TXCFG_IGN_HBEAT|SIS_TXCFG_IGN_CARR)); 1988 SIS_CLRBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS); 1989 } 1990 1991 /* 1992 * Enable interrupts. 1993 */ 1994 CSR_WRITE_4(sc, SIS_IMR, SIS_INTRS); 1995 #ifdef DEVICE_POLLING 1996 /* 1997 * ... only enable interrupts if we are not polling, make sure 1998 * they are off otherwise. 1999 */ 2000 if (ifp->if_flags & IFF_POLLING) 2001 CSR_WRITE_4(sc, SIS_IER, 0); 2002 else 2003 #endif /* DEVICE_POLLING */ 2004 CSR_WRITE_4(sc, SIS_IER, 1); 2005 2006 /* Enable receiver and transmitter. */ 2007 SIS_CLRBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE|SIS_CSR_RX_DISABLE); 2008 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE); 2009 2010 #ifdef notdef 2011 mii_mediachg(mii); 2012 #endif 2013 2014 /* 2015 * Page 75 of the DP83815 manual recommends the 2016 * following register settings "for optimum 2017 * performance." Note however that at least three 2018 * of the registers are listed as "reserved" in 2019 * the register map, so who knows what they do. 2020 */ 2021 if (sc->sis_type == SIS_TYPE_83815) { 2022 CSR_WRITE_4(sc, NS_PHY_PAGE, 0x0001); 2023 CSR_WRITE_4(sc, NS_PHY_CR, 0x189C); 2024 CSR_WRITE_4(sc, NS_PHY_TDATA, 0x0000); 2025 CSR_WRITE_4(sc, NS_PHY_DSPCFG, 0x5040); 2026 CSR_WRITE_4(sc, NS_PHY_SDCFG, 0x008C); 2027 } 2028 2029 ifp->if_flags |= IFF_RUNNING; 2030 ifp->if_flags &= ~IFF_OACTIVE; 2031 2032 callout_reset(&sc->sis_timer, hz, sis_tick, sc); 2033 } 2034 2035 /* 2036 * Set media options. 2037 */ 2038 static int 2039 sis_ifmedia_upd(struct ifnet *ifp) 2040 { 2041 struct sis_softc *sc; 2042 struct mii_data *mii; 2043 2044 sc = ifp->if_softc; 2045 2046 mii = device_get_softc(sc->sis_miibus); 2047 sc->sis_link = 0; 2048 if (mii->mii_instance) { 2049 struct mii_softc *miisc; 2050 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 2051 mii_phy_reset(miisc); 2052 } 2053 mii_mediachg(mii); 2054 2055 return(0); 2056 } 2057 2058 /* 2059 * Report current media status. 2060 */ 2061 static void 2062 sis_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 2063 { 2064 struct sis_softc *sc; 2065 struct mii_data *mii; 2066 2067 sc = ifp->if_softc; 2068 2069 mii = device_get_softc(sc->sis_miibus); 2070 mii_pollstat(mii); 2071 ifmr->ifm_active = mii->mii_media_active; 2072 ifmr->ifm_status = mii->mii_media_status; 2073 } 2074 2075 static int 2076 sis_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr) 2077 { 2078 struct sis_softc *sc = ifp->if_softc; 2079 struct ifreq *ifr = (struct ifreq *) data; 2080 struct mii_data *mii; 2081 int error = 0; 2082 2083 switch(command) { 2084 case SIOCSIFFLAGS: 2085 if (ifp->if_flags & IFF_UP) { 2086 sis_init(sc); 2087 } else { 2088 if (ifp->if_flags & IFF_RUNNING) 2089 sis_stop(sc); 2090 } 2091 error = 0; 2092 break; 2093 case SIOCADDMULTI: 2094 case SIOCDELMULTI: 2095 if (sc->sis_type == SIS_TYPE_83815) 2096 sis_setmulti_ns(sc); 2097 else 2098 sis_setmulti_sis(sc); 2099 error = 0; 2100 break; 2101 case SIOCGIFMEDIA: 2102 case SIOCSIFMEDIA: 2103 mii = device_get_softc(sc->sis_miibus); 2104 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 2105 break; 2106 default: 2107 error = ether_ioctl(ifp, command, data); 2108 break; 2109 } 2110 return(error); 2111 } 2112 2113 static void 2114 sis_watchdog(struct ifnet *ifp) 2115 { 2116 struct sis_softc *sc; 2117 2118 sc = ifp->if_softc; 2119 2120 ifp->if_oerrors++; 2121 if_printf(ifp, "watchdog timeout\n"); 2122 2123 sis_stop(sc); 2124 sis_reset(sc); 2125 sis_init(sc); 2126 2127 if (!ifq_is_empty(&ifp->if_snd)) 2128 sis_start(ifp); 2129 } 2130 2131 /* 2132 * Stop the adapter and free any mbufs allocated to the 2133 * RX and TX lists. 2134 */ 2135 static void 2136 sis_stop(struct sis_softc *sc) 2137 { 2138 int i; 2139 struct ifnet *ifp; 2140 2141 ifp = &sc->arpcom.ac_if; 2142 ifp->if_timer = 0; 2143 2144 callout_stop(&sc->sis_timer); 2145 2146 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2147 CSR_WRITE_4(sc, SIS_IER, 0); 2148 CSR_WRITE_4(sc, SIS_IMR, 0); 2149 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE|SIS_CSR_RX_DISABLE); 2150 DELAY(1000); 2151 CSR_WRITE_4(sc, SIS_TX_LISTPTR, 0); 2152 CSR_WRITE_4(sc, SIS_RX_LISTPTR, 0); 2153 2154 sc->sis_link = 0; 2155 2156 /* 2157 * Free data in the RX lists. 2158 */ 2159 for (i = 0; i < SIS_RX_LIST_CNT; i++) { 2160 if (sc->sis_ldata.sis_rx_list[i].sis_mbuf != NULL) { 2161 bus_dmamap_unload(sc->sis_tag, 2162 sc->sis_ldata.sis_rx_list[i].sis_map); 2163 bus_dmamap_destroy(sc->sis_tag, 2164 sc->sis_ldata.sis_rx_list[i].sis_map); 2165 m_freem(sc->sis_ldata.sis_rx_list[i].sis_mbuf); 2166 sc->sis_ldata.sis_rx_list[i].sis_mbuf = NULL; 2167 } 2168 } 2169 bzero(sc->sis_ldata.sis_rx_list, sizeof(sc->sis_ldata.sis_rx_list)); 2170 2171 /* 2172 * Free the TX list buffers. 2173 */ 2174 for (i = 0; i < SIS_TX_LIST_CNT; i++) { 2175 if (sc->sis_ldata.sis_tx_list[i].sis_mbuf != NULL) { 2176 bus_dmamap_unload(sc->sis_tag, 2177 sc->sis_ldata.sis_tx_list[i].sis_map); 2178 bus_dmamap_destroy(sc->sis_tag, 2179 sc->sis_ldata.sis_tx_list[i].sis_map); 2180 m_freem(sc->sis_ldata.sis_tx_list[i].sis_mbuf); 2181 sc->sis_ldata.sis_tx_list[i].sis_mbuf = NULL; 2182 } 2183 } 2184 2185 bzero(sc->sis_ldata.sis_tx_list, sizeof(sc->sis_ldata.sis_tx_list)); 2186 } 2187 2188 /* 2189 * Stop all chip I/O so that the kernel's probe routines don't 2190 * get confused by errant DMAs when rebooting. 2191 */ 2192 static void 2193 sis_shutdown(device_t dev) 2194 { 2195 struct sis_softc *sc; 2196 struct ifnet *ifp; 2197 2198 sc = device_get_softc(dev); 2199 ifp = &sc->arpcom.ac_if; 2200 lwkt_serialize_enter(ifp->if_serializer); 2201 sis_reset(sc); 2202 sis_stop(sc); 2203 lwkt_serialize_exit(ifp->if_serializer); 2204 } 2205 2206