1 /* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: src/sys/pci/if_sis.c,v 1.13.4.24 2003/03/05 18:42:33 njl Exp $ 33 * $DragonFly: src/sys/dev/netif/sis/if_sis.c,v 1.24 2005/06/12 17:19:07 joerg Exp $ 34 */ 35 36 /* 37 * SiS 900/SiS 7016 fast ethernet PCI NIC driver. Datasheets are 38 * available from http://www.sis.com.tw. 39 * 40 * This driver also supports the NatSemi DP83815. Datasheets are 41 * available from http://www.national.com. 42 * 43 * Written by Bill Paul <wpaul@ee.columbia.edu> 44 * Electrical Engineering Department 45 * Columbia University, New York City 46 */ 47 48 /* 49 * The SiS 900 is a fairly simple chip. It uses bus master DMA with 50 * simple TX and RX descriptors of 3 longwords in size. The receiver 51 * has a single perfect filter entry for the station address and a 52 * 128-bit multicast hash table. The SiS 900 has a built-in MII-based 53 * transceiver while the 7016 requires an external transceiver chip. 54 * Both chips offer the standard bit-bang MII interface as well as 55 * an enchanced PHY interface which simplifies accessing MII registers. 56 * 57 * The only downside to this chipset is that RX descriptors must be 58 * longword aligned. 59 */ 60 61 #include <sys/param.h> 62 #include <sys/systm.h> 63 #include <sys/sockio.h> 64 #include <sys/mbuf.h> 65 #include <sys/malloc.h> 66 #include <sys/kernel.h> 67 #include <sys/socket.h> 68 #include <sys/sysctl.h> 69 #include <sys/thread2.h> 70 71 #include <net/if.h> 72 #include <net/ifq_var.h> 73 #include <net/if_arp.h> 74 #include <net/ethernet.h> 75 #include <net/if_dl.h> 76 #include <net/if_media.h> 77 #include <net/if_types.h> 78 #include <net/vlan/if_vlan_var.h> 79 80 #include <net/bpf.h> 81 82 #include <machine/bus_pio.h> 83 #include <machine/bus_memio.h> 84 #include <machine/bus.h> 85 #include <machine/resource.h> 86 #include <sys/bus.h> 87 #include <sys/rman.h> 88 89 #include <dev/netif/mii_layer/mii.h> 90 #include <dev/netif/mii_layer/miivar.h> 91 92 #include <bus/pci/pcireg.h> 93 #include <bus/pci/pcivar.h> 94 95 #define SIS_USEIOSPACE 96 97 #include "if_sisreg.h" 98 99 /* "controller miibus0" required. See GENERIC if you get errors here. */ 100 #include "miibus_if.h" 101 102 /* 103 * Various supported device vendors/types and their names. 104 */ 105 static struct sis_type sis_devs[] = { 106 { SIS_VENDORID, SIS_DEVICEID_900, "SiS 900 10/100BaseTX" }, 107 { SIS_VENDORID, SIS_DEVICEID_7016, "SiS 7016 10/100BaseTX" }, 108 { NS_VENDORID, NS_DEVICEID_DP83815, "NatSemi DP8381[56] 10/100BaseTX" }, 109 { 0, 0, NULL } 110 }; 111 112 static int sis_probe(device_t); 113 static int sis_attach(device_t); 114 static int sis_detach(device_t); 115 116 static int sis_newbuf(struct sis_softc *, struct sis_desc *, 117 struct mbuf *); 118 static int sis_encap(struct sis_softc *, struct mbuf *, uint32_t *); 119 static void sis_rxeof(struct sis_softc *); 120 static void sis_rxeoc(struct sis_softc *); 121 static void sis_txeof(struct sis_softc *); 122 static void sis_intr(void *); 123 static void sis_tick(void *); 124 static void sis_start(struct ifnet *); 125 static int sis_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *); 126 static void sis_init(void *); 127 static void sis_stop(struct sis_softc *); 128 static void sis_watchdog(struct ifnet *); 129 static void sis_shutdown(device_t); 130 static int sis_ifmedia_upd(struct ifnet *); 131 static void sis_ifmedia_sts(struct ifnet *, struct ifmediareq *); 132 133 static uint16_t sis_reverse(uint16_t); 134 static void sis_delay(struct sis_softc *); 135 static void sis_eeprom_idle(struct sis_softc *); 136 static void sis_eeprom_putbyte(struct sis_softc *, int); 137 static void sis_eeprom_getword(struct sis_softc *, int, uint16_t *); 138 static void sis_read_eeprom(struct sis_softc *, caddr_t, int, int, int); 139 #ifdef __i386__ 140 static void sis_read_cmos(struct sis_softc *, device_t, caddr_t, int, int); 141 static void sis_read_mac(struct sis_softc *, device_t, caddr_t); 142 static device_t sis_find_bridge(device_t); 143 #endif 144 145 static void sis_mii_sync(struct sis_softc *); 146 static void sis_mii_send(struct sis_softc *, uint32_t, int); 147 static int sis_mii_readreg(struct sis_softc *, struct sis_mii_frame *); 148 static int sis_mii_writereg(struct sis_softc *, struct sis_mii_frame *); 149 static int sis_miibus_readreg(device_t, int, int); 150 static int sis_miibus_writereg(device_t, int, int, int); 151 static void sis_miibus_statchg(device_t); 152 153 static void sis_setmulti_sis(struct sis_softc *); 154 static void sis_setmulti_ns(struct sis_softc *); 155 static uint32_t sis_mchash(struct sis_softc *, const uint8_t *); 156 static void sis_reset(struct sis_softc *); 157 static int sis_list_rx_init(struct sis_softc *); 158 static int sis_list_tx_init(struct sis_softc *); 159 160 static void sis_dma_map_desc_ptr(void *, bus_dma_segment_t *, int, int); 161 static void sis_dma_map_desc_next(void *, bus_dma_segment_t *, int, int); 162 static void sis_dma_map_ring(void *, bus_dma_segment_t *, int, int); 163 #ifdef DEVICE_POLLING 164 static poll_handler_t sis_poll; 165 #endif 166 #ifdef SIS_USEIOSPACE 167 #define SIS_RES SYS_RES_IOPORT 168 #define SIS_RID SIS_PCI_LOIO 169 #else 170 #define SIS_RES SYS_RES_MEMORY 171 #define SIS_RID SIS_PCI_LOMEM 172 #endif 173 174 static device_method_t sis_methods[] = { 175 /* Device interface */ 176 DEVMETHOD(device_probe, sis_probe), 177 DEVMETHOD(device_attach, sis_attach), 178 DEVMETHOD(device_detach, sis_detach), 179 DEVMETHOD(device_shutdown, sis_shutdown), 180 181 /* bus interface */ 182 DEVMETHOD(bus_print_child, bus_generic_print_child), 183 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 184 185 /* MII interface */ 186 DEVMETHOD(miibus_readreg, sis_miibus_readreg), 187 DEVMETHOD(miibus_writereg, sis_miibus_writereg), 188 DEVMETHOD(miibus_statchg, sis_miibus_statchg), 189 190 { 0, 0 } 191 }; 192 193 static driver_t sis_driver = { 194 "sis", 195 sis_methods, 196 sizeof(struct sis_softc) 197 }; 198 199 static devclass_t sis_devclass; 200 201 DECLARE_DUMMY_MODULE(if_sis); 202 DRIVER_MODULE(if_sis, pci, sis_driver, sis_devclass, 0, 0); 203 DRIVER_MODULE(miibus, sis, miibus_driver, miibus_devclass, 0, 0); 204 205 #define SIS_SETBIT(sc, reg, x) \ 206 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x)) 207 208 #define SIS_CLRBIT(sc, reg, x) \ 209 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x)) 210 211 #define SIO_SET(x) \ 212 CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) | x) 213 214 #define SIO_CLR(x) \ 215 CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) & ~x) 216 217 static void 218 sis_dma_map_desc_next(void *arg, bus_dma_segment_t *segs, int nseg, int error) 219 { 220 struct sis_desc *r; 221 222 r = arg; 223 r->sis_next = segs->ds_addr; 224 } 225 226 static void 227 sis_dma_map_desc_ptr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 228 { 229 struct sis_desc *r; 230 231 r = arg; 232 r->sis_ptr = segs->ds_addr; 233 } 234 235 static void 236 sis_dma_map_ring(void *arg, bus_dma_segment_t *segs, int nseg, int error) 237 { 238 uint32_t *p; 239 240 p = arg; 241 *p = segs->ds_addr; 242 } 243 244 /* 245 * Routine to reverse the bits in a word. Stolen almost 246 * verbatim from /usr/games/fortune. 247 */ 248 static uint16_t 249 sis_reverse(uint16_t n) 250 { 251 n = ((n >> 1) & 0x5555) | ((n << 1) & 0xaaaa); 252 n = ((n >> 2) & 0x3333) | ((n << 2) & 0xcccc); 253 n = ((n >> 4) & 0x0f0f) | ((n << 4) & 0xf0f0); 254 n = ((n >> 8) & 0x00ff) | ((n << 8) & 0xff00); 255 256 return(n); 257 } 258 259 static void 260 sis_delay(struct sis_softc *sc) 261 { 262 int idx; 263 264 for (idx = (300 / 33) + 1; idx > 0; idx--) 265 CSR_READ_4(sc, SIS_CSR); 266 } 267 268 static void 269 sis_eeprom_idle(struct sis_softc *sc) 270 { 271 int i; 272 273 SIO_SET(SIS_EECTL_CSEL); 274 sis_delay(sc); 275 SIO_SET(SIS_EECTL_CLK); 276 sis_delay(sc); 277 278 for (i = 0; i < 25; i++) { 279 SIO_CLR(SIS_EECTL_CLK); 280 sis_delay(sc); 281 SIO_SET(SIS_EECTL_CLK); 282 sis_delay(sc); 283 } 284 285 SIO_CLR(SIS_EECTL_CLK); 286 sis_delay(sc); 287 SIO_CLR(SIS_EECTL_CSEL); 288 sis_delay(sc); 289 CSR_WRITE_4(sc, SIS_EECTL, 0x00000000); 290 } 291 292 /* 293 * Send a read command and address to the EEPROM, check for ACK. 294 */ 295 static void 296 sis_eeprom_putbyte(struct sis_softc *sc, int addr) 297 { 298 int d, i; 299 300 d = addr | SIS_EECMD_READ; 301 302 /* 303 * Feed in each bit and stobe the clock. 304 */ 305 for (i = 0x400; i; i >>= 1) { 306 if (d & i) 307 SIO_SET(SIS_EECTL_DIN); 308 else 309 SIO_CLR(SIS_EECTL_DIN); 310 sis_delay(sc); 311 SIO_SET(SIS_EECTL_CLK); 312 sis_delay(sc); 313 SIO_CLR(SIS_EECTL_CLK); 314 sis_delay(sc); 315 } 316 } 317 318 /* 319 * Read a word of data stored in the EEPROM at address 'addr.' 320 */ 321 static void 322 sis_eeprom_getword(struct sis_softc *sc, int addr, uint16_t *dest) 323 { 324 int i; 325 uint16_t word = 0; 326 327 /* Force EEPROM to idle state. */ 328 sis_eeprom_idle(sc); 329 330 /* Enter EEPROM access mode. */ 331 sis_delay(sc); 332 SIO_CLR(SIS_EECTL_CLK); 333 sis_delay(sc); 334 SIO_SET(SIS_EECTL_CSEL); 335 sis_delay(sc); 336 337 /* 338 * Send address of word we want to read. 339 */ 340 sis_eeprom_putbyte(sc, addr); 341 342 /* 343 * Start reading bits from EEPROM. 344 */ 345 for (i = 0x8000; i; i >>= 1) { 346 SIO_SET(SIS_EECTL_CLK); 347 sis_delay(sc); 348 if (CSR_READ_4(sc, SIS_EECTL) & SIS_EECTL_DOUT) 349 word |= i; 350 sis_delay(sc); 351 SIO_CLR(SIS_EECTL_CLK); 352 sis_delay(sc); 353 } 354 355 /* Turn off EEPROM access mode. */ 356 sis_eeprom_idle(sc); 357 358 *dest = word; 359 } 360 361 /* 362 * Read a sequence of words from the EEPROM. 363 */ 364 static void 365 sis_read_eeprom(struct sis_softc *sc, caddr_t dest, int off, int cnt, int swap) 366 { 367 int i; 368 uint16_t word = 0, *ptr; 369 370 for (i = 0; i < cnt; i++) { 371 sis_eeprom_getword(sc, off + i, &word); 372 ptr = (uint16_t *)(dest + (i * 2)); 373 if (swap) 374 *ptr = ntohs(word); 375 else 376 *ptr = word; 377 } 378 } 379 380 #ifdef __i386__ 381 static device_t 382 sis_find_bridge(device_t dev) 383 { 384 devclass_t pci_devclass; 385 device_t *pci_devices; 386 int pci_count = 0; 387 device_t *pci_children; 388 int pci_childcount = 0; 389 device_t *busp, *childp; 390 device_t child = NULL; 391 int i, j; 392 393 if ((pci_devclass = devclass_find("pci")) == NULL) 394 return(NULL); 395 396 devclass_get_devices(pci_devclass, &pci_devices, &pci_count); 397 398 for (i = 0, busp = pci_devices; i < pci_count; i++, busp++) { 399 pci_childcount = 0; 400 device_get_children(*busp, &pci_children, &pci_childcount); 401 for (j = 0, childp = pci_children; j < pci_childcount; 402 j++, childp++) { 403 if (pci_get_vendor(*childp) == SIS_VENDORID && 404 pci_get_device(*childp) == 0x0008) { 405 child = *childp; 406 goto done; 407 } 408 } 409 } 410 411 done: 412 free(pci_devices, M_TEMP); 413 free(pci_children, M_TEMP); 414 return(child); 415 } 416 417 static void 418 sis_read_cmos(struct sis_softc *sc, device_t dev, caddr_t dest, int off, 419 int cnt) 420 { 421 device_t bridge; 422 uint8_t reg; 423 int i; 424 bus_space_tag_t btag; 425 426 bridge = sis_find_bridge(dev); 427 if (bridge == NULL) 428 return; 429 reg = pci_read_config(bridge, 0x48, 1); 430 pci_write_config(bridge, 0x48, reg|0x40, 1); 431 432 /* XXX */ 433 btag = I386_BUS_SPACE_IO; 434 435 for (i = 0; i < cnt; i++) { 436 bus_space_write_1(btag, 0x0, 0x70, i + off); 437 *(dest + i) = bus_space_read_1(btag, 0x0, 0x71); 438 } 439 440 pci_write_config(bridge, 0x48, reg & ~0x40, 1); 441 } 442 443 static void 444 sis_read_mac(struct sis_softc *sc, device_t dev, caddr_t dest) 445 { 446 uint32_t filtsave, csrsave; 447 448 filtsave = CSR_READ_4(sc, SIS_RXFILT_CTL); 449 csrsave = CSR_READ_4(sc, SIS_CSR); 450 451 CSR_WRITE_4(sc, SIS_CSR, SIS_CSR_RELOAD | filtsave); 452 CSR_WRITE_4(sc, SIS_CSR, 0); 453 454 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave & ~SIS_RXFILTCTL_ENABLE); 455 456 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR0); 457 ((uint16_t *)dest)[0] = CSR_READ_2(sc, SIS_RXFILT_DATA); 458 CSR_WRITE_4(sc, SIS_RXFILT_CTL,SIS_FILTADDR_PAR1); 459 ((uint16_t *)dest)[1] = CSR_READ_2(sc, SIS_RXFILT_DATA); 460 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR2); 461 ((uint16_t *)dest)[2] = CSR_READ_2(sc, SIS_RXFILT_DATA); 462 463 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave); 464 CSR_WRITE_4(sc, SIS_CSR, csrsave); 465 } 466 #endif 467 468 /* 469 * Sync the PHYs by setting data bit and strobing the clock 32 times. 470 */ 471 static void 472 sis_mii_sync(struct sis_softc *sc) 473 { 474 int i; 475 476 SIO_SET(SIS_MII_DIR|SIS_MII_DATA); 477 478 for (i = 0; i < 32; i++) { 479 SIO_SET(SIS_MII_CLK); 480 DELAY(1); 481 SIO_CLR(SIS_MII_CLK); 482 DELAY(1); 483 } 484 } 485 486 /* 487 * Clock a series of bits through the MII. 488 */ 489 static void 490 sis_mii_send(struct sis_softc *sc, uint32_t bits, int cnt) 491 { 492 int i; 493 494 SIO_CLR(SIS_MII_CLK); 495 496 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 497 if (bits & i) 498 SIO_SET(SIS_MII_DATA); 499 else 500 SIO_CLR(SIS_MII_DATA); 501 DELAY(1); 502 SIO_CLR(SIS_MII_CLK); 503 DELAY(1); 504 SIO_SET(SIS_MII_CLK); 505 } 506 } 507 508 /* 509 * Read an PHY register through the MII. 510 */ 511 static int 512 sis_mii_readreg(struct sis_softc *sc, struct sis_mii_frame *frame) 513 { 514 int i, ack; 515 516 crit_enter(); 517 518 /* 519 * Set up frame for RX. 520 */ 521 frame->mii_stdelim = SIS_MII_STARTDELIM; 522 frame->mii_opcode = SIS_MII_READOP; 523 frame->mii_turnaround = 0; 524 frame->mii_data = 0; 525 526 /* 527 * Turn on data xmit. 528 */ 529 SIO_SET(SIS_MII_DIR); 530 531 sis_mii_sync(sc); 532 533 /* 534 * Send command/address info. 535 */ 536 sis_mii_send(sc, frame->mii_stdelim, 2); 537 sis_mii_send(sc, frame->mii_opcode, 2); 538 sis_mii_send(sc, frame->mii_phyaddr, 5); 539 sis_mii_send(sc, frame->mii_regaddr, 5); 540 541 /* Idle bit */ 542 SIO_CLR((SIS_MII_CLK|SIS_MII_DATA)); 543 DELAY(1); 544 SIO_SET(SIS_MII_CLK); 545 DELAY(1); 546 547 /* Turn off xmit. */ 548 SIO_CLR(SIS_MII_DIR); 549 550 /* Check for ack */ 551 SIO_CLR(SIS_MII_CLK); 552 DELAY(1); 553 ack = CSR_READ_4(sc, SIS_EECTL) & SIS_MII_DATA; 554 SIO_SET(SIS_MII_CLK); 555 DELAY(1); 556 557 /* 558 * Now try reading data bits. If the ack failed, we still 559 * need to clock through 16 cycles to keep the PHY(s) in sync. 560 */ 561 if (ack) { 562 for(i = 0; i < 16; i++) { 563 SIO_CLR(SIS_MII_CLK); 564 DELAY(1); 565 SIO_SET(SIS_MII_CLK); 566 DELAY(1); 567 } 568 goto fail; 569 } 570 571 for (i = 0x8000; i; i >>= 1) { 572 SIO_CLR(SIS_MII_CLK); 573 DELAY(1); 574 if (!ack) { 575 if (CSR_READ_4(sc, SIS_EECTL) & SIS_MII_DATA) 576 frame->mii_data |= i; 577 DELAY(1); 578 } 579 SIO_SET(SIS_MII_CLK); 580 DELAY(1); 581 } 582 583 fail: 584 585 SIO_CLR(SIS_MII_CLK); 586 DELAY(1); 587 SIO_SET(SIS_MII_CLK); 588 DELAY(1); 589 590 crit_exit(); 591 592 if (ack) 593 return(1); 594 return(0); 595 } 596 597 /* 598 * Write to a PHY register through the MII. 599 */ 600 static int 601 sis_mii_writereg(struct sis_softc *sc, struct sis_mii_frame *frame) 602 { 603 crit_enter(); 604 605 /* 606 * Set up frame for TX. 607 */ 608 609 frame->mii_stdelim = SIS_MII_STARTDELIM; 610 frame->mii_opcode = SIS_MII_WRITEOP; 611 frame->mii_turnaround = SIS_MII_TURNAROUND; 612 613 /* 614 * Turn on data output. 615 */ 616 SIO_SET(SIS_MII_DIR); 617 618 sis_mii_sync(sc); 619 620 sis_mii_send(sc, frame->mii_stdelim, 2); 621 sis_mii_send(sc, frame->mii_opcode, 2); 622 sis_mii_send(sc, frame->mii_phyaddr, 5); 623 sis_mii_send(sc, frame->mii_regaddr, 5); 624 sis_mii_send(sc, frame->mii_turnaround, 2); 625 sis_mii_send(sc, frame->mii_data, 16); 626 627 /* Idle bit. */ 628 SIO_SET(SIS_MII_CLK); 629 DELAY(1); 630 SIO_CLR(SIS_MII_CLK); 631 DELAY(1); 632 633 /* 634 * Turn off xmit. 635 */ 636 SIO_CLR(SIS_MII_DIR); 637 638 crit_exit(); 639 640 return(0); 641 } 642 643 static int 644 sis_miibus_readreg(device_t dev, int phy, int reg) 645 { 646 struct sis_softc *sc; 647 struct sis_mii_frame frame; 648 649 sc = device_get_softc(dev); 650 651 if (sc->sis_type == SIS_TYPE_83815) { 652 if (phy != 0) 653 return(0); 654 /* 655 * The NatSemi chip can take a while after 656 * a reset to come ready, during which the BMSR 657 * returns a value of 0. This is *never* supposed 658 * to happen: some of the BMSR bits are meant to 659 * be hardwired in the on position, and this can 660 * confuse the miibus code a bit during the probe 661 * and attach phase. So we make an effort to check 662 * for this condition and wait for it to clear. 663 */ 664 if (!CSR_READ_4(sc, NS_BMSR)) 665 DELAY(1000); 666 return CSR_READ_4(sc, NS_BMCR + (reg * 4)); 667 } 668 /* 669 * Chipsets < SIS_635 seem not to be able to read/write 670 * through mdio. Use the enhanced PHY access register 671 * again for them. 672 */ 673 if (sc->sis_type == SIS_TYPE_900 && 674 sc->sis_rev < SIS_REV_635) { 675 int i, val = 0; 676 677 if (phy != 0) 678 return(0); 679 680 CSR_WRITE_4(sc, SIS_PHYCTL, 681 (phy << 11) | (reg << 6) | SIS_PHYOP_READ); 682 SIS_SETBIT(sc, SIS_PHYCTL, SIS_PHYCTL_ACCESS); 683 684 for (i = 0; i < SIS_TIMEOUT; i++) { 685 if (!(CSR_READ_4(sc, SIS_PHYCTL) & SIS_PHYCTL_ACCESS)) 686 break; 687 } 688 689 if (i == SIS_TIMEOUT) { 690 device_printf(dev, "PHY failed to come ready\n"); 691 return(0); 692 } 693 694 val = (CSR_READ_4(sc, SIS_PHYCTL) >> 16) & 0xFFFF; 695 696 if (val == 0xFFFF) 697 return(0); 698 699 return(val); 700 } else { 701 bzero((char *)&frame, sizeof(frame)); 702 703 frame.mii_phyaddr = phy; 704 frame.mii_regaddr = reg; 705 sis_mii_readreg(sc, &frame); 706 707 return(frame.mii_data); 708 } 709 } 710 711 static int 712 sis_miibus_writereg(device_t dev, int phy, int reg, int data) 713 { 714 struct sis_softc *sc; 715 struct sis_mii_frame frame; 716 717 sc = device_get_softc(dev); 718 719 if (sc->sis_type == SIS_TYPE_83815) { 720 if (phy != 0) 721 return(0); 722 CSR_WRITE_4(sc, NS_BMCR + (reg * 4), data); 723 return(0); 724 } 725 726 if (sc->sis_type == SIS_TYPE_900 && 727 sc->sis_rev < SIS_REV_635) { 728 int i; 729 730 if (phy != 0) 731 return(0); 732 733 CSR_WRITE_4(sc, SIS_PHYCTL, (data << 16) | (phy << 11) | 734 (reg << 6) | SIS_PHYOP_WRITE); 735 SIS_SETBIT(sc, SIS_PHYCTL, SIS_PHYCTL_ACCESS); 736 737 for (i = 0; i < SIS_TIMEOUT; i++) { 738 if (!(CSR_READ_4(sc, SIS_PHYCTL) & SIS_PHYCTL_ACCESS)) 739 break; 740 } 741 742 if (i == SIS_TIMEOUT) 743 device_printf(dev, "PHY failed to come ready\n"); 744 } else { 745 bzero((char *)&frame, sizeof(frame)); 746 747 frame.mii_phyaddr = phy; 748 frame.mii_regaddr = reg; 749 frame.mii_data = data; 750 sis_mii_writereg(sc, &frame); 751 } 752 return(0); 753 } 754 755 static void sis_miibus_statchg(device_t dev) 756 { 757 struct sis_softc *sc; 758 759 sc = device_get_softc(dev); 760 sis_init(sc); 761 } 762 763 static uint32_t 764 sis_mchash(struct sis_softc *sc, const uint8_t *addr) 765 { 766 uint32_t crc, carry; 767 int i, j; 768 uint8_t c; 769 770 /* Compute CRC for the address value. */ 771 crc = 0xFFFFFFFF; /* initial value */ 772 773 for (i = 0; i < 6; i++) { 774 c = *(addr + i); 775 for (j = 0; j < 8; j++) { 776 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 777 crc <<= 1; 778 c >>= 1; 779 if (carry) 780 crc = (crc ^ 0x04c11db6) | carry; 781 } 782 } 783 784 /* 785 * return the filter bit position 786 * 787 * The NatSemi chip has a 512-bit filter, which is 788 * different than the SiS, so we special-case it. 789 */ 790 if (sc->sis_type == SIS_TYPE_83815) 791 return (crc >> 23); 792 else if (sc->sis_rev >= SIS_REV_635 || sc->sis_rev == SIS_REV_900B) 793 return (crc >> 24); 794 else 795 return (crc >> 25); 796 } 797 798 static void 799 sis_setmulti_ns(struct sis_softc *sc) 800 { 801 struct ifnet *ifp; 802 struct ifmultiaddr *ifma; 803 uint32_t h = 0, i, filtsave; 804 int bit, index; 805 806 ifp = &sc->arpcom.ac_if; 807 808 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 809 SIS_CLRBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_MCHASH); 810 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLMULTI); 811 return; 812 } 813 814 /* 815 * We have to explicitly enable the multicast hash table 816 * on the NatSemi chip if we want to use it, which we do. 817 */ 818 SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_MCHASH); 819 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLMULTI); 820 821 filtsave = CSR_READ_4(sc, SIS_RXFILT_CTL); 822 823 /* first, zot all the existing hash bits */ 824 for (i = 0; i < 32; i++) { 825 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_FMEM_LO + (i*2)); 826 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 0); 827 } 828 829 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 830 if (ifma->ifma_addr->sa_family != AF_LINK) 831 continue; 832 h = sis_mchash(sc, 833 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 834 index = h >> 3; 835 bit = h & 0x1F; 836 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_FMEM_LO + index); 837 if (bit > 0xF) 838 bit -= 0x10; 839 SIS_SETBIT(sc, SIS_RXFILT_DATA, (1 << bit)); 840 } 841 842 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave); 843 } 844 845 static void 846 sis_setmulti_sis(struct sis_softc *sc) 847 { 848 struct ifnet *ifp; 849 struct ifmultiaddr *ifma; 850 uint32_t h, i, n, ctl; 851 uint16_t hashes[16]; 852 853 ifp = &sc->arpcom.ac_if; 854 855 /* hash table size */ 856 if (sc->sis_rev >= SIS_REV_635 || sc->sis_rev == SIS_REV_900B) 857 n = 16; 858 else 859 n = 8; 860 861 ctl = CSR_READ_4(sc, SIS_RXFILT_CTL) & SIS_RXFILTCTL_ENABLE; 862 863 if (ifp->if_flags & IFF_BROADCAST) 864 ctl |= SIS_RXFILTCTL_BROAD; 865 866 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 867 ctl |= SIS_RXFILTCTL_ALLMULTI; 868 if (ifp->if_flags & IFF_PROMISC) 869 ctl |= SIS_RXFILTCTL_BROAD|SIS_RXFILTCTL_ALLPHYS; 870 for (i = 0; i < n; i++) 871 hashes[i] = ~0; 872 } else { 873 for (i = 0; i < n; i++) 874 hashes[i] = 0; 875 i = 0; 876 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 877 if (ifma->ifma_addr->sa_family != AF_LINK) 878 continue; 879 h = sis_mchash(sc, 880 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 881 hashes[h >> 4] |= 1 << (h & 0xf); 882 i++; 883 } 884 if (i > n) { 885 ctl |= SIS_RXFILTCTL_ALLMULTI; 886 for (i = 0; i < n; i++) 887 hashes[i] = ~0; 888 } 889 } 890 891 for (i = 0; i < n; i++) { 892 CSR_WRITE_4(sc, SIS_RXFILT_CTL, (4 + i) << 16); 893 CSR_WRITE_4(sc, SIS_RXFILT_DATA, hashes[i]); 894 } 895 896 CSR_WRITE_4(sc, SIS_RXFILT_CTL, ctl); 897 } 898 899 static void 900 sis_reset(struct sis_softc *sc) 901 { 902 struct ifnet *ifp = &sc->arpcom.ac_if; 903 int i; 904 905 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RESET); 906 907 for (i = 0; i < SIS_TIMEOUT; i++) { 908 if (!(CSR_READ_4(sc, SIS_CSR) & SIS_CSR_RESET)) 909 break; 910 } 911 912 if (i == SIS_TIMEOUT) 913 if_printf(ifp, "reset never completed\n"); 914 915 /* Wait a little while for the chip to get its brains in order. */ 916 DELAY(1000); 917 918 /* 919 * If this is a NetSemi chip, make sure to clear 920 * PME mode. 921 */ 922 if (sc->sis_type == SIS_TYPE_83815) { 923 CSR_WRITE_4(sc, NS_CLKRUN, NS_CLKRUN_PMESTS); 924 CSR_WRITE_4(sc, NS_CLKRUN, 0); 925 } 926 } 927 928 /* 929 * Probe for an SiS chip. Check the PCI vendor and device 930 * IDs against our list and return a device name if we find a match. 931 */ 932 static int 933 sis_probe(device_t dev) 934 { 935 struct sis_type *t; 936 937 t = sis_devs; 938 939 while(t->sis_name != NULL) { 940 if ((pci_get_vendor(dev) == t->sis_vid) && 941 (pci_get_device(dev) == t->sis_did)) { 942 device_set_desc(dev, t->sis_name); 943 return(0); 944 } 945 t++; 946 } 947 948 return(ENXIO); 949 } 950 951 /* 952 * Attach the interface. Allocate softc structures, do ifmedia 953 * setup and ethernet/BPF attach. 954 */ 955 static int 956 sis_attach(device_t dev) 957 { 958 uint8_t eaddr[ETHER_ADDR_LEN]; 959 uint32_t command; 960 struct sis_softc *sc; 961 struct ifnet *ifp; 962 int error, rid, waittime; 963 964 error = waittime = 0; 965 sc = device_get_softc(dev); 966 bzero(sc, sizeof(struct sis_softc)); 967 968 if (pci_get_device(dev) == SIS_DEVICEID_900) 969 sc->sis_type = SIS_TYPE_900; 970 if (pci_get_device(dev) == SIS_DEVICEID_7016) 971 sc->sis_type = SIS_TYPE_7016; 972 if (pci_get_vendor(dev) == NS_VENDORID) 973 sc->sis_type = SIS_TYPE_83815; 974 975 sc->sis_rev = pci_read_config(dev, PCIR_REVID, 1); 976 977 /* 978 * Handle power management nonsense. 979 */ 980 981 command = pci_read_config(dev, SIS_PCI_CAPID, 4) & 0x000000FF; 982 if (command == 0x01) { 983 984 command = pci_read_config(dev, SIS_PCI_PWRMGMTCTRL, 4); 985 if (command & SIS_PSTATE_MASK) { 986 uint32_t iobase, membase, irq; 987 988 /* Save important PCI config data. */ 989 iobase = pci_read_config(dev, SIS_PCI_LOIO, 4); 990 membase = pci_read_config(dev, SIS_PCI_LOMEM, 4); 991 irq = pci_read_config(dev, SIS_PCI_INTLINE, 4); 992 993 /* Reset the power state. */ 994 device_printf(dev, "chip is in D%d power mode " 995 "-- setting to D0\n", command & SIS_PSTATE_MASK); 996 command &= 0xFFFFFFFC; 997 pci_write_config(dev, SIS_PCI_PWRMGMTCTRL, command, 4); 998 999 /* Restore PCI config data. */ 1000 pci_write_config(dev, SIS_PCI_LOIO, iobase, 4); 1001 pci_write_config(dev, SIS_PCI_LOMEM, membase, 4); 1002 pci_write_config(dev, SIS_PCI_INTLINE, irq, 4); 1003 } 1004 } 1005 1006 /* 1007 * Map control/status registers. 1008 */ 1009 command = pci_read_config(dev, PCIR_COMMAND, 4); 1010 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 1011 pci_write_config(dev, PCIR_COMMAND, command, 4); 1012 command = pci_read_config(dev, PCIR_COMMAND, 4); 1013 1014 #ifdef SIS_USEIOSPACE 1015 if (!(command & PCIM_CMD_PORTEN)) { 1016 device_printf(dev, "failed to enable I/O ports!\n"); 1017 error = ENXIO;; 1018 goto fail; 1019 } 1020 #else 1021 if (!(command & PCIM_CMD_MEMEN)) { 1022 device_printf(dev, "failed to enable memory mapping!\n"); 1023 error = ENXIO;; 1024 goto fail; 1025 } 1026 #endif 1027 1028 rid = SIS_RID; 1029 sc->sis_res = bus_alloc_resource_any(dev, SIS_RES, &rid, RF_ACTIVE); 1030 1031 if (sc->sis_res == NULL) { 1032 device_printf(dev, "couldn't map ports/memory\n"); 1033 error = ENXIO; 1034 goto fail; 1035 } 1036 1037 sc->sis_btag = rman_get_bustag(sc->sis_res); 1038 sc->sis_bhandle = rman_get_bushandle(sc->sis_res); 1039 1040 /* Allocate interrupt */ 1041 rid = 0; 1042 sc->sis_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1043 RF_SHAREABLE | RF_ACTIVE); 1044 1045 if (sc->sis_irq == NULL) { 1046 device_printf(dev, "couldn't map interrupt\n"); 1047 error = ENXIO; 1048 goto fail; 1049 } 1050 1051 /* Reset the adapter. */ 1052 sis_reset(sc); 1053 1054 if (sc->sis_type == SIS_TYPE_900 && 1055 (sc->sis_rev == SIS_REV_635 || 1056 sc->sis_rev == SIS_REV_900B)) { 1057 SIO_SET(SIS_CFG_RND_CNT); 1058 SIO_SET(SIS_CFG_PERR_DETECT); 1059 } 1060 1061 /* 1062 * Get station address from the EEPROM. 1063 */ 1064 switch (pci_get_vendor(dev)) { 1065 case NS_VENDORID: 1066 /* 1067 * Reading the MAC address out of the EEPROM on 1068 * the NatSemi chip takes a bit more work than 1069 * you'd expect. The address spans 4 16-bit words, 1070 * with the first word containing only a single bit. 1071 * You have to shift everything over one bit to 1072 * get it aligned properly. Also, the bits are 1073 * stored backwards (the LSB is really the MSB, 1074 * and so on) so you have to reverse them in order 1075 * to get the MAC address into the form we want. 1076 * Why? Who the hell knows. 1077 */ 1078 { 1079 uint16_t tmp[4]; 1080 1081 sis_read_eeprom(sc, (caddr_t)&tmp, 1082 NS_EE_NODEADDR, 4, 0); 1083 1084 /* Shift everything over one bit. */ 1085 tmp[3] = tmp[3] >> 1; 1086 tmp[3] |= tmp[2] << 15; 1087 tmp[2] = tmp[2] >> 1; 1088 tmp[2] |= tmp[1] << 15; 1089 tmp[1] = tmp[1] >> 1; 1090 tmp[1] |= tmp[0] << 15; 1091 1092 /* Now reverse all the bits. */ 1093 tmp[3] = sis_reverse(tmp[3]); 1094 tmp[2] = sis_reverse(tmp[2]); 1095 tmp[1] = sis_reverse(tmp[1]); 1096 1097 bcopy((char *)&tmp[1], eaddr, ETHER_ADDR_LEN); 1098 } 1099 break; 1100 case SIS_VENDORID: 1101 default: 1102 #ifdef __i386__ 1103 /* 1104 * If this is a SiS 630E chipset with an embedded 1105 * SiS 900 controller, we have to read the MAC address 1106 * from the APC CMOS RAM. Our method for doing this 1107 * is very ugly since we have to reach out and grab 1108 * ahold of hardware for which we cannot properly 1109 * allocate resources. This code is only compiled on 1110 * the i386 architecture since the SiS 630E chipset 1111 * is for x86 motherboards only. Note that there are 1112 * a lot of magic numbers in this hack. These are 1113 * taken from SiS's Linux driver. I'd like to replace 1114 * them with proper symbolic definitions, but that 1115 * requires some datasheets that I don't have access 1116 * to at the moment. 1117 */ 1118 if (sc->sis_rev == SIS_REV_630S || 1119 sc->sis_rev == SIS_REV_630E || 1120 sc->sis_rev == SIS_REV_630EA1) 1121 sis_read_cmos(sc, dev, (caddr_t)&eaddr, 0x9, 6); 1122 1123 else if (sc->sis_rev == SIS_REV_635 || 1124 sc->sis_rev == SIS_REV_630ET) 1125 sis_read_mac(sc, dev, (caddr_t)&eaddr); 1126 else if (sc->sis_rev == SIS_REV_96x) { 1127 /* 1128 * Allow to read EEPROM from LAN. It is shared 1129 * between a 1394 controller and the NIC and each 1130 * time we access it, we need to set SIS_EECMD_REQ. 1131 */ 1132 SIO_SET(SIS_EECMD_REQ); 1133 for (waittime = 0; waittime < SIS_TIMEOUT; 1134 waittime++) { 1135 /* Force EEPROM to idle state. */ 1136 sis_eeprom_idle(sc); 1137 if (CSR_READ_4(sc, SIS_EECTL) & SIS_EECMD_GNT) { 1138 sis_read_eeprom(sc, (caddr_t)&eaddr, 1139 SIS_EE_NODEADDR, 3, 0); 1140 break; 1141 } 1142 DELAY(1); 1143 } 1144 /* 1145 * Set SIS_EECTL_CLK to high, so a other master 1146 * can operate on the i2c bus. 1147 */ 1148 SIO_SET(SIS_EECTL_CLK); 1149 /* Refuse EEPROM access by LAN */ 1150 SIO_SET(SIS_EECMD_DONE); 1151 } else 1152 #endif 1153 sis_read_eeprom(sc, (caddr_t)&eaddr, 1154 SIS_EE_NODEADDR, 3, 0); 1155 break; 1156 } 1157 1158 callout_init(&sc->sis_timer); 1159 1160 /* 1161 * Allocate the parent bus DMA tag appropriate for PCI. 1162 */ 1163 #define SIS_NSEG_NEW 32 1164 error = bus_dma_tag_create(NULL, /* parent */ 1165 1, 0, /* alignment, boundary */ 1166 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */ 1167 BUS_SPACE_MAXADDR, /* highaddr */ 1168 NULL, NULL, /* filter, filterarg */ 1169 MAXBSIZE, SIS_NSEG_NEW, /* maxsize, nsegments */ 1170 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1171 BUS_DMA_ALLOCNOW, /* flags */ 1172 &sc->sis_parent_tag); 1173 if (error) 1174 goto fail; 1175 1176 /* 1177 * Now allocate a tag for the DMA descriptor lists and a chunk 1178 * of DMA-able memory based on the tag. Also obtain the physical 1179 * addresses of the RX and TX ring, which we'll need later. 1180 * All of our lists are allocated as a contiguous block of memory. 1181 */ 1182 error = bus_dma_tag_create(sc->sis_parent_tag, /* parent */ 1183 1, 0, /* alignment, boundary */ 1184 BUS_SPACE_MAXADDR, /* lowaddr */ 1185 BUS_SPACE_MAXADDR, /* highaddr */ 1186 NULL, NULL, /* filter, filterarg */ 1187 SIS_RX_LIST_SZ, 1, /* maxsize, nsegments */ 1188 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1189 0, /* flags */ 1190 &sc->sis_ldata.sis_rx_tag); 1191 if (error) 1192 goto fail; 1193 1194 error = bus_dmamem_alloc(sc->sis_ldata.sis_rx_tag, 1195 (void **)&sc->sis_ldata.sis_rx_list, 1196 BUS_DMA_WAITOK | BUS_DMA_ZERO, 1197 &sc->sis_ldata.sis_rx_dmamap); 1198 1199 if (error) { 1200 device_printf(dev, "no memory for rx list buffers!\n"); 1201 bus_dma_tag_destroy(sc->sis_ldata.sis_rx_tag); 1202 sc->sis_ldata.sis_rx_tag = NULL; 1203 goto fail; 1204 } 1205 1206 error = bus_dmamap_load(sc->sis_ldata.sis_rx_tag, 1207 sc->sis_ldata.sis_rx_dmamap, 1208 sc->sis_ldata.sis_rx_list, 1209 sizeof(struct sis_desc), sis_dma_map_ring, 1210 &sc->sis_cdata.sis_rx_paddr, 0); 1211 1212 if (error) { 1213 device_printf(dev, "cannot get address of the rx ring!\n"); 1214 bus_dmamem_free(sc->sis_ldata.sis_rx_tag, 1215 sc->sis_ldata.sis_rx_list, 1216 sc->sis_ldata.sis_rx_dmamap); 1217 bus_dma_tag_destroy(sc->sis_ldata.sis_rx_tag); 1218 sc->sis_ldata.sis_rx_tag = NULL; 1219 goto fail; 1220 } 1221 1222 error = bus_dma_tag_create(sc->sis_parent_tag, /* parent */ 1223 1, 0, /* alignment, boundary */ 1224 BUS_SPACE_MAXADDR, /* lowaddr */ 1225 BUS_SPACE_MAXADDR, /* highaddr */ 1226 NULL, NULL, /* filter, filterarg */ 1227 SIS_TX_LIST_SZ, 1, /* maxsize, nsegments */ 1228 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1229 0, /* flags */ 1230 &sc->sis_ldata.sis_tx_tag); 1231 if (error) 1232 goto fail; 1233 1234 error = bus_dmamem_alloc(sc->sis_ldata.sis_tx_tag, 1235 (void **)&sc->sis_ldata.sis_tx_list, 1236 BUS_DMA_WAITOK | BUS_DMA_ZERO, 1237 &sc->sis_ldata.sis_tx_dmamap); 1238 1239 if (error) { 1240 device_printf(dev, "no memory for tx list buffers!\n"); 1241 bus_dma_tag_destroy(sc->sis_ldata.sis_tx_tag); 1242 sc->sis_ldata.sis_tx_tag = NULL; 1243 goto fail; 1244 } 1245 1246 error = bus_dmamap_load(sc->sis_ldata.sis_tx_tag, 1247 sc->sis_ldata.sis_tx_dmamap, 1248 sc->sis_ldata.sis_tx_list, 1249 sizeof(struct sis_desc), sis_dma_map_ring, 1250 &sc->sis_cdata.sis_tx_paddr, 0); 1251 1252 if (error) { 1253 device_printf(dev, "cannot get address of the tx ring!\n"); 1254 bus_dmamem_free(sc->sis_ldata.sis_tx_tag, 1255 sc->sis_ldata.sis_tx_list, 1256 sc->sis_ldata.sis_tx_dmamap); 1257 bus_dma_tag_destroy(sc->sis_ldata.sis_tx_tag); 1258 sc->sis_ldata.sis_tx_tag = NULL; 1259 goto fail; 1260 } 1261 1262 error = bus_dma_tag_create(sc->sis_parent_tag, /* parent */ 1263 1, 0, /* alignment, boundary */ 1264 BUS_SPACE_MAXADDR, /* lowaddr */ 1265 BUS_SPACE_MAXADDR, /* highaddr */ 1266 NULL, NULL, /* filter, filterarg */ 1267 MCLBYTES, 1, /* maxsize, nsegments */ 1268 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1269 0, /* flags */ 1270 &sc->sis_tag); 1271 if (error) 1272 goto fail; 1273 1274 ifp = &sc->arpcom.ac_if; 1275 ifp->if_softc = sc; 1276 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1277 ifp->if_mtu = ETHERMTU; 1278 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1279 ifp->if_ioctl = sis_ioctl; 1280 ifp->if_start = sis_start; 1281 ifp->if_watchdog = sis_watchdog; 1282 ifp->if_init = sis_init; 1283 ifp->if_baudrate = 10000000; 1284 ifq_set_maxlen(&ifp->if_snd, SIS_TX_LIST_CNT - 1); 1285 ifq_set_ready(&ifp->if_snd); 1286 #ifdef DEVICE_POLLING 1287 ifp->if_poll = sis_poll; 1288 #endif 1289 ifp->if_capenable = ifp->if_capabilities; 1290 1291 /* 1292 * Do MII setup. 1293 */ 1294 if (mii_phy_probe(dev, &sc->sis_miibus, 1295 sis_ifmedia_upd, sis_ifmedia_sts)) { 1296 device_printf(dev, "MII without any PHY!\n"); 1297 error = ENXIO; 1298 goto fail; 1299 } 1300 1301 /* 1302 * Call MI attach routine. 1303 */ 1304 ether_ifattach(ifp, eaddr); 1305 1306 /* 1307 * Tell the upper layer(s) we support long frames. 1308 */ 1309 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1310 1311 error = bus_setup_intr(dev, sc->sis_irq, INTR_TYPE_NET, 1312 sis_intr, sc, 1313 &sc->sis_intrhand, NULL); 1314 1315 if (error) { 1316 device_printf(dev, "couldn't set up irq\n"); 1317 ether_ifdetach(ifp); 1318 goto fail; 1319 } 1320 1321 fail: 1322 if (error) 1323 sis_detach(dev); 1324 1325 return(error); 1326 } 1327 1328 /* 1329 * Shutdown hardware and free up resources. It is called in both the error case 1330 * and the normal detach case so it needs to be careful about only freeing 1331 * resources that have actually been allocated. 1332 */ 1333 static int 1334 sis_detach(device_t dev) 1335 { 1336 struct sis_softc *sc = device_get_softc(dev); 1337 struct ifnet *ifp = &sc->arpcom.ac_if; 1338 1339 crit_enter(); 1340 1341 if (device_is_attached(dev)) { 1342 sis_reset(sc); 1343 sis_stop(sc); 1344 ether_ifdetach(ifp); 1345 } 1346 if (sc->sis_miibus) 1347 device_delete_child(dev, sc->sis_miibus); 1348 bus_generic_detach(dev); 1349 1350 if (sc->sis_intrhand) 1351 bus_teardown_intr(dev, sc->sis_irq, sc->sis_intrhand); 1352 1353 crit_exit(); 1354 1355 if (sc->sis_irq) 1356 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sis_irq); 1357 if (sc->sis_res) 1358 bus_release_resource(dev, SIS_RES, SIS_RID, sc->sis_res); 1359 1360 if (sc->sis_ldata.sis_rx_tag) { 1361 bus_dmamap_unload(sc->sis_ldata.sis_rx_tag, 1362 sc->sis_ldata.sis_rx_dmamap); 1363 bus_dmamem_free(sc->sis_ldata.sis_rx_tag, 1364 sc->sis_ldata.sis_rx_list, 1365 sc->sis_ldata.sis_rx_dmamap); 1366 bus_dma_tag_destroy(sc->sis_ldata.sis_rx_tag); 1367 } 1368 1369 if (sc->sis_ldata.sis_tx_tag) { 1370 bus_dmamap_unload(sc->sis_ldata.sis_tx_tag, 1371 sc->sis_ldata.sis_tx_dmamap); 1372 bus_dmamem_free(sc->sis_ldata.sis_tx_tag, 1373 sc->sis_ldata.sis_tx_list, 1374 sc->sis_ldata.sis_tx_dmamap); 1375 bus_dma_tag_destroy(sc->sis_ldata.sis_tx_tag); 1376 } 1377 if (sc->sis_tag) 1378 bus_dma_tag_destroy(sc->sis_tag); 1379 if (sc->sis_parent_tag) 1380 bus_dma_tag_destroy(sc->sis_parent_tag); 1381 1382 return(0); 1383 } 1384 1385 /* 1386 * Initialize the transmit descriptors. 1387 */ 1388 static int 1389 sis_list_tx_init(struct sis_softc *sc) 1390 { 1391 struct sis_list_data *ld; 1392 struct sis_ring_data *cd; 1393 int i, nexti; 1394 1395 cd = &sc->sis_cdata; 1396 ld = &sc->sis_ldata; 1397 1398 for (i = 0; i < SIS_TX_LIST_CNT; i++) { 1399 nexti = (i == (SIS_TX_LIST_CNT - 1)) ? 0 : i+1; 1400 ld->sis_tx_list[i].sis_nextdesc = 1401 &ld->sis_tx_list[nexti]; 1402 bus_dmamap_load(sc->sis_ldata.sis_tx_tag, 1403 sc->sis_ldata.sis_tx_dmamap, 1404 &ld->sis_tx_list[nexti], 1405 sizeof(struct sis_desc), sis_dma_map_desc_next, 1406 &ld->sis_tx_list[i], 0); 1407 ld->sis_tx_list[i].sis_mbuf = NULL; 1408 ld->sis_tx_list[i].sis_ptr = 0; 1409 ld->sis_tx_list[i].sis_ctl = 0; 1410 } 1411 1412 cd->sis_tx_prod = cd->sis_tx_cons = cd->sis_tx_cnt = 0; 1413 1414 bus_dmamap_sync(sc->sis_ldata.sis_tx_tag, sc->sis_ldata.sis_tx_dmamap, 1415 BUS_DMASYNC_PREWRITE); 1416 1417 return(0); 1418 } 1419 1420 /* 1421 * Initialize the RX descriptors and allocate mbufs for them. Note that 1422 * we arrange the descriptors in a closed ring, so that the last descriptor 1423 * points back to the first. 1424 */ 1425 static int 1426 sis_list_rx_init(struct sis_softc *sc) 1427 { 1428 struct sis_list_data *ld; 1429 struct sis_ring_data *cd; 1430 int i, nexti; 1431 1432 ld = &sc->sis_ldata; 1433 cd = &sc->sis_cdata; 1434 1435 for (i = 0; i < SIS_RX_LIST_CNT; i++) { 1436 if (sis_newbuf(sc, &ld->sis_rx_list[i], NULL) == ENOBUFS) 1437 return(ENOBUFS); 1438 nexti = (i == (SIS_RX_LIST_CNT - 1)) ? 0 : i+1; 1439 ld->sis_rx_list[i].sis_nextdesc = 1440 &ld->sis_rx_list[nexti]; 1441 bus_dmamap_load(sc->sis_ldata.sis_rx_tag, 1442 sc->sis_ldata.sis_rx_dmamap, 1443 &ld->sis_rx_list[nexti], 1444 sizeof(struct sis_desc), sis_dma_map_desc_next, 1445 &ld->sis_rx_list[i], 0); 1446 } 1447 1448 bus_dmamap_sync(sc->sis_ldata.sis_rx_tag, sc->sis_ldata.sis_rx_dmamap, 1449 BUS_DMASYNC_PREWRITE); 1450 1451 cd->sis_rx_prod = 0; 1452 1453 return(0); 1454 } 1455 1456 /* 1457 * Initialize an RX descriptor and attach an MBUF cluster. 1458 */ 1459 static int 1460 sis_newbuf(struct sis_softc *sc, struct sis_desc *c, struct mbuf *m) 1461 { 1462 if (m == NULL) { 1463 m = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR); 1464 if (m == NULL) 1465 return(ENOBUFS); 1466 } else { 1467 m->m_data = m->m_ext.ext_buf; 1468 } 1469 1470 c->sis_mbuf = m; 1471 c->sis_ctl = SIS_RXLEN; 1472 1473 bus_dmamap_create(sc->sis_tag, 0, &c->sis_map); 1474 bus_dmamap_load(sc->sis_tag, c->sis_map, mtod(m, void *), MCLBYTES, 1475 sis_dma_map_desc_ptr, c, 0); 1476 bus_dmamap_sync(sc->sis_tag, c->sis_map, BUS_DMASYNC_PREWRITE); 1477 1478 return(0); 1479 } 1480 1481 /* 1482 * A frame has been uploaded: pass the resulting mbuf chain up to 1483 * the higher level protocols. 1484 */ 1485 static void 1486 sis_rxeof(struct sis_softc *sc) 1487 { 1488 struct mbuf *m; 1489 struct ifnet *ifp; 1490 struct sis_desc *cur_rx; 1491 int i, total_len = 0; 1492 uint32_t rxstat; 1493 1494 ifp = &sc->arpcom.ac_if; 1495 i = sc->sis_cdata.sis_rx_prod; 1496 1497 while(SIS_OWNDESC(&sc->sis_ldata.sis_rx_list[i])) { 1498 1499 #ifdef DEVICE_POLLING 1500 if (ifp->if_flags & IFF_POLLING) { 1501 if (sc->rxcycles <= 0) 1502 break; 1503 sc->rxcycles--; 1504 } 1505 #endif /* DEVICE_POLLING */ 1506 cur_rx = &sc->sis_ldata.sis_rx_list[i]; 1507 rxstat = cur_rx->sis_rxstat; 1508 bus_dmamap_sync(sc->sis_tag, cur_rx->sis_map, 1509 BUS_DMASYNC_POSTWRITE); 1510 bus_dmamap_unload(sc->sis_tag, cur_rx->sis_map); 1511 bus_dmamap_destroy(sc->sis_tag, cur_rx->sis_map); 1512 m = cur_rx->sis_mbuf; 1513 cur_rx->sis_mbuf = NULL; 1514 total_len = SIS_RXBYTES(cur_rx); 1515 SIS_INC(i, SIS_RX_LIST_CNT); 1516 1517 /* 1518 * If an error occurs, update stats, clear the 1519 * status word and leave the mbuf cluster in place: 1520 * it should simply get re-used next time this descriptor 1521 * comes up in the ring. 1522 */ 1523 if (!(rxstat & SIS_CMDSTS_PKT_OK)) { 1524 ifp->if_ierrors++; 1525 if (rxstat & SIS_RXSTAT_COLL) 1526 ifp->if_collisions++; 1527 sis_newbuf(sc, cur_rx, m); 1528 continue; 1529 } 1530 1531 /* No errors; receive the packet. */ 1532 #ifdef __i386__ 1533 /* 1534 * On the x86 we do not have alignment problems, so try to 1535 * allocate a new buffer for the receive ring, and pass up 1536 * the one where the packet is already, saving the expensive 1537 * copy done in m_devget(). 1538 * If we are on an architecture with alignment problems, or 1539 * if the allocation fails, then use m_devget and leave the 1540 * existing buffer in the receive ring. 1541 */ 1542 if (sis_newbuf(sc, cur_rx, NULL) == 0) 1543 m->m_pkthdr.len = m->m_len = total_len; 1544 else 1545 #endif 1546 { 1547 struct mbuf *m0; 1548 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 1549 total_len + ETHER_ALIGN, 0, ifp, NULL); 1550 sis_newbuf(sc, cur_rx, m); 1551 if (m0 == NULL) { 1552 ifp->if_ierrors++; 1553 continue; 1554 } 1555 m_adj(m0, ETHER_ALIGN); 1556 m = m0; 1557 } 1558 1559 ifp->if_ipackets++; 1560 (*ifp->if_input)(ifp, m); 1561 } 1562 1563 sc->sis_cdata.sis_rx_prod = i; 1564 } 1565 1566 static void 1567 sis_rxeoc(struct sis_softc *sc) 1568 { 1569 sis_rxeof(sc); 1570 sis_init(sc); 1571 } 1572 1573 /* 1574 * A frame was downloaded to the chip. It's safe for us to clean up 1575 * the list buffers. 1576 */ 1577 1578 static void 1579 sis_txeof(struct sis_softc *sc) 1580 { 1581 struct sis_desc *cur_tx; 1582 struct ifnet *ifp; 1583 uint32_t idx; 1584 1585 ifp = &sc->arpcom.ac_if; 1586 1587 /* 1588 * Go through our tx list and free mbufs for those 1589 * frames that have been transmitted. 1590 */ 1591 for (idx = sc->sis_cdata.sis_tx_cons; sc->sis_cdata.sis_tx_cnt > 0; 1592 sc->sis_cdata.sis_tx_cnt--, SIS_INC(idx, SIS_TX_LIST_CNT) ) { 1593 cur_tx = &sc->sis_ldata.sis_tx_list[idx]; 1594 1595 if (SIS_OWNDESC(cur_tx)) 1596 break; 1597 1598 if (cur_tx->sis_ctl & SIS_CMDSTS_MORE) 1599 continue; 1600 1601 if (!(cur_tx->sis_ctl & SIS_CMDSTS_PKT_OK)) { 1602 ifp->if_oerrors++; 1603 if (cur_tx->sis_txstat & SIS_TXSTAT_EXCESSCOLLS) 1604 ifp->if_collisions++; 1605 if (cur_tx->sis_txstat & SIS_TXSTAT_OUTOFWINCOLL) 1606 ifp->if_collisions++; 1607 } 1608 1609 ifp->if_collisions += 1610 (cur_tx->sis_txstat & SIS_TXSTAT_COLLCNT) >> 16; 1611 1612 ifp->if_opackets++; 1613 if (cur_tx->sis_mbuf != NULL) { 1614 m_freem(cur_tx->sis_mbuf); 1615 cur_tx->sis_mbuf = NULL; 1616 bus_dmamap_unload(sc->sis_tag, cur_tx->sis_map); 1617 bus_dmamap_destroy(sc->sis_tag, cur_tx->sis_map); 1618 } 1619 } 1620 1621 if (idx != sc->sis_cdata.sis_tx_cons) { 1622 /* we freed up some buffers */ 1623 sc->sis_cdata.sis_tx_cons = idx; 1624 ifp->if_flags &= ~IFF_OACTIVE; 1625 } 1626 1627 ifp->if_timer = (sc->sis_cdata.sis_tx_cnt == 0) ? 0 : 5; 1628 } 1629 1630 static void 1631 sis_tick(void *xsc) 1632 { 1633 struct sis_softc *sc = xsc; 1634 struct mii_data *mii; 1635 struct ifnet *ifp = &sc->arpcom.ac_if; 1636 1637 crit_enter(); 1638 1639 mii = device_get_softc(sc->sis_miibus); 1640 mii_tick(mii); 1641 1642 if (!sc->sis_link) { 1643 mii_pollstat(mii); 1644 if (mii->mii_media_status & IFM_ACTIVE && 1645 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 1646 sc->sis_link++; 1647 if (!ifq_is_empty(&ifp->if_snd)) 1648 sis_start(ifp); 1649 } 1650 1651 callout_reset(&sc->sis_timer, hz, sis_tick, sc); 1652 1653 crit_exit(); 1654 } 1655 1656 #ifdef DEVICE_POLLING 1657 1658 static void 1659 sis_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1660 { 1661 struct sis_softc *sc = ifp->if_softc; 1662 1663 switch(cmd) { 1664 case POLL_REGISTER: 1665 /* disable interrupts */ 1666 CSR_WRITE_4(sc, SIS_IER, 0); 1667 break; 1668 case POLL_DEREGISTER: 1669 /* enable interrupts */ 1670 CSR_WRITE_4(sc, SIS_IER, 1); 1671 break; 1672 default: 1673 /* 1674 * On the sis, reading the status register also clears it. 1675 * So before returning to intr mode we must make sure that all 1676 * possible pending sources of interrupts have been served. 1677 * In practice this means run to completion the *eof routines, 1678 * and then call the interrupt routine 1679 */ 1680 sc->rxcycles = count; 1681 sis_rxeof(sc); 1682 sis_txeof(sc); 1683 if (!ifq_is_empty(&ifp->if_snd)) 1684 sis_start(ifp); 1685 1686 if (sc->rxcycles > 0 || cmd == POLL_AND_CHECK_STATUS) { 1687 uint32_t status; 1688 1689 /* Reading the ISR register clears all interrupts. */ 1690 status = CSR_READ_4(sc, SIS_ISR); 1691 1692 if (status & (SIS_ISR_RX_ERR|SIS_ISR_RX_OFLOW)) 1693 sis_rxeoc(sc); 1694 1695 if (status & (SIS_ISR_RX_IDLE)) 1696 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE); 1697 1698 if (status & SIS_ISR_SYSERR) { 1699 sis_reset(sc); 1700 sis_init(sc); 1701 } 1702 } 1703 break; 1704 } 1705 } 1706 #endif /* DEVICE_POLLING */ 1707 1708 static void 1709 sis_intr(void *arg) 1710 { 1711 struct sis_softc *sc; 1712 struct ifnet *ifp; 1713 uint32_t status; 1714 1715 sc = arg; 1716 ifp = &sc->arpcom.ac_if; 1717 1718 /* Supress unwanted interrupts */ 1719 if (!(ifp->if_flags & IFF_UP)) { 1720 sis_stop(sc); 1721 return; 1722 } 1723 1724 /* Disable interrupts. */ 1725 CSR_WRITE_4(sc, SIS_IER, 0); 1726 1727 for (;;) { 1728 /* Reading the ISR register clears all interrupts. */ 1729 status = CSR_READ_4(sc, SIS_ISR); 1730 1731 if ((status & SIS_INTRS) == 0) 1732 break; 1733 1734 if (status & 1735 (SIS_ISR_TX_DESC_OK | SIS_ISR_TX_ERR | SIS_ISR_TX_OK | 1736 SIS_ISR_TX_IDLE) ) 1737 sis_txeof(sc); 1738 1739 if (status & 1740 (SIS_ISR_RX_DESC_OK | SIS_ISR_RX_OK | SIS_ISR_RX_IDLE)) 1741 sis_rxeof(sc); 1742 1743 if (status & (SIS_ISR_RX_ERR | SIS_ISR_RX_OFLOW)) 1744 sis_rxeoc(sc); 1745 1746 if (status & (SIS_ISR_RX_IDLE)) 1747 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE); 1748 1749 if (status & SIS_ISR_SYSERR) { 1750 sis_reset(sc); 1751 sis_init(sc); 1752 } 1753 } 1754 1755 /* Re-enable interrupts. */ 1756 CSR_WRITE_4(sc, SIS_IER, 1); 1757 1758 if (!ifq_is_empty(&ifp->if_snd)) 1759 sis_start(ifp); 1760 } 1761 1762 /* 1763 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1764 * pointers to the fragment pointers. 1765 */ 1766 static int 1767 sis_encap(struct sis_softc *sc, struct mbuf *m_head, uint32_t *txidx) 1768 { 1769 struct sis_desc *f = NULL; 1770 struct mbuf *m; 1771 int frag, cur, cnt = 0; 1772 1773 /* 1774 * If there's no way we can send any packets, return now. 1775 */ 1776 if (SIS_TX_LIST_CNT - sc->sis_cdata.sis_tx_cnt < 2) 1777 return (ENOBUFS); 1778 1779 /* 1780 * Start packing the mbufs in this chain into 1781 * the fragment pointers. Stop when we run out 1782 * of fragments or hit the end of the mbuf chain. 1783 */ 1784 m = m_head; 1785 cur = frag = *txidx; 1786 1787 for (m = m_head; m != NULL; m = m->m_next) { 1788 if (m->m_len != 0) { 1789 if ((SIS_TX_LIST_CNT - 1790 (sc->sis_cdata.sis_tx_cnt + cnt)) < 2) 1791 return(ENOBUFS); 1792 f = &sc->sis_ldata.sis_tx_list[frag]; 1793 f->sis_ctl = SIS_CMDSTS_MORE | m->m_len; 1794 bus_dmamap_create(sc->sis_tag, 0, &f->sis_map); 1795 bus_dmamap_load(sc->sis_tag, f->sis_map, 1796 mtod(m, void *), m->m_len, 1797 sis_dma_map_desc_ptr, f, 0); 1798 bus_dmamap_sync(sc->sis_tag, f->sis_map, 1799 BUS_DMASYNC_PREREAD); 1800 if (cnt != 0) 1801 f->sis_ctl |= SIS_CMDSTS_OWN; 1802 cur = frag; 1803 SIS_INC(frag, SIS_TX_LIST_CNT); 1804 cnt++; 1805 } 1806 } 1807 1808 if (m != NULL) 1809 return(ENOBUFS); 1810 1811 sc->sis_ldata.sis_tx_list[cur].sis_mbuf = m_head; 1812 sc->sis_ldata.sis_tx_list[cur].sis_ctl &= ~SIS_CMDSTS_MORE; 1813 sc->sis_ldata.sis_tx_list[*txidx].sis_ctl |= SIS_CMDSTS_OWN; 1814 sc->sis_cdata.sis_tx_cnt += cnt; 1815 *txidx = frag; 1816 1817 return(0); 1818 } 1819 1820 /* 1821 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1822 * to the mbuf data regions directly in the transmit lists. We also save a 1823 * copy of the pointers since the transmit list fragment pointers are 1824 * physical addresses. 1825 */ 1826 1827 static void 1828 sis_start(struct ifnet *ifp) 1829 { 1830 struct sis_softc *sc; 1831 struct mbuf *m_head = NULL; 1832 uint32_t idx; 1833 1834 sc = ifp->if_softc; 1835 1836 if (!sc->sis_link) 1837 return; 1838 1839 idx = sc->sis_cdata.sis_tx_prod; 1840 1841 if (ifp->if_flags & IFF_OACTIVE) 1842 return; 1843 1844 while(sc->sis_ldata.sis_tx_list[idx].sis_mbuf == NULL) { 1845 m_head = ifq_poll(&ifp->if_snd); 1846 if (m_head == NULL) 1847 break; 1848 1849 if (sis_encap(sc, m_head, &idx)) { 1850 ifp->if_flags |= IFF_OACTIVE; 1851 break; 1852 } 1853 m_head = ifq_dequeue(&ifp->if_snd); 1854 1855 /* 1856 * If there's a BPF listener, bounce a copy of this frame 1857 * to him. 1858 */ 1859 BPF_MTAP(ifp, m_head); 1860 } 1861 1862 /* Transmit */ 1863 sc->sis_cdata.sis_tx_prod = idx; 1864 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_ENABLE); 1865 1866 /* 1867 * Set a timeout in case the chip goes out to lunch. 1868 */ 1869 ifp->if_timer = 5; 1870 } 1871 1872 static void 1873 sis_init(void *xsc) 1874 { 1875 struct sis_softc *sc = xsc; 1876 struct ifnet *ifp = &sc->arpcom.ac_if; 1877 struct mii_data *mii; 1878 1879 crit_enter(); 1880 1881 /* 1882 * Cancel pending I/O and free all RX/TX buffers. 1883 */ 1884 sis_stop(sc); 1885 1886 mii = device_get_softc(sc->sis_miibus); 1887 1888 /* Set MAC address */ 1889 if (sc->sis_type == SIS_TYPE_83815) { 1890 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR0); 1891 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1892 ((uint16_t *)sc->arpcom.ac_enaddr)[0]); 1893 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR1); 1894 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1895 ((uint16_t *)sc->arpcom.ac_enaddr)[1]); 1896 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR2); 1897 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1898 ((uint16_t *)sc->arpcom.ac_enaddr)[2]); 1899 } else { 1900 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR0); 1901 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1902 ((uint16_t *)sc->arpcom.ac_enaddr)[0]); 1903 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR1); 1904 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1905 ((uint16_t *)sc->arpcom.ac_enaddr)[1]); 1906 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR2); 1907 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1908 ((uint16_t *)sc->arpcom.ac_enaddr)[2]); 1909 } 1910 1911 /* Init circular RX list. */ 1912 if (sis_list_rx_init(sc) == ENOBUFS) { 1913 if_printf(ifp, "initialization failed: " 1914 "no memory for rx buffers\n"); 1915 sis_stop(sc); 1916 crit_exit(); 1917 return; 1918 } 1919 1920 /* 1921 * Init tx descriptors. 1922 */ 1923 sis_list_tx_init(sc); 1924 1925 /* 1926 * For the NatSemi chip, we have to explicitly enable the 1927 * reception of ARP frames, as well as turn on the 'perfect 1928 * match' filter where we store the station address, otherwise 1929 * we won't receive unicasts meant for this host. 1930 */ 1931 if (sc->sis_type == SIS_TYPE_83815) { 1932 SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_ARP); 1933 SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_PERFECT); 1934 } 1935 1936 /* If we want promiscuous mode, set the allframes bit. */ 1937 if (ifp->if_flags & IFF_PROMISC) 1938 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLPHYS); 1939 else 1940 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLPHYS); 1941 1942 /* 1943 * Set the capture broadcast bit to capture broadcast frames. 1944 */ 1945 if (ifp->if_flags & IFF_BROADCAST) 1946 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_BROAD); 1947 else 1948 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_BROAD); 1949 1950 /* 1951 * Load the multicast filter. 1952 */ 1953 if (sc->sis_type == SIS_TYPE_83815) 1954 sis_setmulti_ns(sc); 1955 else 1956 sis_setmulti_sis(sc); 1957 1958 /* Turn the receive filter on */ 1959 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ENABLE); 1960 1961 /* 1962 * Load the address of the RX and TX lists. 1963 */ 1964 CSR_WRITE_4(sc, SIS_RX_LISTPTR, sc->sis_cdata.sis_rx_paddr); 1965 CSR_WRITE_4(sc, SIS_TX_LISTPTR, sc->sis_cdata.sis_tx_paddr); 1966 1967 /* SIS_CFG_EDB_MASTER_EN indicates the EDB bus is used instead of 1968 * the PCI bus. When this bit is set, the Max DMA Burst Size 1969 * for TX/RX DMA should be no larger than 16 double words. 1970 */ 1971 if (CSR_READ_4(sc, SIS_CFG) & SIS_CFG_EDB_MASTER_EN) 1972 CSR_WRITE_4(sc, SIS_RX_CFG, SIS_RXCFG64); 1973 else 1974 CSR_WRITE_4(sc, SIS_RX_CFG, SIS_RXCFG256); 1975 1976 /* Accept Long Packets for VLAN support */ 1977 SIS_SETBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_JABBER); 1978 1979 /* Set TX configuration */ 1980 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T) 1981 CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_10); 1982 else 1983 CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_100); 1984 1985 /* Set full/half duplex mode. */ 1986 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 1987 SIS_SETBIT(sc, SIS_TX_CFG, 1988 (SIS_TXCFG_IGN_HBEAT|SIS_TXCFG_IGN_CARR)); 1989 SIS_SETBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS); 1990 } else { 1991 SIS_CLRBIT(sc, SIS_TX_CFG, 1992 (SIS_TXCFG_IGN_HBEAT|SIS_TXCFG_IGN_CARR)); 1993 SIS_CLRBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS); 1994 } 1995 1996 /* 1997 * Enable interrupts. 1998 */ 1999 CSR_WRITE_4(sc, SIS_IMR, SIS_INTRS); 2000 #ifdef DEVICE_POLLING 2001 /* 2002 * ... only enable interrupts if we are not polling, make sure 2003 * they are off otherwise. 2004 */ 2005 if (ifp->if_flags & IFF_POLLING) 2006 CSR_WRITE_4(sc, SIS_IER, 0); 2007 else 2008 #endif /* DEVICE_POLLING */ 2009 CSR_WRITE_4(sc, SIS_IER, 1); 2010 2011 /* Enable receiver and transmitter. */ 2012 SIS_CLRBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE|SIS_CSR_RX_DISABLE); 2013 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE); 2014 2015 #ifdef notdef 2016 mii_mediachg(mii); 2017 #endif 2018 2019 /* 2020 * Page 75 of the DP83815 manual recommends the 2021 * following register settings "for optimum 2022 * performance." Note however that at least three 2023 * of the registers are listed as "reserved" in 2024 * the register map, so who knows what they do. 2025 */ 2026 if (sc->sis_type == SIS_TYPE_83815) { 2027 CSR_WRITE_4(sc, NS_PHY_PAGE, 0x0001); 2028 CSR_WRITE_4(sc, NS_PHY_CR, 0x189C); 2029 CSR_WRITE_4(sc, NS_PHY_TDATA, 0x0000); 2030 CSR_WRITE_4(sc, NS_PHY_DSPCFG, 0x5040); 2031 CSR_WRITE_4(sc, NS_PHY_SDCFG, 0x008C); 2032 } 2033 2034 ifp->if_flags |= IFF_RUNNING; 2035 ifp->if_flags &= ~IFF_OACTIVE; 2036 2037 callout_reset(&sc->sis_timer, hz, sis_tick, sc); 2038 2039 crit_exit(); 2040 } 2041 2042 /* 2043 * Set media options. 2044 */ 2045 static int 2046 sis_ifmedia_upd(struct ifnet *ifp) 2047 { 2048 struct sis_softc *sc; 2049 struct mii_data *mii; 2050 2051 sc = ifp->if_softc; 2052 2053 mii = device_get_softc(sc->sis_miibus); 2054 sc->sis_link = 0; 2055 if (mii->mii_instance) { 2056 struct mii_softc *miisc; 2057 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 2058 mii_phy_reset(miisc); 2059 } 2060 mii_mediachg(mii); 2061 2062 return(0); 2063 } 2064 2065 /* 2066 * Report current media status. 2067 */ 2068 static void 2069 sis_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 2070 { 2071 struct sis_softc *sc; 2072 struct mii_data *mii; 2073 2074 sc = ifp->if_softc; 2075 2076 mii = device_get_softc(sc->sis_miibus); 2077 mii_pollstat(mii); 2078 ifmr->ifm_active = mii->mii_media_active; 2079 ifmr->ifm_status = mii->mii_media_status; 2080 } 2081 2082 static int 2083 sis_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr) 2084 { 2085 struct sis_softc *sc = ifp->if_softc; 2086 struct ifreq *ifr = (struct ifreq *) data; 2087 struct mii_data *mii; 2088 int error = 0; 2089 2090 crit_enter(); 2091 2092 switch(command) { 2093 case SIOCSIFFLAGS: 2094 if (ifp->if_flags & IFF_UP) { 2095 sis_init(sc); 2096 } else { 2097 if (ifp->if_flags & IFF_RUNNING) 2098 sis_stop(sc); 2099 } 2100 error = 0; 2101 break; 2102 case SIOCADDMULTI: 2103 case SIOCDELMULTI: 2104 if (sc->sis_type == SIS_TYPE_83815) 2105 sis_setmulti_ns(sc); 2106 else 2107 sis_setmulti_sis(sc); 2108 error = 0; 2109 break; 2110 case SIOCGIFMEDIA: 2111 case SIOCSIFMEDIA: 2112 mii = device_get_softc(sc->sis_miibus); 2113 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 2114 break; 2115 default: 2116 error = ether_ioctl(ifp, command, data); 2117 break; 2118 } 2119 2120 crit_exit(); 2121 2122 return(error); 2123 } 2124 2125 static void 2126 sis_watchdog(struct ifnet *ifp) 2127 { 2128 struct sis_softc *sc; 2129 2130 sc = ifp->if_softc; 2131 2132 ifp->if_oerrors++; 2133 if_printf(ifp, "watchdog timeout\n"); 2134 2135 sis_stop(sc); 2136 sis_reset(sc); 2137 sis_init(sc); 2138 2139 if (!ifq_is_empty(&ifp->if_snd)) 2140 sis_start(ifp); 2141 } 2142 2143 /* 2144 * Stop the adapter and free any mbufs allocated to the 2145 * RX and TX lists. 2146 */ 2147 static void 2148 sis_stop(struct sis_softc *sc) 2149 { 2150 int i; 2151 struct ifnet *ifp; 2152 2153 ifp = &sc->arpcom.ac_if; 2154 ifp->if_timer = 0; 2155 2156 callout_stop(&sc->sis_timer); 2157 2158 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2159 CSR_WRITE_4(sc, SIS_IER, 0); 2160 CSR_WRITE_4(sc, SIS_IMR, 0); 2161 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE|SIS_CSR_RX_DISABLE); 2162 DELAY(1000); 2163 CSR_WRITE_4(sc, SIS_TX_LISTPTR, 0); 2164 CSR_WRITE_4(sc, SIS_RX_LISTPTR, 0); 2165 2166 sc->sis_link = 0; 2167 2168 /* 2169 * Free data in the RX lists. 2170 */ 2171 for (i = 0; i < SIS_RX_LIST_CNT; i++) { 2172 if (sc->sis_ldata.sis_rx_list[i].sis_mbuf != NULL) { 2173 bus_dmamap_unload(sc->sis_tag, 2174 sc->sis_ldata.sis_rx_list[i].sis_map); 2175 bus_dmamap_destroy(sc->sis_tag, 2176 sc->sis_ldata.sis_rx_list[i].sis_map); 2177 m_freem(sc->sis_ldata.sis_rx_list[i].sis_mbuf); 2178 sc->sis_ldata.sis_rx_list[i].sis_mbuf = NULL; 2179 } 2180 } 2181 bzero(sc->sis_ldata.sis_rx_list, sizeof(sc->sis_ldata.sis_rx_list)); 2182 2183 /* 2184 * Free the TX list buffers. 2185 */ 2186 for (i = 0; i < SIS_TX_LIST_CNT; i++) { 2187 if (sc->sis_ldata.sis_tx_list[i].sis_mbuf != NULL) { 2188 bus_dmamap_unload(sc->sis_tag, 2189 sc->sis_ldata.sis_tx_list[i].sis_map); 2190 bus_dmamap_destroy(sc->sis_tag, 2191 sc->sis_ldata.sis_tx_list[i].sis_map); 2192 m_freem(sc->sis_ldata.sis_tx_list[i].sis_mbuf); 2193 sc->sis_ldata.sis_tx_list[i].sis_mbuf = NULL; 2194 } 2195 } 2196 2197 bzero(sc->sis_ldata.sis_tx_list, sizeof(sc->sis_ldata.sis_tx_list)); 2198 } 2199 2200 /* 2201 * Stop all chip I/O so that the kernel's probe routines don't 2202 * get confused by errant DMAs when rebooting. 2203 */ 2204 static void 2205 sis_shutdown(device_t dev) 2206 { 2207 struct sis_softc *sc; 2208 2209 sc = device_get_softc(dev); 2210 2211 sis_reset(sc); 2212 sis_stop(sc); 2213 } 2214