1 /* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: src/sys/pci/if_sis.c,v 1.13.4.24 2003/03/05 18:42:33 njl Exp $ 33 */ 34 35 /* 36 * SiS 900/SiS 7016 fast ethernet PCI NIC driver. Datasheets are 37 * available from http://www.sis.com.tw. 38 * 39 * This driver also supports the NatSemi DP83815. Datasheets are 40 * available from http://www.national.com. 41 * 42 * Written by Bill Paul <wpaul@ee.columbia.edu> 43 * Electrical Engineering Department 44 * Columbia University, New York City 45 */ 46 47 /* 48 * The SiS 900 is a fairly simple chip. It uses bus master DMA with 49 * simple TX and RX descriptors of 3 longwords in size. The receiver 50 * has a single perfect filter entry for the station address and a 51 * 128-bit multicast hash table. The SiS 900 has a built-in MII-based 52 * transceiver while the 7016 requires an external transceiver chip. 53 * Both chips offer the standard bit-bang MII interface as well as 54 * an enchanced PHY interface which simplifies accessing MII registers. 55 * 56 * The only downside to this chipset is that RX descriptors must be 57 * longword aligned. 58 */ 59 60 #include "opt_polling.h" 61 62 #include <sys/param.h> 63 #include <sys/systm.h> 64 #include <sys/sockio.h> 65 #include <sys/mbuf.h> 66 #include <sys/malloc.h> 67 #include <sys/kernel.h> 68 #include <sys/socket.h> 69 #include <sys/sysctl.h> 70 #include <sys/serialize.h> 71 #include <sys/thread2.h> 72 #include <sys/bus.h> 73 #include <sys/rman.h> 74 #include <sys/interrupt.h> 75 76 #include <net/if.h> 77 #include <net/ifq_var.h> 78 #include <net/if_arp.h> 79 #include <net/ethernet.h> 80 #include <net/if_dl.h> 81 #include <net/if_media.h> 82 #include <net/if_types.h> 83 #include <net/vlan/if_vlan_var.h> 84 85 #include <net/bpf.h> 86 87 #include <dev/netif/mii_layer/mii.h> 88 #include <dev/netif/mii_layer/miivar.h> 89 90 #include <bus/pci/pcidevs.h> 91 #include <bus/pci/pcireg.h> 92 #include <bus/pci/pcivar.h> 93 94 #define SIS_USEIOSPACE 95 96 #include "if_sisreg.h" 97 98 /* "controller miibus0" required. See GENERIC if you get errors here. */ 99 #include "miibus_if.h" 100 101 /* 102 * Various supported device vendors/types and their names. 103 */ 104 static struct sis_type sis_devs[] = { 105 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_900, "SiS 900 10/100BaseTX" }, 106 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_7016, "SiS 7016 10/100BaseTX" }, 107 { PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815, "NatSemi DP8381[56] 10/100BaseTX" }, 108 { 0, 0, NULL } 109 }; 110 111 static int sis_probe(device_t); 112 static int sis_attach(device_t); 113 static int sis_detach(device_t); 114 115 static int sis_newbuf(struct sis_softc *, int, int); 116 static void sis_setup_rxdesc(struct sis_softc *, int); 117 static int sis_encap(struct sis_softc *, struct mbuf **, uint32_t *); 118 static void sis_rxeof(struct sis_softc *); 119 static void sis_rxeoc(struct sis_softc *); 120 static void sis_txeof(struct sis_softc *); 121 static void sis_intr(void *); 122 static void sis_tick(void *); 123 static void sis_start(struct ifnet *); 124 static int sis_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *); 125 static void sis_init(void *); 126 static void sis_stop(struct sis_softc *); 127 static void sis_watchdog(struct ifnet *); 128 static void sis_shutdown(device_t); 129 static int sis_ifmedia_upd(struct ifnet *); 130 static void sis_ifmedia_sts(struct ifnet *, struct ifmediareq *); 131 132 static uint16_t sis_reverse(uint16_t); 133 static void sis_delay(struct sis_softc *); 134 static void sis_eeprom_idle(struct sis_softc *); 135 static void sis_eeprom_putbyte(struct sis_softc *, int); 136 static void sis_eeprom_getword(struct sis_softc *, int, uint16_t *); 137 static void sis_read_eeprom(struct sis_softc *, caddr_t, int, int, int); 138 #ifdef __i386__ 139 static void sis_read_cmos(struct sis_softc *, device_t, caddr_t, int, int); 140 static void sis_read_mac(struct sis_softc *, device_t, caddr_t); 141 static device_t sis_find_bridge(device_t); 142 #endif 143 144 static void sis_mii_sync(struct sis_softc *); 145 static void sis_mii_send(struct sis_softc *, uint32_t, int); 146 static int sis_mii_readreg(struct sis_softc *, struct sis_mii_frame *); 147 static int sis_mii_writereg(struct sis_softc *, struct sis_mii_frame *); 148 static int sis_miibus_readreg(device_t, int, int); 149 static int sis_miibus_writereg(device_t, int, int, int); 150 static void sis_miibus_statchg(device_t); 151 152 static void sis_setmulti_sis(struct sis_softc *); 153 static void sis_setmulti_ns(struct sis_softc *); 154 static uint32_t sis_mchash(struct sis_softc *, const uint8_t *); 155 static void sis_reset(struct sis_softc *); 156 static int sis_list_rx_init(struct sis_softc *); 157 static int sis_list_tx_init(struct sis_softc *); 158 159 static int sis_dma_alloc(device_t dev); 160 static void sis_dma_free(device_t dev); 161 #ifdef DEVICE_POLLING 162 static poll_handler_t sis_poll; 163 #endif 164 #ifdef SIS_USEIOSPACE 165 #define SIS_RES SYS_RES_IOPORT 166 #define SIS_RID SIS_PCI_LOIO 167 #else 168 #define SIS_RES SYS_RES_MEMORY 169 #define SIS_RID SIS_PCI_LOMEM 170 #endif 171 172 static device_method_t sis_methods[] = { 173 /* Device interface */ 174 DEVMETHOD(device_probe, sis_probe), 175 DEVMETHOD(device_attach, sis_attach), 176 DEVMETHOD(device_detach, sis_detach), 177 DEVMETHOD(device_shutdown, sis_shutdown), 178 179 /* bus interface */ 180 DEVMETHOD(bus_print_child, bus_generic_print_child), 181 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 182 183 /* MII interface */ 184 DEVMETHOD(miibus_readreg, sis_miibus_readreg), 185 DEVMETHOD(miibus_writereg, sis_miibus_writereg), 186 DEVMETHOD(miibus_statchg, sis_miibus_statchg), 187 188 { 0, 0 } 189 }; 190 191 static driver_t sis_driver = { 192 "sis", 193 sis_methods, 194 sizeof(struct sis_softc) 195 }; 196 197 static devclass_t sis_devclass; 198 199 DECLARE_DUMMY_MODULE(if_sis); 200 DRIVER_MODULE(if_sis, pci, sis_driver, sis_devclass, NULL, NULL); 201 DRIVER_MODULE(miibus, sis, miibus_driver, miibus_devclass, NULL, NULL); 202 203 #define SIS_SETBIT(sc, reg, x) \ 204 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x)) 205 206 #define SIS_CLRBIT(sc, reg, x) \ 207 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x)) 208 209 #define SIO_SET(x) \ 210 CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) | x) 211 212 #define SIO_CLR(x) \ 213 CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) & ~x) 214 215 /* 216 * Routine to reverse the bits in a word. Stolen almost 217 * verbatim from /usr/games/fortune. 218 */ 219 static uint16_t 220 sis_reverse(uint16_t n) 221 { 222 n = ((n >> 1) & 0x5555) | ((n << 1) & 0xaaaa); 223 n = ((n >> 2) & 0x3333) | ((n << 2) & 0xcccc); 224 n = ((n >> 4) & 0x0f0f) | ((n << 4) & 0xf0f0); 225 n = ((n >> 8) & 0x00ff) | ((n << 8) & 0xff00); 226 227 return(n); 228 } 229 230 static void 231 sis_delay(struct sis_softc *sc) 232 { 233 int idx; 234 235 for (idx = (300 / 33) + 1; idx > 0; idx--) 236 CSR_READ_4(sc, SIS_CSR); 237 } 238 239 static void 240 sis_eeprom_idle(struct sis_softc *sc) 241 { 242 int i; 243 244 SIO_SET(SIS_EECTL_CSEL); 245 sis_delay(sc); 246 SIO_SET(SIS_EECTL_CLK); 247 sis_delay(sc); 248 249 for (i = 0; i < 25; i++) { 250 SIO_CLR(SIS_EECTL_CLK); 251 sis_delay(sc); 252 SIO_SET(SIS_EECTL_CLK); 253 sis_delay(sc); 254 } 255 256 SIO_CLR(SIS_EECTL_CLK); 257 sis_delay(sc); 258 SIO_CLR(SIS_EECTL_CSEL); 259 sis_delay(sc); 260 CSR_WRITE_4(sc, SIS_EECTL, 0x00000000); 261 } 262 263 /* 264 * Send a read command and address to the EEPROM, check for ACK. 265 */ 266 static void 267 sis_eeprom_putbyte(struct sis_softc *sc, int addr) 268 { 269 int d, i; 270 271 d = addr | SIS_EECMD_READ; 272 273 /* 274 * Feed in each bit and stobe the clock. 275 */ 276 for (i = 0x400; i; i >>= 1) { 277 if (d & i) 278 SIO_SET(SIS_EECTL_DIN); 279 else 280 SIO_CLR(SIS_EECTL_DIN); 281 sis_delay(sc); 282 SIO_SET(SIS_EECTL_CLK); 283 sis_delay(sc); 284 SIO_CLR(SIS_EECTL_CLK); 285 sis_delay(sc); 286 } 287 } 288 289 /* 290 * Read a word of data stored in the EEPROM at address 'addr.' 291 */ 292 static void 293 sis_eeprom_getword(struct sis_softc *sc, int addr, uint16_t *dest) 294 { 295 int i; 296 uint16_t word = 0; 297 298 /* Force EEPROM to idle state. */ 299 sis_eeprom_idle(sc); 300 301 /* Enter EEPROM access mode. */ 302 sis_delay(sc); 303 SIO_CLR(SIS_EECTL_CLK); 304 sis_delay(sc); 305 SIO_SET(SIS_EECTL_CSEL); 306 sis_delay(sc); 307 308 /* 309 * Send address of word we want to read. 310 */ 311 sis_eeprom_putbyte(sc, addr); 312 313 /* 314 * Start reading bits from EEPROM. 315 */ 316 for (i = 0x8000; i; i >>= 1) { 317 SIO_SET(SIS_EECTL_CLK); 318 sis_delay(sc); 319 if (CSR_READ_4(sc, SIS_EECTL) & SIS_EECTL_DOUT) 320 word |= i; 321 sis_delay(sc); 322 SIO_CLR(SIS_EECTL_CLK); 323 sis_delay(sc); 324 } 325 326 /* Turn off EEPROM access mode. */ 327 sis_eeprom_idle(sc); 328 329 *dest = word; 330 } 331 332 /* 333 * Read a sequence of words from the EEPROM. 334 */ 335 static void 336 sis_read_eeprom(struct sis_softc *sc, caddr_t dest, int off, int cnt, int swap) 337 { 338 int i; 339 uint16_t word = 0, *ptr; 340 341 for (i = 0; i < cnt; i++) { 342 sis_eeprom_getword(sc, off + i, &word); 343 ptr = (uint16_t *)(dest + (i * 2)); 344 if (swap) 345 *ptr = ntohs(word); 346 else 347 *ptr = word; 348 } 349 } 350 351 #ifdef __i386__ 352 static device_t 353 sis_find_bridge(device_t dev) 354 { 355 devclass_t pci_devclass; 356 device_t *pci_devices; 357 int pci_count = 0; 358 device_t *pci_children; 359 int pci_childcount = 0; 360 device_t *busp, *childp; 361 device_t child = NULL; 362 int i, j; 363 364 if ((pci_devclass = devclass_find("pci")) == NULL) 365 return(NULL); 366 367 devclass_get_devices(pci_devclass, &pci_devices, &pci_count); 368 369 for (i = 0, busp = pci_devices; i < pci_count; i++, busp++) { 370 pci_childcount = 0; 371 device_get_children(*busp, &pci_children, &pci_childcount); 372 for (j = 0, childp = pci_children; j < pci_childcount; 373 j++, childp++) { 374 if (pci_get_vendor(*childp) == PCI_VENDOR_SIS && 375 pci_get_device(*childp) == 0x0008) { 376 child = *childp; 377 goto done; 378 } 379 } 380 } 381 382 done: 383 kfree(pci_devices, M_TEMP); 384 kfree(pci_children, M_TEMP); 385 return(child); 386 } 387 388 static void 389 sis_read_cmos(struct sis_softc *sc, device_t dev, caddr_t dest, int off, 390 int cnt) 391 { 392 device_t bridge; 393 uint8_t reg; 394 int i; 395 bus_space_tag_t btag; 396 397 bridge = sis_find_bridge(dev); 398 if (bridge == NULL) 399 return; 400 reg = pci_read_config(bridge, 0x48, 1); 401 pci_write_config(bridge, 0x48, reg|0x40, 1); 402 403 /* XXX */ 404 btag = I386_BUS_SPACE_IO; 405 406 for (i = 0; i < cnt; i++) { 407 bus_space_write_1(btag, 0x0, 0x70, i + off); 408 *(dest + i) = bus_space_read_1(btag, 0x0, 0x71); 409 } 410 411 pci_write_config(bridge, 0x48, reg & ~0x40, 1); 412 } 413 414 static void 415 sis_read_mac(struct sis_softc *sc, device_t dev, caddr_t dest) 416 { 417 uint32_t filtsave, csrsave; 418 419 filtsave = CSR_READ_4(sc, SIS_RXFILT_CTL); 420 csrsave = CSR_READ_4(sc, SIS_CSR); 421 422 CSR_WRITE_4(sc, SIS_CSR, SIS_CSR_RELOAD | filtsave); 423 CSR_WRITE_4(sc, SIS_CSR, 0); 424 425 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave & ~SIS_RXFILTCTL_ENABLE); 426 427 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR0); 428 ((uint16_t *)dest)[0] = CSR_READ_2(sc, SIS_RXFILT_DATA); 429 CSR_WRITE_4(sc, SIS_RXFILT_CTL,SIS_FILTADDR_PAR1); 430 ((uint16_t *)dest)[1] = CSR_READ_2(sc, SIS_RXFILT_DATA); 431 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR2); 432 ((uint16_t *)dest)[2] = CSR_READ_2(sc, SIS_RXFILT_DATA); 433 434 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave); 435 CSR_WRITE_4(sc, SIS_CSR, csrsave); 436 } 437 #endif 438 439 /* 440 * Sync the PHYs by setting data bit and strobing the clock 32 times. 441 */ 442 static void 443 sis_mii_sync(struct sis_softc *sc) 444 { 445 int i; 446 447 SIO_SET(SIS_MII_DIR|SIS_MII_DATA); 448 449 for (i = 0; i < 32; i++) { 450 SIO_SET(SIS_MII_CLK); 451 DELAY(1); 452 SIO_CLR(SIS_MII_CLK); 453 DELAY(1); 454 } 455 } 456 457 /* 458 * Clock a series of bits through the MII. 459 */ 460 static void 461 sis_mii_send(struct sis_softc *sc, uint32_t bits, int cnt) 462 { 463 int i; 464 465 SIO_CLR(SIS_MII_CLK); 466 467 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 468 if (bits & i) 469 SIO_SET(SIS_MII_DATA); 470 else 471 SIO_CLR(SIS_MII_DATA); 472 DELAY(1); 473 SIO_CLR(SIS_MII_CLK); 474 DELAY(1); 475 SIO_SET(SIS_MII_CLK); 476 } 477 } 478 479 /* 480 * Read an PHY register through the MII. 481 */ 482 static int 483 sis_mii_readreg(struct sis_softc *sc, struct sis_mii_frame *frame) 484 { 485 int i, ack; 486 487 /* 488 * Set up frame for RX. 489 */ 490 frame->mii_stdelim = SIS_MII_STARTDELIM; 491 frame->mii_opcode = SIS_MII_READOP; 492 frame->mii_turnaround = 0; 493 frame->mii_data = 0; 494 495 /* 496 * Turn on data xmit. 497 */ 498 SIO_SET(SIS_MII_DIR); 499 500 sis_mii_sync(sc); 501 502 /* 503 * Send command/address info. 504 */ 505 sis_mii_send(sc, frame->mii_stdelim, 2); 506 sis_mii_send(sc, frame->mii_opcode, 2); 507 sis_mii_send(sc, frame->mii_phyaddr, 5); 508 sis_mii_send(sc, frame->mii_regaddr, 5); 509 510 /* Idle bit */ 511 SIO_CLR((SIS_MII_CLK|SIS_MII_DATA)); 512 DELAY(1); 513 SIO_SET(SIS_MII_CLK); 514 DELAY(1); 515 516 /* Turn off xmit. */ 517 SIO_CLR(SIS_MII_DIR); 518 519 /* Check for ack */ 520 SIO_CLR(SIS_MII_CLK); 521 DELAY(1); 522 ack = CSR_READ_4(sc, SIS_EECTL) & SIS_MII_DATA; 523 SIO_SET(SIS_MII_CLK); 524 DELAY(1); 525 526 /* 527 * Now try reading data bits. If the ack failed, we still 528 * need to clock through 16 cycles to keep the PHY(s) in sync. 529 */ 530 if (ack) { 531 for(i = 0; i < 16; i++) { 532 SIO_CLR(SIS_MII_CLK); 533 DELAY(1); 534 SIO_SET(SIS_MII_CLK); 535 DELAY(1); 536 } 537 goto fail; 538 } 539 540 for (i = 0x8000; i; i >>= 1) { 541 SIO_CLR(SIS_MII_CLK); 542 DELAY(1); 543 if (!ack) { 544 if (CSR_READ_4(sc, SIS_EECTL) & SIS_MII_DATA) 545 frame->mii_data |= i; 546 DELAY(1); 547 } 548 SIO_SET(SIS_MII_CLK); 549 DELAY(1); 550 } 551 552 fail: 553 554 SIO_CLR(SIS_MII_CLK); 555 DELAY(1); 556 SIO_SET(SIS_MII_CLK); 557 DELAY(1); 558 559 if (ack) 560 return(1); 561 return(0); 562 } 563 564 /* 565 * Write to a PHY register through the MII. 566 */ 567 static int 568 sis_mii_writereg(struct sis_softc *sc, struct sis_mii_frame *frame) 569 { 570 /* 571 * Set up frame for TX. 572 */ 573 574 frame->mii_stdelim = SIS_MII_STARTDELIM; 575 frame->mii_opcode = SIS_MII_WRITEOP; 576 frame->mii_turnaround = SIS_MII_TURNAROUND; 577 578 /* 579 * Turn on data output. 580 */ 581 SIO_SET(SIS_MII_DIR); 582 583 sis_mii_sync(sc); 584 585 sis_mii_send(sc, frame->mii_stdelim, 2); 586 sis_mii_send(sc, frame->mii_opcode, 2); 587 sis_mii_send(sc, frame->mii_phyaddr, 5); 588 sis_mii_send(sc, frame->mii_regaddr, 5); 589 sis_mii_send(sc, frame->mii_turnaround, 2); 590 sis_mii_send(sc, frame->mii_data, 16); 591 592 /* Idle bit. */ 593 SIO_SET(SIS_MII_CLK); 594 DELAY(1); 595 SIO_CLR(SIS_MII_CLK); 596 DELAY(1); 597 598 /* 599 * Turn off xmit. 600 */ 601 SIO_CLR(SIS_MII_DIR); 602 603 return(0); 604 } 605 606 static int 607 sis_miibus_readreg(device_t dev, int phy, int reg) 608 { 609 struct sis_softc *sc; 610 struct sis_mii_frame frame; 611 612 sc = device_get_softc(dev); 613 614 if (sc->sis_type == SIS_TYPE_83815) { 615 if (phy != 0) 616 return(0); 617 /* 618 * The NatSemi chip can take a while after 619 * a reset to come ready, during which the BMSR 620 * returns a value of 0. This is *never* supposed 621 * to happen: some of the BMSR bits are meant to 622 * be hardwired in the on position, and this can 623 * confuse the miibus code a bit during the probe 624 * and attach phase. So we make an effort to check 625 * for this condition and wait for it to clear. 626 */ 627 if (!CSR_READ_4(sc, NS_BMSR)) 628 DELAY(1000); 629 return CSR_READ_4(sc, NS_BMCR + (reg * 4)); 630 } 631 /* 632 * Chipsets < SIS_635 seem not to be able to read/write 633 * through mdio. Use the enhanced PHY access register 634 * again for them. 635 */ 636 if (sc->sis_type == SIS_TYPE_900 && 637 sc->sis_rev < SIS_REV_635) { 638 int i, val = 0; 639 640 if (phy != 0) 641 return(0); 642 643 CSR_WRITE_4(sc, SIS_PHYCTL, 644 (phy << 11) | (reg << 6) | SIS_PHYOP_READ); 645 SIS_SETBIT(sc, SIS_PHYCTL, SIS_PHYCTL_ACCESS); 646 647 for (i = 0; i < SIS_TIMEOUT; i++) { 648 if (!(CSR_READ_4(sc, SIS_PHYCTL) & SIS_PHYCTL_ACCESS)) 649 break; 650 } 651 652 if (i == SIS_TIMEOUT) { 653 device_printf(dev, "PHY failed to come ready\n"); 654 return(0); 655 } 656 657 val = (CSR_READ_4(sc, SIS_PHYCTL) >> 16) & 0xFFFF; 658 659 if (val == 0xFFFF) 660 return(0); 661 662 return(val); 663 } else { 664 bzero((char *)&frame, sizeof(frame)); 665 666 frame.mii_phyaddr = phy; 667 frame.mii_regaddr = reg; 668 sis_mii_readreg(sc, &frame); 669 670 return(frame.mii_data); 671 } 672 } 673 674 static int 675 sis_miibus_writereg(device_t dev, int phy, int reg, int data) 676 { 677 struct sis_softc *sc; 678 struct sis_mii_frame frame; 679 680 sc = device_get_softc(dev); 681 682 if (sc->sis_type == SIS_TYPE_83815) { 683 if (phy != 0) 684 return(0); 685 CSR_WRITE_4(sc, NS_BMCR + (reg * 4), data); 686 return(0); 687 } 688 689 if (sc->sis_type == SIS_TYPE_900 && 690 sc->sis_rev < SIS_REV_635) { 691 int i; 692 693 if (phy != 0) 694 return(0); 695 696 CSR_WRITE_4(sc, SIS_PHYCTL, (data << 16) | (phy << 11) | 697 (reg << 6) | SIS_PHYOP_WRITE); 698 SIS_SETBIT(sc, SIS_PHYCTL, SIS_PHYCTL_ACCESS); 699 700 for (i = 0; i < SIS_TIMEOUT; i++) { 701 if (!(CSR_READ_4(sc, SIS_PHYCTL) & SIS_PHYCTL_ACCESS)) 702 break; 703 } 704 705 if (i == SIS_TIMEOUT) 706 device_printf(dev, "PHY failed to come ready\n"); 707 } else { 708 bzero((char *)&frame, sizeof(frame)); 709 710 frame.mii_phyaddr = phy; 711 frame.mii_regaddr = reg; 712 frame.mii_data = data; 713 sis_mii_writereg(sc, &frame); 714 } 715 return(0); 716 } 717 718 static void 719 sis_miibus_statchg(device_t dev) 720 { 721 struct sis_softc *sc; 722 723 sc = device_get_softc(dev); 724 sis_init(sc); 725 } 726 727 static uint32_t 728 sis_mchash(struct sis_softc *sc, const uint8_t *addr) 729 { 730 uint32_t crc, carry; 731 int i, j; 732 uint8_t c; 733 734 /* Compute CRC for the address value. */ 735 crc = 0xFFFFFFFF; /* initial value */ 736 737 for (i = 0; i < 6; i++) { 738 c = *(addr + i); 739 for (j = 0; j < 8; j++) { 740 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 741 crc <<= 1; 742 c >>= 1; 743 if (carry) 744 crc = (crc ^ 0x04c11db6) | carry; 745 } 746 } 747 748 /* 749 * return the filter bit position 750 * 751 * The NatSemi chip has a 512-bit filter, which is 752 * different than the SiS, so we special-case it. 753 */ 754 if (sc->sis_type == SIS_TYPE_83815) 755 return (crc >> 23); 756 else if (sc->sis_rev >= SIS_REV_635 || sc->sis_rev == SIS_REV_900B) 757 return (crc >> 24); 758 else 759 return (crc >> 25); 760 } 761 762 static void 763 sis_setmulti_ns(struct sis_softc *sc) 764 { 765 struct ifnet *ifp; 766 struct ifmultiaddr *ifma; 767 uint32_t h = 0, i, filtsave; 768 int bit, index; 769 770 ifp = &sc->arpcom.ac_if; 771 772 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 773 SIS_CLRBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_MCHASH); 774 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLMULTI); 775 return; 776 } 777 778 /* 779 * We have to explicitly enable the multicast hash table 780 * on the NatSemi chip if we want to use it, which we do. 781 */ 782 SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_MCHASH); 783 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLMULTI); 784 785 filtsave = CSR_READ_4(sc, SIS_RXFILT_CTL); 786 787 /* first, zot all the existing hash bits */ 788 for (i = 0; i < 32; i++) { 789 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_FMEM_LO + (i*2)); 790 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 0); 791 } 792 793 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 794 if (ifma->ifma_addr->sa_family != AF_LINK) 795 continue; 796 h = sis_mchash(sc, 797 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 798 index = h >> 3; 799 bit = h & 0x1F; 800 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_FMEM_LO + index); 801 if (bit > 0xF) 802 bit -= 0x10; 803 SIS_SETBIT(sc, SIS_RXFILT_DATA, (1 << bit)); 804 } 805 806 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave); 807 } 808 809 static void 810 sis_setmulti_sis(struct sis_softc *sc) 811 { 812 struct ifnet *ifp; 813 struct ifmultiaddr *ifma; 814 uint32_t h, i, n, ctl; 815 uint16_t hashes[16]; 816 817 ifp = &sc->arpcom.ac_if; 818 819 /* hash table size */ 820 if (sc->sis_rev >= SIS_REV_635 || sc->sis_rev == SIS_REV_900B) 821 n = 16; 822 else 823 n = 8; 824 825 ctl = CSR_READ_4(sc, SIS_RXFILT_CTL) & SIS_RXFILTCTL_ENABLE; 826 827 if (ifp->if_flags & IFF_BROADCAST) 828 ctl |= SIS_RXFILTCTL_BROAD; 829 830 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 831 ctl |= SIS_RXFILTCTL_ALLMULTI; 832 if (ifp->if_flags & IFF_PROMISC) 833 ctl |= SIS_RXFILTCTL_BROAD|SIS_RXFILTCTL_ALLPHYS; 834 for (i = 0; i < n; i++) 835 hashes[i] = ~0; 836 } else { 837 for (i = 0; i < n; i++) 838 hashes[i] = 0; 839 i = 0; 840 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 841 if (ifma->ifma_addr->sa_family != AF_LINK) 842 continue; 843 h = sis_mchash(sc, 844 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 845 hashes[h >> 4] |= 1 << (h & 0xf); 846 i++; 847 } 848 if (i > n) { 849 ctl |= SIS_RXFILTCTL_ALLMULTI; 850 for (i = 0; i < n; i++) 851 hashes[i] = ~0; 852 } 853 } 854 855 for (i = 0; i < n; i++) { 856 CSR_WRITE_4(sc, SIS_RXFILT_CTL, (4 + i) << 16); 857 CSR_WRITE_4(sc, SIS_RXFILT_DATA, hashes[i]); 858 } 859 860 CSR_WRITE_4(sc, SIS_RXFILT_CTL, ctl); 861 } 862 863 static void 864 sis_reset(struct sis_softc *sc) 865 { 866 struct ifnet *ifp = &sc->arpcom.ac_if; 867 int i; 868 869 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RESET); 870 871 for (i = 0; i < SIS_TIMEOUT; i++) { 872 if (!(CSR_READ_4(sc, SIS_CSR) & SIS_CSR_RESET)) 873 break; 874 } 875 876 if (i == SIS_TIMEOUT) 877 if_printf(ifp, "reset never completed\n"); 878 879 /* Wait a little while for the chip to get its brains in order. */ 880 DELAY(1000); 881 882 /* 883 * If this is a NetSemi chip, make sure to clear 884 * PME mode. 885 */ 886 if (sc->sis_type == SIS_TYPE_83815) { 887 CSR_WRITE_4(sc, NS_CLKRUN, NS_CLKRUN_PMESTS); 888 CSR_WRITE_4(sc, NS_CLKRUN, 0); 889 } 890 } 891 892 /* 893 * Probe for an SiS chip. Check the PCI vendor and device 894 * IDs against our list and return a device name if we find a match. 895 */ 896 static int 897 sis_probe(device_t dev) 898 { 899 struct sis_type *t; 900 901 t = sis_devs; 902 903 while(t->sis_name != NULL) { 904 if ((pci_get_vendor(dev) == t->sis_vid) && 905 (pci_get_device(dev) == t->sis_did)) { 906 device_set_desc(dev, t->sis_name); 907 return(0); 908 } 909 t++; 910 } 911 912 return(ENXIO); 913 } 914 915 /* 916 * Attach the interface. Allocate softc structures, do ifmedia 917 * setup and ethernet/BPF attach. 918 */ 919 static int 920 sis_attach(device_t dev) 921 { 922 uint8_t eaddr[ETHER_ADDR_LEN]; 923 uint32_t command; 924 struct sis_softc *sc; 925 struct ifnet *ifp; 926 int error, rid, waittime; 927 928 error = waittime = 0; 929 sc = device_get_softc(dev); 930 931 if (pci_get_device(dev) == PCI_PRODUCT_SIS_900) 932 sc->sis_type = SIS_TYPE_900; 933 if (pci_get_device(dev) == PCI_PRODUCT_SIS_7016) 934 sc->sis_type = SIS_TYPE_7016; 935 if (pci_get_vendor(dev) == PCI_VENDOR_NS) 936 sc->sis_type = SIS_TYPE_83815; 937 938 sc->sis_rev = pci_read_config(dev, PCIR_REVID, 1); 939 940 /* 941 * Handle power management nonsense. 942 */ 943 944 command = pci_read_config(dev, SIS_PCI_CAPID, 4) & 0x000000FF; 945 if (command == 0x01) { 946 947 command = pci_read_config(dev, SIS_PCI_PWRMGMTCTRL, 4); 948 if (command & SIS_PSTATE_MASK) { 949 uint32_t iobase, membase, irq; 950 951 /* Save important PCI config data. */ 952 iobase = pci_read_config(dev, SIS_PCI_LOIO, 4); 953 membase = pci_read_config(dev, SIS_PCI_LOMEM, 4); 954 irq = pci_read_config(dev, SIS_PCI_INTLINE, 4); 955 956 /* Reset the power state. */ 957 device_printf(dev, "chip is in D%d power mode " 958 "-- setting to D0\n", command & SIS_PSTATE_MASK); 959 command &= 0xFFFFFFFC; 960 pci_write_config(dev, SIS_PCI_PWRMGMTCTRL, command, 4); 961 962 /* Restore PCI config data. */ 963 pci_write_config(dev, SIS_PCI_LOIO, iobase, 4); 964 pci_write_config(dev, SIS_PCI_LOMEM, membase, 4); 965 pci_write_config(dev, SIS_PCI_INTLINE, irq, 4); 966 } 967 } 968 969 /* 970 * Map control/status registers. 971 */ 972 command = pci_read_config(dev, PCIR_COMMAND, 4); 973 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 974 pci_write_config(dev, PCIR_COMMAND, command, 4); 975 command = pci_read_config(dev, PCIR_COMMAND, 4); 976 977 #ifdef SIS_USEIOSPACE 978 if (!(command & PCIM_CMD_PORTEN)) { 979 device_printf(dev, "failed to enable I/O ports!\n"); 980 error = ENXIO; 981 goto fail; 982 } 983 #else 984 if (!(command & PCIM_CMD_MEMEN)) { 985 device_printf(dev, "failed to enable memory mapping!\n"); 986 error = ENXIO; 987 goto fail; 988 } 989 #endif 990 991 rid = SIS_RID; 992 sc->sis_res = bus_alloc_resource_any(dev, SIS_RES, &rid, RF_ACTIVE); 993 994 if (sc->sis_res == NULL) { 995 device_printf(dev, "couldn't map ports/memory\n"); 996 error = ENXIO; 997 goto fail; 998 } 999 1000 sc->sis_btag = rman_get_bustag(sc->sis_res); 1001 sc->sis_bhandle = rman_get_bushandle(sc->sis_res); 1002 1003 /* Allocate interrupt */ 1004 rid = 0; 1005 sc->sis_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1006 RF_SHAREABLE | RF_ACTIVE); 1007 1008 if (sc->sis_irq == NULL) { 1009 device_printf(dev, "couldn't map interrupt\n"); 1010 error = ENXIO; 1011 goto fail; 1012 } 1013 1014 /* Reset the adapter. */ 1015 sis_reset(sc); 1016 1017 if (sc->sis_type == SIS_TYPE_900 && 1018 (sc->sis_rev == SIS_REV_635 || 1019 sc->sis_rev == SIS_REV_900B)) { 1020 SIO_SET(SIS_CFG_RND_CNT); 1021 SIO_SET(SIS_CFG_PERR_DETECT); 1022 } 1023 1024 /* 1025 * Get station address from the EEPROM. 1026 */ 1027 switch (pci_get_vendor(dev)) { 1028 case PCI_VENDOR_NS: 1029 /* 1030 * Reading the MAC address out of the EEPROM on 1031 * the NatSemi chip takes a bit more work than 1032 * you'd expect. The address spans 4 16-bit words, 1033 * with the first word containing only a single bit. 1034 * You have to shift everything over one bit to 1035 * get it aligned properly. Also, the bits are 1036 * stored backwards (the LSB is really the MSB, 1037 * and so on) so you have to reverse them in order 1038 * to get the MAC address into the form we want. 1039 * Why? Who the hell knows. 1040 */ 1041 { 1042 uint16_t tmp[4]; 1043 1044 sis_read_eeprom(sc, (caddr_t)&tmp, 1045 NS_EE_NODEADDR, 4, 0); 1046 1047 /* Shift everything over one bit. */ 1048 tmp[3] = tmp[3] >> 1; 1049 tmp[3] |= tmp[2] << 15; 1050 tmp[2] = tmp[2] >> 1; 1051 tmp[2] |= tmp[1] << 15; 1052 tmp[1] = tmp[1] >> 1; 1053 tmp[1] |= tmp[0] << 15; 1054 1055 /* Now reverse all the bits. */ 1056 tmp[3] = sis_reverse(tmp[3]); 1057 tmp[2] = sis_reverse(tmp[2]); 1058 tmp[1] = sis_reverse(tmp[1]); 1059 1060 bcopy((char *)&tmp[1], eaddr, ETHER_ADDR_LEN); 1061 } 1062 break; 1063 case PCI_VENDOR_SIS: 1064 default: 1065 #ifdef __i386__ 1066 /* 1067 * If this is a SiS 630E chipset with an embedded 1068 * SiS 900 controller, we have to read the MAC address 1069 * from the APC CMOS RAM. Our method for doing this 1070 * is very ugly since we have to reach out and grab 1071 * ahold of hardware for which we cannot properly 1072 * allocate resources. This code is only compiled on 1073 * the i386 architecture since the SiS 630E chipset 1074 * is for x86 motherboards only. Note that there are 1075 * a lot of magic numbers in this hack. These are 1076 * taken from SiS's Linux driver. I'd like to replace 1077 * them with proper symbolic definitions, but that 1078 * requires some datasheets that I don't have access 1079 * to at the moment. 1080 */ 1081 if (sc->sis_rev == SIS_REV_630S || 1082 sc->sis_rev == SIS_REV_630E || 1083 sc->sis_rev == SIS_REV_630EA1) 1084 sis_read_cmos(sc, dev, (caddr_t)&eaddr, 0x9, 6); 1085 1086 else if (sc->sis_rev == SIS_REV_635 || 1087 sc->sis_rev == SIS_REV_630ET) 1088 sis_read_mac(sc, dev, (caddr_t)&eaddr); 1089 else if (sc->sis_rev == SIS_REV_96x) { 1090 /* 1091 * Allow to read EEPROM from LAN. It is shared 1092 * between a 1394 controller and the NIC and each 1093 * time we access it, we need to set SIS_EECMD_REQ. 1094 */ 1095 SIO_SET(SIS_EECMD_REQ); 1096 for (waittime = 0; waittime < SIS_TIMEOUT; 1097 waittime++) { 1098 /* Force EEPROM to idle state. */ 1099 sis_eeprom_idle(sc); 1100 if (CSR_READ_4(sc, SIS_EECTL) & SIS_EECMD_GNT) { 1101 sis_read_eeprom(sc, (caddr_t)&eaddr, 1102 SIS_EE_NODEADDR, 3, 0); 1103 break; 1104 } 1105 DELAY(1); 1106 } 1107 /* 1108 * Set SIS_EECTL_CLK to high, so a other master 1109 * can operate on the i2c bus. 1110 */ 1111 SIO_SET(SIS_EECTL_CLK); 1112 /* Refuse EEPROM access by LAN */ 1113 SIO_SET(SIS_EECMD_DONE); 1114 } else 1115 #endif 1116 sis_read_eeprom(sc, (caddr_t)&eaddr, 1117 SIS_EE_NODEADDR, 3, 0); 1118 break; 1119 } 1120 1121 callout_init(&sc->sis_timer); 1122 1123 error = sis_dma_alloc(dev); 1124 if (error) 1125 goto fail; 1126 1127 ifp = &sc->arpcom.ac_if; 1128 ifp->if_softc = sc; 1129 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1130 ifp->if_mtu = ETHERMTU; 1131 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1132 ifp->if_ioctl = sis_ioctl; 1133 ifp->if_start = sis_start; 1134 ifp->if_watchdog = sis_watchdog; 1135 ifp->if_init = sis_init; 1136 ifp->if_baudrate = 10000000; 1137 ifq_set_maxlen(&ifp->if_snd, SIS_TX_LIST_CNT - 1); 1138 ifq_set_ready(&ifp->if_snd); 1139 #ifdef DEVICE_POLLING 1140 ifp->if_poll = sis_poll; 1141 #endif 1142 ifp->if_capenable = ifp->if_capabilities; 1143 1144 /* 1145 * Do MII setup. 1146 */ 1147 if (mii_phy_probe(dev, &sc->sis_miibus, 1148 sis_ifmedia_upd, sis_ifmedia_sts)) { 1149 device_printf(dev, "MII without any PHY!\n"); 1150 error = ENXIO; 1151 goto fail; 1152 } 1153 1154 /* 1155 * Call MI attach routine. 1156 */ 1157 ether_ifattach(ifp, eaddr, NULL); 1158 1159 /* 1160 * Tell the upper layer(s) we support long frames. 1161 */ 1162 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1163 1164 error = bus_setup_intr(dev, sc->sis_irq, INTR_MPSAFE, 1165 sis_intr, sc, 1166 &sc->sis_intrhand, 1167 ifp->if_serializer); 1168 1169 if (error) { 1170 device_printf(dev, "couldn't set up irq\n"); 1171 ether_ifdetach(ifp); 1172 goto fail; 1173 } 1174 1175 ifp->if_cpuid = rman_get_cpuid(sc->sis_irq); 1176 KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus); 1177 1178 fail: 1179 if (error) 1180 sis_detach(dev); 1181 1182 return(error); 1183 } 1184 1185 /* 1186 * Shutdown hardware and free up resources. It is called in both the error case 1187 * and the normal detach case so it needs to be careful about only freeing 1188 * resources that have actually been allocated. 1189 */ 1190 static int 1191 sis_detach(device_t dev) 1192 { 1193 struct sis_softc *sc = device_get_softc(dev); 1194 struct ifnet *ifp = &sc->arpcom.ac_if; 1195 1196 1197 if (device_is_attached(dev)) { 1198 lwkt_serialize_enter(ifp->if_serializer); 1199 sis_reset(sc); 1200 sis_stop(sc); 1201 bus_teardown_intr(dev, sc->sis_irq, sc->sis_intrhand); 1202 lwkt_serialize_exit(ifp->if_serializer); 1203 1204 ether_ifdetach(ifp); 1205 } 1206 if (sc->sis_miibus) 1207 device_delete_child(dev, sc->sis_miibus); 1208 bus_generic_detach(dev); 1209 1210 if (sc->sis_irq) 1211 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sis_irq); 1212 if (sc->sis_res) 1213 bus_release_resource(dev, SIS_RES, SIS_RID, sc->sis_res); 1214 1215 sis_dma_free(dev); 1216 1217 return(0); 1218 } 1219 1220 /* 1221 * Initialize the transmit descriptors. 1222 */ 1223 static int 1224 sis_list_tx_init(struct sis_softc *sc) 1225 { 1226 struct sis_list_data *ld = &sc->sis_ldata; 1227 struct sis_chain_data *cd = &sc->sis_cdata; 1228 int i, nexti; 1229 1230 for (i = 0; i < SIS_TX_LIST_CNT; i++) { 1231 bus_addr_t paddr; 1232 1233 /* 1234 * Link the TX desc together 1235 */ 1236 nexti = (i == (SIS_TX_LIST_CNT - 1)) ? 0 : i+1; 1237 paddr = ld->sis_tx_paddr + (nexti * sizeof(struct sis_desc)); 1238 ld->sis_tx_list[i].sis_next = paddr; 1239 } 1240 cd->sis_tx_prod = cd->sis_tx_cons = cd->sis_tx_cnt = 0; 1241 1242 return 0; 1243 } 1244 1245 /* 1246 * Initialize the RX descriptors and allocate mbufs for them. Note that 1247 * we arrange the descriptors in a closed ring, so that the last descriptor 1248 * points back to the first. 1249 */ 1250 static int 1251 sis_list_rx_init(struct sis_softc *sc) 1252 { 1253 struct sis_list_data *ld = &sc->sis_ldata; 1254 struct sis_chain_data *cd = &sc->sis_cdata; 1255 int i, error; 1256 1257 for (i = 0; i < SIS_RX_LIST_CNT; i++) { 1258 bus_addr_t paddr; 1259 int nexti; 1260 1261 error = sis_newbuf(sc, i, 1); 1262 if (error) 1263 return error; 1264 1265 /* 1266 * Link the RX desc together 1267 */ 1268 nexti = (i == (SIS_RX_LIST_CNT - 1)) ? 0 : i+1; 1269 paddr = ld->sis_rx_paddr + (nexti * sizeof(struct sis_desc)); 1270 ld->sis_rx_list[i].sis_next = paddr; 1271 } 1272 cd->sis_rx_prod = 0; 1273 1274 return 0; 1275 } 1276 1277 /* 1278 * Initialize an RX descriptor and attach an MBUF cluster. 1279 */ 1280 static int 1281 sis_newbuf(struct sis_softc *sc, int idx, int init) 1282 { 1283 struct sis_chain_data *cd = &sc->sis_cdata; 1284 struct sis_rx_data *rd = &cd->sis_rx_data[idx]; 1285 bus_dma_segment_t seg; 1286 bus_dmamap_t map; 1287 struct mbuf *m; 1288 int nseg, error; 1289 1290 m = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR); 1291 if (m == NULL) { 1292 if (init) 1293 if_printf(&sc->arpcom.ac_if, "can't alloc RX mbuf\n"); 1294 return ENOBUFS; 1295 } 1296 m->m_len = m->m_pkthdr.len = MCLBYTES; 1297 1298 /* Try loading the mbuf into tmp DMA map */ 1299 error = bus_dmamap_load_mbuf_segment(cd->sis_rxbuf_tag, 1300 cd->sis_rx_tmpmap, m, &seg, 1, &nseg, BUS_DMA_NOWAIT); 1301 if (error) { 1302 m_freem(m); 1303 if (init) 1304 if_printf(&sc->arpcom.ac_if, "can't load RX mbuf\n"); 1305 return error; 1306 } 1307 1308 /* Unload the currently loaded mbuf */ 1309 if (rd->sis_mbuf != NULL) { 1310 bus_dmamap_sync(cd->sis_rxbuf_tag, rd->sis_map, 1311 BUS_DMASYNC_POSTREAD); 1312 bus_dmamap_unload(cd->sis_rxbuf_tag, rd->sis_map); 1313 } 1314 1315 /* Swap DMA maps */ 1316 map = cd->sis_rx_tmpmap; 1317 cd->sis_rx_tmpmap = rd->sis_map; 1318 rd->sis_map = map; 1319 1320 /* Save necessary information */ 1321 rd->sis_mbuf = m; 1322 rd->sis_paddr = seg.ds_addr; 1323 1324 sis_setup_rxdesc(sc, idx); 1325 return 0; 1326 } 1327 1328 static void 1329 sis_setup_rxdesc(struct sis_softc *sc, int idx) 1330 { 1331 struct sis_desc *c = &sc->sis_ldata.sis_rx_list[idx]; 1332 1333 /* Setup the RX desc */ 1334 c->sis_ctl = SIS_RXLEN; 1335 c->sis_ptr = sc->sis_cdata.sis_rx_data[idx].sis_paddr; 1336 } 1337 1338 /* 1339 * A frame has been uploaded: pass the resulting mbuf chain up to 1340 * the higher level protocols. 1341 */ 1342 static void 1343 sis_rxeof(struct sis_softc *sc) 1344 { 1345 struct ifnet *ifp = &sc->arpcom.ac_if; 1346 int i, total_len = 0; 1347 uint32_t rxstat; 1348 1349 i = sc->sis_cdata.sis_rx_prod; 1350 while (SIS_OWNDESC(&sc->sis_ldata.sis_rx_list[i])) { 1351 struct sis_desc *cur_rx; 1352 struct sis_rx_data *rd; 1353 struct mbuf *m; 1354 int idx = i; 1355 1356 #ifdef DEVICE_POLLING 1357 if (ifp->if_flags & IFF_POLLING) { 1358 if (sc->rxcycles <= 0) 1359 break; 1360 sc->rxcycles--; 1361 } 1362 #endif /* DEVICE_POLLING */ 1363 1364 cur_rx = &sc->sis_ldata.sis_rx_list[idx]; 1365 rd = &sc->sis_cdata.sis_rx_data[idx]; 1366 1367 rxstat = cur_rx->sis_rxstat; 1368 total_len = SIS_RXBYTES(cur_rx); 1369 1370 m = rd->sis_mbuf; 1371 1372 SIS_INC(i, SIS_RX_LIST_CNT); 1373 1374 /* 1375 * If an error occurs, update stats, clear the 1376 * status word and leave the mbuf cluster in place: 1377 * it should simply get re-used next time this descriptor 1378 * comes up in the ring. 1379 */ 1380 if (!(rxstat & SIS_CMDSTS_PKT_OK)) { 1381 ifp->if_ierrors++; 1382 if (rxstat & SIS_RXSTAT_COLL) 1383 ifp->if_collisions++; 1384 sis_setup_rxdesc(sc, idx); 1385 continue; 1386 } 1387 1388 /* No errors; receive the packet. */ 1389 if (sis_newbuf(sc, idx, 0) == 0) { 1390 m->m_pkthdr.len = m->m_len = total_len; 1391 m->m_pkthdr.rcvif = ifp; 1392 } else { 1393 ifp->if_ierrors++; 1394 sis_setup_rxdesc(sc, idx); 1395 continue; 1396 } 1397 1398 ifp->if_ipackets++; 1399 ifp->if_input(ifp, m); 1400 } 1401 sc->sis_cdata.sis_rx_prod = i; 1402 } 1403 1404 static void 1405 sis_rxeoc(struct sis_softc *sc) 1406 { 1407 sis_rxeof(sc); 1408 sis_init(sc); 1409 } 1410 1411 /* 1412 * A frame was downloaded to the chip. It's safe for us to clean up 1413 * the list buffers. 1414 */ 1415 1416 static void 1417 sis_txeof(struct sis_softc *sc) 1418 { 1419 struct ifnet *ifp = &sc->arpcom.ac_if; 1420 struct sis_chain_data *cd = &sc->sis_cdata; 1421 uint32_t idx; 1422 1423 /* 1424 * Go through our tx list and free mbufs for those 1425 * frames that have been transmitted. 1426 */ 1427 for (idx = sc->sis_cdata.sis_tx_cons; sc->sis_cdata.sis_tx_cnt > 0; 1428 sc->sis_cdata.sis_tx_cnt--, SIS_INC(idx, SIS_TX_LIST_CNT) ) { 1429 struct sis_desc *cur_tx; 1430 struct sis_tx_data *td; 1431 1432 cur_tx = &sc->sis_ldata.sis_tx_list[idx]; 1433 td = &cd->sis_tx_data[idx]; 1434 1435 if (SIS_OWNDESC(cur_tx)) 1436 break; 1437 1438 if (cur_tx->sis_ctl & SIS_CMDSTS_MORE) 1439 continue; 1440 1441 if (!(cur_tx->sis_ctl & SIS_CMDSTS_PKT_OK)) { 1442 ifp->if_oerrors++; 1443 if (cur_tx->sis_txstat & SIS_TXSTAT_EXCESSCOLLS) 1444 ifp->if_collisions++; 1445 if (cur_tx->sis_txstat & SIS_TXSTAT_OUTOFWINCOLL) 1446 ifp->if_collisions++; 1447 } 1448 1449 ifp->if_collisions += 1450 (cur_tx->sis_txstat & SIS_TXSTAT_COLLCNT) >> 16; 1451 1452 ifp->if_opackets++; 1453 if (td->sis_mbuf != NULL) { 1454 bus_dmamap_unload(cd->sis_txbuf_tag, td->sis_map); 1455 m_freem(td->sis_mbuf); 1456 td->sis_mbuf = NULL; 1457 } 1458 } 1459 1460 if (idx != sc->sis_cdata.sis_tx_cons) { 1461 /* we freed up some buffers */ 1462 sc->sis_cdata.sis_tx_cons = idx; 1463 } 1464 1465 if (cd->sis_tx_cnt == 0) 1466 ifp->if_timer = 0; 1467 if (!SIS_IS_OACTIVE(sc)) 1468 ifp->if_flags &= ~IFF_OACTIVE; 1469 } 1470 1471 static void 1472 sis_tick(void *xsc) 1473 { 1474 struct sis_softc *sc = xsc; 1475 struct mii_data *mii; 1476 struct ifnet *ifp = &sc->arpcom.ac_if; 1477 1478 lwkt_serialize_enter(ifp->if_serializer); 1479 1480 mii = device_get_softc(sc->sis_miibus); 1481 mii_tick(mii); 1482 1483 if (!sc->sis_link) { 1484 mii_pollstat(mii); 1485 if (mii->mii_media_status & IFM_ACTIVE && 1486 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 1487 sc->sis_link++; 1488 if (!ifq_is_empty(&ifp->if_snd)) 1489 if_devstart(ifp); 1490 } 1491 1492 callout_reset(&sc->sis_timer, hz, sis_tick, sc); 1493 lwkt_serialize_exit(ifp->if_serializer); 1494 } 1495 1496 #ifdef DEVICE_POLLING 1497 1498 static void 1499 sis_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1500 { 1501 struct sis_softc *sc = ifp->if_softc; 1502 1503 switch(cmd) { 1504 case POLL_REGISTER: 1505 /* disable interrupts */ 1506 CSR_WRITE_4(sc, SIS_IER, 0); 1507 break; 1508 case POLL_DEREGISTER: 1509 /* enable interrupts */ 1510 CSR_WRITE_4(sc, SIS_IER, 1); 1511 break; 1512 default: 1513 /* 1514 * On the sis, reading the status register also clears it. 1515 * So before returning to intr mode we must make sure that all 1516 * possible pending sources of interrupts have been served. 1517 * In practice this means run to completion the *eof routines, 1518 * and then call the interrupt routine 1519 */ 1520 sc->rxcycles = count; 1521 sis_rxeof(sc); 1522 sis_txeof(sc); 1523 if (!ifq_is_empty(&ifp->if_snd)) 1524 if_devstart(ifp); 1525 1526 if (sc->rxcycles > 0 || cmd == POLL_AND_CHECK_STATUS) { 1527 uint32_t status; 1528 1529 /* Reading the ISR register clears all interrupts. */ 1530 status = CSR_READ_4(sc, SIS_ISR); 1531 1532 if (status & (SIS_ISR_RX_ERR|SIS_ISR_RX_OFLOW)) 1533 sis_rxeoc(sc); 1534 1535 if (status & (SIS_ISR_RX_IDLE)) 1536 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE); 1537 1538 if (status & SIS_ISR_SYSERR) { 1539 sis_reset(sc); 1540 sis_init(sc); 1541 } 1542 } 1543 break; 1544 } 1545 } 1546 #endif /* DEVICE_POLLING */ 1547 1548 static void 1549 sis_intr(void *arg) 1550 { 1551 struct sis_softc *sc; 1552 struct ifnet *ifp; 1553 uint32_t status; 1554 1555 sc = arg; 1556 ifp = &sc->arpcom.ac_if; 1557 1558 /* Supress unwanted interrupts */ 1559 if (!(ifp->if_flags & IFF_UP)) { 1560 sis_stop(sc); 1561 return; 1562 } 1563 1564 /* Disable interrupts. */ 1565 CSR_WRITE_4(sc, SIS_IER, 0); 1566 1567 for (;;) { 1568 /* Reading the ISR register clears all interrupts. */ 1569 status = CSR_READ_4(sc, SIS_ISR); 1570 1571 if ((status & SIS_INTRS) == 0) 1572 break; 1573 1574 if (status & 1575 (SIS_ISR_TX_DESC_OK | SIS_ISR_TX_ERR | SIS_ISR_TX_OK | 1576 SIS_ISR_TX_IDLE) ) 1577 sis_txeof(sc); 1578 1579 if (status & 1580 (SIS_ISR_RX_DESC_OK | SIS_ISR_RX_OK | SIS_ISR_RX_IDLE)) 1581 sis_rxeof(sc); 1582 1583 if (status & (SIS_ISR_RX_ERR | SIS_ISR_RX_OFLOW)) 1584 sis_rxeoc(sc); 1585 1586 if (status & (SIS_ISR_RX_IDLE)) 1587 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE); 1588 1589 if (status & SIS_ISR_SYSERR) { 1590 sis_reset(sc); 1591 sis_init(sc); 1592 } 1593 } 1594 1595 /* Re-enable interrupts. */ 1596 CSR_WRITE_4(sc, SIS_IER, 1); 1597 1598 if (!ifq_is_empty(&ifp->if_snd)) 1599 if_devstart(ifp); 1600 } 1601 1602 /* 1603 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1604 * pointers to the fragment pointers. 1605 */ 1606 static int 1607 sis_encap(struct sis_softc *sc, struct mbuf **m_head, uint32_t *txidx) 1608 { 1609 struct sis_chain_data *cd = &sc->sis_cdata; 1610 struct sis_list_data *ld = &sc->sis_ldata; 1611 bus_dma_segment_t segs[SIS_NSEGS]; 1612 bus_dmamap_t map; 1613 int frag, cur, maxsegs, nsegs, error, i; 1614 1615 maxsegs = SIS_TX_LIST_CNT - SIS_NSEGS_RESERVED - cd->sis_tx_cnt; 1616 KASSERT(maxsegs >= 1, ("not enough TX descs\n")); 1617 if (maxsegs > SIS_NSEGS) 1618 maxsegs = SIS_NSEGS; 1619 1620 map = cd->sis_tx_data[*txidx].sis_map; 1621 error = bus_dmamap_load_mbuf_defrag(cd->sis_txbuf_tag, map, m_head, 1622 segs, maxsegs, &nsegs, BUS_DMA_NOWAIT); 1623 if (error) { 1624 m_freem(*m_head); 1625 *m_head = NULL; 1626 return error; 1627 } 1628 bus_dmamap_sync(cd->sis_txbuf_tag, map, BUS_DMASYNC_PREWRITE); 1629 1630 cur = frag = *txidx; 1631 for (i = 0; i < nsegs; ++i) { 1632 struct sis_desc *f = &ld->sis_tx_list[frag]; 1633 1634 f->sis_ctl = SIS_CMDSTS_MORE | segs[i].ds_len; 1635 f->sis_ptr = segs[i].ds_addr; 1636 if (i != 0) 1637 f->sis_ctl |= SIS_CMDSTS_OWN; 1638 1639 cur = frag; 1640 SIS_INC(frag, SIS_TX_LIST_CNT); 1641 } 1642 ld->sis_tx_list[cur].sis_ctl &= ~SIS_CMDSTS_MORE; 1643 ld->sis_tx_list[*txidx].sis_ctl |= SIS_CMDSTS_OWN; 1644 1645 /* Swap DMA map */ 1646 cd->sis_tx_data[*txidx].sis_map = cd->sis_tx_data[cur].sis_map; 1647 cd->sis_tx_data[cur].sis_map = map; 1648 1649 cd->sis_tx_data[cur].sis_mbuf = *m_head; 1650 1651 cd->sis_tx_cnt += nsegs; 1652 *txidx = frag; 1653 1654 return 0; 1655 } 1656 1657 /* 1658 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1659 * to the mbuf data regions directly in the transmit lists. We also save a 1660 * copy of the pointers since the transmit list fragment pointers are 1661 * physical addresses. 1662 */ 1663 1664 static void 1665 sis_start(struct ifnet *ifp) 1666 { 1667 struct sis_softc *sc = ifp->if_softc; 1668 int need_trans, error; 1669 uint32_t idx; 1670 1671 if (!sc->sis_link) { 1672 ifq_purge(&ifp->if_snd); 1673 return; 1674 } 1675 1676 if ((ifp->if_flags & (IFF_OACTIVE | IFF_RUNNING)) != IFF_RUNNING) 1677 return; 1678 1679 idx = sc->sis_cdata.sis_tx_prod; 1680 need_trans = 0; 1681 1682 while (sc->sis_cdata.sis_tx_data[idx].sis_mbuf == NULL) { 1683 struct mbuf *m_head; 1684 1685 /* 1686 * If there's no way we can send any packets, return now. 1687 */ 1688 if (SIS_IS_OACTIVE(sc)) { 1689 ifp->if_flags |= IFF_OACTIVE; 1690 break; 1691 } 1692 1693 m_head = ifq_dequeue(&ifp->if_snd, NULL); 1694 if (m_head == NULL) 1695 break; 1696 1697 error = sis_encap(sc, &m_head, &idx); 1698 if (error) { 1699 ifp->if_oerrors++; 1700 if (sc->sis_cdata.sis_tx_cnt == 0) { 1701 continue; 1702 } else { 1703 ifp->if_flags |= IFF_OACTIVE; 1704 break; 1705 } 1706 } 1707 need_trans = 1; 1708 1709 /* 1710 * If there's a BPF listener, bounce a copy of this frame 1711 * to him. 1712 */ 1713 BPF_MTAP(ifp, m_head); 1714 } 1715 1716 if (!need_trans) 1717 return; 1718 1719 /* Transmit */ 1720 sc->sis_cdata.sis_tx_prod = idx; 1721 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_ENABLE); 1722 1723 /* 1724 * Set a timeout in case the chip goes out to lunch. 1725 */ 1726 ifp->if_timer = 5; 1727 } 1728 1729 static void 1730 sis_init(void *xsc) 1731 { 1732 struct sis_softc *sc = xsc; 1733 struct ifnet *ifp = &sc->arpcom.ac_if; 1734 struct mii_data *mii; 1735 1736 /* 1737 * Cancel pending I/O and free all RX/TX buffers. 1738 */ 1739 sis_stop(sc); 1740 1741 mii = device_get_softc(sc->sis_miibus); 1742 1743 /* Set MAC address */ 1744 if (sc->sis_type == SIS_TYPE_83815) { 1745 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR0); 1746 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1747 ((uint16_t *)sc->arpcom.ac_enaddr)[0]); 1748 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR1); 1749 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1750 ((uint16_t *)sc->arpcom.ac_enaddr)[1]); 1751 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR2); 1752 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1753 ((uint16_t *)sc->arpcom.ac_enaddr)[2]); 1754 } else { 1755 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR0); 1756 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1757 ((uint16_t *)sc->arpcom.ac_enaddr)[0]); 1758 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR1); 1759 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1760 ((uint16_t *)sc->arpcom.ac_enaddr)[1]); 1761 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR2); 1762 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1763 ((uint16_t *)sc->arpcom.ac_enaddr)[2]); 1764 } 1765 1766 /* Init circular RX list. */ 1767 if (sis_list_rx_init(sc)) { 1768 if_printf(ifp, "initialization failed: " 1769 "no memory for rx buffers\n"); 1770 sis_stop(sc); 1771 return; 1772 } 1773 1774 /* 1775 * Init tx descriptors. 1776 */ 1777 sis_list_tx_init(sc); 1778 1779 /* 1780 * For the NatSemi chip, we have to explicitly enable the 1781 * reception of ARP frames, as well as turn on the 'perfect 1782 * match' filter where we store the station address, otherwise 1783 * we won't receive unicasts meant for this host. 1784 */ 1785 if (sc->sis_type == SIS_TYPE_83815) { 1786 SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_ARP); 1787 SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_PERFECT); 1788 } 1789 1790 /* If we want promiscuous mode, set the allframes bit. */ 1791 if (ifp->if_flags & IFF_PROMISC) 1792 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLPHYS); 1793 else 1794 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLPHYS); 1795 1796 /* 1797 * Set the capture broadcast bit to capture broadcast frames. 1798 */ 1799 if (ifp->if_flags & IFF_BROADCAST) 1800 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_BROAD); 1801 else 1802 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_BROAD); 1803 1804 /* 1805 * Load the multicast filter. 1806 */ 1807 if (sc->sis_type == SIS_TYPE_83815) 1808 sis_setmulti_ns(sc); 1809 else 1810 sis_setmulti_sis(sc); 1811 1812 /* Turn the receive filter on */ 1813 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ENABLE); 1814 1815 /* 1816 * Load the address of the RX and TX lists. 1817 */ 1818 CSR_WRITE_4(sc, SIS_RX_LISTPTR, sc->sis_ldata.sis_rx_paddr); 1819 CSR_WRITE_4(sc, SIS_TX_LISTPTR, sc->sis_ldata.sis_tx_paddr); 1820 1821 /* SIS_CFG_EDB_MASTER_EN indicates the EDB bus is used instead of 1822 * the PCI bus. When this bit is set, the Max DMA Burst Size 1823 * for TX/RX DMA should be no larger than 16 double words. 1824 */ 1825 if (CSR_READ_4(sc, SIS_CFG) & SIS_CFG_EDB_MASTER_EN) 1826 CSR_WRITE_4(sc, SIS_RX_CFG, SIS_RXCFG64); 1827 else 1828 CSR_WRITE_4(sc, SIS_RX_CFG, SIS_RXCFG256); 1829 1830 /* Accept Long Packets for VLAN support */ 1831 SIS_SETBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_JABBER); 1832 1833 /* Set TX configuration */ 1834 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T) 1835 CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_10); 1836 else 1837 CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_100); 1838 1839 /* Set full/half duplex mode. */ 1840 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 1841 SIS_SETBIT(sc, SIS_TX_CFG, 1842 (SIS_TXCFG_IGN_HBEAT|SIS_TXCFG_IGN_CARR)); 1843 SIS_SETBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS); 1844 } else { 1845 SIS_CLRBIT(sc, SIS_TX_CFG, 1846 (SIS_TXCFG_IGN_HBEAT|SIS_TXCFG_IGN_CARR)); 1847 SIS_CLRBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS); 1848 } 1849 1850 /* 1851 * Enable interrupts. 1852 */ 1853 CSR_WRITE_4(sc, SIS_IMR, SIS_INTRS); 1854 #ifdef DEVICE_POLLING 1855 /* 1856 * ... only enable interrupts if we are not polling, make sure 1857 * they are off otherwise. 1858 */ 1859 if (ifp->if_flags & IFF_POLLING) 1860 CSR_WRITE_4(sc, SIS_IER, 0); 1861 else 1862 #endif /* DEVICE_POLLING */ 1863 CSR_WRITE_4(sc, SIS_IER, 1); 1864 1865 /* Enable receiver and transmitter. */ 1866 SIS_CLRBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE|SIS_CSR_RX_DISABLE); 1867 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE); 1868 1869 #ifdef notdef 1870 mii_mediachg(mii); 1871 #endif 1872 1873 /* 1874 * Page 75 of the DP83815 manual recommends the 1875 * following register settings "for optimum 1876 * performance." Note however that at least three 1877 * of the registers are listed as "reserved" in 1878 * the register map, so who knows what they do. 1879 */ 1880 if (sc->sis_type == SIS_TYPE_83815) { 1881 CSR_WRITE_4(sc, NS_PHY_PAGE, 0x0001); 1882 CSR_WRITE_4(sc, NS_PHY_CR, 0x189C); 1883 CSR_WRITE_4(sc, NS_PHY_TDATA, 0x0000); 1884 CSR_WRITE_4(sc, NS_PHY_DSPCFG, 0x5040); 1885 CSR_WRITE_4(sc, NS_PHY_SDCFG, 0x008C); 1886 } 1887 1888 ifp->if_flags |= IFF_RUNNING; 1889 ifp->if_flags &= ~IFF_OACTIVE; 1890 1891 callout_reset(&sc->sis_timer, hz, sis_tick, sc); 1892 } 1893 1894 /* 1895 * Set media options. 1896 */ 1897 static int 1898 sis_ifmedia_upd(struct ifnet *ifp) 1899 { 1900 struct sis_softc *sc; 1901 struct mii_data *mii; 1902 1903 sc = ifp->if_softc; 1904 1905 mii = device_get_softc(sc->sis_miibus); 1906 sc->sis_link = 0; 1907 if (mii->mii_instance) { 1908 struct mii_softc *miisc; 1909 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 1910 mii_phy_reset(miisc); 1911 } 1912 mii_mediachg(mii); 1913 1914 return(0); 1915 } 1916 1917 /* 1918 * Report current media status. 1919 */ 1920 static void 1921 sis_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1922 { 1923 struct sis_softc *sc; 1924 struct mii_data *mii; 1925 1926 sc = ifp->if_softc; 1927 1928 mii = device_get_softc(sc->sis_miibus); 1929 mii_pollstat(mii); 1930 ifmr->ifm_active = mii->mii_media_active; 1931 ifmr->ifm_status = mii->mii_media_status; 1932 } 1933 1934 static int 1935 sis_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr) 1936 { 1937 struct sis_softc *sc = ifp->if_softc; 1938 struct ifreq *ifr = (struct ifreq *) data; 1939 struct mii_data *mii; 1940 int error = 0; 1941 1942 switch(command) { 1943 case SIOCSIFFLAGS: 1944 if (ifp->if_flags & IFF_UP) { 1945 sis_init(sc); 1946 } else { 1947 if (ifp->if_flags & IFF_RUNNING) 1948 sis_stop(sc); 1949 } 1950 error = 0; 1951 break; 1952 case SIOCADDMULTI: 1953 case SIOCDELMULTI: 1954 if (sc->sis_type == SIS_TYPE_83815) 1955 sis_setmulti_ns(sc); 1956 else 1957 sis_setmulti_sis(sc); 1958 error = 0; 1959 break; 1960 case SIOCGIFMEDIA: 1961 case SIOCSIFMEDIA: 1962 mii = device_get_softc(sc->sis_miibus); 1963 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1964 break; 1965 default: 1966 error = ether_ioctl(ifp, command, data); 1967 break; 1968 } 1969 return(error); 1970 } 1971 1972 static void 1973 sis_watchdog(struct ifnet *ifp) 1974 { 1975 struct sis_softc *sc; 1976 1977 sc = ifp->if_softc; 1978 1979 ifp->if_oerrors++; 1980 if_printf(ifp, "watchdog timeout\n"); 1981 1982 sis_stop(sc); 1983 sis_reset(sc); 1984 sis_init(sc); 1985 1986 if (!ifq_is_empty(&ifp->if_snd)) 1987 if_devstart(ifp); 1988 } 1989 1990 /* 1991 * Stop the adapter and free any mbufs allocated to the 1992 * RX and TX lists. 1993 */ 1994 static void 1995 sis_stop(struct sis_softc *sc) 1996 { 1997 struct ifnet *ifp = &sc->arpcom.ac_if; 1998 struct sis_list_data *ld = &sc->sis_ldata; 1999 struct sis_chain_data *cd = &sc->sis_cdata; 2000 int i; 2001 2002 callout_stop(&sc->sis_timer); 2003 2004 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2005 ifp->if_timer = 0; 2006 2007 CSR_WRITE_4(sc, SIS_IER, 0); 2008 CSR_WRITE_4(sc, SIS_IMR, 0); 2009 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE|SIS_CSR_RX_DISABLE); 2010 DELAY(1000); 2011 CSR_WRITE_4(sc, SIS_TX_LISTPTR, 0); 2012 CSR_WRITE_4(sc, SIS_RX_LISTPTR, 0); 2013 2014 sc->sis_link = 0; 2015 2016 /* 2017 * Free data in the RX lists. 2018 */ 2019 for (i = 0; i < SIS_RX_LIST_CNT; i++) { 2020 struct sis_rx_data *rd = &cd->sis_rx_data[i]; 2021 2022 if (rd->sis_mbuf != NULL) { 2023 bus_dmamap_unload(cd->sis_rxbuf_tag, rd->sis_map); 2024 m_freem(rd->sis_mbuf); 2025 rd->sis_mbuf = NULL; 2026 } 2027 } 2028 bzero(ld->sis_rx_list, SIS_RX_LIST_SZ); 2029 2030 /* 2031 * Free the TX list buffers. 2032 */ 2033 for (i = 0; i < SIS_TX_LIST_CNT; i++) { 2034 struct sis_tx_data *td = &cd->sis_tx_data[i]; 2035 2036 if (td->sis_mbuf != NULL) { 2037 bus_dmamap_unload(cd->sis_txbuf_tag, td->sis_map); 2038 m_freem(td->sis_mbuf); 2039 td->sis_mbuf = NULL; 2040 } 2041 } 2042 bzero(ld->sis_tx_list, SIS_TX_LIST_SZ); 2043 } 2044 2045 /* 2046 * Stop all chip I/O so that the kernel's probe routines don't 2047 * get confused by errant DMAs when rebooting. 2048 */ 2049 static void 2050 sis_shutdown(device_t dev) 2051 { 2052 struct sis_softc *sc; 2053 struct ifnet *ifp; 2054 2055 sc = device_get_softc(dev); 2056 ifp = &sc->arpcom.ac_if; 2057 lwkt_serialize_enter(ifp->if_serializer); 2058 sis_reset(sc); 2059 sis_stop(sc); 2060 lwkt_serialize_exit(ifp->if_serializer); 2061 } 2062 2063 static int 2064 sis_dma_alloc(device_t dev) 2065 { 2066 struct sis_softc *sc = device_get_softc(dev); 2067 struct sis_chain_data *cd = &sc->sis_cdata; 2068 struct sis_list_data *ld = &sc->sis_ldata; 2069 int i, error; 2070 2071 /* Create top level DMA tag */ 2072 error = bus_dma_tag_create(NULL, /* parent */ 2073 1, 0, /* alignment, boundary */ 2074 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */ 2075 BUS_SPACE_MAXADDR, /* highaddr */ 2076 NULL, NULL, /* filter, filterarg */ 2077 BUS_SPACE_MAXSIZE_32BIT,/* maxsize */ 2078 0, /* nsegments */ 2079 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 2080 0, /* flags */ 2081 &sc->sis_parent_tag); 2082 if (error) { 2083 device_printf(dev, "could not create parent DMA tag\n"); 2084 return error; 2085 } 2086 2087 /* Allocate RX ring */ 2088 ld->sis_rx_list = bus_dmamem_coherent_any(sc->sis_parent_tag, 2089 SIS_RING_ALIGN, SIS_RX_LIST_SZ, 2090 BUS_DMA_WAITOK | BUS_DMA_ZERO, 2091 &ld->sis_rx_tag, &ld->sis_rx_dmamap, 2092 &ld->sis_rx_paddr); 2093 if (ld->sis_rx_list == NULL) { 2094 device_printf(dev, "could not allocate RX ring\n"); 2095 return ENOMEM; 2096 } 2097 2098 /* Allocate TX ring */ 2099 ld->sis_tx_list = bus_dmamem_coherent_any(sc->sis_parent_tag, 2100 SIS_RING_ALIGN, SIS_TX_LIST_SZ, 2101 BUS_DMA_WAITOK | BUS_DMA_ZERO, 2102 &ld->sis_tx_tag, &ld->sis_tx_dmamap, 2103 &ld->sis_tx_paddr); 2104 if (ld->sis_tx_list == NULL) { 2105 device_printf(dev, "could not allocate TX ring\n"); 2106 return ENOMEM; 2107 } 2108 2109 /* Create DMA tag for TX mbuf */ 2110 error = bus_dma_tag_create(sc->sis_parent_tag,/* parent */ 2111 1, 0, /* alignment, boundary */ 2112 BUS_SPACE_MAXADDR, /* lowaddr */ 2113 BUS_SPACE_MAXADDR, /* highaddr */ 2114 NULL, NULL, /* filter, filterarg */ 2115 MCLBYTES, /* maxsize */ 2116 SIS_NSEGS, /* nsegments */ 2117 MCLBYTES, /* maxsegsize */ 2118 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK,/* flags */ 2119 &cd->sis_txbuf_tag); 2120 if (error) { 2121 device_printf(dev, "could not create TX buf DMA tag\n"); 2122 return error; 2123 } 2124 2125 /* Create DMA maps for TX mbufs */ 2126 for (i = 0; i < SIS_TX_LIST_CNT; ++i) { 2127 error = bus_dmamap_create(cd->sis_txbuf_tag, BUS_DMA_WAITOK, 2128 &cd->sis_tx_data[i].sis_map); 2129 if (error) { 2130 int j; 2131 2132 for (j = 0; j < i; ++j) { 2133 bus_dmamap_destroy(cd->sis_txbuf_tag, 2134 cd->sis_tx_data[j].sis_map); 2135 } 2136 bus_dma_tag_destroy(cd->sis_txbuf_tag); 2137 cd->sis_txbuf_tag = NULL; 2138 2139 device_printf(dev, "could not create %dth " 2140 "TX buf DMA map\n", i); 2141 return error; 2142 } 2143 } 2144 2145 /* Create DMA tag for RX mbuf */ 2146 error = bus_dma_tag_create(sc->sis_parent_tag,/* parent */ 2147 SIS_RXBUF_ALIGN, 0, /* alignment, boundary */ 2148 BUS_SPACE_MAXADDR, /* lowaddr */ 2149 BUS_SPACE_MAXADDR, /* highaddr */ 2150 NULL, NULL, /* filter, filterarg */ 2151 MCLBYTES, /* maxsize */ 2152 1, /* nsegments */ 2153 MCLBYTES, /* maxsegsize */ 2154 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK | 2155 BUS_DMA_ALIGNED, /* flags */ 2156 &cd->sis_rxbuf_tag); 2157 if (error) { 2158 device_printf(dev, "could not create RX buf DMA tag\n"); 2159 return error; 2160 } 2161 2162 /* Create tmp DMA map for loading RX mbuf */ 2163 error = bus_dmamap_create(cd->sis_rxbuf_tag, BUS_DMA_WAITOK, 2164 &cd->sis_rx_tmpmap); 2165 if (error) { 2166 device_printf(dev, "could not create RX buf tmp DMA map\n"); 2167 bus_dma_tag_destroy(cd->sis_rxbuf_tag); 2168 cd->sis_rxbuf_tag = NULL; 2169 return error; 2170 } 2171 2172 /* Create DMA maps for RX mbufs */ 2173 for (i = 0; i < SIS_RX_LIST_CNT; ++i) { 2174 error = bus_dmamap_create(cd->sis_rxbuf_tag, BUS_DMA_WAITOK, 2175 &cd->sis_rx_data[i].sis_map); 2176 if (error) { 2177 int j; 2178 2179 for (j = 0; j < i; ++j) { 2180 bus_dmamap_destroy(cd->sis_rxbuf_tag, 2181 cd->sis_rx_data[j].sis_map); 2182 } 2183 bus_dmamap_destroy(cd->sis_rxbuf_tag, 2184 cd->sis_rx_tmpmap); 2185 bus_dma_tag_destroy(cd->sis_rxbuf_tag); 2186 cd->sis_rxbuf_tag = NULL; 2187 2188 device_printf(dev, "could not create %dth " 2189 "RX buf DMA map\n", i); 2190 return error; 2191 } 2192 } 2193 return 0; 2194 } 2195 2196 static void 2197 sis_dma_free(device_t dev) 2198 { 2199 struct sis_softc *sc = device_get_softc(dev); 2200 struct sis_list_data *ld = &sc->sis_ldata; 2201 struct sis_chain_data *cd = &sc->sis_cdata; 2202 int i; 2203 2204 /* Free TX ring */ 2205 if (ld->sis_tx_list != NULL) { 2206 bus_dmamap_unload(ld->sis_tx_tag, ld->sis_tx_dmamap); 2207 bus_dmamem_free(ld->sis_tx_tag, ld->sis_tx_list, 2208 ld->sis_tx_dmamap); 2209 bus_dma_tag_destroy(ld->sis_tx_tag); 2210 } 2211 2212 /* Free RX ring */ 2213 if (ld->sis_rx_list != NULL) { 2214 bus_dmamap_unload(ld->sis_rx_tag, ld->sis_rx_dmamap); 2215 bus_dmamem_free(ld->sis_rx_tag, ld->sis_rx_list, 2216 ld->sis_rx_dmamap); 2217 bus_dma_tag_destroy(ld->sis_rx_tag); 2218 } 2219 2220 /* Destroy DMA stuffs for TX mbufs */ 2221 if (cd->sis_txbuf_tag != NULL) { 2222 for (i = 0; i < SIS_TX_LIST_CNT; ++i) { 2223 KKASSERT(cd->sis_tx_data[i].sis_mbuf == NULL); 2224 bus_dmamap_destroy(cd->sis_txbuf_tag, 2225 cd->sis_tx_data[i].sis_map); 2226 } 2227 bus_dma_tag_destroy(cd->sis_txbuf_tag); 2228 } 2229 2230 /* Destroy DMA stuffs for RX mbufs */ 2231 if (cd->sis_rxbuf_tag != NULL) { 2232 for (i = 0; i < SIS_RX_LIST_CNT; ++i) { 2233 KKASSERT(cd->sis_rx_data[i].sis_mbuf == NULL); 2234 bus_dmamap_destroy(cd->sis_rxbuf_tag, 2235 cd->sis_rx_data[i].sis_map); 2236 } 2237 bus_dmamap_destroy(cd->sis_rxbuf_tag, cd->sis_rx_tmpmap); 2238 bus_dma_tag_destroy(cd->sis_rxbuf_tag); 2239 } 2240 } 2241