1 /* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: src/sys/pci/if_sis.c,v 1.13.4.24 2003/03/05 18:42:33 njl Exp $ 33 * $DragonFly: src/sys/dev/netif/sis/if_sis.c,v 1.38 2008/08/17 04:32:34 sephe Exp $ 34 */ 35 36 /* 37 * SiS 900/SiS 7016 fast ethernet PCI NIC driver. Datasheets are 38 * available from http://www.sis.com.tw. 39 * 40 * This driver also supports the NatSemi DP83815. Datasheets are 41 * available from http://www.national.com. 42 * 43 * Written by Bill Paul <wpaul@ee.columbia.edu> 44 * Electrical Engineering Department 45 * Columbia University, New York City 46 */ 47 48 /* 49 * The SiS 900 is a fairly simple chip. It uses bus master DMA with 50 * simple TX and RX descriptors of 3 longwords in size. The receiver 51 * has a single perfect filter entry for the station address and a 52 * 128-bit multicast hash table. The SiS 900 has a built-in MII-based 53 * transceiver while the 7016 requires an external transceiver chip. 54 * Both chips offer the standard bit-bang MII interface as well as 55 * an enchanced PHY interface which simplifies accessing MII registers. 56 * 57 * The only downside to this chipset is that RX descriptors must be 58 * longword aligned. 59 */ 60 61 #include "opt_polling.h" 62 63 #include <sys/param.h> 64 #include <sys/systm.h> 65 #include <sys/sockio.h> 66 #include <sys/mbuf.h> 67 #include <sys/malloc.h> 68 #include <sys/kernel.h> 69 #include <sys/socket.h> 70 #include <sys/sysctl.h> 71 #include <sys/serialize.h> 72 #include <sys/thread2.h> 73 #include <sys/bus.h> 74 #include <sys/rman.h> 75 #include <sys/interrupt.h> 76 77 #include <net/if.h> 78 #include <net/ifq_var.h> 79 #include <net/if_arp.h> 80 #include <net/ethernet.h> 81 #include <net/if_dl.h> 82 #include <net/if_media.h> 83 #include <net/if_types.h> 84 #include <net/vlan/if_vlan_var.h> 85 86 #include <net/bpf.h> 87 88 #include <dev/netif/mii_layer/mii.h> 89 #include <dev/netif/mii_layer/miivar.h> 90 91 #include <bus/pci/pcidevs.h> 92 #include <bus/pci/pcireg.h> 93 #include <bus/pci/pcivar.h> 94 95 #define SIS_USEIOSPACE 96 97 #include "if_sisreg.h" 98 99 /* "controller miibus0" required. See GENERIC if you get errors here. */ 100 #include "miibus_if.h" 101 102 /* 103 * Various supported device vendors/types and their names. 104 */ 105 static struct sis_type sis_devs[] = { 106 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_900, "SiS 900 10/100BaseTX" }, 107 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_7016, "SiS 7016 10/100BaseTX" }, 108 { PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815, "NatSemi DP8381[56] 10/100BaseTX" }, 109 { 0, 0, NULL } 110 }; 111 112 static int sis_probe(device_t); 113 static int sis_attach(device_t); 114 static int sis_detach(device_t); 115 116 static int sis_newbuf(struct sis_softc *, int, int); 117 static void sis_setup_rxdesc(struct sis_softc *, int); 118 static int sis_encap(struct sis_softc *, struct mbuf **, uint32_t *); 119 static void sis_rxeof(struct sis_softc *); 120 static void sis_rxeoc(struct sis_softc *); 121 static void sis_txeof(struct sis_softc *); 122 static void sis_intr(void *); 123 static void sis_tick(void *); 124 static void sis_start(struct ifnet *); 125 static int sis_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *); 126 static void sis_init(void *); 127 static void sis_stop(struct sis_softc *); 128 static void sis_watchdog(struct ifnet *); 129 static void sis_shutdown(device_t); 130 static int sis_ifmedia_upd(struct ifnet *); 131 static void sis_ifmedia_sts(struct ifnet *, struct ifmediareq *); 132 133 static uint16_t sis_reverse(uint16_t); 134 static void sis_delay(struct sis_softc *); 135 static void sis_eeprom_idle(struct sis_softc *); 136 static void sis_eeprom_putbyte(struct sis_softc *, int); 137 static void sis_eeprom_getword(struct sis_softc *, int, uint16_t *); 138 static void sis_read_eeprom(struct sis_softc *, caddr_t, int, int, int); 139 #ifdef __i386__ 140 static void sis_read_cmos(struct sis_softc *, device_t, caddr_t, int, int); 141 static void sis_read_mac(struct sis_softc *, device_t, caddr_t); 142 static device_t sis_find_bridge(device_t); 143 #endif 144 145 static void sis_mii_sync(struct sis_softc *); 146 static void sis_mii_send(struct sis_softc *, uint32_t, int); 147 static int sis_mii_readreg(struct sis_softc *, struct sis_mii_frame *); 148 static int sis_mii_writereg(struct sis_softc *, struct sis_mii_frame *); 149 static int sis_miibus_readreg(device_t, int, int); 150 static int sis_miibus_writereg(device_t, int, int, int); 151 static void sis_miibus_statchg(device_t); 152 153 static void sis_setmulti_sis(struct sis_softc *); 154 static void sis_setmulti_ns(struct sis_softc *); 155 static uint32_t sis_mchash(struct sis_softc *, const uint8_t *); 156 static void sis_reset(struct sis_softc *); 157 static int sis_list_rx_init(struct sis_softc *); 158 static int sis_list_tx_init(struct sis_softc *); 159 160 static int sis_dma_alloc(device_t dev); 161 static void sis_dma_free(device_t dev); 162 #ifdef DEVICE_POLLING 163 static poll_handler_t sis_poll; 164 #endif 165 #ifdef SIS_USEIOSPACE 166 #define SIS_RES SYS_RES_IOPORT 167 #define SIS_RID SIS_PCI_LOIO 168 #else 169 #define SIS_RES SYS_RES_MEMORY 170 #define SIS_RID SIS_PCI_LOMEM 171 #endif 172 173 static device_method_t sis_methods[] = { 174 /* Device interface */ 175 DEVMETHOD(device_probe, sis_probe), 176 DEVMETHOD(device_attach, sis_attach), 177 DEVMETHOD(device_detach, sis_detach), 178 DEVMETHOD(device_shutdown, sis_shutdown), 179 180 /* bus interface */ 181 DEVMETHOD(bus_print_child, bus_generic_print_child), 182 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 183 184 /* MII interface */ 185 DEVMETHOD(miibus_readreg, sis_miibus_readreg), 186 DEVMETHOD(miibus_writereg, sis_miibus_writereg), 187 DEVMETHOD(miibus_statchg, sis_miibus_statchg), 188 189 { 0, 0 } 190 }; 191 192 static driver_t sis_driver = { 193 "sis", 194 sis_methods, 195 sizeof(struct sis_softc) 196 }; 197 198 static devclass_t sis_devclass; 199 200 DECLARE_DUMMY_MODULE(if_sis); 201 DRIVER_MODULE(if_sis, pci, sis_driver, sis_devclass, 0, 0); 202 DRIVER_MODULE(miibus, sis, miibus_driver, miibus_devclass, 0, 0); 203 204 #define SIS_SETBIT(sc, reg, x) \ 205 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x)) 206 207 #define SIS_CLRBIT(sc, reg, x) \ 208 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x)) 209 210 #define SIO_SET(x) \ 211 CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) | x) 212 213 #define SIO_CLR(x) \ 214 CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) & ~x) 215 216 /* 217 * Routine to reverse the bits in a word. Stolen almost 218 * verbatim from /usr/games/fortune. 219 */ 220 static uint16_t 221 sis_reverse(uint16_t n) 222 { 223 n = ((n >> 1) & 0x5555) | ((n << 1) & 0xaaaa); 224 n = ((n >> 2) & 0x3333) | ((n << 2) & 0xcccc); 225 n = ((n >> 4) & 0x0f0f) | ((n << 4) & 0xf0f0); 226 n = ((n >> 8) & 0x00ff) | ((n << 8) & 0xff00); 227 228 return(n); 229 } 230 231 static void 232 sis_delay(struct sis_softc *sc) 233 { 234 int idx; 235 236 for (idx = (300 / 33) + 1; idx > 0; idx--) 237 CSR_READ_4(sc, SIS_CSR); 238 } 239 240 static void 241 sis_eeprom_idle(struct sis_softc *sc) 242 { 243 int i; 244 245 SIO_SET(SIS_EECTL_CSEL); 246 sis_delay(sc); 247 SIO_SET(SIS_EECTL_CLK); 248 sis_delay(sc); 249 250 for (i = 0; i < 25; i++) { 251 SIO_CLR(SIS_EECTL_CLK); 252 sis_delay(sc); 253 SIO_SET(SIS_EECTL_CLK); 254 sis_delay(sc); 255 } 256 257 SIO_CLR(SIS_EECTL_CLK); 258 sis_delay(sc); 259 SIO_CLR(SIS_EECTL_CSEL); 260 sis_delay(sc); 261 CSR_WRITE_4(sc, SIS_EECTL, 0x00000000); 262 } 263 264 /* 265 * Send a read command and address to the EEPROM, check for ACK. 266 */ 267 static void 268 sis_eeprom_putbyte(struct sis_softc *sc, int addr) 269 { 270 int d, i; 271 272 d = addr | SIS_EECMD_READ; 273 274 /* 275 * Feed in each bit and stobe the clock. 276 */ 277 for (i = 0x400; i; i >>= 1) { 278 if (d & i) 279 SIO_SET(SIS_EECTL_DIN); 280 else 281 SIO_CLR(SIS_EECTL_DIN); 282 sis_delay(sc); 283 SIO_SET(SIS_EECTL_CLK); 284 sis_delay(sc); 285 SIO_CLR(SIS_EECTL_CLK); 286 sis_delay(sc); 287 } 288 } 289 290 /* 291 * Read a word of data stored in the EEPROM at address 'addr.' 292 */ 293 static void 294 sis_eeprom_getword(struct sis_softc *sc, int addr, uint16_t *dest) 295 { 296 int i; 297 uint16_t word = 0; 298 299 /* Force EEPROM to idle state. */ 300 sis_eeprom_idle(sc); 301 302 /* Enter EEPROM access mode. */ 303 sis_delay(sc); 304 SIO_CLR(SIS_EECTL_CLK); 305 sis_delay(sc); 306 SIO_SET(SIS_EECTL_CSEL); 307 sis_delay(sc); 308 309 /* 310 * Send address of word we want to read. 311 */ 312 sis_eeprom_putbyte(sc, addr); 313 314 /* 315 * Start reading bits from EEPROM. 316 */ 317 for (i = 0x8000; i; i >>= 1) { 318 SIO_SET(SIS_EECTL_CLK); 319 sis_delay(sc); 320 if (CSR_READ_4(sc, SIS_EECTL) & SIS_EECTL_DOUT) 321 word |= i; 322 sis_delay(sc); 323 SIO_CLR(SIS_EECTL_CLK); 324 sis_delay(sc); 325 } 326 327 /* Turn off EEPROM access mode. */ 328 sis_eeprom_idle(sc); 329 330 *dest = word; 331 } 332 333 /* 334 * Read a sequence of words from the EEPROM. 335 */ 336 static void 337 sis_read_eeprom(struct sis_softc *sc, caddr_t dest, int off, int cnt, int swap) 338 { 339 int i; 340 uint16_t word = 0, *ptr; 341 342 for (i = 0; i < cnt; i++) { 343 sis_eeprom_getword(sc, off + i, &word); 344 ptr = (uint16_t *)(dest + (i * 2)); 345 if (swap) 346 *ptr = ntohs(word); 347 else 348 *ptr = word; 349 } 350 } 351 352 #ifdef __i386__ 353 static device_t 354 sis_find_bridge(device_t dev) 355 { 356 devclass_t pci_devclass; 357 device_t *pci_devices; 358 int pci_count = 0; 359 device_t *pci_children; 360 int pci_childcount = 0; 361 device_t *busp, *childp; 362 device_t child = NULL; 363 int i, j; 364 365 if ((pci_devclass = devclass_find("pci")) == NULL) 366 return(NULL); 367 368 devclass_get_devices(pci_devclass, &pci_devices, &pci_count); 369 370 for (i = 0, busp = pci_devices; i < pci_count; i++, busp++) { 371 pci_childcount = 0; 372 device_get_children(*busp, &pci_children, &pci_childcount); 373 for (j = 0, childp = pci_children; j < pci_childcount; 374 j++, childp++) { 375 if (pci_get_vendor(*childp) == PCI_VENDOR_SIS && 376 pci_get_device(*childp) == 0x0008) { 377 child = *childp; 378 goto done; 379 } 380 } 381 } 382 383 done: 384 kfree(pci_devices, M_TEMP); 385 kfree(pci_children, M_TEMP); 386 return(child); 387 } 388 389 static void 390 sis_read_cmos(struct sis_softc *sc, device_t dev, caddr_t dest, int off, 391 int cnt) 392 { 393 device_t bridge; 394 uint8_t reg; 395 int i; 396 bus_space_tag_t btag; 397 398 bridge = sis_find_bridge(dev); 399 if (bridge == NULL) 400 return; 401 reg = pci_read_config(bridge, 0x48, 1); 402 pci_write_config(bridge, 0x48, reg|0x40, 1); 403 404 /* XXX */ 405 btag = I386_BUS_SPACE_IO; 406 407 for (i = 0; i < cnt; i++) { 408 bus_space_write_1(btag, 0x0, 0x70, i + off); 409 *(dest + i) = bus_space_read_1(btag, 0x0, 0x71); 410 } 411 412 pci_write_config(bridge, 0x48, reg & ~0x40, 1); 413 } 414 415 static void 416 sis_read_mac(struct sis_softc *sc, device_t dev, caddr_t dest) 417 { 418 uint32_t filtsave, csrsave; 419 420 filtsave = CSR_READ_4(sc, SIS_RXFILT_CTL); 421 csrsave = CSR_READ_4(sc, SIS_CSR); 422 423 CSR_WRITE_4(sc, SIS_CSR, SIS_CSR_RELOAD | filtsave); 424 CSR_WRITE_4(sc, SIS_CSR, 0); 425 426 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave & ~SIS_RXFILTCTL_ENABLE); 427 428 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR0); 429 ((uint16_t *)dest)[0] = CSR_READ_2(sc, SIS_RXFILT_DATA); 430 CSR_WRITE_4(sc, SIS_RXFILT_CTL,SIS_FILTADDR_PAR1); 431 ((uint16_t *)dest)[1] = CSR_READ_2(sc, SIS_RXFILT_DATA); 432 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR2); 433 ((uint16_t *)dest)[2] = CSR_READ_2(sc, SIS_RXFILT_DATA); 434 435 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave); 436 CSR_WRITE_4(sc, SIS_CSR, csrsave); 437 } 438 #endif 439 440 /* 441 * Sync the PHYs by setting data bit and strobing the clock 32 times. 442 */ 443 static void 444 sis_mii_sync(struct sis_softc *sc) 445 { 446 int i; 447 448 SIO_SET(SIS_MII_DIR|SIS_MII_DATA); 449 450 for (i = 0; i < 32; i++) { 451 SIO_SET(SIS_MII_CLK); 452 DELAY(1); 453 SIO_CLR(SIS_MII_CLK); 454 DELAY(1); 455 } 456 } 457 458 /* 459 * Clock a series of bits through the MII. 460 */ 461 static void 462 sis_mii_send(struct sis_softc *sc, uint32_t bits, int cnt) 463 { 464 int i; 465 466 SIO_CLR(SIS_MII_CLK); 467 468 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 469 if (bits & i) 470 SIO_SET(SIS_MII_DATA); 471 else 472 SIO_CLR(SIS_MII_DATA); 473 DELAY(1); 474 SIO_CLR(SIS_MII_CLK); 475 DELAY(1); 476 SIO_SET(SIS_MII_CLK); 477 } 478 } 479 480 /* 481 * Read an PHY register through the MII. 482 */ 483 static int 484 sis_mii_readreg(struct sis_softc *sc, struct sis_mii_frame *frame) 485 { 486 int i, ack; 487 488 /* 489 * Set up frame for RX. 490 */ 491 frame->mii_stdelim = SIS_MII_STARTDELIM; 492 frame->mii_opcode = SIS_MII_READOP; 493 frame->mii_turnaround = 0; 494 frame->mii_data = 0; 495 496 /* 497 * Turn on data xmit. 498 */ 499 SIO_SET(SIS_MII_DIR); 500 501 sis_mii_sync(sc); 502 503 /* 504 * Send command/address info. 505 */ 506 sis_mii_send(sc, frame->mii_stdelim, 2); 507 sis_mii_send(sc, frame->mii_opcode, 2); 508 sis_mii_send(sc, frame->mii_phyaddr, 5); 509 sis_mii_send(sc, frame->mii_regaddr, 5); 510 511 /* Idle bit */ 512 SIO_CLR((SIS_MII_CLK|SIS_MII_DATA)); 513 DELAY(1); 514 SIO_SET(SIS_MII_CLK); 515 DELAY(1); 516 517 /* Turn off xmit. */ 518 SIO_CLR(SIS_MII_DIR); 519 520 /* Check for ack */ 521 SIO_CLR(SIS_MII_CLK); 522 DELAY(1); 523 ack = CSR_READ_4(sc, SIS_EECTL) & SIS_MII_DATA; 524 SIO_SET(SIS_MII_CLK); 525 DELAY(1); 526 527 /* 528 * Now try reading data bits. If the ack failed, we still 529 * need to clock through 16 cycles to keep the PHY(s) in sync. 530 */ 531 if (ack) { 532 for(i = 0; i < 16; i++) { 533 SIO_CLR(SIS_MII_CLK); 534 DELAY(1); 535 SIO_SET(SIS_MII_CLK); 536 DELAY(1); 537 } 538 goto fail; 539 } 540 541 for (i = 0x8000; i; i >>= 1) { 542 SIO_CLR(SIS_MII_CLK); 543 DELAY(1); 544 if (!ack) { 545 if (CSR_READ_4(sc, SIS_EECTL) & SIS_MII_DATA) 546 frame->mii_data |= i; 547 DELAY(1); 548 } 549 SIO_SET(SIS_MII_CLK); 550 DELAY(1); 551 } 552 553 fail: 554 555 SIO_CLR(SIS_MII_CLK); 556 DELAY(1); 557 SIO_SET(SIS_MII_CLK); 558 DELAY(1); 559 560 if (ack) 561 return(1); 562 return(0); 563 } 564 565 /* 566 * Write to a PHY register through the MII. 567 */ 568 static int 569 sis_mii_writereg(struct sis_softc *sc, struct sis_mii_frame *frame) 570 { 571 /* 572 * Set up frame for TX. 573 */ 574 575 frame->mii_stdelim = SIS_MII_STARTDELIM; 576 frame->mii_opcode = SIS_MII_WRITEOP; 577 frame->mii_turnaround = SIS_MII_TURNAROUND; 578 579 /* 580 * Turn on data output. 581 */ 582 SIO_SET(SIS_MII_DIR); 583 584 sis_mii_sync(sc); 585 586 sis_mii_send(sc, frame->mii_stdelim, 2); 587 sis_mii_send(sc, frame->mii_opcode, 2); 588 sis_mii_send(sc, frame->mii_phyaddr, 5); 589 sis_mii_send(sc, frame->mii_regaddr, 5); 590 sis_mii_send(sc, frame->mii_turnaround, 2); 591 sis_mii_send(sc, frame->mii_data, 16); 592 593 /* Idle bit. */ 594 SIO_SET(SIS_MII_CLK); 595 DELAY(1); 596 SIO_CLR(SIS_MII_CLK); 597 DELAY(1); 598 599 /* 600 * Turn off xmit. 601 */ 602 SIO_CLR(SIS_MII_DIR); 603 604 return(0); 605 } 606 607 static int 608 sis_miibus_readreg(device_t dev, int phy, int reg) 609 { 610 struct sis_softc *sc; 611 struct sis_mii_frame frame; 612 613 sc = device_get_softc(dev); 614 615 if (sc->sis_type == SIS_TYPE_83815) { 616 if (phy != 0) 617 return(0); 618 /* 619 * The NatSemi chip can take a while after 620 * a reset to come ready, during which the BMSR 621 * returns a value of 0. This is *never* supposed 622 * to happen: some of the BMSR bits are meant to 623 * be hardwired in the on position, and this can 624 * confuse the miibus code a bit during the probe 625 * and attach phase. So we make an effort to check 626 * for this condition and wait for it to clear. 627 */ 628 if (!CSR_READ_4(sc, NS_BMSR)) 629 DELAY(1000); 630 return CSR_READ_4(sc, NS_BMCR + (reg * 4)); 631 } 632 /* 633 * Chipsets < SIS_635 seem not to be able to read/write 634 * through mdio. Use the enhanced PHY access register 635 * again for them. 636 */ 637 if (sc->sis_type == SIS_TYPE_900 && 638 sc->sis_rev < SIS_REV_635) { 639 int i, val = 0; 640 641 if (phy != 0) 642 return(0); 643 644 CSR_WRITE_4(sc, SIS_PHYCTL, 645 (phy << 11) | (reg << 6) | SIS_PHYOP_READ); 646 SIS_SETBIT(sc, SIS_PHYCTL, SIS_PHYCTL_ACCESS); 647 648 for (i = 0; i < SIS_TIMEOUT; i++) { 649 if (!(CSR_READ_4(sc, SIS_PHYCTL) & SIS_PHYCTL_ACCESS)) 650 break; 651 } 652 653 if (i == SIS_TIMEOUT) { 654 device_printf(dev, "PHY failed to come ready\n"); 655 return(0); 656 } 657 658 val = (CSR_READ_4(sc, SIS_PHYCTL) >> 16) & 0xFFFF; 659 660 if (val == 0xFFFF) 661 return(0); 662 663 return(val); 664 } else { 665 bzero((char *)&frame, sizeof(frame)); 666 667 frame.mii_phyaddr = phy; 668 frame.mii_regaddr = reg; 669 sis_mii_readreg(sc, &frame); 670 671 return(frame.mii_data); 672 } 673 } 674 675 static int 676 sis_miibus_writereg(device_t dev, int phy, int reg, int data) 677 { 678 struct sis_softc *sc; 679 struct sis_mii_frame frame; 680 681 sc = device_get_softc(dev); 682 683 if (sc->sis_type == SIS_TYPE_83815) { 684 if (phy != 0) 685 return(0); 686 CSR_WRITE_4(sc, NS_BMCR + (reg * 4), data); 687 return(0); 688 } 689 690 if (sc->sis_type == SIS_TYPE_900 && 691 sc->sis_rev < SIS_REV_635) { 692 int i; 693 694 if (phy != 0) 695 return(0); 696 697 CSR_WRITE_4(sc, SIS_PHYCTL, (data << 16) | (phy << 11) | 698 (reg << 6) | SIS_PHYOP_WRITE); 699 SIS_SETBIT(sc, SIS_PHYCTL, SIS_PHYCTL_ACCESS); 700 701 for (i = 0; i < SIS_TIMEOUT; i++) { 702 if (!(CSR_READ_4(sc, SIS_PHYCTL) & SIS_PHYCTL_ACCESS)) 703 break; 704 } 705 706 if (i == SIS_TIMEOUT) 707 device_printf(dev, "PHY failed to come ready\n"); 708 } else { 709 bzero((char *)&frame, sizeof(frame)); 710 711 frame.mii_phyaddr = phy; 712 frame.mii_regaddr = reg; 713 frame.mii_data = data; 714 sis_mii_writereg(sc, &frame); 715 } 716 return(0); 717 } 718 719 static void 720 sis_miibus_statchg(device_t dev) 721 { 722 struct sis_softc *sc; 723 724 sc = device_get_softc(dev); 725 sis_init(sc); 726 } 727 728 static uint32_t 729 sis_mchash(struct sis_softc *sc, const uint8_t *addr) 730 { 731 uint32_t crc, carry; 732 int i, j; 733 uint8_t c; 734 735 /* Compute CRC for the address value. */ 736 crc = 0xFFFFFFFF; /* initial value */ 737 738 for (i = 0; i < 6; i++) { 739 c = *(addr + i); 740 for (j = 0; j < 8; j++) { 741 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 742 crc <<= 1; 743 c >>= 1; 744 if (carry) 745 crc = (crc ^ 0x04c11db6) | carry; 746 } 747 } 748 749 /* 750 * return the filter bit position 751 * 752 * The NatSemi chip has a 512-bit filter, which is 753 * different than the SiS, so we special-case it. 754 */ 755 if (sc->sis_type == SIS_TYPE_83815) 756 return (crc >> 23); 757 else if (sc->sis_rev >= SIS_REV_635 || sc->sis_rev == SIS_REV_900B) 758 return (crc >> 24); 759 else 760 return (crc >> 25); 761 } 762 763 static void 764 sis_setmulti_ns(struct sis_softc *sc) 765 { 766 struct ifnet *ifp; 767 struct ifmultiaddr *ifma; 768 uint32_t h = 0, i, filtsave; 769 int bit, index; 770 771 ifp = &sc->arpcom.ac_if; 772 773 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 774 SIS_CLRBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_MCHASH); 775 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLMULTI); 776 return; 777 } 778 779 /* 780 * We have to explicitly enable the multicast hash table 781 * on the NatSemi chip if we want to use it, which we do. 782 */ 783 SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_MCHASH); 784 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLMULTI); 785 786 filtsave = CSR_READ_4(sc, SIS_RXFILT_CTL); 787 788 /* first, zot all the existing hash bits */ 789 for (i = 0; i < 32; i++) { 790 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_FMEM_LO + (i*2)); 791 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 0); 792 } 793 794 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 795 if (ifma->ifma_addr->sa_family != AF_LINK) 796 continue; 797 h = sis_mchash(sc, 798 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 799 index = h >> 3; 800 bit = h & 0x1F; 801 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_FMEM_LO + index); 802 if (bit > 0xF) 803 bit -= 0x10; 804 SIS_SETBIT(sc, SIS_RXFILT_DATA, (1 << bit)); 805 } 806 807 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave); 808 } 809 810 static void 811 sis_setmulti_sis(struct sis_softc *sc) 812 { 813 struct ifnet *ifp; 814 struct ifmultiaddr *ifma; 815 uint32_t h, i, n, ctl; 816 uint16_t hashes[16]; 817 818 ifp = &sc->arpcom.ac_if; 819 820 /* hash table size */ 821 if (sc->sis_rev >= SIS_REV_635 || sc->sis_rev == SIS_REV_900B) 822 n = 16; 823 else 824 n = 8; 825 826 ctl = CSR_READ_4(sc, SIS_RXFILT_CTL) & SIS_RXFILTCTL_ENABLE; 827 828 if (ifp->if_flags & IFF_BROADCAST) 829 ctl |= SIS_RXFILTCTL_BROAD; 830 831 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 832 ctl |= SIS_RXFILTCTL_ALLMULTI; 833 if (ifp->if_flags & IFF_PROMISC) 834 ctl |= SIS_RXFILTCTL_BROAD|SIS_RXFILTCTL_ALLPHYS; 835 for (i = 0; i < n; i++) 836 hashes[i] = ~0; 837 } else { 838 for (i = 0; i < n; i++) 839 hashes[i] = 0; 840 i = 0; 841 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 842 if (ifma->ifma_addr->sa_family != AF_LINK) 843 continue; 844 h = sis_mchash(sc, 845 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 846 hashes[h >> 4] |= 1 << (h & 0xf); 847 i++; 848 } 849 if (i > n) { 850 ctl |= SIS_RXFILTCTL_ALLMULTI; 851 for (i = 0; i < n; i++) 852 hashes[i] = ~0; 853 } 854 } 855 856 for (i = 0; i < n; i++) { 857 CSR_WRITE_4(sc, SIS_RXFILT_CTL, (4 + i) << 16); 858 CSR_WRITE_4(sc, SIS_RXFILT_DATA, hashes[i]); 859 } 860 861 CSR_WRITE_4(sc, SIS_RXFILT_CTL, ctl); 862 } 863 864 static void 865 sis_reset(struct sis_softc *sc) 866 { 867 struct ifnet *ifp = &sc->arpcom.ac_if; 868 int i; 869 870 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RESET); 871 872 for (i = 0; i < SIS_TIMEOUT; i++) { 873 if (!(CSR_READ_4(sc, SIS_CSR) & SIS_CSR_RESET)) 874 break; 875 } 876 877 if (i == SIS_TIMEOUT) 878 if_printf(ifp, "reset never completed\n"); 879 880 /* Wait a little while for the chip to get its brains in order. */ 881 DELAY(1000); 882 883 /* 884 * If this is a NetSemi chip, make sure to clear 885 * PME mode. 886 */ 887 if (sc->sis_type == SIS_TYPE_83815) { 888 CSR_WRITE_4(sc, NS_CLKRUN, NS_CLKRUN_PMESTS); 889 CSR_WRITE_4(sc, NS_CLKRUN, 0); 890 } 891 } 892 893 /* 894 * Probe for an SiS chip. Check the PCI vendor and device 895 * IDs against our list and return a device name if we find a match. 896 */ 897 static int 898 sis_probe(device_t dev) 899 { 900 struct sis_type *t; 901 902 t = sis_devs; 903 904 while(t->sis_name != NULL) { 905 if ((pci_get_vendor(dev) == t->sis_vid) && 906 (pci_get_device(dev) == t->sis_did)) { 907 device_set_desc(dev, t->sis_name); 908 return(0); 909 } 910 t++; 911 } 912 913 return(ENXIO); 914 } 915 916 /* 917 * Attach the interface. Allocate softc structures, do ifmedia 918 * setup and ethernet/BPF attach. 919 */ 920 static int 921 sis_attach(device_t dev) 922 { 923 uint8_t eaddr[ETHER_ADDR_LEN]; 924 uint32_t command; 925 struct sis_softc *sc; 926 struct ifnet *ifp; 927 int error, rid, waittime; 928 929 error = waittime = 0; 930 sc = device_get_softc(dev); 931 932 if (pci_get_device(dev) == PCI_PRODUCT_SIS_900) 933 sc->sis_type = SIS_TYPE_900; 934 if (pci_get_device(dev) == PCI_PRODUCT_SIS_7016) 935 sc->sis_type = SIS_TYPE_7016; 936 if (pci_get_vendor(dev) == PCI_VENDOR_NS) 937 sc->sis_type = SIS_TYPE_83815; 938 939 sc->sis_rev = pci_read_config(dev, PCIR_REVID, 1); 940 941 /* 942 * Handle power management nonsense. 943 */ 944 945 command = pci_read_config(dev, SIS_PCI_CAPID, 4) & 0x000000FF; 946 if (command == 0x01) { 947 948 command = pci_read_config(dev, SIS_PCI_PWRMGMTCTRL, 4); 949 if (command & SIS_PSTATE_MASK) { 950 uint32_t iobase, membase, irq; 951 952 /* Save important PCI config data. */ 953 iobase = pci_read_config(dev, SIS_PCI_LOIO, 4); 954 membase = pci_read_config(dev, SIS_PCI_LOMEM, 4); 955 irq = pci_read_config(dev, SIS_PCI_INTLINE, 4); 956 957 /* Reset the power state. */ 958 device_printf(dev, "chip is in D%d power mode " 959 "-- setting to D0\n", command & SIS_PSTATE_MASK); 960 command &= 0xFFFFFFFC; 961 pci_write_config(dev, SIS_PCI_PWRMGMTCTRL, command, 4); 962 963 /* Restore PCI config data. */ 964 pci_write_config(dev, SIS_PCI_LOIO, iobase, 4); 965 pci_write_config(dev, SIS_PCI_LOMEM, membase, 4); 966 pci_write_config(dev, SIS_PCI_INTLINE, irq, 4); 967 } 968 } 969 970 /* 971 * Map control/status registers. 972 */ 973 command = pci_read_config(dev, PCIR_COMMAND, 4); 974 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 975 pci_write_config(dev, PCIR_COMMAND, command, 4); 976 command = pci_read_config(dev, PCIR_COMMAND, 4); 977 978 #ifdef SIS_USEIOSPACE 979 if (!(command & PCIM_CMD_PORTEN)) { 980 device_printf(dev, "failed to enable I/O ports!\n"); 981 error = ENXIO; 982 goto fail; 983 } 984 #else 985 if (!(command & PCIM_CMD_MEMEN)) { 986 device_printf(dev, "failed to enable memory mapping!\n"); 987 error = ENXIO; 988 goto fail; 989 } 990 #endif 991 992 rid = SIS_RID; 993 sc->sis_res = bus_alloc_resource_any(dev, SIS_RES, &rid, RF_ACTIVE); 994 995 if (sc->sis_res == NULL) { 996 device_printf(dev, "couldn't map ports/memory\n"); 997 error = ENXIO; 998 goto fail; 999 } 1000 1001 sc->sis_btag = rman_get_bustag(sc->sis_res); 1002 sc->sis_bhandle = rman_get_bushandle(sc->sis_res); 1003 1004 /* Allocate interrupt */ 1005 rid = 0; 1006 sc->sis_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1007 RF_SHAREABLE | RF_ACTIVE); 1008 1009 if (sc->sis_irq == NULL) { 1010 device_printf(dev, "couldn't map interrupt\n"); 1011 error = ENXIO; 1012 goto fail; 1013 } 1014 1015 /* Reset the adapter. */ 1016 sis_reset(sc); 1017 1018 if (sc->sis_type == SIS_TYPE_900 && 1019 (sc->sis_rev == SIS_REV_635 || 1020 sc->sis_rev == SIS_REV_900B)) { 1021 SIO_SET(SIS_CFG_RND_CNT); 1022 SIO_SET(SIS_CFG_PERR_DETECT); 1023 } 1024 1025 /* 1026 * Get station address from the EEPROM. 1027 */ 1028 switch (pci_get_vendor(dev)) { 1029 case PCI_VENDOR_NS: 1030 /* 1031 * Reading the MAC address out of the EEPROM on 1032 * the NatSemi chip takes a bit more work than 1033 * you'd expect. The address spans 4 16-bit words, 1034 * with the first word containing only a single bit. 1035 * You have to shift everything over one bit to 1036 * get it aligned properly. Also, the bits are 1037 * stored backwards (the LSB is really the MSB, 1038 * and so on) so you have to reverse them in order 1039 * to get the MAC address into the form we want. 1040 * Why? Who the hell knows. 1041 */ 1042 { 1043 uint16_t tmp[4]; 1044 1045 sis_read_eeprom(sc, (caddr_t)&tmp, 1046 NS_EE_NODEADDR, 4, 0); 1047 1048 /* Shift everything over one bit. */ 1049 tmp[3] = tmp[3] >> 1; 1050 tmp[3] |= tmp[2] << 15; 1051 tmp[2] = tmp[2] >> 1; 1052 tmp[2] |= tmp[1] << 15; 1053 tmp[1] = tmp[1] >> 1; 1054 tmp[1] |= tmp[0] << 15; 1055 1056 /* Now reverse all the bits. */ 1057 tmp[3] = sis_reverse(tmp[3]); 1058 tmp[2] = sis_reverse(tmp[2]); 1059 tmp[1] = sis_reverse(tmp[1]); 1060 1061 bcopy((char *)&tmp[1], eaddr, ETHER_ADDR_LEN); 1062 } 1063 break; 1064 case PCI_VENDOR_SIS: 1065 default: 1066 #ifdef __i386__ 1067 /* 1068 * If this is a SiS 630E chipset with an embedded 1069 * SiS 900 controller, we have to read the MAC address 1070 * from the APC CMOS RAM. Our method for doing this 1071 * is very ugly since we have to reach out and grab 1072 * ahold of hardware for which we cannot properly 1073 * allocate resources. This code is only compiled on 1074 * the i386 architecture since the SiS 630E chipset 1075 * is for x86 motherboards only. Note that there are 1076 * a lot of magic numbers in this hack. These are 1077 * taken from SiS's Linux driver. I'd like to replace 1078 * them with proper symbolic definitions, but that 1079 * requires some datasheets that I don't have access 1080 * to at the moment. 1081 */ 1082 if (sc->sis_rev == SIS_REV_630S || 1083 sc->sis_rev == SIS_REV_630E || 1084 sc->sis_rev == SIS_REV_630EA1) 1085 sis_read_cmos(sc, dev, (caddr_t)&eaddr, 0x9, 6); 1086 1087 else if (sc->sis_rev == SIS_REV_635 || 1088 sc->sis_rev == SIS_REV_630ET) 1089 sis_read_mac(sc, dev, (caddr_t)&eaddr); 1090 else if (sc->sis_rev == SIS_REV_96x) { 1091 /* 1092 * Allow to read EEPROM from LAN. It is shared 1093 * between a 1394 controller and the NIC and each 1094 * time we access it, we need to set SIS_EECMD_REQ. 1095 */ 1096 SIO_SET(SIS_EECMD_REQ); 1097 for (waittime = 0; waittime < SIS_TIMEOUT; 1098 waittime++) { 1099 /* Force EEPROM to idle state. */ 1100 sis_eeprom_idle(sc); 1101 if (CSR_READ_4(sc, SIS_EECTL) & SIS_EECMD_GNT) { 1102 sis_read_eeprom(sc, (caddr_t)&eaddr, 1103 SIS_EE_NODEADDR, 3, 0); 1104 break; 1105 } 1106 DELAY(1); 1107 } 1108 /* 1109 * Set SIS_EECTL_CLK to high, so a other master 1110 * can operate on the i2c bus. 1111 */ 1112 SIO_SET(SIS_EECTL_CLK); 1113 /* Refuse EEPROM access by LAN */ 1114 SIO_SET(SIS_EECMD_DONE); 1115 } else 1116 #endif 1117 sis_read_eeprom(sc, (caddr_t)&eaddr, 1118 SIS_EE_NODEADDR, 3, 0); 1119 break; 1120 } 1121 1122 callout_init(&sc->sis_timer); 1123 1124 error = sis_dma_alloc(dev); 1125 if (error) 1126 goto fail; 1127 1128 ifp = &sc->arpcom.ac_if; 1129 ifp->if_softc = sc; 1130 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1131 ifp->if_mtu = ETHERMTU; 1132 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1133 ifp->if_ioctl = sis_ioctl; 1134 ifp->if_start = sis_start; 1135 ifp->if_watchdog = sis_watchdog; 1136 ifp->if_init = sis_init; 1137 ifp->if_baudrate = 10000000; 1138 ifq_set_maxlen(&ifp->if_snd, SIS_TX_LIST_CNT - 1); 1139 ifq_set_ready(&ifp->if_snd); 1140 #ifdef DEVICE_POLLING 1141 ifp->if_poll = sis_poll; 1142 #endif 1143 ifp->if_capenable = ifp->if_capabilities; 1144 1145 /* 1146 * Do MII setup. 1147 */ 1148 if (mii_phy_probe(dev, &sc->sis_miibus, 1149 sis_ifmedia_upd, sis_ifmedia_sts)) { 1150 device_printf(dev, "MII without any PHY!\n"); 1151 error = ENXIO; 1152 goto fail; 1153 } 1154 1155 /* 1156 * Call MI attach routine. 1157 */ 1158 ether_ifattach(ifp, eaddr, NULL); 1159 1160 /* 1161 * Tell the upper layer(s) we support long frames. 1162 */ 1163 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1164 1165 error = bus_setup_intr(dev, sc->sis_irq, INTR_MPSAFE, 1166 sis_intr, sc, 1167 &sc->sis_intrhand, 1168 ifp->if_serializer); 1169 1170 if (error) { 1171 device_printf(dev, "couldn't set up irq\n"); 1172 ether_ifdetach(ifp); 1173 goto fail; 1174 } 1175 1176 ifp->if_cpuid = ithread_cpuid(rman_get_start(sc->sis_irq)); 1177 KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus); 1178 1179 fail: 1180 if (error) 1181 sis_detach(dev); 1182 1183 return(error); 1184 } 1185 1186 /* 1187 * Shutdown hardware and free up resources. It is called in both the error case 1188 * and the normal detach case so it needs to be careful about only freeing 1189 * resources that have actually been allocated. 1190 */ 1191 static int 1192 sis_detach(device_t dev) 1193 { 1194 struct sis_softc *sc = device_get_softc(dev); 1195 struct ifnet *ifp = &sc->arpcom.ac_if; 1196 1197 1198 if (device_is_attached(dev)) { 1199 lwkt_serialize_enter(ifp->if_serializer); 1200 sis_reset(sc); 1201 sis_stop(sc); 1202 bus_teardown_intr(dev, sc->sis_irq, sc->sis_intrhand); 1203 lwkt_serialize_exit(ifp->if_serializer); 1204 1205 ether_ifdetach(ifp); 1206 } 1207 if (sc->sis_miibus) 1208 device_delete_child(dev, sc->sis_miibus); 1209 bus_generic_detach(dev); 1210 1211 if (sc->sis_irq) 1212 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sis_irq); 1213 if (sc->sis_res) 1214 bus_release_resource(dev, SIS_RES, SIS_RID, sc->sis_res); 1215 1216 sis_dma_free(dev); 1217 1218 return(0); 1219 } 1220 1221 /* 1222 * Initialize the transmit descriptors. 1223 */ 1224 static int 1225 sis_list_tx_init(struct sis_softc *sc) 1226 { 1227 struct sis_list_data *ld = &sc->sis_ldata; 1228 struct sis_chain_data *cd = &sc->sis_cdata; 1229 int i, nexti; 1230 1231 for (i = 0; i < SIS_TX_LIST_CNT; i++) { 1232 bus_addr_t paddr; 1233 1234 /* 1235 * Link the TX desc together 1236 */ 1237 nexti = (i == (SIS_TX_LIST_CNT - 1)) ? 0 : i+1; 1238 paddr = ld->sis_tx_paddr + (nexti * sizeof(struct sis_desc)); 1239 ld->sis_tx_list[i].sis_next = paddr; 1240 } 1241 cd->sis_tx_prod = cd->sis_tx_cons = cd->sis_tx_cnt = 0; 1242 1243 return 0; 1244 } 1245 1246 /* 1247 * Initialize the RX descriptors and allocate mbufs for them. Note that 1248 * we arrange the descriptors in a closed ring, so that the last descriptor 1249 * points back to the first. 1250 */ 1251 static int 1252 sis_list_rx_init(struct sis_softc *sc) 1253 { 1254 struct sis_list_data *ld = &sc->sis_ldata; 1255 struct sis_chain_data *cd = &sc->sis_cdata; 1256 int i, error; 1257 1258 for (i = 0; i < SIS_RX_LIST_CNT; i++) { 1259 bus_addr_t paddr; 1260 int nexti; 1261 1262 error = sis_newbuf(sc, i, 1); 1263 if (error) 1264 return error; 1265 1266 /* 1267 * Link the RX desc together 1268 */ 1269 nexti = (i == (SIS_RX_LIST_CNT - 1)) ? 0 : i+1; 1270 paddr = ld->sis_rx_paddr + (nexti * sizeof(struct sis_desc)); 1271 ld->sis_rx_list[i].sis_next = paddr; 1272 } 1273 cd->sis_rx_prod = 0; 1274 1275 return 0; 1276 } 1277 1278 /* 1279 * Initialize an RX descriptor and attach an MBUF cluster. 1280 */ 1281 static int 1282 sis_newbuf(struct sis_softc *sc, int idx, int init) 1283 { 1284 struct sis_chain_data *cd = &sc->sis_cdata; 1285 struct sis_rx_data *rd = &cd->sis_rx_data[idx]; 1286 bus_dma_segment_t seg; 1287 bus_dmamap_t map; 1288 struct mbuf *m; 1289 int nseg, error; 1290 1291 m = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR); 1292 if (m == NULL) { 1293 if (init) 1294 if_printf(&sc->arpcom.ac_if, "can't alloc RX mbuf\n"); 1295 return ENOBUFS; 1296 } 1297 m->m_len = m->m_pkthdr.len = MCLBYTES; 1298 1299 /* Try loading the mbuf into tmp DMA map */ 1300 error = bus_dmamap_load_mbuf_segment(cd->sis_rxbuf_tag, 1301 cd->sis_rx_tmpmap, m, &seg, 1, &nseg, BUS_DMA_NOWAIT); 1302 if (error) { 1303 m_freem(m); 1304 if (init) 1305 if_printf(&sc->arpcom.ac_if, "can't load RX mbuf\n"); 1306 return error; 1307 } 1308 1309 /* Unload the currently loaded mbuf */ 1310 if (rd->sis_mbuf != NULL) { 1311 bus_dmamap_sync(cd->sis_rxbuf_tag, rd->sis_map, 1312 BUS_DMASYNC_POSTREAD); 1313 bus_dmamap_unload(cd->sis_rxbuf_tag, rd->sis_map); 1314 } 1315 1316 /* Swap DMA maps */ 1317 map = cd->sis_rx_tmpmap; 1318 cd->sis_rx_tmpmap = rd->sis_map; 1319 rd->sis_map = map; 1320 1321 /* Save necessary information */ 1322 rd->sis_mbuf = m; 1323 rd->sis_paddr = seg.ds_addr; 1324 1325 sis_setup_rxdesc(sc, idx); 1326 return 0; 1327 } 1328 1329 static void 1330 sis_setup_rxdesc(struct sis_softc *sc, int idx) 1331 { 1332 struct sis_desc *c = &sc->sis_ldata.sis_rx_list[idx]; 1333 1334 /* Setup the RX desc */ 1335 c->sis_ctl = SIS_RXLEN; 1336 c->sis_ptr = sc->sis_cdata.sis_rx_data[idx].sis_paddr; 1337 } 1338 1339 /* 1340 * A frame has been uploaded: pass the resulting mbuf chain up to 1341 * the higher level protocols. 1342 */ 1343 static void 1344 sis_rxeof(struct sis_softc *sc) 1345 { 1346 struct ifnet *ifp = &sc->arpcom.ac_if; 1347 int i, total_len = 0; 1348 uint32_t rxstat; 1349 1350 i = sc->sis_cdata.sis_rx_prod; 1351 while (SIS_OWNDESC(&sc->sis_ldata.sis_rx_list[i])) { 1352 struct sis_desc *cur_rx; 1353 struct sis_rx_data *rd; 1354 struct mbuf *m; 1355 int idx = i; 1356 1357 #ifdef DEVICE_POLLING 1358 if (ifp->if_flags & IFF_POLLING) { 1359 if (sc->rxcycles <= 0) 1360 break; 1361 sc->rxcycles--; 1362 } 1363 #endif /* DEVICE_POLLING */ 1364 1365 cur_rx = &sc->sis_ldata.sis_rx_list[idx]; 1366 rd = &sc->sis_cdata.sis_rx_data[idx]; 1367 1368 rxstat = cur_rx->sis_rxstat; 1369 total_len = SIS_RXBYTES(cur_rx); 1370 1371 m = rd->sis_mbuf; 1372 1373 SIS_INC(i, SIS_RX_LIST_CNT); 1374 1375 /* 1376 * If an error occurs, update stats, clear the 1377 * status word and leave the mbuf cluster in place: 1378 * it should simply get re-used next time this descriptor 1379 * comes up in the ring. 1380 */ 1381 if (!(rxstat & SIS_CMDSTS_PKT_OK)) { 1382 ifp->if_ierrors++; 1383 if (rxstat & SIS_RXSTAT_COLL) 1384 ifp->if_collisions++; 1385 sis_setup_rxdesc(sc, idx); 1386 continue; 1387 } 1388 1389 /* No errors; receive the packet. */ 1390 if (sis_newbuf(sc, idx, 0) == 0) { 1391 m->m_pkthdr.len = m->m_len = total_len; 1392 m->m_pkthdr.rcvif = ifp; 1393 } else { 1394 ifp->if_ierrors++; 1395 sis_setup_rxdesc(sc, idx); 1396 continue; 1397 } 1398 1399 ifp->if_ipackets++; 1400 ifp->if_input(ifp, m); 1401 } 1402 sc->sis_cdata.sis_rx_prod = i; 1403 } 1404 1405 static void 1406 sis_rxeoc(struct sis_softc *sc) 1407 { 1408 sis_rxeof(sc); 1409 sis_init(sc); 1410 } 1411 1412 /* 1413 * A frame was downloaded to the chip. It's safe for us to clean up 1414 * the list buffers. 1415 */ 1416 1417 static void 1418 sis_txeof(struct sis_softc *sc) 1419 { 1420 struct ifnet *ifp = &sc->arpcom.ac_if; 1421 struct sis_chain_data *cd = &sc->sis_cdata; 1422 uint32_t idx; 1423 1424 /* 1425 * Go through our tx list and free mbufs for those 1426 * frames that have been transmitted. 1427 */ 1428 for (idx = sc->sis_cdata.sis_tx_cons; sc->sis_cdata.sis_tx_cnt > 0; 1429 sc->sis_cdata.sis_tx_cnt--, SIS_INC(idx, SIS_TX_LIST_CNT) ) { 1430 struct sis_desc *cur_tx; 1431 struct sis_tx_data *td; 1432 1433 cur_tx = &sc->sis_ldata.sis_tx_list[idx]; 1434 td = &cd->sis_tx_data[idx]; 1435 1436 if (SIS_OWNDESC(cur_tx)) 1437 break; 1438 1439 if (cur_tx->sis_ctl & SIS_CMDSTS_MORE) 1440 continue; 1441 1442 if (!(cur_tx->sis_ctl & SIS_CMDSTS_PKT_OK)) { 1443 ifp->if_oerrors++; 1444 if (cur_tx->sis_txstat & SIS_TXSTAT_EXCESSCOLLS) 1445 ifp->if_collisions++; 1446 if (cur_tx->sis_txstat & SIS_TXSTAT_OUTOFWINCOLL) 1447 ifp->if_collisions++; 1448 } 1449 1450 ifp->if_collisions += 1451 (cur_tx->sis_txstat & SIS_TXSTAT_COLLCNT) >> 16; 1452 1453 ifp->if_opackets++; 1454 if (td->sis_mbuf != NULL) { 1455 bus_dmamap_unload(cd->sis_txbuf_tag, td->sis_map); 1456 m_freem(td->sis_mbuf); 1457 td->sis_mbuf = NULL; 1458 } 1459 } 1460 1461 if (idx != sc->sis_cdata.sis_tx_cons) { 1462 /* we freed up some buffers */ 1463 sc->sis_cdata.sis_tx_cons = idx; 1464 } 1465 1466 if (cd->sis_tx_cnt == 0) 1467 ifp->if_timer = 0; 1468 if (!SIS_IS_OACTIVE(sc)) 1469 ifp->if_flags &= ~IFF_OACTIVE; 1470 } 1471 1472 static void 1473 sis_tick(void *xsc) 1474 { 1475 struct sis_softc *sc = xsc; 1476 struct mii_data *mii; 1477 struct ifnet *ifp = &sc->arpcom.ac_if; 1478 1479 lwkt_serialize_enter(ifp->if_serializer); 1480 1481 mii = device_get_softc(sc->sis_miibus); 1482 mii_tick(mii); 1483 1484 if (!sc->sis_link) { 1485 mii_pollstat(mii); 1486 if (mii->mii_media_status & IFM_ACTIVE && 1487 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 1488 sc->sis_link++; 1489 if (!ifq_is_empty(&ifp->if_snd)) 1490 if_devstart(ifp); 1491 } 1492 1493 callout_reset(&sc->sis_timer, hz, sis_tick, sc); 1494 lwkt_serialize_exit(ifp->if_serializer); 1495 } 1496 1497 #ifdef DEVICE_POLLING 1498 1499 static void 1500 sis_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1501 { 1502 struct sis_softc *sc = ifp->if_softc; 1503 1504 switch(cmd) { 1505 case POLL_REGISTER: 1506 /* disable interrupts */ 1507 CSR_WRITE_4(sc, SIS_IER, 0); 1508 break; 1509 case POLL_DEREGISTER: 1510 /* enable interrupts */ 1511 CSR_WRITE_4(sc, SIS_IER, 1); 1512 break; 1513 default: 1514 /* 1515 * On the sis, reading the status register also clears it. 1516 * So before returning to intr mode we must make sure that all 1517 * possible pending sources of interrupts have been served. 1518 * In practice this means run to completion the *eof routines, 1519 * and then call the interrupt routine 1520 */ 1521 sc->rxcycles = count; 1522 sis_rxeof(sc); 1523 sis_txeof(sc); 1524 if (!ifq_is_empty(&ifp->if_snd)) 1525 if_devstart(ifp); 1526 1527 if (sc->rxcycles > 0 || cmd == POLL_AND_CHECK_STATUS) { 1528 uint32_t status; 1529 1530 /* Reading the ISR register clears all interrupts. */ 1531 status = CSR_READ_4(sc, SIS_ISR); 1532 1533 if (status & (SIS_ISR_RX_ERR|SIS_ISR_RX_OFLOW)) 1534 sis_rxeoc(sc); 1535 1536 if (status & (SIS_ISR_RX_IDLE)) 1537 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE); 1538 1539 if (status & SIS_ISR_SYSERR) { 1540 sis_reset(sc); 1541 sis_init(sc); 1542 } 1543 } 1544 break; 1545 } 1546 } 1547 #endif /* DEVICE_POLLING */ 1548 1549 static void 1550 sis_intr(void *arg) 1551 { 1552 struct sis_softc *sc; 1553 struct ifnet *ifp; 1554 uint32_t status; 1555 1556 sc = arg; 1557 ifp = &sc->arpcom.ac_if; 1558 1559 /* Supress unwanted interrupts */ 1560 if (!(ifp->if_flags & IFF_UP)) { 1561 sis_stop(sc); 1562 return; 1563 } 1564 1565 /* Disable interrupts. */ 1566 CSR_WRITE_4(sc, SIS_IER, 0); 1567 1568 for (;;) { 1569 /* Reading the ISR register clears all interrupts. */ 1570 status = CSR_READ_4(sc, SIS_ISR); 1571 1572 if ((status & SIS_INTRS) == 0) 1573 break; 1574 1575 if (status & 1576 (SIS_ISR_TX_DESC_OK | SIS_ISR_TX_ERR | SIS_ISR_TX_OK | 1577 SIS_ISR_TX_IDLE) ) 1578 sis_txeof(sc); 1579 1580 if (status & 1581 (SIS_ISR_RX_DESC_OK | SIS_ISR_RX_OK | SIS_ISR_RX_IDLE)) 1582 sis_rxeof(sc); 1583 1584 if (status & (SIS_ISR_RX_ERR | SIS_ISR_RX_OFLOW)) 1585 sis_rxeoc(sc); 1586 1587 if (status & (SIS_ISR_RX_IDLE)) 1588 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE); 1589 1590 if (status & SIS_ISR_SYSERR) { 1591 sis_reset(sc); 1592 sis_init(sc); 1593 } 1594 } 1595 1596 /* Re-enable interrupts. */ 1597 CSR_WRITE_4(sc, SIS_IER, 1); 1598 1599 if (!ifq_is_empty(&ifp->if_snd)) 1600 if_devstart(ifp); 1601 } 1602 1603 /* 1604 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1605 * pointers to the fragment pointers. 1606 */ 1607 static int 1608 sis_encap(struct sis_softc *sc, struct mbuf **m_head, uint32_t *txidx) 1609 { 1610 struct sis_chain_data *cd = &sc->sis_cdata; 1611 struct sis_list_data *ld = &sc->sis_ldata; 1612 bus_dma_segment_t segs[SIS_NSEGS]; 1613 bus_dmamap_t map; 1614 int frag, cur, maxsegs, nsegs, error, i; 1615 1616 maxsegs = SIS_TX_LIST_CNT - SIS_NSEGS_RESERVED - cd->sis_tx_cnt; 1617 KASSERT(maxsegs >= 1, ("not enough TX descs\n")); 1618 if (maxsegs > SIS_NSEGS) 1619 maxsegs = SIS_NSEGS; 1620 1621 map = cd->sis_tx_data[*txidx].sis_map; 1622 error = bus_dmamap_load_mbuf_defrag(cd->sis_txbuf_tag, map, m_head, 1623 segs, maxsegs, &nsegs, BUS_DMA_NOWAIT); 1624 if (error) { 1625 m_freem(*m_head); 1626 *m_head = NULL; 1627 return error; 1628 } 1629 bus_dmamap_sync(cd->sis_txbuf_tag, map, BUS_DMASYNC_PREWRITE); 1630 1631 cur = frag = *txidx; 1632 for (i = 0; i < nsegs; ++i) { 1633 struct sis_desc *f = &ld->sis_tx_list[frag]; 1634 1635 f->sis_ctl = SIS_CMDSTS_MORE | segs[i].ds_len; 1636 f->sis_ptr = segs[i].ds_addr; 1637 if (i != 0) 1638 f->sis_ctl |= SIS_CMDSTS_OWN; 1639 1640 cur = frag; 1641 SIS_INC(frag, SIS_TX_LIST_CNT); 1642 } 1643 ld->sis_tx_list[cur].sis_ctl &= ~SIS_CMDSTS_MORE; 1644 ld->sis_tx_list[*txidx].sis_ctl |= SIS_CMDSTS_OWN; 1645 1646 /* Swap DMA map */ 1647 cd->sis_tx_data[*txidx].sis_map = cd->sis_tx_data[cur].sis_map; 1648 cd->sis_tx_data[cur].sis_map = map; 1649 1650 cd->sis_tx_data[cur].sis_mbuf = *m_head; 1651 1652 cd->sis_tx_cnt += nsegs; 1653 *txidx = frag; 1654 1655 return 0; 1656 } 1657 1658 /* 1659 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1660 * to the mbuf data regions directly in the transmit lists. We also save a 1661 * copy of the pointers since the transmit list fragment pointers are 1662 * physical addresses. 1663 */ 1664 1665 static void 1666 sis_start(struct ifnet *ifp) 1667 { 1668 struct sis_softc *sc = ifp->if_softc; 1669 int need_trans, error; 1670 uint32_t idx; 1671 1672 if (!sc->sis_link) { 1673 ifq_purge(&ifp->if_snd); 1674 return; 1675 } 1676 1677 if ((ifp->if_flags & (IFF_OACTIVE | IFF_RUNNING)) != IFF_RUNNING) 1678 return; 1679 1680 idx = sc->sis_cdata.sis_tx_prod; 1681 need_trans = 0; 1682 1683 while (sc->sis_cdata.sis_tx_data[idx].sis_mbuf == NULL) { 1684 struct mbuf *m_head; 1685 1686 /* 1687 * If there's no way we can send any packets, return now. 1688 */ 1689 if (SIS_IS_OACTIVE(sc)) { 1690 ifp->if_flags |= IFF_OACTIVE; 1691 break; 1692 } 1693 1694 m_head = ifq_dequeue(&ifp->if_snd, NULL); 1695 if (m_head == NULL) 1696 break; 1697 1698 error = sis_encap(sc, &m_head, &idx); 1699 if (error) { 1700 ifp->if_oerrors++; 1701 if (sc->sis_cdata.sis_tx_cnt == 0) { 1702 continue; 1703 } else { 1704 ifp->if_flags |= IFF_OACTIVE; 1705 break; 1706 } 1707 } 1708 need_trans = 1; 1709 1710 /* 1711 * If there's a BPF listener, bounce a copy of this frame 1712 * to him. 1713 */ 1714 BPF_MTAP(ifp, m_head); 1715 } 1716 1717 if (!need_trans) 1718 return; 1719 1720 /* Transmit */ 1721 sc->sis_cdata.sis_tx_prod = idx; 1722 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_ENABLE); 1723 1724 /* 1725 * Set a timeout in case the chip goes out to lunch. 1726 */ 1727 ifp->if_timer = 5; 1728 } 1729 1730 static void 1731 sis_init(void *xsc) 1732 { 1733 struct sis_softc *sc = xsc; 1734 struct ifnet *ifp = &sc->arpcom.ac_if; 1735 struct mii_data *mii; 1736 1737 /* 1738 * Cancel pending I/O and free all RX/TX buffers. 1739 */ 1740 sis_stop(sc); 1741 1742 mii = device_get_softc(sc->sis_miibus); 1743 1744 /* Set MAC address */ 1745 if (sc->sis_type == SIS_TYPE_83815) { 1746 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR0); 1747 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1748 ((uint16_t *)sc->arpcom.ac_enaddr)[0]); 1749 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR1); 1750 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1751 ((uint16_t *)sc->arpcom.ac_enaddr)[1]); 1752 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR2); 1753 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1754 ((uint16_t *)sc->arpcom.ac_enaddr)[2]); 1755 } else { 1756 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR0); 1757 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1758 ((uint16_t *)sc->arpcom.ac_enaddr)[0]); 1759 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR1); 1760 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1761 ((uint16_t *)sc->arpcom.ac_enaddr)[1]); 1762 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR2); 1763 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1764 ((uint16_t *)sc->arpcom.ac_enaddr)[2]); 1765 } 1766 1767 /* Init circular RX list. */ 1768 if (sis_list_rx_init(sc)) { 1769 if_printf(ifp, "initialization failed: " 1770 "no memory for rx buffers\n"); 1771 sis_stop(sc); 1772 return; 1773 } 1774 1775 /* 1776 * Init tx descriptors. 1777 */ 1778 sis_list_tx_init(sc); 1779 1780 /* 1781 * For the NatSemi chip, we have to explicitly enable the 1782 * reception of ARP frames, as well as turn on the 'perfect 1783 * match' filter where we store the station address, otherwise 1784 * we won't receive unicasts meant for this host. 1785 */ 1786 if (sc->sis_type == SIS_TYPE_83815) { 1787 SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_ARP); 1788 SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_PERFECT); 1789 } 1790 1791 /* If we want promiscuous mode, set the allframes bit. */ 1792 if (ifp->if_flags & IFF_PROMISC) 1793 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLPHYS); 1794 else 1795 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLPHYS); 1796 1797 /* 1798 * Set the capture broadcast bit to capture broadcast frames. 1799 */ 1800 if (ifp->if_flags & IFF_BROADCAST) 1801 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_BROAD); 1802 else 1803 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_BROAD); 1804 1805 /* 1806 * Load the multicast filter. 1807 */ 1808 if (sc->sis_type == SIS_TYPE_83815) 1809 sis_setmulti_ns(sc); 1810 else 1811 sis_setmulti_sis(sc); 1812 1813 /* Turn the receive filter on */ 1814 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ENABLE); 1815 1816 /* 1817 * Load the address of the RX and TX lists. 1818 */ 1819 CSR_WRITE_4(sc, SIS_RX_LISTPTR, sc->sis_ldata.sis_rx_paddr); 1820 CSR_WRITE_4(sc, SIS_TX_LISTPTR, sc->sis_ldata.sis_tx_paddr); 1821 1822 /* SIS_CFG_EDB_MASTER_EN indicates the EDB bus is used instead of 1823 * the PCI bus. When this bit is set, the Max DMA Burst Size 1824 * for TX/RX DMA should be no larger than 16 double words. 1825 */ 1826 if (CSR_READ_4(sc, SIS_CFG) & SIS_CFG_EDB_MASTER_EN) 1827 CSR_WRITE_4(sc, SIS_RX_CFG, SIS_RXCFG64); 1828 else 1829 CSR_WRITE_4(sc, SIS_RX_CFG, SIS_RXCFG256); 1830 1831 /* Accept Long Packets for VLAN support */ 1832 SIS_SETBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_JABBER); 1833 1834 /* Set TX configuration */ 1835 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T) 1836 CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_10); 1837 else 1838 CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_100); 1839 1840 /* Set full/half duplex mode. */ 1841 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 1842 SIS_SETBIT(sc, SIS_TX_CFG, 1843 (SIS_TXCFG_IGN_HBEAT|SIS_TXCFG_IGN_CARR)); 1844 SIS_SETBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS); 1845 } else { 1846 SIS_CLRBIT(sc, SIS_TX_CFG, 1847 (SIS_TXCFG_IGN_HBEAT|SIS_TXCFG_IGN_CARR)); 1848 SIS_CLRBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS); 1849 } 1850 1851 /* 1852 * Enable interrupts. 1853 */ 1854 CSR_WRITE_4(sc, SIS_IMR, SIS_INTRS); 1855 #ifdef DEVICE_POLLING 1856 /* 1857 * ... only enable interrupts if we are not polling, make sure 1858 * they are off otherwise. 1859 */ 1860 if (ifp->if_flags & IFF_POLLING) 1861 CSR_WRITE_4(sc, SIS_IER, 0); 1862 else 1863 #endif /* DEVICE_POLLING */ 1864 CSR_WRITE_4(sc, SIS_IER, 1); 1865 1866 /* Enable receiver and transmitter. */ 1867 SIS_CLRBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE|SIS_CSR_RX_DISABLE); 1868 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE); 1869 1870 #ifdef notdef 1871 mii_mediachg(mii); 1872 #endif 1873 1874 /* 1875 * Page 75 of the DP83815 manual recommends the 1876 * following register settings "for optimum 1877 * performance." Note however that at least three 1878 * of the registers are listed as "reserved" in 1879 * the register map, so who knows what they do. 1880 */ 1881 if (sc->sis_type == SIS_TYPE_83815) { 1882 CSR_WRITE_4(sc, NS_PHY_PAGE, 0x0001); 1883 CSR_WRITE_4(sc, NS_PHY_CR, 0x189C); 1884 CSR_WRITE_4(sc, NS_PHY_TDATA, 0x0000); 1885 CSR_WRITE_4(sc, NS_PHY_DSPCFG, 0x5040); 1886 CSR_WRITE_4(sc, NS_PHY_SDCFG, 0x008C); 1887 } 1888 1889 ifp->if_flags |= IFF_RUNNING; 1890 ifp->if_flags &= ~IFF_OACTIVE; 1891 1892 callout_reset(&sc->sis_timer, hz, sis_tick, sc); 1893 } 1894 1895 /* 1896 * Set media options. 1897 */ 1898 static int 1899 sis_ifmedia_upd(struct ifnet *ifp) 1900 { 1901 struct sis_softc *sc; 1902 struct mii_data *mii; 1903 1904 sc = ifp->if_softc; 1905 1906 mii = device_get_softc(sc->sis_miibus); 1907 sc->sis_link = 0; 1908 if (mii->mii_instance) { 1909 struct mii_softc *miisc; 1910 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 1911 mii_phy_reset(miisc); 1912 } 1913 mii_mediachg(mii); 1914 1915 return(0); 1916 } 1917 1918 /* 1919 * Report current media status. 1920 */ 1921 static void 1922 sis_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1923 { 1924 struct sis_softc *sc; 1925 struct mii_data *mii; 1926 1927 sc = ifp->if_softc; 1928 1929 mii = device_get_softc(sc->sis_miibus); 1930 mii_pollstat(mii); 1931 ifmr->ifm_active = mii->mii_media_active; 1932 ifmr->ifm_status = mii->mii_media_status; 1933 } 1934 1935 static int 1936 sis_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr) 1937 { 1938 struct sis_softc *sc = ifp->if_softc; 1939 struct ifreq *ifr = (struct ifreq *) data; 1940 struct mii_data *mii; 1941 int error = 0; 1942 1943 switch(command) { 1944 case SIOCSIFFLAGS: 1945 if (ifp->if_flags & IFF_UP) { 1946 sis_init(sc); 1947 } else { 1948 if (ifp->if_flags & IFF_RUNNING) 1949 sis_stop(sc); 1950 } 1951 error = 0; 1952 break; 1953 case SIOCADDMULTI: 1954 case SIOCDELMULTI: 1955 if (sc->sis_type == SIS_TYPE_83815) 1956 sis_setmulti_ns(sc); 1957 else 1958 sis_setmulti_sis(sc); 1959 error = 0; 1960 break; 1961 case SIOCGIFMEDIA: 1962 case SIOCSIFMEDIA: 1963 mii = device_get_softc(sc->sis_miibus); 1964 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1965 break; 1966 default: 1967 error = ether_ioctl(ifp, command, data); 1968 break; 1969 } 1970 return(error); 1971 } 1972 1973 static void 1974 sis_watchdog(struct ifnet *ifp) 1975 { 1976 struct sis_softc *sc; 1977 1978 sc = ifp->if_softc; 1979 1980 ifp->if_oerrors++; 1981 if_printf(ifp, "watchdog timeout\n"); 1982 1983 sis_stop(sc); 1984 sis_reset(sc); 1985 sis_init(sc); 1986 1987 if (!ifq_is_empty(&ifp->if_snd)) 1988 if_devstart(ifp); 1989 } 1990 1991 /* 1992 * Stop the adapter and free any mbufs allocated to the 1993 * RX and TX lists. 1994 */ 1995 static void 1996 sis_stop(struct sis_softc *sc) 1997 { 1998 struct ifnet *ifp = &sc->arpcom.ac_if; 1999 struct sis_list_data *ld = &sc->sis_ldata; 2000 struct sis_chain_data *cd = &sc->sis_cdata; 2001 int i; 2002 2003 callout_stop(&sc->sis_timer); 2004 2005 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2006 ifp->if_timer = 0; 2007 2008 CSR_WRITE_4(sc, SIS_IER, 0); 2009 CSR_WRITE_4(sc, SIS_IMR, 0); 2010 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE|SIS_CSR_RX_DISABLE); 2011 DELAY(1000); 2012 CSR_WRITE_4(sc, SIS_TX_LISTPTR, 0); 2013 CSR_WRITE_4(sc, SIS_RX_LISTPTR, 0); 2014 2015 sc->sis_link = 0; 2016 2017 /* 2018 * Free data in the RX lists. 2019 */ 2020 for (i = 0; i < SIS_RX_LIST_CNT; i++) { 2021 struct sis_rx_data *rd = &cd->sis_rx_data[i]; 2022 2023 if (rd->sis_mbuf != NULL) { 2024 bus_dmamap_unload(cd->sis_rxbuf_tag, rd->sis_map); 2025 m_freem(rd->sis_mbuf); 2026 rd->sis_mbuf = NULL; 2027 } 2028 } 2029 bzero(ld->sis_rx_list, SIS_RX_LIST_SZ); 2030 2031 /* 2032 * Free the TX list buffers. 2033 */ 2034 for (i = 0; i < SIS_TX_LIST_CNT; i++) { 2035 struct sis_tx_data *td = &cd->sis_tx_data[i]; 2036 2037 if (td->sis_mbuf != NULL) { 2038 bus_dmamap_unload(cd->sis_txbuf_tag, td->sis_map); 2039 m_freem(td->sis_mbuf); 2040 td->sis_mbuf = NULL; 2041 } 2042 } 2043 bzero(ld->sis_tx_list, SIS_TX_LIST_SZ); 2044 } 2045 2046 /* 2047 * Stop all chip I/O so that the kernel's probe routines don't 2048 * get confused by errant DMAs when rebooting. 2049 */ 2050 static void 2051 sis_shutdown(device_t dev) 2052 { 2053 struct sis_softc *sc; 2054 struct ifnet *ifp; 2055 2056 sc = device_get_softc(dev); 2057 ifp = &sc->arpcom.ac_if; 2058 lwkt_serialize_enter(ifp->if_serializer); 2059 sis_reset(sc); 2060 sis_stop(sc); 2061 lwkt_serialize_exit(ifp->if_serializer); 2062 } 2063 2064 static int 2065 sis_dma_alloc(device_t dev) 2066 { 2067 struct sis_softc *sc = device_get_softc(dev); 2068 struct sis_chain_data *cd = &sc->sis_cdata; 2069 struct sis_list_data *ld = &sc->sis_ldata; 2070 int i, error; 2071 2072 /* Create top level DMA tag */ 2073 error = bus_dma_tag_create(NULL, /* parent */ 2074 1, 0, /* alignment, boundary */ 2075 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */ 2076 BUS_SPACE_MAXADDR, /* highaddr */ 2077 NULL, NULL, /* filter, filterarg */ 2078 BUS_SPACE_MAXSIZE_32BIT,/* maxsize */ 2079 0, /* nsegments */ 2080 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 2081 0, /* flags */ 2082 &sc->sis_parent_tag); 2083 if (error) { 2084 device_printf(dev, "could not create parent DMA tag\n"); 2085 return error; 2086 } 2087 2088 /* Allocate RX ring */ 2089 ld->sis_rx_list = bus_dmamem_coherent_any(sc->sis_parent_tag, 2090 SIS_RING_ALIGN, SIS_RX_LIST_SZ, 2091 BUS_DMA_WAITOK | BUS_DMA_ZERO, 2092 &ld->sis_rx_tag, &ld->sis_rx_dmamap, 2093 &ld->sis_rx_paddr); 2094 if (ld->sis_rx_list == NULL) { 2095 device_printf(dev, "could not allocate RX ring\n"); 2096 return ENOMEM; 2097 } 2098 2099 /* Allocate TX ring */ 2100 ld->sis_tx_list = bus_dmamem_coherent_any(sc->sis_parent_tag, 2101 SIS_RING_ALIGN, SIS_TX_LIST_SZ, 2102 BUS_DMA_WAITOK | BUS_DMA_ZERO, 2103 &ld->sis_tx_tag, &ld->sis_tx_dmamap, 2104 &ld->sis_tx_paddr); 2105 if (ld->sis_tx_list == NULL) { 2106 device_printf(dev, "could not allocate TX ring\n"); 2107 return ENOMEM; 2108 } 2109 2110 /* Create DMA tag for TX mbuf */ 2111 error = bus_dma_tag_create(sc->sis_parent_tag,/* parent */ 2112 1, 0, /* alignment, boundary */ 2113 BUS_SPACE_MAXADDR, /* lowaddr */ 2114 BUS_SPACE_MAXADDR, /* highaddr */ 2115 NULL, NULL, /* filter, filterarg */ 2116 MCLBYTES, /* maxsize */ 2117 SIS_NSEGS, /* nsegments */ 2118 MCLBYTES, /* maxsegsize */ 2119 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK,/* flags */ 2120 &cd->sis_txbuf_tag); 2121 if (error) { 2122 device_printf(dev, "could not create TX buf DMA tag\n"); 2123 return error; 2124 } 2125 2126 /* Create DMA maps for TX mbufs */ 2127 for (i = 0; i < SIS_TX_LIST_CNT; ++i) { 2128 error = bus_dmamap_create(cd->sis_txbuf_tag, BUS_DMA_WAITOK, 2129 &cd->sis_tx_data[i].sis_map); 2130 if (error) { 2131 int j; 2132 2133 for (j = 0; j < i; ++j) { 2134 bus_dmamap_destroy(cd->sis_txbuf_tag, 2135 cd->sis_tx_data[j].sis_map); 2136 } 2137 bus_dma_tag_destroy(cd->sis_txbuf_tag); 2138 cd->sis_txbuf_tag = NULL; 2139 2140 device_printf(dev, "could not create %dth " 2141 "TX buf DMA map\n", i); 2142 return error; 2143 } 2144 } 2145 2146 /* Create DMA tag for RX mbuf */ 2147 error = bus_dma_tag_create(sc->sis_parent_tag,/* parent */ 2148 SIS_RXBUF_ALIGN, 0, /* alignment, boundary */ 2149 BUS_SPACE_MAXADDR, /* lowaddr */ 2150 BUS_SPACE_MAXADDR, /* highaddr */ 2151 NULL, NULL, /* filter, filterarg */ 2152 MCLBYTES, /* maxsize */ 2153 1, /* nsegments */ 2154 MCLBYTES, /* maxsegsize */ 2155 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK | 2156 BUS_DMA_ALIGNED, /* flags */ 2157 &cd->sis_rxbuf_tag); 2158 if (error) { 2159 device_printf(dev, "could not create RX buf DMA tag\n"); 2160 return error; 2161 } 2162 2163 /* Create tmp DMA map for loading RX mbuf */ 2164 error = bus_dmamap_create(cd->sis_rxbuf_tag, BUS_DMA_WAITOK, 2165 &cd->sis_rx_tmpmap); 2166 if (error) { 2167 device_printf(dev, "could not create RX buf tmp DMA map\n"); 2168 bus_dma_tag_destroy(cd->sis_rxbuf_tag); 2169 cd->sis_rxbuf_tag = NULL; 2170 return error; 2171 } 2172 2173 /* Create DMA maps for RX mbufs */ 2174 for (i = 0; i < SIS_RX_LIST_CNT; ++i) { 2175 error = bus_dmamap_create(cd->sis_rxbuf_tag, BUS_DMA_WAITOK, 2176 &cd->sis_rx_data[i].sis_map); 2177 if (error) { 2178 int j; 2179 2180 for (j = 0; j < i; ++j) { 2181 bus_dmamap_destroy(cd->sis_rxbuf_tag, 2182 cd->sis_rx_data[j].sis_map); 2183 } 2184 bus_dmamap_destroy(cd->sis_rxbuf_tag, 2185 cd->sis_rx_tmpmap); 2186 bus_dma_tag_destroy(cd->sis_rxbuf_tag); 2187 cd->sis_rxbuf_tag = NULL; 2188 2189 device_printf(dev, "could not create %dth " 2190 "RX buf DMA map\n", i); 2191 return error; 2192 } 2193 } 2194 return 0; 2195 } 2196 2197 static void 2198 sis_dma_free(device_t dev) 2199 { 2200 struct sis_softc *sc = device_get_softc(dev); 2201 struct sis_list_data *ld = &sc->sis_ldata; 2202 struct sis_chain_data *cd = &sc->sis_cdata; 2203 int i; 2204 2205 /* Free TX ring */ 2206 if (ld->sis_tx_list != NULL) { 2207 bus_dmamap_unload(ld->sis_tx_tag, ld->sis_tx_dmamap); 2208 bus_dmamem_free(ld->sis_tx_tag, ld->sis_tx_list, 2209 ld->sis_tx_dmamap); 2210 bus_dma_tag_destroy(ld->sis_tx_tag); 2211 } 2212 2213 /* Free RX ring */ 2214 if (ld->sis_rx_list != NULL) { 2215 bus_dmamap_unload(ld->sis_rx_tag, ld->sis_rx_dmamap); 2216 bus_dmamem_free(ld->sis_rx_tag, ld->sis_rx_list, 2217 ld->sis_rx_dmamap); 2218 bus_dma_tag_destroy(ld->sis_rx_tag); 2219 } 2220 2221 /* Destroy DMA stuffs for TX mbufs */ 2222 if (cd->sis_txbuf_tag != NULL) { 2223 for (i = 0; i < SIS_TX_LIST_CNT; ++i) { 2224 KKASSERT(cd->sis_tx_data[i].sis_mbuf == NULL); 2225 bus_dmamap_destroy(cd->sis_txbuf_tag, 2226 cd->sis_tx_data[i].sis_map); 2227 } 2228 bus_dma_tag_destroy(cd->sis_txbuf_tag); 2229 } 2230 2231 /* Destroy DMA stuffs for RX mbufs */ 2232 if (cd->sis_rxbuf_tag != NULL) { 2233 for (i = 0; i < SIS_RX_LIST_CNT; ++i) { 2234 KKASSERT(cd->sis_rx_data[i].sis_mbuf == NULL); 2235 bus_dmamap_destroy(cd->sis_rxbuf_tag, 2236 cd->sis_rx_data[i].sis_map); 2237 } 2238 bus_dmamap_destroy(cd->sis_rxbuf_tag, cd->sis_rx_tmpmap); 2239 bus_dma_tag_destroy(cd->sis_rxbuf_tag); 2240 } 2241 } 2242