1 /* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: src/sys/pci/if_sis.c,v 1.13.4.24 2003/03/05 18:42:33 njl Exp $ 33 * $DragonFly: src/sys/dev/netif/sis/if_sis.c,v 1.36 2006/10/25 20:55:59 dillon Exp $ 34 */ 35 36 /* 37 * SiS 900/SiS 7016 fast ethernet PCI NIC driver. Datasheets are 38 * available from http://www.sis.com.tw. 39 * 40 * This driver also supports the NatSemi DP83815. Datasheets are 41 * available from http://www.national.com. 42 * 43 * Written by Bill Paul <wpaul@ee.columbia.edu> 44 * Electrical Engineering Department 45 * Columbia University, New York City 46 */ 47 48 /* 49 * The SiS 900 is a fairly simple chip. It uses bus master DMA with 50 * simple TX and RX descriptors of 3 longwords in size. The receiver 51 * has a single perfect filter entry for the station address and a 52 * 128-bit multicast hash table. The SiS 900 has a built-in MII-based 53 * transceiver while the 7016 requires an external transceiver chip. 54 * Both chips offer the standard bit-bang MII interface as well as 55 * an enchanced PHY interface which simplifies accessing MII registers. 56 * 57 * The only downside to this chipset is that RX descriptors must be 58 * longword aligned. 59 */ 60 61 #include "opt_polling.h" 62 63 #include <sys/param.h> 64 #include <sys/systm.h> 65 #include <sys/sockio.h> 66 #include <sys/mbuf.h> 67 #include <sys/malloc.h> 68 #include <sys/kernel.h> 69 #include <sys/socket.h> 70 #include <sys/sysctl.h> 71 #include <sys/serialize.h> 72 #include <sys/thread2.h> 73 #include <sys/bus.h> 74 #include <sys/rman.h> 75 76 #include <net/if.h> 77 #include <net/ifq_var.h> 78 #include <net/if_arp.h> 79 #include <net/ethernet.h> 80 #include <net/if_dl.h> 81 #include <net/if_media.h> 82 #include <net/if_types.h> 83 #include <net/vlan/if_vlan_var.h> 84 85 #include <net/bpf.h> 86 87 #include <dev/netif/mii_layer/mii.h> 88 #include <dev/netif/mii_layer/miivar.h> 89 90 #include <bus/pci/pcidevs.h> 91 #include <bus/pci/pcireg.h> 92 #include <bus/pci/pcivar.h> 93 94 #define SIS_USEIOSPACE 95 96 #include "if_sisreg.h" 97 98 /* "controller miibus0" required. See GENERIC if you get errors here. */ 99 #include "miibus_if.h" 100 101 /* 102 * Various supported device vendors/types and their names. 103 */ 104 static struct sis_type sis_devs[] = { 105 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_900, "SiS 900 10/100BaseTX" }, 106 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_7016, "SiS 7016 10/100BaseTX" }, 107 { PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815, "NatSemi DP8381[56] 10/100BaseTX" }, 108 { 0, 0, NULL } 109 }; 110 111 static int sis_probe(device_t); 112 static int sis_attach(device_t); 113 static int sis_detach(device_t); 114 115 static int sis_newbuf(struct sis_softc *, struct sis_desc *, 116 struct mbuf *); 117 static int sis_encap(struct sis_softc *, struct mbuf *, uint32_t *); 118 static void sis_rxeof(struct sis_softc *); 119 static void sis_rxeoc(struct sis_softc *); 120 static void sis_txeof(struct sis_softc *); 121 static void sis_intr(void *); 122 static void sis_tick(void *); 123 static void sis_start(struct ifnet *); 124 static int sis_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *); 125 static void sis_init(void *); 126 static void sis_stop(struct sis_softc *); 127 static void sis_watchdog(struct ifnet *); 128 static void sis_shutdown(device_t); 129 static int sis_ifmedia_upd(struct ifnet *); 130 static void sis_ifmedia_sts(struct ifnet *, struct ifmediareq *); 131 132 static uint16_t sis_reverse(uint16_t); 133 static void sis_delay(struct sis_softc *); 134 static void sis_eeprom_idle(struct sis_softc *); 135 static void sis_eeprom_putbyte(struct sis_softc *, int); 136 static void sis_eeprom_getword(struct sis_softc *, int, uint16_t *); 137 static void sis_read_eeprom(struct sis_softc *, caddr_t, int, int, int); 138 #ifdef __i386__ 139 static void sis_read_cmos(struct sis_softc *, device_t, caddr_t, int, int); 140 static void sis_read_mac(struct sis_softc *, device_t, caddr_t); 141 static device_t sis_find_bridge(device_t); 142 #endif 143 144 static void sis_mii_sync(struct sis_softc *); 145 static void sis_mii_send(struct sis_softc *, uint32_t, int); 146 static int sis_mii_readreg(struct sis_softc *, struct sis_mii_frame *); 147 static int sis_mii_writereg(struct sis_softc *, struct sis_mii_frame *); 148 static int sis_miibus_readreg(device_t, int, int); 149 static int sis_miibus_writereg(device_t, int, int, int); 150 static void sis_miibus_statchg(device_t); 151 152 static void sis_setmulti_sis(struct sis_softc *); 153 static void sis_setmulti_ns(struct sis_softc *); 154 static uint32_t sis_mchash(struct sis_softc *, const uint8_t *); 155 static void sis_reset(struct sis_softc *); 156 static int sis_list_rx_init(struct sis_softc *); 157 static int sis_list_tx_init(struct sis_softc *); 158 159 static void sis_dma_map_desc_ptr(void *, bus_dma_segment_t *, int, int); 160 static void sis_dma_map_desc_next(void *, bus_dma_segment_t *, int, int); 161 static void sis_dma_map_ring(void *, bus_dma_segment_t *, int, int); 162 #ifdef DEVICE_POLLING 163 static poll_handler_t sis_poll; 164 #endif 165 #ifdef SIS_USEIOSPACE 166 #define SIS_RES SYS_RES_IOPORT 167 #define SIS_RID SIS_PCI_LOIO 168 #else 169 #define SIS_RES SYS_RES_MEMORY 170 #define SIS_RID SIS_PCI_LOMEM 171 #endif 172 173 static device_method_t sis_methods[] = { 174 /* Device interface */ 175 DEVMETHOD(device_probe, sis_probe), 176 DEVMETHOD(device_attach, sis_attach), 177 DEVMETHOD(device_detach, sis_detach), 178 DEVMETHOD(device_shutdown, sis_shutdown), 179 180 /* bus interface */ 181 DEVMETHOD(bus_print_child, bus_generic_print_child), 182 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 183 184 /* MII interface */ 185 DEVMETHOD(miibus_readreg, sis_miibus_readreg), 186 DEVMETHOD(miibus_writereg, sis_miibus_writereg), 187 DEVMETHOD(miibus_statchg, sis_miibus_statchg), 188 189 { 0, 0 } 190 }; 191 192 static driver_t sis_driver = { 193 "sis", 194 sis_methods, 195 sizeof(struct sis_softc) 196 }; 197 198 static devclass_t sis_devclass; 199 200 DECLARE_DUMMY_MODULE(if_sis); 201 DRIVER_MODULE(if_sis, pci, sis_driver, sis_devclass, 0, 0); 202 DRIVER_MODULE(miibus, sis, miibus_driver, miibus_devclass, 0, 0); 203 204 #define SIS_SETBIT(sc, reg, x) \ 205 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x)) 206 207 #define SIS_CLRBIT(sc, reg, x) \ 208 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x)) 209 210 #define SIO_SET(x) \ 211 CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) | x) 212 213 #define SIO_CLR(x) \ 214 CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) & ~x) 215 216 static void 217 sis_dma_map_desc_next(void *arg, bus_dma_segment_t *segs, int nseg, int error) 218 { 219 struct sis_desc *r; 220 221 r = arg; 222 r->sis_next = segs->ds_addr; 223 } 224 225 static void 226 sis_dma_map_desc_ptr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 227 { 228 struct sis_desc *r; 229 230 r = arg; 231 r->sis_ptr = segs->ds_addr; 232 } 233 234 static void 235 sis_dma_map_ring(void *arg, bus_dma_segment_t *segs, int nseg, int error) 236 { 237 uint32_t *p; 238 239 p = arg; 240 *p = segs->ds_addr; 241 } 242 243 /* 244 * Routine to reverse the bits in a word. Stolen almost 245 * verbatim from /usr/games/fortune. 246 */ 247 static uint16_t 248 sis_reverse(uint16_t n) 249 { 250 n = ((n >> 1) & 0x5555) | ((n << 1) & 0xaaaa); 251 n = ((n >> 2) & 0x3333) | ((n << 2) & 0xcccc); 252 n = ((n >> 4) & 0x0f0f) | ((n << 4) & 0xf0f0); 253 n = ((n >> 8) & 0x00ff) | ((n << 8) & 0xff00); 254 255 return(n); 256 } 257 258 static void 259 sis_delay(struct sis_softc *sc) 260 { 261 int idx; 262 263 for (idx = (300 / 33) + 1; idx > 0; idx--) 264 CSR_READ_4(sc, SIS_CSR); 265 } 266 267 static void 268 sis_eeprom_idle(struct sis_softc *sc) 269 { 270 int i; 271 272 SIO_SET(SIS_EECTL_CSEL); 273 sis_delay(sc); 274 SIO_SET(SIS_EECTL_CLK); 275 sis_delay(sc); 276 277 for (i = 0; i < 25; i++) { 278 SIO_CLR(SIS_EECTL_CLK); 279 sis_delay(sc); 280 SIO_SET(SIS_EECTL_CLK); 281 sis_delay(sc); 282 } 283 284 SIO_CLR(SIS_EECTL_CLK); 285 sis_delay(sc); 286 SIO_CLR(SIS_EECTL_CSEL); 287 sis_delay(sc); 288 CSR_WRITE_4(sc, SIS_EECTL, 0x00000000); 289 } 290 291 /* 292 * Send a read command and address to the EEPROM, check for ACK. 293 */ 294 static void 295 sis_eeprom_putbyte(struct sis_softc *sc, int addr) 296 { 297 int d, i; 298 299 d = addr | SIS_EECMD_READ; 300 301 /* 302 * Feed in each bit and stobe the clock. 303 */ 304 for (i = 0x400; i; i >>= 1) { 305 if (d & i) 306 SIO_SET(SIS_EECTL_DIN); 307 else 308 SIO_CLR(SIS_EECTL_DIN); 309 sis_delay(sc); 310 SIO_SET(SIS_EECTL_CLK); 311 sis_delay(sc); 312 SIO_CLR(SIS_EECTL_CLK); 313 sis_delay(sc); 314 } 315 } 316 317 /* 318 * Read a word of data stored in the EEPROM at address 'addr.' 319 */ 320 static void 321 sis_eeprom_getword(struct sis_softc *sc, int addr, uint16_t *dest) 322 { 323 int i; 324 uint16_t word = 0; 325 326 /* Force EEPROM to idle state. */ 327 sis_eeprom_idle(sc); 328 329 /* Enter EEPROM access mode. */ 330 sis_delay(sc); 331 SIO_CLR(SIS_EECTL_CLK); 332 sis_delay(sc); 333 SIO_SET(SIS_EECTL_CSEL); 334 sis_delay(sc); 335 336 /* 337 * Send address of word we want to read. 338 */ 339 sis_eeprom_putbyte(sc, addr); 340 341 /* 342 * Start reading bits from EEPROM. 343 */ 344 for (i = 0x8000; i; i >>= 1) { 345 SIO_SET(SIS_EECTL_CLK); 346 sis_delay(sc); 347 if (CSR_READ_4(sc, SIS_EECTL) & SIS_EECTL_DOUT) 348 word |= i; 349 sis_delay(sc); 350 SIO_CLR(SIS_EECTL_CLK); 351 sis_delay(sc); 352 } 353 354 /* Turn off EEPROM access mode. */ 355 sis_eeprom_idle(sc); 356 357 *dest = word; 358 } 359 360 /* 361 * Read a sequence of words from the EEPROM. 362 */ 363 static void 364 sis_read_eeprom(struct sis_softc *sc, caddr_t dest, int off, int cnt, int swap) 365 { 366 int i; 367 uint16_t word = 0, *ptr; 368 369 for (i = 0; i < cnt; i++) { 370 sis_eeprom_getword(sc, off + i, &word); 371 ptr = (uint16_t *)(dest + (i * 2)); 372 if (swap) 373 *ptr = ntohs(word); 374 else 375 *ptr = word; 376 } 377 } 378 379 #ifdef __i386__ 380 static device_t 381 sis_find_bridge(device_t dev) 382 { 383 devclass_t pci_devclass; 384 device_t *pci_devices; 385 int pci_count = 0; 386 device_t *pci_children; 387 int pci_childcount = 0; 388 device_t *busp, *childp; 389 device_t child = NULL; 390 int i, j; 391 392 if ((pci_devclass = devclass_find("pci")) == NULL) 393 return(NULL); 394 395 devclass_get_devices(pci_devclass, &pci_devices, &pci_count); 396 397 for (i = 0, busp = pci_devices; i < pci_count; i++, busp++) { 398 pci_childcount = 0; 399 device_get_children(*busp, &pci_children, &pci_childcount); 400 for (j = 0, childp = pci_children; j < pci_childcount; 401 j++, childp++) { 402 if (pci_get_vendor(*childp) == PCI_VENDOR_SIS && 403 pci_get_device(*childp) == 0x0008) { 404 child = *childp; 405 goto done; 406 } 407 } 408 } 409 410 done: 411 kfree(pci_devices, M_TEMP); 412 kfree(pci_children, M_TEMP); 413 return(child); 414 } 415 416 static void 417 sis_read_cmos(struct sis_softc *sc, device_t dev, caddr_t dest, int off, 418 int cnt) 419 { 420 device_t bridge; 421 uint8_t reg; 422 int i; 423 bus_space_tag_t btag; 424 425 bridge = sis_find_bridge(dev); 426 if (bridge == NULL) 427 return; 428 reg = pci_read_config(bridge, 0x48, 1); 429 pci_write_config(bridge, 0x48, reg|0x40, 1); 430 431 /* XXX */ 432 btag = I386_BUS_SPACE_IO; 433 434 for (i = 0; i < cnt; i++) { 435 bus_space_write_1(btag, 0x0, 0x70, i + off); 436 *(dest + i) = bus_space_read_1(btag, 0x0, 0x71); 437 } 438 439 pci_write_config(bridge, 0x48, reg & ~0x40, 1); 440 } 441 442 static void 443 sis_read_mac(struct sis_softc *sc, device_t dev, caddr_t dest) 444 { 445 uint32_t filtsave, csrsave; 446 447 filtsave = CSR_READ_4(sc, SIS_RXFILT_CTL); 448 csrsave = CSR_READ_4(sc, SIS_CSR); 449 450 CSR_WRITE_4(sc, SIS_CSR, SIS_CSR_RELOAD | filtsave); 451 CSR_WRITE_4(sc, SIS_CSR, 0); 452 453 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave & ~SIS_RXFILTCTL_ENABLE); 454 455 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR0); 456 ((uint16_t *)dest)[0] = CSR_READ_2(sc, SIS_RXFILT_DATA); 457 CSR_WRITE_4(sc, SIS_RXFILT_CTL,SIS_FILTADDR_PAR1); 458 ((uint16_t *)dest)[1] = CSR_READ_2(sc, SIS_RXFILT_DATA); 459 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR2); 460 ((uint16_t *)dest)[2] = CSR_READ_2(sc, SIS_RXFILT_DATA); 461 462 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave); 463 CSR_WRITE_4(sc, SIS_CSR, csrsave); 464 } 465 #endif 466 467 /* 468 * Sync the PHYs by setting data bit and strobing the clock 32 times. 469 */ 470 static void 471 sis_mii_sync(struct sis_softc *sc) 472 { 473 int i; 474 475 SIO_SET(SIS_MII_DIR|SIS_MII_DATA); 476 477 for (i = 0; i < 32; i++) { 478 SIO_SET(SIS_MII_CLK); 479 DELAY(1); 480 SIO_CLR(SIS_MII_CLK); 481 DELAY(1); 482 } 483 } 484 485 /* 486 * Clock a series of bits through the MII. 487 */ 488 static void 489 sis_mii_send(struct sis_softc *sc, uint32_t bits, int cnt) 490 { 491 int i; 492 493 SIO_CLR(SIS_MII_CLK); 494 495 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 496 if (bits & i) 497 SIO_SET(SIS_MII_DATA); 498 else 499 SIO_CLR(SIS_MII_DATA); 500 DELAY(1); 501 SIO_CLR(SIS_MII_CLK); 502 DELAY(1); 503 SIO_SET(SIS_MII_CLK); 504 } 505 } 506 507 /* 508 * Read an PHY register through the MII. 509 */ 510 static int 511 sis_mii_readreg(struct sis_softc *sc, struct sis_mii_frame *frame) 512 { 513 int i, ack; 514 515 /* 516 * Set up frame for RX. 517 */ 518 frame->mii_stdelim = SIS_MII_STARTDELIM; 519 frame->mii_opcode = SIS_MII_READOP; 520 frame->mii_turnaround = 0; 521 frame->mii_data = 0; 522 523 /* 524 * Turn on data xmit. 525 */ 526 SIO_SET(SIS_MII_DIR); 527 528 sis_mii_sync(sc); 529 530 /* 531 * Send command/address info. 532 */ 533 sis_mii_send(sc, frame->mii_stdelim, 2); 534 sis_mii_send(sc, frame->mii_opcode, 2); 535 sis_mii_send(sc, frame->mii_phyaddr, 5); 536 sis_mii_send(sc, frame->mii_regaddr, 5); 537 538 /* Idle bit */ 539 SIO_CLR((SIS_MII_CLK|SIS_MII_DATA)); 540 DELAY(1); 541 SIO_SET(SIS_MII_CLK); 542 DELAY(1); 543 544 /* Turn off xmit. */ 545 SIO_CLR(SIS_MII_DIR); 546 547 /* Check for ack */ 548 SIO_CLR(SIS_MII_CLK); 549 DELAY(1); 550 ack = CSR_READ_4(sc, SIS_EECTL) & SIS_MII_DATA; 551 SIO_SET(SIS_MII_CLK); 552 DELAY(1); 553 554 /* 555 * Now try reading data bits. If the ack failed, we still 556 * need to clock through 16 cycles to keep the PHY(s) in sync. 557 */ 558 if (ack) { 559 for(i = 0; i < 16; i++) { 560 SIO_CLR(SIS_MII_CLK); 561 DELAY(1); 562 SIO_SET(SIS_MII_CLK); 563 DELAY(1); 564 } 565 goto fail; 566 } 567 568 for (i = 0x8000; i; i >>= 1) { 569 SIO_CLR(SIS_MII_CLK); 570 DELAY(1); 571 if (!ack) { 572 if (CSR_READ_4(sc, SIS_EECTL) & SIS_MII_DATA) 573 frame->mii_data |= i; 574 DELAY(1); 575 } 576 SIO_SET(SIS_MII_CLK); 577 DELAY(1); 578 } 579 580 fail: 581 582 SIO_CLR(SIS_MII_CLK); 583 DELAY(1); 584 SIO_SET(SIS_MII_CLK); 585 DELAY(1); 586 587 if (ack) 588 return(1); 589 return(0); 590 } 591 592 /* 593 * Write to a PHY register through the MII. 594 */ 595 static int 596 sis_mii_writereg(struct sis_softc *sc, struct sis_mii_frame *frame) 597 { 598 /* 599 * Set up frame for TX. 600 */ 601 602 frame->mii_stdelim = SIS_MII_STARTDELIM; 603 frame->mii_opcode = SIS_MII_WRITEOP; 604 frame->mii_turnaround = SIS_MII_TURNAROUND; 605 606 /* 607 * Turn on data output. 608 */ 609 SIO_SET(SIS_MII_DIR); 610 611 sis_mii_sync(sc); 612 613 sis_mii_send(sc, frame->mii_stdelim, 2); 614 sis_mii_send(sc, frame->mii_opcode, 2); 615 sis_mii_send(sc, frame->mii_phyaddr, 5); 616 sis_mii_send(sc, frame->mii_regaddr, 5); 617 sis_mii_send(sc, frame->mii_turnaround, 2); 618 sis_mii_send(sc, frame->mii_data, 16); 619 620 /* Idle bit. */ 621 SIO_SET(SIS_MII_CLK); 622 DELAY(1); 623 SIO_CLR(SIS_MII_CLK); 624 DELAY(1); 625 626 /* 627 * Turn off xmit. 628 */ 629 SIO_CLR(SIS_MII_DIR); 630 631 return(0); 632 } 633 634 static int 635 sis_miibus_readreg(device_t dev, int phy, int reg) 636 { 637 struct sis_softc *sc; 638 struct sis_mii_frame frame; 639 640 sc = device_get_softc(dev); 641 642 if (sc->sis_type == SIS_TYPE_83815) { 643 if (phy != 0) 644 return(0); 645 /* 646 * The NatSemi chip can take a while after 647 * a reset to come ready, during which the BMSR 648 * returns a value of 0. This is *never* supposed 649 * to happen: some of the BMSR bits are meant to 650 * be hardwired in the on position, and this can 651 * confuse the miibus code a bit during the probe 652 * and attach phase. So we make an effort to check 653 * for this condition and wait for it to clear. 654 */ 655 if (!CSR_READ_4(sc, NS_BMSR)) 656 DELAY(1000); 657 return CSR_READ_4(sc, NS_BMCR + (reg * 4)); 658 } 659 /* 660 * Chipsets < SIS_635 seem not to be able to read/write 661 * through mdio. Use the enhanced PHY access register 662 * again for them. 663 */ 664 if (sc->sis_type == SIS_TYPE_900 && 665 sc->sis_rev < SIS_REV_635) { 666 int i, val = 0; 667 668 if (phy != 0) 669 return(0); 670 671 CSR_WRITE_4(sc, SIS_PHYCTL, 672 (phy << 11) | (reg << 6) | SIS_PHYOP_READ); 673 SIS_SETBIT(sc, SIS_PHYCTL, SIS_PHYCTL_ACCESS); 674 675 for (i = 0; i < SIS_TIMEOUT; i++) { 676 if (!(CSR_READ_4(sc, SIS_PHYCTL) & SIS_PHYCTL_ACCESS)) 677 break; 678 } 679 680 if (i == SIS_TIMEOUT) { 681 device_printf(dev, "PHY failed to come ready\n"); 682 return(0); 683 } 684 685 val = (CSR_READ_4(sc, SIS_PHYCTL) >> 16) & 0xFFFF; 686 687 if (val == 0xFFFF) 688 return(0); 689 690 return(val); 691 } else { 692 bzero((char *)&frame, sizeof(frame)); 693 694 frame.mii_phyaddr = phy; 695 frame.mii_regaddr = reg; 696 sis_mii_readreg(sc, &frame); 697 698 return(frame.mii_data); 699 } 700 } 701 702 static int 703 sis_miibus_writereg(device_t dev, int phy, int reg, int data) 704 { 705 struct sis_softc *sc; 706 struct sis_mii_frame frame; 707 708 sc = device_get_softc(dev); 709 710 if (sc->sis_type == SIS_TYPE_83815) { 711 if (phy != 0) 712 return(0); 713 CSR_WRITE_4(sc, NS_BMCR + (reg * 4), data); 714 return(0); 715 } 716 717 if (sc->sis_type == SIS_TYPE_900 && 718 sc->sis_rev < SIS_REV_635) { 719 int i; 720 721 if (phy != 0) 722 return(0); 723 724 CSR_WRITE_4(sc, SIS_PHYCTL, (data << 16) | (phy << 11) | 725 (reg << 6) | SIS_PHYOP_WRITE); 726 SIS_SETBIT(sc, SIS_PHYCTL, SIS_PHYCTL_ACCESS); 727 728 for (i = 0; i < SIS_TIMEOUT; i++) { 729 if (!(CSR_READ_4(sc, SIS_PHYCTL) & SIS_PHYCTL_ACCESS)) 730 break; 731 } 732 733 if (i == SIS_TIMEOUT) 734 device_printf(dev, "PHY failed to come ready\n"); 735 } else { 736 bzero((char *)&frame, sizeof(frame)); 737 738 frame.mii_phyaddr = phy; 739 frame.mii_regaddr = reg; 740 frame.mii_data = data; 741 sis_mii_writereg(sc, &frame); 742 } 743 return(0); 744 } 745 746 static void 747 sis_miibus_statchg(device_t dev) 748 { 749 struct sis_softc *sc; 750 751 sc = device_get_softc(dev); 752 sis_init(sc); 753 } 754 755 static uint32_t 756 sis_mchash(struct sis_softc *sc, const uint8_t *addr) 757 { 758 uint32_t crc, carry; 759 int i, j; 760 uint8_t c; 761 762 /* Compute CRC for the address value. */ 763 crc = 0xFFFFFFFF; /* initial value */ 764 765 for (i = 0; i < 6; i++) { 766 c = *(addr + i); 767 for (j = 0; j < 8; j++) { 768 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 769 crc <<= 1; 770 c >>= 1; 771 if (carry) 772 crc = (crc ^ 0x04c11db6) | carry; 773 } 774 } 775 776 /* 777 * return the filter bit position 778 * 779 * The NatSemi chip has a 512-bit filter, which is 780 * different than the SiS, so we special-case it. 781 */ 782 if (sc->sis_type == SIS_TYPE_83815) 783 return (crc >> 23); 784 else if (sc->sis_rev >= SIS_REV_635 || sc->sis_rev == SIS_REV_900B) 785 return (crc >> 24); 786 else 787 return (crc >> 25); 788 } 789 790 static void 791 sis_setmulti_ns(struct sis_softc *sc) 792 { 793 struct ifnet *ifp; 794 struct ifmultiaddr *ifma; 795 uint32_t h = 0, i, filtsave; 796 int bit, index; 797 798 ifp = &sc->arpcom.ac_if; 799 800 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 801 SIS_CLRBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_MCHASH); 802 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLMULTI); 803 return; 804 } 805 806 /* 807 * We have to explicitly enable the multicast hash table 808 * on the NatSemi chip if we want to use it, which we do. 809 */ 810 SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_MCHASH); 811 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLMULTI); 812 813 filtsave = CSR_READ_4(sc, SIS_RXFILT_CTL); 814 815 /* first, zot all the existing hash bits */ 816 for (i = 0; i < 32; i++) { 817 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_FMEM_LO + (i*2)); 818 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 0); 819 } 820 821 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 822 if (ifma->ifma_addr->sa_family != AF_LINK) 823 continue; 824 h = sis_mchash(sc, 825 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 826 index = h >> 3; 827 bit = h & 0x1F; 828 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_FMEM_LO + index); 829 if (bit > 0xF) 830 bit -= 0x10; 831 SIS_SETBIT(sc, SIS_RXFILT_DATA, (1 << bit)); 832 } 833 834 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave); 835 } 836 837 static void 838 sis_setmulti_sis(struct sis_softc *sc) 839 { 840 struct ifnet *ifp; 841 struct ifmultiaddr *ifma; 842 uint32_t h, i, n, ctl; 843 uint16_t hashes[16]; 844 845 ifp = &sc->arpcom.ac_if; 846 847 /* hash table size */ 848 if (sc->sis_rev >= SIS_REV_635 || sc->sis_rev == SIS_REV_900B) 849 n = 16; 850 else 851 n = 8; 852 853 ctl = CSR_READ_4(sc, SIS_RXFILT_CTL) & SIS_RXFILTCTL_ENABLE; 854 855 if (ifp->if_flags & IFF_BROADCAST) 856 ctl |= SIS_RXFILTCTL_BROAD; 857 858 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 859 ctl |= SIS_RXFILTCTL_ALLMULTI; 860 if (ifp->if_flags & IFF_PROMISC) 861 ctl |= SIS_RXFILTCTL_BROAD|SIS_RXFILTCTL_ALLPHYS; 862 for (i = 0; i < n; i++) 863 hashes[i] = ~0; 864 } else { 865 for (i = 0; i < n; i++) 866 hashes[i] = 0; 867 i = 0; 868 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 869 if (ifma->ifma_addr->sa_family != AF_LINK) 870 continue; 871 h = sis_mchash(sc, 872 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 873 hashes[h >> 4] |= 1 << (h & 0xf); 874 i++; 875 } 876 if (i > n) { 877 ctl |= SIS_RXFILTCTL_ALLMULTI; 878 for (i = 0; i < n; i++) 879 hashes[i] = ~0; 880 } 881 } 882 883 for (i = 0; i < n; i++) { 884 CSR_WRITE_4(sc, SIS_RXFILT_CTL, (4 + i) << 16); 885 CSR_WRITE_4(sc, SIS_RXFILT_DATA, hashes[i]); 886 } 887 888 CSR_WRITE_4(sc, SIS_RXFILT_CTL, ctl); 889 } 890 891 static void 892 sis_reset(struct sis_softc *sc) 893 { 894 struct ifnet *ifp = &sc->arpcom.ac_if; 895 int i; 896 897 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RESET); 898 899 for (i = 0; i < SIS_TIMEOUT; i++) { 900 if (!(CSR_READ_4(sc, SIS_CSR) & SIS_CSR_RESET)) 901 break; 902 } 903 904 if (i == SIS_TIMEOUT) 905 if_printf(ifp, "reset never completed\n"); 906 907 /* Wait a little while for the chip to get its brains in order. */ 908 DELAY(1000); 909 910 /* 911 * If this is a NetSemi chip, make sure to clear 912 * PME mode. 913 */ 914 if (sc->sis_type == SIS_TYPE_83815) { 915 CSR_WRITE_4(sc, NS_CLKRUN, NS_CLKRUN_PMESTS); 916 CSR_WRITE_4(sc, NS_CLKRUN, 0); 917 } 918 } 919 920 /* 921 * Probe for an SiS chip. Check the PCI vendor and device 922 * IDs against our list and return a device name if we find a match. 923 */ 924 static int 925 sis_probe(device_t dev) 926 { 927 struct sis_type *t; 928 929 t = sis_devs; 930 931 while(t->sis_name != NULL) { 932 if ((pci_get_vendor(dev) == t->sis_vid) && 933 (pci_get_device(dev) == t->sis_did)) { 934 device_set_desc(dev, t->sis_name); 935 return(0); 936 } 937 t++; 938 } 939 940 return(ENXIO); 941 } 942 943 /* 944 * Attach the interface. Allocate softc structures, do ifmedia 945 * setup and ethernet/BPF attach. 946 */ 947 static int 948 sis_attach(device_t dev) 949 { 950 uint8_t eaddr[ETHER_ADDR_LEN]; 951 uint32_t command; 952 struct sis_softc *sc; 953 struct ifnet *ifp; 954 int error, rid, waittime; 955 956 error = waittime = 0; 957 sc = device_get_softc(dev); 958 959 if (pci_get_device(dev) == PCI_PRODUCT_SIS_900) 960 sc->sis_type = SIS_TYPE_900; 961 if (pci_get_device(dev) == PCI_PRODUCT_SIS_7016) 962 sc->sis_type = SIS_TYPE_7016; 963 if (pci_get_vendor(dev) == PCI_VENDOR_NS) 964 sc->sis_type = SIS_TYPE_83815; 965 966 sc->sis_rev = pci_read_config(dev, PCIR_REVID, 1); 967 968 /* 969 * Handle power management nonsense. 970 */ 971 972 command = pci_read_config(dev, SIS_PCI_CAPID, 4) & 0x000000FF; 973 if (command == 0x01) { 974 975 command = pci_read_config(dev, SIS_PCI_PWRMGMTCTRL, 4); 976 if (command & SIS_PSTATE_MASK) { 977 uint32_t iobase, membase, irq; 978 979 /* Save important PCI config data. */ 980 iobase = pci_read_config(dev, SIS_PCI_LOIO, 4); 981 membase = pci_read_config(dev, SIS_PCI_LOMEM, 4); 982 irq = pci_read_config(dev, SIS_PCI_INTLINE, 4); 983 984 /* Reset the power state. */ 985 device_printf(dev, "chip is in D%d power mode " 986 "-- setting to D0\n", command & SIS_PSTATE_MASK); 987 command &= 0xFFFFFFFC; 988 pci_write_config(dev, SIS_PCI_PWRMGMTCTRL, command, 4); 989 990 /* Restore PCI config data. */ 991 pci_write_config(dev, SIS_PCI_LOIO, iobase, 4); 992 pci_write_config(dev, SIS_PCI_LOMEM, membase, 4); 993 pci_write_config(dev, SIS_PCI_INTLINE, irq, 4); 994 } 995 } 996 997 /* 998 * Map control/status registers. 999 */ 1000 command = pci_read_config(dev, PCIR_COMMAND, 4); 1001 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 1002 pci_write_config(dev, PCIR_COMMAND, command, 4); 1003 command = pci_read_config(dev, PCIR_COMMAND, 4); 1004 1005 #ifdef SIS_USEIOSPACE 1006 if (!(command & PCIM_CMD_PORTEN)) { 1007 device_printf(dev, "failed to enable I/O ports!\n"); 1008 error = ENXIO; 1009 goto fail; 1010 } 1011 #else 1012 if (!(command & PCIM_CMD_MEMEN)) { 1013 device_printf(dev, "failed to enable memory mapping!\n"); 1014 error = ENXIO; 1015 goto fail; 1016 } 1017 #endif 1018 1019 rid = SIS_RID; 1020 sc->sis_res = bus_alloc_resource_any(dev, SIS_RES, &rid, RF_ACTIVE); 1021 1022 if (sc->sis_res == NULL) { 1023 device_printf(dev, "couldn't map ports/memory\n"); 1024 error = ENXIO; 1025 goto fail; 1026 } 1027 1028 sc->sis_btag = rman_get_bustag(sc->sis_res); 1029 sc->sis_bhandle = rman_get_bushandle(sc->sis_res); 1030 1031 /* Allocate interrupt */ 1032 rid = 0; 1033 sc->sis_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1034 RF_SHAREABLE | RF_ACTIVE); 1035 1036 if (sc->sis_irq == NULL) { 1037 device_printf(dev, "couldn't map interrupt\n"); 1038 error = ENXIO; 1039 goto fail; 1040 } 1041 1042 /* Reset the adapter. */ 1043 sis_reset(sc); 1044 1045 if (sc->sis_type == SIS_TYPE_900 && 1046 (sc->sis_rev == SIS_REV_635 || 1047 sc->sis_rev == SIS_REV_900B)) { 1048 SIO_SET(SIS_CFG_RND_CNT); 1049 SIO_SET(SIS_CFG_PERR_DETECT); 1050 } 1051 1052 /* 1053 * Get station address from the EEPROM. 1054 */ 1055 switch (pci_get_vendor(dev)) { 1056 case PCI_VENDOR_NS: 1057 /* 1058 * Reading the MAC address out of the EEPROM on 1059 * the NatSemi chip takes a bit more work than 1060 * you'd expect. The address spans 4 16-bit words, 1061 * with the first word containing only a single bit. 1062 * You have to shift everything over one bit to 1063 * get it aligned properly. Also, the bits are 1064 * stored backwards (the LSB is really the MSB, 1065 * and so on) so you have to reverse them in order 1066 * to get the MAC address into the form we want. 1067 * Why? Who the hell knows. 1068 */ 1069 { 1070 uint16_t tmp[4]; 1071 1072 sis_read_eeprom(sc, (caddr_t)&tmp, 1073 NS_EE_NODEADDR, 4, 0); 1074 1075 /* Shift everything over one bit. */ 1076 tmp[3] = tmp[3] >> 1; 1077 tmp[3] |= tmp[2] << 15; 1078 tmp[2] = tmp[2] >> 1; 1079 tmp[2] |= tmp[1] << 15; 1080 tmp[1] = tmp[1] >> 1; 1081 tmp[1] |= tmp[0] << 15; 1082 1083 /* Now reverse all the bits. */ 1084 tmp[3] = sis_reverse(tmp[3]); 1085 tmp[2] = sis_reverse(tmp[2]); 1086 tmp[1] = sis_reverse(tmp[1]); 1087 1088 bcopy((char *)&tmp[1], eaddr, ETHER_ADDR_LEN); 1089 } 1090 break; 1091 case PCI_VENDOR_SIS: 1092 default: 1093 #ifdef __i386__ 1094 /* 1095 * If this is a SiS 630E chipset with an embedded 1096 * SiS 900 controller, we have to read the MAC address 1097 * from the APC CMOS RAM. Our method for doing this 1098 * is very ugly since we have to reach out and grab 1099 * ahold of hardware for which we cannot properly 1100 * allocate resources. This code is only compiled on 1101 * the i386 architecture since the SiS 630E chipset 1102 * is for x86 motherboards only. Note that there are 1103 * a lot of magic numbers in this hack. These are 1104 * taken from SiS's Linux driver. I'd like to replace 1105 * them with proper symbolic definitions, but that 1106 * requires some datasheets that I don't have access 1107 * to at the moment. 1108 */ 1109 if (sc->sis_rev == SIS_REV_630S || 1110 sc->sis_rev == SIS_REV_630E || 1111 sc->sis_rev == SIS_REV_630EA1) 1112 sis_read_cmos(sc, dev, (caddr_t)&eaddr, 0x9, 6); 1113 1114 else if (sc->sis_rev == SIS_REV_635 || 1115 sc->sis_rev == SIS_REV_630ET) 1116 sis_read_mac(sc, dev, (caddr_t)&eaddr); 1117 else if (sc->sis_rev == SIS_REV_96x) { 1118 /* 1119 * Allow to read EEPROM from LAN. It is shared 1120 * between a 1394 controller and the NIC and each 1121 * time we access it, we need to set SIS_EECMD_REQ. 1122 */ 1123 SIO_SET(SIS_EECMD_REQ); 1124 for (waittime = 0; waittime < SIS_TIMEOUT; 1125 waittime++) { 1126 /* Force EEPROM to idle state. */ 1127 sis_eeprom_idle(sc); 1128 if (CSR_READ_4(sc, SIS_EECTL) & SIS_EECMD_GNT) { 1129 sis_read_eeprom(sc, (caddr_t)&eaddr, 1130 SIS_EE_NODEADDR, 3, 0); 1131 break; 1132 } 1133 DELAY(1); 1134 } 1135 /* 1136 * Set SIS_EECTL_CLK to high, so a other master 1137 * can operate on the i2c bus. 1138 */ 1139 SIO_SET(SIS_EECTL_CLK); 1140 /* Refuse EEPROM access by LAN */ 1141 SIO_SET(SIS_EECMD_DONE); 1142 } else 1143 #endif 1144 sis_read_eeprom(sc, (caddr_t)&eaddr, 1145 SIS_EE_NODEADDR, 3, 0); 1146 break; 1147 } 1148 1149 callout_init(&sc->sis_timer); 1150 1151 /* 1152 * Allocate the parent bus DMA tag appropriate for PCI. 1153 */ 1154 #define SIS_NSEG_NEW 32 1155 error = bus_dma_tag_create(NULL, /* parent */ 1156 1, 0, /* alignment, boundary */ 1157 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */ 1158 BUS_SPACE_MAXADDR, /* highaddr */ 1159 NULL, NULL, /* filter, filterarg */ 1160 MAXBSIZE, SIS_NSEG_NEW, /* maxsize, nsegments */ 1161 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1162 BUS_DMA_ALLOCNOW, /* flags */ 1163 &sc->sis_parent_tag); 1164 if (error) 1165 goto fail; 1166 1167 /* 1168 * Now allocate a tag for the DMA descriptor lists and a chunk 1169 * of DMA-able memory based on the tag. Also obtain the physical 1170 * addresses of the RX and TX ring, which we'll need later. 1171 * All of our lists are allocated as a contiguous block of memory. 1172 */ 1173 error = bus_dma_tag_create(sc->sis_parent_tag, /* parent */ 1174 1, 0, /* alignment, boundary */ 1175 BUS_SPACE_MAXADDR, /* lowaddr */ 1176 BUS_SPACE_MAXADDR, /* highaddr */ 1177 NULL, NULL, /* filter, filterarg */ 1178 SIS_RX_LIST_SZ, 1, /* maxsize, nsegments */ 1179 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1180 0, /* flags */ 1181 &sc->sis_ldata.sis_rx_tag); 1182 if (error) 1183 goto fail; 1184 1185 error = bus_dmamem_alloc(sc->sis_ldata.sis_rx_tag, 1186 (void **)&sc->sis_ldata.sis_rx_list, 1187 BUS_DMA_WAITOK | BUS_DMA_ZERO, 1188 &sc->sis_ldata.sis_rx_dmamap); 1189 1190 if (error) { 1191 device_printf(dev, "no memory for rx list buffers!\n"); 1192 bus_dma_tag_destroy(sc->sis_ldata.sis_rx_tag); 1193 sc->sis_ldata.sis_rx_tag = NULL; 1194 goto fail; 1195 } 1196 1197 error = bus_dmamap_load(sc->sis_ldata.sis_rx_tag, 1198 sc->sis_ldata.sis_rx_dmamap, 1199 sc->sis_ldata.sis_rx_list, 1200 sizeof(struct sis_desc), sis_dma_map_ring, 1201 &sc->sis_cdata.sis_rx_paddr, 0); 1202 1203 if (error) { 1204 device_printf(dev, "cannot get address of the rx ring!\n"); 1205 bus_dmamem_free(sc->sis_ldata.sis_rx_tag, 1206 sc->sis_ldata.sis_rx_list, 1207 sc->sis_ldata.sis_rx_dmamap); 1208 bus_dma_tag_destroy(sc->sis_ldata.sis_rx_tag); 1209 sc->sis_ldata.sis_rx_tag = NULL; 1210 goto fail; 1211 } 1212 1213 error = bus_dma_tag_create(sc->sis_parent_tag, /* parent */ 1214 1, 0, /* alignment, boundary */ 1215 BUS_SPACE_MAXADDR, /* lowaddr */ 1216 BUS_SPACE_MAXADDR, /* highaddr */ 1217 NULL, NULL, /* filter, filterarg */ 1218 SIS_TX_LIST_SZ, 1, /* maxsize, nsegments */ 1219 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1220 0, /* flags */ 1221 &sc->sis_ldata.sis_tx_tag); 1222 if (error) 1223 goto fail; 1224 1225 error = bus_dmamem_alloc(sc->sis_ldata.sis_tx_tag, 1226 (void **)&sc->sis_ldata.sis_tx_list, 1227 BUS_DMA_WAITOK | BUS_DMA_ZERO, 1228 &sc->sis_ldata.sis_tx_dmamap); 1229 1230 if (error) { 1231 device_printf(dev, "no memory for tx list buffers!\n"); 1232 bus_dma_tag_destroy(sc->sis_ldata.sis_tx_tag); 1233 sc->sis_ldata.sis_tx_tag = NULL; 1234 goto fail; 1235 } 1236 1237 error = bus_dmamap_load(sc->sis_ldata.sis_tx_tag, 1238 sc->sis_ldata.sis_tx_dmamap, 1239 sc->sis_ldata.sis_tx_list, 1240 sizeof(struct sis_desc), sis_dma_map_ring, 1241 &sc->sis_cdata.sis_tx_paddr, 0); 1242 1243 if (error) { 1244 device_printf(dev, "cannot get address of the tx ring!\n"); 1245 bus_dmamem_free(sc->sis_ldata.sis_tx_tag, 1246 sc->sis_ldata.sis_tx_list, 1247 sc->sis_ldata.sis_tx_dmamap); 1248 bus_dma_tag_destroy(sc->sis_ldata.sis_tx_tag); 1249 sc->sis_ldata.sis_tx_tag = NULL; 1250 goto fail; 1251 } 1252 1253 error = bus_dma_tag_create(sc->sis_parent_tag, /* parent */ 1254 1, 0, /* alignment, boundary */ 1255 BUS_SPACE_MAXADDR, /* lowaddr */ 1256 BUS_SPACE_MAXADDR, /* highaddr */ 1257 NULL, NULL, /* filter, filterarg */ 1258 MCLBYTES, 1, /* maxsize, nsegments */ 1259 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1260 0, /* flags */ 1261 &sc->sis_tag); 1262 if (error) 1263 goto fail; 1264 1265 ifp = &sc->arpcom.ac_if; 1266 ifp->if_softc = sc; 1267 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1268 ifp->if_mtu = ETHERMTU; 1269 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1270 ifp->if_ioctl = sis_ioctl; 1271 ifp->if_start = sis_start; 1272 ifp->if_watchdog = sis_watchdog; 1273 ifp->if_init = sis_init; 1274 ifp->if_baudrate = 10000000; 1275 ifq_set_maxlen(&ifp->if_snd, SIS_TX_LIST_CNT - 1); 1276 ifq_set_ready(&ifp->if_snd); 1277 #ifdef DEVICE_POLLING 1278 ifp->if_poll = sis_poll; 1279 #endif 1280 ifp->if_capenable = ifp->if_capabilities; 1281 1282 /* 1283 * Do MII setup. 1284 */ 1285 if (mii_phy_probe(dev, &sc->sis_miibus, 1286 sis_ifmedia_upd, sis_ifmedia_sts)) { 1287 device_printf(dev, "MII without any PHY!\n"); 1288 error = ENXIO; 1289 goto fail; 1290 } 1291 1292 /* 1293 * Call MI attach routine. 1294 */ 1295 ether_ifattach(ifp, eaddr, NULL); 1296 1297 /* 1298 * Tell the upper layer(s) we support long frames. 1299 */ 1300 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1301 1302 error = bus_setup_intr(dev, sc->sis_irq, INTR_NETSAFE, 1303 sis_intr, sc, 1304 &sc->sis_intrhand, 1305 ifp->if_serializer); 1306 1307 if (error) { 1308 device_printf(dev, "couldn't set up irq\n"); 1309 ether_ifdetach(ifp); 1310 goto fail; 1311 } 1312 1313 fail: 1314 if (error) 1315 sis_detach(dev); 1316 1317 return(error); 1318 } 1319 1320 /* 1321 * Shutdown hardware and free up resources. It is called in both the error case 1322 * and the normal detach case so it needs to be careful about only freeing 1323 * resources that have actually been allocated. 1324 */ 1325 static int 1326 sis_detach(device_t dev) 1327 { 1328 struct sis_softc *sc = device_get_softc(dev); 1329 struct ifnet *ifp = &sc->arpcom.ac_if; 1330 1331 1332 if (device_is_attached(dev)) { 1333 lwkt_serialize_enter(ifp->if_serializer); 1334 sis_reset(sc); 1335 sis_stop(sc); 1336 bus_teardown_intr(dev, sc->sis_irq, sc->sis_intrhand); 1337 lwkt_serialize_exit(ifp->if_serializer); 1338 1339 ether_ifdetach(ifp); 1340 } 1341 if (sc->sis_miibus) 1342 device_delete_child(dev, sc->sis_miibus); 1343 bus_generic_detach(dev); 1344 1345 if (sc->sis_irq) 1346 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sis_irq); 1347 if (sc->sis_res) 1348 bus_release_resource(dev, SIS_RES, SIS_RID, sc->sis_res); 1349 1350 if (sc->sis_ldata.sis_rx_tag) { 1351 bus_dmamap_unload(sc->sis_ldata.sis_rx_tag, 1352 sc->sis_ldata.sis_rx_dmamap); 1353 bus_dmamem_free(sc->sis_ldata.sis_rx_tag, 1354 sc->sis_ldata.sis_rx_list, 1355 sc->sis_ldata.sis_rx_dmamap); 1356 bus_dma_tag_destroy(sc->sis_ldata.sis_rx_tag); 1357 } 1358 1359 if (sc->sis_ldata.sis_tx_tag) { 1360 bus_dmamap_unload(sc->sis_ldata.sis_tx_tag, 1361 sc->sis_ldata.sis_tx_dmamap); 1362 bus_dmamem_free(sc->sis_ldata.sis_tx_tag, 1363 sc->sis_ldata.sis_tx_list, 1364 sc->sis_ldata.sis_tx_dmamap); 1365 bus_dma_tag_destroy(sc->sis_ldata.sis_tx_tag); 1366 } 1367 if (sc->sis_tag) 1368 bus_dma_tag_destroy(sc->sis_tag); 1369 if (sc->sis_parent_tag) 1370 bus_dma_tag_destroy(sc->sis_parent_tag); 1371 1372 return(0); 1373 } 1374 1375 /* 1376 * Initialize the transmit descriptors. 1377 */ 1378 static int 1379 sis_list_tx_init(struct sis_softc *sc) 1380 { 1381 struct sis_list_data *ld; 1382 struct sis_ring_data *cd; 1383 int i, nexti; 1384 1385 cd = &sc->sis_cdata; 1386 ld = &sc->sis_ldata; 1387 1388 for (i = 0; i < SIS_TX_LIST_CNT; i++) { 1389 nexti = (i == (SIS_TX_LIST_CNT - 1)) ? 0 : i+1; 1390 ld->sis_tx_list[i].sis_nextdesc = 1391 &ld->sis_tx_list[nexti]; 1392 bus_dmamap_load(sc->sis_ldata.sis_tx_tag, 1393 sc->sis_ldata.sis_tx_dmamap, 1394 &ld->sis_tx_list[nexti], 1395 sizeof(struct sis_desc), sis_dma_map_desc_next, 1396 &ld->sis_tx_list[i], 0); 1397 ld->sis_tx_list[i].sis_mbuf = NULL; 1398 ld->sis_tx_list[i].sis_ptr = 0; 1399 ld->sis_tx_list[i].sis_ctl = 0; 1400 } 1401 1402 cd->sis_tx_prod = cd->sis_tx_cons = cd->sis_tx_cnt = 0; 1403 1404 bus_dmamap_sync(sc->sis_ldata.sis_tx_tag, sc->sis_ldata.sis_tx_dmamap, 1405 BUS_DMASYNC_PREWRITE); 1406 1407 return(0); 1408 } 1409 1410 /* 1411 * Initialize the RX descriptors and allocate mbufs for them. Note that 1412 * we arrange the descriptors in a closed ring, so that the last descriptor 1413 * points back to the first. 1414 */ 1415 static int 1416 sis_list_rx_init(struct sis_softc *sc) 1417 { 1418 struct sis_list_data *ld; 1419 struct sis_ring_data *cd; 1420 int i, nexti; 1421 1422 ld = &sc->sis_ldata; 1423 cd = &sc->sis_cdata; 1424 1425 for (i = 0; i < SIS_RX_LIST_CNT; i++) { 1426 if (sis_newbuf(sc, &ld->sis_rx_list[i], NULL) == ENOBUFS) 1427 return(ENOBUFS); 1428 nexti = (i == (SIS_RX_LIST_CNT - 1)) ? 0 : i+1; 1429 ld->sis_rx_list[i].sis_nextdesc = 1430 &ld->sis_rx_list[nexti]; 1431 bus_dmamap_load(sc->sis_ldata.sis_rx_tag, 1432 sc->sis_ldata.sis_rx_dmamap, 1433 &ld->sis_rx_list[nexti], 1434 sizeof(struct sis_desc), sis_dma_map_desc_next, 1435 &ld->sis_rx_list[i], 0); 1436 } 1437 1438 bus_dmamap_sync(sc->sis_ldata.sis_rx_tag, sc->sis_ldata.sis_rx_dmamap, 1439 BUS_DMASYNC_PREWRITE); 1440 1441 cd->sis_rx_prod = 0; 1442 1443 return(0); 1444 } 1445 1446 /* 1447 * Initialize an RX descriptor and attach an MBUF cluster. 1448 */ 1449 static int 1450 sis_newbuf(struct sis_softc *sc, struct sis_desc *c, struct mbuf *m) 1451 { 1452 if (m == NULL) { 1453 m = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR); 1454 if (m == NULL) 1455 return(ENOBUFS); 1456 } else { 1457 m->m_data = m->m_ext.ext_buf; 1458 } 1459 1460 c->sis_mbuf = m; 1461 c->sis_ctl = SIS_RXLEN; 1462 1463 bus_dmamap_create(sc->sis_tag, 0, &c->sis_map); 1464 bus_dmamap_load(sc->sis_tag, c->sis_map, mtod(m, void *), MCLBYTES, 1465 sis_dma_map_desc_ptr, c, 0); 1466 bus_dmamap_sync(sc->sis_tag, c->sis_map, BUS_DMASYNC_PREWRITE); 1467 1468 return(0); 1469 } 1470 1471 /* 1472 * A frame has been uploaded: pass the resulting mbuf chain up to 1473 * the higher level protocols. 1474 */ 1475 static void 1476 sis_rxeof(struct sis_softc *sc) 1477 { 1478 struct mbuf *m; 1479 struct ifnet *ifp; 1480 struct sis_desc *cur_rx; 1481 int i, total_len = 0; 1482 uint32_t rxstat; 1483 1484 ifp = &sc->arpcom.ac_if; 1485 i = sc->sis_cdata.sis_rx_prod; 1486 1487 while(SIS_OWNDESC(&sc->sis_ldata.sis_rx_list[i])) { 1488 1489 #ifdef DEVICE_POLLING 1490 if (ifp->if_flags & IFF_POLLING) { 1491 if (sc->rxcycles <= 0) 1492 break; 1493 sc->rxcycles--; 1494 } 1495 #endif /* DEVICE_POLLING */ 1496 cur_rx = &sc->sis_ldata.sis_rx_list[i]; 1497 rxstat = cur_rx->sis_rxstat; 1498 bus_dmamap_sync(sc->sis_tag, cur_rx->sis_map, 1499 BUS_DMASYNC_POSTWRITE); 1500 bus_dmamap_unload(sc->sis_tag, cur_rx->sis_map); 1501 bus_dmamap_destroy(sc->sis_tag, cur_rx->sis_map); 1502 m = cur_rx->sis_mbuf; 1503 cur_rx->sis_mbuf = NULL; 1504 total_len = SIS_RXBYTES(cur_rx); 1505 SIS_INC(i, SIS_RX_LIST_CNT); 1506 1507 /* 1508 * If an error occurs, update stats, clear the 1509 * status word and leave the mbuf cluster in place: 1510 * it should simply get re-used next time this descriptor 1511 * comes up in the ring. 1512 */ 1513 if (!(rxstat & SIS_CMDSTS_PKT_OK)) { 1514 ifp->if_ierrors++; 1515 if (rxstat & SIS_RXSTAT_COLL) 1516 ifp->if_collisions++; 1517 sis_newbuf(sc, cur_rx, m); 1518 continue; 1519 } 1520 1521 /* No errors; receive the packet. */ 1522 #ifdef __i386__ 1523 /* 1524 * On the x86 we do not have alignment problems, so try to 1525 * allocate a new buffer for the receive ring, and pass up 1526 * the one where the packet is already, saving the expensive 1527 * copy done in m_devget(). 1528 * If we are on an architecture with alignment problems, or 1529 * if the allocation fails, then use m_devget and leave the 1530 * existing buffer in the receive ring. 1531 */ 1532 if (sis_newbuf(sc, cur_rx, NULL) == 0) 1533 m->m_pkthdr.len = m->m_len = total_len; 1534 else 1535 #endif 1536 { 1537 struct mbuf *m0; 1538 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 1539 total_len + ETHER_ALIGN, 0, ifp, NULL); 1540 sis_newbuf(sc, cur_rx, m); 1541 if (m0 == NULL) { 1542 ifp->if_ierrors++; 1543 continue; 1544 } 1545 m_adj(m0, ETHER_ALIGN); 1546 m = m0; 1547 } 1548 1549 ifp->if_ipackets++; 1550 ifp->if_input(ifp, m); 1551 } 1552 1553 sc->sis_cdata.sis_rx_prod = i; 1554 } 1555 1556 static void 1557 sis_rxeoc(struct sis_softc *sc) 1558 { 1559 sis_rxeof(sc); 1560 sis_init(sc); 1561 } 1562 1563 /* 1564 * A frame was downloaded to the chip. It's safe for us to clean up 1565 * the list buffers. 1566 */ 1567 1568 static void 1569 sis_txeof(struct sis_softc *sc) 1570 { 1571 struct sis_desc *cur_tx; 1572 struct ifnet *ifp; 1573 uint32_t idx; 1574 1575 ifp = &sc->arpcom.ac_if; 1576 1577 /* 1578 * Go through our tx list and free mbufs for those 1579 * frames that have been transmitted. 1580 */ 1581 for (idx = sc->sis_cdata.sis_tx_cons; sc->sis_cdata.sis_tx_cnt > 0; 1582 sc->sis_cdata.sis_tx_cnt--, SIS_INC(idx, SIS_TX_LIST_CNT) ) { 1583 cur_tx = &sc->sis_ldata.sis_tx_list[idx]; 1584 1585 if (SIS_OWNDESC(cur_tx)) 1586 break; 1587 1588 if (cur_tx->sis_ctl & SIS_CMDSTS_MORE) 1589 continue; 1590 1591 if (!(cur_tx->sis_ctl & SIS_CMDSTS_PKT_OK)) { 1592 ifp->if_oerrors++; 1593 if (cur_tx->sis_txstat & SIS_TXSTAT_EXCESSCOLLS) 1594 ifp->if_collisions++; 1595 if (cur_tx->sis_txstat & SIS_TXSTAT_OUTOFWINCOLL) 1596 ifp->if_collisions++; 1597 } 1598 1599 ifp->if_collisions += 1600 (cur_tx->sis_txstat & SIS_TXSTAT_COLLCNT) >> 16; 1601 1602 ifp->if_opackets++; 1603 if (cur_tx->sis_mbuf != NULL) { 1604 m_freem(cur_tx->sis_mbuf); 1605 cur_tx->sis_mbuf = NULL; 1606 bus_dmamap_unload(sc->sis_tag, cur_tx->sis_map); 1607 bus_dmamap_destroy(sc->sis_tag, cur_tx->sis_map); 1608 } 1609 } 1610 1611 if (idx != sc->sis_cdata.sis_tx_cons) { 1612 /* we freed up some buffers */ 1613 sc->sis_cdata.sis_tx_cons = idx; 1614 ifp->if_flags &= ~IFF_OACTIVE; 1615 } 1616 1617 ifp->if_timer = (sc->sis_cdata.sis_tx_cnt == 0) ? 0 : 5; 1618 } 1619 1620 static void 1621 sis_tick(void *xsc) 1622 { 1623 struct sis_softc *sc = xsc; 1624 struct mii_data *mii; 1625 struct ifnet *ifp = &sc->arpcom.ac_if; 1626 1627 lwkt_serialize_enter(ifp->if_serializer); 1628 1629 mii = device_get_softc(sc->sis_miibus); 1630 mii_tick(mii); 1631 1632 if (!sc->sis_link) { 1633 mii_pollstat(mii); 1634 if (mii->mii_media_status & IFM_ACTIVE && 1635 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 1636 sc->sis_link++; 1637 if (!ifq_is_empty(&ifp->if_snd)) 1638 sis_start(ifp); 1639 } 1640 1641 callout_reset(&sc->sis_timer, hz, sis_tick, sc); 1642 lwkt_serialize_exit(ifp->if_serializer); 1643 } 1644 1645 #ifdef DEVICE_POLLING 1646 1647 static void 1648 sis_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1649 { 1650 struct sis_softc *sc = ifp->if_softc; 1651 1652 switch(cmd) { 1653 case POLL_REGISTER: 1654 /* disable interrupts */ 1655 CSR_WRITE_4(sc, SIS_IER, 0); 1656 break; 1657 case POLL_DEREGISTER: 1658 /* enable interrupts */ 1659 CSR_WRITE_4(sc, SIS_IER, 1); 1660 break; 1661 default: 1662 /* 1663 * On the sis, reading the status register also clears it. 1664 * So before returning to intr mode we must make sure that all 1665 * possible pending sources of interrupts have been served. 1666 * In practice this means run to completion the *eof routines, 1667 * and then call the interrupt routine 1668 */ 1669 sc->rxcycles = count; 1670 sis_rxeof(sc); 1671 sis_txeof(sc); 1672 if (!ifq_is_empty(&ifp->if_snd)) 1673 sis_start(ifp); 1674 1675 if (sc->rxcycles > 0 || cmd == POLL_AND_CHECK_STATUS) { 1676 uint32_t status; 1677 1678 /* Reading the ISR register clears all interrupts. */ 1679 status = CSR_READ_4(sc, SIS_ISR); 1680 1681 if (status & (SIS_ISR_RX_ERR|SIS_ISR_RX_OFLOW)) 1682 sis_rxeoc(sc); 1683 1684 if (status & (SIS_ISR_RX_IDLE)) 1685 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE); 1686 1687 if (status & SIS_ISR_SYSERR) { 1688 sis_reset(sc); 1689 sis_init(sc); 1690 } 1691 } 1692 break; 1693 } 1694 } 1695 #endif /* DEVICE_POLLING */ 1696 1697 static void 1698 sis_intr(void *arg) 1699 { 1700 struct sis_softc *sc; 1701 struct ifnet *ifp; 1702 uint32_t status; 1703 1704 sc = arg; 1705 ifp = &sc->arpcom.ac_if; 1706 1707 /* Supress unwanted interrupts */ 1708 if (!(ifp->if_flags & IFF_UP)) { 1709 sis_stop(sc); 1710 return; 1711 } 1712 1713 /* Disable interrupts. */ 1714 CSR_WRITE_4(sc, SIS_IER, 0); 1715 1716 for (;;) { 1717 /* Reading the ISR register clears all interrupts. */ 1718 status = CSR_READ_4(sc, SIS_ISR); 1719 1720 if ((status & SIS_INTRS) == 0) 1721 break; 1722 1723 if (status & 1724 (SIS_ISR_TX_DESC_OK | SIS_ISR_TX_ERR | SIS_ISR_TX_OK | 1725 SIS_ISR_TX_IDLE) ) 1726 sis_txeof(sc); 1727 1728 if (status & 1729 (SIS_ISR_RX_DESC_OK | SIS_ISR_RX_OK | SIS_ISR_RX_IDLE)) 1730 sis_rxeof(sc); 1731 1732 if (status & (SIS_ISR_RX_ERR | SIS_ISR_RX_OFLOW)) 1733 sis_rxeoc(sc); 1734 1735 if (status & (SIS_ISR_RX_IDLE)) 1736 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE); 1737 1738 if (status & SIS_ISR_SYSERR) { 1739 sis_reset(sc); 1740 sis_init(sc); 1741 } 1742 } 1743 1744 /* Re-enable interrupts. */ 1745 CSR_WRITE_4(sc, SIS_IER, 1); 1746 1747 if (!ifq_is_empty(&ifp->if_snd)) 1748 sis_start(ifp); 1749 } 1750 1751 /* 1752 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1753 * pointers to the fragment pointers. 1754 */ 1755 static int 1756 sis_encap(struct sis_softc *sc, struct mbuf *m_head, uint32_t *txidx) 1757 { 1758 struct sis_desc *f = NULL; 1759 struct mbuf *m; 1760 int frag, cur, cnt = 0; 1761 1762 /* 1763 * If there's no way we can send any packets, return now. 1764 */ 1765 if (SIS_TX_LIST_CNT - sc->sis_cdata.sis_tx_cnt < 2) 1766 return (ENOBUFS); 1767 1768 /* 1769 * Start packing the mbufs in this chain into 1770 * the fragment pointers. Stop when we run out 1771 * of fragments or hit the end of the mbuf chain. 1772 */ 1773 m = m_head; 1774 cur = frag = *txidx; 1775 1776 for (m = m_head; m != NULL; m = m->m_next) { 1777 if (m->m_len != 0) { 1778 if ((SIS_TX_LIST_CNT - 1779 (sc->sis_cdata.sis_tx_cnt + cnt)) < 2) 1780 return(ENOBUFS); 1781 f = &sc->sis_ldata.sis_tx_list[frag]; 1782 f->sis_ctl = SIS_CMDSTS_MORE | m->m_len; 1783 bus_dmamap_create(sc->sis_tag, 0, &f->sis_map); 1784 bus_dmamap_load(sc->sis_tag, f->sis_map, 1785 mtod(m, void *), m->m_len, 1786 sis_dma_map_desc_ptr, f, 0); 1787 bus_dmamap_sync(sc->sis_tag, f->sis_map, 1788 BUS_DMASYNC_PREREAD); 1789 if (cnt != 0) 1790 f->sis_ctl |= SIS_CMDSTS_OWN; 1791 cur = frag; 1792 SIS_INC(frag, SIS_TX_LIST_CNT); 1793 cnt++; 1794 } 1795 } 1796 1797 if (m != NULL) 1798 return(ENOBUFS); 1799 1800 sc->sis_ldata.sis_tx_list[cur].sis_mbuf = m_head; 1801 sc->sis_ldata.sis_tx_list[cur].sis_ctl &= ~SIS_CMDSTS_MORE; 1802 sc->sis_ldata.sis_tx_list[*txidx].sis_ctl |= SIS_CMDSTS_OWN; 1803 sc->sis_cdata.sis_tx_cnt += cnt; 1804 *txidx = frag; 1805 1806 return(0); 1807 } 1808 1809 /* 1810 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1811 * to the mbuf data regions directly in the transmit lists. We also save a 1812 * copy of the pointers since the transmit list fragment pointers are 1813 * physical addresses. 1814 */ 1815 1816 static void 1817 sis_start(struct ifnet *ifp) 1818 { 1819 struct sis_softc *sc; 1820 struct mbuf *m_head = NULL; 1821 uint32_t idx; 1822 int need_trans; 1823 1824 sc = ifp->if_softc; 1825 1826 if (!sc->sis_link) 1827 return; 1828 1829 idx = sc->sis_cdata.sis_tx_prod; 1830 1831 if (ifp->if_flags & IFF_OACTIVE) 1832 return; 1833 1834 need_trans = 0; 1835 while(sc->sis_ldata.sis_tx_list[idx].sis_mbuf == NULL) { 1836 m_head = ifq_poll(&ifp->if_snd); 1837 if (m_head == NULL) 1838 break; 1839 1840 if (sis_encap(sc, m_head, &idx)) { 1841 ifp->if_flags |= IFF_OACTIVE; 1842 break; 1843 } 1844 ifq_dequeue(&ifp->if_snd, m_head); 1845 need_trans = 1; 1846 1847 /* 1848 * If there's a BPF listener, bounce a copy of this frame 1849 * to him. 1850 */ 1851 BPF_MTAP(ifp, m_head); 1852 } 1853 1854 if (!need_trans) 1855 return; 1856 1857 /* Transmit */ 1858 sc->sis_cdata.sis_tx_prod = idx; 1859 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_ENABLE); 1860 1861 /* 1862 * Set a timeout in case the chip goes out to lunch. 1863 */ 1864 ifp->if_timer = 5; 1865 } 1866 1867 static void 1868 sis_init(void *xsc) 1869 { 1870 struct sis_softc *sc = xsc; 1871 struct ifnet *ifp = &sc->arpcom.ac_if; 1872 struct mii_data *mii; 1873 1874 /* 1875 * Cancel pending I/O and free all RX/TX buffers. 1876 */ 1877 sis_stop(sc); 1878 1879 mii = device_get_softc(sc->sis_miibus); 1880 1881 /* Set MAC address */ 1882 if (sc->sis_type == SIS_TYPE_83815) { 1883 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR0); 1884 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1885 ((uint16_t *)sc->arpcom.ac_enaddr)[0]); 1886 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR1); 1887 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1888 ((uint16_t *)sc->arpcom.ac_enaddr)[1]); 1889 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR2); 1890 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1891 ((uint16_t *)sc->arpcom.ac_enaddr)[2]); 1892 } else { 1893 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR0); 1894 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1895 ((uint16_t *)sc->arpcom.ac_enaddr)[0]); 1896 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR1); 1897 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1898 ((uint16_t *)sc->arpcom.ac_enaddr)[1]); 1899 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR2); 1900 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1901 ((uint16_t *)sc->arpcom.ac_enaddr)[2]); 1902 } 1903 1904 /* Init circular RX list. */ 1905 if (sis_list_rx_init(sc) == ENOBUFS) { 1906 if_printf(ifp, "initialization failed: " 1907 "no memory for rx buffers\n"); 1908 sis_stop(sc); 1909 return; 1910 } 1911 1912 /* 1913 * Init tx descriptors. 1914 */ 1915 sis_list_tx_init(sc); 1916 1917 /* 1918 * For the NatSemi chip, we have to explicitly enable the 1919 * reception of ARP frames, as well as turn on the 'perfect 1920 * match' filter where we store the station address, otherwise 1921 * we won't receive unicasts meant for this host. 1922 */ 1923 if (sc->sis_type == SIS_TYPE_83815) { 1924 SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_ARP); 1925 SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_PERFECT); 1926 } 1927 1928 /* If we want promiscuous mode, set the allframes bit. */ 1929 if (ifp->if_flags & IFF_PROMISC) 1930 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLPHYS); 1931 else 1932 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLPHYS); 1933 1934 /* 1935 * Set the capture broadcast bit to capture broadcast frames. 1936 */ 1937 if (ifp->if_flags & IFF_BROADCAST) 1938 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_BROAD); 1939 else 1940 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_BROAD); 1941 1942 /* 1943 * Load the multicast filter. 1944 */ 1945 if (sc->sis_type == SIS_TYPE_83815) 1946 sis_setmulti_ns(sc); 1947 else 1948 sis_setmulti_sis(sc); 1949 1950 /* Turn the receive filter on */ 1951 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ENABLE); 1952 1953 /* 1954 * Load the address of the RX and TX lists. 1955 */ 1956 CSR_WRITE_4(sc, SIS_RX_LISTPTR, sc->sis_cdata.sis_rx_paddr); 1957 CSR_WRITE_4(sc, SIS_TX_LISTPTR, sc->sis_cdata.sis_tx_paddr); 1958 1959 /* SIS_CFG_EDB_MASTER_EN indicates the EDB bus is used instead of 1960 * the PCI bus. When this bit is set, the Max DMA Burst Size 1961 * for TX/RX DMA should be no larger than 16 double words. 1962 */ 1963 if (CSR_READ_4(sc, SIS_CFG) & SIS_CFG_EDB_MASTER_EN) 1964 CSR_WRITE_4(sc, SIS_RX_CFG, SIS_RXCFG64); 1965 else 1966 CSR_WRITE_4(sc, SIS_RX_CFG, SIS_RXCFG256); 1967 1968 /* Accept Long Packets for VLAN support */ 1969 SIS_SETBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_JABBER); 1970 1971 /* Set TX configuration */ 1972 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T) 1973 CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_10); 1974 else 1975 CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_100); 1976 1977 /* Set full/half duplex mode. */ 1978 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 1979 SIS_SETBIT(sc, SIS_TX_CFG, 1980 (SIS_TXCFG_IGN_HBEAT|SIS_TXCFG_IGN_CARR)); 1981 SIS_SETBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS); 1982 } else { 1983 SIS_CLRBIT(sc, SIS_TX_CFG, 1984 (SIS_TXCFG_IGN_HBEAT|SIS_TXCFG_IGN_CARR)); 1985 SIS_CLRBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS); 1986 } 1987 1988 /* 1989 * Enable interrupts. 1990 */ 1991 CSR_WRITE_4(sc, SIS_IMR, SIS_INTRS); 1992 #ifdef DEVICE_POLLING 1993 /* 1994 * ... only enable interrupts if we are not polling, make sure 1995 * they are off otherwise. 1996 */ 1997 if (ifp->if_flags & IFF_POLLING) 1998 CSR_WRITE_4(sc, SIS_IER, 0); 1999 else 2000 #endif /* DEVICE_POLLING */ 2001 CSR_WRITE_4(sc, SIS_IER, 1); 2002 2003 /* Enable receiver and transmitter. */ 2004 SIS_CLRBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE|SIS_CSR_RX_DISABLE); 2005 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE); 2006 2007 #ifdef notdef 2008 mii_mediachg(mii); 2009 #endif 2010 2011 /* 2012 * Page 75 of the DP83815 manual recommends the 2013 * following register settings "for optimum 2014 * performance." Note however that at least three 2015 * of the registers are listed as "reserved" in 2016 * the register map, so who knows what they do. 2017 */ 2018 if (sc->sis_type == SIS_TYPE_83815) { 2019 CSR_WRITE_4(sc, NS_PHY_PAGE, 0x0001); 2020 CSR_WRITE_4(sc, NS_PHY_CR, 0x189C); 2021 CSR_WRITE_4(sc, NS_PHY_TDATA, 0x0000); 2022 CSR_WRITE_4(sc, NS_PHY_DSPCFG, 0x5040); 2023 CSR_WRITE_4(sc, NS_PHY_SDCFG, 0x008C); 2024 } 2025 2026 ifp->if_flags |= IFF_RUNNING; 2027 ifp->if_flags &= ~IFF_OACTIVE; 2028 2029 callout_reset(&sc->sis_timer, hz, sis_tick, sc); 2030 } 2031 2032 /* 2033 * Set media options. 2034 */ 2035 static int 2036 sis_ifmedia_upd(struct ifnet *ifp) 2037 { 2038 struct sis_softc *sc; 2039 struct mii_data *mii; 2040 2041 sc = ifp->if_softc; 2042 2043 mii = device_get_softc(sc->sis_miibus); 2044 sc->sis_link = 0; 2045 if (mii->mii_instance) { 2046 struct mii_softc *miisc; 2047 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 2048 mii_phy_reset(miisc); 2049 } 2050 mii_mediachg(mii); 2051 2052 return(0); 2053 } 2054 2055 /* 2056 * Report current media status. 2057 */ 2058 static void 2059 sis_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 2060 { 2061 struct sis_softc *sc; 2062 struct mii_data *mii; 2063 2064 sc = ifp->if_softc; 2065 2066 mii = device_get_softc(sc->sis_miibus); 2067 mii_pollstat(mii); 2068 ifmr->ifm_active = mii->mii_media_active; 2069 ifmr->ifm_status = mii->mii_media_status; 2070 } 2071 2072 static int 2073 sis_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr) 2074 { 2075 struct sis_softc *sc = ifp->if_softc; 2076 struct ifreq *ifr = (struct ifreq *) data; 2077 struct mii_data *mii; 2078 int error = 0; 2079 2080 switch(command) { 2081 case SIOCSIFFLAGS: 2082 if (ifp->if_flags & IFF_UP) { 2083 sis_init(sc); 2084 } else { 2085 if (ifp->if_flags & IFF_RUNNING) 2086 sis_stop(sc); 2087 } 2088 error = 0; 2089 break; 2090 case SIOCADDMULTI: 2091 case SIOCDELMULTI: 2092 if (sc->sis_type == SIS_TYPE_83815) 2093 sis_setmulti_ns(sc); 2094 else 2095 sis_setmulti_sis(sc); 2096 error = 0; 2097 break; 2098 case SIOCGIFMEDIA: 2099 case SIOCSIFMEDIA: 2100 mii = device_get_softc(sc->sis_miibus); 2101 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 2102 break; 2103 default: 2104 error = ether_ioctl(ifp, command, data); 2105 break; 2106 } 2107 return(error); 2108 } 2109 2110 static void 2111 sis_watchdog(struct ifnet *ifp) 2112 { 2113 struct sis_softc *sc; 2114 2115 sc = ifp->if_softc; 2116 2117 ifp->if_oerrors++; 2118 if_printf(ifp, "watchdog timeout\n"); 2119 2120 sis_stop(sc); 2121 sis_reset(sc); 2122 sis_init(sc); 2123 2124 if (!ifq_is_empty(&ifp->if_snd)) 2125 sis_start(ifp); 2126 } 2127 2128 /* 2129 * Stop the adapter and free any mbufs allocated to the 2130 * RX and TX lists. 2131 */ 2132 static void 2133 sis_stop(struct sis_softc *sc) 2134 { 2135 int i; 2136 struct ifnet *ifp; 2137 2138 ifp = &sc->arpcom.ac_if; 2139 ifp->if_timer = 0; 2140 2141 callout_stop(&sc->sis_timer); 2142 2143 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2144 CSR_WRITE_4(sc, SIS_IER, 0); 2145 CSR_WRITE_4(sc, SIS_IMR, 0); 2146 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE|SIS_CSR_RX_DISABLE); 2147 DELAY(1000); 2148 CSR_WRITE_4(sc, SIS_TX_LISTPTR, 0); 2149 CSR_WRITE_4(sc, SIS_RX_LISTPTR, 0); 2150 2151 sc->sis_link = 0; 2152 2153 /* 2154 * Free data in the RX lists. 2155 */ 2156 for (i = 0; i < SIS_RX_LIST_CNT; i++) { 2157 if (sc->sis_ldata.sis_rx_list[i].sis_mbuf != NULL) { 2158 bus_dmamap_unload(sc->sis_tag, 2159 sc->sis_ldata.sis_rx_list[i].sis_map); 2160 bus_dmamap_destroy(sc->sis_tag, 2161 sc->sis_ldata.sis_rx_list[i].sis_map); 2162 m_freem(sc->sis_ldata.sis_rx_list[i].sis_mbuf); 2163 sc->sis_ldata.sis_rx_list[i].sis_mbuf = NULL; 2164 } 2165 } 2166 bzero(sc->sis_ldata.sis_rx_list, sizeof(sc->sis_ldata.sis_rx_list)); 2167 2168 /* 2169 * Free the TX list buffers. 2170 */ 2171 for (i = 0; i < SIS_TX_LIST_CNT; i++) { 2172 if (sc->sis_ldata.sis_tx_list[i].sis_mbuf != NULL) { 2173 bus_dmamap_unload(sc->sis_tag, 2174 sc->sis_ldata.sis_tx_list[i].sis_map); 2175 bus_dmamap_destroy(sc->sis_tag, 2176 sc->sis_ldata.sis_tx_list[i].sis_map); 2177 m_freem(sc->sis_ldata.sis_tx_list[i].sis_mbuf); 2178 sc->sis_ldata.sis_tx_list[i].sis_mbuf = NULL; 2179 } 2180 } 2181 2182 bzero(sc->sis_ldata.sis_tx_list, sizeof(sc->sis_ldata.sis_tx_list)); 2183 } 2184 2185 /* 2186 * Stop all chip I/O so that the kernel's probe routines don't 2187 * get confused by errant DMAs when rebooting. 2188 */ 2189 static void 2190 sis_shutdown(device_t dev) 2191 { 2192 struct sis_softc *sc; 2193 struct ifnet *ifp; 2194 2195 sc = device_get_softc(dev); 2196 ifp = &sc->arpcom.ac_if; 2197 lwkt_serialize_enter(ifp->if_serializer); 2198 sis_reset(sc); 2199 sis_stop(sc); 2200 lwkt_serialize_exit(ifp->if_serializer); 2201 } 2202 2203