1 /* 2 * Copyright (c) 1997, 1998, 1999, 2000 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $OpenBSD: if_sk.c,v 1.33 2003/08/12 05:23:06 nate Exp $ 33 * $FreeBSD: src/sys/pci/if_sk.c,v 1.19.2.9 2003/03/05 18:42:34 njl Exp $ 34 * $DragonFly: src/sys/dev/netif/sk/if_sk.c,v 1.42 2005/12/31 14:08:00 sephe Exp $ 35 */ 36 37 /* 38 * Copyright (c) 2003 Nathan L. Binkert <binkertn@umich.edu> 39 * 40 * Permission to use, copy, modify, and distribute this software for any 41 * purpose with or without fee is hereby granted, provided that the above 42 * copyright notice and this permission notice appear in all copies. 43 * 44 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 45 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 46 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 47 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 48 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 49 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 50 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 51 */ 52 53 /* 54 * SysKonnect SK-NET gigabit ethernet driver for FreeBSD. Supports 55 * the SK-984x series adapters, both single port and dual port. 56 * References: 57 * The XaQti XMAC II datasheet, 58 * http://www.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 59 * The SysKonnect GEnesis manual, http://www.syskonnect.com 60 * 61 * Note: XaQti has been aquired by Vitesse, and Vitesse does not have the 62 * XMAC II datasheet online. I have put my copy at people.freebsd.org as a 63 * convenience to others until Vitesse corrects this problem: 64 * 65 * http://people.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 66 * 67 * Written by Bill Paul <wpaul@ee.columbia.edu> 68 * Department of Electrical Engineering 69 * Columbia University, New York City 70 */ 71 72 /* 73 * The SysKonnect gigabit ethernet adapters consist of two main 74 * components: the SysKonnect GEnesis controller chip and the XaQti Corp. 75 * XMAC II gigabit ethernet MAC. The XMAC provides all of the MAC 76 * components and a PHY while the GEnesis controller provides a PCI 77 * interface with DMA support. Each card may have between 512K and 78 * 2MB of SRAM on board depending on the configuration. 79 * 80 * The SysKonnect GEnesis controller can have either one or two XMAC 81 * chips connected to it, allowing single or dual port NIC configurations. 82 * SysKonnect has the distinction of being the only vendor on the market 83 * with a dual port gigabit ethernet NIC. The GEnesis provides dual FIFOs, 84 * dual DMA queues, packet/MAC/transmit arbiters and direct access to the 85 * XMAC registers. This driver takes advantage of these features to allow 86 * both XMACs to operate as independent interfaces. 87 */ 88 89 #include <sys/param.h> 90 #include <sys/systm.h> 91 #include <sys/sockio.h> 92 #include <sys/mbuf.h> 93 #include <sys/malloc.h> 94 #include <sys/kernel.h> 95 #include <sys/socket.h> 96 #include <sys/queue.h> 97 #include <sys/serialize.h> 98 #include <sys/thread2.h> 99 100 #include <net/if.h> 101 #include <net/ifq_var.h> 102 #include <net/if_arp.h> 103 #include <net/ethernet.h> 104 #include <net/if_dl.h> 105 #include <net/if_media.h> 106 107 #include <net/bpf.h> 108 109 #include <vm/vm.h> /* for vtophys */ 110 #include <vm/pmap.h> /* for vtophys */ 111 #include <machine/bus.h> 112 #include <machine/resource.h> 113 #include <sys/bus.h> 114 #include <sys/rman.h> 115 116 #include <dev/netif/mii_layer/mii.h> 117 #include <dev/netif/mii_layer/miivar.h> 118 #include <dev/netif/mii_layer/brgphyreg.h> 119 120 #include <bus/pci/pcireg.h> 121 #include <bus/pci/pcivar.h> 122 123 #if 0 124 #define SK_USEIOSPACE 125 #endif 126 127 #include "if_skreg.h" 128 #include "xmaciireg.h" 129 #include "yukonreg.h" 130 131 /* "controller miibus0" required. See GENERIC if you get errors here. */ 132 #include "miibus_if.h" 133 134 static struct sk_type sk_devs[] = { 135 { VENDORID_SK, DEVICEID_SK_V1, 136 "SysKonnect Gigabit Ethernet (V1.0)" }, 137 { VENDORID_SK, DEVICEID_SK_V2, 138 "SysKonnect Gigabit Ethernet (V2.0)" }, 139 { VENDORID_MARVELL, DEVICEID_SK_V2, 140 "Marvell Gigabit Ethernet" }, 141 { VENDORID_3COM, DEVICEID_3COM_3C940, 142 "3Com 3C940 Gigabit Ethernet" }, 143 { VENDORID_LINKSYS, DEVICEID_LINKSYS_EG1032, 144 "Linksys EG1032 Gigabit Ethernet" }, 145 { VENDORID_DLINK, DEVICEID_DLINK_DGE530T, 146 "D-Link DGE-530T Gigabit Ethernet" }, 147 { 0, 0, NULL } 148 }; 149 150 static int skc_probe(device_t); 151 static int skc_attach(device_t); 152 static int skc_detach(device_t); 153 static void skc_shutdown(device_t); 154 static int sk_probe(device_t); 155 static int sk_attach(device_t); 156 static int sk_detach(device_t); 157 static void sk_tick(void *); 158 static void sk_intr(void *); 159 static void sk_intr_bcom(struct sk_if_softc *); 160 static void sk_intr_xmac(struct sk_if_softc *); 161 static void sk_intr_yukon(struct sk_if_softc *); 162 static void sk_rxeof(struct sk_if_softc *); 163 static void sk_txeof(struct sk_if_softc *); 164 static int sk_encap(struct sk_if_softc *, struct mbuf *, uint32_t *); 165 static void sk_start(struct ifnet *); 166 static int sk_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *); 167 static void sk_init(void *); 168 static void sk_init_xmac(struct sk_if_softc *); 169 static void sk_init_yukon(struct sk_if_softc *); 170 static void sk_stop(struct sk_if_softc *); 171 static void sk_watchdog(struct ifnet *); 172 static int sk_ifmedia_upd(struct ifnet *); 173 static void sk_ifmedia_sts(struct ifnet *, struct ifmediareq *); 174 static void sk_reset(struct sk_softc *); 175 static int sk_newbuf(struct sk_if_softc *, struct sk_chain *, 176 struct mbuf *); 177 static int sk_alloc_jumbo_mem(struct sk_if_softc *); 178 static struct sk_jslot 179 *sk_jalloc(struct sk_if_softc *); 180 static void sk_jfree(void *); 181 static void sk_jref(void *); 182 static int sk_init_rx_ring(struct sk_if_softc *); 183 static void sk_init_tx_ring(struct sk_if_softc *); 184 static uint32_t sk_win_read_4(struct sk_softc *, int); 185 static uint16_t sk_win_read_2(struct sk_softc *, int); 186 static uint8_t sk_win_read_1(struct sk_softc *, int); 187 static void sk_win_write_4(struct sk_softc *, int, uint32_t); 188 static void sk_win_write_2(struct sk_softc *, int, uint32_t); 189 static void sk_win_write_1(struct sk_softc *, int, uint32_t); 190 static uint8_t sk_vpd_readbyte(struct sk_softc *, int); 191 static void sk_vpd_read_res(struct sk_softc *, struct vpd_res *, int); 192 static void sk_vpd_read(struct sk_softc *); 193 194 static int sk_miibus_readreg(device_t, int, int); 195 static int sk_miibus_writereg(device_t, int, int, int); 196 static void sk_miibus_statchg(device_t); 197 198 static int sk_xmac_miibus_readreg(struct sk_if_softc *, int, int); 199 static int sk_xmac_miibus_writereg(struct sk_if_softc *, int, int, int); 200 static void sk_xmac_miibus_statchg(struct sk_if_softc *); 201 202 static int sk_marv_miibus_readreg(struct sk_if_softc *, int, int); 203 static int sk_marv_miibus_writereg(struct sk_if_softc *, int, int, int); 204 static void sk_marv_miibus_statchg(struct sk_if_softc *); 205 206 static void sk_setfilt(struct sk_if_softc *, caddr_t, int); 207 static void sk_setmulti(struct sk_if_softc *); 208 static void sk_setpromisc(struct sk_if_softc *); 209 210 #ifdef SK_USEIOSPACE 211 #define SK_RES SYS_RES_IOPORT 212 #define SK_RID SK_PCI_LOIO 213 #else 214 #define SK_RES SYS_RES_MEMORY 215 #define SK_RID SK_PCI_LOMEM 216 #endif 217 218 /* 219 * Note that we have newbus methods for both the GEnesis controller 220 * itself and the XMAC(s). The XMACs are children of the GEnesis, and 221 * the miibus code is a child of the XMACs. We need to do it this way 222 * so that the miibus drivers can access the PHY registers on the 223 * right PHY. It's not quite what I had in mind, but it's the only 224 * design that achieves the desired effect. 225 */ 226 static device_method_t skc_methods[] = { 227 /* Device interface */ 228 DEVMETHOD(device_probe, skc_probe), 229 DEVMETHOD(device_attach, skc_attach), 230 DEVMETHOD(device_detach, skc_detach), 231 DEVMETHOD(device_shutdown, skc_shutdown), 232 233 /* bus interface */ 234 DEVMETHOD(bus_print_child, bus_generic_print_child), 235 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 236 237 { 0, 0 } 238 }; 239 240 static DEFINE_CLASS_0(skc, skc_driver, skc_methods, sizeof(struct sk_softc)); 241 static devclass_t skc_devclass; 242 243 static device_method_t sk_methods[] = { 244 /* Device interface */ 245 DEVMETHOD(device_probe, sk_probe), 246 DEVMETHOD(device_attach, sk_attach), 247 DEVMETHOD(device_detach, sk_detach), 248 DEVMETHOD(device_shutdown, bus_generic_shutdown), 249 250 /* bus interface */ 251 DEVMETHOD(bus_print_child, bus_generic_print_child), 252 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 253 254 /* MII interface */ 255 DEVMETHOD(miibus_readreg, sk_miibus_readreg), 256 DEVMETHOD(miibus_writereg, sk_miibus_writereg), 257 DEVMETHOD(miibus_statchg, sk_miibus_statchg), 258 259 { 0, 0 } 260 }; 261 262 static DEFINE_CLASS_0(sk, sk_driver, sk_methods, sizeof(struct sk_if_softc)); 263 static devclass_t sk_devclass; 264 static struct lwkt_serialize sk_serializer; 265 266 DECLARE_DUMMY_MODULE(if_sk); 267 DRIVER_MODULE(if_sk, pci, skc_driver, skc_devclass, 0, 0); 268 DRIVER_MODULE(if_sk, skc, sk_driver, sk_devclass, 0, 0); 269 DRIVER_MODULE(miibus, sk, miibus_driver, miibus_devclass, 0, 0); 270 271 #define SK_SETBIT(sc, reg, x) \ 272 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | x) 273 274 #define SK_CLRBIT(sc, reg, x) \ 275 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~x) 276 277 #define SK_WIN_SETBIT_4(sc, reg, x) \ 278 sk_win_write_4(sc, reg, sk_win_read_4(sc, reg) | x) 279 280 #define SK_WIN_CLRBIT_4(sc, reg, x) \ 281 sk_win_write_4(sc, reg, sk_win_read_4(sc, reg) & ~x) 282 283 #define SK_WIN_SETBIT_2(sc, reg, x) \ 284 sk_win_write_2(sc, reg, sk_win_read_2(sc, reg) | x) 285 286 #define SK_WIN_CLRBIT_2(sc, reg, x) \ 287 sk_win_write_2(sc, reg, sk_win_read_2(sc, reg) & ~x) 288 289 static uint32_t 290 sk_win_read_4(struct sk_softc *sc, int reg) 291 { 292 #ifdef SK_USEIOSPACE 293 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 294 return(CSR_READ_4(sc, SK_WIN_BASE + SK_REG(reg))); 295 #else 296 return(CSR_READ_4(sc, reg)); 297 #endif 298 } 299 300 static uint16_t 301 sk_win_read_2(struct sk_softc *sc, int reg) 302 { 303 #ifdef SK_USEIOSPACE 304 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 305 return(CSR_READ_2(sc, SK_WIN_BASE + SK_REG(reg))); 306 #else 307 return(CSR_READ_2(sc, reg)); 308 #endif 309 } 310 311 static uint8_t 312 sk_win_read_1(struct sk_softc *sc, int reg) 313 { 314 #ifdef SK_USEIOSPACE 315 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 316 return(CSR_READ_1(sc, SK_WIN_BASE + SK_REG(reg))); 317 #else 318 return(CSR_READ_1(sc, reg)); 319 #endif 320 } 321 322 static void 323 sk_win_write_4(struct sk_softc *sc, int reg, uint32_t val) 324 { 325 #ifdef SK_USEIOSPACE 326 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 327 CSR_WRITE_4(sc, SK_WIN_BASE + SK_REG(reg), val); 328 #else 329 CSR_WRITE_4(sc, reg, val); 330 #endif 331 } 332 333 static void 334 sk_win_write_2(struct sk_softc *sc, int reg, uint32_t val) 335 { 336 #ifdef SK_USEIOSPACE 337 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 338 CSR_WRITE_2(sc, SK_WIN_BASE + SK_REG(reg), val); 339 #else 340 CSR_WRITE_2(sc, reg, val); 341 #endif 342 } 343 344 static void 345 sk_win_write_1(struct sk_softc *sc, int reg, uint32_t val) 346 { 347 #ifdef SK_USEIOSPACE 348 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 349 CSR_WRITE_1(sc, SK_WIN_BASE + SK_REG(reg), val); 350 #else 351 CSR_WRITE_1(sc, reg, val); 352 #endif 353 } 354 355 /* 356 * The VPD EEPROM contains Vital Product Data, as suggested in 357 * the PCI 2.1 specification. The VPD data is separared into areas 358 * denoted by resource IDs. The SysKonnect VPD contains an ID string 359 * resource (the name of the adapter), a read-only area resource 360 * containing various key/data fields and a read/write area which 361 * can be used to store asset management information or log messages. 362 * We read the ID string and read-only into buffers attached to 363 * the controller softc structure for later use. At the moment, 364 * we only use the ID string during sk_attach(). 365 */ 366 static uint8_t 367 sk_vpd_readbyte(struct sk_softc *sc, int addr) 368 { 369 int i; 370 371 sk_win_write_2(sc, SK_PCI_REG(SK_PCI_VPD_ADDR), addr); 372 for (i = 0; i < SK_TIMEOUT; i++) { 373 DELAY(1); 374 if (sk_win_read_2(sc, 375 SK_PCI_REG(SK_PCI_VPD_ADDR)) & SK_VPD_FLAG) 376 break; 377 } 378 379 if (i == SK_TIMEOUT) 380 return(0); 381 382 return(sk_win_read_1(sc, SK_PCI_REG(SK_PCI_VPD_DATA))); 383 } 384 385 static void 386 sk_vpd_read_res(struct sk_softc *sc, struct vpd_res *res, int addr) 387 { 388 int i; 389 uint8_t *ptr; 390 391 ptr = (uint8_t *)res; 392 for (i = 0; i < sizeof(struct vpd_res); i++) 393 ptr[i] = sk_vpd_readbyte(sc, i + addr); 394 } 395 396 static void 397 sk_vpd_read(struct sk_softc *sc) 398 { 399 struct vpd_res res; 400 int i, pos = 0; 401 402 if (sc->sk_vpd_prodname != NULL) 403 free(sc->sk_vpd_prodname, M_DEVBUF); 404 if (sc->sk_vpd_readonly != NULL) 405 free(sc->sk_vpd_readonly, M_DEVBUF); 406 sc->sk_vpd_prodname = NULL; 407 sc->sk_vpd_readonly = NULL; 408 409 sk_vpd_read_res(sc, &res, pos); 410 411 if (res.vr_id != VPD_RES_ID) { 412 printf("skc%d: bad VPD resource id: expected %x got %x\n", 413 sc->sk_unit, VPD_RES_ID, res.vr_id); 414 return; 415 } 416 417 pos += sizeof(res); 418 sc->sk_vpd_prodname = malloc(res.vr_len + 1, M_DEVBUF, M_INTWAIT); 419 for (i = 0; i < res.vr_len; i++) 420 sc->sk_vpd_prodname[i] = sk_vpd_readbyte(sc, i + pos); 421 sc->sk_vpd_prodname[i] = '\0'; 422 pos += i; 423 424 sk_vpd_read_res(sc, &res, pos); 425 426 if (res.vr_id != VPD_RES_READ) { 427 printf("skc%d: bad VPD resource id: expected %x got %x\n", 428 sc->sk_unit, VPD_RES_READ, res.vr_id); 429 return; 430 } 431 432 pos += sizeof(res); 433 sc->sk_vpd_readonly = malloc(res.vr_len, M_DEVBUF, M_INTWAIT); 434 for (i = 0; i < res.vr_len + 1; i++) 435 sc->sk_vpd_readonly[i] = sk_vpd_readbyte(sc, i + pos); 436 } 437 438 static int 439 sk_miibus_readreg(device_t dev, int phy, int reg) 440 { 441 struct sk_if_softc *sc_if = device_get_softc(dev); 442 443 switch(sc_if->sk_softc->sk_type) { 444 case SK_GENESIS: 445 return(sk_xmac_miibus_readreg(sc_if, phy, reg)); 446 case SK_YUKON: 447 return(sk_marv_miibus_readreg(sc_if, phy, reg)); 448 } 449 450 return(0); 451 } 452 453 static int 454 sk_miibus_writereg(device_t dev, int phy, int reg, int val) 455 { 456 struct sk_if_softc *sc_if = device_get_softc(dev); 457 458 switch(sc_if->sk_softc->sk_type) { 459 case SK_GENESIS: 460 return(sk_xmac_miibus_writereg(sc_if, phy, reg, val)); 461 case SK_YUKON: 462 return(sk_marv_miibus_writereg(sc_if, phy, reg, val)); 463 } 464 465 return(0); 466 } 467 468 static void 469 sk_miibus_statchg(device_t dev) 470 { 471 struct sk_if_softc *sc_if = device_get_softc(dev); 472 473 switch(sc_if->sk_softc->sk_type) { 474 case SK_GENESIS: 475 sk_xmac_miibus_statchg(sc_if); 476 break; 477 case SK_YUKON: 478 sk_marv_miibus_statchg(sc_if); 479 break; 480 } 481 } 482 483 static int 484 sk_xmac_miibus_readreg(struct sk_if_softc *sc_if, int phy, int reg) 485 { 486 int i; 487 488 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC && phy != 0) 489 return(0); 490 491 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8)); 492 SK_XM_READ_2(sc_if, XM_PHY_DATA); 493 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) { 494 for (i = 0; i < SK_TIMEOUT; i++) { 495 DELAY(1); 496 if (SK_XM_READ_2(sc_if, XM_MMUCMD) & 497 XM_MMUCMD_PHYDATARDY) 498 break; 499 } 500 501 if (i == SK_TIMEOUT) { 502 printf("sk%d: phy failed to come ready\n", 503 sc_if->sk_unit); 504 return(0); 505 } 506 } 507 DELAY(1); 508 return(SK_XM_READ_2(sc_if, XM_PHY_DATA)); 509 } 510 511 static int 512 sk_xmac_miibus_writereg(struct sk_if_softc *sc_if, int phy, int reg, int val) 513 { 514 int i; 515 516 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8)); 517 for (i = 0; i < SK_TIMEOUT; i++) { 518 if ((SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY) == 0) 519 break; 520 } 521 522 if (i == SK_TIMEOUT) { 523 printf("sk%d: phy failed to come ready\n", sc_if->sk_unit); 524 return(ETIMEDOUT); 525 } 526 527 SK_XM_WRITE_2(sc_if, XM_PHY_DATA, val); 528 for (i = 0; i < SK_TIMEOUT; i++) { 529 DELAY(1); 530 if ((SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY) == 0) 531 break; 532 } 533 534 if (i == SK_TIMEOUT) 535 printf("sk%d: phy write timed out\n", sc_if->sk_unit); 536 537 return(0); 538 } 539 540 static void 541 sk_xmac_miibus_statchg(struct sk_if_softc *sc_if) 542 { 543 struct mii_data *mii; 544 545 mii = device_get_softc(sc_if->sk_miibus); 546 547 /* 548 * If this is a GMII PHY, manually set the XMAC's 549 * duplex mode accordingly. 550 */ 551 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) { 552 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) 553 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX); 554 else 555 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX); 556 } 557 } 558 559 static int 560 sk_marv_miibus_readreg(struct sk_if_softc *sc_if, int phy, int reg) 561 { 562 uint16_t val; 563 int i; 564 565 if (phy != 0 || 566 (sc_if->sk_phytype != SK_PHYTYPE_MARV_COPPER && 567 sc_if->sk_phytype != SK_PHYTYPE_MARV_FIBER)) { 568 return(0); 569 } 570 571 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 572 YU_SMICR_REGAD(reg) | YU_SMICR_OP_READ); 573 574 for (i = 0; i < SK_TIMEOUT; i++) { 575 DELAY(1); 576 val = SK_YU_READ_2(sc_if, YUKON_SMICR); 577 if (val & YU_SMICR_READ_VALID) 578 break; 579 } 580 581 if (i == SK_TIMEOUT) { 582 printf("sk%d: phy failed to come ready\n", 583 sc_if->sk_unit); 584 return(0); 585 } 586 587 val = SK_YU_READ_2(sc_if, YUKON_SMIDR); 588 589 return(val); 590 } 591 592 static int 593 sk_marv_miibus_writereg(struct sk_if_softc *sc_if, int phy, int reg, int val) 594 { 595 int i; 596 597 SK_YU_WRITE_2(sc_if, YUKON_SMIDR, val); 598 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 599 YU_SMICR_REGAD(reg) | YU_SMICR_OP_WRITE); 600 601 for (i = 0; i < SK_TIMEOUT; i++) { 602 DELAY(1); 603 if (SK_YU_READ_2(sc_if, YUKON_SMICR) & YU_SMICR_BUSY) 604 break; 605 } 606 607 return(0); 608 } 609 610 static void 611 sk_marv_miibus_statchg(struct sk_if_softc *sc_if) 612 { 613 } 614 615 #define HASH_BITS 6 616 617 static void sk_setfilt(struct sk_if_softc *sc_if, caddr_t addr, int slot) 618 { 619 int base; 620 621 base = XM_RXFILT_ENTRY(slot); 622 623 SK_XM_WRITE_2(sc_if, base, *(uint16_t *)(&addr[0])); 624 SK_XM_WRITE_2(sc_if, base + 2, *(uint16_t *)(&addr[2])); 625 SK_XM_WRITE_2(sc_if, base + 4, *(uint16_t *)(&addr[4])); 626 } 627 628 static void 629 sk_setmulti(struct sk_if_softc *sc_if) 630 { 631 struct sk_softc *sc = sc_if->sk_softc; 632 struct ifnet *ifp = &sc_if->arpcom.ac_if; 633 uint32_t hashes[2] = { 0, 0 }; 634 int h, i; 635 struct ifmultiaddr *ifma; 636 uint8_t dummy[] = { 0, 0, 0, 0, 0 ,0 }; 637 638 /* First, zot all the existing filters. */ 639 switch(sc->sk_type) { 640 case SK_GENESIS: 641 for (i = 1; i < XM_RXFILT_MAX; i++) 642 sk_setfilt(sc_if, (caddr_t)&dummy, i); 643 644 SK_XM_WRITE_4(sc_if, XM_MAR0, 0); 645 SK_XM_WRITE_4(sc_if, XM_MAR2, 0); 646 break; 647 case SK_YUKON: 648 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, 0); 649 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, 0); 650 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, 0); 651 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, 0); 652 break; 653 } 654 655 /* Now program new ones. */ 656 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 657 hashes[0] = 0xFFFFFFFF; 658 hashes[1] = 0xFFFFFFFF; 659 } else { 660 i = 1; 661 /* First find the tail of the list. */ 662 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 663 if (ifma->ifma_link.le_next == NULL) 664 break; 665 } 666 /* Now traverse the list backwards. */ 667 for (; ifma != NULL && ifma != (void *)&ifp->if_multiaddrs; 668 ifma = (struct ifmultiaddr *)ifma->ifma_link.le_prev) { 669 if (ifma->ifma_addr->sa_family != AF_LINK) 670 continue; 671 /* 672 * Program the first XM_RXFILT_MAX multicast groups 673 * into the perfect filter. For all others, 674 * use the hash table. 675 */ 676 if (sc->sk_type == SK_GENESIS && i < XM_RXFILT_MAX) { 677 sk_setfilt(sc_if, 678 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), i); 679 i++; 680 continue; 681 } 682 683 switch(sc->sk_type) { 684 case SK_GENESIS: 685 h = ~ether_crc32_le(LLADDR((struct sockaddr_dl *) 686 ifma->ifma_addr), ETHER_ADDR_LEN) & 687 ((1 << HASH_BITS) -1 ); 688 if (h < 32) 689 hashes[0] |= (1 << h); 690 else 691 hashes[1] |= (1 << (h - 32)); 692 break; 693 694 case SK_YUKON: 695 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 696 ifma->ifma_addr), ETHER_ADDR_LEN) & 697 ((1 << HASH_BITS) -1 ); 698 if (h < 32) 699 hashes[0] |= (1 << h); 700 else 701 hashes[1] |= (1 << (h - 32)); 702 break; 703 } 704 } 705 } 706 707 switch(sc->sk_type) { 708 case SK_GENESIS: 709 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_HASH| 710 XM_MODE_RX_USE_PERFECT); 711 SK_XM_WRITE_4(sc_if, XM_MAR0, hashes[0]); 712 SK_XM_WRITE_4(sc_if, XM_MAR2, hashes[1]); 713 break; 714 case SK_YUKON: 715 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, hashes[0] & 0xffff); 716 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, (hashes[0] >> 16) & 0xffff); 717 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, hashes[1] & 0xffff); 718 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, (hashes[1] >> 16) & 0xffff); 719 break; 720 } 721 } 722 723 static void 724 sk_setpromisc(struct sk_if_softc *sc_if) 725 { 726 struct sk_softc *sc = sc_if->sk_softc; 727 struct ifnet *ifp = &sc_if->arpcom.ac_if; 728 729 switch(sc->sk_type) { 730 case SK_GENESIS: 731 if (ifp->if_flags & IFF_PROMISC) { 732 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 733 } else { 734 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 735 } 736 break; 737 case SK_YUKON: 738 if (ifp->if_flags & IFF_PROMISC) { 739 SK_YU_CLRBIT_2(sc_if, YUKON_RCR, 740 YU_RCR_UFLEN | YU_RCR_MUFLEN); 741 } else { 742 SK_YU_SETBIT_2(sc_if, YUKON_RCR, 743 YU_RCR_UFLEN | YU_RCR_MUFLEN); 744 } 745 break; 746 } 747 } 748 749 static int 750 sk_init_rx_ring(struct sk_if_softc *sc_if) 751 { 752 struct sk_chain_data *cd = &sc_if->sk_cdata; 753 struct sk_ring_data *rd = sc_if->sk_rdata; 754 int i; 755 756 bzero(rd->sk_rx_ring, sizeof(struct sk_rx_desc) * SK_RX_RING_CNT); 757 758 for (i = 0; i < SK_RX_RING_CNT; i++) { 759 cd->sk_rx_chain[i].sk_desc = &rd->sk_rx_ring[i]; 760 if (sk_newbuf(sc_if, &cd->sk_rx_chain[i], NULL) == ENOBUFS) 761 return(ENOBUFS); 762 if (i == (SK_RX_RING_CNT - 1)) { 763 cd->sk_rx_chain[i].sk_next = 764 &cd->sk_rx_chain[0]; 765 rd->sk_rx_ring[i].sk_next = 766 vtophys(&rd->sk_rx_ring[0]); 767 } else { 768 cd->sk_rx_chain[i].sk_next = 769 &cd->sk_rx_chain[i + 1]; 770 rd->sk_rx_ring[i].sk_next = 771 vtophys(&rd->sk_rx_ring[i + 1]); 772 } 773 } 774 775 sc_if->sk_cdata.sk_rx_prod = 0; 776 sc_if->sk_cdata.sk_rx_cons = 0; 777 778 return(0); 779 } 780 781 static void 782 sk_init_tx_ring(struct sk_if_softc *sc_if) 783 { 784 struct sk_chain_data *cd = &sc_if->sk_cdata; 785 struct sk_ring_data *rd = sc_if->sk_rdata; 786 int i, nexti; 787 788 bzero(sc_if->sk_rdata->sk_tx_ring, 789 sizeof(struct sk_tx_desc) * SK_TX_RING_CNT); 790 791 for (i = 0; i < SK_TX_RING_CNT; i++) { 792 nexti = (i == (SK_TX_RING_CNT - 1)) ? 0 : i + 1; 793 cd->sk_tx_chain[i].sk_desc = &rd->sk_tx_ring[i]; 794 cd->sk_tx_chain[i].sk_next = &cd->sk_tx_chain[nexti]; 795 rd->sk_tx_ring[i].sk_next = vtophys(&rd->sk_tx_ring[nexti]); 796 } 797 798 sc_if->sk_cdata.sk_tx_prod = 0; 799 sc_if->sk_cdata.sk_tx_cons = 0; 800 sc_if->sk_cdata.sk_tx_cnt = 0; 801 } 802 803 static int 804 sk_newbuf(struct sk_if_softc *sc_if, struct sk_chain *c, struct mbuf *m) 805 { 806 struct mbuf *m_new = NULL; 807 struct sk_rx_desc *r; 808 struct sk_jslot *buf; 809 810 if (m == NULL) { 811 MGETHDR(m_new, MB_DONTWAIT, MT_DATA); 812 if (m_new == NULL) 813 return(ENOBUFS); 814 815 /* Allocate the jumbo buffer */ 816 buf = sk_jalloc(sc_if); 817 if (buf == NULL) { 818 m_freem(m_new); 819 #ifdef SK_VERBOSE 820 printf("sk%d: jumbo allocation failed " 821 "-- packet dropped!\n", sc_if->sk_unit); 822 #endif 823 return(ENOBUFS); 824 } 825 826 /* Attach the buffer to the mbuf */ 827 m_new->m_ext.ext_arg = buf; 828 m_new->m_ext.ext_buf = buf->sk_buf; 829 m_new->m_ext.ext_free = sk_jfree; 830 m_new->m_ext.ext_ref = sk_jref; 831 m_new->m_ext.ext_size = SK_JUMBO_FRAMELEN; 832 833 m_new->m_data = m_new->m_ext.ext_buf; 834 m_new->m_flags |= M_EXT; 835 m_new->m_len = m_new->m_pkthdr.len = m_new->m_ext.ext_size; 836 } else { 837 /* 838 * We're re-using a previously allocated mbuf; 839 * be sure to re-init pointers and lengths to 840 * default values. 841 */ 842 m_new = m; 843 m_new->m_len = m_new->m_pkthdr.len = SK_JLEN; 844 m_new->m_data = m_new->m_ext.ext_buf; 845 } 846 847 /* 848 * Adjust alignment so packet payload begins on a 849 * longword boundary. Mandatory for Alpha, useful on 850 * x86 too. 851 */ 852 m_adj(m_new, ETHER_ALIGN); 853 854 r = c->sk_desc; 855 c->sk_mbuf = m_new; 856 r->sk_data_lo = vtophys(mtod(m_new, caddr_t)); 857 r->sk_ctl = m_new->m_len | SK_RXSTAT; 858 859 return(0); 860 } 861 862 /* 863 * Allocate jumbo buffer storage. The SysKonnect adapters support 864 * "jumbograms" (9K frames), although SysKonnect doesn't currently 865 * use them in their drivers. In order for us to use them, we need 866 * large 9K receive buffers, however standard mbuf clusters are only 867 * 2048 bytes in size. Consequently, we need to allocate and manage 868 * our own jumbo buffer pool. Fortunately, this does not require an 869 * excessive amount of additional code. 870 */ 871 static int 872 sk_alloc_jumbo_mem(struct sk_if_softc *sc_if) 873 { 874 caddr_t ptr; 875 int i; 876 struct sk_jslot *entry; 877 878 /* Grab a big chunk o' storage. */ 879 sc_if->sk_cdata.sk_jumbo_buf = contigmalloc(SK_JMEM, M_DEVBUF, 880 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 881 882 if (sc_if->sk_cdata.sk_jumbo_buf == NULL) { 883 printf("sk%d: no memory for jumbo buffers!\n", sc_if->sk_unit); 884 return(ENOBUFS); 885 } 886 887 SLIST_INIT(&sc_if->sk_jfree_listhead); 888 889 /* 890 * Now divide it up into 9K pieces and save the addresses 891 * in an array. Note that we play an evil trick here by using 892 * the first few bytes in the buffer to hold the the address 893 * of the softc structure for this interface. This is because 894 * sk_jfree() needs it, but it is called by the mbuf management 895 * code which will not pass it to us explicitly. 896 */ 897 ptr = sc_if->sk_cdata.sk_jumbo_buf; 898 for (i = 0; i < SK_JSLOTS; i++) { 899 entry = &sc_if->sk_cdata.sk_jslots[i]; 900 entry->sk_sc = sc_if; 901 entry->sk_buf = ptr; 902 entry->sk_inuse = 0; 903 entry->sk_slot = i; 904 SLIST_INSERT_HEAD(&sc_if->sk_jfree_listhead, entry, jslot_link); 905 ptr += SK_JLEN; 906 } 907 908 return(0); 909 } 910 911 /* 912 * Allocate a jumbo buffer. 913 */ 914 static struct sk_jslot * 915 sk_jalloc(struct sk_if_softc *sc_if) 916 { 917 struct sk_jslot *entry; 918 919 lwkt_serialize_enter(&sc_if->sk_jslot_serializer); 920 entry = SLIST_FIRST(&sc_if->sk_jfree_listhead); 921 if (entry) { 922 SLIST_REMOVE_HEAD(&sc_if->sk_jfree_listhead, jslot_link); 923 entry->sk_inuse = 1; 924 } else { 925 #ifdef SK_VERBOSE 926 printf("sk%d: no free jumbo buffers\n", sc_if->sk_unit); 927 #endif 928 } 929 lwkt_serialize_exit(&sc_if->sk_jslot_serializer); 930 return(entry); 931 } 932 933 /* 934 * Adjust usage count on a jumbo buffer. In general this doesn't 935 * get used much because our jumbo buffers don't get passed around 936 * a lot, but it's implemented for correctness. 937 */ 938 static void 939 sk_jref(void *arg) 940 { 941 struct sk_jslot *entry = (struct sk_jslot *)arg; 942 struct sk_if_softc *sc = entry->sk_sc; 943 944 if (sc == NULL) 945 panic("sk_jref: can't find softc pointer!"); 946 947 if (&sc->sk_cdata.sk_jslots[entry->sk_slot] != entry) 948 panic("sk_jref: asked to reference buffer " 949 "that we don't manage!"); 950 if (entry->sk_inuse == 0) 951 panic("sk_jref: buffer already free!"); 952 atomic_add_int(&entry->sk_inuse, 1); 953 } 954 955 /* 956 * Release a jumbo buffer. 957 */ 958 static void 959 sk_jfree(void *arg) 960 { 961 struct sk_jslot *entry = (struct sk_jslot *)arg; 962 struct sk_if_softc *sc = entry->sk_sc; 963 964 if (sc == NULL) 965 panic("sk_jref: can't find softc pointer!"); 966 967 if (&sc->sk_cdata.sk_jslots[entry->sk_slot] != entry) 968 panic("sk_jref: asked to reference buffer " 969 "that we don't manage!"); 970 if (entry->sk_inuse == 0) 971 panic("sk_jref: buffer already free!"); 972 lwkt_serialize_enter(&sc->sk_jslot_serializer); 973 atomic_subtract_int(&entry->sk_inuse, 1); 974 if (entry->sk_inuse == 0) 975 SLIST_INSERT_HEAD(&sc->sk_jfree_listhead, entry, jslot_link); 976 lwkt_serialize_exit(&sc->sk_jslot_serializer); 977 } 978 979 /* 980 * Set media options. 981 */ 982 static int 983 sk_ifmedia_upd(struct ifnet *ifp) 984 { 985 struct sk_if_softc *sc_if = ifp->if_softc; 986 struct mii_data *mii; 987 988 mii = device_get_softc(sc_if->sk_miibus); 989 sk_init(sc_if); 990 mii_mediachg(mii); 991 992 return(0); 993 } 994 995 /* 996 * Report current media status. 997 */ 998 static void 999 sk_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1000 { 1001 struct sk_if_softc *sc_if; 1002 struct mii_data *mii; 1003 1004 sc_if = ifp->if_softc; 1005 mii = device_get_softc(sc_if->sk_miibus); 1006 1007 mii_pollstat(mii); 1008 ifmr->ifm_active = mii->mii_media_active; 1009 ifmr->ifm_status = mii->mii_media_status; 1010 } 1011 1012 static int 1013 sk_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr) 1014 { 1015 struct sk_if_softc *sc_if = ifp->if_softc; 1016 struct ifreq *ifr = (struct ifreq *)data; 1017 struct mii_data *mii; 1018 int error = 0; 1019 1020 crit_enter(); 1021 1022 switch(command) { 1023 case SIOCSIFMTU: 1024 if (ifr->ifr_mtu > SK_JUMBO_MTU) 1025 error = EINVAL; 1026 else { 1027 ifp->if_mtu = ifr->ifr_mtu; 1028 sk_init(sc_if); 1029 } 1030 break; 1031 case SIOCSIFFLAGS: 1032 if (ifp->if_flags & IFF_UP) { 1033 if (ifp->if_flags & IFF_RUNNING) { 1034 if ((ifp->if_flags ^ sc_if->sk_if_flags) 1035 & IFF_PROMISC) { 1036 sk_setpromisc(sc_if); 1037 sk_setmulti(sc_if); 1038 } 1039 } else 1040 sk_init(sc_if); 1041 } else { 1042 if (ifp->if_flags & IFF_RUNNING) 1043 sk_stop(sc_if); 1044 } 1045 sc_if->sk_if_flags = ifp->if_flags; 1046 error = 0; 1047 break; 1048 case SIOCADDMULTI: 1049 case SIOCDELMULTI: 1050 sk_setmulti(sc_if); 1051 error = 0; 1052 break; 1053 case SIOCGIFMEDIA: 1054 case SIOCSIFMEDIA: 1055 mii = device_get_softc(sc_if->sk_miibus); 1056 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1057 break; 1058 default: 1059 error = ether_ioctl(ifp, command, data); 1060 break; 1061 } 1062 1063 crit_exit(); 1064 1065 return(error); 1066 } 1067 1068 /* 1069 * Probe for a SysKonnect GEnesis chip. Check the PCI vendor and device 1070 * IDs against our list and return a device name if we find a match. 1071 */ 1072 static int 1073 skc_probe(device_t dev) 1074 { 1075 struct sk_type *t; 1076 uint16_t vendor, product; 1077 1078 lwkt_serialize_init(&sk_serializer); 1079 vendor = pci_get_vendor(dev); 1080 product = pci_get_device(dev); 1081 1082 for (t = sk_devs; t->sk_name != NULL; t++) { 1083 if (vendor == t->sk_vid && product == t->sk_did) { 1084 device_set_desc(dev, t->sk_name); 1085 return(0); 1086 } 1087 } 1088 1089 return(ENXIO); 1090 } 1091 1092 /* 1093 * Force the GEnesis into reset, then bring it out of reset. 1094 */ 1095 static void 1096 sk_reset(struct sk_softc *sc) 1097 { 1098 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_RESET); 1099 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_RESET); 1100 if (sc->sk_type == SK_YUKON) 1101 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_SET); 1102 1103 DELAY(1000); 1104 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_UNRESET); 1105 DELAY(2); 1106 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_UNRESET); 1107 if (sc->sk_type == SK_YUKON) 1108 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_CLEAR); 1109 1110 if (sc->sk_type == SK_GENESIS) { 1111 /* Configure packet arbiter */ 1112 sk_win_write_2(sc, SK_PKTARB_CTL, SK_PKTARBCTL_UNRESET); 1113 sk_win_write_2(sc, SK_RXPA1_TINIT, SK_PKTARB_TIMEOUT); 1114 sk_win_write_2(sc, SK_TXPA1_TINIT, SK_PKTARB_TIMEOUT); 1115 sk_win_write_2(sc, SK_RXPA2_TINIT, SK_PKTARB_TIMEOUT); 1116 sk_win_write_2(sc, SK_TXPA2_TINIT, SK_PKTARB_TIMEOUT); 1117 } 1118 1119 /* Enable RAM interface */ 1120 sk_win_write_4(sc, SK_RAMCTL, SK_RAMCTL_UNRESET); 1121 1122 /* 1123 * Configure interrupt moderation. The moderation timer 1124 * defers interrupts specified in the interrupt moderation 1125 * timer mask based on the timeout specified in the interrupt 1126 * moderation timer init register. Each bit in the timer 1127 * register represents 18.825ns, so to specify a timeout in 1128 * microseconds, we have to multiply by 54. 1129 */ 1130 sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(200)); 1131 sk_win_write_4(sc, SK_IMMR, SK_ISR_TX1_S_EOF|SK_ISR_TX2_S_EOF| 1132 SK_ISR_RX1_EOF|SK_ISR_RX2_EOF); 1133 sk_win_write_1(sc, SK_IMTIMERCTL, SK_IMCTL_START); 1134 } 1135 1136 static int 1137 sk_probe(device_t dev) 1138 { 1139 struct sk_softc *sc = device_get_softc(device_get_parent(dev)); 1140 1141 /* 1142 * Not much to do here. We always know there will be 1143 * at least one XMAC present, and if there are two, 1144 * skc_attach() will create a second device instance 1145 * for us. 1146 */ 1147 switch (sc->sk_type) { 1148 case SK_GENESIS: 1149 device_set_desc(dev, "XaQti Corp. XMAC II"); 1150 break; 1151 case SK_YUKON: 1152 device_set_desc(dev, "Marvell Semiconductor, Inc. Yukon"); 1153 break; 1154 } 1155 1156 return(0); 1157 } 1158 1159 /* 1160 * Each XMAC chip is attached as a separate logical IP interface. 1161 * Single port cards will have only one logical interface of course. 1162 */ 1163 static int 1164 sk_attach(device_t dev) 1165 { 1166 struct sk_softc *sc = device_get_softc(device_get_parent(dev)); 1167 struct sk_if_softc *sc_if = device_get_softc(dev); 1168 struct ifnet *ifp; 1169 int i, port; 1170 1171 port = *(int *)device_get_ivars(dev); 1172 free(device_get_ivars(dev), M_DEVBUF); 1173 device_set_ivars(dev, NULL); 1174 sc_if->sk_dev = dev; 1175 callout_init(&sc_if->sk_tick_timer); 1176 lwkt_serialize_init(&sc_if->sk_jslot_serializer); 1177 1178 sc_if->sk_dev = dev; 1179 sc_if->sk_unit = device_get_unit(dev); 1180 sc_if->sk_port = port; 1181 sc_if->sk_softc = sc; 1182 sc->sk_if[port] = sc_if; 1183 if (port == SK_PORT_A) 1184 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR0; 1185 if (port == SK_PORT_B) 1186 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR1; 1187 1188 /* 1189 * Get station address for this interface. Note that 1190 * dual port cards actually come with three station 1191 * addresses: one for each port, plus an extra. The 1192 * extra one is used by the SysKonnect driver software 1193 * as a 'virtual' station address for when both ports 1194 * are operating in failover mode. Currently we don't 1195 * use this extra address. 1196 */ 1197 for (i = 0; i < ETHER_ADDR_LEN; i++) 1198 sc_if->arpcom.ac_enaddr[i] = 1199 sk_win_read_1(sc, SK_MAC0_0 + (port * 8) + i); 1200 1201 /* 1202 * Set up RAM buffer addresses. The NIC will have a certain 1203 * amount of SRAM on it, somewhere between 512K and 2MB. We 1204 * need to divide this up a) between the transmitter and 1205 * receiver and b) between the two XMACs, if this is a 1206 * dual port NIC. Our algotithm is to divide up the memory 1207 * evenly so that everyone gets a fair share. 1208 */ 1209 if (sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC) { 1210 uint32_t chunk, val; 1211 1212 chunk = sc->sk_ramsize / 2; 1213 val = sc->sk_rboff / sizeof(uint64_t); 1214 sc_if->sk_rx_ramstart = val; 1215 val += (chunk / sizeof(uint64_t)); 1216 sc_if->sk_rx_ramend = val - 1; 1217 sc_if->sk_tx_ramstart = val; 1218 val += (chunk / sizeof(uint64_t)); 1219 sc_if->sk_tx_ramend = val - 1; 1220 } else { 1221 uint32_t chunk, val; 1222 1223 chunk = sc->sk_ramsize / 4; 1224 val = (sc->sk_rboff + (chunk * 2 * sc_if->sk_port)) / 1225 sizeof(uint64_t); 1226 sc_if->sk_rx_ramstart = val; 1227 val += (chunk / sizeof(uint64_t)); 1228 sc_if->sk_rx_ramend = val - 1; 1229 sc_if->sk_tx_ramstart = val; 1230 val += (chunk / sizeof(uint64_t)); 1231 sc_if->sk_tx_ramend = val - 1; 1232 } 1233 1234 /* Read and save PHY type and set PHY address */ 1235 sc_if->sk_phytype = sk_win_read_1(sc, SK_EPROM1) & 0xF; 1236 switch(sc_if->sk_phytype) { 1237 case SK_PHYTYPE_XMAC: 1238 sc_if->sk_phyaddr = SK_PHYADDR_XMAC; 1239 break; 1240 case SK_PHYTYPE_BCOM: 1241 sc_if->sk_phyaddr = SK_PHYADDR_BCOM; 1242 break; 1243 case SK_PHYTYPE_MARV_COPPER: 1244 sc_if->sk_phyaddr = SK_PHYADDR_MARV; 1245 break; 1246 default: 1247 printf("skc%d: unsupported PHY type: %d\n", 1248 sc->sk_unit, sc_if->sk_phytype); 1249 sc->sk_if[port] = NULL; 1250 return(ENODEV); 1251 } 1252 1253 /* Allocate the descriptor queues. */ 1254 sc_if->sk_rdata = contigmalloc(sizeof(struct sk_ring_data), M_DEVBUF, 1255 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 1256 1257 if (sc_if->sk_rdata == NULL) { 1258 printf("sk%d: no memory for list buffers!\n", sc_if->sk_unit); 1259 sc->sk_if[port] = NULL; 1260 return(ENOMEM); 1261 } 1262 1263 bzero(sc_if->sk_rdata, sizeof(struct sk_ring_data)); 1264 1265 /* Try to allocate memory for jumbo buffers. */ 1266 if (sk_alloc_jumbo_mem(sc_if)) { 1267 printf("sk%d: jumbo buffer allocation failed\n", 1268 sc_if->sk_unit); 1269 contigfree(sc_if->sk_rdata, 1270 sizeof(struct sk_ring_data), M_DEVBUF); 1271 sc->sk_if[port] = NULL; 1272 return(ENOMEM); 1273 } 1274 1275 ifp = &sc_if->arpcom.ac_if; 1276 ifp->if_softc = sc_if; 1277 if_initname(ifp, "sk", sc_if->sk_unit); 1278 ifp->if_mtu = ETHERMTU; 1279 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1280 ifp->if_ioctl = sk_ioctl; 1281 ifp->if_start = sk_start; 1282 ifp->if_watchdog = sk_watchdog; 1283 ifp->if_init = sk_init; 1284 ifp->if_baudrate = 1000000000; 1285 ifq_set_maxlen(&ifp->if_snd, SK_TX_RING_CNT - 1); 1286 ifq_set_ready(&ifp->if_snd); 1287 1288 /* 1289 * Do miibus setup. 1290 */ 1291 switch (sc->sk_type) { 1292 case SK_GENESIS: 1293 sk_init_xmac(sc_if); 1294 break; 1295 case SK_YUKON: 1296 sk_init_yukon(sc_if); 1297 break; 1298 } 1299 1300 if (mii_phy_probe(dev, &sc_if->sk_miibus, 1301 sk_ifmedia_upd, sk_ifmedia_sts)) { 1302 printf("skc%d: no PHY found!\n", sc_if->sk_unit); 1303 contigfree(sc_if->sk_cdata.sk_jumbo_buf, SK_JMEM, 1304 M_DEVBUF); 1305 contigfree(sc_if->sk_rdata, 1306 sizeof(struct sk_ring_data), M_DEVBUF); 1307 sc->sk_if[port] = NULL; 1308 return(ENXIO); 1309 } 1310 1311 /* 1312 * Call MI attach routine. 1313 */ 1314 ether_ifattach(ifp, sc_if->arpcom.ac_enaddr, &sk_serializer); 1315 callout_init(&sc_if->sk_tick_timer); 1316 1317 return(0); 1318 } 1319 1320 /* 1321 * Attach the interface. Allocate softc structures, do ifmedia 1322 * setup and ethernet/BPF attach. 1323 */ 1324 static int 1325 skc_attach(device_t dev) 1326 { 1327 struct sk_softc *sc; 1328 int error = 0, *port, rid, unit; 1329 uint32_t command; 1330 uint8_t skrs; 1331 1332 crit_enter(); 1333 1334 sc = device_get_softc(dev); 1335 unit = device_get_unit(dev); 1336 switch (pci_get_device(dev)) { 1337 case DEVICEID_SK_V1: 1338 sc->sk_type = SK_GENESIS; 1339 break; 1340 case DEVICEID_SK_V2: 1341 case DEVICEID_3COM_3C940: 1342 case DEVICEID_LINKSYS_EG1032: 1343 case DEVICEID_DLINK_DGE530T: 1344 sc->sk_type = SK_YUKON; 1345 break; 1346 } 1347 1348 /* 1349 * Handle power management nonsense. 1350 */ 1351 command = pci_read_config(dev, SK_PCI_CAPID, 4) & 0x000000FF; 1352 if (command == 0x01) { 1353 command = pci_read_config(dev, SK_PCI_PWRMGMTCTRL, 4); 1354 if (command & SK_PSTATE_MASK) { 1355 uint32_t iobase, membase, irq; 1356 1357 /* Save important PCI config data. */ 1358 iobase = pci_read_config(dev, SK_PCI_LOIO, 4); 1359 membase = pci_read_config(dev, SK_PCI_LOMEM, 4); 1360 irq = pci_read_config(dev, SK_PCI_INTLINE, 4); 1361 1362 /* Reset the power state. */ 1363 printf("skc%d: chip is in D%d power mode " 1364 "-- setting to D0\n", unit, command & SK_PSTATE_MASK); 1365 command &= 0xFFFFFFFC; 1366 pci_write_config(dev, SK_PCI_PWRMGMTCTRL, command, 4); 1367 1368 /* Restore PCI config data. */ 1369 pci_write_config(dev, SK_PCI_LOIO, iobase, 4); 1370 pci_write_config(dev, SK_PCI_LOMEM, membase, 4); 1371 pci_write_config(dev, SK_PCI_INTLINE, irq, 4); 1372 } 1373 } 1374 1375 /* 1376 * Map control/status registers. 1377 */ 1378 command = pci_read_config(dev, PCIR_COMMAND, 4); 1379 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 1380 pci_write_config(dev, PCIR_COMMAND, command, 4); 1381 command = pci_read_config(dev, PCIR_COMMAND, 4); 1382 1383 #ifdef SK_USEIOSPACE 1384 if ((command & PCIM_CMD_PORTEN) == 0) { 1385 printf("skc%d: failed to enable I/O ports!\n", unit); 1386 error = ENXIO; 1387 goto fail; 1388 } 1389 #else 1390 if ((command & PCIM_CMD_MEMEN) == 0) { 1391 printf("skc%d: failed to enable memory mapping!\n", unit); 1392 error = ENXIO; 1393 goto fail; 1394 } 1395 #endif 1396 1397 rid = SK_RID; 1398 sc->sk_res = bus_alloc_resource_any(dev, SK_RES, &rid, RF_ACTIVE); 1399 1400 if (sc->sk_res == NULL) { 1401 printf("sk%d: couldn't map ports/memory\n", unit); 1402 error = ENXIO; 1403 goto fail; 1404 } 1405 1406 sc->sk_btag = rman_get_bustag(sc->sk_res); 1407 sc->sk_bhandle = rman_get_bushandle(sc->sk_res); 1408 1409 /* Allocate interrupt */ 1410 rid = 0; 1411 sc->sk_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1412 RF_SHAREABLE | RF_ACTIVE); 1413 1414 if (sc->sk_irq == NULL) { 1415 printf("skc%d: couldn't map interrupt\n", unit); 1416 bus_release_resource(dev, SK_RES, SK_RID, sc->sk_res); 1417 error = ENXIO; 1418 goto fail; 1419 } 1420 1421 error = bus_setup_intr(dev, sc->sk_irq, INTR_NETSAFE, 1422 sk_intr, sc, 1423 &sc->sk_intrhand, &sk_serializer); 1424 1425 if (error) { 1426 printf("skc%d: couldn't set up irq\n", unit); 1427 bus_release_resource(dev, SK_RES, SK_RID, sc->sk_res); 1428 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sk_irq); 1429 goto fail; 1430 } 1431 1432 /* Reset the adapter. */ 1433 sk_reset(sc); 1434 1435 sc->sk_unit = unit; 1436 1437 /* Read and save vital product data from EEPROM. */ 1438 sk_vpd_read(sc); 1439 1440 skrs = sk_win_read_1(sc, SK_EPROM0); 1441 if (sc->sk_type == SK_GENESIS) { 1442 /* Read and save RAM size and RAMbuffer offset */ 1443 switch(skrs) { 1444 case SK_RAMSIZE_512K_64: 1445 sc->sk_ramsize = 0x80000; 1446 sc->sk_rboff = SK_RBOFF_0; 1447 break; 1448 case SK_RAMSIZE_1024K_64: 1449 sc->sk_ramsize = 0x100000; 1450 sc->sk_rboff = SK_RBOFF_80000; 1451 break; 1452 case SK_RAMSIZE_1024K_128: 1453 sc->sk_ramsize = 0x100000; 1454 sc->sk_rboff = SK_RBOFF_0; 1455 break; 1456 case SK_RAMSIZE_2048K_128: 1457 sc->sk_ramsize = 0x200000; 1458 sc->sk_rboff = SK_RBOFF_0; 1459 break; 1460 default: 1461 printf("skc%d: unknown ram size: %d\n", 1462 sc->sk_unit, sk_win_read_1(sc, SK_EPROM0)); 1463 bus_teardown_intr(dev, sc->sk_irq, sc->sk_intrhand); 1464 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sk_irq); 1465 bus_release_resource(dev, SK_RES, SK_RID, sc->sk_res); 1466 error = ENXIO; 1467 goto fail; 1468 break; 1469 } 1470 } else { /* SK_YUKON */ 1471 if (skrs == 0x00) { 1472 sc->sk_ramsize = 0x20000; 1473 } else { 1474 sc->sk_ramsize = skrs * (1<<12); 1475 } 1476 sc->sk_rboff = SK_RBOFF_0; 1477 } 1478 1479 /* Read and save physical media type */ 1480 switch(sk_win_read_1(sc, SK_PMDTYPE)) { 1481 case SK_PMD_1000BASESX: 1482 sc->sk_pmd = IFM_1000_SX; 1483 break; 1484 case SK_PMD_1000BASELX: 1485 sc->sk_pmd = IFM_1000_LX; 1486 break; 1487 case SK_PMD_1000BASECX: 1488 sc->sk_pmd = IFM_1000_CX; 1489 break; 1490 case SK_PMD_1000BASETX: 1491 sc->sk_pmd = IFM_1000_T; 1492 break; 1493 default: 1494 printf("skc%d: unknown media type: 0x%x\n", 1495 sc->sk_unit, sk_win_read_1(sc, SK_PMDTYPE)); 1496 bus_teardown_intr(dev, sc->sk_irq, sc->sk_intrhand); 1497 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sk_irq); 1498 bus_release_resource(dev, SK_RES, SK_RID, sc->sk_res); 1499 error = ENXIO; 1500 goto fail; 1501 } 1502 1503 /* Announce the product name. */ 1504 printf("skc%d: %s\n", sc->sk_unit, sc->sk_vpd_prodname); 1505 sc->sk_devs[SK_PORT_A] = device_add_child(dev, "sk", -1); 1506 port = malloc(sizeof(int), M_DEVBUF, M_WAITOK); 1507 *port = SK_PORT_A; 1508 device_set_ivars(sc->sk_devs[SK_PORT_A], port); 1509 1510 if (!(sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC)) { 1511 sc->sk_devs[SK_PORT_B] = device_add_child(dev, "sk", -1); 1512 port = malloc(sizeof(int), M_DEVBUF, M_WAITOK); 1513 *port = SK_PORT_B; 1514 device_set_ivars(sc->sk_devs[SK_PORT_B], port); 1515 } 1516 1517 /* Turn on the 'driver is loaded' LED. */ 1518 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON); 1519 1520 bus_generic_attach(dev); 1521 1522 fail: 1523 crit_exit(); 1524 return(error); 1525 } 1526 1527 static int 1528 sk_detach(device_t dev) 1529 { 1530 struct sk_if_softc *sc_if = device_get_softc(dev); 1531 struct ifnet *ifp = &sc_if->arpcom.ac_if; 1532 1533 ether_ifdetach(ifp); 1534 bus_generic_detach(dev); 1535 if (sc_if->sk_miibus != NULL) 1536 device_delete_child(dev, sc_if->sk_miibus); 1537 contigfree(sc_if->sk_cdata.sk_jumbo_buf, SK_JMEM, M_DEVBUF); 1538 contigfree(sc_if->sk_rdata, sizeof(struct sk_ring_data), M_DEVBUF); 1539 1540 return(0); 1541 } 1542 1543 static int 1544 skc_detach(device_t dev) 1545 { 1546 struct sk_softc *sc; 1547 1548 sc = device_get_softc(dev); 1549 1550 lwkt_serialize_enter(&sk_serializer); 1551 1552 if (sc->sk_if[SK_PORT_A] != NULL) 1553 sk_stop(sc->sk_if[SK_PORT_A]); 1554 if (sc->sk_if[SK_PORT_B] != NULL) 1555 sk_stop(sc->sk_if[SK_PORT_B]); 1556 1557 bus_teardown_intr(dev, sc->sk_irq, sc->sk_intrhand); 1558 1559 lwkt_serialize_exit(&sk_serializer); 1560 1561 /* 1562 * recursed from sk_detach ? don't need serializer 1563 */ 1564 bus_generic_detach(dev); 1565 if (sc->sk_devs[SK_PORT_A] != NULL) 1566 device_delete_child(dev, sc->sk_devs[SK_PORT_A]); 1567 if (sc->sk_devs[SK_PORT_B] != NULL) 1568 device_delete_child(dev, sc->sk_devs[SK_PORT_B]); 1569 1570 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sk_irq); 1571 bus_release_resource(dev, SK_RES, SK_RID, sc->sk_res); 1572 1573 return(0); 1574 } 1575 1576 static int 1577 sk_encap(struct sk_if_softc *sc_if, struct mbuf *m_head, uint32_t *txidx) 1578 { 1579 struct sk_tx_desc *f = NULL; 1580 struct mbuf *m; 1581 uint32_t cnt = 0, cur, frag; 1582 1583 m = m_head; 1584 cur = frag = *txidx; 1585 1586 /* 1587 * Start packing the mbufs in this chain into 1588 * the fragment pointers. Stop when we run out 1589 * of fragments or hit the end of the mbuf chain. 1590 */ 1591 for (m = m_head; m != NULL; m = m->m_next) { 1592 if (m->m_len != 0) { 1593 if ((SK_TX_RING_CNT - 1594 (sc_if->sk_cdata.sk_tx_cnt + cnt)) < 2) 1595 return(ENOBUFS); 1596 f = &sc_if->sk_rdata->sk_tx_ring[frag]; 1597 f->sk_data_lo = vtophys(mtod(m, vm_offset_t)); 1598 f->sk_ctl = m->m_len | SK_OPCODE_DEFAULT; 1599 if (cnt == 0) 1600 f->sk_ctl |= SK_TXCTL_FIRSTFRAG; 1601 else 1602 f->sk_ctl |= SK_TXCTL_OWN; 1603 cur = frag; 1604 SK_INC(frag, SK_TX_RING_CNT); 1605 cnt++; 1606 } 1607 } 1608 1609 if (m != NULL) 1610 return(ENOBUFS); 1611 1612 sc_if->sk_rdata->sk_tx_ring[cur].sk_ctl |= 1613 SK_TXCTL_LASTFRAG|SK_TXCTL_EOF_INTR; 1614 sc_if->sk_cdata.sk_tx_chain[cur].sk_mbuf = m_head; 1615 sc_if->sk_rdata->sk_tx_ring[*txidx].sk_ctl |= SK_TXCTL_OWN; 1616 sc_if->sk_cdata.sk_tx_cnt += cnt; 1617 1618 *txidx = frag; 1619 1620 return(0); 1621 } 1622 1623 static void 1624 sk_start(struct ifnet *ifp) 1625 { 1626 struct sk_if_softc *sc_if = ifp->if_softc; 1627 struct sk_softc *sc = sc_if->sk_softc; 1628 struct mbuf *m_head = NULL; 1629 uint32_t idx; 1630 int need_trans; 1631 1632 idx = sc_if->sk_cdata.sk_tx_prod; 1633 1634 need_trans = 0; 1635 while(sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf == NULL) { 1636 m_head = ifq_poll(&ifp->if_snd); 1637 if (m_head == NULL) 1638 break; 1639 1640 /* 1641 * Pack the data into the transmit ring. If we 1642 * don't have room, set the OACTIVE flag and wait 1643 * for the NIC to drain the ring. 1644 */ 1645 if (sk_encap(sc_if, m_head, &idx)) { 1646 ifp->if_flags |= IFF_OACTIVE; 1647 break; 1648 } 1649 ifq_dequeue(&ifp->if_snd, m_head); 1650 need_trans = 1; 1651 1652 BPF_MTAP(ifp, m_head); 1653 } 1654 1655 if (!need_trans) 1656 return; 1657 1658 /* Transmit */ 1659 sc_if->sk_cdata.sk_tx_prod = idx; 1660 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START); 1661 1662 /* Set a timeout in case the chip goes out to lunch. */ 1663 ifp->if_timer = 5; 1664 } 1665 1666 1667 static void 1668 sk_watchdog(struct ifnet *ifp) 1669 { 1670 struct sk_if_softc *sc_if; 1671 1672 sc_if = ifp->if_softc; 1673 1674 printf("sk%d: watchdog timeout\n", sc_if->sk_unit); 1675 sk_init(sc_if); 1676 1677 if (!ifq_is_empty(&ifp->if_snd)) 1678 ifp->if_start(ifp); 1679 } 1680 1681 static void 1682 skc_shutdown(device_t dev) 1683 { 1684 struct sk_softc *sc = device_get_softc(dev); 1685 1686 lwkt_serialize_enter(&sk_serializer); 1687 1688 /* Turn off the 'driver is loaded' LED. */ 1689 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF); 1690 1691 /* 1692 * Reset the GEnesis controller. Doing this should also 1693 * assert the resets on the attached XMAC(s). 1694 */ 1695 sk_reset(sc); 1696 lwkt_serialize_exit(&sk_serializer); 1697 } 1698 1699 static void 1700 sk_rxeof(struct sk_if_softc *sc_if) 1701 { 1702 struct ifnet *ifp = &sc_if->arpcom.ac_if; 1703 struct mbuf *m; 1704 struct sk_chain *cur_rx; 1705 int i, total_len = 0; 1706 uint32_t rxstat; 1707 1708 i = sc_if->sk_cdata.sk_rx_prod; 1709 cur_rx = &sc_if->sk_cdata.sk_rx_chain[i]; 1710 1711 while(!(sc_if->sk_rdata->sk_rx_ring[i].sk_ctl & SK_RXCTL_OWN)) { 1712 cur_rx = &sc_if->sk_cdata.sk_rx_chain[i]; 1713 rxstat = sc_if->sk_rdata->sk_rx_ring[i].sk_xmac_rxstat; 1714 m = cur_rx->sk_mbuf; 1715 cur_rx->sk_mbuf = NULL; 1716 total_len = SK_RXBYTES(sc_if->sk_rdata->sk_rx_ring[i].sk_ctl); 1717 SK_INC(i, SK_RX_RING_CNT); 1718 1719 if (rxstat & XM_RXSTAT_ERRFRAME) { 1720 ifp->if_ierrors++; 1721 sk_newbuf(sc_if, cur_rx, m); 1722 continue; 1723 } 1724 1725 /* 1726 * Try to allocate a new jumbo buffer. If that 1727 * fails, copy the packet to mbufs and put the 1728 * jumbo buffer back in the ring so it can be 1729 * re-used. If allocating mbufs fails, then we 1730 * have to drop the packet. 1731 */ 1732 if (sk_newbuf(sc_if, cur_rx, NULL) == ENOBUFS) { 1733 struct mbuf *m0; 1734 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 1735 total_len + ETHER_ALIGN, 0, ifp, NULL); 1736 sk_newbuf(sc_if, cur_rx, m); 1737 if (m0 == NULL) { 1738 printf("sk%d: no receive buffers " 1739 "available -- packet dropped!\n", 1740 sc_if->sk_unit); 1741 ifp->if_ierrors++; 1742 continue; 1743 } 1744 m_adj(m0, ETHER_ALIGN); 1745 m = m0; 1746 } else { 1747 m->m_pkthdr.rcvif = ifp; 1748 m->m_pkthdr.len = m->m_len = total_len; 1749 } 1750 1751 ifp->if_ipackets++; 1752 ifp->if_input(ifp, m); 1753 } 1754 1755 sc_if->sk_cdata.sk_rx_prod = i; 1756 } 1757 1758 static void 1759 sk_txeof(struct sk_if_softc *sc_if) 1760 { 1761 struct ifnet *ifp = &sc_if->arpcom.ac_if; 1762 struct sk_tx_desc *cur_tx = NULL; 1763 uint32_t idx; 1764 1765 /* 1766 * Go through our tx ring and free mbufs for those 1767 * frames that have been sent. 1768 */ 1769 idx = sc_if->sk_cdata.sk_tx_cons; 1770 while(idx != sc_if->sk_cdata.sk_tx_prod) { 1771 cur_tx = &sc_if->sk_rdata->sk_tx_ring[idx]; 1772 if (cur_tx->sk_ctl & SK_TXCTL_OWN) 1773 break; 1774 if (cur_tx->sk_ctl & SK_TXCTL_LASTFRAG) 1775 ifp->if_opackets++; 1776 if (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf != NULL) { 1777 m_freem(sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf); 1778 sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf = NULL; 1779 } 1780 sc_if->sk_cdata.sk_tx_cnt--; 1781 SK_INC(idx, SK_TX_RING_CNT); 1782 ifp->if_timer = 0; 1783 } 1784 1785 sc_if->sk_cdata.sk_tx_cons = idx; 1786 1787 if (cur_tx != NULL) 1788 ifp->if_flags &= ~IFF_OACTIVE; 1789 } 1790 1791 static void 1792 sk_tick(void *xsc_if) 1793 { 1794 struct sk_if_softc *sc_if = xsc_if; 1795 struct ifnet *ifp = &sc_if->arpcom.ac_if; 1796 struct mii_data *mii = device_get_softc(sc_if->sk_miibus); 1797 int i; 1798 1799 lwkt_serialize_enter(&sk_serializer); 1800 1801 if ((ifp->if_flags & IFF_UP) == 0) { 1802 lwkt_serialize_exit(&sk_serializer); 1803 return; 1804 } 1805 1806 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 1807 sk_intr_bcom(sc_if); 1808 lwkt_serialize_exit(&sk_serializer); 1809 return; 1810 } 1811 1812 /* 1813 * According to SysKonnect, the correct way to verify that 1814 * the link has come back up is to poll bit 0 of the GPIO 1815 * register three times. This pin has the signal from the 1816 * link_sync pin connected to it; if we read the same link 1817 * state 3 times in a row, we know the link is up. 1818 */ 1819 for (i = 0; i < 3; i++) { 1820 if (SK_XM_READ_2(sc_if, XM_GPIO) & XM_GPIO_GP0_SET) 1821 break; 1822 } 1823 1824 if (i != 3) { 1825 callout_reset(&sc_if->sk_tick_timer, hz, sk_tick, sc_if); 1826 lwkt_serialize_exit(&sk_serializer); 1827 return; 1828 } 1829 1830 /* Turn the GP0 interrupt back on. */ 1831 SK_XM_CLRBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET); 1832 SK_XM_READ_2(sc_if, XM_ISR); 1833 mii_tick(mii); 1834 mii_pollstat(mii); 1835 callout_stop(&sc_if->sk_tick_timer); 1836 lwkt_serialize_exit(&sk_serializer); 1837 } 1838 1839 static void 1840 sk_intr_bcom(struct sk_if_softc *sc_if) 1841 { 1842 struct ifnet *ifp = &sc_if->arpcom.ac_if; 1843 struct mii_data *mii = device_get_softc(sc_if->sk_miibus); 1844 int status; 1845 1846 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 1847 1848 /* 1849 * Read the PHY interrupt register to make sure 1850 * we clear any pending interrupts. 1851 */ 1852 status = sk_xmac_miibus_readreg(sc_if, SK_PHYADDR_BCOM, BRGPHY_MII_ISR); 1853 1854 if ((ifp->if_flags & IFF_RUNNING) == 0) { 1855 sk_init_xmac(sc_if); 1856 return; 1857 } 1858 1859 if (status & (BRGPHY_ISR_LNK_CHG|BRGPHY_ISR_AN_PR)) { 1860 int lstat; 1861 lstat = sk_xmac_miibus_readreg(sc_if, SK_PHYADDR_BCOM, 1862 BRGPHY_MII_AUXSTS); 1863 1864 if (!(lstat & BRGPHY_AUXSTS_LINK) && sc_if->sk_link) { 1865 mii_mediachg(mii); 1866 /* Turn off the link LED. */ 1867 SK_IF_WRITE_1(sc_if, 0, 1868 SK_LINKLED1_CTL, SK_LINKLED_OFF); 1869 sc_if->sk_link = 0; 1870 } else if (status & BRGPHY_ISR_LNK_CHG) { 1871 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM, 1872 BRGPHY_MII_IMR, 0xFF00); 1873 mii_tick(mii); 1874 sc_if->sk_link = 1; 1875 /* Turn on the link LED. */ 1876 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, 1877 SK_LINKLED_ON|SK_LINKLED_LINKSYNC_OFF| 1878 SK_LINKLED_BLINK_OFF); 1879 mii_pollstat(mii); 1880 } else { 1881 mii_tick(mii); 1882 callout_reset(&sc_if->sk_tick_timer, hz, 1883 sk_tick, sc_if); 1884 } 1885 } 1886 1887 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 1888 } 1889 1890 static void 1891 sk_intr_xmac(struct sk_if_softc *sc_if) 1892 { 1893 uint16_t status; 1894 1895 status = SK_XM_READ_2(sc_if, XM_ISR); 1896 1897 /* 1898 * Link has gone down. Start MII tick timeout to 1899 * watch for link resync. 1900 */ 1901 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) { 1902 if (status & XM_ISR_GP0_SET) { 1903 SK_XM_SETBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET); 1904 callout_reset(&sc_if->sk_tick_timer, hz, 1905 sk_tick, sc_if); 1906 } 1907 1908 if (status & XM_ISR_AUTONEG_DONE) { 1909 callout_reset(&sc_if->sk_tick_timer, hz, 1910 sk_tick, sc_if); 1911 } 1912 } 1913 1914 if (status & XM_IMR_TX_UNDERRUN) 1915 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_TXFIFO); 1916 1917 if (status & XM_IMR_RX_OVERRUN) 1918 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_RXFIFO); 1919 1920 status = SK_XM_READ_2(sc_if, XM_ISR); 1921 } 1922 1923 static void 1924 sk_intr_yukon(struct sk_if_softc *sc_if) 1925 { 1926 int status; 1927 1928 status = SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 1929 } 1930 1931 static void 1932 sk_intr(void *xsc) 1933 { 1934 struct sk_softc *sc = xsc; 1935 struct sk_if_softc *sc_if0 = sc->sk_if[SK_PORT_A]; 1936 struct sk_if_softc *sc_if1 = sc->sk_if[SK_PORT_A]; 1937 struct ifnet *ifp0 = NULL, *ifp1 = NULL; 1938 uint32_t status; 1939 1940 if (sc_if0 != NULL) 1941 ifp0 = &sc_if0->arpcom.ac_if; 1942 if (sc_if1 != NULL) 1943 ifp1 = &sc_if1->arpcom.ac_if; 1944 1945 for (;;) { 1946 status = CSR_READ_4(sc, SK_ISSR); 1947 if ((status & sc->sk_intrmask) == 0) 1948 break; 1949 1950 /* Handle receive interrupts first. */ 1951 if (status & SK_ISR_RX1_EOF) { 1952 sk_rxeof(sc_if0); 1953 CSR_WRITE_4(sc, SK_BMU_RX_CSR0, 1954 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START); 1955 } 1956 if (status & SK_ISR_RX2_EOF) { 1957 sk_rxeof(sc_if1); 1958 CSR_WRITE_4(sc, SK_BMU_RX_CSR1, 1959 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START); 1960 } 1961 1962 /* Then transmit interrupts. */ 1963 if (status & SK_ISR_TX1_S_EOF) { 1964 sk_txeof(sc_if0); 1965 CSR_WRITE_4(sc, SK_BMU_TXS_CSR0, 1966 SK_TXBMU_CLR_IRQ_EOF); 1967 } 1968 if (status & SK_ISR_TX2_S_EOF) { 1969 sk_txeof(sc_if1); 1970 CSR_WRITE_4(sc, SK_BMU_TXS_CSR1, 1971 SK_TXBMU_CLR_IRQ_EOF); 1972 } 1973 1974 /* Then MAC interrupts. */ 1975 if (status & SK_ISR_MAC1 && ifp0->if_flags & IFF_RUNNING) { 1976 if (sc->sk_type == SK_GENESIS) 1977 sk_intr_xmac(sc_if0); 1978 else 1979 sk_intr_yukon(sc_if0); 1980 } 1981 1982 if (status & SK_ISR_MAC2 && ifp1->if_flags & IFF_RUNNING) { 1983 if (sc->sk_type == SK_GENESIS) 1984 sk_intr_xmac(sc_if1); 1985 else 1986 sk_intr_yukon(sc_if0); 1987 } 1988 1989 if (status & SK_ISR_EXTERNAL_REG) { 1990 if (ifp0 != NULL && 1991 sc_if0->sk_phytype == SK_PHYTYPE_BCOM) 1992 sk_intr_bcom(sc_if0); 1993 if (ifp1 != NULL && 1994 sc_if1->sk_phytype == SK_PHYTYPE_BCOM) 1995 sk_intr_bcom(sc_if1); 1996 } 1997 } 1998 1999 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2000 2001 if (ifp0 != NULL && !ifq_is_empty(&ifp0->if_snd)) 2002 sk_start(ifp0); 2003 if (ifp1 != NULL && !ifq_is_empty(&ifp0->if_snd)) 2004 sk_start(ifp1); 2005 } 2006 2007 static void 2008 sk_init_xmac(struct sk_if_softc *sc_if) 2009 { 2010 struct sk_softc *sc = sc_if->sk_softc; 2011 struct ifnet *ifp = &sc_if->arpcom.ac_if; 2012 struct sk_bcom_hack bhack[] = { 2013 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 }, { 0x17, 0x0013 }, 2014 { 0x15, 0x0404 }, { 0x17, 0x8006 }, { 0x15, 0x0132 }, { 0x17, 0x8006 }, 2015 { 0x15, 0x0232 }, { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 }, 2016 { 0, 0 } }; 2017 2018 /* Unreset the XMAC. */ 2019 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_UNRESET); 2020 DELAY(1000); 2021 2022 /* Reset the XMAC's internal state. */ 2023 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 2024 2025 /* Save the XMAC II revision */ 2026 sc_if->sk_xmac_rev = XM_XMAC_REV(SK_XM_READ_4(sc_if, XM_DEVID)); 2027 2028 /* 2029 * Perform additional initialization for external PHYs, 2030 * namely for the 1000baseTX cards that use the XMAC's 2031 * GMII mode. 2032 */ 2033 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2034 int i = 0; 2035 uint32_t val; 2036 2037 /* Take PHY out of reset. */ 2038 val = sk_win_read_4(sc, SK_GPIO); 2039 if (sc_if->sk_port == SK_PORT_A) 2040 val |= SK_GPIO_DIR0|SK_GPIO_DAT0; 2041 else 2042 val |= SK_GPIO_DIR2|SK_GPIO_DAT2; 2043 sk_win_write_4(sc, SK_GPIO, val); 2044 2045 /* Enable GMII mode on the XMAC. */ 2046 SK_XM_SETBIT_2(sc_if, XM_HWCFG, XM_HWCFG_GMIIMODE); 2047 2048 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM, 2049 BRGPHY_MII_BMCR, BRGPHY_BMCR_RESET); 2050 DELAY(10000); 2051 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM, 2052 BRGPHY_MII_IMR, 0xFFF0); 2053 2054 /* 2055 * Early versions of the BCM5400 apparently have 2056 * a bug that requires them to have their reserved 2057 * registers initialized to some magic values. I don't 2058 * know what the numbers do, I'm just the messenger. 2059 */ 2060 if (sk_xmac_miibus_readreg(sc_if, SK_PHYADDR_BCOM, 0x03) 2061 == 0x6041) { 2062 while(bhack[i].reg) { 2063 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM, 2064 bhack[i].reg, bhack[i].val); 2065 i++; 2066 } 2067 } 2068 } 2069 2070 /* Set station address */ 2071 SK_XM_WRITE_2(sc_if, XM_PAR0, 2072 *(uint16_t *)(&sc_if->arpcom.ac_enaddr[0])); 2073 SK_XM_WRITE_2(sc_if, XM_PAR1, 2074 *(uint16_t *)(&sc_if->arpcom.ac_enaddr[2])); 2075 SK_XM_WRITE_2(sc_if, XM_PAR2, 2076 *(uint16_t *)(&sc_if->arpcom.ac_enaddr[4])); 2077 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_STATION); 2078 2079 if (ifp->if_flags & IFF_BROADCAST) 2080 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD); 2081 else 2082 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD); 2083 2084 /* We don't need the FCS appended to the packet. */ 2085 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_STRIPFCS); 2086 2087 /* We want short frames padded to 60 bytes. */ 2088 SK_XM_SETBIT_2(sc_if, XM_TXCMD, XM_TXCMD_AUTOPAD); 2089 2090 /* 2091 * Enable the reception of all error frames. This is is 2092 * a necessary evil due to the design of the XMAC. The 2093 * XMAC's receive FIFO is only 8K in size, however jumbo 2094 * frames can be up to 9000 bytes in length. When bad 2095 * frame filtering is enabled, the XMAC's RX FIFO operates 2096 * in 'store and forward' mode. For this to work, the 2097 * entire frame has to fit into the FIFO, but that means 2098 * that jumbo frames larger than 8192 bytes will be 2099 * truncated. Disabling all bad frame filtering causes 2100 * the RX FIFO to operate in streaming mode, in which 2101 * case the XMAC will start transfering frames out of the 2102 * RX FIFO as soon as the FIFO threshold is reached. 2103 */ 2104 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_BADFRAMES| 2105 XM_MODE_RX_GIANTS|XM_MODE_RX_RUNTS|XM_MODE_RX_CRCERRS| 2106 XM_MODE_RX_INRANGELEN); 2107 2108 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 2109 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK); 2110 else 2111 SK_XM_CLRBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK); 2112 2113 /* 2114 * Bump up the transmit threshold. This helps hold off transmit 2115 * underruns when we're blasting traffic from both ports at once. 2116 */ 2117 SK_XM_WRITE_2(sc_if, XM_TX_REQTHRESH, SK_XM_TX_FIFOTHRESH); 2118 2119 /* Set promiscuous mode */ 2120 sk_setpromisc(sc_if); 2121 2122 /* Set multicast filter */ 2123 sk_setmulti(sc_if); 2124 2125 /* Clear and enable interrupts */ 2126 SK_XM_READ_2(sc_if, XM_ISR); 2127 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) 2128 SK_XM_WRITE_2(sc_if, XM_IMR, XM_INTRS); 2129 else 2130 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 2131 2132 /* Configure MAC arbiter */ 2133 switch(sc_if->sk_xmac_rev) { 2134 case XM_XMAC_REV_B2: 2135 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_B2); 2136 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_B2); 2137 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_B2); 2138 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_B2); 2139 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_B2); 2140 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_B2); 2141 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_B2); 2142 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_B2); 2143 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2); 2144 break; 2145 case XM_XMAC_REV_C1: 2146 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_C1); 2147 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_C1); 2148 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_C1); 2149 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_C1); 2150 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_C1); 2151 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_C1); 2152 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_C1); 2153 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_C1); 2154 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2); 2155 break; 2156 default: 2157 break; 2158 } 2159 sk_win_write_2(sc, SK_MACARB_CTL, 2160 SK_MACARBCTL_UNRESET|SK_MACARBCTL_FASTOE_OFF); 2161 2162 sc_if->sk_link = 1; 2163 } 2164 2165 static void 2166 sk_init_yukon(struct sk_if_softc *sc_if) 2167 { 2168 struct ifnet *ifp = &sc_if->arpcom.ac_if; 2169 uint32_t phy; 2170 uint16_t reg; 2171 int i; 2172 2173 /* GMAC and GPHY Reset */ 2174 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_SET); 2175 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 2176 DELAY(1000); 2177 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_CLEAR); 2178 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 2179 DELAY(1000); 2180 2181 phy = SK_GPHY_INT_POL_HI | SK_GPHY_DIS_FC | SK_GPHY_DIS_SLEEP | 2182 SK_GPHY_ENA_XC | SK_GPHY_ANEG_ALL | SK_GPHY_ENA_PAUSE; 2183 2184 switch(sc_if->sk_softc->sk_pmd) { 2185 case IFM_1000_SX: 2186 case IFM_1000_LX: 2187 phy |= SK_GPHY_FIBER; 2188 break; 2189 2190 case IFM_1000_CX: 2191 case IFM_1000_T: 2192 phy |= SK_GPHY_COPPER; 2193 break; 2194 } 2195 2196 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_SET); 2197 DELAY(1000); 2198 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_CLEAR); 2199 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_LOOP_OFF | 2200 SK_GMAC_PAUSE_ON | SK_GMAC_RESET_CLEAR); 2201 2202 /* unused read of the interrupt source register */ 2203 SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 2204 2205 reg = SK_YU_READ_2(sc_if, YUKON_PAR); 2206 2207 /* MIB Counter Clear Mode set */ 2208 reg |= YU_PAR_MIB_CLR; 2209 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2210 2211 /* MIB Counter Clear Mode clear */ 2212 reg &= ~YU_PAR_MIB_CLR; 2213 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2214 2215 /* receive control reg */ 2216 SK_YU_WRITE_2(sc_if, YUKON_RCR, YU_RCR_CRCR); 2217 2218 /* transmit parameter register */ 2219 SK_YU_WRITE_2(sc_if, YUKON_TPR, YU_TPR_JAM_LEN(0x3) | 2220 YU_TPR_JAM_IPG(0xb) | YU_TPR_JAM2DATA_IPG(0x1a) ); 2221 2222 /* serial mode register */ 2223 reg = YU_SMR_DATA_BLIND(0x1c) | YU_SMR_MFL_VLAN | YU_SMR_IPG_DATA(0x1e); 2224 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 2225 reg |= YU_SMR_MFL_JUMBO; 2226 SK_YU_WRITE_2(sc_if, YUKON_SMR, reg); 2227 2228 /* Setup Yukon's address */ 2229 for (i = 0; i < 3; i++) { 2230 /* Write Source Address 1 (unicast filter) */ 2231 SK_YU_WRITE_2(sc_if, YUKON_SAL1 + i * 4, 2232 sc_if->arpcom.ac_enaddr[i * 2] | 2233 sc_if->arpcom.ac_enaddr[i * 2 + 1] << 8); 2234 } 2235 2236 for (i = 0; i < 3; i++) { 2237 reg = sk_win_read_2(sc_if->sk_softc, 2238 SK_MAC1_0 + i * 2 + sc_if->sk_port * 8); 2239 SK_YU_WRITE_2(sc_if, YUKON_SAL2 + i * 4, reg); 2240 } 2241 2242 /* Set promiscuous mode */ 2243 sk_setpromisc(sc_if); 2244 2245 /* Set multicast filter */ 2246 sk_setmulti(sc_if); 2247 2248 /* enable interrupt mask for counter overflows */ 2249 SK_YU_WRITE_2(sc_if, YUKON_TIMR, 0); 2250 SK_YU_WRITE_2(sc_if, YUKON_RIMR, 0); 2251 SK_YU_WRITE_2(sc_if, YUKON_TRIMR, 0); 2252 2253 /* Configure RX MAC FIFO */ 2254 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_CLEAR); 2255 SK_IF_WRITE_4(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_OPERATION_ON); 2256 2257 /* Configure TX MAC FIFO */ 2258 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_CLEAR); 2259 SK_IF_WRITE_4(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_OPERATION_ON); 2260 } 2261 2262 /* 2263 * Note that to properly initialize any part of the GEnesis chip, 2264 * you first have to take it out of reset mode. 2265 */ 2266 static void 2267 sk_init(void *xsc) 2268 { 2269 struct sk_if_softc *sc_if = xsc; 2270 struct sk_softc *sc = sc_if->sk_softc; 2271 struct ifnet *ifp = &sc_if->arpcom.ac_if; 2272 struct mii_data *mii = device_get_softc(sc_if->sk_miibus); 2273 uint16_t reg; 2274 2275 crit_enter(); 2276 2277 /* Cancel pending I/O and free all RX/TX buffers. */ 2278 sk_stop(sc_if); 2279 2280 if (sc->sk_type == SK_GENESIS) { 2281 /* Configure LINK_SYNC LED */ 2282 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_ON); 2283 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, 2284 SK_LINKLED_LINKSYNC_ON); 2285 2286 /* Configure RX LED */ 2287 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, 2288 SK_RXLEDCTL_COUNTER_START); 2289 2290 /* Configure TX LED */ 2291 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, 2292 SK_TXLEDCTL_COUNTER_START); 2293 } 2294 2295 /* Configure I2C registers */ 2296 2297 /* Configure XMAC(s) */ 2298 switch (sc->sk_type) { 2299 case SK_GENESIS: 2300 sk_init_xmac(sc_if); 2301 break; 2302 case SK_YUKON: 2303 sk_init_yukon(sc_if); 2304 break; 2305 } 2306 mii_mediachg(mii); 2307 2308 if (sc->sk_type == SK_GENESIS) { 2309 /* Configure MAC FIFOs */ 2310 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_UNRESET); 2311 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_END, SK_FIFO_END); 2312 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_ON); 2313 2314 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_UNRESET); 2315 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_END, SK_FIFO_END); 2316 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_ON); 2317 } 2318 2319 /* Configure transmit arbiter(s) */ 2320 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, 2321 SK_TXARCTL_ON | SK_TXARCTL_FSYNC_ON); 2322 2323 /* Configure RAMbuffers */ 2324 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_UNRESET); 2325 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_START, sc_if->sk_rx_ramstart); 2326 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_WR_PTR, sc_if->sk_rx_ramstart); 2327 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_RD_PTR, sc_if->sk_rx_ramstart); 2328 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_END, sc_if->sk_rx_ramend); 2329 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_ON); 2330 2331 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_UNRESET); 2332 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_STORENFWD_ON); 2333 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_START, sc_if->sk_tx_ramstart); 2334 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_WR_PTR, sc_if->sk_tx_ramstart); 2335 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_RD_PTR, sc_if->sk_tx_ramstart); 2336 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_END, sc_if->sk_tx_ramend); 2337 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_ON); 2338 2339 /* Configure BMUs */ 2340 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_ONLINE); 2341 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_LO, 2342 vtophys(&sc_if->sk_rdata->sk_rx_ring[0])); 2343 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_HI, 0); 2344 2345 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_ONLINE); 2346 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_LO, 2347 vtophys(&sc_if->sk_rdata->sk_tx_ring[0])); 2348 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_HI, 0); 2349 2350 /* Init descriptors */ 2351 if (sk_init_rx_ring(sc_if) == ENOBUFS) { 2352 printf("sk%d: initialization failed: no " 2353 "memory for rx buffers\n", sc_if->sk_unit); 2354 sk_stop(sc_if); 2355 crit_exit(); 2356 return; 2357 } 2358 sk_init_tx_ring(sc_if); 2359 2360 /* Configure interrupt handling */ 2361 CSR_READ_4(sc, SK_ISSR); 2362 if (sc_if->sk_port == SK_PORT_A) 2363 sc->sk_intrmask |= SK_INTRS1; 2364 else 2365 sc->sk_intrmask |= SK_INTRS2; 2366 2367 sc->sk_intrmask |= SK_ISR_EXTERNAL_REG; 2368 2369 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2370 2371 /* Start BMUs. */ 2372 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_RX_START); 2373 2374 switch(sc->sk_type) { 2375 case SK_GENESIS: 2376 /* Enable XMACs TX and RX state machines */ 2377 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_IGNPAUSE); 2378 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, 2379 XM_MMUCMD_TX_ENB | XM_MMUCMD_RX_ENB); 2380 break; 2381 case SK_YUKON: 2382 reg = SK_YU_READ_2(sc_if, YUKON_GPCR); 2383 reg |= YU_GPCR_TXEN | YU_GPCR_RXEN; 2384 reg &= ~(YU_GPCR_SPEED_EN | YU_GPCR_DPLX_EN); 2385 SK_YU_WRITE_2(sc_if, YUKON_GPCR, reg); 2386 } 2387 2388 ifp->if_flags |= IFF_RUNNING; 2389 ifp->if_flags &= ~IFF_OACTIVE; 2390 2391 crit_exit(); 2392 } 2393 2394 static void 2395 sk_stop(struct sk_if_softc *sc_if) 2396 { 2397 int i; 2398 struct sk_softc *sc = sc_if->sk_softc; 2399 struct ifnet *ifp = &sc_if->arpcom.ac_if; 2400 2401 callout_stop(&sc_if->sk_tick_timer); 2402 2403 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2404 uint32_t val; 2405 2406 /* Put PHY back into reset. */ 2407 val = sk_win_read_4(sc, SK_GPIO); 2408 if (sc_if->sk_port == SK_PORT_A) { 2409 val |= SK_GPIO_DIR0; 2410 val &= ~SK_GPIO_DAT0; 2411 } else { 2412 val |= SK_GPIO_DIR2; 2413 val &= ~SK_GPIO_DAT2; 2414 } 2415 sk_win_write_4(sc, SK_GPIO, val); 2416 } 2417 2418 /* Turn off various components of this interface. */ 2419 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 2420 switch (sc->sk_type) { 2421 case SK_GENESIS: 2422 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_RESET); 2423 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_RESET); 2424 break; 2425 case SK_YUKON: 2426 SK_IF_WRITE_1(sc_if,0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_SET); 2427 SK_IF_WRITE_1(sc_if,0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_SET); 2428 break; 2429 } 2430 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_OFFLINE); 2431 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_RESET | SK_RBCTL_OFF); 2432 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_OFFLINE); 2433 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, 2434 SK_RBCTL_RESET | SK_RBCTL_OFF); 2435 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_OFF); 2436 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2437 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2438 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_OFF); 2439 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_OFF); 2440 2441 /* Disable interrupts */ 2442 if (sc_if->sk_port == SK_PORT_A) 2443 sc->sk_intrmask &= ~SK_INTRS1; 2444 else 2445 sc->sk_intrmask &= ~SK_INTRS2; 2446 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2447 2448 SK_XM_READ_2(sc_if, XM_ISR); 2449 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 2450 2451 /* Free RX and TX mbufs still in the queues. */ 2452 for (i = 0; i < SK_RX_RING_CNT; i++) { 2453 if (sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf != NULL) { 2454 m_freem(sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf); 2455 sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL; 2456 } 2457 } 2458 2459 for (i = 0; i < SK_TX_RING_CNT; i++) { 2460 if (sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf != NULL) { 2461 m_freem(sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf); 2462 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL; 2463 } 2464 } 2465 2466 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 2467 } 2468