1 /* 2 * Copyright (c) 1997, 1998, 1999, 2000 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $OpenBSD: if_sk.c,v 1.33 2003/08/12 05:23:06 nate Exp $ 33 * $FreeBSD: src/sys/pci/if_sk.c,v 1.19.2.9 2003/03/05 18:42:34 njl Exp $ 34 * $DragonFly: src/sys/dev/netif/sk/if_sk.c,v 1.44 2006/08/06 12:49:06 swildner Exp $ 35 */ 36 37 /* 38 * Copyright (c) 2003 Nathan L. Binkert <binkertn@umich.edu> 39 * 40 * Permission to use, copy, modify, and distribute this software for any 41 * purpose with or without fee is hereby granted, provided that the above 42 * copyright notice and this permission notice appear in all copies. 43 * 44 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 45 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 46 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 47 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 48 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 49 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 50 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 51 */ 52 53 /* 54 * SysKonnect SK-NET gigabit ethernet driver for FreeBSD. Supports 55 * the SK-984x series adapters, both single port and dual port. 56 * References: 57 * The XaQti XMAC II datasheet, 58 * http://www.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 59 * The SysKonnect GEnesis manual, http://www.syskonnect.com 60 * 61 * Note: XaQti has been aquired by Vitesse, and Vitesse does not have the 62 * XMAC II datasheet online. I have put my copy at people.freebsd.org as a 63 * convenience to others until Vitesse corrects this problem: 64 * 65 * http://people.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 66 * 67 * Written by Bill Paul <wpaul@ee.columbia.edu> 68 * Department of Electrical Engineering 69 * Columbia University, New York City 70 */ 71 72 /* 73 * The SysKonnect gigabit ethernet adapters consist of two main 74 * components: the SysKonnect GEnesis controller chip and the XaQti Corp. 75 * XMAC II gigabit ethernet MAC. The XMAC provides all of the MAC 76 * components and a PHY while the GEnesis controller provides a PCI 77 * interface with DMA support. Each card may have between 512K and 78 * 2MB of SRAM on board depending on the configuration. 79 * 80 * The SysKonnect GEnesis controller can have either one or two XMAC 81 * chips connected to it, allowing single or dual port NIC configurations. 82 * SysKonnect has the distinction of being the only vendor on the market 83 * with a dual port gigabit ethernet NIC. The GEnesis provides dual FIFOs, 84 * dual DMA queues, packet/MAC/transmit arbiters and direct access to the 85 * XMAC registers. This driver takes advantage of these features to allow 86 * both XMACs to operate as independent interfaces. 87 */ 88 89 #include <sys/param.h> 90 #include <sys/systm.h> 91 #include <sys/sockio.h> 92 #include <sys/mbuf.h> 93 #include <sys/malloc.h> 94 #include <sys/kernel.h> 95 #include <sys/socket.h> 96 #include <sys/queue.h> 97 #include <sys/serialize.h> 98 #include <sys/thread2.h> 99 100 #include <net/if.h> 101 #include <net/ifq_var.h> 102 #include <net/if_arp.h> 103 #include <net/ethernet.h> 104 #include <net/if_dl.h> 105 #include <net/if_media.h> 106 107 #include <net/bpf.h> 108 109 #include <vm/vm.h> /* for vtophys */ 110 #include <vm/pmap.h> /* for vtophys */ 111 #include <machine/bus.h> 112 #include <machine/resource.h> 113 #include <sys/bus.h> 114 #include <sys/rman.h> 115 116 #include <dev/netif/mii_layer/mii.h> 117 #include <dev/netif/mii_layer/miivar.h> 118 #include <dev/netif/mii_layer/brgphyreg.h> 119 120 #include <bus/pci/pcireg.h> 121 #include <bus/pci/pcivar.h> 122 123 #if 0 124 #define SK_USEIOSPACE 125 #endif 126 127 #include "if_skreg.h" 128 #include "xmaciireg.h" 129 #include "yukonreg.h" 130 131 /* "controller miibus0" required. See GENERIC if you get errors here. */ 132 #include "miibus_if.h" 133 134 static struct sk_type sk_devs[] = { 135 { VENDORID_SK, DEVICEID_SK_V1, 136 "SysKonnect Gigabit Ethernet (V1.0)" }, 137 { VENDORID_SK, DEVICEID_SK_V2, 138 "SysKonnect Gigabit Ethernet (V2.0)" }, 139 { VENDORID_MARVELL, DEVICEID_SK_V2, 140 "Marvell Gigabit Ethernet" }, 141 { VENDORID_3COM, DEVICEID_3COM_3C940, 142 "3Com 3C940 Gigabit Ethernet" }, 143 { VENDORID_LINKSYS, DEVICEID_LINKSYS_EG1032, 144 "Linksys EG1032 Gigabit Ethernet" }, 145 { VENDORID_DLINK, DEVICEID_DLINK_DGE530T, 146 "D-Link DGE-530T Gigabit Ethernet" }, 147 { 0, 0, NULL } 148 }; 149 150 static int skc_probe(device_t); 151 static int skc_attach(device_t); 152 static int skc_detach(device_t); 153 static void skc_shutdown(device_t); 154 static int sk_probe(device_t); 155 static int sk_attach(device_t); 156 static int sk_detach(device_t); 157 static void sk_tick(void *); 158 static void sk_intr(void *); 159 static void sk_intr_bcom(struct sk_if_softc *); 160 static void sk_intr_xmac(struct sk_if_softc *); 161 static void sk_intr_yukon(struct sk_if_softc *); 162 static void sk_rxeof(struct sk_if_softc *); 163 static void sk_txeof(struct sk_if_softc *); 164 static int sk_encap(struct sk_if_softc *, struct mbuf *, uint32_t *); 165 static void sk_start(struct ifnet *); 166 static int sk_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *); 167 static void sk_init(void *); 168 static void sk_init_xmac(struct sk_if_softc *); 169 static void sk_init_yukon(struct sk_if_softc *); 170 static void sk_stop(struct sk_if_softc *); 171 static void sk_watchdog(struct ifnet *); 172 static int sk_ifmedia_upd(struct ifnet *); 173 static void sk_ifmedia_sts(struct ifnet *, struct ifmediareq *); 174 static void sk_reset(struct sk_softc *); 175 static int sk_newbuf(struct sk_if_softc *, struct sk_chain *, 176 struct mbuf *); 177 static int sk_alloc_jumbo_mem(struct sk_if_softc *); 178 static struct sk_jslot 179 *sk_jalloc(struct sk_if_softc *); 180 static void sk_jfree(void *); 181 static void sk_jref(void *); 182 static int sk_init_rx_ring(struct sk_if_softc *); 183 static void sk_init_tx_ring(struct sk_if_softc *); 184 static uint32_t sk_win_read_4(struct sk_softc *, int); 185 static uint16_t sk_win_read_2(struct sk_softc *, int); 186 static uint8_t sk_win_read_1(struct sk_softc *, int); 187 static void sk_win_write_4(struct sk_softc *, int, uint32_t); 188 static void sk_win_write_2(struct sk_softc *, int, uint32_t); 189 static void sk_win_write_1(struct sk_softc *, int, uint32_t); 190 static uint8_t sk_vpd_readbyte(struct sk_softc *, int); 191 static void sk_vpd_read_res(struct sk_softc *, struct vpd_res *, int); 192 static void sk_vpd_read(struct sk_softc *); 193 194 static int sk_miibus_readreg(device_t, int, int); 195 static int sk_miibus_writereg(device_t, int, int, int); 196 static void sk_miibus_statchg(device_t); 197 198 static int sk_xmac_miibus_readreg(struct sk_if_softc *, int, int); 199 static int sk_xmac_miibus_writereg(struct sk_if_softc *, int, int, int); 200 static void sk_xmac_miibus_statchg(struct sk_if_softc *); 201 202 static int sk_marv_miibus_readreg(struct sk_if_softc *, int, int); 203 static int sk_marv_miibus_writereg(struct sk_if_softc *, int, int, int); 204 static void sk_marv_miibus_statchg(struct sk_if_softc *); 205 206 static void sk_setfilt(struct sk_if_softc *, caddr_t, int); 207 static void sk_setmulti(struct sk_if_softc *); 208 static void sk_setpromisc(struct sk_if_softc *); 209 210 #ifdef SK_USEIOSPACE 211 #define SK_RES SYS_RES_IOPORT 212 #define SK_RID SK_PCI_LOIO 213 #else 214 #define SK_RES SYS_RES_MEMORY 215 #define SK_RID SK_PCI_LOMEM 216 #endif 217 218 /* 219 * Note that we have newbus methods for both the GEnesis controller 220 * itself and the XMAC(s). The XMACs are children of the GEnesis, and 221 * the miibus code is a child of the XMACs. We need to do it this way 222 * so that the miibus drivers can access the PHY registers on the 223 * right PHY. It's not quite what I had in mind, but it's the only 224 * design that achieves the desired effect. 225 */ 226 static device_method_t skc_methods[] = { 227 /* Device interface */ 228 DEVMETHOD(device_probe, skc_probe), 229 DEVMETHOD(device_attach, skc_attach), 230 DEVMETHOD(device_detach, skc_detach), 231 DEVMETHOD(device_shutdown, skc_shutdown), 232 233 /* bus interface */ 234 DEVMETHOD(bus_print_child, bus_generic_print_child), 235 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 236 237 { 0, 0 } 238 }; 239 240 static DEFINE_CLASS_0(skc, skc_driver, skc_methods, sizeof(struct sk_softc)); 241 static devclass_t skc_devclass; 242 243 static device_method_t sk_methods[] = { 244 /* Device interface */ 245 DEVMETHOD(device_probe, sk_probe), 246 DEVMETHOD(device_attach, sk_attach), 247 DEVMETHOD(device_detach, sk_detach), 248 DEVMETHOD(device_shutdown, bus_generic_shutdown), 249 250 /* bus interface */ 251 DEVMETHOD(bus_print_child, bus_generic_print_child), 252 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 253 254 /* MII interface */ 255 DEVMETHOD(miibus_readreg, sk_miibus_readreg), 256 DEVMETHOD(miibus_writereg, sk_miibus_writereg), 257 DEVMETHOD(miibus_statchg, sk_miibus_statchg), 258 259 { 0, 0 } 260 }; 261 262 static DEFINE_CLASS_0(sk, sk_driver, sk_methods, sizeof(struct sk_if_softc)); 263 static devclass_t sk_devclass; 264 static struct lwkt_serialize sk_serializer; 265 266 DECLARE_DUMMY_MODULE(if_sk); 267 DRIVER_MODULE(if_sk, pci, skc_driver, skc_devclass, 0, 0); 268 DRIVER_MODULE(if_sk, skc, sk_driver, sk_devclass, 0, 0); 269 DRIVER_MODULE(miibus, sk, miibus_driver, miibus_devclass, 0, 0); 270 271 #define SK_SETBIT(sc, reg, x) \ 272 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | x) 273 274 #define SK_CLRBIT(sc, reg, x) \ 275 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~x) 276 277 #define SK_WIN_SETBIT_4(sc, reg, x) \ 278 sk_win_write_4(sc, reg, sk_win_read_4(sc, reg) | x) 279 280 #define SK_WIN_CLRBIT_4(sc, reg, x) \ 281 sk_win_write_4(sc, reg, sk_win_read_4(sc, reg) & ~x) 282 283 #define SK_WIN_SETBIT_2(sc, reg, x) \ 284 sk_win_write_2(sc, reg, sk_win_read_2(sc, reg) | x) 285 286 #define SK_WIN_CLRBIT_2(sc, reg, x) \ 287 sk_win_write_2(sc, reg, sk_win_read_2(sc, reg) & ~x) 288 289 static uint32_t 290 sk_win_read_4(struct sk_softc *sc, int reg) 291 { 292 #ifdef SK_USEIOSPACE 293 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 294 return(CSR_READ_4(sc, SK_WIN_BASE + SK_REG(reg))); 295 #else 296 return(CSR_READ_4(sc, reg)); 297 #endif 298 } 299 300 static uint16_t 301 sk_win_read_2(struct sk_softc *sc, int reg) 302 { 303 #ifdef SK_USEIOSPACE 304 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 305 return(CSR_READ_2(sc, SK_WIN_BASE + SK_REG(reg))); 306 #else 307 return(CSR_READ_2(sc, reg)); 308 #endif 309 } 310 311 static uint8_t 312 sk_win_read_1(struct sk_softc *sc, int reg) 313 { 314 #ifdef SK_USEIOSPACE 315 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 316 return(CSR_READ_1(sc, SK_WIN_BASE + SK_REG(reg))); 317 #else 318 return(CSR_READ_1(sc, reg)); 319 #endif 320 } 321 322 static void 323 sk_win_write_4(struct sk_softc *sc, int reg, uint32_t val) 324 { 325 #ifdef SK_USEIOSPACE 326 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 327 CSR_WRITE_4(sc, SK_WIN_BASE + SK_REG(reg), val); 328 #else 329 CSR_WRITE_4(sc, reg, val); 330 #endif 331 } 332 333 static void 334 sk_win_write_2(struct sk_softc *sc, int reg, uint32_t val) 335 { 336 #ifdef SK_USEIOSPACE 337 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 338 CSR_WRITE_2(sc, SK_WIN_BASE + SK_REG(reg), val); 339 #else 340 CSR_WRITE_2(sc, reg, val); 341 #endif 342 } 343 344 static void 345 sk_win_write_1(struct sk_softc *sc, int reg, uint32_t val) 346 { 347 #ifdef SK_USEIOSPACE 348 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 349 CSR_WRITE_1(sc, SK_WIN_BASE + SK_REG(reg), val); 350 #else 351 CSR_WRITE_1(sc, reg, val); 352 #endif 353 } 354 355 /* 356 * The VPD EEPROM contains Vital Product Data, as suggested in 357 * the PCI 2.1 specification. The VPD data is separared into areas 358 * denoted by resource IDs. The SysKonnect VPD contains an ID string 359 * resource (the name of the adapter), a read-only area resource 360 * containing various key/data fields and a read/write area which 361 * can be used to store asset management information or log messages. 362 * We read the ID string and read-only into buffers attached to 363 * the controller softc structure for later use. At the moment, 364 * we only use the ID string during sk_attach(). 365 */ 366 static uint8_t 367 sk_vpd_readbyte(struct sk_softc *sc, int addr) 368 { 369 int i; 370 371 sk_win_write_2(sc, SK_PCI_REG(SK_PCI_VPD_ADDR), addr); 372 for (i = 0; i < SK_TIMEOUT; i++) { 373 DELAY(1); 374 if (sk_win_read_2(sc, 375 SK_PCI_REG(SK_PCI_VPD_ADDR)) & SK_VPD_FLAG) 376 break; 377 } 378 379 if (i == SK_TIMEOUT) 380 return(0); 381 382 return(sk_win_read_1(sc, SK_PCI_REG(SK_PCI_VPD_DATA))); 383 } 384 385 static void 386 sk_vpd_read_res(struct sk_softc *sc, struct vpd_res *res, int addr) 387 { 388 int i; 389 uint8_t *ptr; 390 391 ptr = (uint8_t *)res; 392 for (i = 0; i < sizeof(struct vpd_res); i++) 393 ptr[i] = sk_vpd_readbyte(sc, i + addr); 394 } 395 396 static void 397 sk_vpd_read(struct sk_softc *sc) 398 { 399 struct vpd_res res; 400 int i, pos = 0; 401 402 if (sc->sk_vpd_prodname != NULL) 403 free(sc->sk_vpd_prodname, M_DEVBUF); 404 if (sc->sk_vpd_readonly != NULL) 405 free(sc->sk_vpd_readonly, M_DEVBUF); 406 sc->sk_vpd_prodname = NULL; 407 sc->sk_vpd_readonly = NULL; 408 409 sk_vpd_read_res(sc, &res, pos); 410 411 if (res.vr_id != VPD_RES_ID) { 412 printf("skc%d: bad VPD resource id: expected %x got %x\n", 413 sc->sk_unit, VPD_RES_ID, res.vr_id); 414 return; 415 } 416 417 pos += sizeof(res); 418 sc->sk_vpd_prodname = malloc(res.vr_len + 1, M_DEVBUF, M_INTWAIT); 419 for (i = 0; i < res.vr_len; i++) 420 sc->sk_vpd_prodname[i] = sk_vpd_readbyte(sc, i + pos); 421 sc->sk_vpd_prodname[i] = '\0'; 422 pos += i; 423 424 sk_vpd_read_res(sc, &res, pos); 425 426 if (res.vr_id != VPD_RES_READ) { 427 printf("skc%d: bad VPD resource id: expected %x got %x\n", 428 sc->sk_unit, VPD_RES_READ, res.vr_id); 429 return; 430 } 431 432 pos += sizeof(res); 433 sc->sk_vpd_readonly = malloc(res.vr_len, M_DEVBUF, M_INTWAIT); 434 for (i = 0; i < res.vr_len + 1; i++) 435 sc->sk_vpd_readonly[i] = sk_vpd_readbyte(sc, i + pos); 436 } 437 438 static int 439 sk_miibus_readreg(device_t dev, int phy, int reg) 440 { 441 struct sk_if_softc *sc_if = device_get_softc(dev); 442 443 switch(sc_if->sk_softc->sk_type) { 444 case SK_GENESIS: 445 return(sk_xmac_miibus_readreg(sc_if, phy, reg)); 446 case SK_YUKON: 447 return(sk_marv_miibus_readreg(sc_if, phy, reg)); 448 } 449 450 return(0); 451 } 452 453 static int 454 sk_miibus_writereg(device_t dev, int phy, int reg, int val) 455 { 456 struct sk_if_softc *sc_if = device_get_softc(dev); 457 458 switch(sc_if->sk_softc->sk_type) { 459 case SK_GENESIS: 460 return(sk_xmac_miibus_writereg(sc_if, phy, reg, val)); 461 case SK_YUKON: 462 return(sk_marv_miibus_writereg(sc_if, phy, reg, val)); 463 } 464 465 return(0); 466 } 467 468 static void 469 sk_miibus_statchg(device_t dev) 470 { 471 struct sk_if_softc *sc_if = device_get_softc(dev); 472 473 switch(sc_if->sk_softc->sk_type) { 474 case SK_GENESIS: 475 sk_xmac_miibus_statchg(sc_if); 476 break; 477 case SK_YUKON: 478 sk_marv_miibus_statchg(sc_if); 479 break; 480 } 481 } 482 483 static int 484 sk_xmac_miibus_readreg(struct sk_if_softc *sc_if, int phy, int reg) 485 { 486 int i; 487 488 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC && phy != 0) 489 return(0); 490 491 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8)); 492 SK_XM_READ_2(sc_if, XM_PHY_DATA); 493 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) { 494 for (i = 0; i < SK_TIMEOUT; i++) { 495 DELAY(1); 496 if (SK_XM_READ_2(sc_if, XM_MMUCMD) & 497 XM_MMUCMD_PHYDATARDY) 498 break; 499 } 500 501 if (i == SK_TIMEOUT) { 502 printf("sk%d: phy failed to come ready\n", 503 sc_if->sk_unit); 504 return(0); 505 } 506 } 507 DELAY(1); 508 return(SK_XM_READ_2(sc_if, XM_PHY_DATA)); 509 } 510 511 static int 512 sk_xmac_miibus_writereg(struct sk_if_softc *sc_if, int phy, int reg, int val) 513 { 514 int i; 515 516 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8)); 517 for (i = 0; i < SK_TIMEOUT; i++) { 518 if ((SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY) == 0) 519 break; 520 } 521 522 if (i == SK_TIMEOUT) { 523 printf("sk%d: phy failed to come ready\n", sc_if->sk_unit); 524 return(ETIMEDOUT); 525 } 526 527 SK_XM_WRITE_2(sc_if, XM_PHY_DATA, val); 528 for (i = 0; i < SK_TIMEOUT; i++) { 529 DELAY(1); 530 if ((SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY) == 0) 531 break; 532 } 533 534 if (i == SK_TIMEOUT) 535 printf("sk%d: phy write timed out\n", sc_if->sk_unit); 536 537 return(0); 538 } 539 540 static void 541 sk_xmac_miibus_statchg(struct sk_if_softc *sc_if) 542 { 543 struct mii_data *mii; 544 545 mii = device_get_softc(sc_if->sk_miibus); 546 547 /* 548 * If this is a GMII PHY, manually set the XMAC's 549 * duplex mode accordingly. 550 */ 551 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) { 552 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) 553 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX); 554 else 555 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX); 556 } 557 } 558 559 static int 560 sk_marv_miibus_readreg(struct sk_if_softc *sc_if, int phy, int reg) 561 { 562 uint16_t val; 563 int i; 564 565 if (phy != 0 || 566 (sc_if->sk_phytype != SK_PHYTYPE_MARV_COPPER && 567 sc_if->sk_phytype != SK_PHYTYPE_MARV_FIBER)) { 568 return(0); 569 } 570 571 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 572 YU_SMICR_REGAD(reg) | YU_SMICR_OP_READ); 573 574 for (i = 0; i < SK_TIMEOUT; i++) { 575 DELAY(1); 576 val = SK_YU_READ_2(sc_if, YUKON_SMICR); 577 if (val & YU_SMICR_READ_VALID) 578 break; 579 } 580 581 if (i == SK_TIMEOUT) { 582 printf("sk%d: phy failed to come ready\n", 583 sc_if->sk_unit); 584 return(0); 585 } 586 587 val = SK_YU_READ_2(sc_if, YUKON_SMIDR); 588 589 return(val); 590 } 591 592 static int 593 sk_marv_miibus_writereg(struct sk_if_softc *sc_if, int phy, int reg, int val) 594 { 595 int i; 596 597 SK_YU_WRITE_2(sc_if, YUKON_SMIDR, val); 598 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 599 YU_SMICR_REGAD(reg) | YU_SMICR_OP_WRITE); 600 601 for (i = 0; i < SK_TIMEOUT; i++) { 602 DELAY(1); 603 if (SK_YU_READ_2(sc_if, YUKON_SMICR) & YU_SMICR_BUSY) 604 break; 605 } 606 607 return(0); 608 } 609 610 static void 611 sk_marv_miibus_statchg(struct sk_if_softc *sc_if) 612 { 613 } 614 615 #define HASH_BITS 6 616 617 static void 618 sk_setfilt(struct sk_if_softc *sc_if, caddr_t addr, int slot) 619 { 620 int base; 621 622 base = XM_RXFILT_ENTRY(slot); 623 624 SK_XM_WRITE_2(sc_if, base, *(uint16_t *)(&addr[0])); 625 SK_XM_WRITE_2(sc_if, base + 2, *(uint16_t *)(&addr[2])); 626 SK_XM_WRITE_2(sc_if, base + 4, *(uint16_t *)(&addr[4])); 627 } 628 629 static void 630 sk_setmulti(struct sk_if_softc *sc_if) 631 { 632 struct sk_softc *sc = sc_if->sk_softc; 633 struct ifnet *ifp = &sc_if->arpcom.ac_if; 634 uint32_t hashes[2] = { 0, 0 }; 635 int h, i; 636 struct ifmultiaddr *ifma; 637 uint8_t dummy[] = { 0, 0, 0, 0, 0 ,0 }; 638 639 /* First, zot all the existing filters. */ 640 switch(sc->sk_type) { 641 case SK_GENESIS: 642 for (i = 1; i < XM_RXFILT_MAX; i++) 643 sk_setfilt(sc_if, (caddr_t)&dummy, i); 644 645 SK_XM_WRITE_4(sc_if, XM_MAR0, 0); 646 SK_XM_WRITE_4(sc_if, XM_MAR2, 0); 647 break; 648 case SK_YUKON: 649 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, 0); 650 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, 0); 651 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, 0); 652 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, 0); 653 break; 654 } 655 656 /* Now program new ones. */ 657 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 658 hashes[0] = 0xFFFFFFFF; 659 hashes[1] = 0xFFFFFFFF; 660 } else { 661 i = 1; 662 /* First find the tail of the list. */ 663 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 664 if (ifma->ifma_link.le_next == NULL) 665 break; 666 } 667 /* Now traverse the list backwards. */ 668 for (; ifma != NULL && ifma != (void *)&ifp->if_multiaddrs; 669 ifma = (struct ifmultiaddr *)ifma->ifma_link.le_prev) { 670 if (ifma->ifma_addr->sa_family != AF_LINK) 671 continue; 672 /* 673 * Program the first XM_RXFILT_MAX multicast groups 674 * into the perfect filter. For all others, 675 * use the hash table. 676 */ 677 if (sc->sk_type == SK_GENESIS && i < XM_RXFILT_MAX) { 678 sk_setfilt(sc_if, 679 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), i); 680 i++; 681 continue; 682 } 683 684 switch(sc->sk_type) { 685 case SK_GENESIS: 686 h = ~ether_crc32_le(LLADDR((struct sockaddr_dl *) 687 ifma->ifma_addr), ETHER_ADDR_LEN) & 688 ((1 << HASH_BITS) -1 ); 689 if (h < 32) 690 hashes[0] |= (1 << h); 691 else 692 hashes[1] |= (1 << (h - 32)); 693 break; 694 695 case SK_YUKON: 696 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 697 ifma->ifma_addr), ETHER_ADDR_LEN) & 698 ((1 << HASH_BITS) -1 ); 699 if (h < 32) 700 hashes[0] |= (1 << h); 701 else 702 hashes[1] |= (1 << (h - 32)); 703 break; 704 } 705 } 706 } 707 708 switch(sc->sk_type) { 709 case SK_GENESIS: 710 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_HASH| 711 XM_MODE_RX_USE_PERFECT); 712 SK_XM_WRITE_4(sc_if, XM_MAR0, hashes[0]); 713 SK_XM_WRITE_4(sc_if, XM_MAR2, hashes[1]); 714 break; 715 case SK_YUKON: 716 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, hashes[0] & 0xffff); 717 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, (hashes[0] >> 16) & 0xffff); 718 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, hashes[1] & 0xffff); 719 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, (hashes[1] >> 16) & 0xffff); 720 break; 721 } 722 } 723 724 static void 725 sk_setpromisc(struct sk_if_softc *sc_if) 726 { 727 struct sk_softc *sc = sc_if->sk_softc; 728 struct ifnet *ifp = &sc_if->arpcom.ac_if; 729 730 switch(sc->sk_type) { 731 case SK_GENESIS: 732 if (ifp->if_flags & IFF_PROMISC) { 733 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 734 } else { 735 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 736 } 737 break; 738 case SK_YUKON: 739 if (ifp->if_flags & IFF_PROMISC) { 740 SK_YU_CLRBIT_2(sc_if, YUKON_RCR, 741 YU_RCR_UFLEN | YU_RCR_MUFLEN); 742 } else { 743 SK_YU_SETBIT_2(sc_if, YUKON_RCR, 744 YU_RCR_UFLEN | YU_RCR_MUFLEN); 745 } 746 break; 747 } 748 } 749 750 static int 751 sk_init_rx_ring(struct sk_if_softc *sc_if) 752 { 753 struct sk_chain_data *cd = &sc_if->sk_cdata; 754 struct sk_ring_data *rd = sc_if->sk_rdata; 755 int i; 756 757 bzero(rd->sk_rx_ring, sizeof(struct sk_rx_desc) * SK_RX_RING_CNT); 758 759 for (i = 0; i < SK_RX_RING_CNT; i++) { 760 cd->sk_rx_chain[i].sk_desc = &rd->sk_rx_ring[i]; 761 if (sk_newbuf(sc_if, &cd->sk_rx_chain[i], NULL) == ENOBUFS) 762 return(ENOBUFS); 763 if (i == (SK_RX_RING_CNT - 1)) { 764 cd->sk_rx_chain[i].sk_next = 765 &cd->sk_rx_chain[0]; 766 rd->sk_rx_ring[i].sk_next = 767 vtophys(&rd->sk_rx_ring[0]); 768 } else { 769 cd->sk_rx_chain[i].sk_next = 770 &cd->sk_rx_chain[i + 1]; 771 rd->sk_rx_ring[i].sk_next = 772 vtophys(&rd->sk_rx_ring[i + 1]); 773 } 774 } 775 776 sc_if->sk_cdata.sk_rx_prod = 0; 777 sc_if->sk_cdata.sk_rx_cons = 0; 778 779 return(0); 780 } 781 782 static void 783 sk_init_tx_ring(struct sk_if_softc *sc_if) 784 { 785 struct sk_chain_data *cd = &sc_if->sk_cdata; 786 struct sk_ring_data *rd = sc_if->sk_rdata; 787 int i, nexti; 788 789 bzero(sc_if->sk_rdata->sk_tx_ring, 790 sizeof(struct sk_tx_desc) * SK_TX_RING_CNT); 791 792 for (i = 0; i < SK_TX_RING_CNT; i++) { 793 nexti = (i == (SK_TX_RING_CNT - 1)) ? 0 : i + 1; 794 cd->sk_tx_chain[i].sk_desc = &rd->sk_tx_ring[i]; 795 cd->sk_tx_chain[i].sk_next = &cd->sk_tx_chain[nexti]; 796 rd->sk_tx_ring[i].sk_next = vtophys(&rd->sk_tx_ring[nexti]); 797 } 798 799 sc_if->sk_cdata.sk_tx_prod = 0; 800 sc_if->sk_cdata.sk_tx_cons = 0; 801 sc_if->sk_cdata.sk_tx_cnt = 0; 802 } 803 804 static int 805 sk_newbuf(struct sk_if_softc *sc_if, struct sk_chain *c, struct mbuf *m) 806 { 807 struct mbuf *m_new = NULL; 808 struct sk_rx_desc *r; 809 struct sk_jslot *buf; 810 811 if (m == NULL) { 812 MGETHDR(m_new, MB_DONTWAIT, MT_DATA); 813 if (m_new == NULL) 814 return(ENOBUFS); 815 816 /* Allocate the jumbo buffer */ 817 buf = sk_jalloc(sc_if); 818 if (buf == NULL) { 819 m_freem(m_new); 820 #ifdef SK_VERBOSE 821 printf("sk%d: jumbo allocation failed " 822 "-- packet dropped!\n", sc_if->sk_unit); 823 #endif 824 return(ENOBUFS); 825 } 826 827 /* Attach the buffer to the mbuf */ 828 m_new->m_ext.ext_arg = buf; 829 m_new->m_ext.ext_buf = buf->sk_buf; 830 m_new->m_ext.ext_free = sk_jfree; 831 m_new->m_ext.ext_ref = sk_jref; 832 m_new->m_ext.ext_size = SK_JUMBO_FRAMELEN; 833 834 m_new->m_data = m_new->m_ext.ext_buf; 835 m_new->m_flags |= M_EXT; 836 m_new->m_len = m_new->m_pkthdr.len = m_new->m_ext.ext_size; 837 } else { 838 /* 839 * We're re-using a previously allocated mbuf; 840 * be sure to re-init pointers and lengths to 841 * default values. 842 */ 843 m_new = m; 844 m_new->m_len = m_new->m_pkthdr.len = SK_JLEN; 845 m_new->m_data = m_new->m_ext.ext_buf; 846 } 847 848 /* 849 * Adjust alignment so packet payload begins on a 850 * longword boundary. Mandatory for Alpha, useful on 851 * x86 too. 852 */ 853 m_adj(m_new, ETHER_ALIGN); 854 855 r = c->sk_desc; 856 c->sk_mbuf = m_new; 857 r->sk_data_lo = vtophys(mtod(m_new, caddr_t)); 858 r->sk_ctl = m_new->m_len | SK_RXSTAT; 859 860 return(0); 861 } 862 863 /* 864 * Allocate jumbo buffer storage. The SysKonnect adapters support 865 * "jumbograms" (9K frames), although SysKonnect doesn't currently 866 * use them in their drivers. In order for us to use them, we need 867 * large 9K receive buffers, however standard mbuf clusters are only 868 * 2048 bytes in size. Consequently, we need to allocate and manage 869 * our own jumbo buffer pool. Fortunately, this does not require an 870 * excessive amount of additional code. 871 */ 872 static int 873 sk_alloc_jumbo_mem(struct sk_if_softc *sc_if) 874 { 875 caddr_t ptr; 876 int i; 877 struct sk_jslot *entry; 878 879 /* Grab a big chunk o' storage. */ 880 sc_if->sk_cdata.sk_jumbo_buf = contigmalloc(SK_JMEM, M_DEVBUF, 881 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 882 883 if (sc_if->sk_cdata.sk_jumbo_buf == NULL) { 884 printf("sk%d: no memory for jumbo buffers!\n", sc_if->sk_unit); 885 return(ENOBUFS); 886 } 887 888 SLIST_INIT(&sc_if->sk_jfree_listhead); 889 890 /* 891 * Now divide it up into 9K pieces and save the addresses 892 * in an array. Note that we play an evil trick here by using 893 * the first few bytes in the buffer to hold the the address 894 * of the softc structure for this interface. This is because 895 * sk_jfree() needs it, but it is called by the mbuf management 896 * code which will not pass it to us explicitly. 897 */ 898 ptr = sc_if->sk_cdata.sk_jumbo_buf; 899 for (i = 0; i < SK_JSLOTS; i++) { 900 entry = &sc_if->sk_cdata.sk_jslots[i]; 901 entry->sk_sc = sc_if; 902 entry->sk_buf = ptr; 903 entry->sk_inuse = 0; 904 entry->sk_slot = i; 905 SLIST_INSERT_HEAD(&sc_if->sk_jfree_listhead, entry, jslot_link); 906 ptr += SK_JLEN; 907 } 908 909 return(0); 910 } 911 912 /* 913 * Allocate a jumbo buffer. 914 */ 915 static struct sk_jslot * 916 sk_jalloc(struct sk_if_softc *sc_if) 917 { 918 struct sk_jslot *entry; 919 920 lwkt_serialize_enter(&sc_if->sk_jslot_serializer); 921 entry = SLIST_FIRST(&sc_if->sk_jfree_listhead); 922 if (entry) { 923 SLIST_REMOVE_HEAD(&sc_if->sk_jfree_listhead, jslot_link); 924 entry->sk_inuse = 1; 925 } else { 926 #ifdef SK_VERBOSE 927 printf("sk%d: no free jumbo buffers\n", sc_if->sk_unit); 928 #endif 929 } 930 lwkt_serialize_exit(&sc_if->sk_jslot_serializer); 931 return(entry); 932 } 933 934 /* 935 * Adjust usage count on a jumbo buffer. In general this doesn't 936 * get used much because our jumbo buffers don't get passed around 937 * a lot, but it's implemented for correctness. 938 */ 939 static void 940 sk_jref(void *arg) 941 { 942 struct sk_jslot *entry = (struct sk_jslot *)arg; 943 struct sk_if_softc *sc = entry->sk_sc; 944 945 if (sc == NULL) 946 panic("sk_jref: can't find softc pointer!"); 947 948 if (&sc->sk_cdata.sk_jslots[entry->sk_slot] != entry) 949 panic("sk_jref: asked to reference buffer " 950 "that we don't manage!"); 951 if (entry->sk_inuse == 0) 952 panic("sk_jref: buffer already free!"); 953 atomic_add_int(&entry->sk_inuse, 1); 954 } 955 956 /* 957 * Release a jumbo buffer. 958 */ 959 static void 960 sk_jfree(void *arg) 961 { 962 struct sk_jslot *entry = (struct sk_jslot *)arg; 963 struct sk_if_softc *sc = entry->sk_sc; 964 965 if (sc == NULL) 966 panic("sk_jref: can't find softc pointer!"); 967 968 if (&sc->sk_cdata.sk_jslots[entry->sk_slot] != entry) 969 panic("sk_jref: asked to reference buffer " 970 "that we don't manage!"); 971 if (entry->sk_inuse == 0) 972 panic("sk_jref: buffer already free!"); 973 lwkt_serialize_enter(&sc->sk_jslot_serializer); 974 atomic_subtract_int(&entry->sk_inuse, 1); 975 if (entry->sk_inuse == 0) 976 SLIST_INSERT_HEAD(&sc->sk_jfree_listhead, entry, jslot_link); 977 lwkt_serialize_exit(&sc->sk_jslot_serializer); 978 } 979 980 /* 981 * Set media options. 982 */ 983 static int 984 sk_ifmedia_upd(struct ifnet *ifp) 985 { 986 struct sk_if_softc *sc_if = ifp->if_softc; 987 struct mii_data *mii; 988 989 mii = device_get_softc(sc_if->sk_miibus); 990 sk_init(sc_if); 991 mii_mediachg(mii); 992 993 return(0); 994 } 995 996 /* 997 * Report current media status. 998 */ 999 static void 1000 sk_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1001 { 1002 struct sk_if_softc *sc_if; 1003 struct mii_data *mii; 1004 1005 sc_if = ifp->if_softc; 1006 mii = device_get_softc(sc_if->sk_miibus); 1007 1008 mii_pollstat(mii); 1009 ifmr->ifm_active = mii->mii_media_active; 1010 ifmr->ifm_status = mii->mii_media_status; 1011 } 1012 1013 static int 1014 sk_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr) 1015 { 1016 struct sk_if_softc *sc_if = ifp->if_softc; 1017 struct ifreq *ifr = (struct ifreq *)data; 1018 struct mii_data *mii; 1019 int error = 0; 1020 1021 crit_enter(); 1022 1023 switch(command) { 1024 case SIOCSIFMTU: 1025 if (ifr->ifr_mtu > SK_JUMBO_MTU) 1026 error = EINVAL; 1027 else { 1028 ifp->if_mtu = ifr->ifr_mtu; 1029 ifp->if_flags &= ~IFF_RUNNING; 1030 sk_init(sc_if); 1031 } 1032 break; 1033 case SIOCSIFFLAGS: 1034 if (ifp->if_flags & IFF_UP) { 1035 if (ifp->if_flags & IFF_RUNNING) { 1036 if ((ifp->if_flags ^ sc_if->sk_if_flags) 1037 & IFF_PROMISC) { 1038 sk_setpromisc(sc_if); 1039 sk_setmulti(sc_if); 1040 } 1041 } else 1042 sk_init(sc_if); 1043 } else { 1044 if (ifp->if_flags & IFF_RUNNING) 1045 sk_stop(sc_if); 1046 } 1047 sc_if->sk_if_flags = ifp->if_flags; 1048 error = 0; 1049 break; 1050 case SIOCADDMULTI: 1051 case SIOCDELMULTI: 1052 sk_setmulti(sc_if); 1053 error = 0; 1054 break; 1055 case SIOCGIFMEDIA: 1056 case SIOCSIFMEDIA: 1057 mii = device_get_softc(sc_if->sk_miibus); 1058 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1059 break; 1060 default: 1061 error = ether_ioctl(ifp, command, data); 1062 break; 1063 } 1064 1065 crit_exit(); 1066 1067 return(error); 1068 } 1069 1070 /* 1071 * Probe for a SysKonnect GEnesis chip. Check the PCI vendor and device 1072 * IDs against our list and return a device name if we find a match. 1073 */ 1074 static int 1075 skc_probe(device_t dev) 1076 { 1077 struct sk_type *t; 1078 uint16_t vendor, product; 1079 1080 lwkt_serialize_init(&sk_serializer); 1081 vendor = pci_get_vendor(dev); 1082 product = pci_get_device(dev); 1083 1084 for (t = sk_devs; t->sk_name != NULL; t++) { 1085 if (vendor == t->sk_vid && product == t->sk_did) { 1086 device_set_desc(dev, t->sk_name); 1087 return(0); 1088 } 1089 } 1090 1091 return(ENXIO); 1092 } 1093 1094 /* 1095 * Force the GEnesis into reset, then bring it out of reset. 1096 */ 1097 static void 1098 sk_reset(struct sk_softc *sc) 1099 { 1100 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_RESET); 1101 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_RESET); 1102 if (sc->sk_type == SK_YUKON) 1103 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_SET); 1104 1105 DELAY(1000); 1106 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_UNRESET); 1107 DELAY(2); 1108 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_UNRESET); 1109 if (sc->sk_type == SK_YUKON) 1110 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_CLEAR); 1111 1112 if (sc->sk_type == SK_GENESIS) { 1113 /* Configure packet arbiter */ 1114 sk_win_write_2(sc, SK_PKTARB_CTL, SK_PKTARBCTL_UNRESET); 1115 sk_win_write_2(sc, SK_RXPA1_TINIT, SK_PKTARB_TIMEOUT); 1116 sk_win_write_2(sc, SK_TXPA1_TINIT, SK_PKTARB_TIMEOUT); 1117 sk_win_write_2(sc, SK_RXPA2_TINIT, SK_PKTARB_TIMEOUT); 1118 sk_win_write_2(sc, SK_TXPA2_TINIT, SK_PKTARB_TIMEOUT); 1119 } 1120 1121 /* Enable RAM interface */ 1122 sk_win_write_4(sc, SK_RAMCTL, SK_RAMCTL_UNRESET); 1123 1124 /* 1125 * Configure interrupt moderation. The moderation timer 1126 * defers interrupts specified in the interrupt moderation 1127 * timer mask based on the timeout specified in the interrupt 1128 * moderation timer init register. Each bit in the timer 1129 * register represents 18.825ns, so to specify a timeout in 1130 * microseconds, we have to multiply by 54. 1131 */ 1132 sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(200)); 1133 sk_win_write_4(sc, SK_IMMR, SK_ISR_TX1_S_EOF|SK_ISR_TX2_S_EOF| 1134 SK_ISR_RX1_EOF|SK_ISR_RX2_EOF); 1135 sk_win_write_1(sc, SK_IMTIMERCTL, SK_IMCTL_START); 1136 } 1137 1138 static int 1139 sk_probe(device_t dev) 1140 { 1141 struct sk_softc *sc = device_get_softc(device_get_parent(dev)); 1142 1143 /* 1144 * Not much to do here. We always know there will be 1145 * at least one XMAC present, and if there are two, 1146 * skc_attach() will create a second device instance 1147 * for us. 1148 */ 1149 switch (sc->sk_type) { 1150 case SK_GENESIS: 1151 device_set_desc(dev, "XaQti Corp. XMAC II"); 1152 break; 1153 case SK_YUKON: 1154 device_set_desc(dev, "Marvell Semiconductor, Inc. Yukon"); 1155 break; 1156 } 1157 1158 return(0); 1159 } 1160 1161 /* 1162 * Each XMAC chip is attached as a separate logical IP interface. 1163 * Single port cards will have only one logical interface of course. 1164 */ 1165 static int 1166 sk_attach(device_t dev) 1167 { 1168 struct sk_softc *sc = device_get_softc(device_get_parent(dev)); 1169 struct sk_if_softc *sc_if = device_get_softc(dev); 1170 struct ifnet *ifp; 1171 int i, port; 1172 1173 port = *(int *)device_get_ivars(dev); 1174 free(device_get_ivars(dev), M_DEVBUF); 1175 device_set_ivars(dev, NULL); 1176 sc_if->sk_dev = dev; 1177 callout_init(&sc_if->sk_tick_timer); 1178 lwkt_serialize_init(&sc_if->sk_jslot_serializer); 1179 1180 sc_if->sk_dev = dev; 1181 sc_if->sk_unit = device_get_unit(dev); 1182 sc_if->sk_port = port; 1183 sc_if->sk_softc = sc; 1184 sc->sk_if[port] = sc_if; 1185 if (port == SK_PORT_A) 1186 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR0; 1187 if (port == SK_PORT_B) 1188 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR1; 1189 1190 /* 1191 * Get station address for this interface. Note that 1192 * dual port cards actually come with three station 1193 * addresses: one for each port, plus an extra. The 1194 * extra one is used by the SysKonnect driver software 1195 * as a 'virtual' station address for when both ports 1196 * are operating in failover mode. Currently we don't 1197 * use this extra address. 1198 */ 1199 for (i = 0; i < ETHER_ADDR_LEN; i++) 1200 sc_if->arpcom.ac_enaddr[i] = 1201 sk_win_read_1(sc, SK_MAC0_0 + (port * 8) + i); 1202 1203 /* 1204 * Set up RAM buffer addresses. The NIC will have a certain 1205 * amount of SRAM on it, somewhere between 512K and 2MB. We 1206 * need to divide this up a) between the transmitter and 1207 * receiver and b) between the two XMACs, if this is a 1208 * dual port NIC. Our algotithm is to divide up the memory 1209 * evenly so that everyone gets a fair share. 1210 */ 1211 if (sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC) { 1212 uint32_t chunk, val; 1213 1214 chunk = sc->sk_ramsize / 2; 1215 val = sc->sk_rboff / sizeof(uint64_t); 1216 sc_if->sk_rx_ramstart = val; 1217 val += (chunk / sizeof(uint64_t)); 1218 sc_if->sk_rx_ramend = val - 1; 1219 sc_if->sk_tx_ramstart = val; 1220 val += (chunk / sizeof(uint64_t)); 1221 sc_if->sk_tx_ramend = val - 1; 1222 } else { 1223 uint32_t chunk, val; 1224 1225 chunk = sc->sk_ramsize / 4; 1226 val = (sc->sk_rboff + (chunk * 2 * sc_if->sk_port)) / 1227 sizeof(uint64_t); 1228 sc_if->sk_rx_ramstart = val; 1229 val += (chunk / sizeof(uint64_t)); 1230 sc_if->sk_rx_ramend = val - 1; 1231 sc_if->sk_tx_ramstart = val; 1232 val += (chunk / sizeof(uint64_t)); 1233 sc_if->sk_tx_ramend = val - 1; 1234 } 1235 1236 /* Read and save PHY type and set PHY address */ 1237 sc_if->sk_phytype = sk_win_read_1(sc, SK_EPROM1) & 0xF; 1238 switch(sc_if->sk_phytype) { 1239 case SK_PHYTYPE_XMAC: 1240 sc_if->sk_phyaddr = SK_PHYADDR_XMAC; 1241 break; 1242 case SK_PHYTYPE_BCOM: 1243 sc_if->sk_phyaddr = SK_PHYADDR_BCOM; 1244 break; 1245 case SK_PHYTYPE_MARV_COPPER: 1246 sc_if->sk_phyaddr = SK_PHYADDR_MARV; 1247 break; 1248 default: 1249 printf("skc%d: unsupported PHY type: %d\n", 1250 sc->sk_unit, sc_if->sk_phytype); 1251 sc->sk_if[port] = NULL; 1252 return(ENODEV); 1253 } 1254 1255 /* Allocate the descriptor queues. */ 1256 sc_if->sk_rdata = contigmalloc(sizeof(struct sk_ring_data), M_DEVBUF, 1257 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 1258 1259 if (sc_if->sk_rdata == NULL) { 1260 printf("sk%d: no memory for list buffers!\n", sc_if->sk_unit); 1261 sc->sk_if[port] = NULL; 1262 return(ENOMEM); 1263 } 1264 1265 bzero(sc_if->sk_rdata, sizeof(struct sk_ring_data)); 1266 1267 /* Try to allocate memory for jumbo buffers. */ 1268 if (sk_alloc_jumbo_mem(sc_if)) { 1269 printf("sk%d: jumbo buffer allocation failed\n", 1270 sc_if->sk_unit); 1271 contigfree(sc_if->sk_rdata, 1272 sizeof(struct sk_ring_data), M_DEVBUF); 1273 sc->sk_if[port] = NULL; 1274 return(ENOMEM); 1275 } 1276 1277 ifp = &sc_if->arpcom.ac_if; 1278 ifp->if_softc = sc_if; 1279 if_initname(ifp, "sk", sc_if->sk_unit); 1280 ifp->if_mtu = ETHERMTU; 1281 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1282 ifp->if_ioctl = sk_ioctl; 1283 ifp->if_start = sk_start; 1284 ifp->if_watchdog = sk_watchdog; 1285 ifp->if_init = sk_init; 1286 ifp->if_baudrate = 1000000000; 1287 ifq_set_maxlen(&ifp->if_snd, SK_TX_RING_CNT - 1); 1288 ifq_set_ready(&ifp->if_snd); 1289 1290 /* 1291 * Do miibus setup. 1292 */ 1293 switch (sc->sk_type) { 1294 case SK_GENESIS: 1295 sk_init_xmac(sc_if); 1296 break; 1297 case SK_YUKON: 1298 sk_init_yukon(sc_if); 1299 break; 1300 } 1301 1302 if (mii_phy_probe(dev, &sc_if->sk_miibus, 1303 sk_ifmedia_upd, sk_ifmedia_sts)) { 1304 printf("skc%d: no PHY found!\n", sc_if->sk_unit); 1305 contigfree(sc_if->sk_cdata.sk_jumbo_buf, SK_JMEM, 1306 M_DEVBUF); 1307 contigfree(sc_if->sk_rdata, 1308 sizeof(struct sk_ring_data), M_DEVBUF); 1309 sc->sk_if[port] = NULL; 1310 return(ENXIO); 1311 } 1312 1313 /* 1314 * Call MI attach routine. 1315 */ 1316 ether_ifattach(ifp, sc_if->arpcom.ac_enaddr, &sk_serializer); 1317 callout_init(&sc_if->sk_tick_timer); 1318 1319 return(0); 1320 } 1321 1322 /* 1323 * Attach the interface. Allocate softc structures, do ifmedia 1324 * setup and ethernet/BPF attach. 1325 */ 1326 static int 1327 skc_attach(device_t dev) 1328 { 1329 struct sk_softc *sc; 1330 int error = 0, *port, rid, unit; 1331 uint32_t command; 1332 uint8_t skrs; 1333 1334 crit_enter(); 1335 1336 sc = device_get_softc(dev); 1337 unit = device_get_unit(dev); 1338 switch (pci_get_device(dev)) { 1339 case DEVICEID_SK_V1: 1340 sc->sk_type = SK_GENESIS; 1341 break; 1342 case DEVICEID_SK_V2: 1343 case DEVICEID_3COM_3C940: 1344 case DEVICEID_LINKSYS_EG1032: 1345 case DEVICEID_DLINK_DGE530T: 1346 sc->sk_type = SK_YUKON; 1347 break; 1348 } 1349 1350 /* 1351 * Handle power management nonsense. 1352 */ 1353 command = pci_read_config(dev, SK_PCI_CAPID, 4) & 0x000000FF; 1354 if (command == 0x01) { 1355 command = pci_read_config(dev, SK_PCI_PWRMGMTCTRL, 4); 1356 if (command & SK_PSTATE_MASK) { 1357 uint32_t iobase, membase, irq; 1358 1359 /* Save important PCI config data. */ 1360 iobase = pci_read_config(dev, SK_PCI_LOIO, 4); 1361 membase = pci_read_config(dev, SK_PCI_LOMEM, 4); 1362 irq = pci_read_config(dev, SK_PCI_INTLINE, 4); 1363 1364 /* Reset the power state. */ 1365 printf("skc%d: chip is in D%d power mode " 1366 "-- setting to D0\n", unit, command & SK_PSTATE_MASK); 1367 command &= 0xFFFFFFFC; 1368 pci_write_config(dev, SK_PCI_PWRMGMTCTRL, command, 4); 1369 1370 /* Restore PCI config data. */ 1371 pci_write_config(dev, SK_PCI_LOIO, iobase, 4); 1372 pci_write_config(dev, SK_PCI_LOMEM, membase, 4); 1373 pci_write_config(dev, SK_PCI_INTLINE, irq, 4); 1374 } 1375 } 1376 1377 /* 1378 * Map control/status registers. 1379 */ 1380 command = pci_read_config(dev, PCIR_COMMAND, 4); 1381 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 1382 pci_write_config(dev, PCIR_COMMAND, command, 4); 1383 command = pci_read_config(dev, PCIR_COMMAND, 4); 1384 1385 #ifdef SK_USEIOSPACE 1386 if ((command & PCIM_CMD_PORTEN) == 0) { 1387 printf("skc%d: failed to enable I/O ports!\n", unit); 1388 error = ENXIO; 1389 goto fail; 1390 } 1391 #else 1392 if ((command & PCIM_CMD_MEMEN) == 0) { 1393 printf("skc%d: failed to enable memory mapping!\n", unit); 1394 error = ENXIO; 1395 goto fail; 1396 } 1397 #endif 1398 1399 rid = SK_RID; 1400 sc->sk_res = bus_alloc_resource_any(dev, SK_RES, &rid, RF_ACTIVE); 1401 1402 if (sc->sk_res == NULL) { 1403 printf("sk%d: couldn't map ports/memory\n", unit); 1404 error = ENXIO; 1405 goto fail; 1406 } 1407 1408 sc->sk_btag = rman_get_bustag(sc->sk_res); 1409 sc->sk_bhandle = rman_get_bushandle(sc->sk_res); 1410 1411 /* Allocate interrupt */ 1412 rid = 0; 1413 sc->sk_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1414 RF_SHAREABLE | RF_ACTIVE); 1415 1416 if (sc->sk_irq == NULL) { 1417 printf("skc%d: couldn't map interrupt\n", unit); 1418 bus_release_resource(dev, SK_RES, SK_RID, sc->sk_res); 1419 error = ENXIO; 1420 goto fail; 1421 } 1422 1423 error = bus_setup_intr(dev, sc->sk_irq, INTR_NETSAFE, 1424 sk_intr, sc, 1425 &sc->sk_intrhand, &sk_serializer); 1426 1427 if (error) { 1428 printf("skc%d: couldn't set up irq\n", unit); 1429 bus_release_resource(dev, SK_RES, SK_RID, sc->sk_res); 1430 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sk_irq); 1431 goto fail; 1432 } 1433 1434 /* Reset the adapter. */ 1435 sk_reset(sc); 1436 1437 sc->sk_unit = unit; 1438 1439 /* Read and save vital product data from EEPROM. */ 1440 sk_vpd_read(sc); 1441 1442 skrs = sk_win_read_1(sc, SK_EPROM0); 1443 if (sc->sk_type == SK_GENESIS) { 1444 /* Read and save RAM size and RAMbuffer offset */ 1445 switch(skrs) { 1446 case SK_RAMSIZE_512K_64: 1447 sc->sk_ramsize = 0x80000; 1448 sc->sk_rboff = SK_RBOFF_0; 1449 break; 1450 case SK_RAMSIZE_1024K_64: 1451 sc->sk_ramsize = 0x100000; 1452 sc->sk_rboff = SK_RBOFF_80000; 1453 break; 1454 case SK_RAMSIZE_1024K_128: 1455 sc->sk_ramsize = 0x100000; 1456 sc->sk_rboff = SK_RBOFF_0; 1457 break; 1458 case SK_RAMSIZE_2048K_128: 1459 sc->sk_ramsize = 0x200000; 1460 sc->sk_rboff = SK_RBOFF_0; 1461 break; 1462 default: 1463 printf("skc%d: unknown ram size: %d\n", 1464 sc->sk_unit, sk_win_read_1(sc, SK_EPROM0)); 1465 bus_teardown_intr(dev, sc->sk_irq, sc->sk_intrhand); 1466 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sk_irq); 1467 bus_release_resource(dev, SK_RES, SK_RID, sc->sk_res); 1468 error = ENXIO; 1469 goto fail; 1470 break; 1471 } 1472 } else { /* SK_YUKON */ 1473 if (skrs == 0x00) { 1474 sc->sk_ramsize = 0x20000; 1475 } else { 1476 sc->sk_ramsize = skrs * (1<<12); 1477 } 1478 sc->sk_rboff = SK_RBOFF_0; 1479 } 1480 1481 /* Read and save physical media type */ 1482 switch(sk_win_read_1(sc, SK_PMDTYPE)) { 1483 case SK_PMD_1000BASESX: 1484 sc->sk_pmd = IFM_1000_SX; 1485 break; 1486 case SK_PMD_1000BASELX: 1487 sc->sk_pmd = IFM_1000_LX; 1488 break; 1489 case SK_PMD_1000BASECX: 1490 sc->sk_pmd = IFM_1000_CX; 1491 break; 1492 case SK_PMD_1000BASETX: 1493 sc->sk_pmd = IFM_1000_T; 1494 break; 1495 default: 1496 printf("skc%d: unknown media type: 0x%x\n", 1497 sc->sk_unit, sk_win_read_1(sc, SK_PMDTYPE)); 1498 bus_teardown_intr(dev, sc->sk_irq, sc->sk_intrhand); 1499 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sk_irq); 1500 bus_release_resource(dev, SK_RES, SK_RID, sc->sk_res); 1501 error = ENXIO; 1502 goto fail; 1503 } 1504 1505 /* Announce the product name. */ 1506 printf("skc%d: %s\n", sc->sk_unit, sc->sk_vpd_prodname); 1507 sc->sk_devs[SK_PORT_A] = device_add_child(dev, "sk", -1); 1508 port = malloc(sizeof(int), M_DEVBUF, M_WAITOK); 1509 *port = SK_PORT_A; 1510 device_set_ivars(sc->sk_devs[SK_PORT_A], port); 1511 1512 if (!(sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC)) { 1513 sc->sk_devs[SK_PORT_B] = device_add_child(dev, "sk", -1); 1514 port = malloc(sizeof(int), M_DEVBUF, M_WAITOK); 1515 *port = SK_PORT_B; 1516 device_set_ivars(sc->sk_devs[SK_PORT_B], port); 1517 } 1518 1519 /* Turn on the 'driver is loaded' LED. */ 1520 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON); 1521 1522 bus_generic_attach(dev); 1523 1524 fail: 1525 crit_exit(); 1526 return(error); 1527 } 1528 1529 static int 1530 sk_detach(device_t dev) 1531 { 1532 struct sk_if_softc *sc_if = device_get_softc(dev); 1533 struct ifnet *ifp = &sc_if->arpcom.ac_if; 1534 1535 ether_ifdetach(ifp); 1536 bus_generic_detach(dev); 1537 if (sc_if->sk_miibus != NULL) 1538 device_delete_child(dev, sc_if->sk_miibus); 1539 contigfree(sc_if->sk_cdata.sk_jumbo_buf, SK_JMEM, M_DEVBUF); 1540 contigfree(sc_if->sk_rdata, sizeof(struct sk_ring_data), M_DEVBUF); 1541 1542 return(0); 1543 } 1544 1545 static int 1546 skc_detach(device_t dev) 1547 { 1548 struct sk_softc *sc; 1549 1550 sc = device_get_softc(dev); 1551 1552 lwkt_serialize_enter(&sk_serializer); 1553 1554 if (sc->sk_if[SK_PORT_A] != NULL) 1555 sk_stop(sc->sk_if[SK_PORT_A]); 1556 if (sc->sk_if[SK_PORT_B] != NULL) 1557 sk_stop(sc->sk_if[SK_PORT_B]); 1558 1559 bus_teardown_intr(dev, sc->sk_irq, sc->sk_intrhand); 1560 1561 lwkt_serialize_exit(&sk_serializer); 1562 1563 /* 1564 * recursed from sk_detach ? don't need serializer 1565 */ 1566 bus_generic_detach(dev); 1567 if (sc->sk_devs[SK_PORT_A] != NULL) 1568 device_delete_child(dev, sc->sk_devs[SK_PORT_A]); 1569 if (sc->sk_devs[SK_PORT_B] != NULL) 1570 device_delete_child(dev, sc->sk_devs[SK_PORT_B]); 1571 1572 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sk_irq); 1573 bus_release_resource(dev, SK_RES, SK_RID, sc->sk_res); 1574 1575 return(0); 1576 } 1577 1578 static int 1579 sk_encap(struct sk_if_softc *sc_if, struct mbuf *m_head, uint32_t *txidx) 1580 { 1581 struct sk_tx_desc *f = NULL; 1582 struct mbuf *m; 1583 uint32_t cnt = 0, cur, frag; 1584 1585 m = m_head; 1586 cur = frag = *txidx; 1587 1588 /* 1589 * Start packing the mbufs in this chain into 1590 * the fragment pointers. Stop when we run out 1591 * of fragments or hit the end of the mbuf chain. 1592 */ 1593 for (m = m_head; m != NULL; m = m->m_next) { 1594 if (m->m_len != 0) { 1595 if ((SK_TX_RING_CNT - 1596 (sc_if->sk_cdata.sk_tx_cnt + cnt)) < 2) 1597 return(ENOBUFS); 1598 f = &sc_if->sk_rdata->sk_tx_ring[frag]; 1599 f->sk_data_lo = vtophys(mtod(m, vm_offset_t)); 1600 f->sk_ctl = m->m_len | SK_OPCODE_DEFAULT; 1601 if (cnt == 0) 1602 f->sk_ctl |= SK_TXCTL_FIRSTFRAG; 1603 else 1604 f->sk_ctl |= SK_TXCTL_OWN; 1605 cur = frag; 1606 SK_INC(frag, SK_TX_RING_CNT); 1607 cnt++; 1608 } 1609 } 1610 1611 if (m != NULL) 1612 return(ENOBUFS); 1613 1614 sc_if->sk_rdata->sk_tx_ring[cur].sk_ctl |= 1615 SK_TXCTL_LASTFRAG|SK_TXCTL_EOF_INTR; 1616 sc_if->sk_cdata.sk_tx_chain[cur].sk_mbuf = m_head; 1617 sc_if->sk_rdata->sk_tx_ring[*txidx].sk_ctl |= SK_TXCTL_OWN; 1618 sc_if->sk_cdata.sk_tx_cnt += cnt; 1619 1620 *txidx = frag; 1621 1622 return(0); 1623 } 1624 1625 static void 1626 sk_start(struct ifnet *ifp) 1627 { 1628 struct sk_if_softc *sc_if = ifp->if_softc; 1629 struct sk_softc *sc = sc_if->sk_softc; 1630 struct mbuf *m_head = NULL; 1631 uint32_t idx; 1632 int need_trans; 1633 1634 idx = sc_if->sk_cdata.sk_tx_prod; 1635 1636 need_trans = 0; 1637 while(sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf == NULL) { 1638 m_head = ifq_poll(&ifp->if_snd); 1639 if (m_head == NULL) 1640 break; 1641 1642 /* 1643 * Pack the data into the transmit ring. If we 1644 * don't have room, set the OACTIVE flag and wait 1645 * for the NIC to drain the ring. 1646 */ 1647 if (sk_encap(sc_if, m_head, &idx)) { 1648 ifp->if_flags |= IFF_OACTIVE; 1649 break; 1650 } 1651 ifq_dequeue(&ifp->if_snd, m_head); 1652 need_trans = 1; 1653 1654 BPF_MTAP(ifp, m_head); 1655 } 1656 1657 if (!need_trans) 1658 return; 1659 1660 /* Transmit */ 1661 sc_if->sk_cdata.sk_tx_prod = idx; 1662 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START); 1663 1664 /* Set a timeout in case the chip goes out to lunch. */ 1665 ifp->if_timer = 5; 1666 } 1667 1668 1669 static void 1670 sk_watchdog(struct ifnet *ifp) 1671 { 1672 struct sk_if_softc *sc_if; 1673 1674 sc_if = ifp->if_softc; 1675 1676 printf("sk%d: watchdog timeout\n", sc_if->sk_unit); 1677 ifp->if_flags &= ~IFF_RUNNING; 1678 sk_init(sc_if); 1679 1680 if (!ifq_is_empty(&ifp->if_snd)) 1681 ifp->if_start(ifp); 1682 } 1683 1684 static void 1685 skc_shutdown(device_t dev) 1686 { 1687 struct sk_softc *sc = device_get_softc(dev); 1688 1689 lwkt_serialize_enter(&sk_serializer); 1690 1691 /* Turn off the 'driver is loaded' LED. */ 1692 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF); 1693 1694 /* 1695 * Reset the GEnesis controller. Doing this should also 1696 * assert the resets on the attached XMAC(s). 1697 */ 1698 sk_reset(sc); 1699 lwkt_serialize_exit(&sk_serializer); 1700 } 1701 1702 static void 1703 sk_rxeof(struct sk_if_softc *sc_if) 1704 { 1705 struct ifnet *ifp = &sc_if->arpcom.ac_if; 1706 struct mbuf *m; 1707 struct sk_chain *cur_rx; 1708 int i, total_len = 0; 1709 uint32_t rxstat; 1710 1711 i = sc_if->sk_cdata.sk_rx_prod; 1712 cur_rx = &sc_if->sk_cdata.sk_rx_chain[i]; 1713 1714 while(!(sc_if->sk_rdata->sk_rx_ring[i].sk_ctl & SK_RXCTL_OWN)) { 1715 cur_rx = &sc_if->sk_cdata.sk_rx_chain[i]; 1716 rxstat = sc_if->sk_rdata->sk_rx_ring[i].sk_xmac_rxstat; 1717 m = cur_rx->sk_mbuf; 1718 cur_rx->sk_mbuf = NULL; 1719 total_len = SK_RXBYTES(sc_if->sk_rdata->sk_rx_ring[i].sk_ctl); 1720 SK_INC(i, SK_RX_RING_CNT); 1721 1722 if (rxstat & XM_RXSTAT_ERRFRAME) { 1723 ifp->if_ierrors++; 1724 sk_newbuf(sc_if, cur_rx, m); 1725 continue; 1726 } 1727 1728 /* 1729 * Try to allocate a new jumbo buffer. If that 1730 * fails, copy the packet to mbufs and put the 1731 * jumbo buffer back in the ring so it can be 1732 * re-used. If allocating mbufs fails, then we 1733 * have to drop the packet. 1734 */ 1735 if (sk_newbuf(sc_if, cur_rx, NULL) == ENOBUFS) { 1736 struct mbuf *m0; 1737 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 1738 total_len + ETHER_ALIGN, 0, ifp, NULL); 1739 sk_newbuf(sc_if, cur_rx, m); 1740 if (m0 == NULL) { 1741 printf("sk%d: no receive buffers " 1742 "available -- packet dropped!\n", 1743 sc_if->sk_unit); 1744 ifp->if_ierrors++; 1745 continue; 1746 } 1747 m_adj(m0, ETHER_ALIGN); 1748 m = m0; 1749 } else { 1750 m->m_pkthdr.rcvif = ifp; 1751 m->m_pkthdr.len = m->m_len = total_len; 1752 } 1753 1754 ifp->if_ipackets++; 1755 ifp->if_input(ifp, m); 1756 } 1757 1758 sc_if->sk_cdata.sk_rx_prod = i; 1759 } 1760 1761 static void 1762 sk_txeof(struct sk_if_softc *sc_if) 1763 { 1764 struct ifnet *ifp = &sc_if->arpcom.ac_if; 1765 struct sk_tx_desc *cur_tx = NULL; 1766 uint32_t idx; 1767 1768 /* 1769 * Go through our tx ring and free mbufs for those 1770 * frames that have been sent. 1771 */ 1772 idx = sc_if->sk_cdata.sk_tx_cons; 1773 while(idx != sc_if->sk_cdata.sk_tx_prod) { 1774 cur_tx = &sc_if->sk_rdata->sk_tx_ring[idx]; 1775 if (cur_tx->sk_ctl & SK_TXCTL_OWN) 1776 break; 1777 if (cur_tx->sk_ctl & SK_TXCTL_LASTFRAG) 1778 ifp->if_opackets++; 1779 if (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf != NULL) { 1780 m_freem(sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf); 1781 sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf = NULL; 1782 } 1783 sc_if->sk_cdata.sk_tx_cnt--; 1784 SK_INC(idx, SK_TX_RING_CNT); 1785 ifp->if_timer = 0; 1786 } 1787 1788 sc_if->sk_cdata.sk_tx_cons = idx; 1789 1790 if (cur_tx != NULL) 1791 ifp->if_flags &= ~IFF_OACTIVE; 1792 } 1793 1794 static void 1795 sk_tick(void *xsc_if) 1796 { 1797 struct sk_if_softc *sc_if = xsc_if; 1798 struct ifnet *ifp = &sc_if->arpcom.ac_if; 1799 struct mii_data *mii = device_get_softc(sc_if->sk_miibus); 1800 int i; 1801 1802 lwkt_serialize_enter(&sk_serializer); 1803 1804 if ((ifp->if_flags & IFF_UP) == 0) { 1805 lwkt_serialize_exit(&sk_serializer); 1806 return; 1807 } 1808 1809 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 1810 sk_intr_bcom(sc_if); 1811 lwkt_serialize_exit(&sk_serializer); 1812 return; 1813 } 1814 1815 /* 1816 * According to SysKonnect, the correct way to verify that 1817 * the link has come back up is to poll bit 0 of the GPIO 1818 * register three times. This pin has the signal from the 1819 * link_sync pin connected to it; if we read the same link 1820 * state 3 times in a row, we know the link is up. 1821 */ 1822 for (i = 0; i < 3; i++) { 1823 if (SK_XM_READ_2(sc_if, XM_GPIO) & XM_GPIO_GP0_SET) 1824 break; 1825 } 1826 1827 if (i != 3) { 1828 callout_reset(&sc_if->sk_tick_timer, hz, sk_tick, sc_if); 1829 lwkt_serialize_exit(&sk_serializer); 1830 return; 1831 } 1832 1833 /* Turn the GP0 interrupt back on. */ 1834 SK_XM_CLRBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET); 1835 SK_XM_READ_2(sc_if, XM_ISR); 1836 mii_tick(mii); 1837 mii_pollstat(mii); 1838 callout_stop(&sc_if->sk_tick_timer); 1839 lwkt_serialize_exit(&sk_serializer); 1840 } 1841 1842 static void 1843 sk_intr_bcom(struct sk_if_softc *sc_if) 1844 { 1845 struct ifnet *ifp = &sc_if->arpcom.ac_if; 1846 struct mii_data *mii = device_get_softc(sc_if->sk_miibus); 1847 int status; 1848 1849 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 1850 1851 /* 1852 * Read the PHY interrupt register to make sure 1853 * we clear any pending interrupts. 1854 */ 1855 status = sk_xmac_miibus_readreg(sc_if, SK_PHYADDR_BCOM, BRGPHY_MII_ISR); 1856 1857 if ((ifp->if_flags & IFF_RUNNING) == 0) { 1858 sk_init_xmac(sc_if); 1859 return; 1860 } 1861 1862 if (status & (BRGPHY_ISR_LNK_CHG|BRGPHY_ISR_AN_PR)) { 1863 int lstat; 1864 lstat = sk_xmac_miibus_readreg(sc_if, SK_PHYADDR_BCOM, 1865 BRGPHY_MII_AUXSTS); 1866 1867 if (!(lstat & BRGPHY_AUXSTS_LINK) && sc_if->sk_link) { 1868 mii_mediachg(mii); 1869 /* Turn off the link LED. */ 1870 SK_IF_WRITE_1(sc_if, 0, 1871 SK_LINKLED1_CTL, SK_LINKLED_OFF); 1872 sc_if->sk_link = 0; 1873 } else if (status & BRGPHY_ISR_LNK_CHG) { 1874 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM, 1875 BRGPHY_MII_IMR, 0xFF00); 1876 mii_tick(mii); 1877 sc_if->sk_link = 1; 1878 /* Turn on the link LED. */ 1879 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, 1880 SK_LINKLED_ON|SK_LINKLED_LINKSYNC_OFF| 1881 SK_LINKLED_BLINK_OFF); 1882 mii_pollstat(mii); 1883 } else { 1884 mii_tick(mii); 1885 callout_reset(&sc_if->sk_tick_timer, hz, 1886 sk_tick, sc_if); 1887 } 1888 } 1889 1890 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 1891 } 1892 1893 static void 1894 sk_intr_xmac(struct sk_if_softc *sc_if) 1895 { 1896 uint16_t status; 1897 1898 status = SK_XM_READ_2(sc_if, XM_ISR); 1899 1900 /* 1901 * Link has gone down. Start MII tick timeout to 1902 * watch for link resync. 1903 */ 1904 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) { 1905 if (status & XM_ISR_GP0_SET) { 1906 SK_XM_SETBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET); 1907 callout_reset(&sc_if->sk_tick_timer, hz, 1908 sk_tick, sc_if); 1909 } 1910 1911 if (status & XM_ISR_AUTONEG_DONE) { 1912 callout_reset(&sc_if->sk_tick_timer, hz, 1913 sk_tick, sc_if); 1914 } 1915 } 1916 1917 if (status & XM_IMR_TX_UNDERRUN) 1918 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_TXFIFO); 1919 1920 if (status & XM_IMR_RX_OVERRUN) 1921 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_RXFIFO); 1922 1923 status = SK_XM_READ_2(sc_if, XM_ISR); 1924 } 1925 1926 static void 1927 sk_intr_yukon(struct sk_if_softc *sc_if) 1928 { 1929 int status; 1930 1931 status = SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 1932 } 1933 1934 static void 1935 sk_intr(void *xsc) 1936 { 1937 struct sk_softc *sc = xsc; 1938 struct sk_if_softc *sc_if0 = sc->sk_if[SK_PORT_A]; 1939 struct sk_if_softc *sc_if1 = sc->sk_if[SK_PORT_A]; 1940 struct ifnet *ifp0 = NULL, *ifp1 = NULL; 1941 uint32_t status; 1942 1943 if (sc_if0 != NULL) 1944 ifp0 = &sc_if0->arpcom.ac_if; 1945 if (sc_if1 != NULL) 1946 ifp1 = &sc_if1->arpcom.ac_if; 1947 1948 for (;;) { 1949 status = CSR_READ_4(sc, SK_ISSR); 1950 if ((status & sc->sk_intrmask) == 0) 1951 break; 1952 1953 /* Handle receive interrupts first. */ 1954 if (status & SK_ISR_RX1_EOF) { 1955 sk_rxeof(sc_if0); 1956 CSR_WRITE_4(sc, SK_BMU_RX_CSR0, 1957 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START); 1958 } 1959 if (status & SK_ISR_RX2_EOF) { 1960 sk_rxeof(sc_if1); 1961 CSR_WRITE_4(sc, SK_BMU_RX_CSR1, 1962 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START); 1963 } 1964 1965 /* Then transmit interrupts. */ 1966 if (status & SK_ISR_TX1_S_EOF) { 1967 sk_txeof(sc_if0); 1968 CSR_WRITE_4(sc, SK_BMU_TXS_CSR0, 1969 SK_TXBMU_CLR_IRQ_EOF); 1970 } 1971 if (status & SK_ISR_TX2_S_EOF) { 1972 sk_txeof(sc_if1); 1973 CSR_WRITE_4(sc, SK_BMU_TXS_CSR1, 1974 SK_TXBMU_CLR_IRQ_EOF); 1975 } 1976 1977 /* Then MAC interrupts. */ 1978 if (status & SK_ISR_MAC1 && ifp0->if_flags & IFF_RUNNING) { 1979 if (sc->sk_type == SK_GENESIS) 1980 sk_intr_xmac(sc_if0); 1981 else 1982 sk_intr_yukon(sc_if0); 1983 } 1984 1985 if (status & SK_ISR_MAC2 && ifp1->if_flags & IFF_RUNNING) { 1986 if (sc->sk_type == SK_GENESIS) 1987 sk_intr_xmac(sc_if1); 1988 else 1989 sk_intr_yukon(sc_if0); 1990 } 1991 1992 if (status & SK_ISR_EXTERNAL_REG) { 1993 if (ifp0 != NULL && 1994 sc_if0->sk_phytype == SK_PHYTYPE_BCOM) 1995 sk_intr_bcom(sc_if0); 1996 if (ifp1 != NULL && 1997 sc_if1->sk_phytype == SK_PHYTYPE_BCOM) 1998 sk_intr_bcom(sc_if1); 1999 } 2000 } 2001 2002 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2003 2004 if (ifp0 != NULL && !ifq_is_empty(&ifp0->if_snd)) 2005 sk_start(ifp0); 2006 if (ifp1 != NULL && !ifq_is_empty(&ifp0->if_snd)) 2007 sk_start(ifp1); 2008 } 2009 2010 static void 2011 sk_init_xmac(struct sk_if_softc *sc_if) 2012 { 2013 struct sk_softc *sc = sc_if->sk_softc; 2014 struct ifnet *ifp = &sc_if->arpcom.ac_if; 2015 struct sk_bcom_hack bhack[] = { 2016 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 }, { 0x17, 0x0013 }, 2017 { 0x15, 0x0404 }, { 0x17, 0x8006 }, { 0x15, 0x0132 }, { 0x17, 0x8006 }, 2018 { 0x15, 0x0232 }, { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 }, 2019 { 0, 0 } }; 2020 2021 /* Unreset the XMAC. */ 2022 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_UNRESET); 2023 DELAY(1000); 2024 2025 /* Reset the XMAC's internal state. */ 2026 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 2027 2028 /* Save the XMAC II revision */ 2029 sc_if->sk_xmac_rev = XM_XMAC_REV(SK_XM_READ_4(sc_if, XM_DEVID)); 2030 2031 /* 2032 * Perform additional initialization for external PHYs, 2033 * namely for the 1000baseTX cards that use the XMAC's 2034 * GMII mode. 2035 */ 2036 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2037 int i = 0; 2038 uint32_t val; 2039 2040 /* Take PHY out of reset. */ 2041 val = sk_win_read_4(sc, SK_GPIO); 2042 if (sc_if->sk_port == SK_PORT_A) 2043 val |= SK_GPIO_DIR0|SK_GPIO_DAT0; 2044 else 2045 val |= SK_GPIO_DIR2|SK_GPIO_DAT2; 2046 sk_win_write_4(sc, SK_GPIO, val); 2047 2048 /* Enable GMII mode on the XMAC. */ 2049 SK_XM_SETBIT_2(sc_if, XM_HWCFG, XM_HWCFG_GMIIMODE); 2050 2051 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM, 2052 BRGPHY_MII_BMCR, BRGPHY_BMCR_RESET); 2053 DELAY(10000); 2054 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM, 2055 BRGPHY_MII_IMR, 0xFFF0); 2056 2057 /* 2058 * Early versions of the BCM5400 apparently have 2059 * a bug that requires them to have their reserved 2060 * registers initialized to some magic values. I don't 2061 * know what the numbers do, I'm just the messenger. 2062 */ 2063 if (sk_xmac_miibus_readreg(sc_if, SK_PHYADDR_BCOM, 0x03) 2064 == 0x6041) { 2065 while(bhack[i].reg) { 2066 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM, 2067 bhack[i].reg, bhack[i].val); 2068 i++; 2069 } 2070 } 2071 } 2072 2073 /* Set station address */ 2074 SK_XM_WRITE_2(sc_if, XM_PAR0, 2075 *(uint16_t *)(&sc_if->arpcom.ac_enaddr[0])); 2076 SK_XM_WRITE_2(sc_if, XM_PAR1, 2077 *(uint16_t *)(&sc_if->arpcom.ac_enaddr[2])); 2078 SK_XM_WRITE_2(sc_if, XM_PAR2, 2079 *(uint16_t *)(&sc_if->arpcom.ac_enaddr[4])); 2080 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_STATION); 2081 2082 if (ifp->if_flags & IFF_BROADCAST) 2083 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD); 2084 else 2085 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD); 2086 2087 /* We don't need the FCS appended to the packet. */ 2088 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_STRIPFCS); 2089 2090 /* We want short frames padded to 60 bytes. */ 2091 SK_XM_SETBIT_2(sc_if, XM_TXCMD, XM_TXCMD_AUTOPAD); 2092 2093 /* 2094 * Enable the reception of all error frames. This is is 2095 * a necessary evil due to the design of the XMAC. The 2096 * XMAC's receive FIFO is only 8K in size, however jumbo 2097 * frames can be up to 9000 bytes in length. When bad 2098 * frame filtering is enabled, the XMAC's RX FIFO operates 2099 * in 'store and forward' mode. For this to work, the 2100 * entire frame has to fit into the FIFO, but that means 2101 * that jumbo frames larger than 8192 bytes will be 2102 * truncated. Disabling all bad frame filtering causes 2103 * the RX FIFO to operate in streaming mode, in which 2104 * case the XMAC will start transfering frames out of the 2105 * RX FIFO as soon as the FIFO threshold is reached. 2106 */ 2107 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_BADFRAMES| 2108 XM_MODE_RX_GIANTS|XM_MODE_RX_RUNTS|XM_MODE_RX_CRCERRS| 2109 XM_MODE_RX_INRANGELEN); 2110 2111 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 2112 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK); 2113 else 2114 SK_XM_CLRBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK); 2115 2116 /* 2117 * Bump up the transmit threshold. This helps hold off transmit 2118 * underruns when we're blasting traffic from both ports at once. 2119 */ 2120 SK_XM_WRITE_2(sc_if, XM_TX_REQTHRESH, SK_XM_TX_FIFOTHRESH); 2121 2122 /* Set promiscuous mode */ 2123 sk_setpromisc(sc_if); 2124 2125 /* Set multicast filter */ 2126 sk_setmulti(sc_if); 2127 2128 /* Clear and enable interrupts */ 2129 SK_XM_READ_2(sc_if, XM_ISR); 2130 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) 2131 SK_XM_WRITE_2(sc_if, XM_IMR, XM_INTRS); 2132 else 2133 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 2134 2135 /* Configure MAC arbiter */ 2136 switch(sc_if->sk_xmac_rev) { 2137 case XM_XMAC_REV_B2: 2138 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_B2); 2139 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_B2); 2140 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_B2); 2141 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_B2); 2142 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_B2); 2143 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_B2); 2144 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_B2); 2145 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_B2); 2146 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2); 2147 break; 2148 case XM_XMAC_REV_C1: 2149 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_C1); 2150 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_C1); 2151 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_C1); 2152 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_C1); 2153 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_C1); 2154 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_C1); 2155 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_C1); 2156 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_C1); 2157 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2); 2158 break; 2159 default: 2160 break; 2161 } 2162 sk_win_write_2(sc, SK_MACARB_CTL, 2163 SK_MACARBCTL_UNRESET|SK_MACARBCTL_FASTOE_OFF); 2164 2165 sc_if->sk_link = 1; 2166 } 2167 2168 static void 2169 sk_init_yukon(struct sk_if_softc *sc_if) 2170 { 2171 struct ifnet *ifp = &sc_if->arpcom.ac_if; 2172 uint32_t phy; 2173 uint16_t reg; 2174 int i; 2175 2176 /* GMAC and GPHY Reset */ 2177 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_SET); 2178 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 2179 DELAY(1000); 2180 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_CLEAR); 2181 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 2182 DELAY(1000); 2183 2184 phy = SK_GPHY_INT_POL_HI | SK_GPHY_DIS_FC | SK_GPHY_DIS_SLEEP | 2185 SK_GPHY_ENA_XC | SK_GPHY_ANEG_ALL | SK_GPHY_ENA_PAUSE; 2186 2187 switch(sc_if->sk_softc->sk_pmd) { 2188 case IFM_1000_SX: 2189 case IFM_1000_LX: 2190 phy |= SK_GPHY_FIBER; 2191 break; 2192 2193 case IFM_1000_CX: 2194 case IFM_1000_T: 2195 phy |= SK_GPHY_COPPER; 2196 break; 2197 } 2198 2199 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_SET); 2200 DELAY(1000); 2201 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_CLEAR); 2202 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_LOOP_OFF | 2203 SK_GMAC_PAUSE_ON | SK_GMAC_RESET_CLEAR); 2204 2205 /* unused read of the interrupt source register */ 2206 SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 2207 2208 reg = SK_YU_READ_2(sc_if, YUKON_PAR); 2209 2210 /* MIB Counter Clear Mode set */ 2211 reg |= YU_PAR_MIB_CLR; 2212 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2213 2214 /* MIB Counter Clear Mode clear */ 2215 reg &= ~YU_PAR_MIB_CLR; 2216 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2217 2218 /* receive control reg */ 2219 SK_YU_WRITE_2(sc_if, YUKON_RCR, YU_RCR_CRCR); 2220 2221 /* transmit parameter register */ 2222 SK_YU_WRITE_2(sc_if, YUKON_TPR, YU_TPR_JAM_LEN(0x3) | 2223 YU_TPR_JAM_IPG(0xb) | YU_TPR_JAM2DATA_IPG(0x1a) ); 2224 2225 /* serial mode register */ 2226 reg = YU_SMR_DATA_BLIND(0x1c) | YU_SMR_MFL_VLAN | YU_SMR_IPG_DATA(0x1e); 2227 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 2228 reg |= YU_SMR_MFL_JUMBO; 2229 SK_YU_WRITE_2(sc_if, YUKON_SMR, reg); 2230 2231 /* Setup Yukon's address */ 2232 for (i = 0; i < 3; i++) { 2233 /* Write Source Address 1 (unicast filter) */ 2234 SK_YU_WRITE_2(sc_if, YUKON_SAL1 + i * 4, 2235 sc_if->arpcom.ac_enaddr[i * 2] | 2236 sc_if->arpcom.ac_enaddr[i * 2 + 1] << 8); 2237 } 2238 2239 for (i = 0; i < 3; i++) { 2240 reg = sk_win_read_2(sc_if->sk_softc, 2241 SK_MAC1_0 + i * 2 + sc_if->sk_port * 8); 2242 SK_YU_WRITE_2(sc_if, YUKON_SAL2 + i * 4, reg); 2243 } 2244 2245 /* Set promiscuous mode */ 2246 sk_setpromisc(sc_if); 2247 2248 /* Set multicast filter */ 2249 sk_setmulti(sc_if); 2250 2251 /* enable interrupt mask for counter overflows */ 2252 SK_YU_WRITE_2(sc_if, YUKON_TIMR, 0); 2253 SK_YU_WRITE_2(sc_if, YUKON_RIMR, 0); 2254 SK_YU_WRITE_2(sc_if, YUKON_TRIMR, 0); 2255 2256 /* Configure RX MAC FIFO */ 2257 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_CLEAR); 2258 SK_IF_WRITE_4(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_OPERATION_ON); 2259 2260 /* Configure TX MAC FIFO */ 2261 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_CLEAR); 2262 SK_IF_WRITE_4(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_OPERATION_ON); 2263 } 2264 2265 /* 2266 * Note that to properly initialize any part of the GEnesis chip, 2267 * you first have to take it out of reset mode. 2268 */ 2269 static void 2270 sk_init(void *xsc) 2271 { 2272 struct sk_if_softc *sc_if = xsc; 2273 struct sk_softc *sc = sc_if->sk_softc; 2274 struct ifnet *ifp = &sc_if->arpcom.ac_if; 2275 struct mii_data *mii = device_get_softc(sc_if->sk_miibus); 2276 uint16_t reg; 2277 2278 crit_enter(); 2279 2280 if (ifp->if_flags & IFF_RUNNING) { 2281 crit_exit(); 2282 return; 2283 } 2284 2285 /* Cancel pending I/O and free all RX/TX buffers. */ 2286 sk_stop(sc_if); 2287 2288 if (sc->sk_type == SK_GENESIS) { 2289 /* Configure LINK_SYNC LED */ 2290 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_ON); 2291 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, 2292 SK_LINKLED_LINKSYNC_ON); 2293 2294 /* Configure RX LED */ 2295 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, 2296 SK_RXLEDCTL_COUNTER_START); 2297 2298 /* Configure TX LED */ 2299 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, 2300 SK_TXLEDCTL_COUNTER_START); 2301 } 2302 2303 /* Configure I2C registers */ 2304 2305 /* Configure XMAC(s) */ 2306 switch (sc->sk_type) { 2307 case SK_GENESIS: 2308 sk_init_xmac(sc_if); 2309 break; 2310 case SK_YUKON: 2311 sk_init_yukon(sc_if); 2312 break; 2313 } 2314 mii_mediachg(mii); 2315 2316 if (sc->sk_type == SK_GENESIS) { 2317 /* Configure MAC FIFOs */ 2318 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_UNRESET); 2319 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_END, SK_FIFO_END); 2320 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_ON); 2321 2322 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_UNRESET); 2323 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_END, SK_FIFO_END); 2324 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_ON); 2325 } 2326 2327 /* Configure transmit arbiter(s) */ 2328 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, 2329 SK_TXARCTL_ON | SK_TXARCTL_FSYNC_ON); 2330 2331 /* Configure RAMbuffers */ 2332 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_UNRESET); 2333 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_START, sc_if->sk_rx_ramstart); 2334 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_WR_PTR, sc_if->sk_rx_ramstart); 2335 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_RD_PTR, sc_if->sk_rx_ramstart); 2336 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_END, sc_if->sk_rx_ramend); 2337 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_ON); 2338 2339 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_UNRESET); 2340 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_STORENFWD_ON); 2341 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_START, sc_if->sk_tx_ramstart); 2342 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_WR_PTR, sc_if->sk_tx_ramstart); 2343 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_RD_PTR, sc_if->sk_tx_ramstart); 2344 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_END, sc_if->sk_tx_ramend); 2345 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_ON); 2346 2347 /* Configure BMUs */ 2348 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_ONLINE); 2349 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_LO, 2350 vtophys(&sc_if->sk_rdata->sk_rx_ring[0])); 2351 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_HI, 0); 2352 2353 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_ONLINE); 2354 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_LO, 2355 vtophys(&sc_if->sk_rdata->sk_tx_ring[0])); 2356 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_HI, 0); 2357 2358 /* Init descriptors */ 2359 if (sk_init_rx_ring(sc_if) == ENOBUFS) { 2360 printf("sk%d: initialization failed: no " 2361 "memory for rx buffers\n", sc_if->sk_unit); 2362 sk_stop(sc_if); 2363 crit_exit(); 2364 return; 2365 } 2366 sk_init_tx_ring(sc_if); 2367 2368 /* Configure interrupt handling */ 2369 CSR_READ_4(sc, SK_ISSR); 2370 if (sc_if->sk_port == SK_PORT_A) 2371 sc->sk_intrmask |= SK_INTRS1; 2372 else 2373 sc->sk_intrmask |= SK_INTRS2; 2374 2375 sc->sk_intrmask |= SK_ISR_EXTERNAL_REG; 2376 2377 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2378 2379 /* Start BMUs. */ 2380 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_RX_START); 2381 2382 switch(sc->sk_type) { 2383 case SK_GENESIS: 2384 /* Enable XMACs TX and RX state machines */ 2385 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_IGNPAUSE); 2386 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, 2387 XM_MMUCMD_TX_ENB | XM_MMUCMD_RX_ENB); 2388 break; 2389 case SK_YUKON: 2390 reg = SK_YU_READ_2(sc_if, YUKON_GPCR); 2391 reg |= YU_GPCR_TXEN | YU_GPCR_RXEN; 2392 reg &= ~(YU_GPCR_SPEED_EN | YU_GPCR_DPLX_EN); 2393 SK_YU_WRITE_2(sc_if, YUKON_GPCR, reg); 2394 } 2395 2396 ifp->if_flags |= IFF_RUNNING; 2397 ifp->if_flags &= ~IFF_OACTIVE; 2398 2399 crit_exit(); 2400 } 2401 2402 static void 2403 sk_stop(struct sk_if_softc *sc_if) 2404 { 2405 int i; 2406 struct sk_softc *sc = sc_if->sk_softc; 2407 struct ifnet *ifp = &sc_if->arpcom.ac_if; 2408 2409 callout_stop(&sc_if->sk_tick_timer); 2410 2411 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2412 uint32_t val; 2413 2414 /* Put PHY back into reset. */ 2415 val = sk_win_read_4(sc, SK_GPIO); 2416 if (sc_if->sk_port == SK_PORT_A) { 2417 val |= SK_GPIO_DIR0; 2418 val &= ~SK_GPIO_DAT0; 2419 } else { 2420 val |= SK_GPIO_DIR2; 2421 val &= ~SK_GPIO_DAT2; 2422 } 2423 sk_win_write_4(sc, SK_GPIO, val); 2424 } 2425 2426 /* Turn off various components of this interface. */ 2427 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 2428 switch (sc->sk_type) { 2429 case SK_GENESIS: 2430 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_RESET); 2431 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_RESET); 2432 break; 2433 case SK_YUKON: 2434 SK_IF_WRITE_1(sc_if,0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_SET); 2435 SK_IF_WRITE_1(sc_if,0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_SET); 2436 break; 2437 } 2438 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_OFFLINE); 2439 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_RESET | SK_RBCTL_OFF); 2440 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_OFFLINE); 2441 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, 2442 SK_RBCTL_RESET | SK_RBCTL_OFF); 2443 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_OFF); 2444 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2445 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2446 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_OFF); 2447 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_OFF); 2448 2449 /* Disable interrupts */ 2450 if (sc_if->sk_port == SK_PORT_A) 2451 sc->sk_intrmask &= ~SK_INTRS1; 2452 else 2453 sc->sk_intrmask &= ~SK_INTRS2; 2454 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2455 2456 SK_XM_READ_2(sc_if, XM_ISR); 2457 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 2458 2459 /* Free RX and TX mbufs still in the queues. */ 2460 for (i = 0; i < SK_RX_RING_CNT; i++) { 2461 if (sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf != NULL) { 2462 m_freem(sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf); 2463 sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL; 2464 } 2465 } 2466 2467 for (i = 0; i < SK_TX_RING_CNT; i++) { 2468 if (sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf != NULL) { 2469 m_freem(sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf); 2470 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL; 2471 } 2472 } 2473 2474 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 2475 } 2476