1 /* 2 * Copyright (c) 1997, 1998, 1999, 2000 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $OpenBSD: if_sk.c,v 1.129 2006/10/16 12:30:08 tom Exp $ 33 * $FreeBSD: /c/ncvs/src/sys/pci/if_sk.c,v 1.20 2000/04/22 02:16:37 wpaul Exp $ 34 * $DragonFly: src/sys/dev/netif/sk/if_sk.c,v 1.53 2007/06/23 09:25:02 sephe Exp $ 35 */ 36 37 /* 38 * Copyright (c) 2003 Nathan L. Binkert <binkertn@umich.edu> 39 * 40 * Permission to use, copy, modify, and distribute this software for any 41 * purpose with or without fee is hereby granted, provided that the above 42 * copyright notice and this permission notice appear in all copies. 43 * 44 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 45 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 46 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 47 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 48 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 49 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 50 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 51 */ 52 53 /* 54 * SysKonnect SK-NET gigabit ethernet driver for FreeBSD. Supports 55 * the SK-984x series adapters, both single port and dual port. 56 * References: 57 * The XaQti XMAC II datasheet, 58 * http://www.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 59 * The SysKonnect GEnesis manual, http://www.syskonnect.com 60 * 61 * Note: XaQti has been acquired by Vitesse, and Vitesse does not have the 62 * XMAC II datasheet online. I have put my copy at people.freebsd.org as a 63 * convenience to others until Vitesse corrects this problem: 64 * 65 * http://people.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 66 * 67 * Written by Bill Paul <wpaul@ee.columbia.edu> 68 * Department of Electrical Engineering 69 * Columbia University, New York City 70 */ 71 72 /* 73 * The SysKonnect gigabit ethernet adapters consist of two main 74 * components: the SysKonnect GEnesis controller chip and the XaQti Corp. 75 * XMAC II gigabit ethernet MAC. The XMAC provides all of the MAC 76 * components and a PHY while the GEnesis controller provides a PCI 77 * interface with DMA support. Each card may have between 512K and 78 * 2MB of SRAM on board depending on the configuration. 79 * 80 * The SysKonnect GEnesis controller can have either one or two XMAC 81 * chips connected to it, allowing single or dual port NIC configurations. 82 * SysKonnect has the distinction of being the only vendor on the market 83 * with a dual port gigabit ethernet NIC. The GEnesis provides dual FIFOs, 84 * dual DMA queues, packet/MAC/transmit arbiters and direct access to the 85 * XMAC registers. This driver takes advantage of these features to allow 86 * both XMACs to operate as independent interfaces. 87 */ 88 89 #include <sys/param.h> 90 #include <sys/bus.h> 91 #include <sys/endian.h> 92 #include <sys/in_cksum.h> 93 #include <sys/kernel.h> 94 #include <sys/mbuf.h> 95 #include <sys/malloc.h> 96 #include <sys/queue.h> 97 #include <sys/rman.h> 98 #include <sys/serialize.h> 99 #include <sys/socket.h> 100 #include <sys/sockio.h> 101 #include <sys/sysctl.h> 102 103 #include <net/bpf.h> 104 #include <net/ethernet.h> 105 #include <net/if.h> 106 #include <net/if_arp.h> 107 #include <net/if_dl.h> 108 #include <net/if_media.h> 109 #include <net/ifq_var.h> 110 #include <net/vlan/if_vlan_var.h> 111 112 #include <netinet/ip.h> 113 #include <netinet/udp.h> 114 115 #include <dev/netif/mii_layer/mii.h> 116 #include <dev/netif/mii_layer/miivar.h> 117 #include <dev/netif/mii_layer/brgphyreg.h> 118 119 #include <bus/pci/pcireg.h> 120 #include <bus/pci/pcivar.h> 121 #include <bus/pci/pcidevs.h> 122 123 #include <dev/netif/sk/if_skreg.h> 124 #include <dev/netif/sk/yukonreg.h> 125 #include <dev/netif/sk/xmaciireg.h> 126 #include <dev/netif/sk/if_skvar.h> 127 128 #include "miibus_if.h" 129 130 #if 0 131 #define SK_DEBUG 132 #endif 133 134 #if 0 135 #define SK_RXCSUM 136 #endif 137 138 /* supported device vendors */ 139 static const struct skc_type { 140 uint16_t skc_vid; 141 uint16_t skc_did; 142 const char *skc_name; 143 } skc_devs[] = { 144 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C940, 145 "3Com 3C940" }, 146 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C940B, 147 "3Com 3C940B" }, 148 149 { PCI_VENDOR_CNET, PCI_PRODUCT_CNET_GIGACARD, 150 "CNet GigaCard" }, 151 152 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE530T_A1, 153 "D-Link DGE-530T A1" }, 154 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE530T_B1, 155 "D-Link DGE-530T B1" }, 156 157 { PCI_VENDOR_LINKSYS, PCI_PRODUCT_LINKSYS_EG1032, 158 "Linksys EG1032 v2" }, 159 { PCI_VENDOR_LINKSYS, PCI_PRODUCT_LINKSYS_EG1064, 160 "Linksys EG1064" }, 161 162 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON, 163 "Marvell Yukon 88E8001/8003/8010" }, 164 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_BELKIN, 165 "Belkin F5D5005" }, 166 167 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SKNET_GE, 168 "SysKonnect SK-NET" }, 169 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK9821v2, 170 "SysKonnect SK9821 v2" }, 171 172 { 0, 0, NULL } 173 }; 174 175 static int skc_probe(device_t); 176 static int skc_attach(device_t); 177 static int skc_detach(device_t); 178 static void skc_shutdown(device_t); 179 static int skc_sysctl_imtime(SYSCTL_HANDLER_ARGS); 180 181 static int sk_probe(device_t); 182 static int sk_attach(device_t); 183 static int sk_detach(device_t); 184 static void sk_tick(void *); 185 static void sk_yukon_tick(void *); 186 static void sk_intr(void *); 187 static void sk_intr_bcom(struct sk_if_softc *); 188 static void sk_intr_xmac(struct sk_if_softc *); 189 static void sk_intr_yukon(struct sk_if_softc *); 190 static void sk_rxeof(struct sk_if_softc *); 191 static void sk_txeof(struct sk_if_softc *); 192 static int sk_encap(struct sk_if_softc *, struct mbuf *, uint32_t *); 193 static void sk_start(struct ifnet *); 194 static int sk_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *); 195 static void sk_init(void *); 196 static void sk_init_xmac(struct sk_if_softc *); 197 static void sk_init_yukon(struct sk_if_softc *); 198 static void sk_stop(struct sk_if_softc *); 199 static void sk_watchdog(struct ifnet *); 200 static int sk_ifmedia_upd(struct ifnet *); 201 static void sk_ifmedia_sts(struct ifnet *, struct ifmediareq *); 202 static void sk_reset(struct sk_softc *); 203 static int sk_newbuf_jumbo(struct sk_if_softc *, int, int); 204 static int sk_newbuf_std(struct sk_if_softc *, int, int); 205 static int sk_jpool_alloc(device_t); 206 static void sk_jpool_free(struct sk_if_softc *); 207 static struct sk_jpool_entry 208 *sk_jalloc(struct sk_if_softc *); 209 static void sk_jfree(void *); 210 static void sk_jref(void *); 211 static int sk_init_rx_ring(struct sk_if_softc *); 212 static int sk_init_tx_ring(struct sk_if_softc *); 213 214 static int sk_miibus_readreg(device_t, int, int); 215 static int sk_miibus_writereg(device_t, int, int, int); 216 static void sk_miibus_statchg(device_t); 217 218 static int sk_xmac_miibus_readreg(struct sk_if_softc *, int, int); 219 static int sk_xmac_miibus_writereg(struct sk_if_softc *, int, int, int); 220 static void sk_xmac_miibus_statchg(struct sk_if_softc *); 221 222 static int sk_marv_miibus_readreg(struct sk_if_softc *, int, int); 223 static int sk_marv_miibus_writereg(struct sk_if_softc *, int, int, int); 224 static void sk_marv_miibus_statchg(struct sk_if_softc *); 225 226 static void sk_setfilt(struct sk_if_softc *, caddr_t, int); 227 static void sk_setmulti(struct sk_if_softc *); 228 static void sk_setpromisc(struct sk_if_softc *); 229 230 #ifdef SK_RXCSUM 231 static void sk_rxcsum(struct ifnet *, struct mbuf *, const uint16_t, 232 const uint16_t); 233 #endif 234 static int sk_dma_alloc(device_t); 235 static void sk_dma_free(device_t); 236 237 static void sk_buf_dma_addr(void *, bus_dma_segment_t *, int, bus_size_t, 238 int); 239 static void sk_dmamem_addr(void *, bus_dma_segment_t *, int, int); 240 241 #ifdef SK_DEBUG 242 #define DPRINTF(x) if (skdebug) kprintf x 243 #define DPRINTFN(n,x) if (skdebug >= (n)) kprintf x 244 static int skdebug = 2; 245 246 static void sk_dump_txdesc(struct sk_tx_desc *, int); 247 static void sk_dump_mbuf(struct mbuf *); 248 static void sk_dump_bytes(const char *, int); 249 #else 250 #define DPRINTF(x) 251 #define DPRINTFN(n,x) 252 #endif 253 254 /* Interrupt moderation time. */ 255 static int skc_imtime = SK_IMTIME_DEFAULT; 256 TUNABLE_INT("hw.skc.imtime", &skc_imtime); 257 258 /* 259 * Note that we have newbus methods for both the GEnesis controller 260 * itself and the XMAC(s). The XMACs are children of the GEnesis, and 261 * the miibus code is a child of the XMACs. We need to do it this way 262 * so that the miibus drivers can access the PHY registers on the 263 * right PHY. It's not quite what I had in mind, but it's the only 264 * design that achieves the desired effect. 265 */ 266 static device_method_t skc_methods[] = { 267 /* Device interface */ 268 DEVMETHOD(device_probe, skc_probe), 269 DEVMETHOD(device_attach, skc_attach), 270 DEVMETHOD(device_detach, skc_detach), 271 DEVMETHOD(device_shutdown, skc_shutdown), 272 273 /* bus interface */ 274 DEVMETHOD(bus_print_child, bus_generic_print_child), 275 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 276 277 { 0, 0 } 278 }; 279 280 static DEFINE_CLASS_0(skc, skc_driver, skc_methods, sizeof(struct sk_softc)); 281 static devclass_t skc_devclass; 282 283 static device_method_t sk_methods[] = { 284 /* Device interface */ 285 DEVMETHOD(device_probe, sk_probe), 286 DEVMETHOD(device_attach, sk_attach), 287 DEVMETHOD(device_detach, sk_detach), 288 DEVMETHOD(device_shutdown, bus_generic_shutdown), 289 290 /* bus interface */ 291 DEVMETHOD(bus_print_child, bus_generic_print_child), 292 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 293 294 /* MII interface */ 295 DEVMETHOD(miibus_readreg, sk_miibus_readreg), 296 DEVMETHOD(miibus_writereg, sk_miibus_writereg), 297 DEVMETHOD(miibus_statchg, sk_miibus_statchg), 298 299 { 0, 0 } 300 }; 301 302 static DEFINE_CLASS_0(sk, sk_driver, sk_methods, sizeof(struct sk_if_softc)); 303 static devclass_t sk_devclass; 304 305 DECLARE_DUMMY_MODULE(if_sk); 306 DRIVER_MODULE(if_sk, pci, skc_driver, skc_devclass, 0, 0); 307 DRIVER_MODULE(if_sk, skc, sk_driver, sk_devclass, 0, 0); 308 DRIVER_MODULE(miibus, sk, miibus_driver, miibus_devclass, 0, 0); 309 310 static __inline uint32_t 311 sk_win_read_4(struct sk_softc *sc, uint32_t reg) 312 { 313 return CSR_READ_4(sc, reg); 314 } 315 316 static __inline uint16_t 317 sk_win_read_2(struct sk_softc *sc, uint32_t reg) 318 { 319 return CSR_READ_2(sc, reg); 320 } 321 322 static __inline uint8_t 323 sk_win_read_1(struct sk_softc *sc, uint32_t reg) 324 { 325 return CSR_READ_1(sc, reg); 326 } 327 328 static __inline void 329 sk_win_write_4(struct sk_softc *sc, uint32_t reg, uint32_t x) 330 { 331 CSR_WRITE_4(sc, reg, x); 332 } 333 334 static __inline void 335 sk_win_write_2(struct sk_softc *sc, uint32_t reg, uint16_t x) 336 { 337 CSR_WRITE_2(sc, reg, x); 338 } 339 340 static __inline void 341 sk_win_write_1(struct sk_softc *sc, uint32_t reg, uint8_t x) 342 { 343 CSR_WRITE_1(sc, reg, x); 344 } 345 346 static __inline int 347 sk_newbuf(struct sk_if_softc *sc_if, int idx, int wait) 348 { 349 int ret; 350 351 if (sc_if->sk_use_jumbo) 352 ret = sk_newbuf_jumbo(sc_if, idx, wait); 353 else 354 ret = sk_newbuf_std(sc_if, idx, wait); 355 return ret; 356 } 357 358 static int 359 sk_miibus_readreg(device_t dev, int phy, int reg) 360 { 361 struct sk_if_softc *sc_if = device_get_softc(dev); 362 363 if (SK_IS_GENESIS(sc_if->sk_softc)) 364 return sk_xmac_miibus_readreg(sc_if, phy, reg); 365 else 366 return sk_marv_miibus_readreg(sc_if, phy, reg); 367 } 368 369 static int 370 sk_miibus_writereg(device_t dev, int phy, int reg, int val) 371 { 372 struct sk_if_softc *sc_if = device_get_softc(dev); 373 374 if (SK_IS_GENESIS(sc_if->sk_softc)) 375 return sk_xmac_miibus_writereg(sc_if, phy, reg, val); 376 else 377 return sk_marv_miibus_writereg(sc_if, phy, reg, val); 378 } 379 380 static void 381 sk_miibus_statchg(device_t dev) 382 { 383 struct sk_if_softc *sc_if = device_get_softc(dev); 384 385 if (SK_IS_GENESIS(sc_if->sk_softc)) 386 sk_xmac_miibus_statchg(sc_if); 387 else 388 sk_marv_miibus_statchg(sc_if); 389 } 390 391 static int 392 sk_xmac_miibus_readreg(struct sk_if_softc *sc_if, int phy, int reg) 393 { 394 int i; 395 396 DPRINTFN(9, ("sk_xmac_miibus_readreg\n")); 397 398 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC && phy != 0) 399 return(0); 400 401 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8)); 402 SK_XM_READ_2(sc_if, XM_PHY_DATA); 403 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) { 404 for (i = 0; i < SK_TIMEOUT; i++) { 405 DELAY(1); 406 if (SK_XM_READ_2(sc_if, XM_MMUCMD) & 407 XM_MMUCMD_PHYDATARDY) 408 break; 409 } 410 411 if (i == SK_TIMEOUT) { 412 if_printf(&sc_if->arpcom.ac_if, 413 "phy failed to come ready\n"); 414 return(0); 415 } 416 } 417 DELAY(1); 418 return(SK_XM_READ_2(sc_if, XM_PHY_DATA)); 419 } 420 421 static int 422 sk_xmac_miibus_writereg(struct sk_if_softc *sc_if, int phy, int reg, int val) 423 { 424 int i; 425 426 DPRINTFN(9, ("sk_xmac_miibus_writereg\n")); 427 428 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8)); 429 for (i = 0; i < SK_TIMEOUT; i++) { 430 if ((SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY) == 0) 431 break; 432 } 433 434 if (i == SK_TIMEOUT) { 435 if_printf(&sc_if->arpcom.ac_if, "phy failed to come ready\n"); 436 return(ETIMEDOUT); 437 } 438 439 SK_XM_WRITE_2(sc_if, XM_PHY_DATA, val); 440 for (i = 0; i < SK_TIMEOUT; i++) { 441 DELAY(1); 442 if ((SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY) == 0) 443 break; 444 } 445 446 if (i == SK_TIMEOUT) 447 if_printf(&sc_if->arpcom.ac_if, "phy write timed out\n"); 448 return(0); 449 } 450 451 static void 452 sk_xmac_miibus_statchg(struct sk_if_softc *sc_if) 453 { 454 struct mii_data *mii; 455 456 mii = device_get_softc(sc_if->sk_miibus); 457 DPRINTFN(9, ("sk_xmac_miibus_statchg\n")); 458 459 /* 460 * If this is a GMII PHY, manually set the XMAC's 461 * duplex mode accordingly. 462 */ 463 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) { 464 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) 465 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX); 466 else 467 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX); 468 } 469 } 470 471 static int 472 sk_marv_miibus_readreg(struct sk_if_softc *sc_if, int phy, int reg) 473 { 474 uint16_t val; 475 int i; 476 477 if (phy != 0 || 478 (sc_if->sk_phytype != SK_PHYTYPE_MARV_COPPER && 479 sc_if->sk_phytype != SK_PHYTYPE_MARV_FIBER)) { 480 DPRINTFN(9, ("sk_marv_miibus_readreg (skip) phy=%d, reg=%#x\n", 481 phy, reg)); 482 return(0); 483 } 484 485 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 486 YU_SMICR_REGAD(reg) | YU_SMICR_OP_READ); 487 488 for (i = 0; i < SK_TIMEOUT; i++) { 489 DELAY(1); 490 val = SK_YU_READ_2(sc_if, YUKON_SMICR); 491 if (val & YU_SMICR_READ_VALID) 492 break; 493 } 494 495 if (i == SK_TIMEOUT) { 496 if_printf(&sc_if->arpcom.ac_if, "phy failed to come ready\n"); 497 return(0); 498 } 499 500 DPRINTFN(9, ("sk_marv_miibus_readreg: i=%d, timeout=%d\n", i, 501 SK_TIMEOUT)); 502 503 val = SK_YU_READ_2(sc_if, YUKON_SMIDR); 504 505 DPRINTFN(9, ("sk_marv_miibus_readreg phy=%d, reg=%#x, val=%#x\n", 506 phy, reg, val)); 507 508 return(val); 509 } 510 511 static int 512 sk_marv_miibus_writereg(struct sk_if_softc *sc_if, int phy, int reg, int val) 513 { 514 int i; 515 516 DPRINTFN(9, ("sk_marv_miibus_writereg phy=%d reg=%#x val=%#x\n", 517 phy, reg, val)); 518 519 SK_YU_WRITE_2(sc_if, YUKON_SMIDR, val); 520 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 521 YU_SMICR_REGAD(reg) | YU_SMICR_OP_WRITE); 522 523 for (i = 0; i < SK_TIMEOUT; i++) { 524 DELAY(1); 525 if (SK_YU_READ_2(sc_if, YUKON_SMICR) & YU_SMICR_BUSY) 526 break; 527 } 528 529 if (i == SK_TIMEOUT) 530 if_printf(&sc_if->arpcom.ac_if, "phy write timed out\n"); 531 532 return(0); 533 } 534 535 static void 536 sk_marv_miibus_statchg(struct sk_if_softc *sc_if) 537 { 538 DPRINTFN(9, ("sk_marv_miibus_statchg: gpcr=%x\n", 539 SK_YU_READ_2(sc_if, YUKON_GPCR))); 540 } 541 542 #define HASH_BITS 6 543 544 static uint32_t 545 sk_xmac_hash(caddr_t addr) 546 { 547 uint32_t crc; 548 549 crc = ether_crc32_le(addr, ETHER_ADDR_LEN); 550 return (~crc & ((1 << HASH_BITS) - 1)); 551 } 552 553 static uint32_t 554 sk_yukon_hash(caddr_t addr) 555 { 556 uint32_t crc; 557 558 crc = ether_crc32_be(addr, ETHER_ADDR_LEN); 559 return (crc & ((1 << HASH_BITS) - 1)); 560 } 561 562 static void 563 sk_setfilt(struct sk_if_softc *sc_if, caddr_t addr, int slot) 564 { 565 int base; 566 567 base = XM_RXFILT_ENTRY(slot); 568 569 SK_XM_WRITE_2(sc_if, base, *(uint16_t *)(&addr[0])); 570 SK_XM_WRITE_2(sc_if, base + 2, *(uint16_t *)(&addr[2])); 571 SK_XM_WRITE_2(sc_if, base + 4, *(uint16_t *)(&addr[4])); 572 } 573 574 static void 575 sk_setmulti(struct sk_if_softc *sc_if) 576 { 577 struct sk_softc *sc = sc_if->sk_softc; 578 struct ifnet *ifp = &sc_if->arpcom.ac_if; 579 uint32_t hashes[2] = { 0, 0 }; 580 int h = 0, i; 581 struct ifmultiaddr *ifma; 582 uint8_t dummy[] = { 0, 0, 0, 0, 0 ,0 }; 583 584 /* First, zot all the existing filters. */ 585 switch(sc->sk_type) { 586 case SK_GENESIS: 587 for (i = 1; i < XM_RXFILT_MAX; i++) 588 sk_setfilt(sc_if, (caddr_t)&dummy, i); 589 590 SK_XM_WRITE_4(sc_if, XM_MAR0, 0); 591 SK_XM_WRITE_4(sc_if, XM_MAR2, 0); 592 break; 593 case SK_YUKON: 594 case SK_YUKON_LITE: 595 case SK_YUKON_LP: 596 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, 0); 597 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, 0); 598 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, 0); 599 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, 0); 600 break; 601 } 602 603 /* Now program new ones. */ 604 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 605 hashes[0] = 0xFFFFFFFF; 606 hashes[1] = 0xFFFFFFFF; 607 } else { 608 i = 1; 609 /* First find the tail of the list. */ 610 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 611 if (ifma->ifma_link.le_next == NULL) 612 break; 613 } 614 /* Now traverse the list backwards. */ 615 for (; ifma != NULL && ifma != (void *)&ifp->if_multiaddrs; 616 ifma = (struct ifmultiaddr *)ifma->ifma_link.le_prev) { 617 caddr_t maddr; 618 619 if (ifma->ifma_addr->sa_family != AF_LINK) 620 continue; 621 622 maddr = LLADDR((struct sockaddr_dl *)ifma->ifma_addr); 623 624 /* 625 * Program the first XM_RXFILT_MAX multicast groups 626 * into the perfect filter. For all others, 627 * use the hash table. 628 */ 629 if (SK_IS_GENESIS(sc) && i < XM_RXFILT_MAX) { 630 sk_setfilt(sc_if, maddr, i); 631 i++; 632 continue; 633 } 634 635 switch(sc->sk_type) { 636 case SK_GENESIS: 637 h = sk_xmac_hash(maddr); 638 break; 639 640 case SK_YUKON: 641 case SK_YUKON_LITE: 642 case SK_YUKON_LP: 643 h = sk_yukon_hash(maddr); 644 break; 645 } 646 if (h < 32) 647 hashes[0] |= (1 << h); 648 else 649 hashes[1] |= (1 << (h - 32)); 650 } 651 } 652 653 switch(sc->sk_type) { 654 case SK_GENESIS: 655 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_HASH| 656 XM_MODE_RX_USE_PERFECT); 657 SK_XM_WRITE_4(sc_if, XM_MAR0, hashes[0]); 658 SK_XM_WRITE_4(sc_if, XM_MAR2, hashes[1]); 659 break; 660 case SK_YUKON: 661 case SK_YUKON_LITE: 662 case SK_YUKON_LP: 663 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, hashes[0] & 0xffff); 664 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, (hashes[0] >> 16) & 0xffff); 665 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, hashes[1] & 0xffff); 666 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, (hashes[1] >> 16) & 0xffff); 667 break; 668 } 669 } 670 671 static void 672 sk_setpromisc(struct sk_if_softc *sc_if) 673 { 674 struct sk_softc *sc = sc_if->sk_softc; 675 struct ifnet *ifp = &sc_if->arpcom.ac_if; 676 677 switch(sc->sk_type) { 678 case SK_GENESIS: 679 if (ifp->if_flags & IFF_PROMISC) 680 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 681 else 682 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 683 break; 684 case SK_YUKON: 685 case SK_YUKON_LITE: 686 case SK_YUKON_LP: 687 if (ifp->if_flags & IFF_PROMISC) { 688 SK_YU_CLRBIT_2(sc_if, YUKON_RCR, 689 YU_RCR_UFLEN | YU_RCR_MUFLEN); 690 } else { 691 SK_YU_SETBIT_2(sc_if, YUKON_RCR, 692 YU_RCR_UFLEN | YU_RCR_MUFLEN); 693 } 694 break; 695 } 696 } 697 698 static int 699 sk_init_rx_ring(struct sk_if_softc *sc_if) 700 { 701 struct sk_chain_data *cd = &sc_if->sk_cdata; 702 struct sk_ring_data *rd = sc_if->sk_rdata; 703 int i, nexti, error; 704 705 bzero(rd->sk_rx_ring, sizeof(struct sk_rx_desc) * SK_RX_RING_CNT); 706 707 for (i = 0; i < SK_RX_RING_CNT; i++) { 708 if (i == (SK_RX_RING_CNT - 1)) 709 nexti = 0; 710 else 711 nexti = i + 1; 712 rd->sk_rx_ring[i].sk_next = 713 htole32(SK_RX_RING_ADDR(sc_if, nexti)); 714 rd->sk_rx_ring[i].sk_csum1_start = htole16(ETHER_HDR_LEN); 715 rd->sk_rx_ring[i].sk_csum2_start = 716 htole16(ETHER_HDR_LEN + sizeof(struct ip)); 717 718 error = sk_newbuf(sc_if, i, 1); 719 if (error) { 720 if_printf(&sc_if->arpcom.ac_if, 721 "failed alloc of %dth mbuf\n", i); 722 return error; 723 } 724 } 725 726 cd->sk_rx_prod = 0; 727 cd->sk_rx_cons = 0; 728 729 bus_dmamap_sync(sc_if->sk_rdata_dtag, sc_if->sk_rdata_dmap, 730 BUS_DMASYNC_PREWRITE); 731 732 return (0); 733 } 734 735 static int 736 sk_init_tx_ring(struct sk_if_softc *sc_if) 737 { 738 struct sk_ring_data *rd = sc_if->sk_rdata; 739 int i, nexti; 740 741 bzero(rd->sk_tx_ring, sizeof(struct sk_tx_desc) * SK_TX_RING_CNT); 742 743 for (i = 0; i < SK_TX_RING_CNT; i++) { 744 if (i == (SK_TX_RING_CNT - 1)) 745 nexti = 0; 746 else 747 nexti = i + 1; 748 rd->sk_tx_ring[i].sk_next = htole32(SK_TX_RING_ADDR(sc_if, nexti)); 749 } 750 751 sc_if->sk_cdata.sk_tx_prod = 0; 752 sc_if->sk_cdata.sk_tx_cons = 0; 753 sc_if->sk_cdata.sk_tx_cnt = 0; 754 755 bus_dmamap_sync(sc_if->sk_rdata_dtag, sc_if->sk_rdata_dmap, 756 BUS_DMASYNC_PREWRITE); 757 758 return (0); 759 } 760 761 static int 762 sk_newbuf_jumbo(struct sk_if_softc *sc_if, int idx, int wait) 763 { 764 struct sk_jpool_entry *entry; 765 struct mbuf *m_new = NULL; 766 struct sk_rx_desc *r; 767 768 KKASSERT(idx < SK_RX_RING_CNT && idx >= 0); 769 770 MGETHDR(m_new, wait ? MB_WAIT : MB_DONTWAIT, MT_DATA); 771 if (m_new == NULL) 772 return ENOBUFS; 773 774 /* Allocate the jumbo buffer */ 775 entry = sk_jalloc(sc_if); 776 if (entry == NULL) { 777 m_freem(m_new); 778 DPRINTFN(1, ("%s jumbo allocation failed -- packet " 779 "dropped!\n", sc_if->arpcom.ac_if.if_xname)); 780 return ENOBUFS; 781 } 782 783 m_new->m_ext.ext_arg = entry; 784 m_new->m_ext.ext_buf = entry->buf; 785 m_new->m_ext.ext_free = sk_jfree; 786 m_new->m_ext.ext_ref = sk_jref; 787 m_new->m_ext.ext_size = SK_JLEN; 788 789 m_new->m_flags |= M_EXT; 790 791 m_new->m_data = m_new->m_ext.ext_buf; 792 m_new->m_len = m_new->m_pkthdr.len = m_new->m_ext.ext_size; 793 794 /* 795 * Adjust alignment so packet payload begins on a 796 * longword boundary. Mandatory for Alpha, useful on 797 * x86 too. 798 */ 799 m_adj(m_new, ETHER_ALIGN); 800 801 sc_if->sk_cdata.sk_rx_mbuf[idx] = m_new; 802 803 r = &sc_if->sk_rdata->sk_rx_ring[idx]; 804 r->sk_data_lo = htole32(entry->paddr + ETHER_ALIGN); 805 r->sk_ctl = htole32(m_new->m_pkthdr.len | SK_RXSTAT); 806 807 return 0; 808 } 809 810 static int 811 sk_newbuf_std(struct sk_if_softc *sc_if, int idx, int wait) 812 { 813 struct mbuf *m_new = NULL; 814 struct sk_chain_data *cd = &sc_if->sk_cdata; 815 struct sk_rx_desc *r; 816 struct sk_dma_ctx ctx; 817 bus_dma_segment_t seg; 818 bus_dmamap_t map; 819 int error; 820 821 KKASSERT(idx < SK_RX_RING_CNT && idx >= 0); 822 823 m_new = m_getcl(wait ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR); 824 if (m_new == NULL) 825 return ENOBUFS; 826 827 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 828 829 /* 830 * Adjust alignment so packet payload begins on a 831 * longword boundary. Mandatory for Alpha, useful on 832 * x86 too. 833 */ 834 m_adj(m_new, ETHER_ALIGN); 835 836 bzero(&ctx, sizeof(ctx)); 837 ctx.nsegs = 1; 838 ctx.segs = &seg; 839 error = bus_dmamap_load_mbuf(cd->sk_rx_dtag, cd->sk_rx_dmap_tmp, 840 m_new, sk_buf_dma_addr, &ctx, 841 wait ? BUS_DMA_WAITOK : BUS_DMA_NOWAIT); 842 if (error) { 843 if_printf(&sc_if->arpcom.ac_if, "could not map RX mbuf\n"); 844 m_freem(m_new); 845 return error; 846 } 847 848 /* Unload originally mapped mbuf */ 849 if (cd->sk_rx_mbuf[idx] != NULL) 850 bus_dmamap_unload(cd->sk_rx_dtag, cd->sk_rx_dmap[idx]); 851 852 /* Switch DMA map with tmp DMA map */ 853 map = cd->sk_rx_dmap_tmp; 854 cd->sk_rx_dmap_tmp = cd->sk_rx_dmap[idx]; 855 cd->sk_rx_dmap[idx] = map; 856 857 cd->sk_rx_mbuf[idx] = m_new; 858 859 r = &sc_if->sk_rdata->sk_rx_ring[idx]; 860 r->sk_data_lo = htole32(seg.ds_addr); 861 r->sk_ctl = htole32(m_new->m_pkthdr.len | SK_RXSTAT); 862 863 return 0; 864 } 865 866 /* 867 * Allocate a jumbo buffer. 868 */ 869 struct sk_jpool_entry * 870 sk_jalloc(struct sk_if_softc *sc_if) 871 { 872 struct sk_chain_data *cd = &sc_if->sk_cdata; 873 struct sk_jpool_entry *entry; 874 875 lwkt_serialize_enter(&cd->sk_jpool_serializer); 876 877 entry = SLIST_FIRST(&cd->sk_jpool_free_ent); 878 if (entry != NULL) { 879 SLIST_REMOVE_HEAD(&cd->sk_jpool_free_ent, entry_next); 880 entry->inuse = 1; 881 } else { 882 DPRINTF(("no free jumbo buffer\n")); 883 } 884 885 lwkt_serialize_exit(&cd->sk_jpool_serializer); 886 return entry; 887 } 888 889 /* 890 * Release a jumbo buffer. 891 */ 892 void 893 sk_jfree(void *arg) 894 { 895 struct sk_jpool_entry *entry = arg; 896 struct sk_chain_data *cd = &entry->sc_if->sk_cdata; 897 898 if (&cd->sk_jpool_ent[entry->slot] != entry) 899 panic("%s: free wrong jumbo buffer\n", __func__); 900 else if (entry->inuse == 0) 901 panic("%s: jumbo buffer already freed\n", __func__); 902 903 lwkt_serialize_enter(&cd->sk_jpool_serializer); 904 905 atomic_subtract_int(&entry->inuse, 1); 906 if (entry->inuse == 0) 907 SLIST_INSERT_HEAD(&cd->sk_jpool_free_ent, entry, entry_next); 908 909 lwkt_serialize_exit(&cd->sk_jpool_serializer); 910 } 911 912 static void 913 sk_jref(void *arg) 914 { 915 struct sk_jpool_entry *entry = arg; 916 struct sk_chain_data *cd = &entry->sc_if->sk_cdata; 917 918 if (&cd->sk_jpool_ent[entry->slot] != entry) 919 panic("%s: free wrong jumbo buffer\n", __func__); 920 else if (entry->inuse == 0) 921 panic("%s: jumbo buffer already freed\n", __func__); 922 923 atomic_add_int(&entry->inuse, 1); 924 } 925 926 /* 927 * Set media options. 928 */ 929 static int 930 sk_ifmedia_upd(struct ifnet *ifp) 931 { 932 struct sk_if_softc *sc_if = ifp->if_softc; 933 struct mii_data *mii; 934 935 mii = device_get_softc(sc_if->sk_miibus); 936 sk_init(sc_if); 937 mii_mediachg(mii); 938 939 return(0); 940 } 941 942 /* 943 * Report current media status. 944 */ 945 static void 946 sk_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 947 { 948 struct sk_if_softc *sc_if; 949 struct mii_data *mii; 950 951 sc_if = ifp->if_softc; 952 mii = device_get_softc(sc_if->sk_miibus); 953 954 mii_pollstat(mii); 955 ifmr->ifm_active = mii->mii_media_active; 956 ifmr->ifm_status = mii->mii_media_status; 957 } 958 959 static int 960 sk_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr) 961 { 962 struct sk_if_softc *sc_if = ifp->if_softc; 963 struct ifreq *ifr = (struct ifreq *)data; 964 struct mii_data *mii; 965 int error = 0; 966 967 ASSERT_SERIALIZED(ifp->if_serializer); 968 969 switch(command) { 970 case SIOCSIFMTU: 971 if (ifr->ifr_mtu > SK_JUMBO_MTU) 972 error = EINVAL; 973 else { 974 ifp->if_mtu = ifr->ifr_mtu; 975 ifp->if_flags &= ~IFF_RUNNING; 976 sk_init(sc_if); 977 } 978 break; 979 case SIOCSIFFLAGS: 980 if (ifp->if_flags & IFF_UP) { 981 if (ifp->if_flags & IFF_RUNNING) { 982 if ((ifp->if_flags ^ sc_if->sk_if_flags) 983 & IFF_PROMISC) { 984 sk_setpromisc(sc_if); 985 sk_setmulti(sc_if); 986 } 987 } else 988 sk_init(sc_if); 989 } else { 990 if (ifp->if_flags & IFF_RUNNING) 991 sk_stop(sc_if); 992 } 993 sc_if->sk_if_flags = ifp->if_flags; 994 break; 995 case SIOCADDMULTI: 996 case SIOCDELMULTI: 997 sk_setmulti(sc_if); 998 break; 999 case SIOCGIFMEDIA: 1000 case SIOCSIFMEDIA: 1001 mii = device_get_softc(sc_if->sk_miibus); 1002 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1003 break; 1004 default: 1005 error = ether_ioctl(ifp, command, data); 1006 break; 1007 } 1008 1009 return(error); 1010 } 1011 1012 /* 1013 * Probe for a SysKonnect GEnesis chip. Check the PCI vendor and device 1014 * IDs against our list and return a device name if we find a match. 1015 */ 1016 static int 1017 skc_probe(device_t dev) 1018 { 1019 const struct skc_type *t; 1020 uint16_t vid, did; 1021 1022 vid = pci_get_vendor(dev); 1023 did = pci_get_device(dev); 1024 1025 /* 1026 * Only attach to rev.2 of the Linksys EG1032 adapter. 1027 * Rev.3 is supported by re(4). 1028 */ 1029 if (vid == PCI_VENDOR_LINKSYS && 1030 did == PCI_PRODUCT_LINKSYS_EG1032 && 1031 pci_get_subdevice(dev) != SUBDEVICEID_LINKSYS_EG1032_REV2) 1032 return ENXIO; 1033 1034 for (t = skc_devs; t->skc_name != NULL; t++) { 1035 if (vid == t->skc_vid && did == t->skc_did) { 1036 device_set_desc(dev, t->skc_name); 1037 return 0; 1038 } 1039 } 1040 return ENXIO; 1041 } 1042 1043 /* 1044 * Force the GEnesis into reset, then bring it out of reset. 1045 */ 1046 static void 1047 sk_reset(struct sk_softc *sc) 1048 { 1049 DPRINTFN(2, ("sk_reset\n")); 1050 1051 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_RESET); 1052 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_RESET); 1053 if (SK_IS_YUKON(sc)) 1054 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_SET); 1055 1056 DELAY(1000); 1057 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_UNRESET); 1058 DELAY(2); 1059 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_UNRESET); 1060 if (SK_IS_YUKON(sc)) 1061 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_CLEAR); 1062 1063 DPRINTFN(2, ("sk_reset: sk_csr=%x\n", CSR_READ_2(sc, SK_CSR))); 1064 DPRINTFN(2, ("sk_reset: sk_link_ctrl=%x\n", 1065 CSR_READ_2(sc, SK_LINK_CTRL))); 1066 1067 if (SK_IS_GENESIS(sc)) { 1068 /* Configure packet arbiter */ 1069 sk_win_write_2(sc, SK_PKTARB_CTL, SK_PKTARBCTL_UNRESET); 1070 sk_win_write_2(sc, SK_RXPA1_TINIT, SK_PKTARB_TIMEOUT); 1071 sk_win_write_2(sc, SK_TXPA1_TINIT, SK_PKTARB_TIMEOUT); 1072 sk_win_write_2(sc, SK_RXPA2_TINIT, SK_PKTARB_TIMEOUT); 1073 sk_win_write_2(sc, SK_TXPA2_TINIT, SK_PKTARB_TIMEOUT); 1074 } 1075 1076 /* Enable RAM interface */ 1077 sk_win_write_4(sc, SK_RAMCTL, SK_RAMCTL_UNRESET); 1078 1079 /* 1080 * Configure interrupt moderation. The moderation timer 1081 * defers interrupts specified in the interrupt moderation 1082 * timer mask based on the timeout specified in the interrupt 1083 * moderation timer init register. Each bit in the timer 1084 * register represents one tick, so to specify a timeout in 1085 * microseconds, we have to multiply by the correct number of 1086 * ticks-per-microsecond. 1087 */ 1088 KKASSERT(sc->sk_imtimer_ticks != 0 && sc->sk_imtime != 0); 1089 sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(sc, sc->sk_imtime)); 1090 sk_win_write_4(sc, SK_IMMR, SK_ISR_TX1_S_EOF|SK_ISR_TX2_S_EOF| 1091 SK_ISR_RX1_EOF|SK_ISR_RX2_EOF); 1092 sk_win_write_1(sc, SK_IMTIMERCTL, SK_IMCTL_START); 1093 } 1094 1095 static int 1096 sk_probe(device_t dev) 1097 { 1098 struct sk_softc *sc = device_get_softc(device_get_parent(dev)); 1099 const char *revstr = "", *name = NULL; 1100 char devname[80]; 1101 1102 switch (sc->sk_type) { 1103 case SK_GENESIS: 1104 name = "SysKonnect GEnesis"; 1105 break; 1106 case SK_YUKON: 1107 name = "Marvell Yukon"; 1108 break; 1109 case SK_YUKON_LITE: 1110 name = "Marvell Yukon Lite"; 1111 switch (sc->sk_rev) { 1112 case SK_YUKON_LITE_REV_A0: 1113 revstr = " rev.A0"; 1114 break; 1115 case SK_YUKON_LITE_REV_A1: 1116 revstr = " rev.A1"; 1117 break; 1118 case SK_YUKON_LITE_REV_A3: 1119 revstr = " rev.A3"; 1120 break; 1121 } 1122 break; 1123 case SK_YUKON_LP: 1124 name = "Marvell Yukon LP"; 1125 break; 1126 default: 1127 return ENXIO; 1128 } 1129 1130 ksnprintf(devname, sizeof(devname), "%s%s (0x%x)", 1131 name, revstr, sc->sk_rev); 1132 device_set_desc_copy(dev, devname); 1133 return 0; 1134 } 1135 1136 /* 1137 * Each XMAC chip is attached as a separate logical IP interface. 1138 * Single port cards will have only one logical interface of course. 1139 */ 1140 static int 1141 sk_attach(device_t dev) 1142 { 1143 struct sk_softc *sc = device_get_softc(device_get_parent(dev)); 1144 struct sk_if_softc *sc_if = device_get_softc(dev); 1145 struct ifnet *ifp = &sc_if->arpcom.ac_if; 1146 int i, error; 1147 1148 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1149 1150 sc_if->sk_port = *(int *)device_get_ivars(dev); 1151 KKASSERT(sc_if->sk_port == SK_PORT_A || sc_if->sk_port == SK_PORT_B); 1152 1153 sc_if->sk_softc = sc; 1154 sc->sk_if[sc_if->sk_port] = sc_if; 1155 1156 kfree(device_get_ivars(dev), M_DEVBUF); 1157 device_set_ivars(dev, NULL); 1158 1159 if (sc_if->sk_port == SK_PORT_A) 1160 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR0; 1161 if (sc_if->sk_port == SK_PORT_B) 1162 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR1; 1163 1164 DPRINTFN(2, ("begin sk_attach: port=%d\n", sc_if->sk_port)); 1165 1166 /* 1167 * Get station address for this interface. Note that 1168 * dual port cards actually come with three station 1169 * addresses: one for each port, plus an extra. The 1170 * extra one is used by the SysKonnect driver software 1171 * as a 'virtual' station address for when both ports 1172 * are operating in failover mode. Currently we don't 1173 * use this extra address. 1174 */ 1175 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1176 /* XXX */ 1177 sc_if->arpcom.ac_enaddr[i] = 1178 sk_win_read_1(sc, SK_MAC0_0 + (sc_if->sk_port * 8) + i); 1179 } 1180 1181 /* 1182 * Set up RAM buffer addresses. The NIC will have a certain 1183 * amount of SRAM on it, somewhere between 512K and 2MB. We 1184 * need to divide this up a) between the transmitter and 1185 * receiver and b) between the two XMACs, if this is a 1186 * dual port NIC. Our algorithm is to divide up the memory 1187 * evenly so that everyone gets a fair share. 1188 */ 1189 if (sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC) { 1190 uint32_t chunk, val; 1191 1192 chunk = sc->sk_ramsize / 2; 1193 val = sc->sk_rboff / sizeof(uint64_t); 1194 sc_if->sk_rx_ramstart = val; 1195 val += (chunk / sizeof(uint64_t)); 1196 sc_if->sk_rx_ramend = val - 1; 1197 sc_if->sk_tx_ramstart = val; 1198 val += (chunk / sizeof(uint64_t)); 1199 sc_if->sk_tx_ramend = val - 1; 1200 } else { 1201 uint32_t chunk, val; 1202 1203 chunk = sc->sk_ramsize / 4; 1204 val = (sc->sk_rboff + (chunk * 2 * sc_if->sk_port)) / 1205 sizeof(uint64_t); 1206 sc_if->sk_rx_ramstart = val; 1207 val += (chunk / sizeof(uint64_t)); 1208 sc_if->sk_rx_ramend = val - 1; 1209 sc_if->sk_tx_ramstart = val; 1210 val += (chunk / sizeof(uint64_t)); 1211 sc_if->sk_tx_ramend = val - 1; 1212 } 1213 1214 DPRINTFN(2, ("sk_attach: rx_ramstart=%#x rx_ramend=%#x\n" 1215 " tx_ramstart=%#x tx_ramend=%#x\n", 1216 sc_if->sk_rx_ramstart, sc_if->sk_rx_ramend, 1217 sc_if->sk_tx_ramstart, sc_if->sk_tx_ramend)); 1218 1219 /* Read and save PHY type */ 1220 sc_if->sk_phytype = sk_win_read_1(sc, SK_EPROM1) & 0xF; 1221 1222 /* Set PHY address */ 1223 if (SK_IS_GENESIS(sc)) { 1224 switch (sc_if->sk_phytype) { 1225 case SK_PHYTYPE_XMAC: 1226 sc_if->sk_phyaddr = SK_PHYADDR_XMAC; 1227 break; 1228 case SK_PHYTYPE_BCOM: 1229 sc_if->sk_phyaddr = SK_PHYADDR_BCOM; 1230 break; 1231 default: 1232 device_printf(dev, "unsupported PHY type: %d\n", 1233 sc_if->sk_phytype); 1234 error = ENXIO; 1235 goto fail; 1236 } 1237 } 1238 1239 if (SK_IS_YUKON(sc)) { 1240 if ((sc_if->sk_phytype < SK_PHYTYPE_MARV_COPPER && 1241 sc->sk_pmd != 'L' && sc->sk_pmd != 'S')) { 1242 /* not initialized, punt */ 1243 sc_if->sk_phytype = SK_PHYTYPE_MARV_COPPER; 1244 sc->sk_coppertype = 1; 1245 } 1246 1247 sc_if->sk_phyaddr = SK_PHYADDR_MARV; 1248 1249 if (!(sc->sk_coppertype)) 1250 sc_if->sk_phytype = SK_PHYTYPE_MARV_FIBER; 1251 } 1252 1253 error = sk_dma_alloc(dev); 1254 if (error) 1255 goto fail; 1256 1257 ifp->if_softc = sc_if; 1258 ifp->if_mtu = ETHERMTU; 1259 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1260 ifp->if_ioctl = sk_ioctl; 1261 ifp->if_start = sk_start; 1262 ifp->if_watchdog = sk_watchdog; 1263 ifp->if_init = sk_init; 1264 ifp->if_baudrate = 1000000000; 1265 ifq_set_maxlen(&ifp->if_snd, SK_TX_RING_CNT - 1); 1266 ifq_set_ready(&ifp->if_snd); 1267 1268 ifp->if_capabilities = IFCAP_VLAN_MTU; 1269 1270 /* Don't use jumbo buffers by default */ 1271 sc_if->sk_use_jumbo = 0; 1272 1273 /* 1274 * Do miibus setup. 1275 */ 1276 switch (sc->sk_type) { 1277 case SK_GENESIS: 1278 sk_init_xmac(sc_if); 1279 break; 1280 case SK_YUKON: 1281 case SK_YUKON_LITE: 1282 case SK_YUKON_LP: 1283 sk_init_yukon(sc_if); 1284 break; 1285 default: 1286 device_printf(dev, "unknown device type %d\n", sc->sk_type); 1287 error = ENXIO; 1288 goto fail; 1289 } 1290 1291 DPRINTFN(2, ("sk_attach: 1\n")); 1292 1293 error = mii_phy_probe(dev, &sc_if->sk_miibus, 1294 sk_ifmedia_upd, sk_ifmedia_sts); 1295 if (error) { 1296 device_printf(dev, "no PHY found!\n"); 1297 goto fail; 1298 } 1299 1300 callout_init(&sc_if->sk_tick_timer); 1301 1302 /* 1303 * Call MI attach routines. 1304 */ 1305 ether_ifattach(ifp, sc_if->arpcom.ac_enaddr, &sc->sk_serializer); 1306 1307 DPRINTFN(2, ("sk_attach: end\n")); 1308 return 0; 1309 fail: 1310 sk_detach(dev); 1311 sc->sk_if[sc_if->sk_port] = NULL; 1312 return error; 1313 } 1314 1315 /* 1316 * Attach the interface. Allocate softc structures, do ifmedia 1317 * setup and ethernet/BPF attach. 1318 */ 1319 static int 1320 skc_attach(device_t dev) 1321 { 1322 struct sk_softc *sc = device_get_softc(dev); 1323 uint8_t skrs; 1324 int *port; 1325 int error; 1326 1327 DPRINTFN(2, ("begin skc_attach\n")); 1328 1329 lwkt_serialize_init(&sc->sk_serializer); 1330 1331 #ifndef BURN_BRIDGES 1332 /* 1333 * Handle power management nonsense. 1334 */ 1335 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 1336 uint32_t iobase, membase, irq; 1337 1338 /* Save important PCI config data. */ 1339 iobase = pci_read_config(dev, SK_PCI_LOIO, 4); 1340 membase = pci_read_config(dev, SK_PCI_LOMEM, 4); 1341 irq = pci_read_config(dev, SK_PCI_INTLINE, 4); 1342 1343 /* Reset the power state. */ 1344 device_printf(dev, "chip is in D%d power mode " 1345 "-- setting to D0\n", pci_get_powerstate(dev)); 1346 1347 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 1348 1349 /* Restore PCI config data. */ 1350 pci_write_config(dev, SK_PCI_LOIO, iobase, 4); 1351 pci_write_config(dev, SK_PCI_LOMEM, membase, 4); 1352 pci_write_config(dev, SK_PCI_INTLINE, irq, 4); 1353 } 1354 #endif /* BURN_BRIDGES */ 1355 1356 /* 1357 * Map control/status registers. 1358 */ 1359 pci_enable_busmaster(dev); 1360 1361 sc->sk_res_rid = SK_PCI_LOMEM; 1362 sc->sk_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 1363 &sc->sk_res_rid, RF_ACTIVE); 1364 if (sc->sk_res == NULL) { 1365 device_printf(dev, "couldn't map memory\n"); 1366 error = ENXIO; 1367 goto fail; 1368 } 1369 sc->sk_btag = rman_get_bustag(sc->sk_res); 1370 sc->sk_bhandle = rman_get_bushandle(sc->sk_res); 1371 1372 sc->sk_type = sk_win_read_1(sc, SK_CHIPVER); 1373 sc->sk_rev = (sk_win_read_1(sc, SK_CONFIG) >> 4); 1374 1375 /* Bail out here if chip is not recognized */ 1376 if (!SK_IS_GENESIS(sc) && !SK_IS_YUKON(sc)) { 1377 device_printf(dev, "unknown chip type: %d\n", sc->sk_type); 1378 error = ENXIO; 1379 goto fail; 1380 } 1381 1382 DPRINTFN(2, ("skc_attach: allocate interrupt\n")); 1383 1384 /* Allocate interrupt */ 1385 sc->sk_irq_rid = 0; 1386 sc->sk_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->sk_irq_rid, 1387 RF_SHAREABLE | RF_ACTIVE); 1388 if (sc->sk_irq == NULL) { 1389 device_printf(dev, "couldn't map interrupt\n"); 1390 error = ENXIO; 1391 goto fail; 1392 } 1393 1394 switch (sc->sk_type) { 1395 case SK_GENESIS: 1396 sc->sk_imtimer_ticks = SK_IMTIMER_TICKS_GENESIS; 1397 break; 1398 default: 1399 sc->sk_imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 1400 break; 1401 } 1402 sc->sk_imtime = skc_imtime; 1403 1404 /* Reset the adapter. */ 1405 sk_reset(sc); 1406 1407 skrs = sk_win_read_1(sc, SK_EPROM0); 1408 if (SK_IS_GENESIS(sc)) { 1409 /* Read and save RAM size and RAMbuffer offset */ 1410 switch(skrs) { 1411 case SK_RAMSIZE_512K_64: 1412 sc->sk_ramsize = 0x80000; 1413 sc->sk_rboff = SK_RBOFF_0; 1414 break; 1415 case SK_RAMSIZE_1024K_64: 1416 sc->sk_ramsize = 0x100000; 1417 sc->sk_rboff = SK_RBOFF_80000; 1418 break; 1419 case SK_RAMSIZE_1024K_128: 1420 sc->sk_ramsize = 0x100000; 1421 sc->sk_rboff = SK_RBOFF_0; 1422 break; 1423 case SK_RAMSIZE_2048K_128: 1424 sc->sk_ramsize = 0x200000; 1425 sc->sk_rboff = SK_RBOFF_0; 1426 break; 1427 default: 1428 device_printf(dev, "unknown ram size: %d\n", skrs); 1429 error = ENXIO; 1430 goto fail; 1431 } 1432 } else { 1433 if (skrs == 0x00) 1434 sc->sk_ramsize = 0x20000; 1435 else 1436 sc->sk_ramsize = skrs * (1<<12); 1437 sc->sk_rboff = SK_RBOFF_0; 1438 } 1439 1440 DPRINTFN(2, ("skc_attach: ramsize=%d (%dk), rboff=%d\n", 1441 sc->sk_ramsize, sc->sk_ramsize / 1024, 1442 sc->sk_rboff)); 1443 1444 /* Read and save physical media type */ 1445 sc->sk_pmd = sk_win_read_1(sc, SK_PMDTYPE); 1446 1447 if (sc->sk_pmd == 'T' || sc->sk_pmd == '1') 1448 sc->sk_coppertype = 1; 1449 else 1450 sc->sk_coppertype = 0; 1451 1452 /* Yukon Lite Rev A0 needs special test, from sk98lin driver */ 1453 if (sc->sk_type == SK_YUKON || sc->sk_type == SK_YUKON_LP) { 1454 uint32_t flashaddr; 1455 uint8_t testbyte; 1456 1457 flashaddr = sk_win_read_4(sc, SK_EP_ADDR); 1458 1459 /* Test Flash-Address Register */ 1460 sk_win_write_1(sc, SK_EP_ADDR+3, 0xff); 1461 testbyte = sk_win_read_1(sc, SK_EP_ADDR+3); 1462 1463 if (testbyte != 0) { 1464 /* This is a Yukon Lite Rev A0 */ 1465 sc->sk_type = SK_YUKON_LITE; 1466 sc->sk_rev = SK_YUKON_LITE_REV_A0; 1467 /* Restore Flash-Address Register */ 1468 sk_win_write_4(sc, SK_EP_ADDR, flashaddr); 1469 } 1470 } 1471 1472 /* 1473 * Create sysctl nodes. 1474 */ 1475 sysctl_ctx_init(&sc->sk_sysctl_ctx); 1476 sc->sk_sysctl_tree = SYSCTL_ADD_NODE(&sc->sk_sysctl_ctx, 1477 SYSCTL_STATIC_CHILDREN(_hw), 1478 OID_AUTO, 1479 device_get_nameunit(dev), 1480 CTLFLAG_RD, 0, ""); 1481 if (sc->sk_sysctl_tree == NULL) { 1482 device_printf(dev, "can't add sysctl node\n"); 1483 error = ENXIO; 1484 goto fail; 1485 } 1486 SYSCTL_ADD_PROC(&sc->sk_sysctl_ctx, 1487 SYSCTL_CHILDREN(sc->sk_sysctl_tree), 1488 OID_AUTO, "imtime", CTLTYPE_INT | CTLFLAG_RW, 1489 sc, 0, skc_sysctl_imtime, "I", 1490 "Interrupt moderation time (usec)."); 1491 1492 sc->sk_devs[SK_PORT_A] = device_add_child(dev, "sk", -1); 1493 port = kmalloc(sizeof(*port), M_DEVBUF, M_WAITOK); 1494 *port = SK_PORT_A; 1495 device_set_ivars(sc->sk_devs[SK_PORT_A], port); 1496 1497 if (!(sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC)) { 1498 sc->sk_devs[SK_PORT_B] = device_add_child(dev, "sk", -1); 1499 port = kmalloc(sizeof(*port), M_DEVBUF, M_WAITOK); 1500 *port = SK_PORT_B; 1501 device_set_ivars(sc->sk_devs[SK_PORT_B], port); 1502 } 1503 1504 /* Turn on the 'driver is loaded' LED. */ 1505 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON); 1506 1507 bus_generic_attach(dev); 1508 1509 error = bus_setup_intr(dev, sc->sk_irq, INTR_NETSAFE, sk_intr, sc, 1510 &sc->sk_intrhand, &sc->sk_serializer); 1511 if (error) { 1512 device_printf(dev, "couldn't set up irq\n"); 1513 goto fail; 1514 } 1515 return 0; 1516 fail: 1517 skc_detach(dev); 1518 return error; 1519 } 1520 1521 static int 1522 sk_detach(device_t dev) 1523 { 1524 struct sk_if_softc *sc_if = device_get_softc(dev); 1525 struct ifnet *ifp = &sc_if->arpcom.ac_if; 1526 1527 if (device_is_attached(dev)) 1528 ether_ifdetach(ifp); 1529 1530 bus_generic_detach(dev); 1531 if (sc_if->sk_miibus != NULL) 1532 device_delete_child(dev, sc_if->sk_miibus); 1533 1534 sk_dma_free(dev); 1535 return 0; 1536 } 1537 1538 static int 1539 skc_detach(device_t dev) 1540 { 1541 struct sk_softc *sc = device_get_softc(dev); 1542 int *port; 1543 1544 if (device_is_attached(dev)) { 1545 lwkt_serialize_enter(&sc->sk_serializer); 1546 1547 if (sc->sk_if[SK_PORT_A] != NULL) 1548 sk_stop(sc->sk_if[SK_PORT_A]); 1549 if (sc->sk_if[SK_PORT_B] != NULL) 1550 sk_stop(sc->sk_if[SK_PORT_B]); 1551 1552 bus_teardown_intr(dev, sc->sk_irq, sc->sk_intrhand); 1553 1554 lwkt_serialize_exit(&sc->sk_serializer); 1555 } 1556 1557 bus_generic_detach(dev); 1558 if (sc->sk_devs[SK_PORT_A] != NULL) { 1559 port = device_get_ivars(sc->sk_devs[SK_PORT_A]); 1560 if (port != NULL) { 1561 kfree(port, M_DEVBUF); 1562 device_set_ivars(sc->sk_devs[SK_PORT_A], NULL); 1563 } 1564 device_delete_child(dev, sc->sk_devs[SK_PORT_A]); 1565 } 1566 if (sc->sk_devs[SK_PORT_B] != NULL) { 1567 port = device_get_ivars(sc->sk_devs[SK_PORT_B]); 1568 if (port != NULL) { 1569 kfree(port, M_DEVBUF); 1570 device_set_ivars(sc->sk_devs[SK_PORT_B], NULL); 1571 } 1572 device_delete_child(dev, sc->sk_devs[SK_PORT_B]); 1573 } 1574 1575 if (sc->sk_irq != NULL) { 1576 bus_release_resource(dev, SYS_RES_IRQ, sc->sk_irq_rid, 1577 sc->sk_irq); 1578 } 1579 if (sc->sk_res != NULL) { 1580 bus_release_resource(dev, SYS_RES_MEMORY, sc->sk_res_rid, 1581 sc->sk_res); 1582 } 1583 1584 if (sc->sk_sysctl_tree != NULL) 1585 sysctl_ctx_free(&sc->sk_sysctl_ctx); 1586 1587 return 0; 1588 } 1589 1590 static int 1591 sk_encap(struct sk_if_softc *sc_if, struct mbuf *m_head, uint32_t *txidx) 1592 { 1593 struct sk_chain_data *cd = &sc_if->sk_cdata; 1594 struct sk_ring_data *rd = sc_if->sk_rdata; 1595 struct sk_tx_desc *f = NULL; 1596 uint32_t frag, cur, sk_ctl; 1597 struct sk_dma_ctx ctx; 1598 bus_dma_segment_t segs[SK_NTXSEG]; 1599 bus_dmamap_t map; 1600 int i, error; 1601 1602 DPRINTFN(2, ("sk_encap\n")); 1603 1604 cur = frag = *txidx; 1605 1606 #ifdef SK_DEBUG 1607 if (skdebug >= 2) 1608 sk_dump_mbuf(m_head); 1609 #endif 1610 1611 map = cd->sk_tx_dmap[*txidx]; 1612 1613 /* 1614 * Start packing the mbufs in this chain into 1615 * the fragment pointers. Stop when we run out 1616 * of fragments or hit the end of the mbuf chain. 1617 */ 1618 ctx.nsegs = SK_NTXSEG; 1619 ctx.segs = segs; 1620 error = bus_dmamap_load_mbuf(cd->sk_tx_dtag, map, m_head, 1621 sk_buf_dma_addr, &ctx, BUS_DMA_NOWAIT); 1622 if (error) { 1623 if_printf(&sc_if->arpcom.ac_if, "could not map TX mbuf\n"); 1624 return ENOBUFS; 1625 } 1626 1627 if ((SK_TX_RING_CNT - (cd->sk_tx_cnt + ctx.nsegs)) < 2) { 1628 bus_dmamap_unload(cd->sk_tx_dtag, map); 1629 DPRINTFN(2, ("sk_encap: too few descriptors free\n")); 1630 return ENOBUFS; 1631 } 1632 1633 DPRINTFN(2, ("sk_encap: nsegs=%d\n", ctx.nsegs)); 1634 1635 /* Sync the DMA map. */ 1636 bus_dmamap_sync(cd->sk_tx_dtag, map, BUS_DMASYNC_PREWRITE); 1637 1638 for (i = 0; i < ctx.nsegs; i++) { 1639 f = &rd->sk_tx_ring[frag]; 1640 f->sk_data_lo = htole32(segs[i].ds_addr); 1641 sk_ctl = segs[i].ds_len | SK_OPCODE_DEFAULT; 1642 if (i == 0) 1643 sk_ctl |= SK_TXCTL_FIRSTFRAG; 1644 else 1645 sk_ctl |= SK_TXCTL_OWN; 1646 f->sk_ctl = htole32(sk_ctl); 1647 cur = frag; 1648 SK_INC(frag, SK_TX_RING_CNT); 1649 } 1650 1651 cd->sk_tx_mbuf[cur] = m_head; 1652 /* Switch DMA map */ 1653 cd->sk_tx_dmap[*txidx] = cd->sk_tx_dmap[cur]; 1654 cd->sk_tx_dmap[cur] = map; 1655 1656 rd->sk_tx_ring[cur].sk_ctl |= 1657 htole32(SK_TXCTL_LASTFRAG|SK_TXCTL_EOF_INTR); 1658 rd->sk_tx_ring[*txidx].sk_ctl |= htole32(SK_TXCTL_OWN); 1659 1660 /* Sync first descriptor to hand it off */ 1661 bus_dmamap_sync(sc_if->sk_rdata_dtag, sc_if->sk_rdata_dmap, 1662 BUS_DMASYNC_PREWRITE); 1663 1664 sc_if->sk_cdata.sk_tx_cnt += ctx.nsegs; 1665 1666 #ifdef SK_DEBUG 1667 if (skdebug >= 2) { 1668 struct sk_tx_desc *desc; 1669 uint32_t idx; 1670 1671 for (idx = *txidx; idx != frag; SK_INC(idx, SK_TX_RING_CNT)) { 1672 desc = &sc_if->sk_rdata->sk_tx_ring[idx]; 1673 sk_dump_txdesc(desc, idx); 1674 } 1675 } 1676 #endif 1677 1678 *txidx = frag; 1679 1680 DPRINTFN(2, ("sk_encap: completed successfully\n")); 1681 1682 return (0); 1683 } 1684 1685 static void 1686 sk_start(struct ifnet *ifp) 1687 { 1688 struct sk_if_softc *sc_if = ifp->if_softc; 1689 struct sk_softc *sc = sc_if->sk_softc; 1690 struct mbuf *m_head = NULL; 1691 uint32_t idx = sc_if->sk_cdata.sk_tx_prod; 1692 int pkts = 0; 1693 1694 DPRINTFN(2, ("sk_start\n")); 1695 1696 while (sc_if->sk_cdata.sk_tx_mbuf[idx] == NULL) { 1697 m_head = ifq_poll(&ifp->if_snd); 1698 if (m_head == NULL) 1699 break; 1700 1701 /* 1702 * Pack the data into the transmit ring. If we 1703 * don't have room, set the OACTIVE flag and wait 1704 * for the NIC to drain the ring. 1705 */ 1706 if (sk_encap(sc_if, m_head, &idx)) { 1707 ifp->if_flags |= IFF_OACTIVE; 1708 break; 1709 } 1710 1711 /* now we are committed to transmit the packet */ 1712 ifq_dequeue(&ifp->if_snd, m_head); 1713 pkts++; 1714 1715 BPF_MTAP(ifp, m_head); 1716 } 1717 if (pkts == 0) 1718 return; 1719 1720 /* Transmit */ 1721 if (idx != sc_if->sk_cdata.sk_tx_prod) { 1722 sc_if->sk_cdata.sk_tx_prod = idx; 1723 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START); 1724 1725 /* Set a timeout in case the chip goes out to lunch. */ 1726 ifp->if_timer = 5; 1727 } 1728 } 1729 1730 static void 1731 sk_watchdog(struct ifnet *ifp) 1732 { 1733 struct sk_if_softc *sc_if = ifp->if_softc; 1734 1735 ASSERT_SERIALIZED(ifp->if_serializer); 1736 /* 1737 * Reclaim first as there is a possibility of losing Tx completion 1738 * interrupts. 1739 */ 1740 sk_txeof(sc_if); 1741 if (sc_if->sk_cdata.sk_tx_cnt != 0) { 1742 if_printf(&sc_if->arpcom.ac_if, "watchdog timeout\n"); 1743 ifp->if_oerrors++; 1744 ifp->if_flags &= ~IFF_RUNNING; 1745 sk_init(sc_if); 1746 } 1747 } 1748 1749 static void 1750 skc_shutdown(device_t dev) 1751 { 1752 struct sk_softc *sc = device_get_softc(dev); 1753 1754 DPRINTFN(2, ("sk_shutdown\n")); 1755 1756 lwkt_serialize_enter(&sc->sk_serializer); 1757 1758 /* Turn off the 'driver is loaded' LED. */ 1759 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF); 1760 1761 /* 1762 * Reset the GEnesis controller. Doing this should also 1763 * assert the resets on the attached XMAC(s). 1764 */ 1765 sk_reset(sc); 1766 1767 lwkt_serialize_exit(&sc->sk_serializer); 1768 } 1769 1770 static __inline int 1771 sk_rxvalid(struct sk_softc *sc, uint32_t stat, uint32_t len) 1772 { 1773 if (sc->sk_type == SK_GENESIS) { 1774 if ((stat & XM_RXSTAT_ERRFRAME) == XM_RXSTAT_ERRFRAME || 1775 XM_RXSTAT_BYTES(stat) != len) 1776 return (0); 1777 } else { 1778 if ((stat & (YU_RXSTAT_CRCERR | YU_RXSTAT_LONGERR | 1779 YU_RXSTAT_MIIERR | YU_RXSTAT_BADFC | YU_RXSTAT_GOODFC | 1780 YU_RXSTAT_JABBER)) != 0 || 1781 (stat & YU_RXSTAT_RXOK) != YU_RXSTAT_RXOK || 1782 YU_RXSTAT_BYTES(stat) != len) 1783 return (0); 1784 } 1785 1786 return (1); 1787 } 1788 1789 static void 1790 sk_rxeof(struct sk_if_softc *sc_if) 1791 { 1792 struct sk_softc *sc = sc_if->sk_softc; 1793 struct ifnet *ifp = &sc_if->arpcom.ac_if; 1794 struct sk_chain_data *cd = &sc_if->sk_cdata; 1795 struct sk_ring_data *rd = sc_if->sk_rdata; 1796 int i, reap, max_frmlen; 1797 1798 DPRINTFN(2, ("sk_rxeof\n")); 1799 1800 i = cd->sk_rx_prod; 1801 1802 bus_dmamap_sync(sc_if->sk_rdata_dtag, sc_if->sk_rdata_dmap, 1803 BUS_DMASYNC_POSTREAD); 1804 if (sc_if->sk_use_jumbo) { 1805 bus_dmamap_sync(cd->sk_jpool_dtag, cd->sk_jpool_dmap, 1806 BUS_DMASYNC_POSTREAD); 1807 max_frmlen = SK_JUMBO_FRAMELEN; 1808 } else { 1809 max_frmlen = ETHER_MAX_LEN; 1810 } 1811 1812 reap = 0; 1813 for (;;) { 1814 struct sk_rx_desc *cur_desc; 1815 uint32_t rxstat, sk_ctl; 1816 #ifdef SK_RXCSUM 1817 uint16_t csum1, csum2; 1818 #endif 1819 int cur, total_len; 1820 struct mbuf *m; 1821 1822 cur = i; 1823 cur_desc = &rd->sk_rx_ring[cur]; 1824 1825 sk_ctl = le32toh(cur_desc->sk_ctl); 1826 if (sk_ctl & SK_RXCTL_OWN) { 1827 /* Invalidate the descriptor -- it's not ready yet */ 1828 cd->sk_rx_prod = cur; 1829 break; 1830 } 1831 1832 rxstat = le32toh(cur_desc->sk_xmac_rxstat); 1833 total_len = SK_RXBYTES(le32toh(cur_desc->sk_ctl)); 1834 1835 #ifdef SK_RXCSUM 1836 csum1 = le16toh(cur_desc->sk_csum1); 1837 csum2 = le16toh(cur_desc->sk_csum2); 1838 #endif 1839 1840 m = cd->sk_rx_mbuf[cur]; 1841 1842 /* 1843 * Bump 'i' here, so we can keep going, even if the current 1844 * RX descriptor reaping fails later. 'i' shoult NOT be used 1845 * in the following processing any more. 1846 */ 1847 SK_INC(i, SK_RX_RING_CNT); 1848 reap = 1; 1849 1850 if ((sk_ctl & (SK_RXCTL_STATUS_VALID | SK_RXCTL_FIRSTFRAG | 1851 SK_RXCTL_LASTFRAG)) != (SK_RXCTL_STATUS_VALID | 1852 SK_RXCTL_FIRSTFRAG | SK_RXCTL_LASTFRAG) || 1853 total_len < SK_MIN_FRAMELEN || total_len > max_frmlen || 1854 sk_rxvalid(sc, rxstat, total_len) == 0) { 1855 ifp->if_ierrors++; 1856 cur_desc->sk_ctl = htole32(m->m_pkthdr.len | SK_RXSTAT); 1857 continue; 1858 } 1859 1860 if (!sc_if->sk_use_jumbo) { 1861 bus_dmamap_sync(cd->sk_rx_dtag, cd->sk_rx_dmap[cur], 1862 BUS_DMASYNC_POSTREAD); 1863 } 1864 1865 /* 1866 * Try to allocate a new RX buffer. If that fails, 1867 * copy the packet to mbufs and put the RX buffer 1868 * back in the ring so it can be re-used. If 1869 * allocating mbufs fails, then we have to drop 1870 * the packet. 1871 */ 1872 if (sk_newbuf(sc_if, cur, 0)) { 1873 struct mbuf *m0; 1874 1875 cur_desc->sk_ctl = htole32(m->m_pkthdr.len | SK_RXSTAT); 1876 1877 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 1878 total_len + ETHER_ALIGN, 0, ifp, NULL); 1879 if (m0 == NULL) { 1880 ifp->if_ierrors++; 1881 continue; 1882 } 1883 m_adj(m0, ETHER_ALIGN); 1884 m = m0; 1885 } else { 1886 m->m_pkthdr.rcvif = ifp; 1887 m->m_pkthdr.len = m->m_len = total_len; 1888 } 1889 1890 #ifdef SK_RXCSUM 1891 sk_rxcsum(ifp, m, csum1, csum2); 1892 #endif 1893 1894 ifp->if_ipackets++; 1895 ifp->if_input(ifp, m); 1896 } 1897 1898 if (reap) { 1899 bus_dmamap_sync(sc_if->sk_rdata_dtag, sc_if->sk_rdata_dmap, 1900 BUS_DMASYNC_PREWRITE); 1901 } 1902 } 1903 1904 #ifdef SK_RXCSUM 1905 static void 1906 sk_rxcsum(struct ifnet *ifp, struct mbuf *m, 1907 const uint16_t csum1, const uint16_t csum2) 1908 { 1909 struct ether_header *eh; 1910 struct ip *ip; 1911 uint8_t *pp; 1912 int hlen, len, plen; 1913 uint16_t iph_csum, ipo_csum, ipd_csum, csum; 1914 1915 pp = mtod(m, uint8_t *); 1916 plen = m->m_pkthdr.len; 1917 if (plen < sizeof(*eh)) 1918 return; 1919 eh = (struct ether_header *)pp; 1920 iph_csum = in_addword(csum1, (~csum2 & 0xffff)); 1921 1922 if (eh->ether_type == htons(ETHERTYPE_VLAN)) { 1923 uint16_t *xp = (uint16_t *)pp; 1924 1925 xp = (uint16_t *)pp; 1926 if (xp[1] != htons(ETHERTYPE_IP)) 1927 return; 1928 iph_csum = in_addword(iph_csum, (~xp[0] & 0xffff)); 1929 iph_csum = in_addword(iph_csum, (~xp[1] & 0xffff)); 1930 xp = (uint16_t *)(pp + sizeof(struct ip)); 1931 iph_csum = in_addword(iph_csum, xp[0]); 1932 iph_csum = in_addword(iph_csum, xp[1]); 1933 pp += EVL_ENCAPLEN; 1934 } else if (eh->ether_type != htons(ETHERTYPE_IP)) { 1935 return; 1936 } 1937 1938 pp += sizeof(*eh); 1939 plen -= sizeof(*eh); 1940 1941 ip = (struct ip *)pp; 1942 1943 if (ip->ip_v != IPVERSION) 1944 return; 1945 1946 hlen = ip->ip_hl << 2; 1947 if (hlen < sizeof(struct ip)) 1948 return; 1949 if (hlen > ntohs(ip->ip_len)) 1950 return; 1951 1952 /* Don't deal with truncated or padded packets. */ 1953 if (plen != ntohs(ip->ip_len)) 1954 return; 1955 1956 len = hlen - sizeof(struct ip); 1957 if (len > 0) { 1958 uint16_t *p; 1959 1960 p = (uint16_t *)(ip + 1); 1961 ipo_csum = 0; 1962 for (ipo_csum = 0; len > 0; len -= sizeof(*p), p++) 1963 ipo_csum = in_addword(ipo_csum, *p); 1964 iph_csum = in_addword(iph_csum, ipo_csum); 1965 ipd_csum = in_addword(csum2, (~ipo_csum & 0xffff)); 1966 } else { 1967 ipd_csum = csum2; 1968 } 1969 1970 if (iph_csum != 0xffff) 1971 return; 1972 m->m_pkthdr.csum_flags = CSUM_IP_CHECKED | CSUM_IP_VALID; 1973 1974 if (ip->ip_off & htons(IP_MF | IP_OFFMASK)) 1975 return; /* ip frag, we're done for now */ 1976 1977 pp += hlen; 1978 1979 /* Only know checksum protocol for udp/tcp */ 1980 if (ip->ip_p == IPPROTO_UDP) { 1981 struct udphdr *uh = (struct udphdr *)pp; 1982 1983 if (uh->uh_sum == 0) /* udp with no checksum */ 1984 return; 1985 } else if (ip->ip_p != IPPROTO_TCP) { 1986 return; 1987 } 1988 1989 csum = in_pseudo(ip->ip_src.s_addr, ip->ip_dst.s_addr, 1990 htonl(ntohs(ip->ip_len) - hlen + ip->ip_p) + ipd_csum); 1991 if (csum == 0xffff) { 1992 m->m_pkthdr.csum_data = csum; 1993 m->m_pkthdr.csum_flags |= (CSUM_DATA_VALID | CSUM_PSEUDO_HDR); 1994 } 1995 } 1996 #endif 1997 1998 static void 1999 sk_txeof(struct sk_if_softc *sc_if) 2000 { 2001 struct sk_chain_data *cd = &sc_if->sk_cdata; 2002 struct ifnet *ifp = &sc_if->arpcom.ac_if; 2003 uint32_t idx; 2004 int reap = 0; 2005 2006 DPRINTFN(2, ("sk_txeof\n")); 2007 2008 bus_dmamap_sync(sc_if->sk_rdata_dtag, sc_if->sk_rdata_dmap, 2009 BUS_DMASYNC_POSTREAD); 2010 2011 /* 2012 * Go through our tx ring and free mbufs for those 2013 * frames that have been sent. 2014 */ 2015 idx = cd->sk_tx_cons; 2016 while (idx != cd->sk_tx_prod) { 2017 struct sk_tx_desc *cur_tx; 2018 uint32_t sk_ctl; 2019 2020 cur_tx = &sc_if->sk_rdata->sk_tx_ring[idx]; 2021 sk_ctl = le32toh(cur_tx->sk_ctl); 2022 #ifdef SK_DEBUG 2023 if (skdebug >= 2) 2024 sk_dump_txdesc(cur_tx, idx); 2025 #endif 2026 if (sk_ctl & SK_TXCTL_OWN) 2027 break; 2028 if (sk_ctl & SK_TXCTL_LASTFRAG) 2029 ifp->if_opackets++; 2030 if (cd->sk_tx_mbuf[idx] != NULL) { 2031 bus_dmamap_unload(cd->sk_tx_dtag, cd->sk_tx_dmap[idx]); 2032 m_freem(cd->sk_tx_mbuf[idx]); 2033 cd->sk_tx_mbuf[idx] = NULL; 2034 } 2035 sc_if->sk_cdata.sk_tx_cnt--; 2036 reap = 1; 2037 SK_INC(idx, SK_TX_RING_CNT); 2038 } 2039 ifp->if_timer = sc_if->sk_cdata.sk_tx_cnt > 0 ? 5 : 0; 2040 2041 if (sc_if->sk_cdata.sk_tx_cnt < SK_TX_RING_CNT - 2) 2042 ifp->if_flags &= ~IFF_OACTIVE; 2043 2044 sc_if->sk_cdata.sk_tx_cons = idx; 2045 2046 if (reap) { 2047 bus_dmamap_sync(sc_if->sk_rdata_dtag, sc_if->sk_rdata_dmap, 2048 BUS_DMASYNC_PREWRITE); 2049 } 2050 } 2051 2052 static void 2053 sk_tick(void *xsc_if) 2054 { 2055 struct sk_if_softc *sc_if = xsc_if; 2056 struct ifnet *ifp = &sc_if->arpcom.ac_if; 2057 struct mii_data *mii = device_get_softc(sc_if->sk_miibus); 2058 int i; 2059 2060 DPRINTFN(2, ("sk_tick\n")); 2061 2062 lwkt_serialize_enter(ifp->if_serializer); 2063 2064 if ((ifp->if_flags & IFF_UP) == 0) { 2065 lwkt_serialize_exit(ifp->if_serializer); 2066 return; 2067 } 2068 2069 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2070 sk_intr_bcom(sc_if); 2071 lwkt_serialize_exit(ifp->if_serializer); 2072 return; 2073 } 2074 2075 /* 2076 * According to SysKonnect, the correct way to verify that 2077 * the link has come back up is to poll bit 0 of the GPIO 2078 * register three times. This pin has the signal from the 2079 * link sync pin connected to it; if we read the same link 2080 * state 3 times in a row, we know the link is up. 2081 */ 2082 for (i = 0; i < 3; i++) { 2083 if (SK_XM_READ_2(sc_if, XM_GPIO) & XM_GPIO_GP0_SET) 2084 break; 2085 } 2086 2087 if (i != 3) { 2088 callout_reset(&sc_if->sk_tick_timer, hz, sk_tick, sc_if); 2089 lwkt_serialize_exit(ifp->if_serializer); 2090 return; 2091 } 2092 2093 /* Turn the GP0 interrupt back on. */ 2094 SK_XM_CLRBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET); 2095 SK_XM_READ_2(sc_if, XM_ISR); 2096 mii_tick(mii); 2097 callout_stop(&sc_if->sk_tick_timer); 2098 lwkt_serialize_exit(ifp->if_serializer); 2099 } 2100 2101 static void 2102 sk_yukon_tick(void *xsc_if) 2103 { 2104 struct sk_if_softc *sc_if = xsc_if; 2105 struct ifnet *ifp = &sc_if->arpcom.ac_if; 2106 struct mii_data *mii = device_get_softc(sc_if->sk_miibus); 2107 2108 lwkt_serialize_enter(ifp->if_serializer); 2109 mii_tick(mii); 2110 callout_reset(&sc_if->sk_tick_timer, hz, sk_yukon_tick, sc_if); 2111 lwkt_serialize_exit(ifp->if_serializer); 2112 } 2113 2114 static void 2115 sk_intr_bcom(struct sk_if_softc *sc_if) 2116 { 2117 struct mii_data *mii = device_get_softc(sc_if->sk_miibus); 2118 struct ifnet *ifp = &sc_if->arpcom.ac_if; 2119 int status; 2120 2121 DPRINTFN(2, ("sk_intr_bcom\n")); 2122 2123 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 2124 2125 /* 2126 * Read the PHY interrupt register to make sure 2127 * we clear any pending interrupts. 2128 */ 2129 status = sk_xmac_miibus_readreg(sc_if, SK_PHYADDR_BCOM, BRGPHY_MII_ISR); 2130 2131 if ((ifp->if_flags & IFF_RUNNING) == 0) { 2132 sk_init_xmac(sc_if); 2133 return; 2134 } 2135 2136 if (status & (BRGPHY_ISR_LNK_CHG|BRGPHY_ISR_AN_PR)) { 2137 int lstat; 2138 2139 lstat = sk_xmac_miibus_readreg(sc_if, SK_PHYADDR_BCOM, 2140 BRGPHY_MII_AUXSTS); 2141 2142 if (!(lstat & BRGPHY_AUXSTS_LINK) && sc_if->sk_link) { 2143 mii_mediachg(mii); 2144 /* Turn off the link LED. */ 2145 SK_IF_WRITE_1(sc_if, 0, 2146 SK_LINKLED1_CTL, SK_LINKLED_OFF); 2147 sc_if->sk_link = 0; 2148 } else if (status & BRGPHY_ISR_LNK_CHG) { 2149 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM, 2150 BRGPHY_MII_IMR, 0xFF00); 2151 mii_tick(mii); 2152 sc_if->sk_link = 1; 2153 /* Turn on the link LED. */ 2154 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, 2155 SK_LINKLED_ON|SK_LINKLED_LINKSYNC_OFF| 2156 SK_LINKLED_BLINK_OFF); 2157 } else { 2158 mii_tick(mii); 2159 callout_reset(&sc_if->sk_tick_timer, hz, 2160 sk_tick, sc_if); 2161 } 2162 } 2163 2164 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 2165 } 2166 2167 static void 2168 sk_intr_xmac(struct sk_if_softc *sc_if) 2169 { 2170 uint16_t status; 2171 2172 status = SK_XM_READ_2(sc_if, XM_ISR); 2173 DPRINTFN(2, ("sk_intr_xmac\n")); 2174 2175 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC && 2176 (status & (XM_ISR_GP0_SET | XM_ISR_AUTONEG_DONE))) { 2177 if (status & XM_ISR_GP0_SET) 2178 SK_XM_SETBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET); 2179 2180 callout_reset(&sc_if->sk_tick_timer, hz, 2181 sk_tick, sc_if); 2182 } 2183 2184 if (status & XM_IMR_TX_UNDERRUN) 2185 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_TXFIFO); 2186 2187 if (status & XM_IMR_RX_OVERRUN) 2188 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_RXFIFO); 2189 } 2190 2191 static void 2192 sk_intr_yukon(struct sk_if_softc *sc_if) 2193 { 2194 uint8_t status; 2195 2196 status = SK_IF_READ_1(sc_if, 0, SK_GMAC_ISR); 2197 /* RX overrun */ 2198 if ((status & SK_GMAC_INT_RX_OVER) != 0) { 2199 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, 2200 SK_RFCTL_RX_FIFO_OVER); 2201 } 2202 /* TX underrun */ 2203 if ((status & SK_GMAC_INT_TX_UNDER) != 0) { 2204 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, 2205 SK_TFCTL_TX_FIFO_UNDER); 2206 } 2207 2208 DPRINTFN(2, ("sk_intr_yukon status=%#x\n", status)); 2209 } 2210 2211 static void 2212 sk_intr(void *xsc) 2213 { 2214 struct sk_softc *sc = xsc; 2215 struct sk_if_softc *sc_if0 = sc->sk_if[SK_PORT_A]; 2216 struct sk_if_softc *sc_if1 = sc->sk_if[SK_PORT_B]; 2217 struct ifnet *ifp0 = NULL, *ifp1 = NULL; 2218 uint32_t status; 2219 2220 ASSERT_SERIALIZED(&sc->sk_serializer); 2221 2222 status = CSR_READ_4(sc, SK_ISSR); 2223 if (status == 0 || status == 0xffffffff) 2224 return; 2225 2226 if (sc_if0 != NULL) 2227 ifp0 = &sc_if0->arpcom.ac_if; 2228 if (sc_if1 != NULL) 2229 ifp1 = &sc_if1->arpcom.ac_if; 2230 2231 for (; (status &= sc->sk_intrmask) != 0;) { 2232 /* Handle receive interrupts first. */ 2233 if (sc_if0 && (status & SK_ISR_RX1_EOF)) { 2234 sk_rxeof(sc_if0); 2235 CSR_WRITE_4(sc, SK_BMU_RX_CSR0, 2236 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START); 2237 } 2238 if (sc_if1 && (status & SK_ISR_RX2_EOF)) { 2239 sk_rxeof(sc_if1); 2240 CSR_WRITE_4(sc, SK_BMU_RX_CSR1, 2241 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START); 2242 } 2243 2244 /* Then transmit interrupts. */ 2245 if (sc_if0 && (status & SK_ISR_TX1_S_EOF)) { 2246 sk_txeof(sc_if0); 2247 CSR_WRITE_4(sc, SK_BMU_TXS_CSR0, 2248 SK_TXBMU_CLR_IRQ_EOF); 2249 } 2250 if (sc_if1 && (status & SK_ISR_TX2_S_EOF)) { 2251 sk_txeof(sc_if1); 2252 CSR_WRITE_4(sc, SK_BMU_TXS_CSR1, 2253 SK_TXBMU_CLR_IRQ_EOF); 2254 } 2255 2256 /* Then MAC interrupts. */ 2257 if (sc_if0 && (status & SK_ISR_MAC1) && 2258 (ifp0->if_flags & IFF_RUNNING)) { 2259 if (SK_IS_GENESIS(sc)) 2260 sk_intr_xmac(sc_if0); 2261 else 2262 sk_intr_yukon(sc_if0); 2263 } 2264 2265 if (sc_if1 && (status & SK_ISR_MAC2) && 2266 (ifp1->if_flags & IFF_RUNNING)) { 2267 if (SK_IS_GENESIS(sc)) 2268 sk_intr_xmac(sc_if1); 2269 else 2270 sk_intr_yukon(sc_if1); 2271 } 2272 2273 if (status & SK_ISR_EXTERNAL_REG) { 2274 if (sc_if0 != NULL && 2275 sc_if0->sk_phytype == SK_PHYTYPE_BCOM) 2276 sk_intr_bcom(sc_if0); 2277 2278 if (sc_if1 != NULL && 2279 sc_if1->sk_phytype == SK_PHYTYPE_BCOM) 2280 sk_intr_bcom(sc_if1); 2281 } 2282 status = CSR_READ_4(sc, SK_ISSR); 2283 } 2284 2285 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2286 2287 if (ifp0 != NULL && !ifq_is_empty(&ifp0->if_snd)) 2288 sk_start(ifp0); 2289 if (ifp1 != NULL && !ifq_is_empty(&ifp1->if_snd)) 2290 sk_start(ifp1); 2291 } 2292 2293 static void 2294 sk_init_xmac(struct sk_if_softc *sc_if) 2295 { 2296 struct sk_softc *sc = sc_if->sk_softc; 2297 struct ifnet *ifp = &sc_if->arpcom.ac_if; 2298 static const struct sk_bcom_hack bhack[] = { 2299 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 }, { 0x17, 0x0013 }, 2300 { 0x15, 0x0404 }, { 0x17, 0x8006 }, { 0x15, 0x0132 }, { 0x17, 0x8006 }, 2301 { 0x15, 0x0232 }, { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 }, 2302 { 0, 0 } }; 2303 2304 DPRINTFN(2, ("sk_init_xmac\n")); 2305 2306 /* Unreset the XMAC. */ 2307 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_UNRESET); 2308 DELAY(1000); 2309 2310 /* Reset the XMAC's internal state. */ 2311 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 2312 2313 /* Save the XMAC II revision */ 2314 sc_if->sk_xmac_rev = XM_XMAC_REV(SK_XM_READ_4(sc_if, XM_DEVID)); 2315 2316 /* 2317 * Perform additional initialization for external PHYs, 2318 * namely for the 1000baseTX cards that use the XMAC's 2319 * GMII mode. 2320 */ 2321 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2322 int i = 0; 2323 uint32_t val; 2324 2325 /* Take PHY out of reset. */ 2326 val = sk_win_read_4(sc, SK_GPIO); 2327 if (sc_if->sk_port == SK_PORT_A) 2328 val |= SK_GPIO_DIR0|SK_GPIO_DAT0; 2329 else 2330 val |= SK_GPIO_DIR2|SK_GPIO_DAT2; 2331 sk_win_write_4(sc, SK_GPIO, val); 2332 2333 /* Enable GMII mode on the XMAC. */ 2334 SK_XM_SETBIT_2(sc_if, XM_HWCFG, XM_HWCFG_GMIIMODE); 2335 2336 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM, 2337 BRGPHY_MII_BMCR, BRGPHY_BMCR_RESET); 2338 DELAY(10000); 2339 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM, 2340 BRGPHY_MII_IMR, 0xFFF0); 2341 2342 /* 2343 * Early versions of the BCM5400 apparently have 2344 * a bug that requires them to have their reserved 2345 * registers initialized to some magic values. I don't 2346 * know what the numbers do, I'm just the messenger. 2347 */ 2348 if (sk_xmac_miibus_readreg(sc_if, SK_PHYADDR_BCOM, 0x03) 2349 == 0x6041) { 2350 while(bhack[i].reg) { 2351 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM, 2352 bhack[i].reg, bhack[i].val); 2353 i++; 2354 } 2355 } 2356 } 2357 2358 /* Set station address */ 2359 SK_XM_WRITE_2(sc_if, XM_PAR0, 2360 *(uint16_t *)(&sc_if->arpcom.ac_enaddr[0])); 2361 SK_XM_WRITE_2(sc_if, XM_PAR1, 2362 *(uint16_t *)(&sc_if->arpcom.ac_enaddr[2])); 2363 SK_XM_WRITE_2(sc_if, XM_PAR2, 2364 *(uint16_t *)(&sc_if->arpcom.ac_enaddr[4])); 2365 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_STATION); 2366 2367 if (ifp->if_flags & IFF_BROADCAST) 2368 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD); 2369 else 2370 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD); 2371 2372 /* We don't need the FCS appended to the packet. */ 2373 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_STRIPFCS); 2374 2375 /* We want short frames padded to 60 bytes. */ 2376 SK_XM_SETBIT_2(sc_if, XM_TXCMD, XM_TXCMD_AUTOPAD); 2377 2378 /* 2379 * Enable the reception of all error frames. This is 2380 * a necessary evil due to the design of the XMAC. The 2381 * XMAC's receive FIFO is only 8K in size, however jumbo 2382 * frames can be up to 9000 bytes in length. When bad 2383 * frame filtering is enabled, the XMAC's RX FIFO operates 2384 * in 'store and forward' mode. For this to work, the 2385 * entire frame has to fit into the FIFO, but that means 2386 * that jumbo frames larger than 8192 bytes will be 2387 * truncated. Disabling all bad frame filtering causes 2388 * the RX FIFO to operate in streaming mode, in which 2389 * case the XMAC will start transfering frames out of the 2390 * RX FIFO as soon as the FIFO threshold is reached. 2391 */ 2392 if (sc_if->sk_use_jumbo) { 2393 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_BADFRAMES| 2394 XM_MODE_RX_GIANTS|XM_MODE_RX_RUNTS|XM_MODE_RX_CRCERRS| 2395 XM_MODE_RX_INRANGELEN); 2396 } 2397 2398 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK); 2399 2400 /* 2401 * Bump up the transmit threshold. This helps hold off transmit 2402 * underruns when we're blasting traffic from both ports at once. 2403 */ 2404 SK_XM_WRITE_2(sc_if, XM_TX_REQTHRESH, SK_XM_TX_FIFOTHRESH); 2405 2406 /* Set promiscuous mode */ 2407 sk_setpromisc(sc_if); 2408 2409 /* Set multicast filter */ 2410 sk_setmulti(sc_if); 2411 2412 /* Clear and enable interrupts */ 2413 SK_XM_READ_2(sc_if, XM_ISR); 2414 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) 2415 SK_XM_WRITE_2(sc_if, XM_IMR, XM_INTRS); 2416 else 2417 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 2418 2419 /* Configure MAC arbiter */ 2420 switch(sc_if->sk_xmac_rev) { 2421 case XM_XMAC_REV_B2: 2422 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_B2); 2423 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_B2); 2424 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_B2); 2425 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_B2); 2426 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_B2); 2427 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_B2); 2428 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_B2); 2429 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_B2); 2430 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2); 2431 break; 2432 case XM_XMAC_REV_C1: 2433 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_C1); 2434 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_C1); 2435 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_C1); 2436 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_C1); 2437 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_C1); 2438 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_C1); 2439 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_C1); 2440 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_C1); 2441 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2); 2442 break; 2443 default: 2444 break; 2445 } 2446 sk_win_write_2(sc, SK_MACARB_CTL, 2447 SK_MACARBCTL_UNRESET|SK_MACARBCTL_FASTOE_OFF); 2448 2449 sc_if->sk_link = 1; 2450 } 2451 2452 static void 2453 sk_init_yukon(struct sk_if_softc *sc_if) 2454 { 2455 uint32_t phy, v; 2456 uint16_t reg; 2457 struct sk_softc *sc; 2458 int i; 2459 2460 sc = sc_if->sk_softc; 2461 2462 DPRINTFN(2, ("sk_init_yukon: start: sk_csr=%#x\n", 2463 CSR_READ_4(sc_if->sk_softc, SK_CSR))); 2464 2465 if (sc->sk_type == SK_YUKON_LITE && 2466 sc->sk_rev >= SK_YUKON_LITE_REV_A3) { 2467 /* 2468 * Workaround code for COMA mode, set PHY reset. 2469 * Otherwise it will not correctly take chip out of 2470 * powerdown (coma) 2471 */ 2472 v = sk_win_read_4(sc, SK_GPIO); 2473 v |= SK_GPIO_DIR9 | SK_GPIO_DAT9; 2474 sk_win_write_4(sc, SK_GPIO, v); 2475 } 2476 2477 DPRINTFN(6, ("sk_init_yukon: 1\n")); 2478 2479 /* GMAC and GPHY Reset */ 2480 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_SET); 2481 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 2482 DELAY(1000); 2483 2484 DPRINTFN(6, ("sk_init_yukon: 2\n")); 2485 2486 if (sc->sk_type == SK_YUKON_LITE && 2487 sc->sk_rev >= SK_YUKON_LITE_REV_A3) { 2488 /* 2489 * Workaround code for COMA mode, clear PHY reset 2490 */ 2491 v = sk_win_read_4(sc, SK_GPIO); 2492 v |= SK_GPIO_DIR9; 2493 v &= ~SK_GPIO_DAT9; 2494 sk_win_write_4(sc, SK_GPIO, v); 2495 } 2496 2497 phy = SK_GPHY_INT_POL_HI | SK_GPHY_DIS_FC | SK_GPHY_DIS_SLEEP | 2498 SK_GPHY_ENA_XC | SK_GPHY_ANEG_ALL | SK_GPHY_ENA_PAUSE; 2499 2500 if (sc->sk_coppertype) 2501 phy |= SK_GPHY_COPPER; 2502 else 2503 phy |= SK_GPHY_FIBER; 2504 2505 DPRINTFN(3, ("sk_init_yukon: phy=%#x\n", phy)); 2506 2507 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_SET); 2508 DELAY(1000); 2509 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_CLEAR); 2510 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_LOOP_OFF | 2511 SK_GMAC_PAUSE_ON | SK_GMAC_RESET_CLEAR); 2512 2513 DPRINTFN(3, ("sk_init_yukon: gmac_ctrl=%#x\n", 2514 SK_IF_READ_4(sc_if, 0, SK_GMAC_CTRL))); 2515 2516 DPRINTFN(6, ("sk_init_yukon: 3\n")); 2517 2518 /* unused read of the interrupt source register */ 2519 DPRINTFN(6, ("sk_init_yukon: 4\n")); 2520 SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 2521 2522 DPRINTFN(6, ("sk_init_yukon: 4a\n")); 2523 reg = SK_YU_READ_2(sc_if, YUKON_PAR); 2524 DPRINTFN(6, ("sk_init_yukon: YUKON_PAR=%#x\n", reg)); 2525 2526 /* MIB Counter Clear Mode set */ 2527 reg |= YU_PAR_MIB_CLR; 2528 DPRINTFN(6, ("sk_init_yukon: YUKON_PAR=%#x\n", reg)); 2529 DPRINTFN(6, ("sk_init_yukon: 4b\n")); 2530 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2531 2532 /* MIB Counter Clear Mode clear */ 2533 DPRINTFN(6, ("sk_init_yukon: 5\n")); 2534 reg &= ~YU_PAR_MIB_CLR; 2535 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2536 2537 /* receive control reg */ 2538 DPRINTFN(6, ("sk_init_yukon: 7\n")); 2539 SK_YU_WRITE_2(sc_if, YUKON_RCR, YU_RCR_CRCR); 2540 2541 /* transmit parameter register */ 2542 DPRINTFN(6, ("sk_init_yukon: 8\n")); 2543 SK_YU_WRITE_2(sc_if, YUKON_TPR, YU_TPR_JAM_LEN(0x3) | 2544 YU_TPR_JAM_IPG(0xb) | YU_TPR_JAM2DATA_IPG(0x1a) ); 2545 2546 /* serial mode register */ 2547 DPRINTFN(6, ("sk_init_yukon: 9\n")); 2548 reg = YU_SMR_DATA_BLIND(0x1c) | YU_SMR_MFL_VLAN | YU_SMR_IPG_DATA(0x1e); 2549 if (sc_if->sk_use_jumbo) 2550 reg |= YU_SMR_MFL_JUMBO; 2551 SK_YU_WRITE_2(sc_if, YUKON_SMR, reg); 2552 2553 DPRINTFN(6, ("sk_init_yukon: 10\n")); 2554 /* Setup Yukon's address */ 2555 for (i = 0; i < 3; i++) { 2556 /* Write Source Address 1 (unicast filter) */ 2557 SK_YU_WRITE_2(sc_if, YUKON_SAL1 + i * 4, 2558 sc_if->arpcom.ac_enaddr[i * 2] | 2559 sc_if->arpcom.ac_enaddr[i * 2 + 1] << 8); 2560 } 2561 2562 for (i = 0; i < 3; i++) { 2563 reg = sk_win_read_2(sc_if->sk_softc, 2564 SK_MAC1_0 + i * 2 + sc_if->sk_port * 8); 2565 SK_YU_WRITE_2(sc_if, YUKON_SAL2 + i * 4, reg); 2566 } 2567 2568 /* Set promiscuous mode */ 2569 sk_setpromisc(sc_if); 2570 2571 /* Set multicast filter */ 2572 DPRINTFN(6, ("sk_init_yukon: 11\n")); 2573 sk_setmulti(sc_if); 2574 2575 /* enable interrupt mask for counter overflows */ 2576 DPRINTFN(6, ("sk_init_yukon: 12\n")); 2577 SK_YU_WRITE_2(sc_if, YUKON_TIMR, 0); 2578 SK_YU_WRITE_2(sc_if, YUKON_RIMR, 0); 2579 SK_YU_WRITE_2(sc_if, YUKON_TRIMR, 0); 2580 2581 /* Configure RX MAC FIFO Flush Mask */ 2582 v = YU_RXSTAT_FOFL | YU_RXSTAT_CRCERR | YU_RXSTAT_MIIERR | 2583 YU_RXSTAT_BADFC | YU_RXSTAT_GOODFC | YU_RXSTAT_RUNT | 2584 YU_RXSTAT_JABBER; 2585 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_FLUSH_MASK, v); 2586 2587 /* Disable RX MAC FIFO Flush for YUKON-Lite Rev. A0 only */ 2588 if (sc->sk_type == SK_YUKON_LITE && sc->sk_rev == SK_YUKON_LITE_REV_A0) 2589 v = SK_TFCTL_OPERATION_ON; 2590 else 2591 v = SK_TFCTL_OPERATION_ON | SK_RFCTL_FIFO_FLUSH_ON; 2592 /* Configure RX MAC FIFO */ 2593 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_CLEAR); 2594 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_CTRL_TEST, v); 2595 2596 /* Increase flush threshould to 64 bytes */ 2597 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_FLUSH_THRESHOLD, 2598 SK_RFCTL_FIFO_THRESHOLD + 1); 2599 2600 /* Configure TX MAC FIFO */ 2601 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_CLEAR); 2602 SK_IF_WRITE_2(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_OPERATION_ON); 2603 2604 DPRINTFN(6, ("sk_init_yukon: end\n")); 2605 } 2606 2607 /* 2608 * Note that to properly initialize any part of the GEnesis chip, 2609 * you first have to take it out of reset mode. 2610 */ 2611 static void 2612 sk_init(void *xsc_if) 2613 { 2614 struct sk_if_softc *sc_if = xsc_if; 2615 struct sk_softc *sc = sc_if->sk_softc; 2616 struct ifnet *ifp = &sc_if->arpcom.ac_if; 2617 struct mii_data *mii = device_get_softc(sc_if->sk_miibus); 2618 2619 DPRINTFN(2, ("sk_init\n")); 2620 2621 ASSERT_SERIALIZED(ifp->if_serializer); 2622 2623 if (ifp->if_flags & IFF_RUNNING) 2624 return; 2625 2626 /* Cancel pending I/O and free all RX/TX buffers. */ 2627 sk_stop(sc_if); 2628 2629 /* 2630 * NOTE: Change sk_use_jumbo after sk_stop(), 2631 * but before real initialization. 2632 */ 2633 if (ifp->if_mtu > ETHER_MAX_LEN) 2634 sc_if->sk_use_jumbo = 1; 2635 else 2636 sc_if->sk_use_jumbo = 0; 2637 DPRINTF(("use jumbo buffer: %s\n", sc_if->sk_use_jumbo ? "YES" : "NO")); 2638 2639 if (SK_IS_GENESIS(sc)) { 2640 /* Configure LINK_SYNC LED */ 2641 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_ON); 2642 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, 2643 SK_LINKLED_LINKSYNC_ON); 2644 2645 /* Configure RX LED */ 2646 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, 2647 SK_RXLEDCTL_COUNTER_START); 2648 2649 /* Configure TX LED */ 2650 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, 2651 SK_TXLEDCTL_COUNTER_START); 2652 } 2653 2654 /* 2655 * Configure descriptor poll timer 2656 * 2657 * SK-NET GENESIS data sheet says that possibility of losing Start 2658 * transmit command due to CPU/cache related interim storage problems 2659 * under certain conditions. The document recommends a polling 2660 * mechanism to send a Start transmit command to initiate transfer 2661 * of ready descriptors regulary. To cope with this issue sk(4) now 2662 * enables descriptor poll timer to initiate descriptor processing 2663 * periodically as defined by SK_DPT_TIMER_MAX. However sk(4) still 2664 * issue SK_TXBMU_TX_START to Tx BMU to get fast execution of Tx 2665 * command instead of waiting for next descriptor polling time. 2666 * The same rule may apply to Rx side too but it seems that is not 2667 * needed at the moment. 2668 * Since sk(4) uses descriptor polling as a last resort there is no 2669 * need to set smaller polling time than maximum allowable one. 2670 */ 2671 SK_IF_WRITE_4(sc_if, 0, SK_DPT_INIT, SK_DPT_TIMER_MAX); 2672 2673 /* Configure I2C registers */ 2674 2675 /* Configure XMAC(s) */ 2676 switch (sc->sk_type) { 2677 case SK_GENESIS: 2678 sk_init_xmac(sc_if); 2679 break; 2680 case SK_YUKON: 2681 case SK_YUKON_LITE: 2682 case SK_YUKON_LP: 2683 sk_init_yukon(sc_if); 2684 break; 2685 } 2686 mii_mediachg(mii); 2687 2688 if (SK_IS_GENESIS(sc)) { 2689 /* Configure MAC FIFOs */ 2690 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_UNRESET); 2691 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_END, SK_FIFO_END); 2692 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_ON); 2693 2694 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_UNRESET); 2695 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_END, SK_FIFO_END); 2696 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_ON); 2697 } 2698 2699 /* Configure transmit arbiter(s) */ 2700 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, 2701 SK_TXARCTL_ON | SK_TXARCTL_FSYNC_ON); 2702 2703 /* Configure RAMbuffers */ 2704 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_UNRESET); 2705 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_START, sc_if->sk_rx_ramstart); 2706 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_WR_PTR, sc_if->sk_rx_ramstart); 2707 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_RD_PTR, sc_if->sk_rx_ramstart); 2708 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_END, sc_if->sk_rx_ramend); 2709 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_ON); 2710 2711 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_UNRESET); 2712 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_STORENFWD_ON); 2713 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_START, sc_if->sk_tx_ramstart); 2714 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_WR_PTR, sc_if->sk_tx_ramstart); 2715 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_RD_PTR, sc_if->sk_tx_ramstart); 2716 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_END, sc_if->sk_tx_ramend); 2717 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_ON); 2718 2719 /* Configure BMUs */ 2720 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_ONLINE); 2721 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_LO, 2722 SK_RX_RING_ADDR(sc_if, 0)); 2723 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_HI, 0); 2724 2725 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_ONLINE); 2726 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_LO, 2727 SK_TX_RING_ADDR(sc_if, 0)); 2728 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_HI, 0); 2729 2730 /* Init descriptors */ 2731 if (sk_init_rx_ring(sc_if) == ENOBUFS) { 2732 if_printf(ifp, "initialization failed: " 2733 "no memory for rx buffers\n"); 2734 sk_stop(sc_if); 2735 return; 2736 } 2737 2738 if (sk_init_tx_ring(sc_if) == ENOBUFS) { 2739 if_printf(ifp, "initialization failed: " 2740 "no memory for tx buffers\n"); 2741 sk_stop(sc_if); 2742 return; 2743 } 2744 2745 /* Configure interrupt handling */ 2746 CSR_READ_4(sc, SK_ISSR); 2747 if (sc_if->sk_port == SK_PORT_A) 2748 sc->sk_intrmask |= SK_INTRS1; 2749 else 2750 sc->sk_intrmask |= SK_INTRS2; 2751 2752 sc->sk_intrmask |= SK_ISR_EXTERNAL_REG; 2753 2754 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2755 2756 /* Start BMUs. */ 2757 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_RX_START); 2758 2759 if (SK_IS_GENESIS(sc)) { 2760 /* Enable XMACs TX and RX state machines */ 2761 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_IGNPAUSE); 2762 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, 2763 XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 2764 } 2765 2766 if (SK_IS_YUKON(sc)) { 2767 uint16_t reg = SK_YU_READ_2(sc_if, YUKON_GPCR); 2768 reg |= YU_GPCR_TXEN | YU_GPCR_RXEN; 2769 #if 0 2770 /* XXX disable 100Mbps and full duplex mode? */ 2771 reg &= ~(YU_GPCR_SPEED | YU_GPCR_DPLX_DIS); 2772 #endif 2773 SK_YU_WRITE_2(sc_if, YUKON_GPCR, reg); 2774 } 2775 2776 /* Activate descriptor polling timer */ 2777 SK_IF_WRITE_4(sc_if, 0, SK_DPT_TIMER_CTRL, SK_DPT_TCTL_START); 2778 /* Start transfer of Tx descriptors */ 2779 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START); 2780 2781 ifp->if_flags |= IFF_RUNNING; 2782 ifp->if_flags &= ~IFF_OACTIVE; 2783 2784 if (SK_IS_YUKON(sc)) 2785 callout_reset(&sc_if->sk_tick_timer, hz, sk_yukon_tick, sc_if); 2786 } 2787 2788 static void 2789 sk_stop(struct sk_if_softc *sc_if) 2790 { 2791 struct sk_softc *sc = sc_if->sk_softc; 2792 struct ifnet *ifp = &sc_if->arpcom.ac_if; 2793 struct sk_chain_data *cd = &sc_if->sk_cdata; 2794 uint32_t val; 2795 int i; 2796 2797 ASSERT_SERIALIZED(ifp->if_serializer); 2798 2799 DPRINTFN(2, ("sk_stop\n")); 2800 2801 callout_stop(&sc_if->sk_tick_timer); 2802 2803 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 2804 2805 /* Stop Tx descriptor polling timer */ 2806 SK_IF_WRITE_4(sc_if, 0, SK_DPT_TIMER_CTRL, SK_DPT_TCTL_STOP); 2807 2808 /* Stop transfer of Tx descriptors */ 2809 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_STOP); 2810 for (i = 0; i < SK_TIMEOUT; i++) { 2811 val = CSR_READ_4(sc, sc_if->sk_tx_bmu); 2812 if (!(val & SK_TXBMU_TX_STOP)) 2813 break; 2814 DELAY(1); 2815 } 2816 if (i == SK_TIMEOUT) 2817 if_printf(ifp, "cannot stop transfer of Tx descriptors\n"); 2818 2819 /* Stop transfer of Rx descriptors */ 2820 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_RX_STOP); 2821 for (i = 0; i < SK_TIMEOUT; i++) { 2822 val = SK_IF_READ_4(sc_if, 0, SK_RXQ1_BMU_CSR); 2823 if (!(val & SK_RXBMU_RX_STOP)) 2824 break; 2825 DELAY(1); 2826 } 2827 if (i == SK_TIMEOUT) 2828 if_printf(ifp, "cannot stop transfer of Rx descriptors\n"); 2829 2830 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2831 /* Put PHY back into reset. */ 2832 val = sk_win_read_4(sc, SK_GPIO); 2833 if (sc_if->sk_port == SK_PORT_A) { 2834 val |= SK_GPIO_DIR0; 2835 val &= ~SK_GPIO_DAT0; 2836 } else { 2837 val |= SK_GPIO_DIR2; 2838 val &= ~SK_GPIO_DAT2; 2839 } 2840 sk_win_write_4(sc, SK_GPIO, val); 2841 } 2842 2843 /* Turn off various components of this interface. */ 2844 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 2845 switch (sc->sk_type) { 2846 case SK_GENESIS: 2847 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_RESET); 2848 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_RESET); 2849 break; 2850 case SK_YUKON: 2851 case SK_YUKON_LITE: 2852 case SK_YUKON_LP: 2853 SK_IF_WRITE_1(sc_if,0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_SET); 2854 SK_IF_WRITE_1(sc_if,0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_SET); 2855 break; 2856 } 2857 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_OFFLINE); 2858 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_RESET | SK_RBCTL_OFF); 2859 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_OFFLINE); 2860 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, 2861 SK_RBCTL_RESET | SK_RBCTL_OFF); 2862 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_OFF); 2863 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2864 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2865 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_OFF); 2866 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_OFF); 2867 2868 /* Disable interrupts */ 2869 if (sc_if->sk_port == SK_PORT_A) 2870 sc->sk_intrmask &= ~SK_INTRS1; 2871 else 2872 sc->sk_intrmask &= ~SK_INTRS2; 2873 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2874 2875 SK_XM_READ_2(sc_if, XM_ISR); 2876 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 2877 2878 /* Free RX and TX mbufs still in the queues. */ 2879 for (i = 0; i < SK_RX_RING_CNT; i++) { 2880 if (cd->sk_rx_mbuf[i] != NULL) { 2881 if (!sc_if->sk_use_jumbo) { 2882 bus_dmamap_unload(cd->sk_rx_dtag, 2883 cd->sk_rx_dmap[i]); 2884 } 2885 m_freem(cd->sk_rx_mbuf[i]); 2886 cd->sk_rx_mbuf[i] = NULL; 2887 } 2888 } 2889 for (i = 0; i < SK_TX_RING_CNT; i++) { 2890 if (cd->sk_tx_mbuf[i] != NULL) { 2891 bus_dmamap_unload(cd->sk_tx_dtag, cd->sk_tx_dmap[i]); 2892 m_freem(cd->sk_tx_mbuf[i]); 2893 cd->sk_tx_mbuf[i] = NULL; 2894 } 2895 } 2896 } 2897 2898 #ifdef SK_DEBUG 2899 static void 2900 sk_dump_txdesc(struct sk_tx_desc *desc, int idx) 2901 { 2902 #define DESC_PRINT(X) \ 2903 if (X) \ 2904 kprintf("txdesc[%d]." #X "=%#x\n", \ 2905 idx, X); 2906 2907 DESC_PRINT(le32toh(desc->sk_ctl)); 2908 DESC_PRINT(le32toh(desc->sk_next)); 2909 DESC_PRINT(le32toh(desc->sk_data_lo)); 2910 DESC_PRINT(le32toh(desc->sk_data_hi)); 2911 DESC_PRINT(le32toh(desc->sk_xmac_txstat)); 2912 DESC_PRINT(le16toh(desc->sk_rsvd0)); 2913 DESC_PRINT(le16toh(desc->sk_csum_startval)); 2914 DESC_PRINT(le16toh(desc->sk_csum_startpos)); 2915 DESC_PRINT(le16toh(desc->sk_csum_writepos)); 2916 DESC_PRINT(le16toh(desc->sk_rsvd1)); 2917 #undef PRINT 2918 } 2919 2920 static void 2921 sk_dump_bytes(const char *data, int len) 2922 { 2923 int c, i, j; 2924 2925 for (i = 0; i < len; i += 16) { 2926 kprintf("%08x ", i); 2927 c = len - i; 2928 if (c > 16) c = 16; 2929 2930 for (j = 0; j < c; j++) { 2931 kprintf("%02x ", data[i + j] & 0xff); 2932 if ((j & 0xf) == 7 && j > 0) 2933 kprintf(" "); 2934 } 2935 2936 for (; j < 16; j++) 2937 kprintf(" "); 2938 kprintf(" "); 2939 2940 for (j = 0; j < c; j++) { 2941 int ch = data[i + j] & 0xff; 2942 kprintf("%c", ' ' <= ch && ch <= '~' ? ch : ' '); 2943 } 2944 2945 kprintf("\n"); 2946 2947 if (c < 16) 2948 break; 2949 } 2950 } 2951 2952 static void 2953 sk_dump_mbuf(struct mbuf *m) 2954 { 2955 int count = m->m_pkthdr.len; 2956 2957 kprintf("m=%p, m->m_pkthdr.len=%d\n", m, m->m_pkthdr.len); 2958 2959 while (count > 0 && m) { 2960 kprintf("m=%p, m->m_data=%p, m->m_len=%d\n", 2961 m, m->m_data, m->m_len); 2962 sk_dump_bytes(mtod(m, char *), m->m_len); 2963 2964 count -= m->m_len; 2965 m = m->m_next; 2966 } 2967 } 2968 #endif 2969 2970 /* 2971 * Allocate jumbo buffer storage. The SysKonnect adapters support 2972 * "jumbograms" (9K frames), although SysKonnect doesn't currently 2973 * use them in their drivers. In order for us to use them, we need 2974 * large 9K receive buffers, however standard mbuf clusters are only 2975 * 2048 bytes in size. Consequently, we need to allocate and manage 2976 * our own jumbo buffer pool. Fortunately, this does not require an 2977 * excessive amount of additional code. 2978 */ 2979 static int 2980 sk_jpool_alloc(device_t dev) 2981 { 2982 struct sk_if_softc *sc_if = device_get_softc(dev); 2983 struct sk_chain_data *cd = &sc_if->sk_cdata; 2984 bus_addr_t paddr; 2985 caddr_t buf; 2986 int error, i; 2987 2988 lwkt_serialize_init(&cd->sk_jpool_serializer); 2989 2990 error = bus_dma_tag_create(NULL, PAGE_SIZE, 0, 2991 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, 2992 NULL, NULL, SK_JMEM, 1, SK_JMEM, 2993 0, &cd->sk_jpool_dtag); 2994 if (error) { 2995 device_printf(dev, "can't create jpool DMA tag\n"); 2996 return error; 2997 } 2998 2999 error = bus_dmamem_alloc(cd->sk_jpool_dtag, &cd->sk_jpool, 3000 BUS_DMA_WAITOK, &cd->sk_jpool_dmap); 3001 if (error) { 3002 device_printf(dev, "can't alloc jpool DMA mem\n"); 3003 bus_dma_tag_destroy(cd->sk_jpool_dtag); 3004 cd->sk_jpool_dtag = NULL; 3005 return error; 3006 } 3007 3008 error = bus_dmamap_load(cd->sk_jpool_dtag, cd->sk_jpool_dmap, 3009 cd->sk_jpool, SK_JMEM, 3010 sk_dmamem_addr, &paddr, BUS_DMA_WAITOK); 3011 if (error) { 3012 device_printf(dev, "can't load DMA mem\n"); 3013 bus_dmamem_free(cd->sk_jpool_dtag, cd->sk_jpool, 3014 cd->sk_jpool_dmap); 3015 bus_dma_tag_destroy(cd->sk_jpool_dtag); 3016 cd->sk_jpool_dtag = NULL; 3017 return error; 3018 } 3019 3020 SLIST_INIT(&cd->sk_jpool_free_ent); 3021 buf = cd->sk_jpool; 3022 3023 /* 3024 * Now divide it up into SK_JLEN pieces. 3025 */ 3026 for (i = 0; i < SK_JSLOTS; i++) { 3027 struct sk_jpool_entry *entry = &cd->sk_jpool_ent[i]; 3028 3029 entry->sc_if = sc_if; 3030 entry->inuse = 0; 3031 entry->slot = i; 3032 entry->buf = buf; 3033 entry->paddr = paddr; 3034 3035 SLIST_INSERT_HEAD(&cd->sk_jpool_free_ent, entry, entry_next); 3036 3037 buf += SK_JLEN; 3038 paddr += SK_JLEN; 3039 } 3040 return 0; 3041 } 3042 3043 static void 3044 sk_jpool_free(struct sk_if_softc *sc_if) 3045 { 3046 struct sk_chain_data *cd = &sc_if->sk_cdata; 3047 3048 if (cd->sk_jpool_dtag != NULL) { 3049 bus_dmamap_unload(cd->sk_jpool_dtag, cd->sk_jpool_dmap); 3050 bus_dmamem_free(cd->sk_jpool_dtag, cd->sk_jpool, 3051 cd->sk_jpool_dmap); 3052 bus_dma_tag_destroy(cd->sk_jpool_dtag); 3053 cd->sk_jpool_dtag = NULL; 3054 } 3055 } 3056 3057 static int 3058 sk_dma_alloc(device_t dev) 3059 { 3060 struct sk_if_softc *sc_if = device_get_softc(dev); 3061 struct sk_chain_data *cd = &sc_if->sk_cdata; 3062 int i, j, error; 3063 3064 /* 3065 * Allocate the descriptor queues. 3066 * TODO: split into RX/TX rings 3067 */ 3068 error = bus_dma_tag_create(NULL, PAGE_SIZE, 0, 3069 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, 3070 NULL, NULL, 3071 sizeof(struct sk_ring_data), 1, 3072 sizeof(struct sk_ring_data), 0, 3073 &sc_if->sk_rdata_dtag); 3074 if (error) { 3075 device_printf(dev, "can't create desc DMA tag\n"); 3076 return error; 3077 } 3078 3079 error = bus_dmamem_alloc(sc_if->sk_rdata_dtag, 3080 (void **)&sc_if->sk_rdata, 3081 BUS_DMA_WAITOK | BUS_DMA_ZERO, 3082 &sc_if->sk_rdata_dmap); 3083 if (error) { 3084 device_printf(dev, "can't alloc desc DMA mem\n"); 3085 bus_dma_tag_destroy(sc_if->sk_rdata_dtag); 3086 sc_if->sk_rdata_dtag = NULL; 3087 return error; 3088 } 3089 3090 error = bus_dmamap_load(sc_if->sk_rdata_dtag, sc_if->sk_rdata_dmap, 3091 sc_if->sk_rdata, sizeof(struct sk_ring_data), 3092 sk_dmamem_addr, &sc_if->sk_rdata_paddr, 3093 BUS_DMA_WAITOK); 3094 if (error) { 3095 device_printf(dev, "can't load desc DMA mem\n"); 3096 bus_dmamem_free(sc_if->sk_rdata_dtag, sc_if->sk_rdata, 3097 sc_if->sk_rdata_dmap); 3098 bus_dma_tag_destroy(sc_if->sk_rdata_dtag); 3099 sc_if->sk_rdata_dtag = NULL; 3100 return error; 3101 } 3102 3103 /* Try to allocate memory for jumbo buffers. */ 3104 error = sk_jpool_alloc(dev); 3105 if (error) { 3106 device_printf(dev, "jumbo buffer allocation failed\n"); 3107 return error; 3108 } 3109 3110 /* Create DMA tag for TX. */ 3111 error = bus_dma_tag_create(NULL, 1, 0, 3112 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, 3113 NULL, NULL, 3114 SK_JLEN, SK_NTXSEG, SK_JLEN, 3115 0, &cd->sk_tx_dtag); 3116 if (error) { 3117 device_printf(dev, "can't create TX DMA tag\n"); 3118 return error; 3119 } 3120 3121 /* Create DMA maps for TX. */ 3122 for (i = 0; i < SK_TX_RING_CNT; i++) { 3123 error = bus_dmamap_create(cd->sk_tx_dtag, 0, 3124 &cd->sk_tx_dmap[i]); 3125 if (error) { 3126 device_printf(dev, "can't create %dth TX DMA map\n", i); 3127 3128 for (j = 0; j < i; ++j) { 3129 bus_dmamap_destroy(cd->sk_tx_dtag, 3130 cd->sk_tx_dmap[i]); 3131 } 3132 bus_dma_tag_destroy(cd->sk_tx_dtag); 3133 cd->sk_tx_dtag = NULL; 3134 return error; 3135 } 3136 } 3137 3138 /* Create DMA tag for RX. */ 3139 error = bus_dma_tag_create(NULL, 1, 0, 3140 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, 3141 NULL, NULL, MCLBYTES, 1, MCLBYTES, 3142 0, &cd->sk_rx_dtag); 3143 if (error) { 3144 device_printf(dev, "can't create RX DMA tag\n"); 3145 return error; 3146 } 3147 3148 /* Create a spare RX DMA map. */ 3149 error = bus_dmamap_create(cd->sk_rx_dtag, 0, &cd->sk_rx_dmap_tmp); 3150 if (error) { 3151 device_printf(dev, "can't create spare RX DMA map\n"); 3152 bus_dma_tag_destroy(cd->sk_rx_dtag); 3153 cd->sk_rx_dtag = NULL; 3154 return error; 3155 } 3156 3157 /* Create DMA maps for RX. */ 3158 for (i = 0; i < SK_RX_RING_CNT; ++i) { 3159 error = bus_dmamap_create(cd->sk_rx_dtag, 0, 3160 &cd->sk_rx_dmap[i]); 3161 if (error) { 3162 device_printf(dev, "can't create %dth RX DMA map\n", i); 3163 3164 for (j = 0; j < i; ++j) { 3165 bus_dmamap_destroy(cd->sk_rx_dtag, 3166 cd->sk_rx_dmap[i]); 3167 } 3168 bus_dmamap_destroy(cd->sk_rx_dtag, cd->sk_rx_dmap_tmp); 3169 bus_dma_tag_destroy(cd->sk_rx_dtag); 3170 cd->sk_rx_dtag = NULL; 3171 return error; 3172 } 3173 } 3174 return 0; 3175 } 3176 3177 static void 3178 sk_dma_free(device_t dev) 3179 { 3180 struct sk_if_softc *sc_if = device_get_softc(dev); 3181 struct sk_chain_data *cd = &sc_if->sk_cdata; 3182 int i; 3183 3184 if (cd->sk_tx_dtag != NULL) { 3185 for (i = 0; i < SK_TX_RING_CNT; ++i) { 3186 KASSERT(cd->sk_tx_mbuf[i] == NULL, 3187 ("sk_stop() is not called before %s()", 3188 __func__)); 3189 bus_dmamap_destroy(cd->sk_tx_dtag, cd->sk_tx_dmap[i]); 3190 } 3191 bus_dma_tag_destroy(cd->sk_tx_dtag); 3192 cd->sk_tx_dtag = NULL; 3193 } 3194 3195 if (cd->sk_rx_dtag != NULL) { 3196 for (i = 0; i < SK_RX_RING_CNT; ++i) { 3197 KASSERT(cd->sk_rx_mbuf[i] == NULL, 3198 ("sk_stop() is not called before %s()", 3199 __func__)); 3200 bus_dmamap_destroy(cd->sk_rx_dtag, cd->sk_rx_dmap[i]); 3201 } 3202 bus_dmamap_destroy(cd->sk_rx_dtag, cd->sk_rx_dmap_tmp); 3203 bus_dma_tag_destroy(cd->sk_rx_dtag); 3204 cd->sk_rx_dtag = NULL; 3205 } 3206 3207 sk_jpool_free(sc_if); 3208 3209 if (sc_if->sk_rdata_dtag != NULL) { 3210 bus_dmamap_unload(sc_if->sk_rdata_dtag, sc_if->sk_rdata_dmap); 3211 bus_dmamem_free(sc_if->sk_rdata_dtag, sc_if->sk_rdata, 3212 sc_if->sk_rdata_dmap); 3213 bus_dma_tag_destroy(sc_if->sk_rdata_dtag); 3214 sc_if->sk_rdata_dtag = NULL; 3215 } 3216 } 3217 3218 static void 3219 sk_buf_dma_addr(void *arg, bus_dma_segment_t *segs, int nsegs, 3220 bus_size_t mapsz __unused, int error) 3221 { 3222 struct sk_dma_ctx *ctx = arg; 3223 int i; 3224 3225 if (error) 3226 return; 3227 3228 KASSERT(nsegs <= ctx->nsegs, 3229 ("too many segments(%d), should be <= %d\n", 3230 nsegs, ctx->nsegs)); 3231 3232 ctx->nsegs = nsegs; 3233 for (i = 0; i < nsegs; ++i) 3234 ctx->segs[i] = segs[i]; 3235 } 3236 3237 static void 3238 sk_dmamem_addr(void *arg, bus_dma_segment_t *seg, int nseg, int error) 3239 { 3240 KASSERT(nseg == 1, ("too many segments %d", nseg)); 3241 *((bus_addr_t *)arg) = seg->ds_addr; 3242 } 3243 3244 static int 3245 skc_sysctl_imtime(SYSCTL_HANDLER_ARGS) 3246 { 3247 struct sk_softc *sc = arg1; 3248 struct lwkt_serialize *slize = &sc->sk_serializer; 3249 int error = 0, v; 3250 3251 lwkt_serialize_enter(slize); 3252 3253 v = sc->sk_imtime; 3254 error = sysctl_handle_int(oidp, &v, 0, req); 3255 if (error || req->newptr == NULL) 3256 goto back; 3257 if (v <= 0) { 3258 error = EINVAL; 3259 goto back; 3260 } 3261 3262 if (sc->sk_imtime != v) { 3263 sc->sk_imtime = v; 3264 sk_win_write_4(sc, SK_IMTIMERINIT, 3265 SK_IM_USECS(sc, sc->sk_imtime)); 3266 3267 /* 3268 * Force interrupt moderation timer to 3269 * reload new value. 3270 */ 3271 sk_win_write_4(sc, SK_IMTIMER, 0); 3272 } 3273 back: 3274 lwkt_serialize_exit(slize); 3275 return error; 3276 } 3277