1 /* 2 * Copyright (c) 1997, 1998, 1999, 2000 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $OpenBSD: if_sk.c,v 1.33 2003/08/12 05:23:06 nate Exp $ 33 * $FreeBSD: src/sys/pci/if_sk.c,v 1.19.2.9 2003/03/05 18:42:34 njl Exp $ 34 * $DragonFly: src/sys/dev/netif/sk/if_sk.c,v 1.43 2006/03/19 18:03:37 dillon Exp $ 35 */ 36 37 /* 38 * Copyright (c) 2003 Nathan L. Binkert <binkertn@umich.edu> 39 * 40 * Permission to use, copy, modify, and distribute this software for any 41 * purpose with or without fee is hereby granted, provided that the above 42 * copyright notice and this permission notice appear in all copies. 43 * 44 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 45 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 46 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 47 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 48 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 49 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 50 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 51 */ 52 53 /* 54 * SysKonnect SK-NET gigabit ethernet driver for FreeBSD. Supports 55 * the SK-984x series adapters, both single port and dual port. 56 * References: 57 * The XaQti XMAC II datasheet, 58 * http://www.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 59 * The SysKonnect GEnesis manual, http://www.syskonnect.com 60 * 61 * Note: XaQti has been aquired by Vitesse, and Vitesse does not have the 62 * XMAC II datasheet online. I have put my copy at people.freebsd.org as a 63 * convenience to others until Vitesse corrects this problem: 64 * 65 * http://people.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 66 * 67 * Written by Bill Paul <wpaul@ee.columbia.edu> 68 * Department of Electrical Engineering 69 * Columbia University, New York City 70 */ 71 72 /* 73 * The SysKonnect gigabit ethernet adapters consist of two main 74 * components: the SysKonnect GEnesis controller chip and the XaQti Corp. 75 * XMAC II gigabit ethernet MAC. The XMAC provides all of the MAC 76 * components and a PHY while the GEnesis controller provides a PCI 77 * interface with DMA support. Each card may have between 512K and 78 * 2MB of SRAM on board depending on the configuration. 79 * 80 * The SysKonnect GEnesis controller can have either one or two XMAC 81 * chips connected to it, allowing single or dual port NIC configurations. 82 * SysKonnect has the distinction of being the only vendor on the market 83 * with a dual port gigabit ethernet NIC. The GEnesis provides dual FIFOs, 84 * dual DMA queues, packet/MAC/transmit arbiters and direct access to the 85 * XMAC registers. This driver takes advantage of these features to allow 86 * both XMACs to operate as independent interfaces. 87 */ 88 89 #include <sys/param.h> 90 #include <sys/systm.h> 91 #include <sys/sockio.h> 92 #include <sys/mbuf.h> 93 #include <sys/malloc.h> 94 #include <sys/kernel.h> 95 #include <sys/socket.h> 96 #include <sys/queue.h> 97 #include <sys/serialize.h> 98 #include <sys/thread2.h> 99 100 #include <net/if.h> 101 #include <net/ifq_var.h> 102 #include <net/if_arp.h> 103 #include <net/ethernet.h> 104 #include <net/if_dl.h> 105 #include <net/if_media.h> 106 107 #include <net/bpf.h> 108 109 #include <vm/vm.h> /* for vtophys */ 110 #include <vm/pmap.h> /* for vtophys */ 111 #include <machine/bus.h> 112 #include <machine/resource.h> 113 #include <sys/bus.h> 114 #include <sys/rman.h> 115 116 #include <dev/netif/mii_layer/mii.h> 117 #include <dev/netif/mii_layer/miivar.h> 118 #include <dev/netif/mii_layer/brgphyreg.h> 119 120 #include <bus/pci/pcireg.h> 121 #include <bus/pci/pcivar.h> 122 123 #if 0 124 #define SK_USEIOSPACE 125 #endif 126 127 #include "if_skreg.h" 128 #include "xmaciireg.h" 129 #include "yukonreg.h" 130 131 /* "controller miibus0" required. See GENERIC if you get errors here. */ 132 #include "miibus_if.h" 133 134 static struct sk_type sk_devs[] = { 135 { VENDORID_SK, DEVICEID_SK_V1, 136 "SysKonnect Gigabit Ethernet (V1.0)" }, 137 { VENDORID_SK, DEVICEID_SK_V2, 138 "SysKonnect Gigabit Ethernet (V2.0)" }, 139 { VENDORID_MARVELL, DEVICEID_SK_V2, 140 "Marvell Gigabit Ethernet" }, 141 { VENDORID_3COM, DEVICEID_3COM_3C940, 142 "3Com 3C940 Gigabit Ethernet" }, 143 { VENDORID_LINKSYS, DEVICEID_LINKSYS_EG1032, 144 "Linksys EG1032 Gigabit Ethernet" }, 145 { VENDORID_DLINK, DEVICEID_DLINK_DGE530T, 146 "D-Link DGE-530T Gigabit Ethernet" }, 147 { 0, 0, NULL } 148 }; 149 150 static int skc_probe(device_t); 151 static int skc_attach(device_t); 152 static int skc_detach(device_t); 153 static void skc_shutdown(device_t); 154 static int sk_probe(device_t); 155 static int sk_attach(device_t); 156 static int sk_detach(device_t); 157 static void sk_tick(void *); 158 static void sk_intr(void *); 159 static void sk_intr_bcom(struct sk_if_softc *); 160 static void sk_intr_xmac(struct sk_if_softc *); 161 static void sk_intr_yukon(struct sk_if_softc *); 162 static void sk_rxeof(struct sk_if_softc *); 163 static void sk_txeof(struct sk_if_softc *); 164 static int sk_encap(struct sk_if_softc *, struct mbuf *, uint32_t *); 165 static void sk_start(struct ifnet *); 166 static int sk_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *); 167 static void sk_init(void *); 168 static void sk_init_xmac(struct sk_if_softc *); 169 static void sk_init_yukon(struct sk_if_softc *); 170 static void sk_stop(struct sk_if_softc *); 171 static void sk_watchdog(struct ifnet *); 172 static int sk_ifmedia_upd(struct ifnet *); 173 static void sk_ifmedia_sts(struct ifnet *, struct ifmediareq *); 174 static void sk_reset(struct sk_softc *); 175 static int sk_newbuf(struct sk_if_softc *, struct sk_chain *, 176 struct mbuf *); 177 static int sk_alloc_jumbo_mem(struct sk_if_softc *); 178 static struct sk_jslot 179 *sk_jalloc(struct sk_if_softc *); 180 static void sk_jfree(void *); 181 static void sk_jref(void *); 182 static int sk_init_rx_ring(struct sk_if_softc *); 183 static void sk_init_tx_ring(struct sk_if_softc *); 184 static uint32_t sk_win_read_4(struct sk_softc *, int); 185 static uint16_t sk_win_read_2(struct sk_softc *, int); 186 static uint8_t sk_win_read_1(struct sk_softc *, int); 187 static void sk_win_write_4(struct sk_softc *, int, uint32_t); 188 static void sk_win_write_2(struct sk_softc *, int, uint32_t); 189 static void sk_win_write_1(struct sk_softc *, int, uint32_t); 190 static uint8_t sk_vpd_readbyte(struct sk_softc *, int); 191 static void sk_vpd_read_res(struct sk_softc *, struct vpd_res *, int); 192 static void sk_vpd_read(struct sk_softc *); 193 194 static int sk_miibus_readreg(device_t, int, int); 195 static int sk_miibus_writereg(device_t, int, int, int); 196 static void sk_miibus_statchg(device_t); 197 198 static int sk_xmac_miibus_readreg(struct sk_if_softc *, int, int); 199 static int sk_xmac_miibus_writereg(struct sk_if_softc *, int, int, int); 200 static void sk_xmac_miibus_statchg(struct sk_if_softc *); 201 202 static int sk_marv_miibus_readreg(struct sk_if_softc *, int, int); 203 static int sk_marv_miibus_writereg(struct sk_if_softc *, int, int, int); 204 static void sk_marv_miibus_statchg(struct sk_if_softc *); 205 206 static void sk_setfilt(struct sk_if_softc *, caddr_t, int); 207 static void sk_setmulti(struct sk_if_softc *); 208 static void sk_setpromisc(struct sk_if_softc *); 209 210 #ifdef SK_USEIOSPACE 211 #define SK_RES SYS_RES_IOPORT 212 #define SK_RID SK_PCI_LOIO 213 #else 214 #define SK_RES SYS_RES_MEMORY 215 #define SK_RID SK_PCI_LOMEM 216 #endif 217 218 /* 219 * Note that we have newbus methods for both the GEnesis controller 220 * itself and the XMAC(s). The XMACs are children of the GEnesis, and 221 * the miibus code is a child of the XMACs. We need to do it this way 222 * so that the miibus drivers can access the PHY registers on the 223 * right PHY. It's not quite what I had in mind, but it's the only 224 * design that achieves the desired effect. 225 */ 226 static device_method_t skc_methods[] = { 227 /* Device interface */ 228 DEVMETHOD(device_probe, skc_probe), 229 DEVMETHOD(device_attach, skc_attach), 230 DEVMETHOD(device_detach, skc_detach), 231 DEVMETHOD(device_shutdown, skc_shutdown), 232 233 /* bus interface */ 234 DEVMETHOD(bus_print_child, bus_generic_print_child), 235 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 236 237 { 0, 0 } 238 }; 239 240 static DEFINE_CLASS_0(skc, skc_driver, skc_methods, sizeof(struct sk_softc)); 241 static devclass_t skc_devclass; 242 243 static device_method_t sk_methods[] = { 244 /* Device interface */ 245 DEVMETHOD(device_probe, sk_probe), 246 DEVMETHOD(device_attach, sk_attach), 247 DEVMETHOD(device_detach, sk_detach), 248 DEVMETHOD(device_shutdown, bus_generic_shutdown), 249 250 /* bus interface */ 251 DEVMETHOD(bus_print_child, bus_generic_print_child), 252 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 253 254 /* MII interface */ 255 DEVMETHOD(miibus_readreg, sk_miibus_readreg), 256 DEVMETHOD(miibus_writereg, sk_miibus_writereg), 257 DEVMETHOD(miibus_statchg, sk_miibus_statchg), 258 259 { 0, 0 } 260 }; 261 262 static DEFINE_CLASS_0(sk, sk_driver, sk_methods, sizeof(struct sk_if_softc)); 263 static devclass_t sk_devclass; 264 static struct lwkt_serialize sk_serializer; 265 266 DECLARE_DUMMY_MODULE(if_sk); 267 DRIVER_MODULE(if_sk, pci, skc_driver, skc_devclass, 0, 0); 268 DRIVER_MODULE(if_sk, skc, sk_driver, sk_devclass, 0, 0); 269 DRIVER_MODULE(miibus, sk, miibus_driver, miibus_devclass, 0, 0); 270 271 #define SK_SETBIT(sc, reg, x) \ 272 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | x) 273 274 #define SK_CLRBIT(sc, reg, x) \ 275 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~x) 276 277 #define SK_WIN_SETBIT_4(sc, reg, x) \ 278 sk_win_write_4(sc, reg, sk_win_read_4(sc, reg) | x) 279 280 #define SK_WIN_CLRBIT_4(sc, reg, x) \ 281 sk_win_write_4(sc, reg, sk_win_read_4(sc, reg) & ~x) 282 283 #define SK_WIN_SETBIT_2(sc, reg, x) \ 284 sk_win_write_2(sc, reg, sk_win_read_2(sc, reg) | x) 285 286 #define SK_WIN_CLRBIT_2(sc, reg, x) \ 287 sk_win_write_2(sc, reg, sk_win_read_2(sc, reg) & ~x) 288 289 static uint32_t 290 sk_win_read_4(struct sk_softc *sc, int reg) 291 { 292 #ifdef SK_USEIOSPACE 293 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 294 return(CSR_READ_4(sc, SK_WIN_BASE + SK_REG(reg))); 295 #else 296 return(CSR_READ_4(sc, reg)); 297 #endif 298 } 299 300 static uint16_t 301 sk_win_read_2(struct sk_softc *sc, int reg) 302 { 303 #ifdef SK_USEIOSPACE 304 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 305 return(CSR_READ_2(sc, SK_WIN_BASE + SK_REG(reg))); 306 #else 307 return(CSR_READ_2(sc, reg)); 308 #endif 309 } 310 311 static uint8_t 312 sk_win_read_1(struct sk_softc *sc, int reg) 313 { 314 #ifdef SK_USEIOSPACE 315 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 316 return(CSR_READ_1(sc, SK_WIN_BASE + SK_REG(reg))); 317 #else 318 return(CSR_READ_1(sc, reg)); 319 #endif 320 } 321 322 static void 323 sk_win_write_4(struct sk_softc *sc, int reg, uint32_t val) 324 { 325 #ifdef SK_USEIOSPACE 326 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 327 CSR_WRITE_4(sc, SK_WIN_BASE + SK_REG(reg), val); 328 #else 329 CSR_WRITE_4(sc, reg, val); 330 #endif 331 } 332 333 static void 334 sk_win_write_2(struct sk_softc *sc, int reg, uint32_t val) 335 { 336 #ifdef SK_USEIOSPACE 337 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 338 CSR_WRITE_2(sc, SK_WIN_BASE + SK_REG(reg), val); 339 #else 340 CSR_WRITE_2(sc, reg, val); 341 #endif 342 } 343 344 static void 345 sk_win_write_1(struct sk_softc *sc, int reg, uint32_t val) 346 { 347 #ifdef SK_USEIOSPACE 348 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 349 CSR_WRITE_1(sc, SK_WIN_BASE + SK_REG(reg), val); 350 #else 351 CSR_WRITE_1(sc, reg, val); 352 #endif 353 } 354 355 /* 356 * The VPD EEPROM contains Vital Product Data, as suggested in 357 * the PCI 2.1 specification. The VPD data is separared into areas 358 * denoted by resource IDs. The SysKonnect VPD contains an ID string 359 * resource (the name of the adapter), a read-only area resource 360 * containing various key/data fields and a read/write area which 361 * can be used to store asset management information or log messages. 362 * We read the ID string and read-only into buffers attached to 363 * the controller softc structure for later use. At the moment, 364 * we only use the ID string during sk_attach(). 365 */ 366 static uint8_t 367 sk_vpd_readbyte(struct sk_softc *sc, int addr) 368 { 369 int i; 370 371 sk_win_write_2(sc, SK_PCI_REG(SK_PCI_VPD_ADDR), addr); 372 for (i = 0; i < SK_TIMEOUT; i++) { 373 DELAY(1); 374 if (sk_win_read_2(sc, 375 SK_PCI_REG(SK_PCI_VPD_ADDR)) & SK_VPD_FLAG) 376 break; 377 } 378 379 if (i == SK_TIMEOUT) 380 return(0); 381 382 return(sk_win_read_1(sc, SK_PCI_REG(SK_PCI_VPD_DATA))); 383 } 384 385 static void 386 sk_vpd_read_res(struct sk_softc *sc, struct vpd_res *res, int addr) 387 { 388 int i; 389 uint8_t *ptr; 390 391 ptr = (uint8_t *)res; 392 for (i = 0; i < sizeof(struct vpd_res); i++) 393 ptr[i] = sk_vpd_readbyte(sc, i + addr); 394 } 395 396 static void 397 sk_vpd_read(struct sk_softc *sc) 398 { 399 struct vpd_res res; 400 int i, pos = 0; 401 402 if (sc->sk_vpd_prodname != NULL) 403 free(sc->sk_vpd_prodname, M_DEVBUF); 404 if (sc->sk_vpd_readonly != NULL) 405 free(sc->sk_vpd_readonly, M_DEVBUF); 406 sc->sk_vpd_prodname = NULL; 407 sc->sk_vpd_readonly = NULL; 408 409 sk_vpd_read_res(sc, &res, pos); 410 411 if (res.vr_id != VPD_RES_ID) { 412 printf("skc%d: bad VPD resource id: expected %x got %x\n", 413 sc->sk_unit, VPD_RES_ID, res.vr_id); 414 return; 415 } 416 417 pos += sizeof(res); 418 sc->sk_vpd_prodname = malloc(res.vr_len + 1, M_DEVBUF, M_INTWAIT); 419 for (i = 0; i < res.vr_len; i++) 420 sc->sk_vpd_prodname[i] = sk_vpd_readbyte(sc, i + pos); 421 sc->sk_vpd_prodname[i] = '\0'; 422 pos += i; 423 424 sk_vpd_read_res(sc, &res, pos); 425 426 if (res.vr_id != VPD_RES_READ) { 427 printf("skc%d: bad VPD resource id: expected %x got %x\n", 428 sc->sk_unit, VPD_RES_READ, res.vr_id); 429 return; 430 } 431 432 pos += sizeof(res); 433 sc->sk_vpd_readonly = malloc(res.vr_len, M_DEVBUF, M_INTWAIT); 434 for (i = 0; i < res.vr_len + 1; i++) 435 sc->sk_vpd_readonly[i] = sk_vpd_readbyte(sc, i + pos); 436 } 437 438 static int 439 sk_miibus_readreg(device_t dev, int phy, int reg) 440 { 441 struct sk_if_softc *sc_if = device_get_softc(dev); 442 443 switch(sc_if->sk_softc->sk_type) { 444 case SK_GENESIS: 445 return(sk_xmac_miibus_readreg(sc_if, phy, reg)); 446 case SK_YUKON: 447 return(sk_marv_miibus_readreg(sc_if, phy, reg)); 448 } 449 450 return(0); 451 } 452 453 static int 454 sk_miibus_writereg(device_t dev, int phy, int reg, int val) 455 { 456 struct sk_if_softc *sc_if = device_get_softc(dev); 457 458 switch(sc_if->sk_softc->sk_type) { 459 case SK_GENESIS: 460 return(sk_xmac_miibus_writereg(sc_if, phy, reg, val)); 461 case SK_YUKON: 462 return(sk_marv_miibus_writereg(sc_if, phy, reg, val)); 463 } 464 465 return(0); 466 } 467 468 static void 469 sk_miibus_statchg(device_t dev) 470 { 471 struct sk_if_softc *sc_if = device_get_softc(dev); 472 473 switch(sc_if->sk_softc->sk_type) { 474 case SK_GENESIS: 475 sk_xmac_miibus_statchg(sc_if); 476 break; 477 case SK_YUKON: 478 sk_marv_miibus_statchg(sc_if); 479 break; 480 } 481 } 482 483 static int 484 sk_xmac_miibus_readreg(struct sk_if_softc *sc_if, int phy, int reg) 485 { 486 int i; 487 488 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC && phy != 0) 489 return(0); 490 491 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8)); 492 SK_XM_READ_2(sc_if, XM_PHY_DATA); 493 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) { 494 for (i = 0; i < SK_TIMEOUT; i++) { 495 DELAY(1); 496 if (SK_XM_READ_2(sc_if, XM_MMUCMD) & 497 XM_MMUCMD_PHYDATARDY) 498 break; 499 } 500 501 if (i == SK_TIMEOUT) { 502 printf("sk%d: phy failed to come ready\n", 503 sc_if->sk_unit); 504 return(0); 505 } 506 } 507 DELAY(1); 508 return(SK_XM_READ_2(sc_if, XM_PHY_DATA)); 509 } 510 511 static int 512 sk_xmac_miibus_writereg(struct sk_if_softc *sc_if, int phy, int reg, int val) 513 { 514 int i; 515 516 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8)); 517 for (i = 0; i < SK_TIMEOUT; i++) { 518 if ((SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY) == 0) 519 break; 520 } 521 522 if (i == SK_TIMEOUT) { 523 printf("sk%d: phy failed to come ready\n", sc_if->sk_unit); 524 return(ETIMEDOUT); 525 } 526 527 SK_XM_WRITE_2(sc_if, XM_PHY_DATA, val); 528 for (i = 0; i < SK_TIMEOUT; i++) { 529 DELAY(1); 530 if ((SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY) == 0) 531 break; 532 } 533 534 if (i == SK_TIMEOUT) 535 printf("sk%d: phy write timed out\n", sc_if->sk_unit); 536 537 return(0); 538 } 539 540 static void 541 sk_xmac_miibus_statchg(struct sk_if_softc *sc_if) 542 { 543 struct mii_data *mii; 544 545 mii = device_get_softc(sc_if->sk_miibus); 546 547 /* 548 * If this is a GMII PHY, manually set the XMAC's 549 * duplex mode accordingly. 550 */ 551 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) { 552 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) 553 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX); 554 else 555 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX); 556 } 557 } 558 559 static int 560 sk_marv_miibus_readreg(struct sk_if_softc *sc_if, int phy, int reg) 561 { 562 uint16_t val; 563 int i; 564 565 if (phy != 0 || 566 (sc_if->sk_phytype != SK_PHYTYPE_MARV_COPPER && 567 sc_if->sk_phytype != SK_PHYTYPE_MARV_FIBER)) { 568 return(0); 569 } 570 571 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 572 YU_SMICR_REGAD(reg) | YU_SMICR_OP_READ); 573 574 for (i = 0; i < SK_TIMEOUT; i++) { 575 DELAY(1); 576 val = SK_YU_READ_2(sc_if, YUKON_SMICR); 577 if (val & YU_SMICR_READ_VALID) 578 break; 579 } 580 581 if (i == SK_TIMEOUT) { 582 printf("sk%d: phy failed to come ready\n", 583 sc_if->sk_unit); 584 return(0); 585 } 586 587 val = SK_YU_READ_2(sc_if, YUKON_SMIDR); 588 589 return(val); 590 } 591 592 static int 593 sk_marv_miibus_writereg(struct sk_if_softc *sc_if, int phy, int reg, int val) 594 { 595 int i; 596 597 SK_YU_WRITE_2(sc_if, YUKON_SMIDR, val); 598 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 599 YU_SMICR_REGAD(reg) | YU_SMICR_OP_WRITE); 600 601 for (i = 0; i < SK_TIMEOUT; i++) { 602 DELAY(1); 603 if (SK_YU_READ_2(sc_if, YUKON_SMICR) & YU_SMICR_BUSY) 604 break; 605 } 606 607 return(0); 608 } 609 610 static void 611 sk_marv_miibus_statchg(struct sk_if_softc *sc_if) 612 { 613 } 614 615 #define HASH_BITS 6 616 617 static void sk_setfilt(struct sk_if_softc *sc_if, caddr_t addr, int slot) 618 { 619 int base; 620 621 base = XM_RXFILT_ENTRY(slot); 622 623 SK_XM_WRITE_2(sc_if, base, *(uint16_t *)(&addr[0])); 624 SK_XM_WRITE_2(sc_if, base + 2, *(uint16_t *)(&addr[2])); 625 SK_XM_WRITE_2(sc_if, base + 4, *(uint16_t *)(&addr[4])); 626 } 627 628 static void 629 sk_setmulti(struct sk_if_softc *sc_if) 630 { 631 struct sk_softc *sc = sc_if->sk_softc; 632 struct ifnet *ifp = &sc_if->arpcom.ac_if; 633 uint32_t hashes[2] = { 0, 0 }; 634 int h, i; 635 struct ifmultiaddr *ifma; 636 uint8_t dummy[] = { 0, 0, 0, 0, 0 ,0 }; 637 638 /* First, zot all the existing filters. */ 639 switch(sc->sk_type) { 640 case SK_GENESIS: 641 for (i = 1; i < XM_RXFILT_MAX; i++) 642 sk_setfilt(sc_if, (caddr_t)&dummy, i); 643 644 SK_XM_WRITE_4(sc_if, XM_MAR0, 0); 645 SK_XM_WRITE_4(sc_if, XM_MAR2, 0); 646 break; 647 case SK_YUKON: 648 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, 0); 649 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, 0); 650 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, 0); 651 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, 0); 652 break; 653 } 654 655 /* Now program new ones. */ 656 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 657 hashes[0] = 0xFFFFFFFF; 658 hashes[1] = 0xFFFFFFFF; 659 } else { 660 i = 1; 661 /* First find the tail of the list. */ 662 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 663 if (ifma->ifma_link.le_next == NULL) 664 break; 665 } 666 /* Now traverse the list backwards. */ 667 for (; ifma != NULL && ifma != (void *)&ifp->if_multiaddrs; 668 ifma = (struct ifmultiaddr *)ifma->ifma_link.le_prev) { 669 if (ifma->ifma_addr->sa_family != AF_LINK) 670 continue; 671 /* 672 * Program the first XM_RXFILT_MAX multicast groups 673 * into the perfect filter. For all others, 674 * use the hash table. 675 */ 676 if (sc->sk_type == SK_GENESIS && i < XM_RXFILT_MAX) { 677 sk_setfilt(sc_if, 678 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), i); 679 i++; 680 continue; 681 } 682 683 switch(sc->sk_type) { 684 case SK_GENESIS: 685 h = ~ether_crc32_le(LLADDR((struct sockaddr_dl *) 686 ifma->ifma_addr), ETHER_ADDR_LEN) & 687 ((1 << HASH_BITS) -1 ); 688 if (h < 32) 689 hashes[0] |= (1 << h); 690 else 691 hashes[1] |= (1 << (h - 32)); 692 break; 693 694 case SK_YUKON: 695 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 696 ifma->ifma_addr), ETHER_ADDR_LEN) & 697 ((1 << HASH_BITS) -1 ); 698 if (h < 32) 699 hashes[0] |= (1 << h); 700 else 701 hashes[1] |= (1 << (h - 32)); 702 break; 703 } 704 } 705 } 706 707 switch(sc->sk_type) { 708 case SK_GENESIS: 709 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_HASH| 710 XM_MODE_RX_USE_PERFECT); 711 SK_XM_WRITE_4(sc_if, XM_MAR0, hashes[0]); 712 SK_XM_WRITE_4(sc_if, XM_MAR2, hashes[1]); 713 break; 714 case SK_YUKON: 715 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, hashes[0] & 0xffff); 716 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, (hashes[0] >> 16) & 0xffff); 717 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, hashes[1] & 0xffff); 718 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, (hashes[1] >> 16) & 0xffff); 719 break; 720 } 721 } 722 723 static void 724 sk_setpromisc(struct sk_if_softc *sc_if) 725 { 726 struct sk_softc *sc = sc_if->sk_softc; 727 struct ifnet *ifp = &sc_if->arpcom.ac_if; 728 729 switch(sc->sk_type) { 730 case SK_GENESIS: 731 if (ifp->if_flags & IFF_PROMISC) { 732 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 733 } else { 734 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 735 } 736 break; 737 case SK_YUKON: 738 if (ifp->if_flags & IFF_PROMISC) { 739 SK_YU_CLRBIT_2(sc_if, YUKON_RCR, 740 YU_RCR_UFLEN | YU_RCR_MUFLEN); 741 } else { 742 SK_YU_SETBIT_2(sc_if, YUKON_RCR, 743 YU_RCR_UFLEN | YU_RCR_MUFLEN); 744 } 745 break; 746 } 747 } 748 749 static int 750 sk_init_rx_ring(struct sk_if_softc *sc_if) 751 { 752 struct sk_chain_data *cd = &sc_if->sk_cdata; 753 struct sk_ring_data *rd = sc_if->sk_rdata; 754 int i; 755 756 bzero(rd->sk_rx_ring, sizeof(struct sk_rx_desc) * SK_RX_RING_CNT); 757 758 for (i = 0; i < SK_RX_RING_CNT; i++) { 759 cd->sk_rx_chain[i].sk_desc = &rd->sk_rx_ring[i]; 760 if (sk_newbuf(sc_if, &cd->sk_rx_chain[i], NULL) == ENOBUFS) 761 return(ENOBUFS); 762 if (i == (SK_RX_RING_CNT - 1)) { 763 cd->sk_rx_chain[i].sk_next = 764 &cd->sk_rx_chain[0]; 765 rd->sk_rx_ring[i].sk_next = 766 vtophys(&rd->sk_rx_ring[0]); 767 } else { 768 cd->sk_rx_chain[i].sk_next = 769 &cd->sk_rx_chain[i + 1]; 770 rd->sk_rx_ring[i].sk_next = 771 vtophys(&rd->sk_rx_ring[i + 1]); 772 } 773 } 774 775 sc_if->sk_cdata.sk_rx_prod = 0; 776 sc_if->sk_cdata.sk_rx_cons = 0; 777 778 return(0); 779 } 780 781 static void 782 sk_init_tx_ring(struct sk_if_softc *sc_if) 783 { 784 struct sk_chain_data *cd = &sc_if->sk_cdata; 785 struct sk_ring_data *rd = sc_if->sk_rdata; 786 int i, nexti; 787 788 bzero(sc_if->sk_rdata->sk_tx_ring, 789 sizeof(struct sk_tx_desc) * SK_TX_RING_CNT); 790 791 for (i = 0; i < SK_TX_RING_CNT; i++) { 792 nexti = (i == (SK_TX_RING_CNT - 1)) ? 0 : i + 1; 793 cd->sk_tx_chain[i].sk_desc = &rd->sk_tx_ring[i]; 794 cd->sk_tx_chain[i].sk_next = &cd->sk_tx_chain[nexti]; 795 rd->sk_tx_ring[i].sk_next = vtophys(&rd->sk_tx_ring[nexti]); 796 } 797 798 sc_if->sk_cdata.sk_tx_prod = 0; 799 sc_if->sk_cdata.sk_tx_cons = 0; 800 sc_if->sk_cdata.sk_tx_cnt = 0; 801 } 802 803 static int 804 sk_newbuf(struct sk_if_softc *sc_if, struct sk_chain *c, struct mbuf *m) 805 { 806 struct mbuf *m_new = NULL; 807 struct sk_rx_desc *r; 808 struct sk_jslot *buf; 809 810 if (m == NULL) { 811 MGETHDR(m_new, MB_DONTWAIT, MT_DATA); 812 if (m_new == NULL) 813 return(ENOBUFS); 814 815 /* Allocate the jumbo buffer */ 816 buf = sk_jalloc(sc_if); 817 if (buf == NULL) { 818 m_freem(m_new); 819 #ifdef SK_VERBOSE 820 printf("sk%d: jumbo allocation failed " 821 "-- packet dropped!\n", sc_if->sk_unit); 822 #endif 823 return(ENOBUFS); 824 } 825 826 /* Attach the buffer to the mbuf */ 827 m_new->m_ext.ext_arg = buf; 828 m_new->m_ext.ext_buf = buf->sk_buf; 829 m_new->m_ext.ext_free = sk_jfree; 830 m_new->m_ext.ext_ref = sk_jref; 831 m_new->m_ext.ext_size = SK_JUMBO_FRAMELEN; 832 833 m_new->m_data = m_new->m_ext.ext_buf; 834 m_new->m_flags |= M_EXT; 835 m_new->m_len = m_new->m_pkthdr.len = m_new->m_ext.ext_size; 836 } else { 837 /* 838 * We're re-using a previously allocated mbuf; 839 * be sure to re-init pointers and lengths to 840 * default values. 841 */ 842 m_new = m; 843 m_new->m_len = m_new->m_pkthdr.len = SK_JLEN; 844 m_new->m_data = m_new->m_ext.ext_buf; 845 } 846 847 /* 848 * Adjust alignment so packet payload begins on a 849 * longword boundary. Mandatory for Alpha, useful on 850 * x86 too. 851 */ 852 m_adj(m_new, ETHER_ALIGN); 853 854 r = c->sk_desc; 855 c->sk_mbuf = m_new; 856 r->sk_data_lo = vtophys(mtod(m_new, caddr_t)); 857 r->sk_ctl = m_new->m_len | SK_RXSTAT; 858 859 return(0); 860 } 861 862 /* 863 * Allocate jumbo buffer storage. The SysKonnect adapters support 864 * "jumbograms" (9K frames), although SysKonnect doesn't currently 865 * use them in their drivers. In order for us to use them, we need 866 * large 9K receive buffers, however standard mbuf clusters are only 867 * 2048 bytes in size. Consequently, we need to allocate and manage 868 * our own jumbo buffer pool. Fortunately, this does not require an 869 * excessive amount of additional code. 870 */ 871 static int 872 sk_alloc_jumbo_mem(struct sk_if_softc *sc_if) 873 { 874 caddr_t ptr; 875 int i; 876 struct sk_jslot *entry; 877 878 /* Grab a big chunk o' storage. */ 879 sc_if->sk_cdata.sk_jumbo_buf = contigmalloc(SK_JMEM, M_DEVBUF, 880 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 881 882 if (sc_if->sk_cdata.sk_jumbo_buf == NULL) { 883 printf("sk%d: no memory for jumbo buffers!\n", sc_if->sk_unit); 884 return(ENOBUFS); 885 } 886 887 SLIST_INIT(&sc_if->sk_jfree_listhead); 888 889 /* 890 * Now divide it up into 9K pieces and save the addresses 891 * in an array. Note that we play an evil trick here by using 892 * the first few bytes in the buffer to hold the the address 893 * of the softc structure for this interface. This is because 894 * sk_jfree() needs it, but it is called by the mbuf management 895 * code which will not pass it to us explicitly. 896 */ 897 ptr = sc_if->sk_cdata.sk_jumbo_buf; 898 for (i = 0; i < SK_JSLOTS; i++) { 899 entry = &sc_if->sk_cdata.sk_jslots[i]; 900 entry->sk_sc = sc_if; 901 entry->sk_buf = ptr; 902 entry->sk_inuse = 0; 903 entry->sk_slot = i; 904 SLIST_INSERT_HEAD(&sc_if->sk_jfree_listhead, entry, jslot_link); 905 ptr += SK_JLEN; 906 } 907 908 return(0); 909 } 910 911 /* 912 * Allocate a jumbo buffer. 913 */ 914 static struct sk_jslot * 915 sk_jalloc(struct sk_if_softc *sc_if) 916 { 917 struct sk_jslot *entry; 918 919 lwkt_serialize_enter(&sc_if->sk_jslot_serializer); 920 entry = SLIST_FIRST(&sc_if->sk_jfree_listhead); 921 if (entry) { 922 SLIST_REMOVE_HEAD(&sc_if->sk_jfree_listhead, jslot_link); 923 entry->sk_inuse = 1; 924 } else { 925 #ifdef SK_VERBOSE 926 printf("sk%d: no free jumbo buffers\n", sc_if->sk_unit); 927 #endif 928 } 929 lwkt_serialize_exit(&sc_if->sk_jslot_serializer); 930 return(entry); 931 } 932 933 /* 934 * Adjust usage count on a jumbo buffer. In general this doesn't 935 * get used much because our jumbo buffers don't get passed around 936 * a lot, but it's implemented for correctness. 937 */ 938 static void 939 sk_jref(void *arg) 940 { 941 struct sk_jslot *entry = (struct sk_jslot *)arg; 942 struct sk_if_softc *sc = entry->sk_sc; 943 944 if (sc == NULL) 945 panic("sk_jref: can't find softc pointer!"); 946 947 if (&sc->sk_cdata.sk_jslots[entry->sk_slot] != entry) 948 panic("sk_jref: asked to reference buffer " 949 "that we don't manage!"); 950 if (entry->sk_inuse == 0) 951 panic("sk_jref: buffer already free!"); 952 atomic_add_int(&entry->sk_inuse, 1); 953 } 954 955 /* 956 * Release a jumbo buffer. 957 */ 958 static void 959 sk_jfree(void *arg) 960 { 961 struct sk_jslot *entry = (struct sk_jslot *)arg; 962 struct sk_if_softc *sc = entry->sk_sc; 963 964 if (sc == NULL) 965 panic("sk_jref: can't find softc pointer!"); 966 967 if (&sc->sk_cdata.sk_jslots[entry->sk_slot] != entry) 968 panic("sk_jref: asked to reference buffer " 969 "that we don't manage!"); 970 if (entry->sk_inuse == 0) 971 panic("sk_jref: buffer already free!"); 972 lwkt_serialize_enter(&sc->sk_jslot_serializer); 973 atomic_subtract_int(&entry->sk_inuse, 1); 974 if (entry->sk_inuse == 0) 975 SLIST_INSERT_HEAD(&sc->sk_jfree_listhead, entry, jslot_link); 976 lwkt_serialize_exit(&sc->sk_jslot_serializer); 977 } 978 979 /* 980 * Set media options. 981 */ 982 static int 983 sk_ifmedia_upd(struct ifnet *ifp) 984 { 985 struct sk_if_softc *sc_if = ifp->if_softc; 986 struct mii_data *mii; 987 988 mii = device_get_softc(sc_if->sk_miibus); 989 sk_init(sc_if); 990 mii_mediachg(mii); 991 992 return(0); 993 } 994 995 /* 996 * Report current media status. 997 */ 998 static void 999 sk_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1000 { 1001 struct sk_if_softc *sc_if; 1002 struct mii_data *mii; 1003 1004 sc_if = ifp->if_softc; 1005 mii = device_get_softc(sc_if->sk_miibus); 1006 1007 mii_pollstat(mii); 1008 ifmr->ifm_active = mii->mii_media_active; 1009 ifmr->ifm_status = mii->mii_media_status; 1010 } 1011 1012 static int 1013 sk_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr) 1014 { 1015 struct sk_if_softc *sc_if = ifp->if_softc; 1016 struct ifreq *ifr = (struct ifreq *)data; 1017 struct mii_data *mii; 1018 int error = 0; 1019 1020 crit_enter(); 1021 1022 switch(command) { 1023 case SIOCSIFMTU: 1024 if (ifr->ifr_mtu > SK_JUMBO_MTU) 1025 error = EINVAL; 1026 else { 1027 ifp->if_mtu = ifr->ifr_mtu; 1028 ifp->if_flags &= ~IFF_RUNNING; 1029 sk_init(sc_if); 1030 } 1031 break; 1032 case SIOCSIFFLAGS: 1033 if (ifp->if_flags & IFF_UP) { 1034 if (ifp->if_flags & IFF_RUNNING) { 1035 if ((ifp->if_flags ^ sc_if->sk_if_flags) 1036 & IFF_PROMISC) { 1037 sk_setpromisc(sc_if); 1038 sk_setmulti(sc_if); 1039 } 1040 } else 1041 sk_init(sc_if); 1042 } else { 1043 if (ifp->if_flags & IFF_RUNNING) 1044 sk_stop(sc_if); 1045 } 1046 sc_if->sk_if_flags = ifp->if_flags; 1047 error = 0; 1048 break; 1049 case SIOCADDMULTI: 1050 case SIOCDELMULTI: 1051 sk_setmulti(sc_if); 1052 error = 0; 1053 break; 1054 case SIOCGIFMEDIA: 1055 case SIOCSIFMEDIA: 1056 mii = device_get_softc(sc_if->sk_miibus); 1057 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1058 break; 1059 default: 1060 error = ether_ioctl(ifp, command, data); 1061 break; 1062 } 1063 1064 crit_exit(); 1065 1066 return(error); 1067 } 1068 1069 /* 1070 * Probe for a SysKonnect GEnesis chip. Check the PCI vendor and device 1071 * IDs against our list and return a device name if we find a match. 1072 */ 1073 static int 1074 skc_probe(device_t dev) 1075 { 1076 struct sk_type *t; 1077 uint16_t vendor, product; 1078 1079 lwkt_serialize_init(&sk_serializer); 1080 vendor = pci_get_vendor(dev); 1081 product = pci_get_device(dev); 1082 1083 for (t = sk_devs; t->sk_name != NULL; t++) { 1084 if (vendor == t->sk_vid && product == t->sk_did) { 1085 device_set_desc(dev, t->sk_name); 1086 return(0); 1087 } 1088 } 1089 1090 return(ENXIO); 1091 } 1092 1093 /* 1094 * Force the GEnesis into reset, then bring it out of reset. 1095 */ 1096 static void 1097 sk_reset(struct sk_softc *sc) 1098 { 1099 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_RESET); 1100 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_RESET); 1101 if (sc->sk_type == SK_YUKON) 1102 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_SET); 1103 1104 DELAY(1000); 1105 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_UNRESET); 1106 DELAY(2); 1107 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_UNRESET); 1108 if (sc->sk_type == SK_YUKON) 1109 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_CLEAR); 1110 1111 if (sc->sk_type == SK_GENESIS) { 1112 /* Configure packet arbiter */ 1113 sk_win_write_2(sc, SK_PKTARB_CTL, SK_PKTARBCTL_UNRESET); 1114 sk_win_write_2(sc, SK_RXPA1_TINIT, SK_PKTARB_TIMEOUT); 1115 sk_win_write_2(sc, SK_TXPA1_TINIT, SK_PKTARB_TIMEOUT); 1116 sk_win_write_2(sc, SK_RXPA2_TINIT, SK_PKTARB_TIMEOUT); 1117 sk_win_write_2(sc, SK_TXPA2_TINIT, SK_PKTARB_TIMEOUT); 1118 } 1119 1120 /* Enable RAM interface */ 1121 sk_win_write_4(sc, SK_RAMCTL, SK_RAMCTL_UNRESET); 1122 1123 /* 1124 * Configure interrupt moderation. The moderation timer 1125 * defers interrupts specified in the interrupt moderation 1126 * timer mask based on the timeout specified in the interrupt 1127 * moderation timer init register. Each bit in the timer 1128 * register represents 18.825ns, so to specify a timeout in 1129 * microseconds, we have to multiply by 54. 1130 */ 1131 sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(200)); 1132 sk_win_write_4(sc, SK_IMMR, SK_ISR_TX1_S_EOF|SK_ISR_TX2_S_EOF| 1133 SK_ISR_RX1_EOF|SK_ISR_RX2_EOF); 1134 sk_win_write_1(sc, SK_IMTIMERCTL, SK_IMCTL_START); 1135 } 1136 1137 static int 1138 sk_probe(device_t dev) 1139 { 1140 struct sk_softc *sc = device_get_softc(device_get_parent(dev)); 1141 1142 /* 1143 * Not much to do here. We always know there will be 1144 * at least one XMAC present, and if there are two, 1145 * skc_attach() will create a second device instance 1146 * for us. 1147 */ 1148 switch (sc->sk_type) { 1149 case SK_GENESIS: 1150 device_set_desc(dev, "XaQti Corp. XMAC II"); 1151 break; 1152 case SK_YUKON: 1153 device_set_desc(dev, "Marvell Semiconductor, Inc. Yukon"); 1154 break; 1155 } 1156 1157 return(0); 1158 } 1159 1160 /* 1161 * Each XMAC chip is attached as a separate logical IP interface. 1162 * Single port cards will have only one logical interface of course. 1163 */ 1164 static int 1165 sk_attach(device_t dev) 1166 { 1167 struct sk_softc *sc = device_get_softc(device_get_parent(dev)); 1168 struct sk_if_softc *sc_if = device_get_softc(dev); 1169 struct ifnet *ifp; 1170 int i, port; 1171 1172 port = *(int *)device_get_ivars(dev); 1173 free(device_get_ivars(dev), M_DEVBUF); 1174 device_set_ivars(dev, NULL); 1175 sc_if->sk_dev = dev; 1176 callout_init(&sc_if->sk_tick_timer); 1177 lwkt_serialize_init(&sc_if->sk_jslot_serializer); 1178 1179 sc_if->sk_dev = dev; 1180 sc_if->sk_unit = device_get_unit(dev); 1181 sc_if->sk_port = port; 1182 sc_if->sk_softc = sc; 1183 sc->sk_if[port] = sc_if; 1184 if (port == SK_PORT_A) 1185 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR0; 1186 if (port == SK_PORT_B) 1187 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR1; 1188 1189 /* 1190 * Get station address for this interface. Note that 1191 * dual port cards actually come with three station 1192 * addresses: one for each port, plus an extra. The 1193 * extra one is used by the SysKonnect driver software 1194 * as a 'virtual' station address for when both ports 1195 * are operating in failover mode. Currently we don't 1196 * use this extra address. 1197 */ 1198 for (i = 0; i < ETHER_ADDR_LEN; i++) 1199 sc_if->arpcom.ac_enaddr[i] = 1200 sk_win_read_1(sc, SK_MAC0_0 + (port * 8) + i); 1201 1202 /* 1203 * Set up RAM buffer addresses. The NIC will have a certain 1204 * amount of SRAM on it, somewhere between 512K and 2MB. We 1205 * need to divide this up a) between the transmitter and 1206 * receiver and b) between the two XMACs, if this is a 1207 * dual port NIC. Our algotithm is to divide up the memory 1208 * evenly so that everyone gets a fair share. 1209 */ 1210 if (sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC) { 1211 uint32_t chunk, val; 1212 1213 chunk = sc->sk_ramsize / 2; 1214 val = sc->sk_rboff / sizeof(uint64_t); 1215 sc_if->sk_rx_ramstart = val; 1216 val += (chunk / sizeof(uint64_t)); 1217 sc_if->sk_rx_ramend = val - 1; 1218 sc_if->sk_tx_ramstart = val; 1219 val += (chunk / sizeof(uint64_t)); 1220 sc_if->sk_tx_ramend = val - 1; 1221 } else { 1222 uint32_t chunk, val; 1223 1224 chunk = sc->sk_ramsize / 4; 1225 val = (sc->sk_rboff + (chunk * 2 * sc_if->sk_port)) / 1226 sizeof(uint64_t); 1227 sc_if->sk_rx_ramstart = val; 1228 val += (chunk / sizeof(uint64_t)); 1229 sc_if->sk_rx_ramend = val - 1; 1230 sc_if->sk_tx_ramstart = val; 1231 val += (chunk / sizeof(uint64_t)); 1232 sc_if->sk_tx_ramend = val - 1; 1233 } 1234 1235 /* Read and save PHY type and set PHY address */ 1236 sc_if->sk_phytype = sk_win_read_1(sc, SK_EPROM1) & 0xF; 1237 switch(sc_if->sk_phytype) { 1238 case SK_PHYTYPE_XMAC: 1239 sc_if->sk_phyaddr = SK_PHYADDR_XMAC; 1240 break; 1241 case SK_PHYTYPE_BCOM: 1242 sc_if->sk_phyaddr = SK_PHYADDR_BCOM; 1243 break; 1244 case SK_PHYTYPE_MARV_COPPER: 1245 sc_if->sk_phyaddr = SK_PHYADDR_MARV; 1246 break; 1247 default: 1248 printf("skc%d: unsupported PHY type: %d\n", 1249 sc->sk_unit, sc_if->sk_phytype); 1250 sc->sk_if[port] = NULL; 1251 return(ENODEV); 1252 } 1253 1254 /* Allocate the descriptor queues. */ 1255 sc_if->sk_rdata = contigmalloc(sizeof(struct sk_ring_data), M_DEVBUF, 1256 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 1257 1258 if (sc_if->sk_rdata == NULL) { 1259 printf("sk%d: no memory for list buffers!\n", sc_if->sk_unit); 1260 sc->sk_if[port] = NULL; 1261 return(ENOMEM); 1262 } 1263 1264 bzero(sc_if->sk_rdata, sizeof(struct sk_ring_data)); 1265 1266 /* Try to allocate memory for jumbo buffers. */ 1267 if (sk_alloc_jumbo_mem(sc_if)) { 1268 printf("sk%d: jumbo buffer allocation failed\n", 1269 sc_if->sk_unit); 1270 contigfree(sc_if->sk_rdata, 1271 sizeof(struct sk_ring_data), M_DEVBUF); 1272 sc->sk_if[port] = NULL; 1273 return(ENOMEM); 1274 } 1275 1276 ifp = &sc_if->arpcom.ac_if; 1277 ifp->if_softc = sc_if; 1278 if_initname(ifp, "sk", sc_if->sk_unit); 1279 ifp->if_mtu = ETHERMTU; 1280 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1281 ifp->if_ioctl = sk_ioctl; 1282 ifp->if_start = sk_start; 1283 ifp->if_watchdog = sk_watchdog; 1284 ifp->if_init = sk_init; 1285 ifp->if_baudrate = 1000000000; 1286 ifq_set_maxlen(&ifp->if_snd, SK_TX_RING_CNT - 1); 1287 ifq_set_ready(&ifp->if_snd); 1288 1289 /* 1290 * Do miibus setup. 1291 */ 1292 switch (sc->sk_type) { 1293 case SK_GENESIS: 1294 sk_init_xmac(sc_if); 1295 break; 1296 case SK_YUKON: 1297 sk_init_yukon(sc_if); 1298 break; 1299 } 1300 1301 if (mii_phy_probe(dev, &sc_if->sk_miibus, 1302 sk_ifmedia_upd, sk_ifmedia_sts)) { 1303 printf("skc%d: no PHY found!\n", sc_if->sk_unit); 1304 contigfree(sc_if->sk_cdata.sk_jumbo_buf, SK_JMEM, 1305 M_DEVBUF); 1306 contigfree(sc_if->sk_rdata, 1307 sizeof(struct sk_ring_data), M_DEVBUF); 1308 sc->sk_if[port] = NULL; 1309 return(ENXIO); 1310 } 1311 1312 /* 1313 * Call MI attach routine. 1314 */ 1315 ether_ifattach(ifp, sc_if->arpcom.ac_enaddr, &sk_serializer); 1316 callout_init(&sc_if->sk_tick_timer); 1317 1318 return(0); 1319 } 1320 1321 /* 1322 * Attach the interface. Allocate softc structures, do ifmedia 1323 * setup and ethernet/BPF attach. 1324 */ 1325 static int 1326 skc_attach(device_t dev) 1327 { 1328 struct sk_softc *sc; 1329 int error = 0, *port, rid, unit; 1330 uint32_t command; 1331 uint8_t skrs; 1332 1333 crit_enter(); 1334 1335 sc = device_get_softc(dev); 1336 unit = device_get_unit(dev); 1337 switch (pci_get_device(dev)) { 1338 case DEVICEID_SK_V1: 1339 sc->sk_type = SK_GENESIS; 1340 break; 1341 case DEVICEID_SK_V2: 1342 case DEVICEID_3COM_3C940: 1343 case DEVICEID_LINKSYS_EG1032: 1344 case DEVICEID_DLINK_DGE530T: 1345 sc->sk_type = SK_YUKON; 1346 break; 1347 } 1348 1349 /* 1350 * Handle power management nonsense. 1351 */ 1352 command = pci_read_config(dev, SK_PCI_CAPID, 4) & 0x000000FF; 1353 if (command == 0x01) { 1354 command = pci_read_config(dev, SK_PCI_PWRMGMTCTRL, 4); 1355 if (command & SK_PSTATE_MASK) { 1356 uint32_t iobase, membase, irq; 1357 1358 /* Save important PCI config data. */ 1359 iobase = pci_read_config(dev, SK_PCI_LOIO, 4); 1360 membase = pci_read_config(dev, SK_PCI_LOMEM, 4); 1361 irq = pci_read_config(dev, SK_PCI_INTLINE, 4); 1362 1363 /* Reset the power state. */ 1364 printf("skc%d: chip is in D%d power mode " 1365 "-- setting to D0\n", unit, command & SK_PSTATE_MASK); 1366 command &= 0xFFFFFFFC; 1367 pci_write_config(dev, SK_PCI_PWRMGMTCTRL, command, 4); 1368 1369 /* Restore PCI config data. */ 1370 pci_write_config(dev, SK_PCI_LOIO, iobase, 4); 1371 pci_write_config(dev, SK_PCI_LOMEM, membase, 4); 1372 pci_write_config(dev, SK_PCI_INTLINE, irq, 4); 1373 } 1374 } 1375 1376 /* 1377 * Map control/status registers. 1378 */ 1379 command = pci_read_config(dev, PCIR_COMMAND, 4); 1380 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 1381 pci_write_config(dev, PCIR_COMMAND, command, 4); 1382 command = pci_read_config(dev, PCIR_COMMAND, 4); 1383 1384 #ifdef SK_USEIOSPACE 1385 if ((command & PCIM_CMD_PORTEN) == 0) { 1386 printf("skc%d: failed to enable I/O ports!\n", unit); 1387 error = ENXIO; 1388 goto fail; 1389 } 1390 #else 1391 if ((command & PCIM_CMD_MEMEN) == 0) { 1392 printf("skc%d: failed to enable memory mapping!\n", unit); 1393 error = ENXIO; 1394 goto fail; 1395 } 1396 #endif 1397 1398 rid = SK_RID; 1399 sc->sk_res = bus_alloc_resource_any(dev, SK_RES, &rid, RF_ACTIVE); 1400 1401 if (sc->sk_res == NULL) { 1402 printf("sk%d: couldn't map ports/memory\n", unit); 1403 error = ENXIO; 1404 goto fail; 1405 } 1406 1407 sc->sk_btag = rman_get_bustag(sc->sk_res); 1408 sc->sk_bhandle = rman_get_bushandle(sc->sk_res); 1409 1410 /* Allocate interrupt */ 1411 rid = 0; 1412 sc->sk_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1413 RF_SHAREABLE | RF_ACTIVE); 1414 1415 if (sc->sk_irq == NULL) { 1416 printf("skc%d: couldn't map interrupt\n", unit); 1417 bus_release_resource(dev, SK_RES, SK_RID, sc->sk_res); 1418 error = ENXIO; 1419 goto fail; 1420 } 1421 1422 error = bus_setup_intr(dev, sc->sk_irq, INTR_NETSAFE, 1423 sk_intr, sc, 1424 &sc->sk_intrhand, &sk_serializer); 1425 1426 if (error) { 1427 printf("skc%d: couldn't set up irq\n", unit); 1428 bus_release_resource(dev, SK_RES, SK_RID, sc->sk_res); 1429 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sk_irq); 1430 goto fail; 1431 } 1432 1433 /* Reset the adapter. */ 1434 sk_reset(sc); 1435 1436 sc->sk_unit = unit; 1437 1438 /* Read and save vital product data from EEPROM. */ 1439 sk_vpd_read(sc); 1440 1441 skrs = sk_win_read_1(sc, SK_EPROM0); 1442 if (sc->sk_type == SK_GENESIS) { 1443 /* Read and save RAM size and RAMbuffer offset */ 1444 switch(skrs) { 1445 case SK_RAMSIZE_512K_64: 1446 sc->sk_ramsize = 0x80000; 1447 sc->sk_rboff = SK_RBOFF_0; 1448 break; 1449 case SK_RAMSIZE_1024K_64: 1450 sc->sk_ramsize = 0x100000; 1451 sc->sk_rboff = SK_RBOFF_80000; 1452 break; 1453 case SK_RAMSIZE_1024K_128: 1454 sc->sk_ramsize = 0x100000; 1455 sc->sk_rboff = SK_RBOFF_0; 1456 break; 1457 case SK_RAMSIZE_2048K_128: 1458 sc->sk_ramsize = 0x200000; 1459 sc->sk_rboff = SK_RBOFF_0; 1460 break; 1461 default: 1462 printf("skc%d: unknown ram size: %d\n", 1463 sc->sk_unit, sk_win_read_1(sc, SK_EPROM0)); 1464 bus_teardown_intr(dev, sc->sk_irq, sc->sk_intrhand); 1465 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sk_irq); 1466 bus_release_resource(dev, SK_RES, SK_RID, sc->sk_res); 1467 error = ENXIO; 1468 goto fail; 1469 break; 1470 } 1471 } else { /* SK_YUKON */ 1472 if (skrs == 0x00) { 1473 sc->sk_ramsize = 0x20000; 1474 } else { 1475 sc->sk_ramsize = skrs * (1<<12); 1476 } 1477 sc->sk_rboff = SK_RBOFF_0; 1478 } 1479 1480 /* Read and save physical media type */ 1481 switch(sk_win_read_1(sc, SK_PMDTYPE)) { 1482 case SK_PMD_1000BASESX: 1483 sc->sk_pmd = IFM_1000_SX; 1484 break; 1485 case SK_PMD_1000BASELX: 1486 sc->sk_pmd = IFM_1000_LX; 1487 break; 1488 case SK_PMD_1000BASECX: 1489 sc->sk_pmd = IFM_1000_CX; 1490 break; 1491 case SK_PMD_1000BASETX: 1492 sc->sk_pmd = IFM_1000_T; 1493 break; 1494 default: 1495 printf("skc%d: unknown media type: 0x%x\n", 1496 sc->sk_unit, sk_win_read_1(sc, SK_PMDTYPE)); 1497 bus_teardown_intr(dev, sc->sk_irq, sc->sk_intrhand); 1498 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sk_irq); 1499 bus_release_resource(dev, SK_RES, SK_RID, sc->sk_res); 1500 error = ENXIO; 1501 goto fail; 1502 } 1503 1504 /* Announce the product name. */ 1505 printf("skc%d: %s\n", sc->sk_unit, sc->sk_vpd_prodname); 1506 sc->sk_devs[SK_PORT_A] = device_add_child(dev, "sk", -1); 1507 port = malloc(sizeof(int), M_DEVBUF, M_WAITOK); 1508 *port = SK_PORT_A; 1509 device_set_ivars(sc->sk_devs[SK_PORT_A], port); 1510 1511 if (!(sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC)) { 1512 sc->sk_devs[SK_PORT_B] = device_add_child(dev, "sk", -1); 1513 port = malloc(sizeof(int), M_DEVBUF, M_WAITOK); 1514 *port = SK_PORT_B; 1515 device_set_ivars(sc->sk_devs[SK_PORT_B], port); 1516 } 1517 1518 /* Turn on the 'driver is loaded' LED. */ 1519 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON); 1520 1521 bus_generic_attach(dev); 1522 1523 fail: 1524 crit_exit(); 1525 return(error); 1526 } 1527 1528 static int 1529 sk_detach(device_t dev) 1530 { 1531 struct sk_if_softc *sc_if = device_get_softc(dev); 1532 struct ifnet *ifp = &sc_if->arpcom.ac_if; 1533 1534 ether_ifdetach(ifp); 1535 bus_generic_detach(dev); 1536 if (sc_if->sk_miibus != NULL) 1537 device_delete_child(dev, sc_if->sk_miibus); 1538 contigfree(sc_if->sk_cdata.sk_jumbo_buf, SK_JMEM, M_DEVBUF); 1539 contigfree(sc_if->sk_rdata, sizeof(struct sk_ring_data), M_DEVBUF); 1540 1541 return(0); 1542 } 1543 1544 static int 1545 skc_detach(device_t dev) 1546 { 1547 struct sk_softc *sc; 1548 1549 sc = device_get_softc(dev); 1550 1551 lwkt_serialize_enter(&sk_serializer); 1552 1553 if (sc->sk_if[SK_PORT_A] != NULL) 1554 sk_stop(sc->sk_if[SK_PORT_A]); 1555 if (sc->sk_if[SK_PORT_B] != NULL) 1556 sk_stop(sc->sk_if[SK_PORT_B]); 1557 1558 bus_teardown_intr(dev, sc->sk_irq, sc->sk_intrhand); 1559 1560 lwkt_serialize_exit(&sk_serializer); 1561 1562 /* 1563 * recursed from sk_detach ? don't need serializer 1564 */ 1565 bus_generic_detach(dev); 1566 if (sc->sk_devs[SK_PORT_A] != NULL) 1567 device_delete_child(dev, sc->sk_devs[SK_PORT_A]); 1568 if (sc->sk_devs[SK_PORT_B] != NULL) 1569 device_delete_child(dev, sc->sk_devs[SK_PORT_B]); 1570 1571 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sk_irq); 1572 bus_release_resource(dev, SK_RES, SK_RID, sc->sk_res); 1573 1574 return(0); 1575 } 1576 1577 static int 1578 sk_encap(struct sk_if_softc *sc_if, struct mbuf *m_head, uint32_t *txidx) 1579 { 1580 struct sk_tx_desc *f = NULL; 1581 struct mbuf *m; 1582 uint32_t cnt = 0, cur, frag; 1583 1584 m = m_head; 1585 cur = frag = *txidx; 1586 1587 /* 1588 * Start packing the mbufs in this chain into 1589 * the fragment pointers. Stop when we run out 1590 * of fragments or hit the end of the mbuf chain. 1591 */ 1592 for (m = m_head; m != NULL; m = m->m_next) { 1593 if (m->m_len != 0) { 1594 if ((SK_TX_RING_CNT - 1595 (sc_if->sk_cdata.sk_tx_cnt + cnt)) < 2) 1596 return(ENOBUFS); 1597 f = &sc_if->sk_rdata->sk_tx_ring[frag]; 1598 f->sk_data_lo = vtophys(mtod(m, vm_offset_t)); 1599 f->sk_ctl = m->m_len | SK_OPCODE_DEFAULT; 1600 if (cnt == 0) 1601 f->sk_ctl |= SK_TXCTL_FIRSTFRAG; 1602 else 1603 f->sk_ctl |= SK_TXCTL_OWN; 1604 cur = frag; 1605 SK_INC(frag, SK_TX_RING_CNT); 1606 cnt++; 1607 } 1608 } 1609 1610 if (m != NULL) 1611 return(ENOBUFS); 1612 1613 sc_if->sk_rdata->sk_tx_ring[cur].sk_ctl |= 1614 SK_TXCTL_LASTFRAG|SK_TXCTL_EOF_INTR; 1615 sc_if->sk_cdata.sk_tx_chain[cur].sk_mbuf = m_head; 1616 sc_if->sk_rdata->sk_tx_ring[*txidx].sk_ctl |= SK_TXCTL_OWN; 1617 sc_if->sk_cdata.sk_tx_cnt += cnt; 1618 1619 *txidx = frag; 1620 1621 return(0); 1622 } 1623 1624 static void 1625 sk_start(struct ifnet *ifp) 1626 { 1627 struct sk_if_softc *sc_if = ifp->if_softc; 1628 struct sk_softc *sc = sc_if->sk_softc; 1629 struct mbuf *m_head = NULL; 1630 uint32_t idx; 1631 int need_trans; 1632 1633 idx = sc_if->sk_cdata.sk_tx_prod; 1634 1635 need_trans = 0; 1636 while(sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf == NULL) { 1637 m_head = ifq_poll(&ifp->if_snd); 1638 if (m_head == NULL) 1639 break; 1640 1641 /* 1642 * Pack the data into the transmit ring. If we 1643 * don't have room, set the OACTIVE flag and wait 1644 * for the NIC to drain the ring. 1645 */ 1646 if (sk_encap(sc_if, m_head, &idx)) { 1647 ifp->if_flags |= IFF_OACTIVE; 1648 break; 1649 } 1650 ifq_dequeue(&ifp->if_snd, m_head); 1651 need_trans = 1; 1652 1653 BPF_MTAP(ifp, m_head); 1654 } 1655 1656 if (!need_trans) 1657 return; 1658 1659 /* Transmit */ 1660 sc_if->sk_cdata.sk_tx_prod = idx; 1661 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START); 1662 1663 /* Set a timeout in case the chip goes out to lunch. */ 1664 ifp->if_timer = 5; 1665 } 1666 1667 1668 static void 1669 sk_watchdog(struct ifnet *ifp) 1670 { 1671 struct sk_if_softc *sc_if; 1672 1673 sc_if = ifp->if_softc; 1674 1675 printf("sk%d: watchdog timeout\n", sc_if->sk_unit); 1676 ifp->if_flags &= ~IFF_RUNNING; 1677 sk_init(sc_if); 1678 1679 if (!ifq_is_empty(&ifp->if_snd)) 1680 ifp->if_start(ifp); 1681 } 1682 1683 static void 1684 skc_shutdown(device_t dev) 1685 { 1686 struct sk_softc *sc = device_get_softc(dev); 1687 1688 lwkt_serialize_enter(&sk_serializer); 1689 1690 /* Turn off the 'driver is loaded' LED. */ 1691 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF); 1692 1693 /* 1694 * Reset the GEnesis controller. Doing this should also 1695 * assert the resets on the attached XMAC(s). 1696 */ 1697 sk_reset(sc); 1698 lwkt_serialize_exit(&sk_serializer); 1699 } 1700 1701 static void 1702 sk_rxeof(struct sk_if_softc *sc_if) 1703 { 1704 struct ifnet *ifp = &sc_if->arpcom.ac_if; 1705 struct mbuf *m; 1706 struct sk_chain *cur_rx; 1707 int i, total_len = 0; 1708 uint32_t rxstat; 1709 1710 i = sc_if->sk_cdata.sk_rx_prod; 1711 cur_rx = &sc_if->sk_cdata.sk_rx_chain[i]; 1712 1713 while(!(sc_if->sk_rdata->sk_rx_ring[i].sk_ctl & SK_RXCTL_OWN)) { 1714 cur_rx = &sc_if->sk_cdata.sk_rx_chain[i]; 1715 rxstat = sc_if->sk_rdata->sk_rx_ring[i].sk_xmac_rxstat; 1716 m = cur_rx->sk_mbuf; 1717 cur_rx->sk_mbuf = NULL; 1718 total_len = SK_RXBYTES(sc_if->sk_rdata->sk_rx_ring[i].sk_ctl); 1719 SK_INC(i, SK_RX_RING_CNT); 1720 1721 if (rxstat & XM_RXSTAT_ERRFRAME) { 1722 ifp->if_ierrors++; 1723 sk_newbuf(sc_if, cur_rx, m); 1724 continue; 1725 } 1726 1727 /* 1728 * Try to allocate a new jumbo buffer. If that 1729 * fails, copy the packet to mbufs and put the 1730 * jumbo buffer back in the ring so it can be 1731 * re-used. If allocating mbufs fails, then we 1732 * have to drop the packet. 1733 */ 1734 if (sk_newbuf(sc_if, cur_rx, NULL) == ENOBUFS) { 1735 struct mbuf *m0; 1736 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 1737 total_len + ETHER_ALIGN, 0, ifp, NULL); 1738 sk_newbuf(sc_if, cur_rx, m); 1739 if (m0 == NULL) { 1740 printf("sk%d: no receive buffers " 1741 "available -- packet dropped!\n", 1742 sc_if->sk_unit); 1743 ifp->if_ierrors++; 1744 continue; 1745 } 1746 m_adj(m0, ETHER_ALIGN); 1747 m = m0; 1748 } else { 1749 m->m_pkthdr.rcvif = ifp; 1750 m->m_pkthdr.len = m->m_len = total_len; 1751 } 1752 1753 ifp->if_ipackets++; 1754 ifp->if_input(ifp, m); 1755 } 1756 1757 sc_if->sk_cdata.sk_rx_prod = i; 1758 } 1759 1760 static void 1761 sk_txeof(struct sk_if_softc *sc_if) 1762 { 1763 struct ifnet *ifp = &sc_if->arpcom.ac_if; 1764 struct sk_tx_desc *cur_tx = NULL; 1765 uint32_t idx; 1766 1767 /* 1768 * Go through our tx ring and free mbufs for those 1769 * frames that have been sent. 1770 */ 1771 idx = sc_if->sk_cdata.sk_tx_cons; 1772 while(idx != sc_if->sk_cdata.sk_tx_prod) { 1773 cur_tx = &sc_if->sk_rdata->sk_tx_ring[idx]; 1774 if (cur_tx->sk_ctl & SK_TXCTL_OWN) 1775 break; 1776 if (cur_tx->sk_ctl & SK_TXCTL_LASTFRAG) 1777 ifp->if_opackets++; 1778 if (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf != NULL) { 1779 m_freem(sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf); 1780 sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf = NULL; 1781 } 1782 sc_if->sk_cdata.sk_tx_cnt--; 1783 SK_INC(idx, SK_TX_RING_CNT); 1784 ifp->if_timer = 0; 1785 } 1786 1787 sc_if->sk_cdata.sk_tx_cons = idx; 1788 1789 if (cur_tx != NULL) 1790 ifp->if_flags &= ~IFF_OACTIVE; 1791 } 1792 1793 static void 1794 sk_tick(void *xsc_if) 1795 { 1796 struct sk_if_softc *sc_if = xsc_if; 1797 struct ifnet *ifp = &sc_if->arpcom.ac_if; 1798 struct mii_data *mii = device_get_softc(sc_if->sk_miibus); 1799 int i; 1800 1801 lwkt_serialize_enter(&sk_serializer); 1802 1803 if ((ifp->if_flags & IFF_UP) == 0) { 1804 lwkt_serialize_exit(&sk_serializer); 1805 return; 1806 } 1807 1808 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 1809 sk_intr_bcom(sc_if); 1810 lwkt_serialize_exit(&sk_serializer); 1811 return; 1812 } 1813 1814 /* 1815 * According to SysKonnect, the correct way to verify that 1816 * the link has come back up is to poll bit 0 of the GPIO 1817 * register three times. This pin has the signal from the 1818 * link_sync pin connected to it; if we read the same link 1819 * state 3 times in a row, we know the link is up. 1820 */ 1821 for (i = 0; i < 3; i++) { 1822 if (SK_XM_READ_2(sc_if, XM_GPIO) & XM_GPIO_GP0_SET) 1823 break; 1824 } 1825 1826 if (i != 3) { 1827 callout_reset(&sc_if->sk_tick_timer, hz, sk_tick, sc_if); 1828 lwkt_serialize_exit(&sk_serializer); 1829 return; 1830 } 1831 1832 /* Turn the GP0 interrupt back on. */ 1833 SK_XM_CLRBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET); 1834 SK_XM_READ_2(sc_if, XM_ISR); 1835 mii_tick(mii); 1836 mii_pollstat(mii); 1837 callout_stop(&sc_if->sk_tick_timer); 1838 lwkt_serialize_exit(&sk_serializer); 1839 } 1840 1841 static void 1842 sk_intr_bcom(struct sk_if_softc *sc_if) 1843 { 1844 struct ifnet *ifp = &sc_if->arpcom.ac_if; 1845 struct mii_data *mii = device_get_softc(sc_if->sk_miibus); 1846 int status; 1847 1848 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 1849 1850 /* 1851 * Read the PHY interrupt register to make sure 1852 * we clear any pending interrupts. 1853 */ 1854 status = sk_xmac_miibus_readreg(sc_if, SK_PHYADDR_BCOM, BRGPHY_MII_ISR); 1855 1856 if ((ifp->if_flags & IFF_RUNNING) == 0) { 1857 sk_init_xmac(sc_if); 1858 return; 1859 } 1860 1861 if (status & (BRGPHY_ISR_LNK_CHG|BRGPHY_ISR_AN_PR)) { 1862 int lstat; 1863 lstat = sk_xmac_miibus_readreg(sc_if, SK_PHYADDR_BCOM, 1864 BRGPHY_MII_AUXSTS); 1865 1866 if (!(lstat & BRGPHY_AUXSTS_LINK) && sc_if->sk_link) { 1867 mii_mediachg(mii); 1868 /* Turn off the link LED. */ 1869 SK_IF_WRITE_1(sc_if, 0, 1870 SK_LINKLED1_CTL, SK_LINKLED_OFF); 1871 sc_if->sk_link = 0; 1872 } else if (status & BRGPHY_ISR_LNK_CHG) { 1873 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM, 1874 BRGPHY_MII_IMR, 0xFF00); 1875 mii_tick(mii); 1876 sc_if->sk_link = 1; 1877 /* Turn on the link LED. */ 1878 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, 1879 SK_LINKLED_ON|SK_LINKLED_LINKSYNC_OFF| 1880 SK_LINKLED_BLINK_OFF); 1881 mii_pollstat(mii); 1882 } else { 1883 mii_tick(mii); 1884 callout_reset(&sc_if->sk_tick_timer, hz, 1885 sk_tick, sc_if); 1886 } 1887 } 1888 1889 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 1890 } 1891 1892 static void 1893 sk_intr_xmac(struct sk_if_softc *sc_if) 1894 { 1895 uint16_t status; 1896 1897 status = SK_XM_READ_2(sc_if, XM_ISR); 1898 1899 /* 1900 * Link has gone down. Start MII tick timeout to 1901 * watch for link resync. 1902 */ 1903 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) { 1904 if (status & XM_ISR_GP0_SET) { 1905 SK_XM_SETBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET); 1906 callout_reset(&sc_if->sk_tick_timer, hz, 1907 sk_tick, sc_if); 1908 } 1909 1910 if (status & XM_ISR_AUTONEG_DONE) { 1911 callout_reset(&sc_if->sk_tick_timer, hz, 1912 sk_tick, sc_if); 1913 } 1914 } 1915 1916 if (status & XM_IMR_TX_UNDERRUN) 1917 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_TXFIFO); 1918 1919 if (status & XM_IMR_RX_OVERRUN) 1920 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_RXFIFO); 1921 1922 status = SK_XM_READ_2(sc_if, XM_ISR); 1923 } 1924 1925 static void 1926 sk_intr_yukon(struct sk_if_softc *sc_if) 1927 { 1928 int status; 1929 1930 status = SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 1931 } 1932 1933 static void 1934 sk_intr(void *xsc) 1935 { 1936 struct sk_softc *sc = xsc; 1937 struct sk_if_softc *sc_if0 = sc->sk_if[SK_PORT_A]; 1938 struct sk_if_softc *sc_if1 = sc->sk_if[SK_PORT_A]; 1939 struct ifnet *ifp0 = NULL, *ifp1 = NULL; 1940 uint32_t status; 1941 1942 if (sc_if0 != NULL) 1943 ifp0 = &sc_if0->arpcom.ac_if; 1944 if (sc_if1 != NULL) 1945 ifp1 = &sc_if1->arpcom.ac_if; 1946 1947 for (;;) { 1948 status = CSR_READ_4(sc, SK_ISSR); 1949 if ((status & sc->sk_intrmask) == 0) 1950 break; 1951 1952 /* Handle receive interrupts first. */ 1953 if (status & SK_ISR_RX1_EOF) { 1954 sk_rxeof(sc_if0); 1955 CSR_WRITE_4(sc, SK_BMU_RX_CSR0, 1956 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START); 1957 } 1958 if (status & SK_ISR_RX2_EOF) { 1959 sk_rxeof(sc_if1); 1960 CSR_WRITE_4(sc, SK_BMU_RX_CSR1, 1961 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START); 1962 } 1963 1964 /* Then transmit interrupts. */ 1965 if (status & SK_ISR_TX1_S_EOF) { 1966 sk_txeof(sc_if0); 1967 CSR_WRITE_4(sc, SK_BMU_TXS_CSR0, 1968 SK_TXBMU_CLR_IRQ_EOF); 1969 } 1970 if (status & SK_ISR_TX2_S_EOF) { 1971 sk_txeof(sc_if1); 1972 CSR_WRITE_4(sc, SK_BMU_TXS_CSR1, 1973 SK_TXBMU_CLR_IRQ_EOF); 1974 } 1975 1976 /* Then MAC interrupts. */ 1977 if (status & SK_ISR_MAC1 && ifp0->if_flags & IFF_RUNNING) { 1978 if (sc->sk_type == SK_GENESIS) 1979 sk_intr_xmac(sc_if0); 1980 else 1981 sk_intr_yukon(sc_if0); 1982 } 1983 1984 if (status & SK_ISR_MAC2 && ifp1->if_flags & IFF_RUNNING) { 1985 if (sc->sk_type == SK_GENESIS) 1986 sk_intr_xmac(sc_if1); 1987 else 1988 sk_intr_yukon(sc_if0); 1989 } 1990 1991 if (status & SK_ISR_EXTERNAL_REG) { 1992 if (ifp0 != NULL && 1993 sc_if0->sk_phytype == SK_PHYTYPE_BCOM) 1994 sk_intr_bcom(sc_if0); 1995 if (ifp1 != NULL && 1996 sc_if1->sk_phytype == SK_PHYTYPE_BCOM) 1997 sk_intr_bcom(sc_if1); 1998 } 1999 } 2000 2001 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2002 2003 if (ifp0 != NULL && !ifq_is_empty(&ifp0->if_snd)) 2004 sk_start(ifp0); 2005 if (ifp1 != NULL && !ifq_is_empty(&ifp0->if_snd)) 2006 sk_start(ifp1); 2007 } 2008 2009 static void 2010 sk_init_xmac(struct sk_if_softc *sc_if) 2011 { 2012 struct sk_softc *sc = sc_if->sk_softc; 2013 struct ifnet *ifp = &sc_if->arpcom.ac_if; 2014 struct sk_bcom_hack bhack[] = { 2015 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 }, { 0x17, 0x0013 }, 2016 { 0x15, 0x0404 }, { 0x17, 0x8006 }, { 0x15, 0x0132 }, { 0x17, 0x8006 }, 2017 { 0x15, 0x0232 }, { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 }, 2018 { 0, 0 } }; 2019 2020 /* Unreset the XMAC. */ 2021 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_UNRESET); 2022 DELAY(1000); 2023 2024 /* Reset the XMAC's internal state. */ 2025 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 2026 2027 /* Save the XMAC II revision */ 2028 sc_if->sk_xmac_rev = XM_XMAC_REV(SK_XM_READ_4(sc_if, XM_DEVID)); 2029 2030 /* 2031 * Perform additional initialization for external PHYs, 2032 * namely for the 1000baseTX cards that use the XMAC's 2033 * GMII mode. 2034 */ 2035 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2036 int i = 0; 2037 uint32_t val; 2038 2039 /* Take PHY out of reset. */ 2040 val = sk_win_read_4(sc, SK_GPIO); 2041 if (sc_if->sk_port == SK_PORT_A) 2042 val |= SK_GPIO_DIR0|SK_GPIO_DAT0; 2043 else 2044 val |= SK_GPIO_DIR2|SK_GPIO_DAT2; 2045 sk_win_write_4(sc, SK_GPIO, val); 2046 2047 /* Enable GMII mode on the XMAC. */ 2048 SK_XM_SETBIT_2(sc_if, XM_HWCFG, XM_HWCFG_GMIIMODE); 2049 2050 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM, 2051 BRGPHY_MII_BMCR, BRGPHY_BMCR_RESET); 2052 DELAY(10000); 2053 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM, 2054 BRGPHY_MII_IMR, 0xFFF0); 2055 2056 /* 2057 * Early versions of the BCM5400 apparently have 2058 * a bug that requires them to have their reserved 2059 * registers initialized to some magic values. I don't 2060 * know what the numbers do, I'm just the messenger. 2061 */ 2062 if (sk_xmac_miibus_readreg(sc_if, SK_PHYADDR_BCOM, 0x03) 2063 == 0x6041) { 2064 while(bhack[i].reg) { 2065 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM, 2066 bhack[i].reg, bhack[i].val); 2067 i++; 2068 } 2069 } 2070 } 2071 2072 /* Set station address */ 2073 SK_XM_WRITE_2(sc_if, XM_PAR0, 2074 *(uint16_t *)(&sc_if->arpcom.ac_enaddr[0])); 2075 SK_XM_WRITE_2(sc_if, XM_PAR1, 2076 *(uint16_t *)(&sc_if->arpcom.ac_enaddr[2])); 2077 SK_XM_WRITE_2(sc_if, XM_PAR2, 2078 *(uint16_t *)(&sc_if->arpcom.ac_enaddr[4])); 2079 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_STATION); 2080 2081 if (ifp->if_flags & IFF_BROADCAST) 2082 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD); 2083 else 2084 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD); 2085 2086 /* We don't need the FCS appended to the packet. */ 2087 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_STRIPFCS); 2088 2089 /* We want short frames padded to 60 bytes. */ 2090 SK_XM_SETBIT_2(sc_if, XM_TXCMD, XM_TXCMD_AUTOPAD); 2091 2092 /* 2093 * Enable the reception of all error frames. This is is 2094 * a necessary evil due to the design of the XMAC. The 2095 * XMAC's receive FIFO is only 8K in size, however jumbo 2096 * frames can be up to 9000 bytes in length. When bad 2097 * frame filtering is enabled, the XMAC's RX FIFO operates 2098 * in 'store and forward' mode. For this to work, the 2099 * entire frame has to fit into the FIFO, but that means 2100 * that jumbo frames larger than 8192 bytes will be 2101 * truncated. Disabling all bad frame filtering causes 2102 * the RX FIFO to operate in streaming mode, in which 2103 * case the XMAC will start transfering frames out of the 2104 * RX FIFO as soon as the FIFO threshold is reached. 2105 */ 2106 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_BADFRAMES| 2107 XM_MODE_RX_GIANTS|XM_MODE_RX_RUNTS|XM_MODE_RX_CRCERRS| 2108 XM_MODE_RX_INRANGELEN); 2109 2110 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 2111 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK); 2112 else 2113 SK_XM_CLRBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK); 2114 2115 /* 2116 * Bump up the transmit threshold. This helps hold off transmit 2117 * underruns when we're blasting traffic from both ports at once. 2118 */ 2119 SK_XM_WRITE_2(sc_if, XM_TX_REQTHRESH, SK_XM_TX_FIFOTHRESH); 2120 2121 /* Set promiscuous mode */ 2122 sk_setpromisc(sc_if); 2123 2124 /* Set multicast filter */ 2125 sk_setmulti(sc_if); 2126 2127 /* Clear and enable interrupts */ 2128 SK_XM_READ_2(sc_if, XM_ISR); 2129 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) 2130 SK_XM_WRITE_2(sc_if, XM_IMR, XM_INTRS); 2131 else 2132 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 2133 2134 /* Configure MAC arbiter */ 2135 switch(sc_if->sk_xmac_rev) { 2136 case XM_XMAC_REV_B2: 2137 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_B2); 2138 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_B2); 2139 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_B2); 2140 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_B2); 2141 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_B2); 2142 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_B2); 2143 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_B2); 2144 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_B2); 2145 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2); 2146 break; 2147 case XM_XMAC_REV_C1: 2148 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_C1); 2149 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_C1); 2150 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_C1); 2151 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_C1); 2152 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_C1); 2153 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_C1); 2154 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_C1); 2155 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_C1); 2156 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2); 2157 break; 2158 default: 2159 break; 2160 } 2161 sk_win_write_2(sc, SK_MACARB_CTL, 2162 SK_MACARBCTL_UNRESET|SK_MACARBCTL_FASTOE_OFF); 2163 2164 sc_if->sk_link = 1; 2165 } 2166 2167 static void 2168 sk_init_yukon(struct sk_if_softc *sc_if) 2169 { 2170 struct ifnet *ifp = &sc_if->arpcom.ac_if; 2171 uint32_t phy; 2172 uint16_t reg; 2173 int i; 2174 2175 /* GMAC and GPHY Reset */ 2176 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_SET); 2177 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 2178 DELAY(1000); 2179 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_CLEAR); 2180 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 2181 DELAY(1000); 2182 2183 phy = SK_GPHY_INT_POL_HI | SK_GPHY_DIS_FC | SK_GPHY_DIS_SLEEP | 2184 SK_GPHY_ENA_XC | SK_GPHY_ANEG_ALL | SK_GPHY_ENA_PAUSE; 2185 2186 switch(sc_if->sk_softc->sk_pmd) { 2187 case IFM_1000_SX: 2188 case IFM_1000_LX: 2189 phy |= SK_GPHY_FIBER; 2190 break; 2191 2192 case IFM_1000_CX: 2193 case IFM_1000_T: 2194 phy |= SK_GPHY_COPPER; 2195 break; 2196 } 2197 2198 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_SET); 2199 DELAY(1000); 2200 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_CLEAR); 2201 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_LOOP_OFF | 2202 SK_GMAC_PAUSE_ON | SK_GMAC_RESET_CLEAR); 2203 2204 /* unused read of the interrupt source register */ 2205 SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 2206 2207 reg = SK_YU_READ_2(sc_if, YUKON_PAR); 2208 2209 /* MIB Counter Clear Mode set */ 2210 reg |= YU_PAR_MIB_CLR; 2211 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2212 2213 /* MIB Counter Clear Mode clear */ 2214 reg &= ~YU_PAR_MIB_CLR; 2215 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2216 2217 /* receive control reg */ 2218 SK_YU_WRITE_2(sc_if, YUKON_RCR, YU_RCR_CRCR); 2219 2220 /* transmit parameter register */ 2221 SK_YU_WRITE_2(sc_if, YUKON_TPR, YU_TPR_JAM_LEN(0x3) | 2222 YU_TPR_JAM_IPG(0xb) | YU_TPR_JAM2DATA_IPG(0x1a) ); 2223 2224 /* serial mode register */ 2225 reg = YU_SMR_DATA_BLIND(0x1c) | YU_SMR_MFL_VLAN | YU_SMR_IPG_DATA(0x1e); 2226 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 2227 reg |= YU_SMR_MFL_JUMBO; 2228 SK_YU_WRITE_2(sc_if, YUKON_SMR, reg); 2229 2230 /* Setup Yukon's address */ 2231 for (i = 0; i < 3; i++) { 2232 /* Write Source Address 1 (unicast filter) */ 2233 SK_YU_WRITE_2(sc_if, YUKON_SAL1 + i * 4, 2234 sc_if->arpcom.ac_enaddr[i * 2] | 2235 sc_if->arpcom.ac_enaddr[i * 2 + 1] << 8); 2236 } 2237 2238 for (i = 0; i < 3; i++) { 2239 reg = sk_win_read_2(sc_if->sk_softc, 2240 SK_MAC1_0 + i * 2 + sc_if->sk_port * 8); 2241 SK_YU_WRITE_2(sc_if, YUKON_SAL2 + i * 4, reg); 2242 } 2243 2244 /* Set promiscuous mode */ 2245 sk_setpromisc(sc_if); 2246 2247 /* Set multicast filter */ 2248 sk_setmulti(sc_if); 2249 2250 /* enable interrupt mask for counter overflows */ 2251 SK_YU_WRITE_2(sc_if, YUKON_TIMR, 0); 2252 SK_YU_WRITE_2(sc_if, YUKON_RIMR, 0); 2253 SK_YU_WRITE_2(sc_if, YUKON_TRIMR, 0); 2254 2255 /* Configure RX MAC FIFO */ 2256 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_CLEAR); 2257 SK_IF_WRITE_4(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_OPERATION_ON); 2258 2259 /* Configure TX MAC FIFO */ 2260 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_CLEAR); 2261 SK_IF_WRITE_4(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_OPERATION_ON); 2262 } 2263 2264 /* 2265 * Note that to properly initialize any part of the GEnesis chip, 2266 * you first have to take it out of reset mode. 2267 */ 2268 static void 2269 sk_init(void *xsc) 2270 { 2271 struct sk_if_softc *sc_if = xsc; 2272 struct sk_softc *sc = sc_if->sk_softc; 2273 struct ifnet *ifp = &sc_if->arpcom.ac_if; 2274 struct mii_data *mii = device_get_softc(sc_if->sk_miibus); 2275 uint16_t reg; 2276 2277 crit_enter(); 2278 2279 if (ifp->if_flags & IFF_RUNNING) { 2280 crit_exit(); 2281 return; 2282 } 2283 2284 /* Cancel pending I/O and free all RX/TX buffers. */ 2285 sk_stop(sc_if); 2286 2287 if (sc->sk_type == SK_GENESIS) { 2288 /* Configure LINK_SYNC LED */ 2289 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_ON); 2290 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, 2291 SK_LINKLED_LINKSYNC_ON); 2292 2293 /* Configure RX LED */ 2294 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, 2295 SK_RXLEDCTL_COUNTER_START); 2296 2297 /* Configure TX LED */ 2298 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, 2299 SK_TXLEDCTL_COUNTER_START); 2300 } 2301 2302 /* Configure I2C registers */ 2303 2304 /* Configure XMAC(s) */ 2305 switch (sc->sk_type) { 2306 case SK_GENESIS: 2307 sk_init_xmac(sc_if); 2308 break; 2309 case SK_YUKON: 2310 sk_init_yukon(sc_if); 2311 break; 2312 } 2313 mii_mediachg(mii); 2314 2315 if (sc->sk_type == SK_GENESIS) { 2316 /* Configure MAC FIFOs */ 2317 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_UNRESET); 2318 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_END, SK_FIFO_END); 2319 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_ON); 2320 2321 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_UNRESET); 2322 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_END, SK_FIFO_END); 2323 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_ON); 2324 } 2325 2326 /* Configure transmit arbiter(s) */ 2327 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, 2328 SK_TXARCTL_ON | SK_TXARCTL_FSYNC_ON); 2329 2330 /* Configure RAMbuffers */ 2331 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_UNRESET); 2332 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_START, sc_if->sk_rx_ramstart); 2333 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_WR_PTR, sc_if->sk_rx_ramstart); 2334 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_RD_PTR, sc_if->sk_rx_ramstart); 2335 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_END, sc_if->sk_rx_ramend); 2336 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_ON); 2337 2338 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_UNRESET); 2339 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_STORENFWD_ON); 2340 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_START, sc_if->sk_tx_ramstart); 2341 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_WR_PTR, sc_if->sk_tx_ramstart); 2342 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_RD_PTR, sc_if->sk_tx_ramstart); 2343 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_END, sc_if->sk_tx_ramend); 2344 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_ON); 2345 2346 /* Configure BMUs */ 2347 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_ONLINE); 2348 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_LO, 2349 vtophys(&sc_if->sk_rdata->sk_rx_ring[0])); 2350 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_HI, 0); 2351 2352 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_ONLINE); 2353 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_LO, 2354 vtophys(&sc_if->sk_rdata->sk_tx_ring[0])); 2355 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_HI, 0); 2356 2357 /* Init descriptors */ 2358 if (sk_init_rx_ring(sc_if) == ENOBUFS) { 2359 printf("sk%d: initialization failed: no " 2360 "memory for rx buffers\n", sc_if->sk_unit); 2361 sk_stop(sc_if); 2362 crit_exit(); 2363 return; 2364 } 2365 sk_init_tx_ring(sc_if); 2366 2367 /* Configure interrupt handling */ 2368 CSR_READ_4(sc, SK_ISSR); 2369 if (sc_if->sk_port == SK_PORT_A) 2370 sc->sk_intrmask |= SK_INTRS1; 2371 else 2372 sc->sk_intrmask |= SK_INTRS2; 2373 2374 sc->sk_intrmask |= SK_ISR_EXTERNAL_REG; 2375 2376 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2377 2378 /* Start BMUs. */ 2379 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_RX_START); 2380 2381 switch(sc->sk_type) { 2382 case SK_GENESIS: 2383 /* Enable XMACs TX and RX state machines */ 2384 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_IGNPAUSE); 2385 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, 2386 XM_MMUCMD_TX_ENB | XM_MMUCMD_RX_ENB); 2387 break; 2388 case SK_YUKON: 2389 reg = SK_YU_READ_2(sc_if, YUKON_GPCR); 2390 reg |= YU_GPCR_TXEN | YU_GPCR_RXEN; 2391 reg &= ~(YU_GPCR_SPEED_EN | YU_GPCR_DPLX_EN); 2392 SK_YU_WRITE_2(sc_if, YUKON_GPCR, reg); 2393 } 2394 2395 ifp->if_flags |= IFF_RUNNING; 2396 ifp->if_flags &= ~IFF_OACTIVE; 2397 2398 crit_exit(); 2399 } 2400 2401 static void 2402 sk_stop(struct sk_if_softc *sc_if) 2403 { 2404 int i; 2405 struct sk_softc *sc = sc_if->sk_softc; 2406 struct ifnet *ifp = &sc_if->arpcom.ac_if; 2407 2408 callout_stop(&sc_if->sk_tick_timer); 2409 2410 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2411 uint32_t val; 2412 2413 /* Put PHY back into reset. */ 2414 val = sk_win_read_4(sc, SK_GPIO); 2415 if (sc_if->sk_port == SK_PORT_A) { 2416 val |= SK_GPIO_DIR0; 2417 val &= ~SK_GPIO_DAT0; 2418 } else { 2419 val |= SK_GPIO_DIR2; 2420 val &= ~SK_GPIO_DAT2; 2421 } 2422 sk_win_write_4(sc, SK_GPIO, val); 2423 } 2424 2425 /* Turn off various components of this interface. */ 2426 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 2427 switch (sc->sk_type) { 2428 case SK_GENESIS: 2429 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_RESET); 2430 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_RESET); 2431 break; 2432 case SK_YUKON: 2433 SK_IF_WRITE_1(sc_if,0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_SET); 2434 SK_IF_WRITE_1(sc_if,0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_SET); 2435 break; 2436 } 2437 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_OFFLINE); 2438 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_RESET | SK_RBCTL_OFF); 2439 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_OFFLINE); 2440 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, 2441 SK_RBCTL_RESET | SK_RBCTL_OFF); 2442 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_OFF); 2443 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2444 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2445 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_OFF); 2446 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_OFF); 2447 2448 /* Disable interrupts */ 2449 if (sc_if->sk_port == SK_PORT_A) 2450 sc->sk_intrmask &= ~SK_INTRS1; 2451 else 2452 sc->sk_intrmask &= ~SK_INTRS2; 2453 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2454 2455 SK_XM_READ_2(sc_if, XM_ISR); 2456 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 2457 2458 /* Free RX and TX mbufs still in the queues. */ 2459 for (i = 0; i < SK_RX_RING_CNT; i++) { 2460 if (sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf != NULL) { 2461 m_freem(sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf); 2462 sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL; 2463 } 2464 } 2465 2466 for (i = 0; i < SK_TX_RING_CNT; i++) { 2467 if (sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf != NULL) { 2468 m_freem(sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf); 2469 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL; 2470 } 2471 } 2472 2473 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 2474 } 2475