1 /* 2 * Copyright (c) 1997, 1998, 1999, 2000 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: /c/ncvs/src/sys/pci/if_skreg.h,v 1.9 2000/04/22 02:16:37 wpaul Exp $ 33 * $OpenBSD: if_skreg.h,v 1.39 2006/08/20 19:15:46 brad Exp $ 34 * $DragonFly: src/sys/dev/netif/sk/if_skreg.h,v 1.12 2006/11/14 12:52:31 sephe Exp $ 35 */ 36 37 /* 38 * Copyright (c) 2003 Nathan L. Binkert <binkertn@umich.edu> 39 * 40 * Permission to use, copy, modify, and distribute this software for any 41 * purpose with or without fee is hereby granted, provided that the above 42 * copyright notice and this permission notice appear in all copies. 43 * 44 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 45 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 46 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 47 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 48 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 49 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 50 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 51 */ 52 53 /* 54 * GEnesis registers. The GEnesis chip has a 256-byte I/O window 55 * but internally it has a 16K register space. This 16K space is 56 * divided into 128-byte blocks. The first 128 bytes of the I/O 57 * window represent the first block, which is permanently mapped 58 * at the start of the window. The other 127 blocks can be mapped 59 * to the second 128 bytes of the I/O window by setting the desired 60 * block value in the RAP register in block 0. Not all of the 127 61 * blocks are actually used. Most registers are 32 bits wide, but 62 * there are a few 16-bit and 8-bit ones as well. 63 */ 64 65 /* Start of remappable register window. */ 66 #define SK_WIN_BASE 0x0080 67 68 /* Size of a window */ 69 #define SK_WIN_LEN 0x80 70 71 #define SK_WIN_MASK 0x3F80 72 #define SK_REG_MASK 0x7F 73 74 /* Compute the window of a given register (for the RAP register) */ 75 #define SK_WIN(reg) (((reg) & SK_WIN_MASK) / SK_WIN_LEN) 76 77 /* Compute the relative offset of a register within the window */ 78 #define SK_REG(reg) ((reg) & SK_REG_MASK) 79 80 #define SK_PORT_A 0 81 #define SK_PORT_B 1 82 83 /* 84 * Compute offset of port-specific register. Since there are two 85 * ports, there are two of some GEnesis modules (e.g. two sets of 86 * DMA queues, two sets of FIFO control registers, etc...). Normally, 87 * the block for port 0 is at offset 0x0 and the block for port 1 is 88 * at offset 0x80 (i.e. the next page over). However for the transmit 89 * BMUs and RAMbuffers, there are two blocks for each port: one for 90 * the sync transmit queue and one for the async queue (which we don't 91 * use). However instead of ordering them like this: 92 * TX sync 1 / TX sync 2 / TX async 1 / TX async 2 93 * SysKonnect has instead ordered them like this: 94 * TX sync 1 / TX async 1 / TX sync 2 / TX async 2 95 * This means that when referencing the TX BMU and RAMbuffer registers, 96 * we have to double the block offset (0x80 * 2) in order to reach the 97 * second queue. This prevents us from using the same formula 98 * (sk_port * 0x80) to compute the offsets for all of the port-specific 99 * blocks: we need an extra offset for the BMU and RAMbuffer registers. 100 * The simplest thing is to provide an extra argument to these macros: 101 * the 'skip' parameter. The 'skip' value is the number of extra pages 102 * for skip when computing the port0/port1 offsets. For most registers, 103 * the skip value is 0; for the BMU and RAMbuffer registers, it's 1. 104 */ 105 #define SK_IF_READ_4(sc_if, skip, reg) \ 106 sk_win_read_4(sc_if->sk_softc, reg + \ 107 ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN)) 108 #define SK_IF_READ_2(sc_if, skip, reg) \ 109 sk_win_read_2(sc_if->sk_softc, reg + \ 110 ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN)) 111 #define SK_IF_READ_1(sc_if, skip, reg) \ 112 sk_win_read_1(sc_if->sk_softc, reg + \ 113 ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN)) 114 115 #define SK_IF_WRITE_4(sc_if, skip, reg, val) \ 116 sk_win_write_4(sc_if->sk_softc, \ 117 reg + ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN), val) 118 #define SK_IF_WRITE_2(sc_if, skip, reg, val) \ 119 sk_win_write_2(sc_if->sk_softc, \ 120 reg + ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN), val) 121 #define SK_IF_WRITE_1(sc_if, skip, reg, val) \ 122 sk_win_write_1(sc_if->sk_softc, \ 123 reg + ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN), val) 124 125 /* Block 0 registers, permanently mapped at iobase. */ 126 #define SK_RAP 0x0000 127 #define SK_CSR 0x0004 128 #define SK_LED 0x0006 129 #define SK_ISR 0x0008 /* interrupt source */ 130 #define SK_IMR 0x000C /* interrupt mask */ 131 #define SK_IESR 0x0010 /* interrupt hardware error source */ 132 #define SK_IEMR 0x0014 /* interrupt hardware error mask */ 133 #define SK_ISSR 0x0018 /* special interrupt source */ 134 #define SK_Y2_ISSR2 0x001C 135 #define SK_Y2_ISSR3 0x0020 136 #define SK_Y2_EISR 0x0024 137 #define SK_Y2_LISR 0x0028 138 #define SK_Y2_ICR 0x002C 139 #define SK_XM_IMR0 0x0020 140 #define SK_XM_ISR0 0x0028 141 #define SK_XM_PHYADDR0 0x0030 142 #define SK_XM_PHYDATA0 0x0034 143 #define SK_XM_IMR1 0x0040 144 #define SK_XM_ISR1 0x0048 145 #define SK_XM_PHYADDR1 0x0050 146 #define SK_XM_PHYDATA1 0x0054 147 #define SK_BMU_RX_CSR0 0x0060 148 #define SK_BMU_RX_CSR1 0x0064 149 #define SK_BMU_TXS_CSR0 0x0068 150 #define SK_BMU_TXA_CSR0 0x006C 151 #define SK_BMU_TXS_CSR1 0x0070 152 #define SK_BMU_TXA_CSR1 0x0074 153 154 /* SK_CSR register */ 155 #define SK_CSR_SW_RESET 0x0001 156 #define SK_CSR_SW_UNRESET 0x0002 157 #define SK_CSR_MASTER_RESET 0x0004 158 #define SK_CSR_MASTER_UNRESET 0x0008 159 #define SK_CSR_MASTER_STOP 0x0010 160 #define SK_CSR_MASTER_DONE 0x0020 161 #define SK_CSR_SW_IRQ_CLEAR 0x0040 162 #define SK_CSR_SW_IRQ_SET 0x0080 163 #define SK_CSR_SLOTSIZE 0x0100 /* 1 == 64 bits, 0 == 32 */ 164 #define SK_CSR_BUSCLOCK 0x0200 /* 1 == 33/66 MHz, = 33 */ 165 #define SK_CSR_ASF_OFF 0x1000 166 #define SK_CSR_ASF_ON 0x2000 167 168 /* SK_LED register */ 169 #define SK_LED_GREEN_OFF 0x01 170 #define SK_LED_GREEN_ON 0x02 171 172 /* SK_ISR register */ 173 #define SK_ISR_TX2_AS_CHECK 0x00000001 174 #define SK_ISR_TX2_AS_EOF 0x00000002 175 #define SK_ISR_TX2_AS_EOB 0x00000004 176 #define SK_ISR_TX2_S_CHECK 0x00000008 177 #define SK_ISR_TX2_S_EOF 0x00000010 178 #define SK_ISR_TX2_S_EOB 0x00000020 179 #define SK_ISR_TX1_AS_CHECK 0x00000040 180 #define SK_ISR_TX1_AS_EOF 0x00000080 181 #define SK_ISR_TX1_AS_EOB 0x00000100 182 #define SK_ISR_TX1_S_CHECK 0x00000200 183 #define SK_ISR_TX1_S_EOF 0x00000400 184 #define SK_ISR_TX1_S_EOB 0x00000800 185 #define SK_ISR_RX2_CHECK 0x00001000 186 #define SK_ISR_RX2_EOF 0x00002000 187 #define SK_ISR_RX2_EOB 0x00004000 188 #define SK_ISR_RX1_CHECK 0x00008000 189 #define SK_ISR_RX1_EOF 0x00010000 190 #define SK_ISR_RX1_EOB 0x00020000 191 #define SK_ISR_LINK2_OFLOW 0x00040000 192 #define SK_ISR_MAC2 0x00080000 193 #define SK_ISR_LINK1_OFLOW 0x00100000 194 #define SK_ISR_MAC1 0x00200000 195 #define SK_ISR_TIMER 0x00400000 196 #define SK_ISR_EXTERNAL_REG 0x00800000 197 #define SK_ISR_SW 0x01000000 198 #define SK_ISR_I2C_RDY 0x02000000 199 #define SK_ISR_TX2_TIMEO 0x04000000 200 #define SK_ISR_TX1_TIMEO 0x08000000 201 #define SK_ISR_RX2_TIMEO 0x10000000 202 #define SK_ISR_RX1_TIMEO 0x20000000 203 #define SK_ISR_RSVD 0x40000000 204 #define SK_ISR_HWERR 0x80000000 205 206 /* SK_IMR register */ 207 #define SK_IMR_TX2_AS_CHECK 0x00000001 208 #define SK_IMR_TX2_AS_EOF 0x00000002 209 #define SK_IMR_TX2_AS_EOB 0x00000004 210 #define SK_IMR_TX2_S_CHECK 0x00000008 211 #define SK_IMR_TX2_S_EOF 0x00000010 212 #define SK_IMR_TX2_S_EOB 0x00000020 213 #define SK_IMR_TX1_AS_CHECK 0x00000040 214 #define SK_IMR_TX1_AS_EOF 0x00000080 215 #define SK_IMR_TX1_AS_EOB 0x00000100 216 #define SK_IMR_TX1_S_CHECK 0x00000200 217 #define SK_IMR_TX1_S_EOF 0x00000400 218 #define SK_IMR_TX1_S_EOB 0x00000800 219 #define SK_IMR_RX2_CHECK 0x00001000 220 #define SK_IMR_RX2_EOF 0x00002000 221 #define SK_IMR_RX2_EOB 0x00004000 222 #define SK_IMR_RX1_CHECK 0x00008000 223 #define SK_IMR_RX1_EOF 0x00010000 224 #define SK_IMR_RX1_EOB 0x00020000 225 #define SK_IMR_LINK2_OFLOW 0x00040000 226 #define SK_IMR_MAC2 0x00080000 227 #define SK_IMR_LINK1_OFLOW 0x00100000 228 #define SK_IMR_MAC1 0x00200000 229 #define SK_IMR_TIMER 0x00400000 230 #define SK_IMR_EXTERNAL_REG 0x00800000 231 #define SK_IMR_SW 0x01000000 232 #define SK_IMR_I2C_RDY 0x02000000 233 #define SK_IMR_TX2_TIMEO 0x04000000 234 #define SK_IMR_TX1_TIMEO 0x08000000 235 #define SK_IMR_RX2_TIMEO 0x10000000 236 #define SK_IMR_RX1_TIMEO 0x20000000 237 #define SK_IMR_RSVD 0x40000000 238 #define SK_IMR_HWERR 0x80000000 239 240 #define SK_INTRS1 \ 241 (SK_IMR_RX1_EOF|SK_IMR_TX1_S_EOF|SK_IMR_MAC1) 242 243 #define SK_INTRS2 \ 244 (SK_IMR_RX2_EOF|SK_IMR_TX2_S_EOF|SK_IMR_MAC2) 245 246 /* SK_IESR register */ 247 #define SK_IESR_PAR_RX2 0x00000001 248 #define SK_IESR_PAR_RX1 0x00000002 249 #define SK_IESR_PAR_MAC2 0x00000004 250 #define SK_IESR_PAR_MAC1 0x00000008 251 #define SK_IESR_PAR_WR_RAM 0x00000010 252 #define SK_IESR_PAR_RD_RAM 0x00000020 253 #define SK_IESR_NO_TSTAMP_MAC2 0x00000040 254 #define SK_IESR_NO_TSTAMO_MAC1 0x00000080 255 #define SK_IESR_NO_STS_MAC2 0x00000100 256 #define SK_IESR_NO_STS_MAC1 0x00000200 257 #define SK_IESR_IRQ_STS 0x00000400 258 #define SK_IESR_MASTERERR 0x00000800 259 260 /* SK_IEMR register */ 261 #define SK_IEMR_PAR_RX2 0x00000001 262 #define SK_IEMR_PAR_RX1 0x00000002 263 #define SK_IEMR_PAR_MAC2 0x00000004 264 #define SK_IEMR_PAR_MAC1 0x00000008 265 #define SK_IEMR_PAR_WR_RAM 0x00000010 266 #define SK_IEMR_PAR_RD_RAM 0x00000020 267 #define SK_IEMR_NO_TSTAMP_MAC2 0x00000040 268 #define SK_IEMR_NO_TSTAMO_MAC1 0x00000080 269 #define SK_IEMR_NO_STS_MAC2 0x00000100 270 #define SK_IEMR_NO_STS_MAC1 0x00000200 271 #define SK_IEMR_IRQ_STS 0x00000400 272 #define SK_IEMR_MASTERERR 0x00000800 273 274 /* Block 2 */ 275 #define SK_MAC0_0 0x0100 276 #define SK_MAC0_1 0x0104 277 #define SK_MAC1_0 0x0108 278 #define SK_MAC1_1 0x010C 279 #define SK_MAC2_0 0x0110 280 #define SK_MAC2_1 0x0114 281 #define SK_CONNTYPE 0x0118 282 #define SK_PMDTYPE 0x0119 283 #define SK_CONFIG 0x011A 284 #define SK_CHIPVER 0x011B 285 #define SK_EPROM0 0x011C 286 #define SK_EPROM1 0x011D /* yukon/genesis */ 287 #define SK_EPROM2 0x011E /* yukon/genesis */ 288 #define SK_EPROM3 0x011F 289 #define SK_EP_ADDR 0x0120 290 #define SK_EP_DATA 0x0124 291 #define SK_EP_LOADCTL 0x0128 292 #define SK_EP_LOADTST 0x0129 293 #define SK_TIMERINIT 0x0130 294 #define SK_TIMER 0x0134 295 #define SK_TIMERCTL 0x0138 296 #define SK_TIMERTST 0x0139 297 #define SK_IMTIMERINIT 0x0140 298 #define SK_IMTIMER 0x0144 299 #define SK_IMTIMERCTL 0x0148 300 #define SK_IMTIMERTST 0x0149 301 #define SK_IMMR 0x014C 302 #define SK_IHWEMR 0x0150 303 #define SK_TESTCTL1 0x0158 304 #define SK_TESTCTL2 0x0159 305 #define SK_GPIO 0x015C 306 #define SK_I2CHWCTL 0x0160 307 #define SK_I2CHWDATA 0x0164 308 #define SK_I2CHWIRQ 0x0168 309 #define SK_I2CSW 0x016C 310 #define SK_BLNKINIT 0x0170 311 #define SK_BLNKCOUNT 0x0174 312 #define SK_BLNKCTL 0x0178 313 #define SK_BLNKSTS 0x0179 314 #define SK_BLNKTST 0x017A 315 316 /* Values for SK_CHIPVER */ 317 #define SK_GENESIS 0x0A 318 #define SK_YUKON 0xB0 319 #define SK_YUKON_LITE 0xB1 320 #define SK_YUKON_LP 0xB2 321 322 #define SK_IS_GENESIS(sc) \ 323 ((sc)->sk_type == SK_GENESIS) 324 #define SK_IS_YUKON(sc) \ 325 ((sc)->sk_type >= SK_YUKON && (sc)->sk_type <= SK_YUKON_LP) 326 327 /* Known revisions in SK_CONFIG */ 328 #define SK_YUKON_LITE_REV_A0 0x0 /* invented, see test in skc_attach */ 329 #define SK_YUKON_LITE_REV_A1 0x3 330 #define SK_YUKON_LITE_REV_A3 0x7 331 332 #define SK_IMCTL_IRQ_CLEAR 0x01 333 #define SK_IMCTL_STOP 0x02 334 #define SK_IMCTL_START 0x04 335 336 /* Number of ticks per usec for interrupt moderation */ 337 #define SK_IMTIMER_TICKS_GENESIS 53 338 #define SK_IMTIMER_TICKS_YUKON 78 339 #define SK_IMTIMER_TICKS_YUKON_EC 125 340 #define SK_IM_USECS(x) ((x) * imtimer_ticks) 341 342 /* 343 * The SK_EPROM0 register contains a byte that describes the 344 * amount of SRAM mounted on the NIC. The value also tells if 345 * the chips are 64K or 128K. This affects the RAMbuffer address 346 * offset that we need to use. 347 */ 348 #define SK_RAMSIZE_512K_64 0x1 349 #define SK_RAMSIZE_1024K_128 0x2 350 #define SK_RAMSIZE_1024K_64 0x3 351 #define SK_RAMSIZE_2048K_128 0x4 352 353 #define SK_RBOFF_0 0x0 354 #define SK_RBOFF_80000 0x80000 355 356 /* 357 * SK_EEPROM1 contains the PHY type, which may be XMAC for 358 * fiber-based cards or BCOM for 1000baseT cards with a Broadcom 359 * PHY. 360 */ 361 #define SK_PHYTYPE_XMAC 0 /* integeated XMAC II PHY */ 362 #define SK_PHYTYPE_BCOM 1 /* Broadcom BCM5400 */ 363 #define SK_PHYTYPE_LONE 2 /* Level One LXT1000 */ 364 #define SK_PHYTYPE_NAT 3 /* National DP83891 */ 365 #define SK_PHYTYPE_MARV_COPPER 4 /* Marvell 88E1011S */ 366 #define SK_PHYTYPE_MARV_FIBER 5 /* Marvell 88E1011S (fiber) */ 367 368 /* 369 * PHY addresses. 370 */ 371 #define SK_PHYADDR_XMAC 0x0 372 #define SK_PHYADDR_BCOM 0x1 373 #define SK_PHYADDR_LONE 0x3 374 #define SK_PHYADDR_NAT 0x0 375 #define SK_PHYADDR_MARV 0x0 376 377 #define SK_CONFIG_SINGLEMAC 0x01 378 #define SK_CONFIG_DIS_DSL_CLK 0x02 379 380 #define SK_PMD_1000BASETX_ALT 0x31 381 #define SK_PMD_1000BASECX 0x43 382 #define SK_PMD_1000BASELX 0x4C 383 #define SK_PMD_1000BASESX 0x53 384 #define SK_PMD_1000BASETX 0x54 385 386 /* GPIO bits */ 387 #define SK_GPIO_DAT0 0x00000001 388 #define SK_GPIO_DAT1 0x00000002 389 #define SK_GPIO_DAT2 0x00000004 390 #define SK_GPIO_DAT3 0x00000008 391 #define SK_GPIO_DAT4 0x00000010 392 #define SK_GPIO_DAT5 0x00000020 393 #define SK_GPIO_DAT6 0x00000040 394 #define SK_GPIO_DAT7 0x00000080 395 #define SK_GPIO_DAT8 0x00000100 396 #define SK_GPIO_DAT9 0x00000200 397 #define SK_GPIO_DIR0 0x00010000 398 #define SK_GPIO_DIR1 0x00020000 399 #define SK_GPIO_DIR2 0x00040000 400 #define SK_GPIO_DIR3 0x00080000 401 #define SK_GPIO_DIR4 0x00100000 402 #define SK_GPIO_DIR5 0x00200000 403 #define SK_GPIO_DIR6 0x00400000 404 #define SK_GPIO_DIR7 0x00800000 405 #define SK_GPIO_DIR8 0x01000000 406 #define SK_GPIO_DIR9 0x02000000 407 408 /* Block 3 Ram interface and MAC arbiter registers */ 409 #define SK_RAMADDR 0x0180 410 #define SK_RAMDATA0 0x0184 411 #define SK_RAMDATA1 0x0188 412 #define SK_TO0 0x0190 413 #define SK_TO1 0x0191 414 #define SK_TO2 0x0192 415 #define SK_TO3 0x0193 416 #define SK_TO4 0x0194 417 #define SK_TO5 0x0195 418 #define SK_TO6 0x0196 419 #define SK_TO7 0x0197 420 #define SK_TO8 0x0198 421 #define SK_TO9 0x0199 422 #define SK_TO10 0x019A 423 #define SK_TO11 0x019B 424 #define SK_RITIMEO_TMR 0x019C 425 #define SK_RAMCTL 0x01A0 426 #define SK_RITIMER_TST 0x01A2 427 428 #define SK_RAMCTL_RESET 0x0001 429 #define SK_RAMCTL_UNRESET 0x0002 430 #define SK_RAMCTL_CLR_IRQ_WPAR 0x0100 431 #define SK_RAMCTL_CLR_IRQ_RPAR 0x0200 432 433 /* Mac arbiter registers */ 434 #define SK_MINIT_RX1 0x01B0 435 #define SK_MINIT_RX2 0x01B1 436 #define SK_MINIT_TX1 0x01B2 437 #define SK_MINIT_TX2 0x01B3 438 #define SK_MTIMEO_RX1 0x01B4 439 #define SK_MTIMEO_RX2 0x01B5 440 #define SK_MTIMEO_TX1 0x01B6 441 #define SK_MTIEMO_TX2 0x01B7 442 #define SK_MACARB_CTL 0x01B8 443 #define SK_MTIMER_TST 0x01BA 444 #define SK_RCINIT_RX1 0x01C0 445 #define SK_RCINIT_RX2 0x01C1 446 #define SK_RCINIT_TX1 0x01C2 447 #define SK_RCINIT_TX2 0x01C3 448 #define SK_RCTIMEO_RX1 0x01C4 449 #define SK_RCTIMEO_RX2 0x01C5 450 #define SK_RCTIMEO_TX1 0x01C6 451 #define SK_RCTIMEO_TX2 0x01C7 452 #define SK_RECOVERY_CTL 0x01C8 453 #define SK_RCTIMER_TST 0x01CA 454 455 /* Packet arbiter registers */ 456 #define SK_RXPA1_TINIT 0x01D0 457 #define SK_RXPA2_TINIT 0x01D4 458 #define SK_TXPA1_TINIT 0x01D8 459 #define SK_TXPA2_TINIT 0x01DC 460 #define SK_RXPA1_TIMEO 0x01E0 461 #define SK_RXPA2_TIMEO 0x01E4 462 #define SK_TXPA1_TIMEO 0x01E8 463 #define SK_TXPA2_TIMEO 0x01EC 464 #define SK_PKTARB_CTL 0x01F0 465 #define SK_PKTATB_TST 0x01F2 466 467 #define SK_PKTARB_TIMEOUT 0x2000 468 469 #define SK_PKTARBCTL_RESET 0x0001 470 #define SK_PKTARBCTL_UNRESET 0x0002 471 #define SK_PKTARBCTL_RXTO1_OFF 0x0004 472 #define SK_PKTARBCTL_RXTO1_ON 0x0008 473 #define SK_PKTARBCTL_RXTO2_OFF 0x0010 474 #define SK_PKTARBCTL_RXTO2_ON 0x0020 475 #define SK_PKTARBCTL_TXTO1_OFF 0x0040 476 #define SK_PKTARBCTL_TXTO1_ON 0x0080 477 #define SK_PKTARBCTL_TXTO2_OFF 0x0100 478 #define SK_PKTARBCTL_TXTO2_ON 0x0200 479 #define SK_PKTARBCTL_CLR_IRQ_RXTO1 0x0400 480 #define SK_PKTARBCTL_CLR_IRQ_RXTO2 0x0800 481 #define SK_PKTARBCTL_CLR_IRQ_TXTO1 0x1000 482 #define SK_PKTARBCTL_CLR_IRQ_TXTO2 0x2000 483 484 #define SK_MINIT_XMAC_B2 54 485 #define SK_MINIT_XMAC_C1 63 486 487 #define SK_MACARBCTL_RESET 0x0001 488 #define SK_MACARBCTL_UNRESET 0x0002 489 #define SK_MACARBCTL_FASTOE_OFF 0x0004 490 #define SK_MACARBCRL_FASTOE_ON 0x0008 491 492 #define SK_RCINIT_XMAC_B2 54 493 #define SK_RCINIT_XMAC_C1 0 494 495 #define SK_RECOVERYCTL_RX1_OFF 0x0001 496 #define SK_RECOVERYCTL_RX1_ON 0x0002 497 #define SK_RECOVERYCTL_RX2_OFF 0x0004 498 #define SK_RECOVERYCTL_RX2_ON 0x0008 499 #define SK_RECOVERYCTL_TX1_OFF 0x0010 500 #define SK_RECOVERYCTL_TX1_ON 0x0020 501 #define SK_RECOVERYCTL_TX2_OFF 0x0040 502 #define SK_RECOVERYCTL_TX2_ON 0x0080 503 504 #define SK_RECOVERY_XMAC_B2 \ 505 (SK_RECOVERYCTL_RX1_ON|SK_RECOVERYCTL_RX2_ON| \ 506 SK_RECOVERYCTL_TX1_ON|SK_RECOVERYCTL_TX2_ON) 507 508 #define SK_RECOVERY_XMAC_C1 \ 509 (SK_RECOVERYCTL_RX1_OFF|SK_RECOVERYCTL_RX2_OFF| \ 510 SK_RECOVERYCTL_TX1_OFF|SK_RECOVERYCTL_TX2_OFF) 511 512 /* Block 4 -- TX Arbiter MAC 1 */ 513 #define SK_TXAR1_TIMERINIT 0x0200 514 #define SK_TXAR1_TIMERVAL 0x0204 515 #define SK_TXAR1_LIMITINIT 0x0208 516 #define SK_TXAR1_LIMITCNT 0x020C 517 #define SK_TXAR1_COUNTERCTL 0x0210 518 #define SK_TXAR1_COUNTERTST 0x0212 519 #define SK_TXAR1_COUNTERSTS 0x0212 520 521 /* Block 5 -- TX Arbiter MAC 2 */ 522 #define SK_TXAR2_TIMERINIT 0x0280 523 #define SK_TXAR2_TIMERVAL 0x0284 524 #define SK_TXAR2_LIMITINIT 0x0288 525 #define SK_TXAR2_LIMITCNT 0x028C 526 #define SK_TXAR2_COUNTERCTL 0x0290 527 #define SK_TXAR2_COUNTERTST 0x0291 528 #define SK_TXAR2_COUNTERSTS 0x0292 529 530 #define SK_TXARCTL_OFF 0x01 531 #define SK_TXARCTL_ON 0x02 532 #define SK_TXARCTL_RATECTL_OFF 0x04 533 #define SK_TXARCTL_RATECTL_ON 0x08 534 #define SK_TXARCTL_ALLOC_OFF 0x10 535 #define SK_TXARCTL_ALLOC_ON 0x20 536 #define SK_TXARCTL_FSYNC_OFF 0x40 537 #define SK_TXARCTL_FSYNC_ON 0x80 538 539 /* Block 6 -- External registers */ 540 #define SK_EXTREG_BASE 0x300 541 #define SK_EXTREG_END 0x37C 542 543 /* Block 7 -- PCI config registers */ 544 #define SK_PCI_BASE 0x0380 545 #define SK_PCI_END 0x03FC 546 547 /* Compute offset of mirrored PCI register */ 548 #define SK_PCI_REG(reg) ((reg) + SK_PCI_BASE) 549 550 /* Block 8 -- RX queue 1 */ 551 #define SK_RXQ1_BUFCNT 0x0400 552 #define SK_RXQ1_BUFCTL 0x0402 553 #define SK_RXQ1_NEXTDESC 0x0404 554 #define SK_RXQ1_RXBUF_LO 0x0408 555 #define SK_RXQ1_RXBUF_HI 0x040C 556 #define SK_RXQ1_RXSTAT 0x0410 557 #define SK_RXQ1_TIMESTAMP 0x0414 558 #define SK_RXQ1_CSUM1 0x0418 559 #define SK_RXQ1_CSUM2 0x041A 560 #define SK_RXQ1_CSUM1_START 0x041C 561 #define SK_RXQ1_CSUM2_START 0x041E 562 #define SK_RXQ1_CURADDR_LO 0x0420 563 #define SK_RXQ1_CURADDR_HI 0x0424 564 #define SK_RXQ1_CURCNT_LO 0x0428 565 #define SK_RXQ1_CURCNT_HI 0x042C 566 #define SK_RXQ1_CURBYTES 0x0430 567 #define SK_RXQ1_BMU_CSR 0x0434 568 #define SK_RXQ1_WATERMARK 0x0438 569 #define SK_RXQ1_FLAG 0x043A 570 #define SK_RXQ1_TEST1 0x043C 571 #define SK_RXQ1_TEST2 0x0440 572 #define SK_RXQ1_TEST3 0x0444 573 574 /* Block 9 -- RX queue 2 */ 575 #define SK_RXQ2_BUFCNT 0x0480 576 #define SK_RXQ2_BUFCTL 0x0482 577 #define SK_RXQ2_NEXTDESC 0x0484 578 #define SK_RXQ2_RXBUF_LO 0x0488 579 #define SK_RXQ2_RXBUF_HI 0x048C 580 #define SK_RXQ2_RXSTAT 0x0490 581 #define SK_RXQ2_TIMESTAMP 0x0494 582 #define SK_RXQ2_CSUM1 0x0498 583 #define SK_RXQ2_CSUM2 0x049A 584 #define SK_RXQ2_CSUM1_START 0x049C 585 #define SK_RXQ2_CSUM2_START 0x049E 586 #define SK_RXQ2_CURADDR_LO 0x04A0 587 #define SK_RXQ2_CURADDR_HI 0x04A4 588 #define SK_RXQ2_CURCNT_LO 0x04A8 589 #define SK_RXQ2_CURCNT_HI 0x04AC 590 #define SK_RXQ2_CURBYTES 0x04B0 591 #define SK_RXQ2_BMU_CSR 0x04B4 592 #define SK_RXQ2_WATERMARK 0x04B8 593 #define SK_RXQ2_FLAG 0x04BA 594 #define SK_RXQ2_TEST1 0x04BC 595 #define SK_RXQ2_TEST2 0x04C0 596 #define SK_RXQ2_TEST3 0x04C4 597 598 #define SK_RXBMU_CLR_IRQ_ERR 0x00000001 599 #define SK_RXBMU_CLR_IRQ_EOF 0x00000002 600 #define SK_RXBMU_CLR_IRQ_EOB 0x00000004 601 #define SK_RXBMU_CLR_IRQ_PAR 0x00000008 602 #define SK_RXBMU_RX_START 0x00000010 603 #define SK_RXBMU_RX_STOP 0x00000020 604 #define SK_RXBMU_POLL_OFF 0x00000040 605 #define SK_RXBMU_POLL_ON 0x00000080 606 #define SK_RXBMU_TRANSFER_SM_RESET 0x00000100 607 #define SK_RXBMU_TRANSFER_SM_UNRESET 0x00000200 608 #define SK_RXBMU_DESCWR_SM_RESET 0x00000400 609 #define SK_RXBMU_DESCWR_SM_UNRESET 0x00000800 610 #define SK_RXBMU_DESCRD_SM_RESET 0x00001000 611 #define SK_RXBMU_DESCRD_SM_UNRESET 0x00002000 612 #define SK_RXBMU_SUPERVISOR_SM_RESET 0x00004000 613 #define SK_RXBMU_SUPERVISOR_SM_UNRESET 0x00008000 614 #define SK_RXBMU_PFI_SM_RESET 0x00010000 615 #define SK_RXBMU_PFI_SM_UNRESET 0x00020000 616 #define SK_RXBMU_FIFO_RESET 0x00040000 617 #define SK_RXBMU_FIFO_UNRESET 0x00080000 618 #define SK_RXBMU_DESC_RESET 0x00100000 619 #define SK_RXBMU_DESC_UNRESET 0x00200000 620 #define SK_RXBMU_SUPERVISOR_IDLE 0x01000000 621 622 #define SK_RXBMU_ONLINE \ 623 (SK_RXBMU_TRANSFER_SM_UNRESET|SK_RXBMU_DESCWR_SM_UNRESET| \ 624 SK_RXBMU_DESCRD_SM_UNRESET|SK_RXBMU_SUPERVISOR_SM_UNRESET| \ 625 SK_RXBMU_PFI_SM_UNRESET|SK_RXBMU_FIFO_UNRESET| \ 626 SK_RXBMU_DESC_UNRESET) 627 628 #define SK_RXBMU_OFFLINE \ 629 (SK_RXBMU_TRANSFER_SM_RESET|SK_RXBMU_DESCWR_SM_RESET| \ 630 SK_RXBMU_DESCRD_SM_RESET|SK_RXBMU_SUPERVISOR_SM_RESET| \ 631 SK_RXBMU_PFI_SM_RESET|SK_RXBMU_FIFO_RESET| \ 632 SK_RXBMU_DESC_RESET) 633 634 /* Block 12 -- TX sync queue 1 */ 635 #define SK_TXQS1_BUFCNT 0x0600 636 #define SK_TXQS1_BUFCTL 0x0602 637 #define SK_TXQS1_NEXTDESC 0x0604 638 #define SK_TXQS1_RXBUF_LO 0x0608 639 #define SK_TXQS1_RXBUF_HI 0x060C 640 #define SK_TXQS1_RXSTAT 0x0610 641 #define SK_TXQS1_CSUM_STARTVAL 0x0614 642 #define SK_TXQS1_CSUM_STARTPOS 0x0618 643 #define SK_TXQS1_CSUM_WRITEPOS 0x061A 644 #define SK_TXQS1_CURADDR_LO 0x0620 645 #define SK_TXQS1_CURADDR_HI 0x0624 646 #define SK_TXQS1_CURCNT_LO 0x0628 647 #define SK_TXQS1_CURCNT_HI 0x062C 648 #define SK_TXQS1_CURBYTES 0x0630 649 #define SK_TXQS1_BMU_CSR 0x0634 650 #define SK_TXQS1_WATERMARK 0x0638 651 #define SK_TXQS1_FLAG 0x063A 652 #define SK_TXQS1_TEST1 0x063C 653 #define SK_TXQS1_TEST2 0x0640 654 #define SK_TXQS1_TEST3 0x0644 655 656 /* Block 13 -- TX async queue 1 */ 657 #define SK_TXQA1_BUFCNT 0x0680 658 #define SK_TXQA1_BUFCTL 0x0682 659 #define SK_TXQA1_NEXTDESC 0x0684 660 #define SK_TXQA1_RXBUF_LO 0x0688 661 #define SK_TXQA1_RXBUF_HI 0x068C 662 #define SK_TXQA1_RXSTAT 0x0690 663 #define SK_TXQA1_CSUM_STARTVAL 0x0694 664 #define SK_TXQA1_CSUM_STARTPOS 0x0698 665 #define SK_TXQA1_CSUM_WRITEPOS 0x069A 666 #define SK_TXQA1_CURADDR_LO 0x06A0 667 #define SK_TXQA1_CURADDR_HI 0x06A4 668 #define SK_TXQA1_CURCNT_LO 0x06A8 669 #define SK_TXQA1_CURCNT_HI 0x06AC 670 #define SK_TXQA1_CURBYTES 0x06B0 671 #define SK_TXQA1_BMU_CSR 0x06B4 672 #define SK_TXQA1_WATERMARK 0x06B8 673 #define SK_TXQA1_FLAG 0x06BA 674 #define SK_TXQA1_TEST1 0x06BC 675 #define SK_TXQA1_TEST2 0x06C0 676 #define SK_TXQA1_TEST3 0x06C4 677 678 /* Block 14 -- TX sync queue 2 */ 679 #define SK_TXQS2_BUFCNT 0x0700 680 #define SK_TXQS2_BUFCTL 0x0702 681 #define SK_TXQS2_NEXTDESC 0x0704 682 #define SK_TXQS2_RXBUF_LO 0x0708 683 #define SK_TXQS2_RXBUF_HI 0x070C 684 #define SK_TXQS2_RXSTAT 0x0710 685 #define SK_TXQS2_CSUM_STARTVAL 0x0714 686 #define SK_TXQS2_CSUM_STARTPOS 0x0718 687 #define SK_TXQS2_CSUM_WRITEPOS 0x071A 688 #define SK_TXQS2_CURADDR_LO 0x0720 689 #define SK_TXQS2_CURADDR_HI 0x0724 690 #define SK_TXQS2_CURCNT_LO 0x0728 691 #define SK_TXQS2_CURCNT_HI 0x072C 692 #define SK_TXQS2_CURBYTES 0x0730 693 #define SK_TXQS2_BMU_CSR 0x0734 694 #define SK_TXQS2_WATERMARK 0x0738 695 #define SK_TXQS2_FLAG 0x073A 696 #define SK_TXQS2_TEST1 0x073C 697 #define SK_TXQS2_TEST2 0x0740 698 #define SK_TXQS2_TEST3 0x0744 699 700 /* Block 15 -- TX async queue 2 */ 701 #define SK_TXQA2_BUFCNT 0x0780 702 #define SK_TXQA2_BUFCTL 0x0782 703 #define SK_TXQA2_NEXTDESC 0x0784 704 #define SK_TXQA2_RXBUF_LO 0x0788 705 #define SK_TXQA2_RXBUF_HI 0x078C 706 #define SK_TXQA2_RXSTAT 0x0790 707 #define SK_TXQA2_CSUM_STARTVAL 0x0794 708 #define SK_TXQA2_CSUM_STARTPOS 0x0798 709 #define SK_TXQA2_CSUM_WRITEPOS 0x079A 710 #define SK_TXQA2_CURADDR_LO 0x07A0 711 #define SK_TXQA2_CURADDR_HI 0x07A4 712 #define SK_TXQA2_CURCNT_LO 0x07A8 713 #define SK_TXQA2_CURCNT_HI 0x07AC 714 #define SK_TXQA2_CURBYTES 0x07B0 715 #define SK_TXQA2_BMU_CSR 0x07B4 716 #define SK_TXQA2_WATERMARK 0x07B8 717 #define SK_TXQA2_FLAG 0x07BA 718 #define SK_TXQA2_TEST1 0x07BC 719 #define SK_TXQA2_TEST2 0x07C0 720 #define SK_TXQA2_TEST3 0x07C4 721 722 #define SK_TXBMU_CLR_IRQ_ERR 0x00000001 723 #define SK_TXBMU_CLR_IRQ_EOF 0x00000002 724 #define SK_TXBMU_CLR_IRQ_EOB 0x00000004 725 #define SK_TXBMU_TX_START 0x00000010 726 #define SK_TXBMU_TX_STOP 0x00000020 727 #define SK_TXBMU_POLL_OFF 0x00000040 728 #define SK_TXBMU_POLL_ON 0x00000080 729 #define SK_TXBMU_TRANSFER_SM_RESET 0x00000100 730 #define SK_TXBMU_TRANSFER_SM_UNRESET 0x00000200 731 #define SK_TXBMU_DESCWR_SM_RESET 0x00000400 732 #define SK_TXBMU_DESCWR_SM_UNRESET 0x00000800 733 #define SK_TXBMU_DESCRD_SM_RESET 0x00001000 734 #define SK_TXBMU_DESCRD_SM_UNRESET 0x00002000 735 #define SK_TXBMU_SUPERVISOR_SM_RESET 0x00004000 736 #define SK_TXBMU_SUPERVISOR_SM_UNRESET 0x00008000 737 #define SK_TXBMU_PFI_SM_RESET 0x00010000 738 #define SK_TXBMU_PFI_SM_UNRESET 0x00020000 739 #define SK_TXBMU_FIFO_RESET 0x00040000 740 #define SK_TXBMU_FIFO_UNRESET 0x00080000 741 #define SK_TXBMU_DESC_RESET 0x00100000 742 #define SK_TXBMU_DESC_UNRESET 0x00200000 743 #define SK_TXBMU_SUPERVISOR_IDLE 0x01000000 744 745 #define SK_TXBMU_ONLINE \ 746 (SK_TXBMU_TRANSFER_SM_UNRESET|SK_TXBMU_DESCWR_SM_UNRESET| \ 747 SK_TXBMU_DESCRD_SM_UNRESET|SK_TXBMU_SUPERVISOR_SM_UNRESET| \ 748 SK_TXBMU_PFI_SM_UNRESET|SK_TXBMU_FIFO_UNRESET| \ 749 SK_TXBMU_DESC_UNRESET|SK_TXBMU_POLL_ON) 750 751 #define SK_TXBMU_OFFLINE \ 752 (SK_TXBMU_TRANSFER_SM_RESET|SK_TXBMU_DESCWR_SM_RESET| \ 753 SK_TXBMU_DESCRD_SM_RESET|SK_TXBMU_SUPERVISOR_SM_RESET| \ 754 SK_TXBMU_PFI_SM_RESET|SK_TXBMU_FIFO_RESET| \ 755 SK_TXBMU_DESC_RESET|SK_TXBMU_POLL_OFF) 756 757 /* Block 16 -- Receive RAMbuffer 1 */ 758 #define SK_RXRB1_START 0x0800 759 #define SK_RXRB1_END 0x0804 760 #define SK_RXRB1_WR_PTR 0x0808 761 #define SK_RXRB1_RD_PTR 0x080C 762 #define SK_RXRB1_UTHR_PAUSE 0x0810 763 #define SK_RXRB1_LTHR_PAUSE 0x0814 764 #define SK_RXRB1_UTHR_HIPRIO 0x0818 765 #define SK_RXRB1_UTHR_LOPRIO 0x081C 766 #define SK_RXRB1_PKTCNT 0x0820 767 #define SK_RXRB1_LVL 0x0824 768 #define SK_RXRB1_CTLTST 0x0828 769 770 /* Block 17 -- Receive RAMbuffer 2 */ 771 #define SK_RXRB2_START 0x0880 772 #define SK_RXRB2_END 0x0884 773 #define SK_RXRB2_WR_PTR 0x0888 774 #define SK_RXRB2_RD_PTR 0x088C 775 #define SK_RXRB2_UTHR_PAUSE 0x0890 776 #define SK_RXRB2_LTHR_PAUSE 0x0894 777 #define SK_RXRB2_UTHR_HIPRIO 0x0898 778 #define SK_RXRB2_UTHR_LOPRIO 0x089C 779 #define SK_RXRB2_PKTCNT 0x08A0 780 #define SK_RXRB2_LVL 0x08A4 781 #define SK_RXRB2_CTLTST 0x08A8 782 783 /* Block 20 -- Sync. Transmit RAMbuffer 1 */ 784 #define SK_TXRBS1_START 0x0A00 785 #define SK_TXRBS1_END 0x0A04 786 #define SK_TXRBS1_WR_PTR 0x0A08 787 #define SK_TXRBS1_RD_PTR 0x0A0C 788 #define SK_TXRBS1_PKTCNT 0x0A20 789 #define SK_TXRBS1_LVL 0x0A24 790 #define SK_TXRBS1_CTLTST 0x0A28 791 792 /* Block 21 -- Async. Transmit RAMbuffer 1 */ 793 #define SK_TXRBA1_START 0x0A80 794 #define SK_TXRBA1_END 0x0A84 795 #define SK_TXRBA1_WR_PTR 0x0A88 796 #define SK_TXRBA1_RD_PTR 0x0A8C 797 #define SK_TXRBA1_PKTCNT 0x0AA0 798 #define SK_TXRBA1_LVL 0x0AA4 799 #define SK_TXRBA1_CTLTST 0x0AA8 800 801 /* Block 22 -- Sync. Transmit RAMbuffer 2 */ 802 #define SK_TXRBS2_START 0x0B00 803 #define SK_TXRBS2_END 0x0B04 804 #define SK_TXRBS2_WR_PTR 0x0B08 805 #define SK_TXRBS2_RD_PTR 0x0B0C 806 #define SK_TXRBS2_PKTCNT 0x0B20 807 #define SK_TXRBS2_LVL 0x0B24 808 #define SK_TXRBS2_CTLTST 0x0B28 809 810 /* Block 23 -- Async. Transmit RAMbuffer 2 */ 811 #define SK_TXRBA2_START 0x0B80 812 #define SK_TXRBA2_END 0x0B84 813 #define SK_TXRBA2_WR_PTR 0x0B88 814 #define SK_TXRBA2_RD_PTR 0x0B8C 815 #define SK_TXRBA2_PKTCNT 0x0BA0 816 #define SK_TXRBA2_LVL 0x0BA4 817 #define SK_TXRBA2_CTLTST 0x0BA8 818 819 #define SK_RBCTL_RESET 0x00000001 820 #define SK_RBCTL_UNRESET 0x00000002 821 #define SK_RBCTL_OFF 0x00000004 822 #define SK_RBCTL_ON 0x00000008 823 #define SK_RBCTL_STORENFWD_OFF 0x00000010 824 #define SK_RBCTL_STORENFWD_ON 0x00000020 825 826 /* Block 24 -- RX MAC FIFO 1 regisrers and LINK_SYNC counter */ 827 #define SK_RXF1_END 0x0C00 828 #define SK_RXF1_WPTR 0x0C04 829 #define SK_RXF1_RPTR 0x0C0C 830 #define SK_RXF1_PKTCNT 0x0C10 831 #define SK_RXF1_LVL 0x0C14 832 #define SK_RXF1_MACCTL 0x0C18 833 #define SK_RXF1_CTL 0x0C1C 834 #define SK_RXLED1_CNTINIT 0x0C20 835 #define SK_RXLED1_COUNTER 0x0C24 836 #define SK_RXLED1_CTL 0x0C28 837 #define SK_RXLED1_TST 0x0C29 838 #define SK_LINK_SYNC1_CINIT 0x0C30 839 #define SK_LINK_SYNC1_COUNTER 0x0C34 840 #define SK_LINK_SYNC1_CTL 0x0C38 841 #define SK_LINK_SYNC1_TST 0x0C39 842 #define SK_LINKLED1_CTL 0x0C3C 843 844 #define SK_FIFO_END 0x3F 845 846 /* Receive MAC FIFO 1 (Yukon Only) */ 847 #define SK_RXMF1_END 0x0C40 848 #define SK_RXMF1_THRESHOLD 0x0C44 849 #define SK_RXMF1_CTRL_TEST 0x0C48 850 #define SK_RXMF1_FLUSH_MASK 0x0C4C 851 #define SK_RXMF1_FLUSH_THRESHOLD 0x0C50 852 #define SK_RXMF1_WRITE_PTR 0x0C60 853 #define SK_RXMF1_WRITE_LEVEL 0x0C68 854 #define SK_RXMF1_READ_PTR 0x0C70 855 #define SK_RXMF1_READ_LEVEL 0x0C78 856 857 /* Receive MAC FIFO 1 Control/Test */ 858 #define SK_RFCTL_WR_PTR_TST_ON 0x00004000 /* Write pointer test on*/ 859 #define SK_RFCTL_WR_PTR_TST_OFF 0x00002000 /* Write pointer test off */ 860 #define SK_RFCTL_WR_PTR_STEP 0x00001000 /* Write pointer increment */ 861 #define SK_RFCTL_RD_PTR_TST_ON 0x00000400 /* Read pointer test on */ 862 #define SK_RFCTL_RD_PTR_TST_OFF 0x00000200 /* Read pointer test off */ 863 #define SK_RFCTL_RD_PTR_STEP 0x00000100 /* Read pointer increment */ 864 #define SK_RFCTL_FIFO_FLUSH_OFF 0x00000080 /* RX FIFO Flsuh mode off */ 865 #define SK_RFCTL_FIFO_FLUSH_ON 0x00000040 /* RX FIFO Flush mode on */ 866 #define SK_RFCTL_RX_FIFO_OVER 0x00000020 /* Clear IRQ RX FIFO Overrun */ 867 #define SK_RFCTL_FRAME_RX_DONE 0x00000010 /* Clear IRQ Frame RX Done */ 868 #define SK_RFCTL_OPERATION_ON 0x00000008 /* Operational mode on */ 869 #define SK_RFCTL_OPERATION_OFF 0x00000004 /* Operational mode off */ 870 #define SK_RFCTL_RESET_CLEAR 0x00000002 /* MAC FIFO Reset Clear */ 871 #define SK_RFCTL_RESET_SET 0x00000001 /* MAC FIFO Reset Set */ 872 873 #define SK_RFCTL_FIFO_THRESHOLD 0x0a /* flush threshold (default) */ 874 875 /* Block 25 -- RX MAC FIFO 2 regisrers and LINK_SYNC counter */ 876 #define SK_RXF2_END 0x0C80 877 #define SK_RXF2_WPTR 0x0C84 878 #define SK_RXF2_RPTR 0x0C8C 879 #define SK_RXF2_PKTCNT 0x0C90 880 #define SK_RXF2_LVL 0x0C94 881 #define SK_RXF2_MACCTL 0x0C98 882 #define SK_RXF2_CTL 0x0C9C 883 #define SK_RXLED2_CNTINIT 0x0CA0 884 #define SK_RXLED2_COUNTER 0x0CA4 885 #define SK_RXLED2_CTL 0x0CA8 886 #define SK_RXLED2_TST 0x0CA9 887 #define SK_LINK_SYNC2_CINIT 0x0CB0 888 #define SK_LINK_SYNC2_COUNTER 0x0CB4 889 #define SK_LINK_SYNC2_CTL 0x0CB8 890 #define SK_LINK_SYNC2_TST 0x0CB9 891 #define SK_LINKLED2_CTL 0x0CBC 892 893 #define SK_RXMACCTL_CLR_IRQ_NOSTS 0x00000001 894 #define SK_RXMACCTL_CLR_IRQ_NOTSTAMP 0x00000002 895 #define SK_RXMACCTL_TSTAMP_OFF 0x00000004 896 #define SK_RXMACCTL_RSTAMP_ON 0x00000008 897 #define SK_RXMACCTL_FLUSH_OFF 0x00000010 898 #define SK_RXMACCTL_FLUSH_ON 0x00000020 899 #define SK_RXMACCTL_PAUSE_OFF 0x00000040 900 #define SK_RXMACCTL_PAUSE_ON 0x00000080 901 #define SK_RXMACCTL_AFULL_OFF 0x00000100 902 #define SK_RXMACCTL_AFULL_ON 0x00000200 903 #define SK_RXMACCTL_VALIDTIME_PATCH_OFF 0x00000400 904 #define SK_RXMACCTL_VALIDTIME_PATCH_ON 0x00000800 905 #define SK_RXMACCTL_RXRDY_PATCH_OFF 0x00001000 906 #define SK_RXMACCTL_RXRDY_PATCH_ON 0x00002000 907 #define SK_RXMACCTL_STS_TIMEO 0x00FF0000 908 #define SK_RXMACCTL_TSTAMP_TIMEO 0xFF000000 909 910 #define SK_RXLEDCTL_ENABLE 0x0001 911 #define SK_RXLEDCTL_COUNTER_STOP 0x0002 912 #define SK_RXLEDCTL_COUNTER_START 0x0004 913 914 #define SK_LINKLED_OFF 0x0001 915 #define SK_LINKLED_ON 0x0002 916 #define SK_LINKLED_LINKSYNC_OFF 0x0004 917 #define SK_LINKLED_LINKSYNC_ON 0x0008 918 #define SK_LINKLED_BLINK_OFF 0x0010 919 #define SK_LINKLED_BLINK_ON 0x0020 920 921 /* Block 26 -- TX MAC FIFO 1 regisrers */ 922 #define SK_TXF1_END 0x0D00 923 #define SK_TXF1_WPTR 0x0D04 924 #define SK_TXF1_RPTR 0x0D0C 925 #define SK_TXF1_PKTCNT 0x0D10 926 #define SK_TXF1_LVL 0x0D14 927 #define SK_TXF1_MACCTL 0x0D18 928 #define SK_TXF1_CTL 0x0D1C 929 #define SK_TXLED1_CNTINIT 0x0D20 930 #define SK_TXLED1_COUNTER 0x0D24 931 #define SK_TXLED1_CTL 0x0D28 932 #define SK_TXLED1_TST 0x0D29 933 934 /* Transmit MAC FIFO 1 (Yukon Only) */ 935 #define SK_TXMF1_END 0x0D40 936 #define SK_TXMF1_THRESHOLD 0x0D44 937 #define SK_TXMF1_CTRL_TEST 0x0D48 938 #define SK_TXMF1_WRITE_PTR 0x0D60 939 #define SK_TXMF1_WRITE_SHADOW 0x0D64 940 #define SK_TXMF1_WRITE_LEVEL 0x0D68 941 #define SK_TXMF1_READ_PTR 0x0D70 942 #define SK_TXMF1_RESTART_PTR 0x0D74 943 #define SK_TXMF1_READ_LEVEL 0x0D78 944 945 /* Transmit MAC FIFO Control/Test */ 946 #define SK_TFCTL_WR_PTR_TST_ON 0x00004000 /* Write pointer test on*/ 947 #define SK_TFCTL_WR_PTR_TST_OFF 0x00002000 /* Write pointer test off */ 948 #define SK_TFCTL_WR_PTR_STEP 0x00001000 /* Write pointer increment */ 949 #define SK_TFCTL_RD_PTR_TST_ON 0x00000400 /* Read pointer test on */ 950 #define SK_TFCTL_RD_PTR_TST_OFF 0x00000200 /* Read pointer test off */ 951 #define SK_TFCTL_RD_PTR_STEP 0x00000100 /* Read pointer increment */ 952 #define SK_TFCTL_TX_FIFO_UNDER 0x00000040 /* Clear IRQ TX FIFO Under */ 953 #define SK_TFCTL_FRAME_TX_DONE 0x00000020 /* Clear IRQ Frame TX Done */ 954 #define SK_TFCTL_IRQ_PARITY_ER 0x00000010 /* Clear IRQ Parity Error */ 955 #define SK_TFCTL_OPERATION_ON 0x00000008 /* Operational mode on */ 956 #define SK_TFCTL_OPERATION_OFF 0x00000004 /* Operational mode off */ 957 #define SK_TFCTL_RESET_CLEAR 0x00000002 /* MAC FIFO Reset Clear */ 958 #define SK_TFCTL_RESET_SET 0x00000001 /* MAC FIFO Reset Set */ 959 960 /* Block 27 -- TX MAC FIFO 2 regisrers */ 961 #define SK_TXF2_END 0x0D80 962 #define SK_TXF2_WPTR 0x0D84 963 #define SK_TXF2_RPTR 0x0D8C 964 #define SK_TXF2_PKTCNT 0x0D90 965 #define SK_TXF2_LVL 0x0D94 966 #define SK_TXF2_MACCTL 0x0D98 967 #define SK_TXF2_CTL 0x0D9C 968 #define SK_TXLED2_CNTINIT 0x0DA0 969 #define SK_TXLED2_COUNTER 0x0DA4 970 #define SK_TXLED2_CTL 0x0DA8 971 #define SK_TXLED2_TST 0x0DA9 972 973 #define SK_TXMACCTL_XMAC_RESET 0x00000001 974 #define SK_TXMACCTL_XMAC_UNRESET 0x00000002 975 #define SK_TXMACCTL_LOOP_OFF 0x00000004 976 #define SK_TXMACCTL_LOOP_ON 0x00000008 977 #define SK_TXMACCTL_FLUSH_OFF 0x00000010 978 #define SK_TXMACCTL_FLUSH_ON 0x00000020 979 #define SK_TXMACCTL_WAITEMPTY_OFF 0x00000040 980 #define SK_TXMACCTL_WAITEMPTY_ON 0x00000080 981 #define SK_TXMACCTL_AFULL_OFF 0x00000100 982 #define SK_TXMACCTL_AFULL_ON 0x00000200 983 #define SK_TXMACCTL_TXRDY_PATCH_OFF 0x00000400 984 #define SK_TXMACCTL_RXRDY_PATCH_ON 0x00000800 985 #define SK_TXMACCTL_PKT_RECOVERY_OFF 0x00001000 986 #define SK_TXMACCTL_PKT_RECOVERY_ON 0x00002000 987 #define SK_TXMACCTL_CLR_IRQ_PERR 0x00008000 988 #define SK_TXMACCTL_WAITAFTERFLUSH 0x00010000 989 990 #define SK_TXLEDCTL_ENABLE 0x0001 991 #define SK_TXLEDCTL_COUNTER_STOP 0x0002 992 #define SK_TXLEDCTL_COUNTER_START 0x0004 993 994 #define SK_FIFO_RESET 0x00000001 995 #define SK_FIFO_UNRESET 0x00000002 996 #define SK_FIFO_OFF 0x00000004 997 #define SK_FIFO_ON 0x00000008 998 999 /* Block 28 -- Descriptor Poll Timer */ 1000 #define SK_DPT_INIT 0x0e00 /* Initial value 24 bits */ 1001 #define SK_DPT_TIMER 0x0e04 /* Mul of 78.12MHz clk (24b) */ 1002 1003 #define SK_DPT_TIMER_MAX 0x00ffffffff /* 214.75ms at 78.125MHz */ 1004 1005 #define SK_DPT_TIMER_CTRL 0x0e08 /* Timer Control 16 bits */ 1006 #define SK_DPT_TCTL_STOP 0x0001 /* Stop Timer */ 1007 #define SK_DPT_TCTL_START 0x0002 /* Start Timer */ 1008 1009 #define SK_DPT_TIMER_TEST 0x0e0a /* Timer Test 16 bits */ 1010 #define SK_DPT_TTEST_STEP 0x0001 /* Timer Decrement */ 1011 #define SK_DPT_TTEST_OFF 0x0002 /* Test Mode Off */ 1012 #define SK_DPT_TTEST_ON 0x0004 /* Test Mode On */ 1013 1014 #define SK_TSTAMP_COUNT 0x0e14 1015 #define SK_TSTAMP_CTL 0x0e18 1016 1017 #define SK_TSTAMP_IRQ_CLEAR 0x01 1018 #define SK_TSTAMP_STOP 0x02 1019 #define SK_TSTAMP_START 0x04 1020 1021 /* Block 29 -- Status BMU (Yukon-2 only) */ 1022 #define SK_STAT_BMU_CSR 0x0e80 1023 #define SK_STAT_BMU_LIDX 0x0e84 1024 #define SK_STAT_BMU_ADDRLO 0x0e88 1025 #define SK_STAT_BMU_ADDRHI 0x0e8c 1026 #define SK_STAT_BMU_TXA1_RIDX 0x0e90 1027 #define SK_STAT_BMU_TXS1_RIDX 0x0e92 1028 #define SK_STAT_BMU_TXA2_RIDX 0x0e94 1029 #define SK_STAT_BMU_TXS2_RIDX 0x0e96 1030 #define SK_STAT_BMU_TX_THRESH 0x0e98 1031 #define SK_STAT_BMU_PUTIDX 0x0e9c 1032 #define SK_STAT_BMU_FIFOWP 0x0ea0 1033 #define SK_STAT_BMU_FIFORP 0x0ea4 1034 #define SK_STAT_BMU_FIFORSP 0x0ea6 1035 #define SK_STAT_BMU_FIFOLV 0x0ea8 1036 #define SK_STAT_BMU_FIFOSLV 0x0eaa 1037 #define SK_STAT_BMU_FIFOWM 0x0eac 1038 #define SK_STAT_BMU_FIFOIWM 0x0ead 1039 1040 #define SK_STAT_BMU_RESET 0x00000001 1041 #define SK_STAT_BMU_UNRESET 0x00000002 1042 #define SK_STAT_BMU_OFF 0x00000004 1043 #define SK_STAT_BMU_ON 0x00000008 1044 #define SK_STAT_BMU_IRQ_CLEAR 0x00000010 1045 1046 /* Block 30 -- GMAC/GPHY Control Registers (Yukon Only)*/ 1047 #define SK_GMAC_CTRL 0x0f00 /* GMAC Control Register */ 1048 #define SK_GPHY_CTRL 0x0f04 /* GPHY Control Register */ 1049 #define SK_GMAC_ISR 0x0f08 /* GMAC Interrupt Source Register */ 1050 #define SK_GMAC_IMR 0x0f0c /* GMAC Interrupt Mask Register */ 1051 #define SK_LINK_CTRL 0x0f10 /* Link Control Register (LCR) */ 1052 #define SK_WOL_CTRL 0x0f20 /* Wake on LAN Control Register */ 1053 #define SK_MAC_ADDR_LOW 0x0f24 /* Mack Address Registers LOW */ 1054 #define SK_MAC_ADDR_HIGH 0x0f28 /* Mack Address Registers HIGH */ 1055 #define SK_PAT_READ_PTR 0x0f2c /* Pattern Read Pointer Register */ 1056 #define SK_PAT_LEN_REG0 0x0f30 /* Pattern Length Register 0 */ 1057 #define SK_PAT_LEN0 0x0f30 /* Pattern Length 0 */ 1058 #define SK_PAT_LEN1 0x0f31 /* Pattern Length 1 */ 1059 #define SK_PAT_LEN2 0x0f32 /* Pattern Length 2 */ 1060 #define SK_PAT_LEN3 0x0f33 /* Pattern Length 3 */ 1061 #define SK_PAT_LEN_REG1 0x0f34 /* Pattern Length Register 1 */ 1062 #define SK_PAT_LEN4 0x0f34 /* Pattern Length 4 */ 1063 #define SK_PAT_LEN5 0x0f35 /* Pattern Length 5 */ 1064 #define SK_PAT_LEN6 0x0f36 /* Pattern Length 6 */ 1065 #define SK_PAT_LEN7 0x0f37 /* Pattern Length 7 */ 1066 #define SK_PAT_CTR_REG0 0x0f38 /* Pattern Counter Register 0 */ 1067 #define SK_PAT_CTR0 0x0f38 /* Pattern Counter 0 */ 1068 #define SK_PAT_CTR1 0x0f39 /* Pattern Counter 1 */ 1069 #define SK_PAT_CTR2 0x0f3a /* Pattern Counter 2 */ 1070 #define SK_PAT_CTR3 0x0f3b /* Pattern Counter 3 */ 1071 #define SK_PAT_CTR_REG1 0x0f3c /* Pattern Counter Register 1 */ 1072 #define SK_PAT_CTR4 0x0f3c /* Pattern Counter 4 */ 1073 #define SK_PAT_CTR5 0x0f3d /* Pattern Counter 5 */ 1074 #define SK_PAT_CTR6 0x0f3e /* Pattern Counter 6 */ 1075 #define SK_PAT_CTR7 0x0f3f /* Pattern Counter 7 */ 1076 1077 #define SK_GMAC_LOOP_ON 0x00000020 /* Loopback mode for testing */ 1078 #define SK_GMAC_LOOP_OFF 0x00000010 /* purposes */ 1079 #define SK_GMAC_PAUSE_ON 0x00000008 /* enable forward of pause */ 1080 #define SK_GMAC_PAUSE_OFF 0x00000004 /* signal to GMAC */ 1081 #define SK_GMAC_RESET_CLEAR 0x00000002 /* Clear GMAC Reset */ 1082 #define SK_GMAC_RESET_SET 0x00000001 /* Set GMAC Reset */ 1083 1084 #define SK_GPHY_SEL_BDT 0x10000000 /* Select Bidirectional xfer */ 1085 #define SK_GPHY_INT_POL_HI 0x08000000 /* IRQ Polarity Active */ 1086 #define SK_GPHY_75_OHM 0x04000000 /* Use 75 Ohm Termination */ 1087 #define SK_GPHY_DIS_FC 0x02000000 /* Disable Auto Fiber/Copper */ 1088 #define SK_GPHY_DIS_SLEEP 0x01000000 /* Disable Energy Detect */ 1089 #define SK_GPHY_HWCFG_M_3 0x00800000 /* HWCFG_MODE[3] */ 1090 #define SK_GPHY_HWCFG_M_2 0x00400000 /* HWCFG_MODE[2] */ 1091 #define SK_GPHY_HWCFG_M_1 0x00200000 /* HWCFG_MODE[1] */ 1092 #define SK_GPHY_HWCFG_M_0 0x00100000 /* HWCFG_MODE[0] */ 1093 #define SK_GPHY_ANEG_0 0x00080000 /* ANEG[0] */ 1094 #define SK_GPHY_ENA_XC 0x00040000 /* Enable MDI Crossover */ 1095 #define SK_GPHY_DIS_125 0x00020000 /* Disable 125MHz Clock */ 1096 #define SK_GPHY_ANEG_3 0x00010000 /* ANEG[3] */ 1097 #define SK_GPHY_ANEG_2 0x00008000 /* ANEG[2] */ 1098 #define SK_GPHY_ANEG_1 0x00004000 /* ANEG[1] */ 1099 #define SK_GPHY_ENA_PAUSE 0x00002000 /* Enable Pause */ 1100 #define SK_GPHY_PHYADDR_4 0x00001000 /* Bit 4 of Phy Addr */ 1101 #define SK_GPHY_PHYADDR_3 0x00000800 /* Bit 3 of Phy Addr */ 1102 #define SK_GPHY_PHYADDR_2 0x00000400 /* Bit 2 of Phy Addr */ 1103 #define SK_GPHY_PHYADDR_1 0x00000200 /* Bit 1 of Phy Addr */ 1104 #define SK_GPHY_PHYADDR_0 0x00000100 /* Bit 0 of Phy Addr */ 1105 #define SK_GPHY_RESET_CLEAR 0x00000002 /* Clear GPHY Reset */ 1106 #define SK_GPHY_RESET_SET 0x00000001 /* Set GPHY Reset */ 1107 1108 #define SK_GPHY_COPPER (SK_GPHY_HWCFG_M_0 | SK_GPHY_HWCFG_M_1 | \ 1109 SK_GPHY_HWCFG_M_2 | SK_GPHY_HWCFG_M_3 ) 1110 #define SK_GPHY_FIBER (SK_GPHY_HWCFG_M_0 | SK_GPHY_HWCFG_M_1 | \ 1111 SK_GPHY_HWCFG_M_2 ) 1112 #define SK_GPHY_ANEG_ALL (SK_GPHY_ANEG_0 | SK_GPHY_ANEG_1 | \ 1113 SK_GPHY_ANEG_2 | SK_GPHY_ANEG_3 ) 1114 1115 #define SK_GMAC_INT_TX_OFLOW 0x20 /* Transmit Counter Overflow */ 1116 #define SK_GMAC_INT_RX_OFLOW 0x10 /* Receiver Overflow */ 1117 #define SK_GMAC_INT_TX_UNDER 0x08 /* Transmit FIFO Underrun */ 1118 #define SK_GMAC_INT_TX_DONE 0x04 /* Transmit Complete */ 1119 #define SK_GMAC_INT_RX_OVER 0x02 /* Receive FIFO Overrun */ 1120 #define SK_GMAC_INT_RX_DONE 0x01 /* Receive Complete */ 1121 1122 #define SK_LINK_RESET_CLEAR 0x0002 /* Link Reset Clear */ 1123 #define SK_LINK_RESET_SET 0x0001 /* Link Reset Set */ 1124 1125 /* Block 31 -- reserved */ 1126 1127 /* Block 32-33 -- Pattern Ram */ 1128 #define SK_WOL_PRAM 0x1000 1129 1130 /* Block 0x22 - 0x3f -- reserved */ 1131 1132 /* Block 0x40 to 0x4F -- XMAC 1 registers */ 1133 #define SK_XMAC1_BASE 0x2000 1134 1135 /* Block 0x50 to 0x5F -- MARV 1 registers */ 1136 #define SK_MARV1_BASE 0x2800 1137 1138 /* Block 0x60 to 0x6F -- XMAC 2 registers */ 1139 #define SK_XMAC2_BASE 0x3000 1140 1141 /* Block 0x70 to 0x7F -- MARV 2 registers */ 1142 #define SK_MARV2_BASE 0x3800 1143 1144 /* Compute relative offset of an XMAC register in the XMAC window(s). */ 1145 #define SK_XMAC_REG(sc, reg) (((reg) * 2) + SK_XMAC1_BASE + \ 1146 (((sc)->sk_port) * (SK_XMAC2_BASE - SK_XMAC1_BASE))) 1147 1148 #if 0 1149 #define SK_XM_READ_4(sc, reg) \ 1150 ((sk_win_read_2(sc->sk_softc, \ 1151 SK_XMAC_REG(sc, reg)) & 0xFFFF) | \ 1152 ((sk_win_read_2(sc->sk_softc, \ 1153 SK_XMAC_REG(sc, reg + 2)) & 0xFFFF) << 16)) 1154 1155 #define SK_XM_WRITE_4(sc, reg, val) \ 1156 sk_win_write_2(sc->sk_softc, SK_XMAC_REG(sc, reg), \ 1157 ((val) & 0xFFFF)); \ 1158 sk_win_write_2(sc->sk_softc, SK_XMAC_REG(sc, reg + 2), \ 1159 ((val) >> 16) & 0xFFFF) 1160 #else 1161 #define SK_XM_READ_4(sc, reg) \ 1162 sk_win_read_4(sc->sk_softc, SK_XMAC_REG(sc, reg)) 1163 1164 #define SK_XM_WRITE_4(sc, reg, val) \ 1165 sk_win_write_4(sc->sk_softc, SK_XMAC_REG(sc, reg), (val)) 1166 #endif 1167 1168 #define SK_XM_READ_2(sc, reg) \ 1169 sk_win_read_2(sc->sk_softc, SK_XMAC_REG(sc, reg)) 1170 1171 #define SK_XM_WRITE_2(sc, reg, val) \ 1172 sk_win_write_2(sc->sk_softc, SK_XMAC_REG(sc, reg), val) 1173 1174 #define SK_XM_SETBIT_4(sc, reg, x) \ 1175 SK_XM_WRITE_4(sc, reg, (SK_XM_READ_4(sc, reg)) | (x)) 1176 1177 #define SK_XM_CLRBIT_4(sc, reg, x) \ 1178 SK_XM_WRITE_4(sc, reg, (SK_XM_READ_4(sc, reg)) & ~(x)) 1179 1180 #define SK_XM_SETBIT_2(sc, reg, x) \ 1181 SK_XM_WRITE_2(sc, reg, (SK_XM_READ_2(sc, reg)) | (x)) 1182 1183 #define SK_XM_CLRBIT_2(sc, reg, x) \ 1184 SK_XM_WRITE_2(sc, reg, (SK_XM_READ_2(sc, reg)) & ~(x)) 1185 1186 /* Compute relative offset of an MARV register in the MARV window(s). */ 1187 #define SK_YU_REG(sc, reg) \ 1188 ((reg) + SK_MARV1_BASE + \ 1189 (((sc)->sk_port) * (SK_MARV2_BASE - SK_MARV1_BASE))) 1190 1191 #define SK_YU_READ_4(sc, reg) \ 1192 sk_win_read_4((sc)->sk_softc, SK_YU_REG((sc), (reg))) 1193 1194 #define SK_YU_READ_2(sc, reg) \ 1195 sk_win_read_2((sc)->sk_softc, SK_YU_REG((sc), (reg))) 1196 1197 #define SK_YU_WRITE_4(sc, reg, val) \ 1198 sk_win_write_4((sc)->sk_softc, SK_YU_REG((sc), (reg)), (val)) 1199 1200 #define SK_YU_WRITE_2(sc, reg, val) \ 1201 sk_win_write_2((sc)->sk_softc, SK_YU_REG((sc), (reg)), (val)) 1202 1203 #define SK_YU_SETBIT_4(sc, reg, x) \ 1204 SK_YU_WRITE_4(sc, reg, (SK_YU_READ_4(sc, reg)) | (x)) 1205 1206 #define SK_YU_CLRBIT_4(sc, reg, x) \ 1207 SK_YU_WRITE_4(sc, reg, (SK_YU_READ_4(sc, reg)) & ~(x)) 1208 1209 #define SK_YU_SETBIT_2(sc, reg, x) \ 1210 SK_YU_WRITE_2(sc, reg, (SK_YU_READ_2(sc, reg)) | (x)) 1211 1212 #define SK_YU_CLRBIT_2(sc, reg, x) \ 1213 SK_YU_WRITE_2(sc, reg, (SK_YU_READ_2(sc, reg)) & ~(x)) 1214 1215 /* 1216 * The default FIFO threshold on the XMAC II is 4 bytes. On 1217 * dual port NICs, this often leads to transmit underruns, so we 1218 * bump the threshold a little. 1219 */ 1220 #define SK_XM_TX_FIFOTHRESH 512 1221 1222 #define SK_PCI_VENDOR_ID 0x0000 1223 #define SK_PCI_DEVICE_ID 0x0002 1224 #define SK_PCI_COMMAND 0x0004 1225 #define SK_PCI_STATUS 0x0006 1226 #define SK_PCI_REVID 0x0008 1227 #define SK_PCI_CLASSCODE 0x0009 1228 #define SK_PCI_CACHELEN 0x000C 1229 #define SK_PCI_LATENCY_TIMER 0x000D 1230 #define SK_PCI_HEADER_TYPE 0x000E 1231 #define SK_PCI_LOMEM 0x0010 1232 #define SK_PCI_LOIO 0x0014 1233 #define SK_PCI_SUBVEN_ID 0x002C 1234 #define SK_PCI_SYBSYS_ID 0x002E 1235 #define SK_PCI_BIOSROM 0x0030 1236 #define SK_PCI_INTLINE 0x003C 1237 #define SK_PCI_INTPIN 0x003D 1238 #define SK_PCI_MINGNT 0x003E 1239 #define SK_PCI_MINLAT 0x003F 1240 1241 /* device specific PCI registers */ 1242 #define SK_PCI_OURREG1 0x0040 1243 #define SK_PCI_OURREG2 0x0044 1244 #define SK_PCI_CAPID 0x0048 /* 8 bits */ 1245 #define SK_PCI_NEXTPTR 0x0049 /* 8 bits */ 1246 #define SK_PCI_PWRMGMTCAP 0x004A /* 16 bits */ 1247 #define SK_PCI_PWRMGMTCTRL 0x004C /* 16 bits */ 1248 #define SK_PCI_PME_EVENT 0x004F 1249 1250 #define SK_PSTATE_MASK 0x0003 1251 #define SK_PSTATE_D0 0x0000 1252 #define SK_PSTATE_D1 0x0001 1253 #define SK_PSTATE_D2 0x0002 1254 #define SK_PSTATE_D3 0x0003 1255 #define SK_PME_EN 0x0010 1256 #define SK_PME_STATUS 0x8000 1257 1258 #define CSR_WRITE_4(sc, reg, val) \ 1259 bus_space_write_4((sc)->sk_btag, (sc)->sk_bhandle, (reg), (val)) 1260 #define CSR_WRITE_2(sc, reg, val) \ 1261 bus_space_write_2((sc)->sk_btag, (sc)->sk_bhandle, (reg), (val)) 1262 #define CSR_WRITE_1(sc, reg, val) \ 1263 bus_space_write_1((sc)->sk_btag, (sc)->sk_bhandle, (reg), (val)) 1264 1265 #define CSR_READ_4(sc, reg) \ 1266 bus_space_read_4((sc)->sk_btag, (sc)->sk_bhandle, (reg)) 1267 #define CSR_READ_2(sc, reg) \ 1268 bus_space_read_2((sc)->sk_btag, (sc)->sk_bhandle, (reg)) 1269 #define CSR_READ_1(sc, reg) \ 1270 bus_space_read_1((sc)->sk_btag, (sc)->sk_bhandle, (reg)) 1271 1272 #define SK_ADDR_LO(x) ((uint64_t) (x) & 0xffffffff) 1273 #define SK_ADDR_HI(x) ((uint64_t) (x) >> 32) 1274 1275 #define SK_RING_ALIGN 64 1276 1277 /* RX queue descriptor data structure */ 1278 struct sk_rx_desc { 1279 uint32_t sk_ctl; 1280 uint32_t sk_next; 1281 uint32_t sk_data_lo; 1282 uint32_t sk_data_hi; 1283 uint32_t sk_xmac_rxstat; 1284 uint32_t sk_timestamp; 1285 uint16_t sk_csum2; 1286 uint16_t sk_csum1; 1287 uint16_t sk_csum2_start; 1288 uint16_t sk_csum1_start; 1289 }; 1290 1291 #define SK_OPCODE_DEFAULT 0x00550000 1292 #define SK_OPCODE_CSUM 0x00560000 1293 1294 #define SK_RXCTL_LEN 0x0000FFFF 1295 #define SK_RXCTL_OPCODE 0x00FF0000 1296 #define SK_RXCTL_TSTAMP_VALID 0x01000000 1297 #define SK_RXCTL_STATUS_VALID 0x02000000 1298 #define SK_RXCTL_DEV0 0x04000000 1299 #define SK_RXCTL_EOF_INTR 0x08000000 1300 #define SK_RXCTL_EOB_INTR 0x10000000 1301 #define SK_RXCTL_LASTFRAG 0x20000000 1302 #define SK_RXCTL_FIRSTFRAG 0x40000000 1303 #define SK_RXCTL_OWN 0x80000000 1304 1305 #define SK_RXSTAT \ 1306 (SK_OPCODE_DEFAULT|SK_RXCTL_EOF_INTR|SK_RXCTL_LASTFRAG| \ 1307 SK_RXCTL_FIRSTFRAG|SK_RXCTL_OWN) 1308 1309 struct sk_tx_desc { 1310 uint32_t sk_ctl; 1311 uint32_t sk_next; 1312 uint32_t sk_data_lo; 1313 uint32_t sk_data_hi; 1314 uint32_t sk_xmac_txstat; 1315 uint16_t sk_rsvd0; 1316 uint16_t sk_csum_startval; 1317 uint16_t sk_csum_startpos; 1318 uint16_t sk_csum_writepos; 1319 uint32_t sk_rsvd1; 1320 }; 1321 1322 #define SK_TXCTL_LEN 0x0000FFFF 1323 #define SK_TXCTL_OPCODE 0x00FF0000 1324 #define SK_TXCTL_SW 0x01000000 1325 #define SK_TXCTL_NOCRC 0x02000000 1326 #define SK_TXCTL_STORENFWD 0x04000000 1327 #define SK_TXCTL_EOF_INTR 0x08000000 1328 #define SK_TXCTL_EOB_INTR 0x10000000 1329 #define SK_TXCTL_LASTFRAG 0x20000000 1330 #define SK_TXCTL_FIRSTFRAG 0x40000000 1331 #define SK_TXCTL_OWN 0x80000000 1332 1333 #define SK_TXSTAT \ 1334 (SK_OPCODE_DEFAULT|SK_TXCTL_EOF_INTR|SK_TXCTL_LASTFRAG|SK_TXCTL_OWN) 1335 1336 #define SK_RXBYTES(x) ((x) & 0x0000FFFF); 1337 #define SK_TXBYTES SK_RXBYTES 1338 1339 #define SK_TX_RING_CNT 512 1340 #define SK_RX_RING_CNT 256 1341 1342 /* 1343 * Jumbo buffer stuff. Note that we must allocate more jumbo 1344 * buffers than there are descriptors in the receive ring. This 1345 * is because we don't know how long it will take for a packet 1346 * to be released after we hand it off to the upper protocol 1347 * layers. To be safe, we allocate 1.5 times the number of 1348 * receive descriptors. 1349 */ 1350 #define SK_JUMBO_FRAMELEN 9018 1351 #define SK_JUMBO_MTU (SK_JUMBO_FRAMELEN - ETHER_HDR_LEN - ETHER_CRC_LEN) 1352 #define SK_MIN_FRAMELEN (ETHER_MIN_LEN - ETHER_CRC_LEN) 1353 #define SK_JSLOTS ((SK_RX_RING_CNT / 2) * 3) 1354 1355 #define SK_JRAWLEN (SK_JUMBO_FRAMELEN + ETHER_ALIGN) 1356 #define SK_JLEN SK_JRAWLEN 1357 #define SK_MCLBYTES SK_JLEN 1358 #define SK_JPAGESZ PAGE_SIZE 1359 #define SK_RESID (SK_JPAGESZ - (SK_JLEN * SK_JSLOTS) % SK_JPAGESZ) 1360 #define SK_JMEM ((SK_JLEN * SK_JSLOTS) + SK_RESID) 1361 1362 #define SK_MAXUNIT 256 1363 #define SK_TIMEOUT 1000 1364 1365 #define SUBDEVICEID_LINKSYS_EG1032_REV2 0x0015 1366