1 /* $OpenBSD: if_skreg.h,v 1.10 2003/08/12 05:23:06 nate Exp $ */ 2 3 /* 4 * Copyright (c) 1997, 1998, 1999, 2000 5 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * $FreeBSD: src/sys/pci/if_skreg.h,v 1.8.2.1 2000/04/27 14:48:07 wpaul Exp $ 35 * $DragonFly: src/sys/dev/netif/sk/if_skreg.h,v 1.4 2003/11/12 22:43:07 dillon Exp $ 36 */ 37 38 /* 39 * Copyright (c) 2003 Nathan L. Binkert <binkertn@umich.edu> 40 * 41 * Permission to use, copy, modify, and distribute this software for any 42 * purpose with or without fee is hereby granted, provided that the above 43 * copyright notice and this permission notice appear in all copies. 44 * 45 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 46 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 47 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 48 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 49 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 50 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 51 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 52 */ 53 54 /* Values to keep the different chip revisions apart */ 55 #define SK_GENESIS 0 56 #define SK_YUKON 1 57 58 /* 59 * SysKonnect PCI vendor ID 60 */ 61 #define VENDORID_SK 0x1148 62 63 /* 64 * Marvell PCI vendor ID 65 */ 66 #define VENDORID_MARVELL 0x11AB 67 68 /* 69 * SK-NET gigabit ethernet device IDs 70 */ 71 #define DEVICEID_SK_V1 0x4300 72 #define DEVICEID_SK_V2 0x4320 73 74 /* 75 * 3Com PCI vendor ID 76 */ 77 #define VENDORID_3COM 0x10b7 78 79 /* 80 * 3Com gigabit ethernet device ID 81 */ 82 #define DEVICEID_3COM_3C940 0x1700 83 84 /* 85 * GEnesis registers. The GEnesis chip has a 256-byte I/O window 86 * but internally it has a 16K register space. This 16K space is 87 * divided into 128-byte blocks. The first 128 bytes of the I/O 88 * window represent the first block, which is permanently mapped 89 * at the start of the window. The other 127 blocks can be mapped 90 * to the second 128 bytes of the I/O window by setting the desired 91 * block value in the RAP register in block 0. Not all of the 127 92 * blocks are actually used. Most registers are 32 bits wide, but 93 * there are a few 16-bit and 8-bit ones as well. 94 */ 95 96 97 /* Start of remappable register window. */ 98 #define SK_WIN_BASE 0x0080 99 100 /* Size of a window */ 101 #define SK_WIN_LEN 0x80 102 103 #define SK_WIN_MASK 0x3F80 104 #define SK_REG_MASK 0x7F 105 106 /* Compute the window of a given register (for the RAP register) */ 107 #define SK_WIN(reg) (((reg) & SK_WIN_MASK) / SK_WIN_LEN) 108 109 /* Compute the relative offset of a register within the window */ 110 #define SK_REG(reg) ((reg) & SK_REG_MASK) 111 112 #define SK_PORT_A 0 113 #define SK_PORT_B 1 114 115 /* 116 * Compute offset of port-specific register. Since there are two 117 * ports, there are two of some GEnesis modules (e.g. two sets of 118 * DMA queues, two sets of FIFO control registers, etc...). Normally, 119 * the block for port 0 is at offset 0x0 and the block for port 1 is 120 * at offset 0x80 (i.e. the next page over). However for the transmit 121 * BMUs and RAMbuffers, there are two blocks for each port: one for 122 * the sync transmit queue and one for the async queue (which we don't 123 * use). However instead of ordering them like this: 124 * TX sync 1 / TX sync 2 / TX async 1 / TX async 2 125 * SysKonnect has instead ordered them like this: 126 * TX sync 1 / TX async 1 / TX sync 2 / TX async 2 127 * This means that when referencing the TX BMU and RAMbuffer registers, 128 * we have to double the block offset (0x80 * 2) in order to reach the 129 * second queue. This prevents us from using the same formula 130 * (sk_port * 0x80) to compute the offsets for all of the port-specific 131 * blocks: we need an extra offset for the BMU and RAMbuffer registers. 132 * The simplest thing is to provide an extra argument to these macros: 133 * the 'skip' parameter. The 'skip' value is the number of extra pages 134 * for skip when computing the port0/port1 offsets. For most registers, 135 * the skip value is 0; for the BMU and RAMbuffer registers, it's 1. 136 */ 137 #define SK_IF_READ_4(sc_if, skip, reg) \ 138 sk_win_read_4(sc_if->sk_softc, reg + \ 139 ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN)) 140 #define SK_IF_READ_2(sc_if, skip, reg) \ 141 sk_win_read_2(sc_if->sk_softc, reg + \ 142 ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN)) 143 #define SK_IF_READ_1(sc_if, skip, reg) \ 144 sk_win_read_1(sc_if->sk_softc, reg + \ 145 ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN)) 146 147 #define SK_IF_WRITE_4(sc_if, skip, reg, val) \ 148 sk_win_write_4(sc_if->sk_softc, \ 149 reg + ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN), val) 150 #define SK_IF_WRITE_2(sc_if, skip, reg, val) \ 151 sk_win_write_2(sc_if->sk_softc, \ 152 reg + ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN), val) 153 #define SK_IF_WRITE_1(sc_if, skip, reg, val) \ 154 sk_win_write_1(sc_if->sk_softc, \ 155 reg + ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN), val) 156 157 /* Block 0 registers, permanently mapped at iobase. */ 158 #define SK_RAP 0x0000 159 #define SK_CSR 0x0004 160 #define SK_LED 0x0006 161 #define SK_ISR 0x0008 /* interrupt source */ 162 #define SK_IMR 0x000C /* interrupt mask */ 163 #define SK_IESR 0x0010 /* interrupt hardware error source */ 164 #define SK_IEMR 0x0014 /* interrupt hardware error mask */ 165 #define SK_ISSR 0x0018 /* special interrupt source */ 166 #define SK_XM_IMR0 0x0020 167 #define SK_XM_ISR0 0x0028 168 #define SK_XM_PHYADDR0 0x0030 169 #define SK_XM_PHYDATA0 0x0034 170 #define SK_XM_IMR1 0x0040 171 #define SK_XM_ISR1 0x0048 172 #define SK_XM_PHYADDR1 0x0050 173 #define SK_XM_PHYDATA1 0x0054 174 #define SK_BMU_RX_CSR0 0x0060 175 #define SK_BMU_RX_CSR1 0x0064 176 #define SK_BMU_TXS_CSR0 0x0068 177 #define SK_BMU_TXA_CSR0 0x006C 178 #define SK_BMU_TXS_CSR1 0x0070 179 #define SK_BMU_TXA_CSR1 0x0074 180 181 /* SK_CSR register */ 182 #define SK_CSR_SW_RESET 0x0001 183 #define SK_CSR_SW_UNRESET 0x0002 184 #define SK_CSR_MASTER_RESET 0x0004 185 #define SK_CSR_MASTER_UNRESET 0x0008 186 #define SK_CSR_MASTER_STOP 0x0010 187 #define SK_CSR_MASTER_DONE 0x0020 188 #define SK_CSR_SW_IRQ_CLEAR 0x0040 189 #define SK_CSR_SW_IRQ_SET 0x0080 190 #define SK_CSR_SLOTSIZE 0x0100 /* 1 == 64 bits, 0 == 32 */ 191 #define SK_CSR_BUSCLOCK 0x0200 /* 1 == 33/66 Mhz, = 33 */ 192 193 /* SK_LED register */ 194 #define SK_LED_GREEN_OFF 0x01 195 #define SK_LED_GREEN_ON 0x02 196 197 /* SK_ISR register */ 198 #define SK_ISR_TX2_AS_CHECK 0x00000001 199 #define SK_ISR_TX2_AS_EOF 0x00000002 200 #define SK_ISR_TX2_AS_EOB 0x00000004 201 #define SK_ISR_TX2_S_CHECK 0x00000008 202 #define SK_ISR_TX2_S_EOF 0x00000010 203 #define SK_ISR_TX2_S_EOB 0x00000020 204 #define SK_ISR_TX1_AS_CHECK 0x00000040 205 #define SK_ISR_TX1_AS_EOF 0x00000080 206 #define SK_ISR_TX1_AS_EOB 0x00000100 207 #define SK_ISR_TX1_S_CHECK 0x00000200 208 #define SK_ISR_TX1_S_EOF 0x00000400 209 #define SK_ISR_TX1_S_EOB 0x00000800 210 #define SK_ISR_RX2_CHECK 0x00001000 211 #define SK_ISR_RX2_EOF 0x00002000 212 #define SK_ISR_RX2_EOB 0x00004000 213 #define SK_ISR_RX1_CHECK 0x00008000 214 #define SK_ISR_RX1_EOF 0x00010000 215 #define SK_ISR_RX1_EOB 0x00020000 216 #define SK_ISR_LINK2_OFLOW 0x00040000 217 #define SK_ISR_MAC2 0x00080000 218 #define SK_ISR_LINK1_OFLOW 0x00100000 219 #define SK_ISR_MAC1 0x00200000 220 #define SK_ISR_TIMER 0x00400000 221 #define SK_ISR_EXTERNAL_REG 0x00800000 222 #define SK_ISR_SW 0x01000000 223 #define SK_ISR_I2C_RDY 0x02000000 224 #define SK_ISR_TX2_TIMEO 0x04000000 225 #define SK_ISR_TX1_TIMEO 0x08000000 226 #define SK_ISR_RX2_TIMEO 0x10000000 227 #define SK_ISR_RX1_TIMEO 0x20000000 228 #define SK_ISR_RSVD 0x40000000 229 #define SK_ISR_HWERR 0x80000000 230 231 /* SK_IMR register */ 232 #define SK_IMR_TX2_AS_CHECK 0x00000001 233 #define SK_IMR_TX2_AS_EOF 0x00000002 234 #define SK_IMR_TX2_AS_EOB 0x00000004 235 #define SK_IMR_TX2_S_CHECK 0x00000008 236 #define SK_IMR_TX2_S_EOF 0x00000010 237 #define SK_IMR_TX2_S_EOB 0x00000020 238 #define SK_IMR_TX1_AS_CHECK 0x00000040 239 #define SK_IMR_TX1_AS_EOF 0x00000080 240 #define SK_IMR_TX1_AS_EOB 0x00000100 241 #define SK_IMR_TX1_S_CHECK 0x00000200 242 #define SK_IMR_TX1_S_EOF 0x00000400 243 #define SK_IMR_TX1_S_EOB 0x00000800 244 #define SK_IMR_RX2_CHECK 0x00001000 245 #define SK_IMR_RX2_EOF 0x00002000 246 #define SK_IMR_RX2_EOB 0x00004000 247 #define SK_IMR_RX1_CHECK 0x00008000 248 #define SK_IMR_RX1_EOF 0x00010000 249 #define SK_IMR_RX1_EOB 0x00020000 250 #define SK_IMR_LINK2_OFLOW 0x00040000 251 #define SK_IMR_MAC2 0x00080000 252 #define SK_IMR_LINK1_OFLOW 0x00100000 253 #define SK_IMR_MAC1 0x00200000 254 #define SK_IMR_TIMER 0x00400000 255 #define SK_IMR_EXTERNAL_REG 0x00800000 256 #define SK_IMR_SW 0x01000000 257 #define SK_IMR_I2C_RDY 0x02000000 258 #define SK_IMR_TX2_TIMEO 0x04000000 259 #define SK_IMR_TX1_TIMEO 0x08000000 260 #define SK_IMR_RX2_TIMEO 0x10000000 261 #define SK_IMR_RX1_TIMEO 0x20000000 262 #define SK_IMR_RSVD 0x40000000 263 #define SK_IMR_HWERR 0x80000000 264 265 #define SK_INTRS1 \ 266 (SK_IMR_RX1_EOF|SK_IMR_TX1_S_EOF|SK_IMR_MAC1) 267 268 #define SK_INTRS2 \ 269 (SK_IMR_RX2_EOF|SK_IMR_TX2_S_EOF|SK_IMR_MAC2) 270 271 /* SK_IESR register */ 272 #define SK_IESR_PAR_RX2 0x00000001 273 #define SK_IESR_PAR_RX1 0x00000002 274 #define SK_IESR_PAR_MAC2 0x00000004 275 #define SK_IESR_PAR_MAC1 0x00000008 276 #define SK_IESR_PAR_WR_RAM 0x00000010 277 #define SK_IESR_PAR_RD_RAM 0x00000020 278 #define SK_IESR_NO_TSTAMP_MAC2 0x00000040 279 #define SK_IESR_NO_TSTAMO_MAC1 0x00000080 280 #define SK_IESR_NO_STS_MAC2 0x00000100 281 #define SK_IESR_NO_STS_MAC1 0x00000200 282 #define SK_IESR_IRQ_STS 0x00000400 283 #define SK_IESR_MASTERERR 0x00000800 284 285 /* SK_IEMR register */ 286 #define SK_IEMR_PAR_RX2 0x00000001 287 #define SK_IEMR_PAR_RX1 0x00000002 288 #define SK_IEMR_PAR_MAC2 0x00000004 289 #define SK_IEMR_PAR_MAC1 0x00000008 290 #define SK_IEMR_PAR_WR_RAM 0x00000010 291 #define SK_IEMR_PAR_RD_RAM 0x00000020 292 #define SK_IEMR_NO_TSTAMP_MAC2 0x00000040 293 #define SK_IEMR_NO_TSTAMO_MAC1 0x00000080 294 #define SK_IEMR_NO_STS_MAC2 0x00000100 295 #define SK_IEMR_NO_STS_MAC1 0x00000200 296 #define SK_IEMR_IRQ_STS 0x00000400 297 #define SK_IEMR_MASTERERR 0x00000800 298 299 /* Block 2 */ 300 #define SK_MAC0_0 0x0100 301 #define SK_MAC0_1 0x0104 302 #define SK_MAC1_0 0x0108 303 #define SK_MAC1_1 0x010C 304 #define SK_MAC2_0 0x0110 305 #define SK_MAC2_1 0x0114 306 #define SK_CONNTYPE 0x0118 307 #define SK_PMDTYPE 0x0119 308 #define SK_CONFIG 0x011A 309 #define SK_CHIPVER 0x011B 310 #define SK_EPROM0 0x011C 311 #define SK_EPROM1 0x011D 312 #define SK_EPROM2 0x011E 313 #define SK_EPROM3 0x011F 314 #define SK_EP_ADDR 0x0120 315 #define SK_EP_DATA 0x0124 316 #define SK_EP_LOADCTL 0x0128 317 #define SK_EP_LOADTST 0x0129 318 #define SK_TIMERINIT 0x0130 319 #define SK_TIMER 0x0134 320 #define SK_TIMERCTL 0x0138 321 #define SK_TIMERTST 0x0139 322 #define SK_IMTIMERINIT 0x0140 323 #define SK_IMTIMER 0x0144 324 #define SK_IMTIMERCTL 0x0148 325 #define SK_IMTIMERTST 0x0149 326 #define SK_IMMR 0x014C 327 #define SK_IHWEMR 0x0150 328 #define SK_TESTCTL1 0x0158 329 #define SK_TESTCTL2 0x0159 330 #define SK_GPIO 0x015C 331 #define SK_I2CHWCTL 0x0160 332 #define SK_I2CHWDATA 0x0164 333 #define SK_I2CHWIRQ 0x0168 334 #define SK_I2CSW 0x016C 335 #define SK_BLNKINIT 0x0170 336 #define SK_BLNKCOUNT 0x0174 337 #define SK_BLNKCTL 0x0178 338 #define SK_BLNKSTS 0x0179 339 #define SK_BLNKTST 0x017A 340 341 #define SK_IMCTL_STOP 0x02 342 #define SK_IMCTL_START 0x04 343 344 #define SK_IMTIMER_TICKS 54 345 #define SK_IM_USECS(x) ((x) * SK_IMTIMER_TICKS) 346 347 /* 348 * The SK_EPROM0 register contains a byte that describes the 349 * amount of SRAM mounted on the NIC. The value also tells if 350 * the chips are 64K or 128K. This affects the RAMbuffer address 351 * offset that we need to use. 352 */ 353 #define SK_RAMSIZE_512K_64 0x1 354 #define SK_RAMSIZE_1024K_128 0x2 355 #define SK_RAMSIZE_1024K_64 0x3 356 #define SK_RAMSIZE_2048K_128 0x4 357 358 #define SK_RBOFF_0 0x0 359 #define SK_RBOFF_80000 0x80000 360 361 /* 362 * SK_EEPROM1 contains the PHY type, which may be XMAC for 363 * fiber-based cards or BCOM for 1000baseT cards with a Broadcom 364 * PHY. 365 */ 366 #define SK_PHYTYPE_XMAC 0 /* integeated XMAC II PHY */ 367 #define SK_PHYTYPE_BCOM 1 /* Broadcom BCM5400 */ 368 #define SK_PHYTYPE_LONE 2 /* Level One LXT1000 */ 369 #define SK_PHYTYPE_NAT 3 /* National DP83891 */ 370 #define SK_PHYTYPE_MARV_COPPER 4 /* Marvell 88E1011S */ 371 #define SK_PHYTYPE_MARV_FIBER 5 /* Marvell 88E1011S (fiber) */ 372 373 /* 374 * PHY addresses. 375 */ 376 #define SK_PHYADDR_XMAC 0x0 377 #define SK_PHYADDR_BCOM 0x1 378 #define SK_PHYADDR_LONE 0x3 379 #define SK_PHYADDR_NAT 0x0 380 #define SK_PHYADDR_MARV 0x0 381 382 #define SK_CONFIG_SINGLEMAC 0x01 383 #define SK_CONFIG_DIS_DSL_CLK 0x02 384 385 #define SK_PMD_1000BASELX 0x4C 386 #define SK_PMD_1000BASESX 0x53 387 #define SK_PMD_1000BASECX 0x43 388 #define SK_PMD_1000BASETX 0x54 389 390 /* GPIO bits */ 391 #define SK_GPIO_DAT0 0x00000001 392 #define SK_GPIO_DAT1 0x00000002 393 #define SK_GPIO_DAT2 0x00000004 394 #define SK_GPIO_DAT3 0x00000008 395 #define SK_GPIO_DAT4 0x00000010 396 #define SK_GPIO_DAT5 0x00000020 397 #define SK_GPIO_DAT6 0x00000040 398 #define SK_GPIO_DAT7 0x00000080 399 #define SK_GPIO_DAT8 0x00000100 400 #define SK_GPIO_DAT9 0x00000200 401 #define SK_GPIO_DIR0 0x00010000 402 #define SK_GPIO_DIR1 0x00020000 403 #define SK_GPIO_DIR2 0x00040000 404 #define SK_GPIO_DIR3 0x00080000 405 #define SK_GPIO_DIR4 0x00100000 406 #define SK_GPIO_DIR5 0x00200000 407 #define SK_GPIO_DIR6 0x00400000 408 #define SK_GPIO_DIR7 0x00800000 409 #define SK_GPIO_DIR8 0x01000000 410 #define SK_GPIO_DIR9 0x02000000 411 412 /* Block 3 Ram interface and MAC arbiter registers */ 413 #define SK_RAMADDR 0x0180 414 #define SK_RAMDATA0 0x0184 415 #define SK_RAMDATA1 0x0188 416 #define SK_TO0 0x0190 417 #define SK_TO1 0x0191 418 #define SK_TO2 0x0192 419 #define SK_TO3 0x0193 420 #define SK_TO4 0x0194 421 #define SK_TO5 0x0195 422 #define SK_TO6 0x0196 423 #define SK_TO7 0x0197 424 #define SK_TO8 0x0198 425 #define SK_TO9 0x0199 426 #define SK_TO10 0x019A 427 #define SK_TO11 0x019B 428 #define SK_RITIMEO_TMR 0x019C 429 #define SK_RAMCTL 0x01A0 430 #define SK_RITIMER_TST 0x01A2 431 432 #define SK_RAMCTL_RESET 0x0001 433 #define SK_RAMCTL_UNRESET 0x0002 434 #define SK_RAMCTL_CLR_IRQ_WPAR 0x0100 435 #define SK_RAMCTL_CLR_IRQ_RPAR 0x0200 436 437 /* Mac arbiter registers */ 438 #define SK_MINIT_RX1 0x01B0 439 #define SK_MINIT_RX2 0x01B1 440 #define SK_MINIT_TX1 0x01B2 441 #define SK_MINIT_TX2 0x01B3 442 #define SK_MTIMEO_RX1 0x01B4 443 #define SK_MTIMEO_RX2 0x01B5 444 #define SK_MTIMEO_TX1 0x01B6 445 #define SK_MTIEMO_TX2 0x01B7 446 #define SK_MACARB_CTL 0x01B8 447 #define SK_MTIMER_TST 0x01BA 448 #define SK_RCINIT_RX1 0x01C0 449 #define SK_RCINIT_RX2 0x01C1 450 #define SK_RCINIT_TX1 0x01C2 451 #define SK_RCINIT_TX2 0x01C3 452 #define SK_RCTIMEO_RX1 0x01C4 453 #define SK_RCTIMEO_RX2 0x01C5 454 #define SK_RCTIMEO_TX1 0x01C6 455 #define SK_RCTIMEO_TX2 0x01C7 456 #define SK_RECOVERY_CTL 0x01C8 457 #define SK_RCTIMER_TST 0x01CA 458 459 /* Packet arbiter registers */ 460 #define SK_RXPA1_TINIT 0x01D0 461 #define SK_RXPA2_TINIT 0x01D4 462 #define SK_TXPA1_TINIT 0x01D8 463 #define SK_TXPA2_TINIT 0x01DC 464 #define SK_RXPA1_TIMEO 0x01E0 465 #define SK_RXPA2_TIMEO 0x01E4 466 #define SK_TXPA1_TIMEO 0x01E8 467 #define SK_TXPA2_TIMEO 0x01EC 468 #define SK_PKTARB_CTL 0x01F0 469 #define SK_PKTATB_TST 0x01F2 470 471 #define SK_PKTARB_TIMEOUT 0x2000 472 473 #define SK_PKTARBCTL_RESET 0x0001 474 #define SK_PKTARBCTL_UNRESET 0x0002 475 #define SK_PKTARBCTL_RXTO1_OFF 0x0004 476 #define SK_PKTARBCTL_RXTO1_ON 0x0008 477 #define SK_PKTARBCTL_RXTO2_OFF 0x0010 478 #define SK_PKTARBCTL_RXTO2_ON 0x0020 479 #define SK_PKTARBCTL_TXTO1_OFF 0x0040 480 #define SK_PKTARBCTL_TXTO1_ON 0x0080 481 #define SK_PKTARBCTL_TXTO2_OFF 0x0100 482 #define SK_PKTARBCTL_TXTO2_ON 0x0200 483 #define SK_PKTARBCTL_CLR_IRQ_RXTO1 0x0400 484 #define SK_PKTARBCTL_CLR_IRQ_RXTO2 0x0800 485 #define SK_PKTARBCTL_CLR_IRQ_TXTO1 0x1000 486 #define SK_PKTARBCTL_CLR_IRQ_TXTO2 0x2000 487 488 #define SK_MINIT_XMAC_B2 54 489 #define SK_MINIT_XMAC_C1 63 490 491 #define SK_MACARBCTL_RESET 0x0001 492 #define SK_MACARBCTL_UNRESET 0x0002 493 #define SK_MACARBCTL_FASTOE_OFF 0x0004 494 #define SK_MACARBCRL_FASTOE_ON 0x0008 495 496 #define SK_RCINIT_XMAC_B2 54 497 #define SK_RCINIT_XMAC_C1 0 498 499 #define SK_RECOVERYCTL_RX1_OFF 0x0001 500 #define SK_RECOVERYCTL_RX1_ON 0x0002 501 #define SK_RECOVERYCTL_RX2_OFF 0x0004 502 #define SK_RECOVERYCTL_RX2_ON 0x0008 503 #define SK_RECOVERYCTL_TX1_OFF 0x0010 504 #define SK_RECOVERYCTL_TX1_ON 0x0020 505 #define SK_RECOVERYCTL_TX2_OFF 0x0040 506 #define SK_RECOVERYCTL_TX2_ON 0x0080 507 508 #define SK_RECOVERY_XMAC_B2 \ 509 (SK_RECOVERYCTL_RX1_ON|SK_RECOVERYCTL_RX2_ON| \ 510 SK_RECOVERYCTL_TX1_ON|SK_RECOVERYCTL_TX2_ON) 511 512 #define SK_RECOVERY_XMAC_C1 \ 513 (SK_RECOVERYCTL_RX1_OFF|SK_RECOVERYCTL_RX2_OFF| \ 514 SK_RECOVERYCTL_TX1_OFF|SK_RECOVERYCTL_TX2_OFF) 515 516 /* Block 4 -- TX Arbiter MAC 1 */ 517 #define SK_TXAR1_TIMERINIT 0x0200 518 #define SK_TXAR1_TIMERVAL 0x0204 519 #define SK_TXAR1_LIMITINIT 0x0208 520 #define SK_TXAR1_LIMITCNT 0x020C 521 #define SK_TXAR1_COUNTERCTL 0x0210 522 #define SK_TXAR1_COUNTERTST 0x0212 523 #define SK_TXAR1_COUNTERSTS 0x0212 524 525 /* Block 5 -- TX Arbiter MAC 2 */ 526 #define SK_TXAR2_TIMERINIT 0x0280 527 #define SK_TXAR2_TIMERVAL 0x0284 528 #define SK_TXAR2_LIMITINIT 0x0288 529 #define SK_TXAR2_LIMITCNT 0x028C 530 #define SK_TXAR2_COUNTERCTL 0x0290 531 #define SK_TXAR2_COUNTERTST 0x0291 532 #define SK_TXAR2_COUNTERSTS 0x0292 533 534 #define SK_TXARCTL_OFF 0x01 535 #define SK_TXARCTL_ON 0x02 536 #define SK_TXARCTL_RATECTL_OFF 0x04 537 #define SK_TXARCTL_RATECTL_ON 0x08 538 #define SK_TXARCTL_ALLOC_OFF 0x10 539 #define SK_TXARCTL_ALLOC_ON 0x20 540 #define SK_TXARCTL_FSYNC_OFF 0x40 541 #define SK_TXARCTL_FSYNC_ON 0x80 542 543 /* Block 6 -- External registers */ 544 #define SK_EXTREG_BASE 0x300 545 #define SK_EXTREG_END 0x37C 546 547 /* Block 7 -- PCI config registers */ 548 #define SK_PCI_BASE 0x0380 549 #define SK_PCI_END 0x03FC 550 551 /* Compute offset of mirrored PCI register */ 552 #define SK_PCI_REG(reg) ((reg) + SK_PCI_BASE) 553 554 /* Block 8 -- RX queue 1 */ 555 #define SK_RXQ1_BUFCNT 0x0400 556 #define SK_RXQ1_BUFCTL 0x0402 557 #define SK_RXQ1_NEXTDESC 0x0404 558 #define SK_RXQ1_RXBUF_LO 0x0408 559 #define SK_RXQ1_RXBUF_HI 0x040C 560 #define SK_RXQ1_RXSTAT 0x0410 561 #define SK_RXQ1_TIMESTAMP 0x0414 562 #define SK_RXQ1_CSUM1 0x0418 563 #define SK_RXQ1_CSUM2 0x041A 564 #define SK_RXQ1_CSUM1_START 0x041C 565 #define SK_RXQ1_CSUM2_START 0x041E 566 #define SK_RXQ1_CURADDR_LO 0x0420 567 #define SK_RXQ1_CURADDR_HI 0x0424 568 #define SK_RXQ1_CURCNT_LO 0x0428 569 #define SK_RXQ1_CURCNT_HI 0x042C 570 #define SK_RXQ1_CURBYTES 0x0430 571 #define SK_RXQ1_BMU_CSR 0x0434 572 #define SK_RXQ1_WATERMARK 0x0438 573 #define SK_RXQ1_FLAG 0x043A 574 #define SK_RXQ1_TEST1 0x043C 575 #define SK_RXQ1_TEST2 0x0440 576 #define SK_RXQ1_TEST3 0x0444 577 578 /* Block 9 -- RX queue 2 */ 579 #define SK_RXQ2_BUFCNT 0x0480 580 #define SK_RXQ2_BUFCTL 0x0482 581 #define SK_RXQ2_NEXTDESC 0x0484 582 #define SK_RXQ2_RXBUF_LO 0x0488 583 #define SK_RXQ2_RXBUF_HI 0x048C 584 #define SK_RXQ2_RXSTAT 0x0490 585 #define SK_RXQ2_TIMESTAMP 0x0494 586 #define SK_RXQ2_CSUM1 0x0498 587 #define SK_RXQ2_CSUM2 0x049A 588 #define SK_RXQ2_CSUM1_START 0x049C 589 #define SK_RXQ2_CSUM2_START 0x049E 590 #define SK_RXQ2_CURADDR_LO 0x04A0 591 #define SK_RXQ2_CURADDR_HI 0x04A4 592 #define SK_RXQ2_CURCNT_LO 0x04A8 593 #define SK_RXQ2_CURCNT_HI 0x04AC 594 #define SK_RXQ2_CURBYTES 0x04B0 595 #define SK_RXQ2_BMU_CSR 0x04B4 596 #define SK_RXQ2_WATERMARK 0x04B8 597 #define SK_RXQ2_FLAG 0x04BA 598 #define SK_RXQ2_TEST1 0x04BC 599 #define SK_RXQ2_TEST2 0x04C0 600 #define SK_RXQ2_TEST3 0x04C4 601 602 #define SK_RXBMU_CLR_IRQ_ERR 0x00000001 603 #define SK_RXBMU_CLR_IRQ_EOF 0x00000002 604 #define SK_RXBMU_CLR_IRQ_EOB 0x00000004 605 #define SK_RXBMU_CLR_IRQ_PAR 0x00000008 606 #define SK_RXBMU_RX_START 0x00000010 607 #define SK_RXBMU_RX_STOP 0x00000020 608 #define SK_RXBMU_POLL_OFF 0x00000040 609 #define SK_RXBMU_POLL_ON 0x00000080 610 #define SK_RXBMU_TRANSFER_SM_RESET 0x00000100 611 #define SK_RXBMU_TRANSFER_SM_UNRESET 0x00000200 612 #define SK_RXBMU_DESCWR_SM_RESET 0x00000400 613 #define SK_RXBMU_DESCWR_SM_UNRESET 0x00000800 614 #define SK_RXBMU_DESCRD_SM_RESET 0x00001000 615 #define SK_RXBMU_DESCRD_SM_UNRESET 0x00002000 616 #define SK_RXBMU_SUPERVISOR_SM_RESET 0x00004000 617 #define SK_RXBMU_SUPERVISOR_SM_UNRESET 0x00008000 618 #define SK_RXBMU_PFI_SM_RESET 0x00010000 619 #define SK_RXBMU_PFI_SM_UNRESET 0x00020000 620 #define SK_RXBMU_FIFO_RESET 0x00040000 621 #define SK_RXBMU_FIFO_UNRESET 0x00080000 622 #define SK_RXBMU_DESC_RESET 0x00100000 623 #define SK_RXBMU_DESC_UNRESET 0x00200000 624 #define SK_RXBMU_SUPERVISOR_IDLE 0x01000000 625 626 #define SK_RXBMU_ONLINE \ 627 (SK_RXBMU_TRANSFER_SM_UNRESET|SK_RXBMU_DESCWR_SM_UNRESET| \ 628 SK_RXBMU_DESCRD_SM_UNRESET|SK_RXBMU_SUPERVISOR_SM_UNRESET| \ 629 SK_RXBMU_PFI_SM_UNRESET|SK_RXBMU_FIFO_UNRESET| \ 630 SK_RXBMU_DESC_UNRESET) 631 632 #define SK_RXBMU_OFFLINE \ 633 (SK_RXBMU_TRANSFER_SM_RESET|SK_RXBMU_DESCWR_SM_RESET| \ 634 SK_RXBMU_DESCRD_SM_RESET|SK_RXBMU_SUPERVISOR_SM_RESET| \ 635 SK_RXBMU_PFI_SM_RESET|SK_RXBMU_FIFO_RESET| \ 636 SK_RXBMU_DESC_RESET) 637 638 /* Block 12 -- TX sync queue 1 */ 639 #define SK_TXQS1_BUFCNT 0x0600 640 #define SK_TXQS1_BUFCTL 0x0602 641 #define SK_TXQS1_NEXTDESC 0x0604 642 #define SK_TXQS1_RXBUF_LO 0x0608 643 #define SK_TXQS1_RXBUF_HI 0x060C 644 #define SK_TXQS1_RXSTAT 0x0610 645 #define SK_TXQS1_CSUM_STARTVAL 0x0614 646 #define SK_TXQS1_CSUM_STARTPOS 0x0618 647 #define SK_TXQS1_CSUM_WRITEPOS 0x061A 648 #define SK_TXQS1_CURADDR_LO 0x0620 649 #define SK_TXQS1_CURADDR_HI 0x0624 650 #define SK_TXQS1_CURCNT_LO 0x0628 651 #define SK_TXQS1_CURCNT_HI 0x062C 652 #define SK_TXQS1_CURBYTES 0x0630 653 #define SK_TXQS1_BMU_CSR 0x0634 654 #define SK_TXQS1_WATERMARK 0x0638 655 #define SK_TXQS1_FLAG 0x063A 656 #define SK_TXQS1_TEST1 0x063C 657 #define SK_TXQS1_TEST2 0x0640 658 #define SK_TXQS1_TEST3 0x0644 659 660 /* Block 13 -- TX async queue 1 */ 661 #define SK_TXQA1_BUFCNT 0x0680 662 #define SK_TXQA1_BUFCTL 0x0682 663 #define SK_TXQA1_NEXTDESC 0x0684 664 #define SK_TXQA1_RXBUF_LO 0x0688 665 #define SK_TXQA1_RXBUF_HI 0x068C 666 #define SK_TXQA1_RXSTAT 0x0690 667 #define SK_TXQA1_CSUM_STARTVAL 0x0694 668 #define SK_TXQA1_CSUM_STARTPOS 0x0698 669 #define SK_TXQA1_CSUM_WRITEPOS 0x069A 670 #define SK_TXQA1_CURADDR_LO 0x06A0 671 #define SK_TXQA1_CURADDR_HI 0x06A4 672 #define SK_TXQA1_CURCNT_LO 0x06A8 673 #define SK_TXQA1_CURCNT_HI 0x06AC 674 #define SK_TXQA1_CURBYTES 0x06B0 675 #define SK_TXQA1_BMU_CSR 0x06B4 676 #define SK_TXQA1_WATERMARK 0x06B8 677 #define SK_TXQA1_FLAG 0x06BA 678 #define SK_TXQA1_TEST1 0x06BC 679 #define SK_TXQA1_TEST2 0x06C0 680 #define SK_TXQA1_TEST3 0x06C4 681 682 /* Block 14 -- TX sync queue 2 */ 683 #define SK_TXQS2_BUFCNT 0x0700 684 #define SK_TXQS2_BUFCTL 0x0702 685 #define SK_TXQS2_NEXTDESC 0x0704 686 #define SK_TXQS2_RXBUF_LO 0x0708 687 #define SK_TXQS2_RXBUF_HI 0x070C 688 #define SK_TXQS2_RXSTAT 0x0710 689 #define SK_TXQS2_CSUM_STARTVAL 0x0714 690 #define SK_TXQS2_CSUM_STARTPOS 0x0718 691 #define SK_TXQS2_CSUM_WRITEPOS 0x071A 692 #define SK_TXQS2_CURADDR_LO 0x0720 693 #define SK_TXQS2_CURADDR_HI 0x0724 694 #define SK_TXQS2_CURCNT_LO 0x0728 695 #define SK_TXQS2_CURCNT_HI 0x072C 696 #define SK_TXQS2_CURBYTES 0x0730 697 #define SK_TXQS2_BMU_CSR 0x0734 698 #define SK_TXQS2_WATERMARK 0x0738 699 #define SK_TXQS2_FLAG 0x073A 700 #define SK_TXQS2_TEST1 0x073C 701 #define SK_TXQS2_TEST2 0x0740 702 #define SK_TXQS2_TEST3 0x0744 703 704 /* Block 15 -- TX async queue 2 */ 705 #define SK_TXQA2_BUFCNT 0x0780 706 #define SK_TXQA2_BUFCTL 0x0782 707 #define SK_TXQA2_NEXTDESC 0x0784 708 #define SK_TXQA2_RXBUF_LO 0x0788 709 #define SK_TXQA2_RXBUF_HI 0x078C 710 #define SK_TXQA2_RXSTAT 0x0790 711 #define SK_TXQA2_CSUM_STARTVAL 0x0794 712 #define SK_TXQA2_CSUM_STARTPOS 0x0798 713 #define SK_TXQA2_CSUM_WRITEPOS 0x079A 714 #define SK_TXQA2_CURADDR_LO 0x07A0 715 #define SK_TXQA2_CURADDR_HI 0x07A4 716 #define SK_TXQA2_CURCNT_LO 0x07A8 717 #define SK_TXQA2_CURCNT_HI 0x07AC 718 #define SK_TXQA2_CURBYTES 0x07B0 719 #define SK_TXQA2_BMU_CSR 0x07B4 720 #define SK_TXQA2_WATERMARK 0x07B8 721 #define SK_TXQA2_FLAG 0x07BA 722 #define SK_TXQA2_TEST1 0x07BC 723 #define SK_TXQA2_TEST2 0x07C0 724 #define SK_TXQA2_TEST3 0x07C4 725 726 #define SK_TXBMU_CLR_IRQ_ERR 0x00000001 727 #define SK_TXBMU_CLR_IRQ_EOF 0x00000002 728 #define SK_TXBMU_CLR_IRQ_EOB 0x00000004 729 #define SK_TXBMU_TX_START 0x00000010 730 #define SK_TXBMU_TX_STOP 0x00000020 731 #define SK_TXBMU_POLL_OFF 0x00000040 732 #define SK_TXBMU_POLL_ON 0x00000080 733 #define SK_TXBMU_TRANSFER_SM_RESET 0x00000100 734 #define SK_TXBMU_TRANSFER_SM_UNRESET 0x00000200 735 #define SK_TXBMU_DESCWR_SM_RESET 0x00000400 736 #define SK_TXBMU_DESCWR_SM_UNRESET 0x00000800 737 #define SK_TXBMU_DESCRD_SM_RESET 0x00001000 738 #define SK_TXBMU_DESCRD_SM_UNRESET 0x00002000 739 #define SK_TXBMU_SUPERVISOR_SM_RESET 0x00004000 740 #define SK_TXBMU_SUPERVISOR_SM_UNRESET 0x00008000 741 #define SK_TXBMU_PFI_SM_RESET 0x00010000 742 #define SK_TXBMU_PFI_SM_UNRESET 0x00020000 743 #define SK_TXBMU_FIFO_RESET 0x00040000 744 #define SK_TXBMU_FIFO_UNRESET 0x00080000 745 #define SK_TXBMU_DESC_RESET 0x00100000 746 #define SK_TXBMU_DESC_UNRESET 0x00200000 747 #define SK_TXBMU_SUPERVISOR_IDLE 0x01000000 748 749 #define SK_TXBMU_ONLINE \ 750 (SK_TXBMU_TRANSFER_SM_UNRESET|SK_TXBMU_DESCWR_SM_UNRESET| \ 751 SK_TXBMU_DESCRD_SM_UNRESET|SK_TXBMU_SUPERVISOR_SM_UNRESET| \ 752 SK_TXBMU_PFI_SM_UNRESET|SK_TXBMU_FIFO_UNRESET| \ 753 SK_TXBMU_DESC_UNRESET) 754 755 #define SK_TXBMU_OFFLINE \ 756 (SK_TXBMU_TRANSFER_SM_RESET|SK_TXBMU_DESCWR_SM_RESET| \ 757 SK_TXBMU_DESCRD_SM_RESET|SK_TXBMU_SUPERVISOR_SM_RESET| \ 758 SK_TXBMU_PFI_SM_RESET|SK_TXBMU_FIFO_RESET| \ 759 SK_TXBMU_DESC_RESET) 760 761 /* Block 16 -- Receive RAMbuffer 1 */ 762 #define SK_RXRB1_START 0x0800 763 #define SK_RXRB1_END 0x0804 764 #define SK_RXRB1_WR_PTR 0x0808 765 #define SK_RXRB1_RD_PTR 0x080C 766 #define SK_RXRB1_UTHR_PAUSE 0x0810 767 #define SK_RXRB1_LTHR_PAUSE 0x0814 768 #define SK_RXRB1_UTHR_HIPRIO 0x0818 769 #define SK_RXRB1_UTHR_LOPRIO 0x081C 770 #define SK_RXRB1_PKTCNT 0x0820 771 #define SK_RXRB1_LVL 0x0824 772 #define SK_RXRB1_CTLTST 0x0828 773 774 /* Block 17 -- Receive RAMbuffer 2 */ 775 #define SK_RXRB2_START 0x0880 776 #define SK_RXRB2_END 0x0884 777 #define SK_RXRB2_WR_PTR 0x0888 778 #define SK_RXRB2_RD_PTR 0x088C 779 #define SK_RXRB2_UTHR_PAUSE 0x0890 780 #define SK_RXRB2_LTHR_PAUSE 0x0894 781 #define SK_RXRB2_UTHR_HIPRIO 0x0898 782 #define SK_RXRB2_UTHR_LOPRIO 0x089C 783 #define SK_RXRB2_PKTCNT 0x08A0 784 #define SK_RXRB2_LVL 0x08A4 785 #define SK_RXRB2_CTLTST 0x08A8 786 787 /* Block 20 -- Sync. Transmit RAMbuffer 1 */ 788 #define SK_TXRBS1_START 0x0A00 789 #define SK_TXRBS1_END 0x0A04 790 #define SK_TXRBS1_WR_PTR 0x0A08 791 #define SK_TXRBS1_RD_PTR 0x0A0C 792 #define SK_TXRBS1_PKTCNT 0x0A20 793 #define SK_TXRBS1_LVL 0x0A24 794 #define SK_TXRBS1_CTLTST 0x0A28 795 796 /* Block 21 -- Async. Transmit RAMbuffer 1 */ 797 #define SK_TXRBA1_START 0x0A80 798 #define SK_TXRBA1_END 0x0A84 799 #define SK_TXRBA1_WR_PTR 0x0A88 800 #define SK_TXRBA1_RD_PTR 0x0A8C 801 #define SK_TXRBA1_PKTCNT 0x0AA0 802 #define SK_TXRBA1_LVL 0x0AA4 803 #define SK_TXRBA1_CTLTST 0x0AA8 804 805 /* Block 22 -- Sync. Transmit RAMbuffer 2 */ 806 #define SK_TXRBS2_START 0x0B00 807 #define SK_TXRBS2_END 0x0B04 808 #define SK_TXRBS2_WR_PTR 0x0B08 809 #define SK_TXRBS2_RD_PTR 0x0B0C 810 #define SK_TXRBS2_PKTCNT 0x0B20 811 #define SK_TXRBS2_LVL 0x0B24 812 #define SK_TXRBS2_CTLTST 0x0B28 813 814 /* Block 23 -- Async. Transmit RAMbuffer 2 */ 815 #define SK_TXRBA2_START 0x0B80 816 #define SK_TXRBA2_END 0x0B84 817 #define SK_TXRBA2_WR_PTR 0x0B88 818 #define SK_TXRBA2_RD_PTR 0x0B8C 819 #define SK_TXRBA2_PKTCNT 0x0BA0 820 #define SK_TXRBA2_LVL 0x0BA4 821 #define SK_TXRBA2_CTLTST 0x0BA8 822 823 #define SK_RBCTL_RESET 0x00000001 824 #define SK_RBCTL_UNRESET 0x00000002 825 #define SK_RBCTL_OFF 0x00000004 826 #define SK_RBCTL_ON 0x00000008 827 #define SK_RBCTL_STORENFWD_OFF 0x00000010 828 #define SK_RBCTL_STORENFWD_ON 0x00000020 829 830 /* Block 24 -- RX MAC FIFO 1 regisrers and LINK_SYNC counter */ 831 #define SK_RXF1_END 0x0C00 832 #define SK_RXF1_WPTR 0x0C04 833 #define SK_RXF1_RPTR 0x0C0C 834 #define SK_RXF1_PKTCNT 0x0C10 835 #define SK_RXF1_LVL 0x0C14 836 #define SK_RXF1_MACCTL 0x0C18 837 #define SK_RXF1_CTL 0x0C1C 838 #define SK_RXLED1_CNTINIT 0x0C20 839 #define SK_RXLED1_COUNTER 0x0C24 840 #define SK_RXLED1_CTL 0x0C28 841 #define SK_RXLED1_TST 0x0C29 842 #define SK_LINK_SYNC1_CINIT 0x0C30 843 #define SK_LINK_SYNC1_COUNTER 0x0C34 844 #define SK_LINK_SYNC1_CTL 0x0C38 845 #define SK_LINK_SYNC1_TST 0x0C39 846 #define SK_LINKLED1_CTL 0x0C3C 847 848 #define SK_FIFO_END 0x3F 849 850 /* Receive MAC FIFO 1 (Yukon Only) */ 851 #define SK_RXMF1_END 0x0C40 852 #define SK_RXMF1_THRESHOLD 0x0C44 853 #define SK_RXMF1_CTRL_TEST 0x0C48 854 #define SK_RXMF1_WRITE_PTR 0x0C60 855 #define SK_RXMF1_WRITE_LEVEL 0x0C68 856 #define SK_RXMF1_READ_PTR 0x0C70 857 #define SK_RXMF1_READ_LEVEL 0x0C78 858 859 #define SK_RFCTL_WR_PTR_TST_ON 0x00004000 /* Write pointer test on*/ 860 #define SK_RFCTL_WR_PTR_TST_OFF 0x00002000 /* Write pointer test off */ 861 #define SK_RFCTL_WR_PTR_STEP 0x00001000 /* Write pointer increment */ 862 #define SK_RFCTL_RD_PTR_TST_ON 0x00000400 /* Read pointer test on */ 863 #define SK_RFCTL_RD_PTR_TST_OFF 0x00000200 /* Read pointer test off */ 864 #define SK_RFCTL_RD_PTR_STEP 0x00000100 /* Read pointer increment */ 865 #define SK_RFCTL_RX_FIFO_OVER 0x00000040 /* Clear IRQ RX FIFO Overrun */ 866 #define SK_RFCTL_FRAME_RX_DONE 0x00000010 /* Clear IRQ Frame RX Done */ 867 #define SK_RFCTL_OPERATION_ON 0x00000008 /* Operational mode on */ 868 #define SK_RFCTL_OPERATION_OFF 0x00000004 /* Operational mode off */ 869 #define SK_RFCTL_RESET_CLEAR 0x00000002 /* MAC FIFO Reset Clear */ 870 #define SK_RFCTL_RESET_SET 0x00000001 /* MAC FIFO Reset Set */ 871 872 /* Block 25 -- RX MAC FIFO 2 regisrers and LINK_SYNC counter */ 873 #define SK_RXF2_END 0x0C80 874 #define SK_RXF2_WPTR 0x0C84 875 #define SK_RXF2_RPTR 0x0C8C 876 #define SK_RXF2_PKTCNT 0x0C90 877 #define SK_RXF2_LVL 0x0C94 878 #define SK_RXF2_MACCTL 0x0C98 879 #define SK_RXF2_CTL 0x0C9C 880 #define SK_RXLED2_CNTINIT 0x0CA0 881 #define SK_RXLED2_COUNTER 0x0CA4 882 #define SK_RXLED2_CTL 0x0CA8 883 #define SK_RXLED2_TST 0x0CA9 884 #define SK_LINK_SYNC2_CINIT 0x0CB0 885 #define SK_LINK_SYNC2_COUNTER 0x0CB4 886 #define SK_LINK_SYNC2_CTL 0x0CB8 887 #define SK_LINK_SYNC2_TST 0x0CB9 888 #define SK_LINKLED2_CTL 0x0CBC 889 890 #define SK_RXMACCTL_CLR_IRQ_NOSTS 0x00000001 891 #define SK_RXMACCTL_CLR_IRQ_NOTSTAMP 0x00000002 892 #define SK_RXMACCTL_TSTAMP_OFF 0x00000004 893 #define SK_RXMACCTL_RSTAMP_ON 0x00000008 894 #define SK_RXMACCTL_FLUSH_OFF 0x00000010 895 #define SK_RXMACCTL_FLUSH_ON 0x00000020 896 #define SK_RXMACCTL_PAUSE_OFF 0x00000040 897 #define SK_RXMACCTL_PAUSE_ON 0x00000080 898 #define SK_RXMACCTL_AFULL_OFF 0x00000100 899 #define SK_RXMACCTL_AFULL_ON 0x00000200 900 #define SK_RXMACCTL_VALIDTIME_PATCH_OFF 0x00000400 901 #define SK_RXMACCTL_VALIDTIME_PATCH_ON 0x00000800 902 #define SK_RXMACCTL_RXRDY_PATCH_OFF 0x00001000 903 #define SK_RXMACCTL_RXRDY_PATCH_ON 0x00002000 904 #define SK_RXMACCTL_STS_TIMEO 0x00FF0000 905 #define SK_RXMACCTL_TSTAMP_TIMEO 0xFF000000 906 907 #define SK_RXLEDCTL_ENABLE 0x0001 908 #define SK_RXLEDCTL_COUNTER_STOP 0x0002 909 #define SK_RXLEDCTL_COUNTER_START 0x0004 910 911 #define SK_LINKLED_OFF 0x0001 912 #define SK_LINKLED_ON 0x0002 913 #define SK_LINKLED_LINKSYNC_OFF 0x0004 914 #define SK_LINKLED_LINKSYNC_ON 0x0008 915 #define SK_LINKLED_BLINK_OFF 0x0010 916 #define SK_LINKLED_BLINK_ON 0x0020 917 918 /* Block 26 -- TX MAC FIFO 1 regisrers */ 919 #define SK_TXF1_END 0x0D00 920 #define SK_TXF1_WPTR 0x0D04 921 #define SK_TXF1_RPTR 0x0D0C 922 #define SK_TXF1_PKTCNT 0x0D10 923 #define SK_TXF1_LVL 0x0D14 924 #define SK_TXF1_MACCTL 0x0D18 925 #define SK_TXF1_CTL 0x0D1C 926 #define SK_TXLED1_CNTINIT 0x0D20 927 #define SK_TXLED1_COUNTER 0x0D24 928 #define SK_TXLED1_CTL 0x0D28 929 #define SK_TXLED1_TST 0x0D29 930 931 /* Receive MAC FIFO 1 (Yukon Only) */ 932 #define SK_TXMF1_END 0x0D40 933 #define SK_TXMF1_THRESHOLD 0x0D44 934 #define SK_TXMF1_CTRL_TEST 0x0D48 935 #define SK_TXMF1_WRITE_PTR 0x0D60 936 #define SK_TXMF1_WRITE_SHADOW 0x0D64 937 #define SK_TXMF1_WRITE_LEVEL 0x0D68 938 #define SK_TXMF1_READ_PTR 0x0D70 939 #define SK_TXMF1_RESTART_PTR 0x0D74 940 #define SK_TXMF1_READ_LEVEL 0x0D78 941 942 #define SK_TFCTL_WR_PTR_TST_ON 0x00004000 /* Write pointer test on*/ 943 #define SK_TFCTL_WR_PTR_TST_OFF 0x00002000 /* Write pointer test off */ 944 #define SK_TFCTL_WR_PTR_STEP 0x00001000 /* Write pointer increment */ 945 #define SK_TFCTL_RD_PTR_TST_ON 0x00000400 /* Read pointer test on */ 946 #define SK_TFCTL_RD_PTR_TST_OFF 0x00000200 /* Read pointer test off */ 947 #define SK_TFCTL_RD_PTR_STEP 0x00000100 /* Read pointer increment */ 948 #define SK_TFCTL_TX_FIFO_UNDER 0x00000040 /* Clear IRQ TX FIFO Under */ 949 #define SK_TFCTL_FRAME_TX_DONE 0x00000020 /* Clear IRQ Frame TX Done */ 950 #define SK_TFCTL_IRQ_PARITY_ER 0x00000010 /* Clear IRQ Parity Error */ 951 #define SK_TFCTL_OPERATION_ON 0x00000008 /* Operational mode on */ 952 #define SK_TFCTL_OPERATION_OFF 0x00000004 /* Operational mode off */ 953 #define SK_TFCTL_RESET_CLEAR 0x00000002 /* MAC FIFO Reset Clear */ 954 #define SK_TFCTL_RESET_SET 0x00000001 /* MAC FIFO Reset Set */ 955 956 /* Block 27 -- TX MAC FIFO 2 regisrers */ 957 #define SK_TXF2_END 0x0D80 958 #define SK_TXF2_WPTR 0x0D84 959 #define SK_TXF2_RPTR 0x0D8C 960 #define SK_TXF2_PKTCNT 0x0D90 961 #define SK_TXF2_LVL 0x0D94 962 #define SK_TXF2_MACCTL 0x0D98 963 #define SK_TXF2_CTL 0x0D9C 964 #define SK_TXLED2_CNTINIT 0x0DA0 965 #define SK_TXLED2_COUNTER 0x0DA4 966 #define SK_TXLED2_CTL 0x0DA8 967 #define SK_TXLED2_TST 0x0DA9 968 969 #define SK_TXMACCTL_XMAC_RESET 0x00000001 970 #define SK_TXMACCTL_XMAC_UNRESET 0x00000002 971 #define SK_TXMACCTL_LOOP_OFF 0x00000004 972 #define SK_TXMACCTL_LOOP_ON 0x00000008 973 #define SK_TXMACCTL_FLUSH_OFF 0x00000010 974 #define SK_TXMACCTL_FLUSH_ON 0x00000020 975 #define SK_TXMACCTL_WAITEMPTY_OFF 0x00000040 976 #define SK_TXMACCTL_WAITEMPTY_ON 0x00000080 977 #define SK_TXMACCTL_AFULL_OFF 0x00000100 978 #define SK_TXMACCTL_AFULL_ON 0x00000200 979 #define SK_TXMACCTL_TXRDY_PATCH_OFF 0x00000400 980 #define SK_TXMACCTL_RXRDY_PATCH_ON 0x00000800 981 #define SK_TXMACCTL_PKT_RECOVERY_OFF 0x00001000 982 #define SK_TXMACCTL_PKT_RECOVERY_ON 0x00002000 983 #define SK_TXMACCTL_CLR_IRQ_PERR 0x00008000 984 #define SK_TXMACCTL_WAITAFTERFLUSH 0x00010000 985 986 #define SK_TXLEDCTL_ENABLE 0x0001 987 #define SK_TXLEDCTL_COUNTER_STOP 0x0002 988 #define SK_TXLEDCTL_COUNTER_START 0x0004 989 990 #define SK_FIFO_RESET 0x00000001 991 #define SK_FIFO_UNRESET 0x00000002 992 #define SK_FIFO_OFF 0x00000004 993 #define SK_FIFO_ON 0x00000008 994 995 /* Block 28 -- Descriptor Poll Timer */ 996 #define SK_DPT_INIT 0x0e00 /* Initial value 24 bits */ 997 #define SK_DPT_TIMER 0x0e04 /* Mul of 78.12MHz clk (24b) */ 998 999 #define SK_DPT_TIMER_CTRL 0x0e08 /* Timer Control 16 bits */ 1000 #define SK_DPT_TCTL_STOP 0x0001 /* Stop Timer */ 1001 #define SK_DPT_TCTL_START 0x0002 /* Start Timer */ 1002 1003 #define SK_DPT_TIMER_TEST 0x0e0a /* Timer Test 16 bits */ 1004 #define SK_DPT_TTEST_STEP 0x0001 /* Timer Decrement */ 1005 #define SK_DPT_TTEST_OFF 0x0002 /* Test Mode Off */ 1006 #define SK_DPT_TTEST_ON 0x0004 /* Test Mode On */ 1007 1008 /* Block 29 -- reserved */ 1009 1010 /* Block 30 -- GMAC/GPHY Control Registers (Yukon Only)*/ 1011 #define SK_GMAC_CTRL 0x0f00 /* GMAC Control Register */ 1012 #define SK_GPHY_CTRL 0x0f04 /* GPHY Control Register */ 1013 #define SK_GMAC_ISR 0x0f08 /* GMAC Interrupt Source Register */ 1014 #define SK_GMAC_IMR 0x0f08 /* GMAC Interrupt Mask Register */ 1015 #define SK_LINK_CTRL 0x0f10 /* Link Control Register (LCR) */ 1016 #define SK_WOL_CTRL 0x0f20 /* Wake on LAN Control Register */ 1017 #define SK_MAC_ADDR_LOW 0x0f24 /* Mack Address Registers LOW */ 1018 #define SK_MAC_ADDR_HIGH 0x0f28 /* Mack Address Registers HIGH */ 1019 #define SK_PAT_READ_PTR 0x0f2c /* Pattern Read Pointer Register */ 1020 #define SK_PAT_LEN_REG0 0x0f30 /* Pattern Length Register 0 */ 1021 #define SK_PAT_LEN0 0x0f30 /* Pattern Length 0 */ 1022 #define SK_PAT_LEN1 0x0f31 /* Pattern Length 1 */ 1023 #define SK_PAT_LEN2 0x0f32 /* Pattern Length 2 */ 1024 #define SK_PAT_LEN3 0x0f33 /* Pattern Length 3 */ 1025 #define SK_PAT_LEN_REG1 0x0f34 /* Pattern Length Register 1 */ 1026 #define SK_PAT_LEN4 0x0f34 /* Pattern Length 4 */ 1027 #define SK_PAT_LEN5 0x0f35 /* Pattern Length 5 */ 1028 #define SK_PAT_LEN6 0x0f36 /* Pattern Length 6 */ 1029 #define SK_PAT_LEN7 0x0f37 /* Pattern Length 7 */ 1030 #define SK_PAT_CTR_REG0 0x0f38 /* Pattern Counter Register 0 */ 1031 #define SK_PAT_CTR0 0x0f38 /* Pattern Counter 0 */ 1032 #define SK_PAT_CTR1 0x0f39 /* Pattern Counter 1 */ 1033 #define SK_PAT_CTR2 0x0f3a /* Pattern Counter 2 */ 1034 #define SK_PAT_CTR3 0x0f3b /* Pattern Counter 3 */ 1035 #define SK_PAT_CTR_REG1 0x0f3c /* Pattern Counter Register 1 */ 1036 #define SK_PAT_CTR4 0x0f3c /* Pattern Counter 4 */ 1037 #define SK_PAT_CTR5 0x0f3d /* Pattern Counter 5 */ 1038 #define SK_PAT_CTR6 0x0f3e /* Pattern Counter 6 */ 1039 #define SK_PAT_CTR7 0x0f3f /* Pattern Counter 7 */ 1040 1041 #define SK_GMAC_LOOP_ON 0x00000020 /* Loopback mode for testing */ 1042 #define SK_GMAC_LOOP_OFF 0x00000010 /* purposes */ 1043 #define SK_GMAC_PAUSE_ON 0x00000008 /* enable forward of pause */ 1044 #define SK_GMAC_PAUSE_OFF 0x00000004 /* signal to GMAC */ 1045 #define SK_GMAC_RESET_CLEAR 0x00000002 /* Clear GMAC Reset */ 1046 #define SK_GMAC_RESET_SET 0x00000001 /* Set GMAC Reset */ 1047 1048 #define SK_GPHY_SEL_BDT 0x10000000 /* Select Bidirectional xfer */ 1049 #define SK_GPHY_INT_POL_HI 0x08000000 /* IRQ Polarity Active */ 1050 #define SK_GPHY_75_OHM 0x04000000 /* Use 75 Ohm Termination */ 1051 #define SK_GPHY_DIS_FC 0x02000000 /* Disable Auto Fiber/Copper */ 1052 #define SK_GPHY_DIS_SLEEP 0x01000000 /* Disable Energy Detect */ 1053 #define SK_GPHY_HWCFG_M_3 0x00800000 /* HWCFG_MODE[3] */ 1054 #define SK_GPHY_HWCFG_M_2 0x00400000 /* HWCFG_MODE[2] */ 1055 #define SK_GPHY_HWCFG_M_1 0x00200000 /* HWCFG_MODE[1] */ 1056 #define SK_GPHY_HWCFG_M_0 0x00100000 /* HWCFG_MODE[0] */ 1057 #define SK_GPHY_ANEG_0 0x00080000 /* ANEG[0] */ 1058 #define SK_GPHY_ENA_XC 0x00040000 /* Enable MDI Crossover */ 1059 #define SK_GPHY_DIS_125 0x00020000 /* Disable 125MHz Clock */ 1060 #define SK_GPHY_ANEG_3 0x00010000 /* ANEG[3] */ 1061 #define SK_GPHY_ANEG_2 0x00008000 /* ANEG[2] */ 1062 #define SK_GPHY_ANEG_1 0x00004000 /* ANEG[1] */ 1063 #define SK_GPHY_ENA_PAUSE 0x00002000 /* Enable Pause */ 1064 #define SK_GPHY_PHYADDR_4 0x00001000 /* Bit 4 of Phy Addr */ 1065 #define SK_GPHY_PHYADDR_3 0x00000800 /* Bit 3 of Phy Addr */ 1066 #define SK_GPHY_PHYADDR_2 0x00000400 /* Bit 2 of Phy Addr */ 1067 #define SK_GPHY_PHYADDR_1 0x00000200 /* Bit 1 of Phy Addr */ 1068 #define SK_GPHY_PHYADDR_0 0x00000100 /* Bit 0 of Phy Addr */ 1069 #define SK_GPHY_RESET_CLEAR 0x00000002 /* Clear GPHY Reset */ 1070 #define SK_GPHY_RESET_SET 0x00000001 /* Set GPHY Reset */ 1071 1072 #define SK_GPHY_COPPER (SK_GPHY_HWCFG_M_0 | SK_GPHY_HWCFG_M_1 | \ 1073 SK_GPHY_HWCFG_M_2 | SK_GPHY_HWCFG_M_3 ) 1074 #define SK_GPHY_FIBER (SK_GPHY_HWCFG_M_0 | SK_GPHY_HWCFG_M_1 | \ 1075 SK_GPHY_HWCFG_M_2 ) 1076 #define SK_GPHY_ANEG_ALL (SK_GPHY_ANEG_0 | SK_GPHY_ANEG_1 | \ 1077 SK_GPHY_ANEG_2 | SK_GPHY_ANEG_3 ) 1078 1079 #define SK_GMAC_INT_TX_OFLOW 0x20 /* Transmit Counter Overflow */ 1080 #define SK_GMAC_INT_RX_OFLOW 0x10 /* Receiver Overflow */ 1081 #define SK_GMAC_INT_TX_UNDER 0x08 /* Transmit FIFO Underrun */ 1082 #define SK_GMAC_INT_TX_DONE 0x04 /* Transmit Complete */ 1083 #define SK_GMAC_INT_RX_OVER 0x02 /* Receive FIFO Overrun */ 1084 #define SK_GMAC_INT_RX_DONE 0x01 /* Receive Complete */ 1085 1086 #define SK_LINK_RESET_CLEAR 0x0002 /* Link Reset Clear */ 1087 #define SK_LINK_RESET_SET 0x0001 /* Link Reset Set */ 1088 1089 /* Block 31 -- reserved */ 1090 1091 /* Block 32-33 -- Pattern Ram */ 1092 #define SK_WOL_PRAM 0x1000 1093 1094 /* Block 0x22 - 0x3f -- reserved */ 1095 1096 /* Block 0x40 to 0x4F -- XMAC 1 registers */ 1097 #define SK_XMAC1_BASE 0x2000 1098 1099 /* Block 0x50 to 0x5F -- MARV 1 registers */ 1100 #define SK_MARV1_BASE 0x2800 1101 1102 /* Block 0x60 to 0x6F -- XMAC 2 registers */ 1103 #define SK_XMAC2_BASE 0x3000 1104 1105 /* Block 0x70 to 0x7F -- MARV 2 registers */ 1106 #define SK_MARV2_BASE 0x3800 1107 1108 /* Compute relative offset of an XMAC register in the XMAC window(s). */ 1109 #define SK_XMAC_REG(sc, reg) (((reg) * 2) + SK_XMAC1_BASE + \ 1110 (((sc)->sk_port) * (SK_XMAC2_BASE - SK_XMAC1_BASE))) 1111 1112 #if 0 1113 #define SK_XM_READ_4(sc, reg) \ 1114 ((sk_win_read_2(sc->sk_softc, \ 1115 SK_XMAC_REG(sc, reg)) & 0xFFFF) | \ 1116 ((sk_win_read_2(sc->sk_softc, \ 1117 SK_XMAC_REG(sc, reg + 2)) & 0xFFFF) << 16)) 1118 1119 #define SK_XM_WRITE_4(sc, reg, val) \ 1120 sk_win_write_2(sc->sk_softc, SK_XMAC_REG(sc, reg), \ 1121 ((val) & 0xFFFF)); \ 1122 sk_win_write_2(sc->sk_softc, SK_XMAC_REG(sc, reg + 2), \ 1123 ((val) >> 16) & 0xFFFF) 1124 #else 1125 #define SK_XM_READ_4(sc, reg) \ 1126 sk_win_read_4(sc->sk_softc, SK_XMAC_REG(sc, reg)) 1127 1128 #define SK_XM_WRITE_4(sc, reg, val) \ 1129 sk_win_write_4(sc->sk_softc, SK_XMAC_REG(sc, reg), (val)) 1130 #endif 1131 1132 #define SK_XM_READ_2(sc, reg) \ 1133 sk_win_read_2(sc->sk_softc, SK_XMAC_REG(sc, reg)) 1134 1135 #define SK_XM_WRITE_2(sc, reg, val) \ 1136 sk_win_write_2(sc->sk_softc, SK_XMAC_REG(sc, reg), val) 1137 1138 #define SK_XM_SETBIT_4(sc, reg, x) \ 1139 SK_XM_WRITE_4(sc, reg, (SK_XM_READ_4(sc, reg)) | (x)) 1140 1141 #define SK_XM_CLRBIT_4(sc, reg, x) \ 1142 SK_XM_WRITE_4(sc, reg, (SK_XM_READ_4(sc, reg)) & ~(x)) 1143 1144 #define SK_XM_SETBIT_2(sc, reg, x) \ 1145 SK_XM_WRITE_2(sc, reg, (SK_XM_READ_2(sc, reg)) | (x)) 1146 1147 #define SK_XM_CLRBIT_2(sc, reg, x) \ 1148 SK_XM_WRITE_2(sc, reg, (SK_XM_READ_2(sc, reg)) & ~(x)) 1149 1150 /* Compute relative offset of an MARV register in the MARV window(s). */ 1151 #define SK_YU_REG(sc, reg) \ 1152 ((reg) + SK_MARV1_BASE + \ 1153 (((sc)->sk_port) * (SK_MARV2_BASE - SK_MARV1_BASE))) 1154 1155 #define SK_YU_READ_4(sc, reg) \ 1156 sk_win_read_4((sc)->sk_softc, SK_YU_REG((sc), (reg))) 1157 1158 #define SK_YU_READ_2(sc, reg) \ 1159 sk_win_read_2((sc)->sk_softc, SK_YU_REG((sc), (reg))) 1160 1161 #define SK_YU_WRITE_4(sc, reg, val) \ 1162 sk_win_write_4((sc)->sk_softc, SK_YU_REG((sc), (reg)), (val)) 1163 1164 #define SK_YU_WRITE_2(sc, reg, val) \ 1165 sk_win_write_2((sc)->sk_softc, SK_YU_REG((sc), (reg)), (val)) 1166 1167 #define SK_YU_SETBIT_4(sc, reg, x) \ 1168 SK_YU_WRITE_4(sc, reg, (SK_YU_READ_4(sc, reg)) | (x)) 1169 1170 #define SK_YU_CLRBIT_4(sc, reg, x) \ 1171 SK_YU_WRITE_4(sc, reg, (SK_YU_READ_4(sc, reg)) & ~(x)) 1172 1173 #define SK_YU_SETBIT_2(sc, reg, x) \ 1174 SK_YU_WRITE_2(sc, reg, (SK_YU_READ_2(sc, reg)) | (x)) 1175 1176 #define SK_YU_CLRBIT_2(sc, reg, x) \ 1177 SK_YU_WRITE_2(sc, reg, (SK_YU_READ_2(sc, reg)) & ~(x)) 1178 1179 /* 1180 * The default FIFO threshold on the XMAC II is 4 bytes. On 1181 * dual port NICs, this often leads to transmit underruns, so we 1182 * bump the threshold a little. 1183 */ 1184 #define SK_XM_TX_FIFOTHRESH 512 1185 1186 #define SK_PCI_VENDOR_ID 0x0000 1187 #define SK_PCI_DEVICE_ID 0x0002 1188 #define SK_PCI_COMMAND 0x0004 1189 #define SK_PCI_STATUS 0x0006 1190 #define SK_PCI_REVID 0x0008 1191 #define SK_PCI_CLASSCODE 0x0009 1192 #define SK_PCI_CACHELEN 0x000C 1193 #define SK_PCI_LATENCY_TIMER 0x000D 1194 #define SK_PCI_HEADER_TYPE 0x000E 1195 #define SK_PCI_LOMEM 0x0010 1196 #define SK_PCI_LOIO 0x0014 1197 #define SK_PCI_SUBVEN_ID 0x002C 1198 #define SK_PCI_SYBSYS_ID 0x002E 1199 #define SK_PCI_BIOSROM 0x0030 1200 #define SK_PCI_INTLINE 0x003C 1201 #define SK_PCI_INTPIN 0x003D 1202 #define SK_PCI_MINGNT 0x003E 1203 #define SK_PCI_MINLAT 0x003F 1204 1205 /* device specific PCI registers */ 1206 #define SK_PCI_OURREG1 0x0040 1207 #define SK_PCI_OURREG2 0x0044 1208 #define SK_PCI_CAPID 0x0048 /* 8 bits */ 1209 #define SK_PCI_NEXTPTR 0x0049 /* 8 bits */ 1210 #define SK_PCI_PWRMGMTCAP 0x004A /* 16 bits */ 1211 #define SK_PCI_PWRMGMTCTRL 0x004C /* 16 bits */ 1212 #define SK_PCI_PME_EVENT 0x004F 1213 #define SK_PCI_VPD_CAPID 0x0050 1214 #define SK_PCI_VPD_NEXTPTR 0x0051 1215 #define SK_PCI_VPD_ADDR 0x0052 1216 #define SK_PCI_VPD_DATA 0x0054 1217 1218 #define SK_PSTATE_MASK 0x0003 1219 #define SK_PSTATE_D0 0x0000 1220 #define SK_PSTATE_D1 0x0001 1221 #define SK_PSTATE_D2 0x0002 1222 #define SK_PSTATE_D3 0x0003 1223 #define SK_PME_EN 0x0010 1224 #define SK_PME_STATUS 0x8000 1225 1226 /* 1227 * VPD flag bit. Set to 0 to initiate a read, will become 1 when 1228 * read is complete. Set to 1 to initiate a write, will become 0 1229 * when write is finished. 1230 */ 1231 #define SK_VPD_FLAG 0x8000 1232 1233 /* VPD structures */ 1234 struct vpd_res { 1235 u_int8_t vr_id; 1236 u_int8_t vr_len; 1237 u_int8_t vr_pad; 1238 }; 1239 1240 struct vpd_key { 1241 char vk_key[2]; 1242 u_int8_t vk_len; 1243 }; 1244 1245 #define VPD_RES_ID 0x82 /* ID string */ 1246 #define VPD_RES_READ 0x90 /* start of read only area */ 1247 #define VPD_RES_WRITE 0x81 /* start of read/write area */ 1248 #define VPD_RES_END 0x78 /* end tag */ 1249 1250 #define CSR_WRITE_4(sc, reg, val) \ 1251 bus_space_write_4((sc)->sk_btag, (sc)->sk_bhandle, (reg), (val)) 1252 #define CSR_WRITE_2(sc, reg, val) \ 1253 bus_space_write_2((sc)->sk_btag, (sc)->sk_bhandle, (reg), (val)) 1254 #define CSR_WRITE_1(sc, reg, val) \ 1255 bus_space_write_1((sc)->sk_btag, (sc)->sk_bhandle, (reg), (val)) 1256 1257 #define CSR_READ_4(sc, reg) \ 1258 bus_space_read_4((sc)->sk_btag, (sc)->sk_bhandle, (reg)) 1259 #define CSR_READ_2(sc, reg) \ 1260 bus_space_read_2((sc)->sk_btag, (sc)->sk_bhandle, (reg)) 1261 #define CSR_READ_1(sc, reg) \ 1262 bus_space_read_1((sc)->sk_btag, (sc)->sk_bhandle, (reg)) 1263 1264 struct sk_type { 1265 u_int16_t sk_vid; 1266 u_int16_t sk_did; 1267 char *sk_name; 1268 }; 1269 1270 /* RX queue descriptor data structure */ 1271 struct sk_rx_desc { 1272 u_int32_t sk_ctl; 1273 u_int32_t sk_next; 1274 u_int32_t sk_data_lo; 1275 u_int32_t sk_data_hi; 1276 u_int32_t sk_xmac_rxstat; 1277 u_int32_t sk_timestamp; 1278 u_int16_t sk_csum2; 1279 u_int16_t sk_csum1; 1280 u_int16_t sk_csum2_start; 1281 u_int16_t sk_csum1_start; 1282 }; 1283 1284 #define SK_OPCODE_DEFAULT 0x00550000 1285 #define SK_OPCODE_CSUM 0x00560000 1286 1287 #define SK_RXCTL_LEN 0x0000FFFF 1288 #define SK_RXCTL_OPCODE 0x00FF0000 1289 #define SK_RXCTL_TSTAMP_VALID 0x01000000 1290 #define SK_RXCTL_STATUS_VALID 0x02000000 1291 #define SK_RXCTL_DEV0 0x04000000 1292 #define SK_RXCTL_EOF_INTR 0x08000000 1293 #define SK_RXCTL_EOB_INTR 0x10000000 1294 #define SK_RXCTL_LASTFRAG 0x20000000 1295 #define SK_RXCTL_FIRSTFRAG 0x40000000 1296 #define SK_RXCTL_OWN 0x80000000 1297 1298 #define SK_RXSTAT \ 1299 (SK_OPCODE_DEFAULT|SK_RXCTL_EOF_INTR|SK_RXCTL_LASTFRAG| \ 1300 SK_RXCTL_FIRSTFRAG|SK_RXCTL_OWN) 1301 1302 struct sk_tx_desc { 1303 u_int32_t sk_ctl; 1304 u_int32_t sk_next; 1305 u_int32_t sk_data_lo; 1306 u_int32_t sk_data_hi; 1307 u_int32_t sk_xmac_txstat; 1308 u_int16_t sk_rsvd0; 1309 u_int16_t sk_csum_startval; 1310 u_int16_t sk_csum_startpos; 1311 u_int16_t sk_csum_writepos; 1312 u_int32_t sk_rsvd1; 1313 }; 1314 1315 #define SK_TXCTL_LEN 0x0000FFFF 1316 #define SK_TXCTL_OPCODE 0x00FF0000 1317 #define SK_TXCTL_SW 0x01000000 1318 #define SK_TXCTL_NOCRC 0x02000000 1319 #define SK_TXCTL_STORENFWD 0x04000000 1320 #define SK_TXCTL_EOF_INTR 0x08000000 1321 #define SK_TXCTL_EOB_INTR 0x10000000 1322 #define SK_TXCTL_LASTFRAG 0x20000000 1323 #define SK_TXCTL_FIRSTFRAG 0x40000000 1324 #define SK_TXCTL_OWN 0x80000000 1325 1326 #define SK_TXSTAT \ 1327 (SK_OPCODE_DEFAULT|SK_TXCTL_EOF_INTR|SK_TXCTL_LASTFRAG|SK_TXCTL_OWN) 1328 1329 #define SK_RXBYTES(x) (x) & 0x0000FFFF; 1330 #define SK_TXBYTES SK_RXBYTES 1331 1332 #define SK_TX_RING_CNT 512 1333 #define SK_RX_RING_CNT 256 1334 1335 /* 1336 * Jumbo buffer stuff. Note that we must allocate more jumbo 1337 * buffers than there are descriptors in the receive ring. This 1338 * is because we don't know how long it will take for a packet 1339 * to be released after we hand it off to the upper protocol 1340 * layers. To be safe, we allocate 1.5 times the number of 1341 * receive descriptors. 1342 */ 1343 #define SK_JUMBO_FRAMELEN 9018 1344 #define SK_JUMBO_MTU (SK_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN) 1345 #define SK_JSLOTS 384 1346 1347 #define SK_JRAWLEN (SK_JUMBO_FRAMELEN + ETHER_ALIGN + sizeof(u_int64_t)) 1348 #define SK_JLEN (SK_JRAWLEN + (sizeof(u_int64_t) - \ 1349 (SK_JRAWLEN % sizeof(u_int64_t)))) 1350 #define SK_MCLBYTES (SK_JLEN - sizeof(u_int64_t)) 1351 #define SK_JPAGESZ PAGE_SIZE 1352 #define SK_RESID (SK_JPAGESZ - (SK_JLEN * SK_JSLOTS) % SK_JPAGESZ) 1353 #define SK_JMEM ((SK_JLEN * SK_JSLOTS) + SK_RESID) 1354 1355 struct sk_jslot { 1356 caddr_t sk_buf; 1357 int sk_inuse; 1358 }; 1359 1360 struct sk_jpool_entry { 1361 int slot; 1362 SLIST_ENTRY(sk_jpool_entry) jpool_entries; 1363 }; 1364 1365 struct sk_chain { 1366 void *sk_desc; 1367 struct mbuf *sk_mbuf; 1368 struct sk_chain *sk_next; 1369 }; 1370 1371 struct sk_chain_data { 1372 struct sk_chain sk_tx_chain[SK_TX_RING_CNT]; 1373 struct sk_chain sk_rx_chain[SK_RX_RING_CNT]; 1374 int sk_tx_prod; 1375 int sk_tx_cons; 1376 int sk_tx_cnt; 1377 int sk_rx_prod; 1378 int sk_rx_cons; 1379 int sk_rx_cnt; 1380 /* Stick the jumbo mem management stuff here too. */ 1381 struct sk_jslot sk_jslots[SK_JSLOTS]; 1382 void *sk_jumbo_buf; 1383 1384 }; 1385 1386 struct sk_ring_data { 1387 struct sk_tx_desc sk_tx_ring[SK_TX_RING_CNT]; 1388 struct sk_rx_desc sk_rx_ring[SK_RX_RING_CNT]; 1389 }; 1390 1391 struct sk_bcom_hack { 1392 int reg; 1393 int val; 1394 }; 1395 1396 #define SK_INC(x, y) (x) = (x + 1) % y 1397 1398 /* Forward decl. */ 1399 struct sk_if_softc; 1400 1401 /* Softc for the GEnesis controller. */ 1402 struct sk_softc { 1403 bus_space_handle_t sk_bhandle; /* bus space handle */ 1404 bus_space_tag_t sk_btag; /* bus space tag */ 1405 void *sk_intrhand; /* irq handler handle */ 1406 struct resource *sk_irq; /* IRQ resource handle */ 1407 struct resource *sk_res; /* I/O or shared mem handle */ 1408 u_int8_t sk_unit; /* controller number */ 1409 u_int8_t sk_type; 1410 char *sk_vpd_prodname; 1411 char *sk_vpd_readonly; 1412 u_int32_t sk_rboff; /* RAMbuffer offset */ 1413 u_int32_t sk_ramsize; /* amount of RAM on NIC */ 1414 u_int32_t sk_pmd; /* physical media type */ 1415 u_int32_t sk_intrmask; 1416 struct sk_if_softc *sk_if[2]; 1417 device_t sk_devs[2]; 1418 }; 1419 1420 /* Softc for each logical interface */ 1421 struct sk_if_softc { 1422 struct arpcom arpcom; /* interface info */ 1423 device_t sk_miibus; 1424 u_int8_t sk_unit; /* interface number */ 1425 u_int8_t sk_port; /* port # on controller */ 1426 u_int8_t sk_xmac_rev; /* XMAC chip rev (B2 or C1) */ 1427 u_int32_t sk_rx_ramstart; 1428 u_int32_t sk_rx_ramend; 1429 u_int32_t sk_tx_ramstart; 1430 u_int32_t sk_tx_ramend; 1431 int sk_phytype; 1432 int sk_phyaddr; 1433 device_t sk_dev; 1434 int sk_cnt; 1435 int sk_link; 1436 struct callout_handle sk_tick_ch; 1437 struct sk_chain_data sk_cdata; 1438 struct sk_ring_data *sk_rdata; 1439 struct sk_softc *sk_softc; /* parent controller */ 1440 int sk_tx_bmu; /* TX BMU register */ 1441 int sk_if_flags; 1442 SLIST_HEAD(__sk_jfreehead, sk_jpool_entry) sk_jfree_listhead; 1443 SLIST_HEAD(__sk_jinusehead, sk_jpool_entry) sk_jinuse_listhead; 1444 }; 1445 1446 #define SK_MAXUNIT 256 1447 #define SK_TIMEOUT 1000 1448 #define ETHER_ALIGN 2 1449 1450 #ifdef __alpha__ 1451 #undef vtophys 1452 #define vtophys(va) alpha_XXX_dmamap((vm_offset_t)va) 1453 #endif 1454