1 /* 2 * Copyright (c) 2008 The DragonFly Project. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in 12 * the documentation and/or other materials provided with the 13 * distribution. 14 * 3. Neither the name of The DragonFly Project nor the names of its 15 * contributors may be used to endorse or promote products derived 16 * from this software without specific, prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 19 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 20 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 21 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 22 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 23 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING, 24 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 26 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 27 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 28 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 * 31 * $FreeBSD-4.7: /usr/src/sys/pci/silan.c,v 1.0 2003/01/10 gaoyonghong $ 32 */ 33 34 #include <sys/param.h> 35 #include <sys/bus.h> 36 #include <sys/endian.h> 37 #include <sys/kernel.h> 38 #include <sys/interrupt.h> 39 #include <sys/malloc.h> 40 #include <sys/mbuf.h> 41 #include <sys/resource.h> 42 #include <sys/rman.h> 43 #include <sys/socket.h> 44 #include <sys/sockio.h> 45 #include <sys/systm.h> 46 47 #include <bus/pci/pcidevs.h> 48 #include <bus/pci/pcireg.h> 49 #include <bus/pci/pcivar.h> 50 51 #include <machine/clock.h> 52 53 #include <net/bpf.h> 54 #include <net/ethernet.h> 55 #include <net/ifq_var.h> 56 #include <net/if.h> 57 #include <net/if_arp.h> 58 #include <net/if_dl.h> 59 #include <net/if_media.h> 60 #include <net/if_var.h> 61 62 #include <vm/pmap.h> 63 #include <vm/vm.h> 64 65 #include "if_slnreg.h" 66 #include "if_slnvar.h" 67 68 /* Default to using PIO access for netcard driver */ 69 #define SL_USEIOSPACE 70 71 #ifdef SLN_DEBUG 72 #define PDEBUG(fmt, args...) kprintf("%s: " fmt "\n" , __func__ , ## args) 73 #else 74 #define PDEBUG(fmt, args...) 75 #endif 76 77 static const struct sln_dev { 78 uint16_t vid; 79 uint16_t did; 80 const char *desc; 81 } sln_devs[] = { 82 {PCI_VENDOR_SILAN, PCI_PRODUCT_SILAN_SC92031, 83 "Silan SC92031 Fast Ethernet" }, 84 {PCI_VENDOR_SILAN, PCI_PRODUCT_SILAN_8139D, 85 "Silan Rsltek 8139D Fast Ethernet" }, 86 {0, 0, NULL} 87 }; 88 89 static int sln_probe(device_t); 90 static int sln_attach(device_t); 91 static int sln_detach(device_t); 92 static int sln_shutdown(device_t); 93 static int sln_suspend(device_t); 94 static int sln_resume(device_t); 95 96 static void sln_reset(struct sln_softc *); 97 static void sln_init(void *); 98 99 static void sln_tx(struct ifnet *); 100 static void sln_rx(struct sln_softc *); 101 static void sln_tx_intr(struct sln_softc *); 102 static void sln_media_intr(struct sln_softc *); 103 static void sln_interrupt(void *); 104 static int sln_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *); 105 static void sln_stop(struct sln_softc *); 106 static void sln_watchdog(struct ifnet *); 107 108 static int sln_media_upd(struct ifnet *); 109 110 static void sln_media_stat(struct ifnet *, struct ifmediareq *); 111 static void sln_mii_cmd(struct sln_softc *, uint32_t, u_long *); 112 static void sln_media_cfg(struct sln_softc *); 113 static void sln_mac_cfg(struct sln_softc *); 114 static uint32_t sln_ether_crc32(caddr_t); 115 static void sln_set_multi(struct sln_softc *); 116 static void sln_init_tx(struct sln_softc *); 117 static void sln_tick(void *); 118 119 #ifdef SL_USEIOSPACE 120 #define SL_RID SL_PCI_IOAD 121 #define SL_RES SYS_RES_IOPORT 122 #else 123 #define SL_RID SL_PCI_MEMAD 124 #define SL_RES SYS_RES_MEMORY 125 #endif 126 127 static device_method_t sln_methods[] = { 128 DEVMETHOD(device_probe, sln_probe), 129 DEVMETHOD(device_attach, sln_attach), 130 DEVMETHOD(device_detach, sln_detach), 131 DEVMETHOD(device_shutdown, sln_shutdown), 132 DEVMETHOD(device_suspend, sln_suspend), 133 DEVMETHOD(device_resume, sln_resume), 134 135 DEVMETHOD(bus_print_child, bus_generic_print_child), 136 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 137 138 {0, 0} 139 }; 140 141 static driver_t sln_driver = { 142 "sln", 143 sln_methods, 144 sizeof(struct sln_softc) 145 }; 146 147 static devclass_t sln_devclass; 148 149 DRIVER_MODULE(sln, pci, sln_driver, sln_devclass, NULL, NULL); 150 151 static int 152 sln_probe(struct device *dev) 153 { 154 const struct sln_dev *d; 155 uint16_t did, vid; 156 157 vid = pci_get_vendor(dev); 158 did = pci_get_device(dev); 159 160 for (d = sln_devs; d->desc != NULL; d++) { 161 if (vid == d->vid && did == d->did) { 162 device_set_desc(dev, d->desc); 163 return 0; 164 } 165 } 166 return ENXIO; 167 } 168 169 /* the chip reset */ 170 static void 171 sln_reset(struct sln_softc *sc) 172 { 173 SLN_WRITE_4(sc, SL_CFG0, SL_SOFT_RESET); 174 DELAY(200000); 175 SLN_WRITE_4(sc, SL_CFG0, 0x0); 176 DELAY(10000); 177 } 178 179 /* Attach the interface. Allocate softc structures */ 180 static int 181 sln_attach(device_t dev) 182 { 183 struct sln_softc *sc = device_get_softc(dev); 184 struct ifnet *ifp = &sc->arpcom.ac_if; 185 unsigned char eaddr[ETHER_ADDR_LEN]; 186 int rid; 187 int error = 0; 188 189 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 190 191 /* TODO: power state change */ 192 193 pci_enable_busmaster(dev); 194 195 rid = SL_RID; 196 sc->sln_res = bus_alloc_resource_any(dev, SL_RES, &rid, RF_ACTIVE); 197 if (sc->sln_res == NULL) { 198 device_printf(dev, "couldn't map ports/memory\n"); 199 error = ENXIO; 200 goto fail; 201 } 202 sc->sln_bustag = rman_get_bustag(sc->sln_res); 203 sc->sln_bushandle = rman_get_bushandle(sc->sln_res); 204 205 /* alloc pci irq */ 206 rid = 0; 207 sc->sln_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 208 RF_SHAREABLE | RF_ACTIVE); 209 if (sc->sln_irq == NULL) { 210 device_printf(dev, "couldn't map interrupt\n"); 211 bus_release_resource(dev, SL_RES, SL_RID, sc->sln_res); 212 error = ENXIO; 213 goto fail; 214 } 215 216 /* Get MAC address */ 217 ((uint32_t *)(&eaddr))[0] = be32toh(SLN_READ_4(sc, SL_MAC_ADDR0)); 218 ((uint16_t *)(&eaddr))[2] = be16toh(SLN_READ_4(sc, SL_MAC_ADDR1)); 219 220 /* alloc rx buffer space */ 221 sc->sln_bufdata.sln_rx_buf = contigmalloc(SL_RX_BUFLEN, 222 M_DEVBUF, M_WAITOK, 0, 0xffffffff, PAGE_SIZE, 0); 223 if (sc->sln_bufdata.sln_rx_buf == NULL) { 224 device_printf(dev, "no memory for rx buffers!\n"); 225 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sln_irq); 226 bus_release_resource(dev, SL_RES, SL_RID, sc->sln_res); 227 error = ENXIO; 228 goto fail; 229 } 230 callout_init(&sc->sln_state); 231 232 ifp->if_softc = sc; 233 ifp->if_mtu = ETHERMTU; 234 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 235 ifp->if_init = sln_init; 236 ifp->if_start = sln_tx; 237 ifp->if_ioctl = sln_ioctl; 238 ifp->if_watchdog = sln_watchdog; 239 ifq_set_maxlen(&ifp->if_snd, IFQ_MAXLEN); 240 ifq_set_ready(&ifp->if_snd); 241 242 /* initial media */ 243 ifmedia_init(&sc->ifmedia, 0, sln_media_upd, sln_media_stat); 244 245 /* supported media types */ 246 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL); 247 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_10_T, 0, NULL); 248 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_10_T | IFM_HDX, 0, NULL); 249 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_10_T | IFM_FDX, 0, NULL); 250 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_100_TX, 0, NULL); 251 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_100_TX | IFM_HDX, 0, NULL); 252 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_100_TX | IFM_FDX, 0, NULL); 253 254 /* Choose a default media. */ 255 ifmedia_set(&sc->ifmedia, IFM_ETHER | IFM_AUTO); 256 257 ether_ifattach(ifp, eaddr, NULL); 258 259 error = bus_setup_intr(dev, sc->sln_irq, INTR_MPSAFE, sln_interrupt, sc, 260 &sc->sln_intrhand, ifp->if_serializer); 261 if (error) { 262 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sln_irq); 263 bus_release_resource(dev, SL_RES, SL_RID, sc->sln_res); 264 ether_ifdetach(ifp); 265 device_printf(dev, "couldn't set up irq\n"); 266 goto fail; 267 } 268 269 ifp->if_cpuid = rman_get_cpuid(sc->sln_irq); 270 KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus); 271 272 return 0; 273 fail: 274 return error; 275 } 276 277 /* Stop the adapter and free any mbufs allocated to the RX and TX buffers */ 278 static void 279 sln_stop(struct sln_softc *sc) 280 { 281 struct ifnet *ifp = &sc->arpcom.ac_if; 282 uint32_t intr_status; 283 int i; 284 285 ASSERT_SERIALIZED(ifp->if_serializer); 286 287 ifp->if_timer = 0; 288 callout_stop(&sc->sln_state); 289 290 /* disable Tx/Rx */ 291 sc->txcfg &= ~SL_TXCFG_EN; 292 sc->rxcfg &= ~SL_RXCFG_EN; 293 SLN_WRITE_4(sc, SL_TX_CONFIG, sc->txcfg); 294 SLN_WRITE_4(sc, SL_RX_CONFIG, sc->rxcfg); 295 296 /* Clear interrupt */ 297 SLN_WRITE_4(sc, SL_INT_MASK, 0); 298 intr_status = SLN_READ_4(sc, SL_INT_STATUS); 299 300 /* Free the TX list buffers */ 301 for (i = 0; i < SL_TXD_CNT; i++) { 302 if (sc->sln_bufdata.sln_tx_buf[i] != NULL) { 303 m_freem(sc->sln_bufdata.sln_tx_buf[i]); 304 sc->sln_bufdata.sln_tx_buf[i] = NULL; 305 SLN_WRITE_4(sc, SL_TSAD0 + i * 4, 0); 306 } 307 } 308 309 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 310 } 311 312 static int 313 sln_detach(device_t dev) 314 { 315 struct sln_softc *sc = device_get_softc(dev); 316 struct ifnet *ifp = &sc->arpcom.ac_if; 317 318 lwkt_serialize_enter(ifp->if_serializer); 319 sln_stop(sc); 320 bus_teardown_intr(dev, sc->sln_irq, sc->sln_intrhand); 321 lwkt_serialize_exit(ifp->if_serializer); 322 323 ether_ifdetach(ifp); 324 325 bus_generic_detach(dev); 326 327 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sln_irq); 328 bus_release_resource(dev, SL_RES, SL_RID, sc->sln_res); 329 330 contigfree(sc->sln_bufdata.sln_rx_buf, SL_RX_BUFLEN, M_DEVBUF); 331 332 return 0; 333 } 334 335 static int 336 sln_media_upd(struct ifnet *ifp) 337 { 338 struct sln_softc *sc = ifp->if_softc; 339 struct ifmedia *ifm = &sc->ifmedia; 340 341 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 342 return EINVAL; 343 344 if (ifp->if_flags & IFF_UP) 345 sln_init(sc); 346 347 return 0; 348 } 349 350 static void 351 sln_media_stat(struct ifnet *ifp, struct ifmediareq *ifmr) 352 { 353 struct sln_softc *sc = ifp->if_softc; 354 u_long phys[2]; 355 uint32_t temp; 356 357 ifmr->ifm_status = IFM_AVALID; 358 ifmr->ifm_active = IFM_ETHER; 359 360 phys[0] = SL_MII_STAT; 361 sln_mii_cmd(sc, SL_MII0_READ, phys); 362 363 if (phys[1] & SL_MIISTAT_LINK) 364 ifmr->ifm_status |= IFM_ACTIVE; 365 366 temp = SLN_READ_4(sc, SL_PHY_CTRL); 367 368 if ((temp & (SL_PHYCTL_DUX | SL_PHYCTL_SPD100 | SL_PHYCTL_SPD10)) == 0x60800000) 369 ifmr->ifm_active |= IFM_AUTO; 370 else if ((temp & (SL_PHYCTL_DUX | SL_PHYCTL_SPD100)) == 0x40800000) 371 ifmr->ifm_active |= IFM_100_TX | IFM_FDX; 372 else if ((temp & SL_PHYCTL_SPD100) == 0x40000000) 373 ifmr->ifm_active |= IFM_100_TX | IFM_HDX; 374 else if ((temp & (SL_PHYCTL_DUX | SL_PHYCTL_SPD10)) == 0x20800000) 375 ifmr->ifm_active |= IFM_10_T | IFM_FDX; 376 else if ((temp & SL_PHYCTL_SPD10) == 0x20000000) 377 ifmr->ifm_active |= IFM_10_T | IFM_HDX; 378 379 sln_mii_cmd(sc, SL_MII0_SCAN, phys); 380 } 381 382 /* command selected in MII command register */ 383 static void 384 sln_mii_cmd(struct sln_softc *sc, uint32_t cmd, u_long *phys) 385 { 386 uint32_t mii_status; 387 388 SLN_WRITE_4(sc, SL_MII_CMD0, SL_MII0_DIVEDER); 389 390 do { 391 mii_status = 0; 392 DELAY(10); 393 mii_status = SLN_READ_4(sc, SL_MII_STATUS); 394 } while (mii_status & SL_MIISTAT_BUSY); 395 396 switch (cmd) { 397 case SL_MII0_SCAN: 398 SLN_WRITE_4(sc, SL_MII_CMD1, 0x1 << 6); 399 SLN_WRITE_4(sc, SL_MII_CMD0, SL_MII0_DIVEDER | SL_MII0_SCAN); 400 break; 401 402 case SL_MII0_READ: 403 SLN_WRITE_4(sc, SL_MII_CMD1, phys[0] << 6); 404 SLN_WRITE_4(sc, SL_MII_CMD0, SL_MII0_DIVEDER | SL_MII0_READ); 405 break; 406 407 default: /* WRITE */ 408 SLN_WRITE_4(sc, SL_MII_CMD1, phys[0] << 6 | phys[1] << 11); 409 SLN_WRITE_4(sc, SL_MII_CMD0, SL_MII0_DIVEDER | SL_MII0_WRITE); 410 break; 411 } 412 413 do { 414 DELAY(10); 415 mii_status = SLN_READ_4(sc, SL_MII_STATUS); 416 } while (mii_status & SL_MIISTAT_BUSY); 417 418 if (SL_MII0_READ == cmd) 419 phys[1] = (mii_status >> 13) & 0xffff; 420 } 421 422 /* Set media speed and duplex mode */ 423 static void 424 sln_media_cfg(struct sln_softc *sc) 425 { 426 u_long phys[2]; 427 uint32_t mediatype; 428 uint32_t temp; 429 430 mediatype = (&sc->ifmedia)->ifm_cur->ifm_media; 431 432 temp = SLN_READ_4(sc, SL_PHY_CTRL); 433 temp &= ~(SL_PHYCTL_DUX | SL_PHYCTL_SPD100 | SL_PHYCTL_SPD10); 434 temp |= (SL_PHYCTL_ANE | SL_PHYCTL_RESET); 435 436 /************************************************/ 437 /* currently set media word by selected media */ 438 /* */ 439 /* IFM_ETHER = 0x00000020 */ 440 /* IFM_AUTO=0, IFM_10_T=3, IFM_100_TX=6 */ 441 /* IFM_FDX=0x00100000 IFM_HDX=0x00200000 */ 442 /************************************************/ 443 switch (mediatype) { 444 case 0x00000020: 445 PDEBUG(" autoselet supported\n"); 446 temp |= (SL_PHYCTL_DUX | SL_PHYCTL_SPD100 | SL_PHYCTL_SPD10); 447 sc->ifmedia.ifm_media = IFM_ETHER | IFM_AUTO; 448 ifmedia_set(&sc->ifmedia, IFM_ETHER | IFM_AUTO); 449 break; 450 case 0x23: 451 case 0x00200023: 452 PDEBUG(" 10Mbps half_duplex supported\n"); 453 temp |= SL_PHYCTL_SPD10; 454 sc->ifmedia.ifm_media = IFM_ETHER | IFM_10_T | IFM_HDX; 455 ifmedia_set(&sc->ifmedia, IFM_ETHER | IFM_10_T | IFM_HDX); 456 break; 457 458 case 0x00100023: 459 PDEBUG("10Mbps full_duplex supported\n"); 460 temp |= (SL_PHYCTL_SPD10 | SL_PHYCTL_DUX); 461 sc->ifmedia.ifm_media = IFM_ETHER | IFM_10_T | IFM_FDX; 462 ifmedia_set(&sc->ifmedia, IFM_ETHER | IFM_10_T | IFM_FDX); 463 break; 464 465 case 0x26: 466 case 0x00200026: 467 PDEBUG("100Mbps half_duplex supported\n"); 468 temp |= SL_PHYCTL_SPD100; 469 sc->ifmedia.ifm_media = IFM_ETHER | IFM_100_TX | IFM_HDX; 470 ifmedia_set(&sc->ifmedia, IFM_ETHER | IFM_100_TX | IFM_HDX); 471 break; 472 473 case 0x00100026: 474 PDEBUG("100Mbps full_duplex supported\n"); 475 temp |= (SL_PHYCTL_SPD100 | SL_PHYCTL_DUX); 476 sc->ifmedia.ifm_media = IFM_ETHER | IFM_100_TX | IFM_FDX; 477 ifmedia_set(&sc->ifmedia, IFM_ETHER | IFM_100_TX | IFM_FDX); 478 break; 479 480 default: 481 break; 482 } 483 484 SLN_WRITE_4(sc, SL_PHY_CTRL, temp); 485 486 DELAY(10000); 487 temp &= ~SL_PHYCTL_RESET; 488 SLN_WRITE_4(sc, SL_PHY_CTRL, temp); 489 490 DELAY(1000); 491 phys[0] = SL_MII_JAB; 492 phys[1] = SL_PHY_16_JAB_ENB | SL_PHY_16_PORT_ENB; 493 sln_mii_cmd(sc, SL_MII0_WRITE, phys); 494 495 sc->connect = 0; 496 sln_mii_cmd(sc, SL_MII0_SCAN, phys); 497 } 498 499 static void 500 sln_mac_cfg(struct sln_softc *sc) 501 { 502 struct ifnet *ifp = &sc->arpcom.ac_if; 503 u_long flowcfg = 0; 504 505 /* Set the initial TX/RX/Flow Control configuration */ 506 sc->rxcfg = SL_RXCFG_LOW_THRESHOLD | SL_RXCFG_HIGH_THRESHOLD; 507 sc->txcfg = TX_CFG_DEFAULT; 508 509 if (sc->txenablepad) 510 sc->txcfg |= 0x20000000; 511 512 if (sc->media_speed == IFM_10_T) 513 sc->txcfg |= SL_TXCFG_DATARATE; 514 515 if (sc->media_duplex == IFM_FDX) { 516 sc->rxcfg |= SL_RXCFG_FULLDX; 517 sc->txcfg |= SL_TXCFG_FULLDX; 518 flowcfg = SL_FLOWCTL_FULLDX | SL_FLOWCTL_EN; 519 } else { 520 sc->rxcfg &= ~SL_RXCFG_FULLDX; 521 sc->txcfg &= ~SL_TXCFG_FULLDX; 522 } 523 524 /* if promiscuous mode, set the allframes bit. */ 525 if (ifp->if_flags & IFF_PROMISC) 526 sc->rxcfg |= (SL_RXCFG_EN | SL_RXCFG_RCV_SMALL | SL_RXCFG_RCV_HUGE | SL_RXCFG_RCV_ERR | SL_RXCFG_RCV_BROAD | SL_RXCFG_RCV_MULTI | SL_RXCFG_RCV_ALL); 527 else 528 sc->rxcfg &= ~(SL_RXCFG_EN | SL_RXCFG_RCV_SMALL | SL_RXCFG_RCV_HUGE | SL_RXCFG_RCV_ERR | SL_RXCFG_RCV_BROAD | SL_RXCFG_RCV_MULTI | SL_RXCFG_RCV_ALL); 529 530 /* Set capture broadcast bit to capture broadcast frames */ 531 if (ifp->if_flags & IFF_BROADCAST) 532 sc->rxcfg |= SL_RXCFG_EN | SL_RXCFG_RCV_BROAD; 533 else 534 sc->rxcfg &= ~(SL_RXCFG_EN | SL_RXCFG_RCV_BROAD); 535 536 /* Program the multicast filter, if necessary */ 537 sln_set_multi(sc); 538 539 SLN_WRITE_4(sc, SL_RX_CONFIG, sc->rxcfg); 540 SLN_WRITE_4(sc, SL_TX_CONFIG, sc->txcfg); 541 SLN_WRITE_4(sc, SL_FLOW_CTRL, flowcfg); 542 } 543 544 static u_char shade_map[] = { 0x0, 0x8, 0x4, 0xc, 0x2, 0xa, 0x6, 0xe, 545 0x1, 0x9, 0x5, 0xd, 0x3, 0xb, 0x7, 0xf }; 546 547 /* Calculate CRC32 of a multicast group address */ 548 static uint32_t 549 sln_ether_crc32(caddr_t addr) 550 { 551 uint32_t crc, crcr; 552 int i, j; 553 unsigned char data = 0; 554 /* Compute CRC for the address value. */ 555 556 crc = 0xFFFFFFFF; /* initial value */ 557 558 for (i = ETHER_ADDR_LEN; i > 0; i--) { 559 data = *addr++; 560 561 for (j = 0; j < 8; j++) { 562 if (((data & 0x1) ^ (crc & 0x1)) != 0) { 563 crc >>= 1; 564 crc ^= 0xEDB88320; 565 } else { 566 crc >>= 1; 567 } 568 data >>= 1; 569 } 570 } 571 572 crcr = shade_map[crc >> 28]; 573 crcr |= (shade_map[(crc >> 24) & 0xf] << 4); 574 crcr |= (shade_map[(crc >> 20) & 0xf] << 8); 575 crcr |= (shade_map[(crc >> 16) & 0xf] << 12); 576 crcr |= (shade_map[(crc >> 12) & 0xf] << 16); 577 crcr |= (shade_map[(crc >> 8) & 0xf] << 20); 578 crcr |= (shade_map[(crc >> 4) & 0xf] << 24); 579 crcr |= (shade_map[crc & 0xf] << 28); 580 581 return crcr; 582 } 583 584 /* Program the 64-bit multicast hash filter */ 585 static void 586 sln_set_multi(struct sln_softc *sc) 587 { 588 struct ifnet *ifp = &sc->arpcom.ac_if; 589 uint32_t crc = 0; 590 uint32_t mc_g[2] = {0, 0}; 591 struct ifmultiaddr *ifma; 592 int j; 593 594 if (ifp->if_flags & IFF_PROMISC) { 595 kprintf("Promisc mode is enabled\n"); 596 sc->rxcfg |= SL_RXCFG_EN | SL_RXCFG_RCV_MULTI; 597 mc_g[0] = mc_g[1] = 0xFFFFFFFF; 598 } else if (ifp->if_flags & IFF_ALLMULTI) { 599 kprintf("Allmulti mode is enabled\n"); 600 sc->rxcfg |= SL_RXCFG_EN | SL_RXCFG_RCV_MULTI; 601 mc_g[0] = mc_g[1] = 0xFFFFFFFF; 602 } else if (ifp->if_flags & IFF_MULTICAST) { 603 kprintf("Multicast mode is enabled\n"); 604 sc->rxcfg |= SL_RXCFG_EN | SL_RXCFG_RCV_MULTI; 605 606 /* first, zero all the existing hash bits */ 607 mc_g[0] = mc_g[1] = 0; 608 609 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 610 j = 0; 611 612 if ((ifma->ifma_addr->sa_family) != AF_LINK) 613 continue; 614 615 crc = ~sln_ether_crc32(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 616 crc >>= 24; 617 618 if (crc & 0x1) 619 j |= 0x2; 620 if (crc & 0x2) 621 j |= 0x1; 622 if (crc & 0x10) 623 j |= 0x20; 624 if (crc & 0x20) 625 j |= 0x10; 626 if (crc & 0x40) 627 j |= 0x8; 628 if (crc & 0x80) 629 j |= 0x4; 630 631 if (j > 31) 632 mc_g[0] |= (0x1 << (j - 32)); 633 else 634 mc_g[1] |= (0x1 << j); 635 } 636 } else { 637 sc->rxcfg &= ~(SL_RXCFG_EN | SL_RXCFG_RCV_MULTI); 638 } 639 640 SLN_WRITE_4(sc, SL_RX_CONFIG, sc->rxcfg); 641 SLN_WRITE_4(sc, SL_MULTI_GROUP0, mc_g[0]); 642 SLN_WRITE_4(sc, SL_MULTI_GROUP1, mc_g[1]); 643 } 644 645 /* Initialize the TX/Rx descriptors */ 646 static void 647 sln_init_tx(struct sln_softc *sc) 648 { 649 int i; 650 651 sc->sln_bufdata.cur_tx = 0; 652 sc->sln_bufdata.dirty_tx = 0; 653 654 for (i = 0; i < SL_TXD_CNT; i++) { 655 sc->sln_bufdata.sln_tx_buf[i] = NULL; 656 SLN_WRITE_4(sc, SL_TSAD0 + (i * 4), 0); 657 } 658 } 659 660 /* Software & Hardware Initialize */ 661 static void 662 sln_init(void *x) 663 { 664 struct sln_softc *sc = x; 665 struct ifnet *ifp = &sc->arpcom.ac_if; 666 667 PDEBUG("sln_init\n"); 668 669 ASSERT_SERIALIZED(ifp->if_serializer); 670 671 sln_stop(sc); 672 673 /* soft reset the chip */ 674 sln_reset(sc); 675 676 /* disable interrupt */ 677 SLN_WRITE_4(sc, SL_INT_MASK, 0); 678 679 /* SLN_WRITE_4(sc, SL_MII_CMD0, SL_MII0_DIVEDER); */ 680 681 /* clear multicast address */ 682 SLN_WRITE_4(sc, SL_MULTI_GROUP0, 0); 683 SLN_WRITE_4(sc, SL_MULTI_GROUP1, 0); 684 685 /* Init the RX buffer start address register. */ 686 SLN_WRITE_4(sc, SL_RBSA, vtophys(sc->sln_bufdata.sln_rx_buf)); 687 sc->sln_bufdata.dirty_rx = vtophys(sc->sln_bufdata.sln_rx_buf); 688 689 /* Init TX descriptors. */ 690 sln_init_tx(sc); 691 692 /* configure RX buffer size */ 693 if (sc->tx_early_ctrl && sc->rx_early_ctrl) 694 SLN_WRITE_4(sc, SL_CFG1, SL_EARLY_RX | SL_EARLY_TX | SL_RXBUF_64 | SL_RXFIFO_1024BYTES); 695 else if (sc->tx_early_ctrl) 696 SLN_WRITE_4(sc, SL_CFG1, SL_EARLY_TX | SL_RXBUF_64); 697 else if (sc->rx_early_ctrl) 698 SLN_WRITE_4(sc, SL_CFG1, SL_EARLY_RX | SL_RXBUF_64 | SL_RXFIFO_1024BYTES); 699 else 700 SLN_WRITE_4(sc, SL_CFG1, SL_RXBUF_64); 701 702 /* MII media configuration */ 703 sln_media_cfg(sc); 704 705 if (sc->connect) { 706 /* Enable transmit and receive */ 707 sc->rxcfg |= SL_RXCFG_EN; 708 sc->txcfg |= SL_TXCFG_EN; 709 } else { 710 sc->rxcfg &= ~SL_RXCFG_EN; 711 sc->txcfg &= ~SL_TXCFG_EN; 712 } 713 714 SLN_WRITE_4(sc, SL_TX_CONFIG, sc->txcfg); 715 SLN_WRITE_4(sc, SL_RX_CONFIG, sc->rxcfg); 716 717 /* Enable interrupts */ 718 SLN_WRITE_4(sc, SL_INT_MASK, SL_INRTS); 719 720 sc->suspended = 0; 721 722 ifp->if_flags |= IFF_RUNNING; 723 ifp->if_flags &= ~IFF_OACTIVE; 724 725 callout_reset(&sc->sln_state, hz, sln_tick, sc); 726 } 727 728 /* Transmit Packet */ 729 static void 730 sln_tx(struct ifnet *ifp) 731 { 732 struct sln_softc *sc = ifp->if_softc; 733 struct mbuf *m_head = NULL; 734 struct mbuf *m_new = NULL; 735 int entry; 736 737 ASSERT_SERIALIZED(ifp->if_serializer); 738 739 if (!sc->connect) { 740 ifq_purge(&ifp->if_snd); 741 return; 742 } 743 744 if ((ifp->if_flags & (IFF_OACTIVE | IFF_RUNNING)) != IFF_RUNNING) 745 return; 746 747 while (SL_CUR_TXBUF(sc) == NULL) { /* SL_CUR_TXBUF(x) = x->sln_bufdata.sln_tx_buf[x->sln_bufdata.cur_tx] */ 748 entry = sc->sln_bufdata.cur_tx; 749 750 m_head = ifq_dequeue(&ifp->if_snd, NULL); 751 if (m_head == NULL) 752 break; 753 754 MGETHDR(m_new, MB_DONTWAIT, MT_DATA); 755 if (m_new == NULL) { 756 if_printf(ifp, "no memory for tx descriptor"); 757 m_freem(m_head); 758 break; 759 } 760 if ((m_head->m_pkthdr.len > MHLEN) || (60 > MHLEN)) { 761 MCLGET(m_new, MB_DONTWAIT); 762 if (!(m_new->m_flags & M_EXT)) { 763 m_freem(m_new); 764 m_freem(m_head); 765 if_printf(ifp, "no memory for tx descriptor"); 766 break; 767 } 768 } 769 m_copydata(m_head, 0, m_head->m_pkthdr.len, mtod(m_new, caddr_t)); 770 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 771 m_freem(m_head); 772 m_head = m_new; 773 SL_CUR_TXBUF(sc) = m_head; 774 775 /* 776 * if there's a BPF listener, bounce a copy of this frame to 777 * him 778 */ 779 BPF_MTAP(ifp, SL_CUR_TXBUF(sc)); 780 781 /* Transmit the frame */ 782 SLN_WRITE_4(sc, ((entry * 4) + SL_TSAD0), 783 vtophys(mtod(SL_CUR_TXBUF(sc), caddr_t))); 784 785 /* calculate length of the frame */ 786 if ((SL_CUR_TXBUF(sc)->m_pkthdr.len < 60) && (!sc->txenablepad)) { 787 memset(mtod(m_head, char *)+m_head->m_pkthdr.len, 0x20, 60 - m_head->m_pkthdr.len); 788 SLN_WRITE_4(sc, (entry * 4) + SL_TSD0, 60); 789 } else if (SL_CUR_TXBUF(sc)->m_pkthdr.len < 100) 790 SLN_WRITE_4(sc, (entry * 4) + SL_TSD0, SL_CUR_TXBUF(sc)->m_pkthdr.len); 791 else if (SL_CUR_TXBUF(sc)->m_pkthdr.len < 300) 792 SLN_WRITE_4(sc, (entry * 4) + SL_TSD0, 0x30000 | SL_CUR_TXBUF(sc)->m_pkthdr.len); 793 else 794 SLN_WRITE_4(sc, (entry * 4) + SL_TSD0, 0x50000 | SL_CUR_TXBUF(sc)->m_pkthdr.len); 795 sc->sln_bufdata.cur_tx = (entry + 1) % SL_TXD_CNT; 796 797 PDEBUG("Queue tx packet size %d to tx-descriptor %d.\n", m_head->m_pkthdr.len, entry); 798 } 799 800 /* Tx buffer chain full */ 801 if (SL_CUR_TXBUF(sc) != NULL) 802 ifp->if_flags |= IFF_OACTIVE; 803 804 /* Set a timeout in case the chip goes out to lunch */ 805 ifp->if_timer = 5; 806 } 807 808 /* Receive Data handler */ 809 static void 810 sln_rx(struct sln_softc *sc) 811 { 812 struct mbuf *m; 813 struct ifnet *ifp = &sc->arpcom.ac_if; 814 uint32_t rxstat = 0; 815 uint32_t rx_offset; 816 caddr_t rx_bufpos = NULL; 817 uint32_t cur_rx = 0; 818 uint32_t dirty_rx; 819 long rx_len; 820 u_long rx_space; 821 u_long rx_size = 0; 822 u_long rx_size_align = 0; 823 uint32_t rx_bytes = 0; 824 u_long pkt_size = 0; 825 826 cur_rx = SLN_READ_4(sc, SL_RBW_PTR); 827 dirty_rx = sc->sln_bufdata.dirty_rx; 828 829 /* 830 * cur_rx is only 17 bits in the RxBufWPtr register. if cur_rx can be 831 * used in physical space, we need to change it to 32 bits physical 832 * address 833 */ 834 cur_rx |= vtophys(sc->sln_bufdata.sln_rx_buf) & (~(u_long) (SL_RX_BUFLEN - 1)); 835 836 if (cur_rx < vtophys(sc->sln_bufdata.sln_rx_buf)) 837 cur_rx += SL_RX_BUFLEN; 838 839 if (cur_rx >= dirty_rx) 840 rx_len = (long)(cur_rx - dirty_rx); 841 else 842 rx_len = SL_RX_BUFLEN - (long)(dirty_rx - cur_rx); 843 844 if ((rx_len > SL_RX_BUFLEN) || (rx_len < 0)) { 845 if_printf(ifp, "rx len is fail\n"); 846 return; 847 } 848 if (rx_len == 0) 849 return; 850 851 rx_offset = (dirty_rx - vtophys(sc->sln_bufdata.sln_rx_buf)) & (u_long) (SL_RX_BUFLEN - 1); 852 853 while (rx_len > 0) { 854 rx_bufpos = sc->sln_bufdata.sln_rx_buf + rx_offset; 855 rxstat = *(uint32_t *) rx_bufpos; 856 rx_size = (rxstat >> 20) & 0x0FFF; 857 rx_size_align = (rx_size + 3) & ~3; /* for 4 bytes aligned */ 858 pkt_size = rx_size - ETHER_CRC_LEN; /* Omit the four octet 859 * CRC from the length. */ 860 861 PDEBUG("rx len: %ld rx frame size:%ld rx state:0x%x\n", rx_len, rx_size, rxstat); 862 863 /* errors receive packets caculatation */ 864 if (rxstat == 0 || rx_size < 16 || !(rxstat & SL_RXSTAT_RXOK)) { 865 ifp->if_ierrors++; 866 867 if (!(rxstat & SL_RXSTAT_RXOK)) 868 if_printf(ifp, "receiver ok error\n"); 869 870 if (!(rxstat & SL_RXSTAT_CRCOK)) 871 if_printf(ifp, "crc error\n"); 872 873 if (rxstat & SL_RXSTAT_ALIGNERR) 874 if_printf(ifp, "frame alignment error\n"); 875 876 if (rxstat & (SL_RXSTAT_HUGEFRM | SL_RXSTAT_SMALLFRM)) 877 if_printf(ifp, "received frame length is error\n"); 878 879 break; 880 } 881 rx_len -= (long)(rx_size_align + 4); /* 4 bytes for receive 882 * frame head */ 883 884 if (rx_len < 0) { 885 kprintf("rx packets len is too small\n"); 886 break; 887 } 888 #ifdef SLN_PDEBUG 889 caddr_t p = NULL; 890 891 if_printf(ifp, "rx frame content\n"); 892 p = rx_bufpos; 893 for (i = 0; i < 30; i++, p++) { 894 if (i % 10 == 0) 895 kprintf("\n"); 896 if_printf(ifp, "%x ", (u_char)*p); 897 } 898 if_printf(ifp, "\n"); 899 #endif 900 /* No errors; receive the packet. */ 901 rx_bytes = rx_bytes + rx_size + 4; /* 4 bytes for receive 902 * frame header */ 903 904 if (rx_bufpos == (sc->sln_bufdata.sln_rx_buf + SL_RX_BUFLEN)) 905 rx_bufpos = sc->sln_bufdata.sln_rx_buf; 906 907 rx_bufpos = rx_bufpos + 4; /* 4 bytes for receive frame 908 * header */ 909 rx_space = (u_long)((sc->sln_bufdata.sln_rx_buf + SL_RX_BUFLEN) - rx_bufpos); 910 911 if (pkt_size > rx_space) { 912 m = m_devget(rx_bufpos - 2, pkt_size + 2, 0, ifp, NULL); /* 2 for etherer head 913 * align */ 914 915 if (m == NULL) { 916 ifp->if_ierrors++; 917 if_printf(ifp, 918 "out of mbufs, tried to copy %ld bytes\n", 919 rx_space); 920 } else { 921 m_adj(m, 2); 922 m_copyback(m, rx_space, pkt_size - rx_space, sc->sln_bufdata.sln_rx_buf); 923 } 924 } else { 925 m = m_devget(rx_bufpos - 2, pkt_size + 2, 0, ifp, NULL); 926 927 if (m == NULL) { 928 ifp->if_ierrors++; 929 if_printf(ifp, 930 "out of mbufs, tried to copy %ld bytes\n", 931 pkt_size); 932 if_printf(ifp, "ierrors = %ld\n", ifp->if_ierrors); 933 934 } else { 935 m_adj(m, 2); 936 } 937 } 938 939 ifp->if_ipackets++; 940 PDEBUG("ipackets = %ld\n", ifp->if_ipackets); 941 942 ifp->if_input(ifp, m); 943 944 rx_offset = (rx_offset + rx_size + 4) & (u_long) (SL_RX_BUFLEN - 1); /* 4 bytes for receive 945 * frame head */ 946 } 947 948 sc->sln_bufdata.dirty_rx = cur_rx; 949 950 SLN_WRITE_4(sc, SL_RBR_PTR, cur_rx); 951 } 952 953 /* Transmit OK/ERR handler */ 954 static void 955 sln_tx_intr(struct sln_softc *sc) 956 { 957 struct ifnet *ifp = &sc->arpcom.ac_if; 958 uint32_t txstat; 959 int entry; 960 961 do { 962 entry = sc->sln_bufdata.dirty_tx; 963 txstat = SLN_READ_4(sc, SL_TSD0 + entry * 4); 964 965 if (!(txstat & (SL_TXSD_TOK | SL_TXSD_TUN | SL_TXSD_TABT))) 966 break; /* It still hasn't been sent */ 967 968 if (SL_DIRTY_TXBUF(sc) != NULL) { /* SL_DIRTY_TXBUF(x) = 969 * x->sln_bufdata.sln_tx_ 970 * buf[x->sln_bufdata.dir 971 * ty_tx] */ 972 m_freem(SL_DIRTY_TXBUF(sc)); 973 SL_DIRTY_TXBUF(sc) = NULL; 974 } 975 if (txstat & SL_TXSD_TOK) { 976 ifp->if_opackets++; 977 ifp->if_obytes += txstat & SL_TXSD_LENMASK; 978 PDEBUG("opackets = %ld\n", ifp->if_opackets); 979 ifp->if_collisions += (txstat & SL_TXSD_NCC) >> 22; 980 } else { 981 ifp->if_oerrors++; 982 if ((txstat & (SL_TXSD_TABT | SL_TXSD_OWC))) { 983 sc->txcfg = TX_CFG_DEFAULT; 984 985 if (sc->txenablepad) 986 sc->txcfg |= 0x20000000; 987 988 SLN_WRITE_4(sc, SL_TX_CONFIG, sc->txcfg); 989 } 990 } 991 PDEBUG("tx done descriprtor %x\n", entry); 992 sc->sln_bufdata.dirty_tx = (entry + 1) % SL_TXD_CNT; 993 994 ifp->if_flags &= ~IFF_OACTIVE; 995 } while (sc->sln_bufdata.dirty_tx != sc->sln_bufdata.cur_tx); 996 997 if (sc->sln_bufdata.dirty_tx == sc->sln_bufdata.cur_tx) 998 ifp->if_timer = 0; 999 else 1000 ifp->if_timer = 5; 1001 } 1002 1003 static void 1004 sln_media_intr(struct sln_softc *sc) 1005 { 1006 u_long phys[2]; 1007 struct ifnet *ifp = &sc->arpcom.ac_if; 1008 1009 phys[0] = SL_MII_STAT; 1010 sln_mii_cmd(sc, SL_MII0_READ, phys); 1011 1012 PDEBUG("mii_stat:0x%lx\n", phys[1]); 1013 1014 if (0 == (phys[1] & SL_MIISTAT_LINK)) { 1015 kprintf("media is unconnect,linked down,or uncompatible\n"); 1016 sc->connect = 0; 1017 sln_mii_cmd(sc, SL_MII0_SCAN, phys); 1018 /* disable tx/rx */ 1019 sc->txcfg &= ~SL_TXCFG_EN; 1020 sc->rxcfg &= ~SL_RXCFG_EN; 1021 SLN_WRITE_4(sc, SL_TX_CONFIG, sc->txcfg); 1022 SLN_WRITE_4(sc, SL_RX_CONFIG, sc->rxcfg); 1023 1024 return; 1025 } 1026 /* Link is good. Report modes and set duplex mode. */ 1027 PDEBUG("media is connecting---> "); 1028 sc->connect = 1; 1029 1030 phys[0] = SL_MII_STAT_OUTPUT; 1031 sln_mii_cmd(sc, SL_MII0_READ, phys); 1032 sc->media_duplex = ((phys[1] & 0x0004) == 0) ? IFM_HDX : IFM_FDX; 1033 sc->media_speed = ((phys[1] & 0x0002) == 0) ? IFM_10_T : IFM_100_TX; 1034 1035 if_printf(ifp, "media option:%dM %s-duplex\n", 1036 sc->media_speed == 0x6 ? 100 : 10, 1037 sc->media_duplex == 0x100000 ? "full" : "half"); 1038 1039 sln_mii_cmd(sc, SL_MII0_SCAN, phys); 1040 1041 sln_mac_cfg(sc); 1042 1043 /* Enable tx/rx */ 1044 sc->rxcfg |= SL_RXCFG_EN; 1045 sc->txcfg |= SL_TXCFG_EN; 1046 SLN_WRITE_4(sc, SL_TX_CONFIG, sc->txcfg); 1047 SLN_WRITE_4(sc, SL_RX_CONFIG, sc->rxcfg); 1048 } 1049 1050 /* Interrupt Handler */ 1051 static void 1052 sln_interrupt(void *arg) 1053 { 1054 struct sln_softc *sc = arg; 1055 struct ifnet *ifp = &sc->arpcom.ac_if; 1056 uint32_t int_status; 1057 1058 ASSERT_SERIALIZED(ifp->if_serializer); 1059 1060 if (sc->suspended || (ifp->if_flags & IFF_RUNNING) == 0) 1061 return; 1062 1063 /* Disable interrupts. */ 1064 SLN_WRITE_4(sc, SL_INT_MASK, 0); 1065 1066 int_status = SLN_READ_4(sc, SL_INT_STATUS); 1067 1068 if ((int_status == 0xffffffff) || (int_status & SL_INRTS) == 0) 1069 goto back; 1070 1071 int_status = int_status & SL_INRTS; 1072 PDEBUG("int_status = 0x%x\n", int_status); 1073 1074 while (0 != int_status) { 1075 if (int_status & SL_INT_ROK) 1076 sln_rx(sc); 1077 1078 if (int_status & SL_INT_TOK) 1079 sln_tx_intr(sc); 1080 1081 if (int_status & SL_INT_RBO) { 1082 ifp->if_ierrors++; 1083 PDEBUG("rx buffer is overflow\n"); 1084 } 1085 1086 if (int_status & (SL_INT_LINKFAIL | SL_INT_LINKOK)) 1087 sln_media_intr(sc); 1088 1089 int_status = SLN_READ_4(sc, SL_INT_STATUS); 1090 } 1091 1092 /* Data in Tx buffer waiting for transimission */ 1093 if (!ifq_is_empty(&ifp->if_snd)) 1094 if_devstart(ifp); 1095 back: 1096 /* Re-enable interrupts. */ 1097 SLN_WRITE_4(sc, SL_INT_MASK, SL_INRTS); 1098 } 1099 1100 static void 1101 sln_tick(void *x) 1102 { 1103 struct sln_softc *sc = x; 1104 1105 callout_reset(&sc->sln_state, hz, sln_tick, sc); 1106 } 1107 1108 static int 1109 sln_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data, struct ucred *cr) 1110 { 1111 struct sln_softc *sc = ifp->if_softc; 1112 struct ifreq *ifr = (struct ifreq *)data; 1113 int error = 0; 1114 1115 ASSERT_SERIALIZED(ifp->if_serializer); 1116 1117 switch (cmd) { 1118 case SIOCSIFFLAGS: 1119 if (ifp->if_flags & IFF_UP) { 1120 if ((ifp->if_flags & IFF_RUNNING) == 0) 1121 sln_init(sc); 1122 } else { 1123 if (ifp->if_flags & IFF_RUNNING) 1124 sln_stop(sc); 1125 } 1126 break; 1127 case SIOCADDMULTI: 1128 case SIOCDELMULTI: 1129 sln_set_multi(sc); 1130 break; 1131 case SIOCGIFMEDIA: 1132 case SIOCSIFMEDIA: 1133 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, cmd); 1134 break; 1135 default: 1136 error = ether_ioctl(ifp, cmd, data); 1137 break; 1138 } 1139 return error; 1140 } 1141 1142 static void 1143 sln_watchdog(struct ifnet *ifp) 1144 { 1145 struct sln_softc *sc = ifp->if_softc; 1146 1147 ASSERT_SERIALIZED(ifp->if_serializer); 1148 1149 if_printf(ifp, "watchdog timeout!\n"); 1150 ifp->if_oerrors++; 1151 1152 sln_tx_intr(sc); 1153 sln_rx(sc); 1154 sln_init(sc); 1155 1156 if (!ifq_is_empty(&ifp->if_snd)) 1157 if_devstart(ifp); 1158 } 1159 1160 /* Stop all chip I/O */ 1161 static int 1162 sln_shutdown(device_t dev) 1163 { 1164 struct sln_softc *sc = device_get_softc(dev); 1165 struct ifnet *ifp = &sc->arpcom.ac_if; 1166 1167 lwkt_serialize_enter(ifp->if_serializer); 1168 sln_stop(sc); 1169 lwkt_serialize_exit(ifp->if_serializer); 1170 1171 return 0; 1172 } 1173 1174 /* device suspend routine */ 1175 static int 1176 sln_suspend(device_t dev) 1177 { 1178 struct sln_softc *sc = device_get_softc(dev); 1179 struct ifnet *ifp = &sc->arpcom.ac_if; 1180 1181 lwkt_serialize_enter(ifp->if_serializer); 1182 sln_stop(sc); 1183 sc->suspended = 1; 1184 lwkt_serialize_exit(ifp->if_serializer); 1185 1186 return 0; 1187 } 1188 1189 /* device resume routine */ 1190 static int 1191 sln_resume(device_t dev) 1192 { 1193 struct sln_softc *sc = device_get_softc(dev); 1194 struct ifnet *ifp = &sc->arpcom.ac_if; 1195 1196 lwkt_serialize_enter(ifp->if_serializer); 1197 if (ifp->if_flags & IFF_UP) 1198 sln_init(sc); 1199 sc->suspended = 0; 1200 lwkt_serialize_exit(ifp->if_serializer); 1201 1202 return 0; 1203 } 1204