1 /* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: src/sys/pci/if_ste.c,v 1.14.2.9 2003/02/05 22:03:57 mbr Exp $ 33 * $DragonFly: src/sys/dev/netif/ste/if_ste.c,v 1.16 2005/02/21 18:40:37 joerg Exp $ 34 */ 35 36 #include <sys/param.h> 37 #include <sys/systm.h> 38 #include <sys/sockio.h> 39 #include <sys/mbuf.h> 40 #include <sys/malloc.h> 41 #include <sys/kernel.h> 42 #include <sys/socket.h> 43 44 #include <net/if.h> 45 #include <net/ifq_var.h> 46 #include <net/if_arp.h> 47 #include <net/ethernet.h> 48 #include <net/if_dl.h> 49 #include <net/if_media.h> 50 #include <net/vlan/if_vlan_var.h> 51 52 #include <net/bpf.h> 53 54 #include <vm/vm.h> /* for vtophys */ 55 #include <vm/pmap.h> /* for vtophys */ 56 #include <machine/clock.h> /* for DELAY */ 57 #include <machine/bus_memio.h> 58 #include <machine/bus_pio.h> 59 #include <machine/bus.h> 60 #include <machine/resource.h> 61 #include <sys/bus.h> 62 #include <sys/rman.h> 63 64 #include "../mii_layer/mii.h" 65 #include "../mii_layer/miivar.h" 66 67 #include <bus/pci/pcireg.h> 68 #include <bus/pci/pcivar.h> 69 70 /* "controller miibus0" required. See GENERIC if you get errors here. */ 71 #include "miibus_if.h" 72 73 #define STE_USEIOSPACE 74 75 #include "if_stereg.h" 76 77 /* 78 * Various supported device vendors/types and their names. 79 */ 80 static struct ste_type ste_devs[] = { 81 { ST_VENDORID, ST_DEVICEID_ST201, "Sundance ST201 10/100BaseTX" }, 82 { DL_VENDORID, DL_DEVICEID_550TX, "D-Link DFE-550TX 10/100BaseTX" }, 83 { 0, 0, NULL } 84 }; 85 86 static int ste_probe (device_t); 87 static int ste_attach (device_t); 88 static int ste_detach (device_t); 89 static void ste_init (void *); 90 static void ste_intr (void *); 91 static void ste_rxeof (struct ste_softc *); 92 static void ste_txeoc (struct ste_softc *); 93 static void ste_txeof (struct ste_softc *); 94 static void ste_stats_update (void *); 95 static void ste_stop (struct ste_softc *); 96 static void ste_reset (struct ste_softc *); 97 static int ste_ioctl (struct ifnet *, u_long, caddr_t, 98 struct ucred *); 99 static int ste_encap (struct ste_softc *, struct ste_chain *, 100 struct mbuf *); 101 static void ste_start (struct ifnet *); 102 static void ste_watchdog (struct ifnet *); 103 static void ste_shutdown (device_t); 104 static int ste_newbuf (struct ste_softc *, 105 struct ste_chain_onefrag *, 106 struct mbuf *); 107 static int ste_ifmedia_upd (struct ifnet *); 108 static void ste_ifmedia_sts (struct ifnet *, struct ifmediareq *); 109 110 static void ste_mii_sync (struct ste_softc *); 111 static void ste_mii_send (struct ste_softc *, u_int32_t, int); 112 static int ste_mii_readreg (struct ste_softc *, 113 struct ste_mii_frame *); 114 static int ste_mii_writereg (struct ste_softc *, 115 struct ste_mii_frame *); 116 static int ste_miibus_readreg (device_t, int, int); 117 static int ste_miibus_writereg (device_t, int, int, int); 118 static void ste_miibus_statchg (device_t); 119 120 static int ste_eeprom_wait (struct ste_softc *); 121 static int ste_read_eeprom (struct ste_softc *, caddr_t, int, 122 int, int); 123 static void ste_wait (struct ste_softc *); 124 static u_int8_t ste_calchash (caddr_t); 125 static void ste_setmulti (struct ste_softc *); 126 static int ste_init_rx_list (struct ste_softc *); 127 static void ste_init_tx_list (struct ste_softc *); 128 129 #ifdef STE_USEIOSPACE 130 #define STE_RES SYS_RES_IOPORT 131 #define STE_RID STE_PCI_LOIO 132 #else 133 #define STE_RES SYS_RES_MEMORY 134 #define STE_RID STE_PCI_LOMEM 135 #endif 136 137 static device_method_t ste_methods[] = { 138 /* Device interface */ 139 DEVMETHOD(device_probe, ste_probe), 140 DEVMETHOD(device_attach, ste_attach), 141 DEVMETHOD(device_detach, ste_detach), 142 DEVMETHOD(device_shutdown, ste_shutdown), 143 144 /* bus interface */ 145 DEVMETHOD(bus_print_child, bus_generic_print_child), 146 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 147 148 /* MII interface */ 149 DEVMETHOD(miibus_readreg, ste_miibus_readreg), 150 DEVMETHOD(miibus_writereg, ste_miibus_writereg), 151 DEVMETHOD(miibus_statchg, ste_miibus_statchg), 152 153 { 0, 0 } 154 }; 155 156 static driver_t ste_driver = { 157 "ste", 158 ste_methods, 159 sizeof(struct ste_softc) 160 }; 161 162 static devclass_t ste_devclass; 163 164 DECLARE_DUMMY_MODULE(if_ste); 165 DRIVER_MODULE(if_ste, pci, ste_driver, ste_devclass, 0, 0); 166 DRIVER_MODULE(miibus, ste, miibus_driver, miibus_devclass, 0, 0); 167 168 #define STE_SETBIT4(sc, reg, x) \ 169 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | x) 170 171 #define STE_CLRBIT4(sc, reg, x) \ 172 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~x) 173 174 #define STE_SETBIT2(sc, reg, x) \ 175 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) | x) 176 177 #define STE_CLRBIT2(sc, reg, x) \ 178 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) & ~x) 179 180 #define STE_SETBIT1(sc, reg, x) \ 181 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | x) 182 183 #define STE_CLRBIT1(sc, reg, x) \ 184 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~x) 185 186 187 #define MII_SET(x) STE_SETBIT1(sc, STE_PHYCTL, x) 188 #define MII_CLR(x) STE_CLRBIT1(sc, STE_PHYCTL, x) 189 190 /* 191 * Sync the PHYs by setting data bit and strobing the clock 32 times. 192 */ 193 static void ste_mii_sync(sc) 194 struct ste_softc *sc; 195 { 196 int i; 197 198 MII_SET(STE_PHYCTL_MDIR|STE_PHYCTL_MDATA); 199 200 for (i = 0; i < 32; i++) { 201 MII_SET(STE_PHYCTL_MCLK); 202 DELAY(1); 203 MII_CLR(STE_PHYCTL_MCLK); 204 DELAY(1); 205 } 206 207 return; 208 } 209 210 /* 211 * Clock a series of bits through the MII. 212 */ 213 static void ste_mii_send(sc, bits, cnt) 214 struct ste_softc *sc; 215 u_int32_t bits; 216 int cnt; 217 { 218 int i; 219 220 MII_CLR(STE_PHYCTL_MCLK); 221 222 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 223 if (bits & i) { 224 MII_SET(STE_PHYCTL_MDATA); 225 } else { 226 MII_CLR(STE_PHYCTL_MDATA); 227 } 228 DELAY(1); 229 MII_CLR(STE_PHYCTL_MCLK); 230 DELAY(1); 231 MII_SET(STE_PHYCTL_MCLK); 232 } 233 } 234 235 /* 236 * Read an PHY register through the MII. 237 */ 238 static int ste_mii_readreg(sc, frame) 239 struct ste_softc *sc; 240 struct ste_mii_frame *frame; 241 242 { 243 int i, ack, s; 244 245 s = splimp(); 246 247 /* 248 * Set up frame for RX. 249 */ 250 frame->mii_stdelim = STE_MII_STARTDELIM; 251 frame->mii_opcode = STE_MII_READOP; 252 frame->mii_turnaround = 0; 253 frame->mii_data = 0; 254 255 CSR_WRITE_2(sc, STE_PHYCTL, 0); 256 /* 257 * Turn on data xmit. 258 */ 259 MII_SET(STE_PHYCTL_MDIR); 260 261 ste_mii_sync(sc); 262 263 /* 264 * Send command/address info. 265 */ 266 ste_mii_send(sc, frame->mii_stdelim, 2); 267 ste_mii_send(sc, frame->mii_opcode, 2); 268 ste_mii_send(sc, frame->mii_phyaddr, 5); 269 ste_mii_send(sc, frame->mii_regaddr, 5); 270 271 /* Turn off xmit. */ 272 MII_CLR(STE_PHYCTL_MDIR); 273 274 /* Idle bit */ 275 MII_CLR((STE_PHYCTL_MCLK|STE_PHYCTL_MDATA)); 276 DELAY(1); 277 MII_SET(STE_PHYCTL_MCLK); 278 DELAY(1); 279 280 /* Check for ack */ 281 MII_CLR(STE_PHYCTL_MCLK); 282 DELAY(1); 283 ack = CSR_READ_2(sc, STE_PHYCTL) & STE_PHYCTL_MDATA; 284 MII_SET(STE_PHYCTL_MCLK); 285 DELAY(1); 286 287 /* 288 * Now try reading data bits. If the ack failed, we still 289 * need to clock through 16 cycles to keep the PHY(s) in sync. 290 */ 291 if (ack) { 292 for(i = 0; i < 16; i++) { 293 MII_CLR(STE_PHYCTL_MCLK); 294 DELAY(1); 295 MII_SET(STE_PHYCTL_MCLK); 296 DELAY(1); 297 } 298 goto fail; 299 } 300 301 for (i = 0x8000; i; i >>= 1) { 302 MII_CLR(STE_PHYCTL_MCLK); 303 DELAY(1); 304 if (!ack) { 305 if (CSR_READ_2(sc, STE_PHYCTL) & STE_PHYCTL_MDATA) 306 frame->mii_data |= i; 307 DELAY(1); 308 } 309 MII_SET(STE_PHYCTL_MCLK); 310 DELAY(1); 311 } 312 313 fail: 314 315 MII_CLR(STE_PHYCTL_MCLK); 316 DELAY(1); 317 MII_SET(STE_PHYCTL_MCLK); 318 DELAY(1); 319 320 splx(s); 321 322 if (ack) 323 return(1); 324 return(0); 325 } 326 327 /* 328 * Write to a PHY register through the MII. 329 */ 330 static int ste_mii_writereg(sc, frame) 331 struct ste_softc *sc; 332 struct ste_mii_frame *frame; 333 334 { 335 int s; 336 337 s = splimp(); 338 /* 339 * Set up frame for TX. 340 */ 341 342 frame->mii_stdelim = STE_MII_STARTDELIM; 343 frame->mii_opcode = STE_MII_WRITEOP; 344 frame->mii_turnaround = STE_MII_TURNAROUND; 345 346 /* 347 * Turn on data output. 348 */ 349 MII_SET(STE_PHYCTL_MDIR); 350 351 ste_mii_sync(sc); 352 353 ste_mii_send(sc, frame->mii_stdelim, 2); 354 ste_mii_send(sc, frame->mii_opcode, 2); 355 ste_mii_send(sc, frame->mii_phyaddr, 5); 356 ste_mii_send(sc, frame->mii_regaddr, 5); 357 ste_mii_send(sc, frame->mii_turnaround, 2); 358 ste_mii_send(sc, frame->mii_data, 16); 359 360 /* Idle bit. */ 361 MII_SET(STE_PHYCTL_MCLK); 362 DELAY(1); 363 MII_CLR(STE_PHYCTL_MCLK); 364 DELAY(1); 365 366 /* 367 * Turn off xmit. 368 */ 369 MII_CLR(STE_PHYCTL_MDIR); 370 371 splx(s); 372 373 return(0); 374 } 375 376 static int ste_miibus_readreg(dev, phy, reg) 377 device_t dev; 378 int phy, reg; 379 { 380 struct ste_softc *sc; 381 struct ste_mii_frame frame; 382 383 sc = device_get_softc(dev); 384 385 if ( sc->ste_one_phy && phy != 0 ) 386 return (0); 387 388 bzero((char *)&frame, sizeof(frame)); 389 390 frame.mii_phyaddr = phy; 391 frame.mii_regaddr = reg; 392 ste_mii_readreg(sc, &frame); 393 394 return(frame.mii_data); 395 } 396 397 static int ste_miibus_writereg(dev, phy, reg, data) 398 device_t dev; 399 int phy, reg, data; 400 { 401 struct ste_softc *sc; 402 struct ste_mii_frame frame; 403 404 sc = device_get_softc(dev); 405 bzero((char *)&frame, sizeof(frame)); 406 407 frame.mii_phyaddr = phy; 408 frame.mii_regaddr = reg; 409 frame.mii_data = data; 410 411 ste_mii_writereg(sc, &frame); 412 413 return(0); 414 } 415 416 static void ste_miibus_statchg(dev) 417 device_t dev; 418 { 419 struct ste_softc *sc; 420 struct mii_data *mii; 421 int i; 422 423 sc = device_get_softc(dev); 424 mii = device_get_softc(sc->ste_miibus); 425 426 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 427 STE_SETBIT2(sc, STE_MACCTL0, STE_MACCTL0_FULLDUPLEX); 428 } else { 429 STE_CLRBIT2(sc, STE_MACCTL0, STE_MACCTL0_FULLDUPLEX); 430 } 431 432 STE_SETBIT4(sc, STE_ASICCTL,STE_ASICCTL_RX_RESET | 433 STE_ASICCTL_TX_RESET); 434 for (i = 0; i < STE_TIMEOUT; i++) { 435 if (!(CSR_READ_4(sc, STE_ASICCTL) & STE_ASICCTL_RESET_BUSY)) 436 break; 437 } 438 if (i == STE_TIMEOUT) 439 printf("ste%d: rx reset never completed\n", sc->ste_unit); 440 441 return; 442 } 443 444 static int ste_ifmedia_upd(ifp) 445 struct ifnet *ifp; 446 { 447 struct ste_softc *sc; 448 struct mii_data *mii; 449 450 sc = ifp->if_softc; 451 mii = device_get_softc(sc->ste_miibus); 452 sc->ste_link = 0; 453 if (mii->mii_instance) { 454 struct mii_softc *miisc; 455 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 456 miisc = LIST_NEXT(miisc, mii_list)) 457 mii_phy_reset(miisc); 458 } 459 mii_mediachg(mii); 460 461 return(0); 462 } 463 464 static void ste_ifmedia_sts(ifp, ifmr) 465 struct ifnet *ifp; 466 struct ifmediareq *ifmr; 467 { 468 struct ste_softc *sc; 469 struct mii_data *mii; 470 471 sc = ifp->if_softc; 472 mii = device_get_softc(sc->ste_miibus); 473 474 mii_pollstat(mii); 475 ifmr->ifm_active = mii->mii_media_active; 476 ifmr->ifm_status = mii->mii_media_status; 477 478 return; 479 } 480 481 static void ste_wait(sc) 482 struct ste_softc *sc; 483 { 484 int i; 485 486 for (i = 0; i < STE_TIMEOUT; i++) { 487 if (!(CSR_READ_4(sc, STE_DMACTL) & STE_DMACTL_DMA_HALTINPROG)) 488 break; 489 } 490 491 if (i == STE_TIMEOUT) 492 printf("ste%d: command never completed!\n", sc->ste_unit); 493 494 return; 495 } 496 497 /* 498 * The EEPROM is slow: give it time to come ready after issuing 499 * it a command. 500 */ 501 static int ste_eeprom_wait(sc) 502 struct ste_softc *sc; 503 { 504 int i; 505 506 DELAY(1000); 507 508 for (i = 0; i < 100; i++) { 509 if (CSR_READ_2(sc, STE_EEPROM_CTL) & STE_EECTL_BUSY) 510 DELAY(1000); 511 else 512 break; 513 } 514 515 if (i == 100) { 516 printf("ste%d: eeprom failed to come ready\n", sc->ste_unit); 517 return(1); 518 } 519 520 return(0); 521 } 522 523 /* 524 * Read a sequence of words from the EEPROM. Note that ethernet address 525 * data is stored in the EEPROM in network byte order. 526 */ 527 static int ste_read_eeprom(sc, dest, off, cnt, swap) 528 struct ste_softc *sc; 529 caddr_t dest; 530 int off; 531 int cnt; 532 int swap; 533 { 534 int err = 0, i; 535 u_int16_t word = 0, *ptr; 536 537 if (ste_eeprom_wait(sc)) 538 return(1); 539 540 for (i = 0; i < cnt; i++) { 541 CSR_WRITE_2(sc, STE_EEPROM_CTL, STE_EEOPCODE_READ | (off + i)); 542 err = ste_eeprom_wait(sc); 543 if (err) 544 break; 545 word = CSR_READ_2(sc, STE_EEPROM_DATA); 546 ptr = (u_int16_t *)(dest + (i * 2)); 547 if (swap) 548 *ptr = ntohs(word); 549 else 550 *ptr = word; 551 } 552 553 return(err ? 1 : 0); 554 } 555 556 static u_int8_t ste_calchash(addr) 557 caddr_t addr; 558 { 559 560 u_int32_t crc, carry; 561 int i, j; 562 u_int8_t c; 563 564 /* Compute CRC for the address value. */ 565 crc = 0xFFFFFFFF; /* initial value */ 566 567 for (i = 0; i < 6; i++) { 568 c = *(addr + i); 569 for (j = 0; j < 8; j++) { 570 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 571 crc <<= 1; 572 c >>= 1; 573 if (carry) 574 crc = (crc ^ 0x04c11db6) | carry; 575 } 576 } 577 578 /* return the filter bit position */ 579 return(crc & 0x0000003F); 580 } 581 582 static void ste_setmulti(sc) 583 struct ste_softc *sc; 584 { 585 struct ifnet *ifp; 586 int h = 0; 587 u_int32_t hashes[2] = { 0, 0 }; 588 struct ifmultiaddr *ifma; 589 590 ifp = &sc->arpcom.ac_if; 591 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 592 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_ALLMULTI); 593 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_MULTIHASH); 594 return; 595 } 596 597 /* first, zot all the existing hash bits */ 598 CSR_WRITE_2(sc, STE_MAR0, 0); 599 CSR_WRITE_2(sc, STE_MAR1, 0); 600 CSR_WRITE_2(sc, STE_MAR2, 0); 601 CSR_WRITE_2(sc, STE_MAR3, 0); 602 603 /* now program new ones */ 604 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 605 ifma = ifma->ifma_link.le_next) { 606 if (ifma->ifma_addr->sa_family != AF_LINK) 607 continue; 608 h = ste_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 609 if (h < 32) 610 hashes[0] |= (1 << h); 611 else 612 hashes[1] |= (1 << (h - 32)); 613 } 614 615 CSR_WRITE_2(sc, STE_MAR0, hashes[0] & 0xFFFF); 616 CSR_WRITE_2(sc, STE_MAR1, (hashes[0] >> 16) & 0xFFFF); 617 CSR_WRITE_2(sc, STE_MAR2, hashes[1] & 0xFFFF); 618 CSR_WRITE_2(sc, STE_MAR3, (hashes[1] >> 16) & 0xFFFF); 619 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_ALLMULTI); 620 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_MULTIHASH); 621 622 return; 623 } 624 625 static void ste_intr(xsc) 626 void *xsc; 627 { 628 struct ste_softc *sc; 629 struct ifnet *ifp; 630 u_int16_t status; 631 632 sc = xsc; 633 ifp = &sc->arpcom.ac_if; 634 635 /* See if this is really our interrupt. */ 636 if (!(CSR_READ_2(sc, STE_ISR) & STE_ISR_INTLATCH)) 637 return; 638 639 for (;;) { 640 status = CSR_READ_2(sc, STE_ISR_ACK); 641 642 if (!(status & STE_INTRS)) 643 break; 644 645 if (status & STE_ISR_RX_DMADONE) 646 ste_rxeof(sc); 647 648 if (status & STE_ISR_TX_DMADONE) 649 ste_txeof(sc); 650 651 if (status & STE_ISR_TX_DONE) 652 ste_txeoc(sc); 653 654 if (status & STE_ISR_STATS_OFLOW) { 655 callout_stop(&sc->ste_stat_timer); 656 ste_stats_update(sc); 657 } 658 659 if (status & STE_ISR_LINKEVENT) 660 mii_pollstat(device_get_softc(sc->ste_miibus)); 661 662 if (status & STE_ISR_HOSTERR) { 663 ste_reset(sc); 664 ste_init(sc); 665 } 666 } 667 668 /* Re-enable interrupts */ 669 CSR_WRITE_2(sc, STE_IMR, STE_INTRS); 670 671 if (!ifq_is_empty(&ifp->if_snd)) 672 ste_start(ifp); 673 674 return; 675 } 676 677 /* 678 * A frame has been uploaded: pass the resulting mbuf chain up to 679 * the higher level protocols. 680 */ 681 static void ste_rxeof(sc) 682 struct ste_softc *sc; 683 { 684 struct mbuf *m; 685 struct ifnet *ifp; 686 struct ste_chain_onefrag *cur_rx; 687 int total_len = 0, count=0; 688 u_int32_t rxstat; 689 690 ifp = &sc->arpcom.ac_if; 691 692 while((rxstat = sc->ste_cdata.ste_rx_head->ste_ptr->ste_status) 693 & STE_RXSTAT_DMADONE) { 694 if ((STE_RX_LIST_CNT - count) < 3) { 695 break; 696 } 697 698 cur_rx = sc->ste_cdata.ste_rx_head; 699 sc->ste_cdata.ste_rx_head = cur_rx->ste_next; 700 701 /* 702 * If an error occurs, update stats, clear the 703 * status word and leave the mbuf cluster in place: 704 * it should simply get re-used next time this descriptor 705 * comes up in the ring. 706 */ 707 if (rxstat & STE_RXSTAT_FRAME_ERR) { 708 ifp->if_ierrors++; 709 cur_rx->ste_ptr->ste_status = 0; 710 continue; 711 } 712 713 /* 714 * If there error bit was not set, the upload complete 715 * bit should be set which means we have a valid packet. 716 * If not, something truly strange has happened. 717 */ 718 if (!(rxstat & STE_RXSTAT_DMADONE)) { 719 printf("ste%d: bad receive status -- packet dropped", 720 sc->ste_unit); 721 ifp->if_ierrors++; 722 cur_rx->ste_ptr->ste_status = 0; 723 continue; 724 } 725 726 /* No errors; receive the packet. */ 727 m = cur_rx->ste_mbuf; 728 total_len = cur_rx->ste_ptr->ste_status & STE_RXSTAT_FRAMELEN; 729 730 /* 731 * Try to conjure up a new mbuf cluster. If that 732 * fails, it means we have an out of memory condition and 733 * should leave the buffer in place and continue. This will 734 * result in a lost packet, but there's little else we 735 * can do in this situation. 736 */ 737 if (ste_newbuf(sc, cur_rx, NULL) == ENOBUFS) { 738 ifp->if_ierrors++; 739 cur_rx->ste_ptr->ste_status = 0; 740 continue; 741 } 742 743 ifp->if_ipackets++; 744 m->m_pkthdr.rcvif = ifp; 745 m->m_pkthdr.len = m->m_len = total_len; 746 747 (*ifp->if_input)(ifp, m); 748 749 cur_rx->ste_ptr->ste_status = 0; 750 count++; 751 } 752 753 return; 754 } 755 756 static void ste_txeoc(sc) 757 struct ste_softc *sc; 758 { 759 u_int8_t txstat; 760 struct ifnet *ifp; 761 762 ifp = &sc->arpcom.ac_if; 763 764 while ((txstat = CSR_READ_1(sc, STE_TX_STATUS)) & 765 STE_TXSTATUS_TXDONE) { 766 if (txstat & STE_TXSTATUS_UNDERRUN || 767 txstat & STE_TXSTATUS_EXCESSCOLLS || 768 txstat & STE_TXSTATUS_RECLAIMERR) { 769 ifp->if_oerrors++; 770 printf("ste%d: transmission error: %x\n", 771 sc->ste_unit, txstat); 772 773 ste_reset(sc); 774 ste_init(sc); 775 776 if (txstat & STE_TXSTATUS_UNDERRUN && 777 sc->ste_tx_thresh < STE_PACKET_SIZE) { 778 sc->ste_tx_thresh += STE_MIN_FRAMELEN; 779 printf("ste%d: tx underrun, increasing tx" 780 " start threshold to %d bytes\n", 781 sc->ste_unit, sc->ste_tx_thresh); 782 } 783 CSR_WRITE_2(sc, STE_TX_STARTTHRESH, sc->ste_tx_thresh); 784 CSR_WRITE_2(sc, STE_TX_RECLAIM_THRESH, 785 (STE_PACKET_SIZE >> 4)); 786 } 787 ste_init(sc); 788 CSR_WRITE_2(sc, STE_TX_STATUS, txstat); 789 } 790 791 return; 792 } 793 794 static void ste_txeof(sc) 795 struct ste_softc *sc; 796 { 797 struct ste_chain *cur_tx = NULL; 798 struct ifnet *ifp; 799 int idx; 800 801 ifp = &sc->arpcom.ac_if; 802 803 idx = sc->ste_cdata.ste_tx_cons; 804 while(idx != sc->ste_cdata.ste_tx_prod) { 805 cur_tx = &sc->ste_cdata.ste_tx_chain[idx]; 806 807 if (!(cur_tx->ste_ptr->ste_ctl & STE_TXCTL_DMADONE)) 808 break; 809 810 if (cur_tx->ste_mbuf != NULL) { 811 m_freem(cur_tx->ste_mbuf); 812 cur_tx->ste_mbuf = NULL; 813 } 814 815 ifp->if_opackets++; 816 817 sc->ste_cdata.ste_tx_cnt--; 818 STE_INC(idx, STE_TX_LIST_CNT); 819 ifp->if_timer = 0; 820 } 821 822 sc->ste_cdata.ste_tx_cons = idx; 823 824 if (cur_tx != NULL) 825 ifp->if_flags &= ~IFF_OACTIVE; 826 827 return; 828 } 829 830 static void ste_stats_update(xsc) 831 void *xsc; 832 { 833 struct ste_softc *sc; 834 struct ifnet *ifp; 835 struct mii_data *mii; 836 int s; 837 838 s = splimp(); 839 840 sc = xsc; 841 ifp = &sc->arpcom.ac_if; 842 mii = device_get_softc(sc->ste_miibus); 843 844 ifp->if_collisions += CSR_READ_1(sc, STE_LATE_COLLS) 845 + CSR_READ_1(sc, STE_MULTI_COLLS) 846 + CSR_READ_1(sc, STE_SINGLE_COLLS); 847 848 if (!sc->ste_link) { 849 mii_pollstat(mii); 850 if (mii->mii_media_status & IFM_ACTIVE && 851 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 852 sc->ste_link++; 853 /* 854 * we don't get a call-back on re-init so do it 855 * otherwise we get stuck in the wrong link state 856 */ 857 ste_miibus_statchg(sc->ste_dev); 858 if (!ifq_is_empty(&ifp->if_snd)) 859 ste_start(ifp); 860 } 861 } 862 863 callout_reset(&sc->ste_stat_timer, hz, ste_stats_update, sc); 864 splx(s); 865 866 return; 867 } 868 869 870 /* 871 * Probe for a Sundance ST201 chip. Check the PCI vendor and device 872 * IDs against our list and return a device name if we find a match. 873 */ 874 static int ste_probe(dev) 875 device_t dev; 876 { 877 struct ste_type *t; 878 879 t = ste_devs; 880 881 while(t->ste_name != NULL) { 882 if ((pci_get_vendor(dev) == t->ste_vid) && 883 (pci_get_device(dev) == t->ste_did)) { 884 device_set_desc(dev, t->ste_name); 885 return(0); 886 } 887 t++; 888 } 889 890 return(ENXIO); 891 } 892 893 /* 894 * Attach the interface. Allocate softc structures, do ifmedia 895 * setup and ethernet/BPF attach. 896 */ 897 static int ste_attach(dev) 898 device_t dev; 899 { 900 int s; 901 u_int32_t command; 902 struct ste_softc *sc; 903 struct ifnet *ifp; 904 int unit, error = 0, rid; 905 906 s = splimp(); 907 908 sc = device_get_softc(dev); 909 unit = device_get_unit(dev); 910 bzero(sc, sizeof(struct ste_softc)); 911 sc->ste_dev = dev; 912 913 /* 914 * Only use one PHY since this chip reports multiple 915 * Note on the DFE-550 the PHY is at 1 on the DFE-580 916 * it is at 0 & 1. It is rev 0x12. 917 */ 918 if (pci_get_vendor(dev) == DL_VENDORID && 919 pci_get_device(dev) == DL_DEVICEID_550TX && 920 pci_get_revid(dev) == 0x12 ) 921 sc->ste_one_phy = 1; 922 923 /* 924 * Handle power management nonsense. 925 */ 926 command = pci_read_config(dev, STE_PCI_CAPID, 4) & 0x000000FF; 927 if (command == 0x01) { 928 929 command = pci_read_config(dev, STE_PCI_PWRMGMTCTRL, 4); 930 if (command & STE_PSTATE_MASK) { 931 u_int32_t iobase, membase, irq; 932 933 /* Save important PCI config data. */ 934 iobase = pci_read_config(dev, STE_PCI_LOIO, 4); 935 membase = pci_read_config(dev, STE_PCI_LOMEM, 4); 936 irq = pci_read_config(dev, STE_PCI_INTLINE, 4); 937 938 /* Reset the power state. */ 939 printf("ste%d: chip is in D%d power mode " 940 "-- setting to D0\n", unit, command & STE_PSTATE_MASK); 941 command &= 0xFFFFFFFC; 942 pci_write_config(dev, STE_PCI_PWRMGMTCTRL, command, 4); 943 944 /* Restore PCI config data. */ 945 pci_write_config(dev, STE_PCI_LOIO, iobase, 4); 946 pci_write_config(dev, STE_PCI_LOMEM, membase, 4); 947 pci_write_config(dev, STE_PCI_INTLINE, irq, 4); 948 } 949 } 950 951 /* 952 * Map control/status registers. 953 */ 954 command = pci_read_config(dev, PCIR_COMMAND, 4); 955 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 956 pci_write_config(dev, PCIR_COMMAND, command, 4); 957 command = pci_read_config(dev, PCIR_COMMAND, 4); 958 959 #ifdef STE_USEIOSPACE 960 if (!(command & PCIM_CMD_PORTEN)) { 961 printf("ste%d: failed to enable I/O ports!\n", unit); 962 error = ENXIO; 963 goto fail; 964 } 965 #else 966 if (!(command & PCIM_CMD_MEMEN)) { 967 printf("ste%d: failed to enable memory mapping!\n", unit); 968 error = ENXIO; 969 goto fail; 970 } 971 #endif 972 973 rid = STE_RID; 974 sc->ste_res = bus_alloc_resource(dev, STE_RES, &rid, 975 0, ~0, 1, RF_ACTIVE); 976 977 if (sc->ste_res == NULL) { 978 printf ("ste%d: couldn't map ports/memory\n", unit); 979 error = ENXIO; 980 goto fail; 981 } 982 983 sc->ste_btag = rman_get_bustag(sc->ste_res); 984 sc->ste_bhandle = rman_get_bushandle(sc->ste_res); 985 986 rid = 0; 987 sc->ste_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 988 RF_SHAREABLE | RF_ACTIVE); 989 990 if (sc->ste_irq == NULL) { 991 printf("ste%d: couldn't map interrupt\n", unit); 992 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res); 993 error = ENXIO; 994 goto fail; 995 } 996 997 error = bus_setup_intr(dev, sc->ste_irq, INTR_TYPE_NET, 998 ste_intr, sc, &sc->ste_intrhand); 999 1000 if (error) { 1001 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq); 1002 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res); 1003 printf("ste%d: couldn't set up irq\n", unit); 1004 goto fail; 1005 } 1006 1007 callout_init(&sc->ste_stat_timer); 1008 1009 /* Reset the adapter. */ 1010 ste_reset(sc); 1011 1012 /* 1013 * Get station address from the EEPROM. 1014 */ 1015 if (ste_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr, 1016 STE_EEADDR_NODE0, 3, 0)) { 1017 printf("ste%d: failed to read station address\n", unit); 1018 bus_teardown_intr(dev, sc->ste_irq, sc->ste_intrhand); 1019 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq); 1020 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res); 1021 error = ENXIO;; 1022 goto fail; 1023 } 1024 1025 sc->ste_unit = unit; 1026 1027 /* Allocate the descriptor queues. */ 1028 sc->ste_ldata = contigmalloc(sizeof(struct ste_list_data), M_DEVBUF, 1029 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 1030 1031 if (sc->ste_ldata == NULL) { 1032 printf("ste%d: no memory for list buffers!\n", unit); 1033 bus_teardown_intr(dev, sc->ste_irq, sc->ste_intrhand); 1034 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq); 1035 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res); 1036 error = ENXIO; 1037 goto fail; 1038 } 1039 1040 bzero(sc->ste_ldata, sizeof(struct ste_list_data)); 1041 1042 /* Do MII setup. */ 1043 if (mii_phy_probe(dev, &sc->ste_miibus, 1044 ste_ifmedia_upd, ste_ifmedia_sts)) { 1045 printf("ste%d: MII without any phy!\n", sc->ste_unit); 1046 bus_teardown_intr(dev, sc->ste_irq, sc->ste_intrhand); 1047 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq); 1048 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res); 1049 contigfree(sc->ste_ldata, 1050 sizeof(struct ste_list_data), M_DEVBUF); 1051 error = ENXIO; 1052 goto fail; 1053 } 1054 1055 ifp = &sc->arpcom.ac_if; 1056 ifp->if_softc = sc; 1057 if_initname(ifp, "ste", unit); 1058 ifp->if_mtu = ETHERMTU; 1059 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1060 ifp->if_ioctl = ste_ioctl; 1061 ifp->if_start = ste_start; 1062 ifp->if_watchdog = ste_watchdog; 1063 ifp->if_init = ste_init; 1064 ifp->if_baudrate = 10000000; 1065 ifq_set_maxlen(&ifp->if_snd, STE_TX_LIST_CNT - 1); 1066 ifq_set_ready(&ifp->if_snd); 1067 1068 sc->ste_tx_thresh = STE_TXSTART_THRESH; 1069 1070 /* 1071 * Call MI attach routine. 1072 */ 1073 ether_ifattach(ifp, sc->arpcom.ac_enaddr); 1074 1075 /* 1076 * Tell the upper layer(s) we support long frames. 1077 */ 1078 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1079 1080 fail: 1081 splx(s); 1082 return(error); 1083 } 1084 1085 static int ste_detach(dev) 1086 device_t dev; 1087 { 1088 struct ste_softc *sc; 1089 struct ifnet *ifp; 1090 int s; 1091 1092 s = splimp(); 1093 1094 sc = device_get_softc(dev); 1095 ifp = &sc->arpcom.ac_if; 1096 1097 ste_stop(sc); 1098 ether_ifdetach(ifp); 1099 1100 bus_generic_detach(dev); 1101 device_delete_child(dev, sc->ste_miibus); 1102 1103 bus_teardown_intr(dev, sc->ste_irq, sc->ste_intrhand); 1104 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq); 1105 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res); 1106 1107 contigfree(sc->ste_ldata, sizeof(struct ste_list_data), M_DEVBUF); 1108 1109 splx(s); 1110 1111 return(0); 1112 } 1113 1114 static int ste_newbuf(sc, c, m) 1115 struct ste_softc *sc; 1116 struct ste_chain_onefrag *c; 1117 struct mbuf *m; 1118 { 1119 struct mbuf *m_new = NULL; 1120 1121 if (m == NULL) { 1122 MGETHDR(m_new, MB_DONTWAIT, MT_DATA); 1123 if (m_new == NULL) 1124 return(ENOBUFS); 1125 MCLGET(m_new, MB_DONTWAIT); 1126 if (!(m_new->m_flags & M_EXT)) { 1127 m_freem(m_new); 1128 return(ENOBUFS); 1129 } 1130 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1131 } else { 1132 m_new = m; 1133 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1134 m_new->m_data = m_new->m_ext.ext_buf; 1135 } 1136 1137 m_adj(m_new, ETHER_ALIGN); 1138 1139 c->ste_mbuf = m_new; 1140 c->ste_ptr->ste_status = 0; 1141 c->ste_ptr->ste_frag.ste_addr = vtophys(mtod(m_new, caddr_t)); 1142 c->ste_ptr->ste_frag.ste_len = (1536 + EVL_ENCAPLEN) | STE_FRAG_LAST; 1143 1144 return(0); 1145 } 1146 1147 static int ste_init_rx_list(sc) 1148 struct ste_softc *sc; 1149 { 1150 struct ste_chain_data *cd; 1151 struct ste_list_data *ld; 1152 int i; 1153 1154 cd = &sc->ste_cdata; 1155 ld = sc->ste_ldata; 1156 1157 for (i = 0; i < STE_RX_LIST_CNT; i++) { 1158 cd->ste_rx_chain[i].ste_ptr = &ld->ste_rx_list[i]; 1159 if (ste_newbuf(sc, &cd->ste_rx_chain[i], NULL) == ENOBUFS) 1160 return(ENOBUFS); 1161 if (i == (STE_RX_LIST_CNT - 1)) { 1162 cd->ste_rx_chain[i].ste_next = 1163 &cd->ste_rx_chain[0]; 1164 ld->ste_rx_list[i].ste_next = 1165 vtophys(&ld->ste_rx_list[0]); 1166 } else { 1167 cd->ste_rx_chain[i].ste_next = 1168 &cd->ste_rx_chain[i + 1]; 1169 ld->ste_rx_list[i].ste_next = 1170 vtophys(&ld->ste_rx_list[i + 1]); 1171 } 1172 ld->ste_rx_list[i].ste_status = 0; 1173 } 1174 1175 cd->ste_rx_head = &cd->ste_rx_chain[0]; 1176 1177 return(0); 1178 } 1179 1180 static void ste_init_tx_list(sc) 1181 struct ste_softc *sc; 1182 { 1183 struct ste_chain_data *cd; 1184 struct ste_list_data *ld; 1185 int i; 1186 1187 cd = &sc->ste_cdata; 1188 ld = sc->ste_ldata; 1189 for (i = 0; i < STE_TX_LIST_CNT; i++) { 1190 cd->ste_tx_chain[i].ste_ptr = &ld->ste_tx_list[i]; 1191 cd->ste_tx_chain[i].ste_ptr->ste_next = 0; 1192 cd->ste_tx_chain[i].ste_ptr->ste_ctl = 0; 1193 cd->ste_tx_chain[i].ste_phys = vtophys(&ld->ste_tx_list[i]); 1194 if (i == (STE_TX_LIST_CNT - 1)) 1195 cd->ste_tx_chain[i].ste_next = 1196 &cd->ste_tx_chain[0]; 1197 else 1198 cd->ste_tx_chain[i].ste_next = 1199 &cd->ste_tx_chain[i + 1]; 1200 if (i == 0) 1201 cd->ste_tx_chain[i].ste_prev = 1202 &cd->ste_tx_chain[STE_TX_LIST_CNT - 1]; 1203 else 1204 cd->ste_tx_chain[i].ste_prev = 1205 &cd->ste_tx_chain[i - 1]; 1206 } 1207 1208 cd->ste_tx_prod = 0; 1209 cd->ste_tx_cons = 0; 1210 cd->ste_tx_cnt = 0; 1211 1212 return; 1213 } 1214 1215 static void ste_init(xsc) 1216 void *xsc; 1217 { 1218 struct ste_softc *sc; 1219 int i, s; 1220 struct ifnet *ifp; 1221 struct mii_data *mii; 1222 1223 s = splimp(); 1224 1225 sc = xsc; 1226 ifp = &sc->arpcom.ac_if; 1227 mii = device_get_softc(sc->ste_miibus); 1228 1229 ste_stop(sc); 1230 1231 /* Init our MAC address */ 1232 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1233 CSR_WRITE_1(sc, STE_PAR0 + i, sc->arpcom.ac_enaddr[i]); 1234 } 1235 1236 /* Init RX list */ 1237 if (ste_init_rx_list(sc) == ENOBUFS) { 1238 printf("ste%d: initialization failed: no " 1239 "memory for RX buffers\n", sc->ste_unit); 1240 ste_stop(sc); 1241 splx(s); 1242 return; 1243 } 1244 1245 /* Set RX polling interval */ 1246 CSR_WRITE_1(sc, STE_RX_DMAPOLL_PERIOD, 1); 1247 1248 /* Init TX descriptors */ 1249 ste_init_tx_list(sc); 1250 1251 /* Set the TX freethresh value */ 1252 CSR_WRITE_1(sc, STE_TX_DMABURST_THRESH, STE_PACKET_SIZE >> 8); 1253 1254 /* Set the TX start threshold for best performance. */ 1255 CSR_WRITE_2(sc, STE_TX_STARTTHRESH, sc->ste_tx_thresh); 1256 1257 /* Set the TX reclaim threshold. */ 1258 CSR_WRITE_1(sc, STE_TX_RECLAIM_THRESH, (STE_PACKET_SIZE >> 4)); 1259 1260 /* Set up the RX filter. */ 1261 CSR_WRITE_1(sc, STE_RX_MODE, STE_RXMODE_UNICAST); 1262 1263 /* If we want promiscuous mode, set the allframes bit. */ 1264 if (ifp->if_flags & IFF_PROMISC) { 1265 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_PROMISC); 1266 } else { 1267 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_PROMISC); 1268 } 1269 1270 /* Set capture broadcast bit to accept broadcast frames. */ 1271 if (ifp->if_flags & IFF_BROADCAST) { 1272 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_BROADCAST); 1273 } else { 1274 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_BROADCAST); 1275 } 1276 1277 ste_setmulti(sc); 1278 1279 /* Load the address of the RX list. */ 1280 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_STALL); 1281 ste_wait(sc); 1282 CSR_WRITE_4(sc, STE_RX_DMALIST_PTR, 1283 vtophys(&sc->ste_ldata->ste_rx_list[0])); 1284 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL); 1285 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL); 1286 1287 /* Set TX polling interval (defer until we TX first packet */ 1288 CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 0); 1289 1290 /* Load address of the TX list */ 1291 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL); 1292 ste_wait(sc); 1293 CSR_WRITE_4(sc, STE_TX_DMALIST_PTR, 0); 1294 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 1295 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 1296 ste_wait(sc); 1297 sc->ste_tx_prev_idx=-1; 1298 1299 /* Enable receiver and transmitter */ 1300 CSR_WRITE_2(sc, STE_MACCTL0, 0); 1301 CSR_WRITE_2(sc, STE_MACCTL1, 0); 1302 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_TX_ENABLE); 1303 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_RX_ENABLE); 1304 1305 /* Enable stats counters. */ 1306 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_STATS_ENABLE); 1307 1308 /* Enable interrupts. */ 1309 CSR_WRITE_2(sc, STE_ISR, 0xFFFF); 1310 CSR_WRITE_2(sc, STE_IMR, STE_INTRS); 1311 1312 /* Accept VLAN length packets */ 1313 CSR_WRITE_2(sc, STE_MAX_FRAMELEN, ETHER_MAX_LEN + EVL_ENCAPLEN); 1314 1315 ste_ifmedia_upd(ifp); 1316 1317 ifp->if_flags |= IFF_RUNNING; 1318 ifp->if_flags &= ~IFF_OACTIVE; 1319 1320 splx(s); 1321 1322 callout_reset(&sc->ste_stat_timer, hz, ste_stats_update, sc); 1323 1324 return; 1325 } 1326 1327 static void ste_stop(sc) 1328 struct ste_softc *sc; 1329 { 1330 int i; 1331 struct ifnet *ifp; 1332 1333 ifp = &sc->arpcom.ac_if; 1334 1335 callout_stop(&sc->ste_stat_timer); 1336 1337 CSR_WRITE_2(sc, STE_IMR, 0); 1338 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_TX_DISABLE); 1339 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_RX_DISABLE); 1340 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_STATS_DISABLE); 1341 STE_SETBIT2(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL); 1342 STE_SETBIT2(sc, STE_DMACTL, STE_DMACTL_RXDMA_STALL); 1343 ste_wait(sc); 1344 /* 1345 * Try really hard to stop the RX engine or under heavy RX 1346 * data chip will write into de-allocated memory. 1347 */ 1348 ste_reset(sc); 1349 1350 sc->ste_link = 0; 1351 1352 for (i = 0; i < STE_RX_LIST_CNT; i++) { 1353 if (sc->ste_cdata.ste_rx_chain[i].ste_mbuf != NULL) { 1354 m_freem(sc->ste_cdata.ste_rx_chain[i].ste_mbuf); 1355 sc->ste_cdata.ste_rx_chain[i].ste_mbuf = NULL; 1356 } 1357 } 1358 1359 for (i = 0; i < STE_TX_LIST_CNT; i++) { 1360 if (sc->ste_cdata.ste_tx_chain[i].ste_mbuf != NULL) { 1361 m_freem(sc->ste_cdata.ste_tx_chain[i].ste_mbuf); 1362 sc->ste_cdata.ste_tx_chain[i].ste_mbuf = NULL; 1363 } 1364 } 1365 1366 bzero(sc->ste_ldata, sizeof(struct ste_list_data)); 1367 1368 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 1369 1370 return; 1371 } 1372 1373 static void ste_reset(sc) 1374 struct ste_softc *sc; 1375 { 1376 int i; 1377 1378 STE_SETBIT4(sc, STE_ASICCTL, 1379 STE_ASICCTL_GLOBAL_RESET|STE_ASICCTL_RX_RESET| 1380 STE_ASICCTL_TX_RESET|STE_ASICCTL_DMA_RESET| 1381 STE_ASICCTL_FIFO_RESET|STE_ASICCTL_NETWORK_RESET| 1382 STE_ASICCTL_AUTOINIT_RESET|STE_ASICCTL_HOST_RESET| 1383 STE_ASICCTL_EXTRESET_RESET); 1384 1385 DELAY(100000); 1386 1387 for (i = 0; i < STE_TIMEOUT; i++) { 1388 if (!(CSR_READ_4(sc, STE_ASICCTL) & STE_ASICCTL_RESET_BUSY)) 1389 break; 1390 } 1391 1392 if (i == STE_TIMEOUT) 1393 printf("ste%d: global reset never completed\n", sc->ste_unit); 1394 1395 return; 1396 } 1397 1398 static int ste_ioctl(ifp, command, data, cr) 1399 struct ifnet *ifp; 1400 u_long command; 1401 caddr_t data; 1402 struct ucred *cr; 1403 { 1404 struct ste_softc *sc; 1405 struct ifreq *ifr; 1406 struct mii_data *mii; 1407 int error = 0, s; 1408 1409 s = splimp(); 1410 1411 sc = ifp->if_softc; 1412 ifr = (struct ifreq *)data; 1413 1414 switch(command) { 1415 case SIOCSIFADDR: 1416 case SIOCGIFADDR: 1417 case SIOCSIFMTU: 1418 error = ether_ioctl(ifp, command, data); 1419 break; 1420 case SIOCSIFFLAGS: 1421 if (ifp->if_flags & IFF_UP) { 1422 if (ifp->if_flags & IFF_RUNNING && 1423 ifp->if_flags & IFF_PROMISC && 1424 !(sc->ste_if_flags & IFF_PROMISC)) { 1425 STE_SETBIT1(sc, STE_RX_MODE, 1426 STE_RXMODE_PROMISC); 1427 } else if (ifp->if_flags & IFF_RUNNING && 1428 !(ifp->if_flags & IFF_PROMISC) && 1429 sc->ste_if_flags & IFF_PROMISC) { 1430 STE_CLRBIT1(sc, STE_RX_MODE, 1431 STE_RXMODE_PROMISC); 1432 } 1433 if (!(ifp->if_flags & IFF_RUNNING)) { 1434 sc->ste_tx_thresh = STE_TXSTART_THRESH; 1435 ste_init(sc); 1436 } 1437 } else { 1438 if (ifp->if_flags & IFF_RUNNING) 1439 ste_stop(sc); 1440 } 1441 sc->ste_if_flags = ifp->if_flags; 1442 error = 0; 1443 break; 1444 case SIOCADDMULTI: 1445 case SIOCDELMULTI: 1446 ste_setmulti(sc); 1447 error = 0; 1448 break; 1449 case SIOCGIFMEDIA: 1450 case SIOCSIFMEDIA: 1451 mii = device_get_softc(sc->ste_miibus); 1452 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1453 break; 1454 default: 1455 error = EINVAL; 1456 break; 1457 } 1458 1459 splx(s); 1460 1461 return(error); 1462 } 1463 1464 static int ste_encap(sc, c, m_head) 1465 struct ste_softc *sc; 1466 struct ste_chain *c; 1467 struct mbuf *m_head; 1468 { 1469 int frag = 0; 1470 struct ste_frag *f = NULL; 1471 struct mbuf *m; 1472 struct ste_desc *d; 1473 int total_len = 0; 1474 1475 d = c->ste_ptr; 1476 d->ste_ctl = 0; 1477 1478 encap_retry: 1479 for (m = m_head, frag = 0; m != NULL; m = m->m_next) { 1480 if (m->m_len != 0) { 1481 if (frag == STE_MAXFRAGS) 1482 break; 1483 total_len += m->m_len; 1484 f = &d->ste_frags[frag]; 1485 f->ste_addr = vtophys(mtod(m, vm_offset_t)); 1486 f->ste_len = m->m_len; 1487 frag++; 1488 } 1489 } 1490 1491 if (m != NULL) { 1492 struct mbuf *mn; 1493 1494 /* 1495 * We ran out of segments. We have to recopy this 1496 * mbuf chain first. Bail out if we can't get the 1497 * new buffers. Code borrowed from if_fxp.c. 1498 */ 1499 MGETHDR(mn, MB_DONTWAIT, MT_DATA); 1500 if (mn == NULL) { 1501 m_freem(m_head); 1502 return ENOMEM; 1503 } 1504 if (m_head->m_pkthdr.len > MHLEN) { 1505 MCLGET(mn, MB_DONTWAIT); 1506 if ((mn->m_flags & M_EXT) == 0) { 1507 m_freem(mn); 1508 m_freem(m_head); 1509 return ENOMEM; 1510 } 1511 } 1512 m_copydata(m_head, 0, m_head->m_pkthdr.len, 1513 mtod(mn, caddr_t)); 1514 mn->m_pkthdr.len = mn->m_len = m_head->m_pkthdr.len; 1515 m_freem(m_head); 1516 m_head = mn; 1517 goto encap_retry; 1518 } 1519 1520 c->ste_mbuf = m_head; 1521 d->ste_frags[frag - 1].ste_len |= STE_FRAG_LAST; 1522 d->ste_ctl = 1; 1523 1524 return(0); 1525 } 1526 1527 static void ste_start(ifp) 1528 struct ifnet *ifp; 1529 { 1530 struct ste_softc *sc; 1531 struct mbuf *m_head = NULL; 1532 struct ste_chain *cur_tx = NULL; 1533 int idx; 1534 1535 sc = ifp->if_softc; 1536 1537 if (!sc->ste_link) 1538 return; 1539 1540 if (ifp->if_flags & IFF_OACTIVE) 1541 return; 1542 1543 idx = sc->ste_cdata.ste_tx_prod; 1544 1545 while(sc->ste_cdata.ste_tx_chain[idx].ste_mbuf == NULL) { 1546 1547 if ((STE_TX_LIST_CNT - sc->ste_cdata.ste_tx_cnt) < 3) { 1548 ifp->if_flags |= IFF_OACTIVE; 1549 break; 1550 } 1551 1552 m_head = ifq_dequeue(&ifp->if_snd); 1553 if (m_head == NULL) 1554 break; 1555 1556 cur_tx = &sc->ste_cdata.ste_tx_chain[idx]; 1557 1558 if (ste_encap(sc, cur_tx, m_head) != 0) 1559 break; 1560 1561 cur_tx->ste_ptr->ste_next = 0; 1562 1563 if(sc->ste_tx_prev_idx < 0){ 1564 cur_tx->ste_ptr->ste_ctl = STE_TXCTL_DMAINTR | 1; 1565 /* Load address of the TX list */ 1566 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL); 1567 ste_wait(sc); 1568 1569 CSR_WRITE_4(sc, STE_TX_DMALIST_PTR, 1570 vtophys(&sc->ste_ldata->ste_tx_list[0])); 1571 1572 /* Set TX polling interval to start TX engine */ 1573 CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 64); 1574 1575 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 1576 ste_wait(sc); 1577 }else{ 1578 cur_tx->ste_ptr->ste_ctl = STE_TXCTL_DMAINTR | 1; 1579 sc->ste_cdata.ste_tx_chain[ 1580 sc->ste_tx_prev_idx].ste_ptr->ste_next 1581 = cur_tx->ste_phys; 1582 } 1583 1584 sc->ste_tx_prev_idx=idx; 1585 1586 BPF_MTAP(ifp, cur_tx->ste_mbuf); 1587 1588 STE_INC(idx, STE_TX_LIST_CNT); 1589 sc->ste_cdata.ste_tx_cnt++; 1590 ifp->if_timer = 5; 1591 sc->ste_cdata.ste_tx_prod = idx; 1592 } 1593 1594 return; 1595 } 1596 1597 static void ste_watchdog(ifp) 1598 struct ifnet *ifp; 1599 { 1600 struct ste_softc *sc; 1601 1602 sc = ifp->if_softc; 1603 1604 ifp->if_oerrors++; 1605 printf("ste%d: watchdog timeout\n", sc->ste_unit); 1606 1607 ste_txeoc(sc); 1608 ste_txeof(sc); 1609 ste_rxeof(sc); 1610 ste_reset(sc); 1611 ste_init(sc); 1612 1613 if (!ifq_is_empty(&ifp->if_snd)) 1614 ste_start(ifp); 1615 1616 return; 1617 } 1618 1619 static void ste_shutdown(dev) 1620 device_t dev; 1621 { 1622 struct ste_softc *sc; 1623 1624 sc = device_get_softc(dev); 1625 1626 ste_stop(sc); 1627 1628 return; 1629 } 1630