1 /* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: src/sys/pci/if_ste.c,v 1.14.2.9 2003/02/05 22:03:57 mbr Exp $ 33 * $DragonFly: src/sys/dev/netif/ste/if_ste.c,v 1.28 2005/06/20 15:10:41 joerg Exp $ 34 */ 35 36 #include <sys/param.h> 37 #include <sys/systm.h> 38 #include <sys/sockio.h> 39 #include <sys/mbuf.h> 40 #include <sys/malloc.h> 41 #include <sys/kernel.h> 42 #include <sys/socket.h> 43 #include <sys/thread2.h> 44 45 #include <net/if.h> 46 #include <net/ifq_var.h> 47 #include <net/if_arp.h> 48 #include <net/ethernet.h> 49 #include <net/if_dl.h> 50 #include <net/if_media.h> 51 #include <net/vlan/if_vlan_var.h> 52 53 #include <net/bpf.h> 54 55 #include <vm/vm.h> /* for vtophys */ 56 #include <vm/pmap.h> /* for vtophys */ 57 #include <machine/bus_memio.h> 58 #include <machine/bus_pio.h> 59 #include <machine/bus.h> 60 #include <machine/resource.h> 61 #include <sys/bus.h> 62 #include <sys/rman.h> 63 64 #include "../mii_layer/mii.h" 65 #include "../mii_layer/miivar.h" 66 67 #include <bus/pci/pcireg.h> 68 #include <bus/pci/pcivar.h> 69 70 /* "controller miibus0" required. See GENERIC if you get errors here. */ 71 #include "miibus_if.h" 72 73 #define STE_USEIOSPACE 74 75 #include "if_stereg.h" 76 77 /* 78 * Various supported device vendors/types and their names. 79 */ 80 static struct ste_type ste_devs[] = { 81 { ST_VENDORID, ST_DEVICEID_ST201, "Sundance ST201 10/100BaseTX" }, 82 { DL_VENDORID, DL_DEVICEID_550TX, "D-Link DFE-550TX 10/100BaseTX" }, 83 { 0, 0, NULL } 84 }; 85 86 static int ste_probe (device_t); 87 static int ste_attach (device_t); 88 static int ste_detach (device_t); 89 static void ste_init (void *); 90 static void ste_intr (void *); 91 static void ste_rxeof (struct ste_softc *); 92 static void ste_txeoc (struct ste_softc *); 93 static void ste_txeof (struct ste_softc *); 94 static void ste_stats_update (void *); 95 static void ste_stop (struct ste_softc *); 96 static void ste_reset (struct ste_softc *); 97 static int ste_ioctl (struct ifnet *, u_long, caddr_t, 98 struct ucred *); 99 static int ste_encap (struct ste_softc *, struct ste_chain *, 100 struct mbuf *); 101 static void ste_start (struct ifnet *); 102 static void ste_watchdog (struct ifnet *); 103 static void ste_shutdown (device_t); 104 static int ste_newbuf (struct ste_softc *, 105 struct ste_chain_onefrag *, 106 struct mbuf *); 107 static int ste_ifmedia_upd (struct ifnet *); 108 static void ste_ifmedia_sts (struct ifnet *, struct ifmediareq *); 109 110 static void ste_mii_sync (struct ste_softc *); 111 static void ste_mii_send (struct ste_softc *, u_int32_t, int); 112 static int ste_mii_readreg (struct ste_softc *, 113 struct ste_mii_frame *); 114 static int ste_mii_writereg (struct ste_softc *, 115 struct ste_mii_frame *); 116 static int ste_miibus_readreg (device_t, int, int); 117 static int ste_miibus_writereg (device_t, int, int, int); 118 static void ste_miibus_statchg (device_t); 119 120 static int ste_eeprom_wait (struct ste_softc *); 121 static int ste_read_eeprom (struct ste_softc *, caddr_t, int, 122 int, int); 123 static void ste_wait (struct ste_softc *); 124 static void ste_setmulti (struct ste_softc *); 125 static int ste_init_rx_list (struct ste_softc *); 126 static void ste_init_tx_list (struct ste_softc *); 127 128 #ifdef STE_USEIOSPACE 129 #define STE_RES SYS_RES_IOPORT 130 #define STE_RID STE_PCI_LOIO 131 #else 132 #define STE_RES SYS_RES_MEMORY 133 #define STE_RID STE_PCI_LOMEM 134 #endif 135 136 static device_method_t ste_methods[] = { 137 /* Device interface */ 138 DEVMETHOD(device_probe, ste_probe), 139 DEVMETHOD(device_attach, ste_attach), 140 DEVMETHOD(device_detach, ste_detach), 141 DEVMETHOD(device_shutdown, ste_shutdown), 142 143 /* bus interface */ 144 DEVMETHOD(bus_print_child, bus_generic_print_child), 145 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 146 147 /* MII interface */ 148 DEVMETHOD(miibus_readreg, ste_miibus_readreg), 149 DEVMETHOD(miibus_writereg, ste_miibus_writereg), 150 DEVMETHOD(miibus_statchg, ste_miibus_statchg), 151 152 { 0, 0 } 153 }; 154 155 static driver_t ste_driver = { 156 "ste", 157 ste_methods, 158 sizeof(struct ste_softc) 159 }; 160 161 static devclass_t ste_devclass; 162 163 DECLARE_DUMMY_MODULE(if_ste); 164 DRIVER_MODULE(if_ste, pci, ste_driver, ste_devclass, 0, 0); 165 DRIVER_MODULE(miibus, ste, miibus_driver, miibus_devclass, 0, 0); 166 167 #define STE_SETBIT4(sc, reg, x) \ 168 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | x) 169 170 #define STE_CLRBIT4(sc, reg, x) \ 171 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~x) 172 173 #define STE_SETBIT2(sc, reg, x) \ 174 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) | x) 175 176 #define STE_CLRBIT2(sc, reg, x) \ 177 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) & ~x) 178 179 #define STE_SETBIT1(sc, reg, x) \ 180 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | x) 181 182 #define STE_CLRBIT1(sc, reg, x) \ 183 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~x) 184 185 186 #define MII_SET(x) STE_SETBIT1(sc, STE_PHYCTL, x) 187 #define MII_CLR(x) STE_CLRBIT1(sc, STE_PHYCTL, x) 188 189 /* 190 * Sync the PHYs by setting data bit and strobing the clock 32 times. 191 */ 192 static void ste_mii_sync(sc) 193 struct ste_softc *sc; 194 { 195 int i; 196 197 MII_SET(STE_PHYCTL_MDIR|STE_PHYCTL_MDATA); 198 199 for (i = 0; i < 32; i++) { 200 MII_SET(STE_PHYCTL_MCLK); 201 DELAY(1); 202 MII_CLR(STE_PHYCTL_MCLK); 203 DELAY(1); 204 } 205 206 return; 207 } 208 209 /* 210 * Clock a series of bits through the MII. 211 */ 212 static void ste_mii_send(sc, bits, cnt) 213 struct ste_softc *sc; 214 u_int32_t bits; 215 int cnt; 216 { 217 int i; 218 219 MII_CLR(STE_PHYCTL_MCLK); 220 221 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 222 if (bits & i) { 223 MII_SET(STE_PHYCTL_MDATA); 224 } else { 225 MII_CLR(STE_PHYCTL_MDATA); 226 } 227 DELAY(1); 228 MII_CLR(STE_PHYCTL_MCLK); 229 DELAY(1); 230 MII_SET(STE_PHYCTL_MCLK); 231 } 232 } 233 234 /* 235 * Read an PHY register through the MII. 236 */ 237 static int ste_mii_readreg(sc, frame) 238 struct ste_softc *sc; 239 struct ste_mii_frame *frame; 240 241 { 242 int i, ack; 243 244 crit_enter(); 245 246 /* 247 * Set up frame for RX. 248 */ 249 frame->mii_stdelim = STE_MII_STARTDELIM; 250 frame->mii_opcode = STE_MII_READOP; 251 frame->mii_turnaround = 0; 252 frame->mii_data = 0; 253 254 CSR_WRITE_2(sc, STE_PHYCTL, 0); 255 /* 256 * Turn on data xmit. 257 */ 258 MII_SET(STE_PHYCTL_MDIR); 259 260 ste_mii_sync(sc); 261 262 /* 263 * Send command/address info. 264 */ 265 ste_mii_send(sc, frame->mii_stdelim, 2); 266 ste_mii_send(sc, frame->mii_opcode, 2); 267 ste_mii_send(sc, frame->mii_phyaddr, 5); 268 ste_mii_send(sc, frame->mii_regaddr, 5); 269 270 /* Turn off xmit. */ 271 MII_CLR(STE_PHYCTL_MDIR); 272 273 /* Idle bit */ 274 MII_CLR((STE_PHYCTL_MCLK|STE_PHYCTL_MDATA)); 275 DELAY(1); 276 MII_SET(STE_PHYCTL_MCLK); 277 DELAY(1); 278 279 /* Check for ack */ 280 MII_CLR(STE_PHYCTL_MCLK); 281 DELAY(1); 282 ack = CSR_READ_2(sc, STE_PHYCTL) & STE_PHYCTL_MDATA; 283 MII_SET(STE_PHYCTL_MCLK); 284 DELAY(1); 285 286 /* 287 * Now try reading data bits. If the ack failed, we still 288 * need to clock through 16 cycles to keep the PHY(s) in sync. 289 */ 290 if (ack) { 291 for(i = 0; i < 16; i++) { 292 MII_CLR(STE_PHYCTL_MCLK); 293 DELAY(1); 294 MII_SET(STE_PHYCTL_MCLK); 295 DELAY(1); 296 } 297 goto fail; 298 } 299 300 for (i = 0x8000; i; i >>= 1) { 301 MII_CLR(STE_PHYCTL_MCLK); 302 DELAY(1); 303 if (!ack) { 304 if (CSR_READ_2(sc, STE_PHYCTL) & STE_PHYCTL_MDATA) 305 frame->mii_data |= i; 306 DELAY(1); 307 } 308 MII_SET(STE_PHYCTL_MCLK); 309 DELAY(1); 310 } 311 312 fail: 313 314 MII_CLR(STE_PHYCTL_MCLK); 315 DELAY(1); 316 MII_SET(STE_PHYCTL_MCLK); 317 DELAY(1); 318 319 crit_exit(); 320 321 if (ack) 322 return(1); 323 return(0); 324 } 325 326 /* 327 * Write to a PHY register through the MII. 328 */ 329 static int ste_mii_writereg(sc, frame) 330 struct ste_softc *sc; 331 struct ste_mii_frame *frame; 332 333 { 334 335 crit_enter(); 336 /* 337 * Set up frame for TX. 338 */ 339 340 frame->mii_stdelim = STE_MII_STARTDELIM; 341 frame->mii_opcode = STE_MII_WRITEOP; 342 frame->mii_turnaround = STE_MII_TURNAROUND; 343 344 /* 345 * Turn on data output. 346 */ 347 MII_SET(STE_PHYCTL_MDIR); 348 349 ste_mii_sync(sc); 350 351 ste_mii_send(sc, frame->mii_stdelim, 2); 352 ste_mii_send(sc, frame->mii_opcode, 2); 353 ste_mii_send(sc, frame->mii_phyaddr, 5); 354 ste_mii_send(sc, frame->mii_regaddr, 5); 355 ste_mii_send(sc, frame->mii_turnaround, 2); 356 ste_mii_send(sc, frame->mii_data, 16); 357 358 /* Idle bit. */ 359 MII_SET(STE_PHYCTL_MCLK); 360 DELAY(1); 361 MII_CLR(STE_PHYCTL_MCLK); 362 DELAY(1); 363 364 /* 365 * Turn off xmit. 366 */ 367 MII_CLR(STE_PHYCTL_MDIR); 368 369 crit_exit(); 370 371 return(0); 372 } 373 374 static int ste_miibus_readreg(dev, phy, reg) 375 device_t dev; 376 int phy, reg; 377 { 378 struct ste_softc *sc; 379 struct ste_mii_frame frame; 380 381 sc = device_get_softc(dev); 382 383 if ( sc->ste_one_phy && phy != 0 ) 384 return (0); 385 386 bzero((char *)&frame, sizeof(frame)); 387 388 frame.mii_phyaddr = phy; 389 frame.mii_regaddr = reg; 390 ste_mii_readreg(sc, &frame); 391 392 return(frame.mii_data); 393 } 394 395 static int ste_miibus_writereg(dev, phy, reg, data) 396 device_t dev; 397 int phy, reg, data; 398 { 399 struct ste_softc *sc; 400 struct ste_mii_frame frame; 401 402 sc = device_get_softc(dev); 403 bzero((char *)&frame, sizeof(frame)); 404 405 frame.mii_phyaddr = phy; 406 frame.mii_regaddr = reg; 407 frame.mii_data = data; 408 409 ste_mii_writereg(sc, &frame); 410 411 return(0); 412 } 413 414 static void ste_miibus_statchg(dev) 415 device_t dev; 416 { 417 struct ste_softc *sc; 418 struct mii_data *mii; 419 int i; 420 421 sc = device_get_softc(dev); 422 mii = device_get_softc(sc->ste_miibus); 423 424 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 425 STE_SETBIT2(sc, STE_MACCTL0, STE_MACCTL0_FULLDUPLEX); 426 } else { 427 STE_CLRBIT2(sc, STE_MACCTL0, STE_MACCTL0_FULLDUPLEX); 428 } 429 430 STE_SETBIT4(sc, STE_ASICCTL,STE_ASICCTL_RX_RESET | 431 STE_ASICCTL_TX_RESET); 432 for (i = 0; i < STE_TIMEOUT; i++) { 433 if (!(CSR_READ_4(sc, STE_ASICCTL) & STE_ASICCTL_RESET_BUSY)) 434 break; 435 } 436 if (i == STE_TIMEOUT) 437 if_printf(&sc->arpcom.ac_if, "rx reset never completed\n"); 438 439 return; 440 } 441 442 static int ste_ifmedia_upd(ifp) 443 struct ifnet *ifp; 444 { 445 struct ste_softc *sc; 446 struct mii_data *mii; 447 448 sc = ifp->if_softc; 449 mii = device_get_softc(sc->ste_miibus); 450 sc->ste_link = 0; 451 if (mii->mii_instance) { 452 struct mii_softc *miisc; 453 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 454 miisc = LIST_NEXT(miisc, mii_list)) 455 mii_phy_reset(miisc); 456 } 457 mii_mediachg(mii); 458 459 return(0); 460 } 461 462 static void ste_ifmedia_sts(ifp, ifmr) 463 struct ifnet *ifp; 464 struct ifmediareq *ifmr; 465 { 466 struct ste_softc *sc; 467 struct mii_data *mii; 468 469 sc = ifp->if_softc; 470 mii = device_get_softc(sc->ste_miibus); 471 472 mii_pollstat(mii); 473 ifmr->ifm_active = mii->mii_media_active; 474 ifmr->ifm_status = mii->mii_media_status; 475 476 return; 477 } 478 479 static void ste_wait(sc) 480 struct ste_softc *sc; 481 { 482 int i; 483 484 for (i = 0; i < STE_TIMEOUT; i++) { 485 if (!(CSR_READ_4(sc, STE_DMACTL) & STE_DMACTL_DMA_HALTINPROG)) 486 break; 487 } 488 489 if (i == STE_TIMEOUT) 490 if_printf(&sc->arpcom.ac_if, "command never completed!\n"); 491 492 return; 493 } 494 495 /* 496 * The EEPROM is slow: give it time to come ready after issuing 497 * it a command. 498 */ 499 static int ste_eeprom_wait(sc) 500 struct ste_softc *sc; 501 { 502 int i; 503 504 DELAY(1000); 505 506 for (i = 0; i < 100; i++) { 507 if (CSR_READ_2(sc, STE_EEPROM_CTL) & STE_EECTL_BUSY) 508 DELAY(1000); 509 else 510 break; 511 } 512 513 if (i == 100) { 514 if_printf(&sc->arpcom.ac_if, "eeprom failed to come ready\n"); 515 return(1); 516 } 517 518 return(0); 519 } 520 521 /* 522 * Read a sequence of words from the EEPROM. Note that ethernet address 523 * data is stored in the EEPROM in network byte order. 524 */ 525 static int ste_read_eeprom(sc, dest, off, cnt, swap) 526 struct ste_softc *sc; 527 caddr_t dest; 528 int off; 529 int cnt; 530 int swap; 531 { 532 int err = 0, i; 533 u_int16_t word = 0, *ptr; 534 535 if (ste_eeprom_wait(sc)) 536 return(1); 537 538 for (i = 0; i < cnt; i++) { 539 CSR_WRITE_2(sc, STE_EEPROM_CTL, STE_EEOPCODE_READ | (off + i)); 540 err = ste_eeprom_wait(sc); 541 if (err) 542 break; 543 word = CSR_READ_2(sc, STE_EEPROM_DATA); 544 ptr = (u_int16_t *)(dest + (i * 2)); 545 if (swap) 546 *ptr = ntohs(word); 547 else 548 *ptr = word; 549 } 550 551 return(err ? 1 : 0); 552 } 553 554 static void ste_setmulti(sc) 555 struct ste_softc *sc; 556 { 557 struct ifnet *ifp; 558 int h = 0; 559 u_int32_t hashes[2] = { 0, 0 }; 560 struct ifmultiaddr *ifma; 561 562 ifp = &sc->arpcom.ac_if; 563 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 564 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_ALLMULTI); 565 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_MULTIHASH); 566 return; 567 } 568 569 /* first, zot all the existing hash bits */ 570 CSR_WRITE_2(sc, STE_MAR0, 0); 571 CSR_WRITE_2(sc, STE_MAR1, 0); 572 CSR_WRITE_2(sc, STE_MAR2, 0); 573 CSR_WRITE_2(sc, STE_MAR3, 0); 574 575 /* now program new ones */ 576 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 577 if (ifma->ifma_addr->sa_family != AF_LINK) 578 continue; 579 h = ether_crc32_be( 580 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 581 ETHER_ADDR_LEN) & 0x3f; 582 if (h < 32) 583 hashes[0] |= (1 << h); 584 else 585 hashes[1] |= (1 << (h - 32)); 586 } 587 588 CSR_WRITE_2(sc, STE_MAR0, hashes[0] & 0xFFFF); 589 CSR_WRITE_2(sc, STE_MAR1, (hashes[0] >> 16) & 0xFFFF); 590 CSR_WRITE_2(sc, STE_MAR2, hashes[1] & 0xFFFF); 591 CSR_WRITE_2(sc, STE_MAR3, (hashes[1] >> 16) & 0xFFFF); 592 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_ALLMULTI); 593 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_MULTIHASH); 594 595 return; 596 } 597 598 static void ste_intr(xsc) 599 void *xsc; 600 { 601 struct ste_softc *sc; 602 struct ifnet *ifp; 603 u_int16_t status; 604 605 sc = xsc; 606 ifp = &sc->arpcom.ac_if; 607 608 /* See if this is really our interrupt. */ 609 if (!(CSR_READ_2(sc, STE_ISR) & STE_ISR_INTLATCH)) 610 return; 611 612 for (;;) { 613 status = CSR_READ_2(sc, STE_ISR_ACK); 614 615 if (!(status & STE_INTRS)) 616 break; 617 618 if (status & STE_ISR_RX_DMADONE) 619 ste_rxeof(sc); 620 621 if (status & STE_ISR_TX_DMADONE) 622 ste_txeof(sc); 623 624 if (status & STE_ISR_TX_DONE) 625 ste_txeoc(sc); 626 627 if (status & STE_ISR_STATS_OFLOW) { 628 callout_stop(&sc->ste_stat_timer); 629 ste_stats_update(sc); 630 } 631 632 if (status & STE_ISR_LINKEVENT) 633 mii_pollstat(device_get_softc(sc->ste_miibus)); 634 635 if (status & STE_ISR_HOSTERR) { 636 ste_reset(sc); 637 ste_init(sc); 638 } 639 } 640 641 /* Re-enable interrupts */ 642 CSR_WRITE_2(sc, STE_IMR, STE_INTRS); 643 644 if (!ifq_is_empty(&ifp->if_snd)) 645 ste_start(ifp); 646 647 return; 648 } 649 650 /* 651 * A frame has been uploaded: pass the resulting mbuf chain up to 652 * the higher level protocols. 653 */ 654 static void ste_rxeof(sc) 655 struct ste_softc *sc; 656 { 657 struct mbuf *m; 658 struct ifnet *ifp; 659 struct ste_chain_onefrag *cur_rx; 660 int total_len = 0, count=0; 661 u_int32_t rxstat; 662 663 ifp = &sc->arpcom.ac_if; 664 665 while((rxstat = sc->ste_cdata.ste_rx_head->ste_ptr->ste_status) 666 & STE_RXSTAT_DMADONE) { 667 if ((STE_RX_LIST_CNT - count) < 3) { 668 break; 669 } 670 671 cur_rx = sc->ste_cdata.ste_rx_head; 672 sc->ste_cdata.ste_rx_head = cur_rx->ste_next; 673 674 /* 675 * If an error occurs, update stats, clear the 676 * status word and leave the mbuf cluster in place: 677 * it should simply get re-used next time this descriptor 678 * comes up in the ring. 679 */ 680 if (rxstat & STE_RXSTAT_FRAME_ERR) { 681 ifp->if_ierrors++; 682 cur_rx->ste_ptr->ste_status = 0; 683 continue; 684 } 685 686 /* 687 * If there error bit was not set, the upload complete 688 * bit should be set which means we have a valid packet. 689 * If not, something truly strange has happened. 690 */ 691 if (!(rxstat & STE_RXSTAT_DMADONE)) { 692 if_printf(ifp, "bad receive status -- packet dropped"); 693 ifp->if_ierrors++; 694 cur_rx->ste_ptr->ste_status = 0; 695 continue; 696 } 697 698 /* No errors; receive the packet. */ 699 m = cur_rx->ste_mbuf; 700 total_len = cur_rx->ste_ptr->ste_status & STE_RXSTAT_FRAMELEN; 701 702 /* 703 * Try to conjure up a new mbuf cluster. If that 704 * fails, it means we have an out of memory condition and 705 * should leave the buffer in place and continue. This will 706 * result in a lost packet, but there's little else we 707 * can do in this situation. 708 */ 709 if (ste_newbuf(sc, cur_rx, NULL) == ENOBUFS) { 710 ifp->if_ierrors++; 711 cur_rx->ste_ptr->ste_status = 0; 712 continue; 713 } 714 715 ifp->if_ipackets++; 716 m->m_pkthdr.rcvif = ifp; 717 m->m_pkthdr.len = m->m_len = total_len; 718 719 (*ifp->if_input)(ifp, m); 720 721 cur_rx->ste_ptr->ste_status = 0; 722 count++; 723 } 724 725 return; 726 } 727 728 static void ste_txeoc(sc) 729 struct ste_softc *sc; 730 { 731 u_int8_t txstat; 732 struct ifnet *ifp; 733 734 ifp = &sc->arpcom.ac_if; 735 736 while ((txstat = CSR_READ_1(sc, STE_TX_STATUS)) & 737 STE_TXSTATUS_TXDONE) { 738 if (txstat & STE_TXSTATUS_UNDERRUN || 739 txstat & STE_TXSTATUS_EXCESSCOLLS || 740 txstat & STE_TXSTATUS_RECLAIMERR) { 741 ifp->if_oerrors++; 742 if_printf(ifp, "transmission error: %x\n", txstat); 743 744 ste_reset(sc); 745 ste_init(sc); 746 747 if (txstat & STE_TXSTATUS_UNDERRUN && 748 sc->ste_tx_thresh < STE_PACKET_SIZE) { 749 sc->ste_tx_thresh += STE_MIN_FRAMELEN; 750 if_printf(ifp, "tx underrun, increasing tx" 751 " start threshold to %d bytes\n", 752 sc->ste_tx_thresh); 753 } 754 CSR_WRITE_2(sc, STE_TX_STARTTHRESH, sc->ste_tx_thresh); 755 CSR_WRITE_2(sc, STE_TX_RECLAIM_THRESH, 756 (STE_PACKET_SIZE >> 4)); 757 } 758 ste_init(sc); 759 CSR_WRITE_2(sc, STE_TX_STATUS, txstat); 760 } 761 762 return; 763 } 764 765 static void ste_txeof(sc) 766 struct ste_softc *sc; 767 { 768 struct ste_chain *cur_tx = NULL; 769 struct ifnet *ifp; 770 int idx; 771 772 ifp = &sc->arpcom.ac_if; 773 774 idx = sc->ste_cdata.ste_tx_cons; 775 while(idx != sc->ste_cdata.ste_tx_prod) { 776 cur_tx = &sc->ste_cdata.ste_tx_chain[idx]; 777 778 if (!(cur_tx->ste_ptr->ste_ctl & STE_TXCTL_DMADONE)) 779 break; 780 781 if (cur_tx->ste_mbuf != NULL) { 782 m_freem(cur_tx->ste_mbuf); 783 cur_tx->ste_mbuf = NULL; 784 } 785 786 ifp->if_opackets++; 787 788 sc->ste_cdata.ste_tx_cnt--; 789 STE_INC(idx, STE_TX_LIST_CNT); 790 ifp->if_timer = 0; 791 } 792 793 sc->ste_cdata.ste_tx_cons = idx; 794 795 if (cur_tx != NULL) 796 ifp->if_flags &= ~IFF_OACTIVE; 797 798 return; 799 } 800 801 static void ste_stats_update(xsc) 802 void *xsc; 803 { 804 struct ste_softc *sc; 805 struct ifnet *ifp; 806 struct mii_data *mii; 807 808 crit_enter(); 809 810 sc = xsc; 811 ifp = &sc->arpcom.ac_if; 812 mii = device_get_softc(sc->ste_miibus); 813 814 ifp->if_collisions += CSR_READ_1(sc, STE_LATE_COLLS) 815 + CSR_READ_1(sc, STE_MULTI_COLLS) 816 + CSR_READ_1(sc, STE_SINGLE_COLLS); 817 818 if (!sc->ste_link) { 819 mii_pollstat(mii); 820 if (mii->mii_media_status & IFM_ACTIVE && 821 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 822 sc->ste_link++; 823 /* 824 * we don't get a call-back on re-init so do it 825 * otherwise we get stuck in the wrong link state 826 */ 827 ste_miibus_statchg(sc->ste_dev); 828 if (!ifq_is_empty(&ifp->if_snd)) 829 ste_start(ifp); 830 } 831 } 832 833 callout_reset(&sc->ste_stat_timer, hz, ste_stats_update, sc); 834 crit_exit(); 835 836 return; 837 } 838 839 840 /* 841 * Probe for a Sundance ST201 chip. Check the PCI vendor and device 842 * IDs against our list and return a device name if we find a match. 843 */ 844 static int ste_probe(dev) 845 device_t dev; 846 { 847 struct ste_type *t; 848 849 t = ste_devs; 850 851 while(t->ste_name != NULL) { 852 if ((pci_get_vendor(dev) == t->ste_vid) && 853 (pci_get_device(dev) == t->ste_did)) { 854 device_set_desc(dev, t->ste_name); 855 return(0); 856 } 857 t++; 858 } 859 860 return(ENXIO); 861 } 862 863 /* 864 * Attach the interface. Allocate softc structures, do ifmedia 865 * setup and ethernet/BPF attach. 866 */ 867 static int ste_attach(dev) 868 device_t dev; 869 { 870 struct ste_softc *sc; 871 struct ifnet *ifp; 872 int error = 0, rid; 873 uint8_t eaddr[ETHER_ADDR_LEN]; 874 875 sc = device_get_softc(dev); 876 sc->ste_dev = dev; 877 878 /* 879 * Only use one PHY since this chip reports multiple 880 * Note on the DFE-550 the PHY is at 1 on the DFE-580 881 * it is at 0 & 1. It is rev 0x12. 882 */ 883 if (pci_get_vendor(dev) == DL_VENDORID && 884 pci_get_device(dev) == DL_DEVICEID_550TX && 885 pci_get_revid(dev) == 0x12 ) 886 sc->ste_one_phy = 1; 887 888 /* 889 * Handle power management nonsense. 890 */ 891 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 892 u_int32_t iobase, membase, irq; 893 894 /* Save important PCI config data. */ 895 iobase = pci_read_config(dev, STE_PCI_LOIO, 4); 896 membase = pci_read_config(dev, STE_PCI_LOMEM, 4); 897 irq = pci_read_config(dev, STE_PCI_INTLINE, 4); 898 899 /* Reset the power state. */ 900 device_printf(dev, "chip is in D%d power mode " 901 "-- setting to D0\n", pci_get_powerstate(dev)); 902 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 903 904 /* Restore PCI config data. */ 905 pci_write_config(dev, STE_PCI_LOIO, iobase, 4); 906 pci_write_config(dev, STE_PCI_LOMEM, membase, 4); 907 pci_write_config(dev, STE_PCI_INTLINE, irq, 4); 908 } 909 910 /* 911 * Map control/status registers. 912 */ 913 pci_enable_busmaster(dev); 914 915 rid = STE_RID; 916 sc->ste_res = bus_alloc_resource_any(dev, STE_RES, &rid, RF_ACTIVE); 917 918 if (sc->ste_res == NULL) { 919 device_printf(dev, "couldn't map ports/memory\n"); 920 error = ENXIO; 921 goto fail; 922 } 923 924 sc->ste_btag = rman_get_bustag(sc->ste_res); 925 sc->ste_bhandle = rman_get_bushandle(sc->ste_res); 926 927 rid = 0; 928 sc->ste_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 929 RF_SHAREABLE | RF_ACTIVE); 930 931 if (sc->ste_irq == NULL) { 932 device_printf(dev, "couldn't map interrupt\n"); 933 error = ENXIO; 934 goto fail; 935 } 936 937 callout_init(&sc->ste_stat_timer); 938 939 ifp = &sc->arpcom.ac_if; 940 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 941 942 /* Reset the adapter. */ 943 ste_reset(sc); 944 945 /* 946 * Get station address from the EEPROM. 947 */ 948 if (ste_read_eeprom(sc, eaddr, STE_EEADDR_NODE0, 3, 0)) { 949 device_printf(dev, "failed to read station address\n"); 950 error = ENXIO; 951 goto fail; 952 } 953 954 /* Allocate the descriptor queues. */ 955 sc->ste_ldata = contigmalloc(sizeof(struct ste_list_data), M_DEVBUF, 956 M_WAITOK, 0, 0xffffffff, PAGE_SIZE, 0); 957 958 if (sc->ste_ldata == NULL) { 959 device_printf(dev, "no memory for list buffers!\n"); 960 error = ENXIO; 961 goto fail; 962 } 963 964 bzero(sc->ste_ldata, sizeof(struct ste_list_data)); 965 966 /* Do MII setup. */ 967 if (mii_phy_probe(dev, &sc->ste_miibus, 968 ste_ifmedia_upd, ste_ifmedia_sts)) { 969 device_printf(dev, "MII without any phy!\n"); 970 error = ENXIO; 971 goto fail; 972 } 973 974 ifp->if_softc = sc; 975 ifp->if_mtu = ETHERMTU; 976 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 977 ifp->if_ioctl = ste_ioctl; 978 ifp->if_start = ste_start; 979 ifp->if_watchdog = ste_watchdog; 980 ifp->if_init = ste_init; 981 ifp->if_baudrate = 10000000; 982 ifq_set_maxlen(&ifp->if_snd, STE_TX_LIST_CNT - 1); 983 ifq_set_ready(&ifp->if_snd); 984 985 sc->ste_tx_thresh = STE_TXSTART_THRESH; 986 987 /* 988 * Call MI attach routine. 989 */ 990 ether_ifattach(ifp, eaddr); 991 992 /* 993 * Tell the upper layer(s) we support long frames. 994 */ 995 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 996 997 error = bus_setup_intr(dev, sc->ste_irq, INTR_TYPE_NET, 998 ste_intr, sc, &sc->ste_intrhand, NULL); 999 if (error) { 1000 device_printf(dev, "couldn't set up irq\n"); 1001 ether_ifdetach(ifp); 1002 goto fail; 1003 } 1004 1005 return 0; 1006 1007 fail: 1008 ste_detach(dev); 1009 return(error); 1010 } 1011 1012 static int ste_detach(dev) 1013 device_t dev; 1014 { 1015 struct ste_softc *sc; 1016 struct ifnet *ifp; 1017 1018 crit_enter(); 1019 1020 sc = device_get_softc(dev); 1021 ifp = &sc->arpcom.ac_if; 1022 1023 if (device_is_attached(dev)) { 1024 if (bus_child_present(dev)) 1025 ste_stop(sc); 1026 ether_ifdetach(ifp); 1027 } 1028 if (sc->ste_miibus != NULL) 1029 device_delete_child(dev, sc->ste_miibus); 1030 bus_generic_detach(dev); 1031 1032 if (sc->ste_intrhand != NULL) 1033 bus_teardown_intr(dev, sc->ste_irq, sc->ste_intrhand); 1034 1035 crit_exit(); 1036 1037 if (sc->ste_irq != NULL) 1038 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq); 1039 if (sc->ste_res != NULL) 1040 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res); 1041 if (sc->ste_ldata != NULL) { 1042 contigfree(sc->ste_ldata, sizeof(struct ste_list_data), 1043 M_DEVBUF); 1044 } 1045 1046 return(0); 1047 } 1048 1049 static int ste_newbuf(sc, c, m) 1050 struct ste_softc *sc; 1051 struct ste_chain_onefrag *c; 1052 struct mbuf *m; 1053 { 1054 struct mbuf *m_new = NULL; 1055 1056 if (m == NULL) { 1057 MGETHDR(m_new, MB_DONTWAIT, MT_DATA); 1058 if (m_new == NULL) 1059 return(ENOBUFS); 1060 MCLGET(m_new, MB_DONTWAIT); 1061 if (!(m_new->m_flags & M_EXT)) { 1062 m_freem(m_new); 1063 return(ENOBUFS); 1064 } 1065 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1066 } else { 1067 m_new = m; 1068 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1069 m_new->m_data = m_new->m_ext.ext_buf; 1070 } 1071 1072 m_adj(m_new, ETHER_ALIGN); 1073 1074 c->ste_mbuf = m_new; 1075 c->ste_ptr->ste_status = 0; 1076 c->ste_ptr->ste_frag.ste_addr = vtophys(mtod(m_new, caddr_t)); 1077 c->ste_ptr->ste_frag.ste_len = (1536 + EVL_ENCAPLEN) | STE_FRAG_LAST; 1078 1079 return(0); 1080 } 1081 1082 static int ste_init_rx_list(sc) 1083 struct ste_softc *sc; 1084 { 1085 struct ste_chain_data *cd; 1086 struct ste_list_data *ld; 1087 int i; 1088 1089 cd = &sc->ste_cdata; 1090 ld = sc->ste_ldata; 1091 1092 for (i = 0; i < STE_RX_LIST_CNT; i++) { 1093 cd->ste_rx_chain[i].ste_ptr = &ld->ste_rx_list[i]; 1094 if (ste_newbuf(sc, &cd->ste_rx_chain[i], NULL) == ENOBUFS) 1095 return(ENOBUFS); 1096 if (i == (STE_RX_LIST_CNT - 1)) { 1097 cd->ste_rx_chain[i].ste_next = 1098 &cd->ste_rx_chain[0]; 1099 ld->ste_rx_list[i].ste_next = 1100 vtophys(&ld->ste_rx_list[0]); 1101 } else { 1102 cd->ste_rx_chain[i].ste_next = 1103 &cd->ste_rx_chain[i + 1]; 1104 ld->ste_rx_list[i].ste_next = 1105 vtophys(&ld->ste_rx_list[i + 1]); 1106 } 1107 ld->ste_rx_list[i].ste_status = 0; 1108 } 1109 1110 cd->ste_rx_head = &cd->ste_rx_chain[0]; 1111 1112 return(0); 1113 } 1114 1115 static void ste_init_tx_list(sc) 1116 struct ste_softc *sc; 1117 { 1118 struct ste_chain_data *cd; 1119 struct ste_list_data *ld; 1120 int i; 1121 1122 cd = &sc->ste_cdata; 1123 ld = sc->ste_ldata; 1124 for (i = 0; i < STE_TX_LIST_CNT; i++) { 1125 cd->ste_tx_chain[i].ste_ptr = &ld->ste_tx_list[i]; 1126 cd->ste_tx_chain[i].ste_ptr->ste_next = 0; 1127 cd->ste_tx_chain[i].ste_ptr->ste_ctl = 0; 1128 cd->ste_tx_chain[i].ste_phys = vtophys(&ld->ste_tx_list[i]); 1129 if (i == (STE_TX_LIST_CNT - 1)) 1130 cd->ste_tx_chain[i].ste_next = 1131 &cd->ste_tx_chain[0]; 1132 else 1133 cd->ste_tx_chain[i].ste_next = 1134 &cd->ste_tx_chain[i + 1]; 1135 if (i == 0) 1136 cd->ste_tx_chain[i].ste_prev = 1137 &cd->ste_tx_chain[STE_TX_LIST_CNT - 1]; 1138 else 1139 cd->ste_tx_chain[i].ste_prev = 1140 &cd->ste_tx_chain[i - 1]; 1141 } 1142 1143 cd->ste_tx_prod = 0; 1144 cd->ste_tx_cons = 0; 1145 cd->ste_tx_cnt = 0; 1146 1147 return; 1148 } 1149 1150 static void ste_init(xsc) 1151 void *xsc; 1152 { 1153 struct ste_softc *sc; 1154 int i; 1155 struct ifnet *ifp; 1156 struct mii_data *mii; 1157 1158 crit_enter(); 1159 1160 sc = xsc; 1161 ifp = &sc->arpcom.ac_if; 1162 mii = device_get_softc(sc->ste_miibus); 1163 1164 ste_stop(sc); 1165 1166 /* Init our MAC address */ 1167 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1168 CSR_WRITE_1(sc, STE_PAR0 + i, sc->arpcom.ac_enaddr[i]); 1169 } 1170 1171 /* Init RX list */ 1172 if (ste_init_rx_list(sc) == ENOBUFS) { 1173 if_printf(ifp, "initialization failed: no " 1174 "memory for RX buffers\n"); 1175 ste_stop(sc); 1176 crit_exit(); 1177 return; 1178 } 1179 1180 /* Set RX polling interval */ 1181 CSR_WRITE_1(sc, STE_RX_DMAPOLL_PERIOD, 1); 1182 1183 /* Init TX descriptors */ 1184 ste_init_tx_list(sc); 1185 1186 /* Set the TX freethresh value */ 1187 CSR_WRITE_1(sc, STE_TX_DMABURST_THRESH, STE_PACKET_SIZE >> 8); 1188 1189 /* Set the TX start threshold for best performance. */ 1190 CSR_WRITE_2(sc, STE_TX_STARTTHRESH, sc->ste_tx_thresh); 1191 1192 /* Set the TX reclaim threshold. */ 1193 CSR_WRITE_1(sc, STE_TX_RECLAIM_THRESH, (STE_PACKET_SIZE >> 4)); 1194 1195 /* Set up the RX filter. */ 1196 CSR_WRITE_1(sc, STE_RX_MODE, STE_RXMODE_UNICAST); 1197 1198 /* If we want promiscuous mode, set the allframes bit. */ 1199 if (ifp->if_flags & IFF_PROMISC) { 1200 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_PROMISC); 1201 } else { 1202 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_PROMISC); 1203 } 1204 1205 /* Set capture broadcast bit to accept broadcast frames. */ 1206 if (ifp->if_flags & IFF_BROADCAST) { 1207 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_BROADCAST); 1208 } else { 1209 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_BROADCAST); 1210 } 1211 1212 ste_setmulti(sc); 1213 1214 /* Load the address of the RX list. */ 1215 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_STALL); 1216 ste_wait(sc); 1217 CSR_WRITE_4(sc, STE_RX_DMALIST_PTR, 1218 vtophys(&sc->ste_ldata->ste_rx_list[0])); 1219 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL); 1220 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL); 1221 1222 /* Set TX polling interval (defer until we TX first packet */ 1223 CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 0); 1224 1225 /* Load address of the TX list */ 1226 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL); 1227 ste_wait(sc); 1228 CSR_WRITE_4(sc, STE_TX_DMALIST_PTR, 0); 1229 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 1230 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 1231 ste_wait(sc); 1232 sc->ste_tx_prev_idx=-1; 1233 1234 /* Enable receiver and transmitter */ 1235 CSR_WRITE_2(sc, STE_MACCTL0, 0); 1236 CSR_WRITE_2(sc, STE_MACCTL1, 0); 1237 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_TX_ENABLE); 1238 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_RX_ENABLE); 1239 1240 /* Enable stats counters. */ 1241 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_STATS_ENABLE); 1242 1243 /* Enable interrupts. */ 1244 CSR_WRITE_2(sc, STE_ISR, 0xFFFF); 1245 CSR_WRITE_2(sc, STE_IMR, STE_INTRS); 1246 1247 /* Accept VLAN length packets */ 1248 CSR_WRITE_2(sc, STE_MAX_FRAMELEN, ETHER_MAX_LEN + EVL_ENCAPLEN); 1249 1250 ste_ifmedia_upd(ifp); 1251 1252 ifp->if_flags |= IFF_RUNNING; 1253 ifp->if_flags &= ~IFF_OACTIVE; 1254 1255 crit_exit(); 1256 1257 callout_reset(&sc->ste_stat_timer, hz, ste_stats_update, sc); 1258 1259 return; 1260 } 1261 1262 static void ste_stop(sc) 1263 struct ste_softc *sc; 1264 { 1265 int i; 1266 struct ifnet *ifp; 1267 1268 ifp = &sc->arpcom.ac_if; 1269 1270 callout_stop(&sc->ste_stat_timer); 1271 1272 CSR_WRITE_2(sc, STE_IMR, 0); 1273 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_TX_DISABLE); 1274 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_RX_DISABLE); 1275 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_STATS_DISABLE); 1276 STE_SETBIT2(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL); 1277 STE_SETBIT2(sc, STE_DMACTL, STE_DMACTL_RXDMA_STALL); 1278 ste_wait(sc); 1279 /* 1280 * Try really hard to stop the RX engine or under heavy RX 1281 * data chip will write into de-allocated memory. 1282 */ 1283 ste_reset(sc); 1284 1285 sc->ste_link = 0; 1286 1287 for (i = 0; i < STE_RX_LIST_CNT; i++) { 1288 if (sc->ste_cdata.ste_rx_chain[i].ste_mbuf != NULL) { 1289 m_freem(sc->ste_cdata.ste_rx_chain[i].ste_mbuf); 1290 sc->ste_cdata.ste_rx_chain[i].ste_mbuf = NULL; 1291 } 1292 } 1293 1294 for (i = 0; i < STE_TX_LIST_CNT; i++) { 1295 if (sc->ste_cdata.ste_tx_chain[i].ste_mbuf != NULL) { 1296 m_freem(sc->ste_cdata.ste_tx_chain[i].ste_mbuf); 1297 sc->ste_cdata.ste_tx_chain[i].ste_mbuf = NULL; 1298 } 1299 } 1300 1301 bzero(sc->ste_ldata, sizeof(struct ste_list_data)); 1302 1303 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 1304 1305 return; 1306 } 1307 1308 static void ste_reset(sc) 1309 struct ste_softc *sc; 1310 { 1311 int i; 1312 1313 STE_SETBIT4(sc, STE_ASICCTL, 1314 STE_ASICCTL_GLOBAL_RESET|STE_ASICCTL_RX_RESET| 1315 STE_ASICCTL_TX_RESET|STE_ASICCTL_DMA_RESET| 1316 STE_ASICCTL_FIFO_RESET|STE_ASICCTL_NETWORK_RESET| 1317 STE_ASICCTL_AUTOINIT_RESET|STE_ASICCTL_HOST_RESET| 1318 STE_ASICCTL_EXTRESET_RESET); 1319 1320 DELAY(100000); 1321 1322 for (i = 0; i < STE_TIMEOUT; i++) { 1323 if (!(CSR_READ_4(sc, STE_ASICCTL) & STE_ASICCTL_RESET_BUSY)) 1324 break; 1325 } 1326 1327 if (i == STE_TIMEOUT) 1328 if_printf(&sc->arpcom.ac_if, "global reset never completed\n"); 1329 1330 return; 1331 } 1332 1333 static int ste_ioctl(ifp, command, data, cr) 1334 struct ifnet *ifp; 1335 u_long command; 1336 caddr_t data; 1337 struct ucred *cr; 1338 { 1339 struct ste_softc *sc; 1340 struct ifreq *ifr; 1341 struct mii_data *mii; 1342 int error = 0; 1343 1344 crit_enter(); 1345 1346 sc = ifp->if_softc; 1347 ifr = (struct ifreq *)data; 1348 1349 switch(command) { 1350 case SIOCSIFFLAGS: 1351 if (ifp->if_flags & IFF_UP) { 1352 if (ifp->if_flags & IFF_RUNNING && 1353 ifp->if_flags & IFF_PROMISC && 1354 !(sc->ste_if_flags & IFF_PROMISC)) { 1355 STE_SETBIT1(sc, STE_RX_MODE, 1356 STE_RXMODE_PROMISC); 1357 } else if (ifp->if_flags & IFF_RUNNING && 1358 !(ifp->if_flags & IFF_PROMISC) && 1359 sc->ste_if_flags & IFF_PROMISC) { 1360 STE_CLRBIT1(sc, STE_RX_MODE, 1361 STE_RXMODE_PROMISC); 1362 } 1363 if (!(ifp->if_flags & IFF_RUNNING)) { 1364 sc->ste_tx_thresh = STE_TXSTART_THRESH; 1365 ste_init(sc); 1366 } 1367 } else { 1368 if (ifp->if_flags & IFF_RUNNING) 1369 ste_stop(sc); 1370 } 1371 sc->ste_if_flags = ifp->if_flags; 1372 error = 0; 1373 break; 1374 case SIOCADDMULTI: 1375 case SIOCDELMULTI: 1376 ste_setmulti(sc); 1377 error = 0; 1378 break; 1379 case SIOCGIFMEDIA: 1380 case SIOCSIFMEDIA: 1381 mii = device_get_softc(sc->ste_miibus); 1382 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1383 break; 1384 default: 1385 error = ether_ioctl(ifp, command, data); 1386 break; 1387 } 1388 1389 crit_exit(); 1390 1391 return(error); 1392 } 1393 1394 static int ste_encap(sc, c, m_head) 1395 struct ste_softc *sc; 1396 struct ste_chain *c; 1397 struct mbuf *m_head; 1398 { 1399 int frag = 0; 1400 struct ste_frag *f = NULL; 1401 struct mbuf *m; 1402 struct ste_desc *d; 1403 int total_len = 0; 1404 1405 d = c->ste_ptr; 1406 d->ste_ctl = 0; 1407 1408 encap_retry: 1409 for (m = m_head, frag = 0; m != NULL; m = m->m_next) { 1410 if (m->m_len != 0) { 1411 if (frag == STE_MAXFRAGS) 1412 break; 1413 total_len += m->m_len; 1414 f = &d->ste_frags[frag]; 1415 f->ste_addr = vtophys(mtod(m, vm_offset_t)); 1416 f->ste_len = m->m_len; 1417 frag++; 1418 } 1419 } 1420 1421 if (m != NULL) { 1422 struct mbuf *mn; 1423 1424 /* 1425 * We ran out of segments. We have to recopy this 1426 * mbuf chain first. Bail out if we can't get the 1427 * new buffers. Code borrowed from if_fxp.c. 1428 */ 1429 MGETHDR(mn, MB_DONTWAIT, MT_DATA); 1430 if (mn == NULL) { 1431 m_freem(m_head); 1432 return ENOMEM; 1433 } 1434 if (m_head->m_pkthdr.len > MHLEN) { 1435 MCLGET(mn, MB_DONTWAIT); 1436 if ((mn->m_flags & M_EXT) == 0) { 1437 m_freem(mn); 1438 m_freem(m_head); 1439 return ENOMEM; 1440 } 1441 } 1442 m_copydata(m_head, 0, m_head->m_pkthdr.len, 1443 mtod(mn, caddr_t)); 1444 mn->m_pkthdr.len = mn->m_len = m_head->m_pkthdr.len; 1445 m_freem(m_head); 1446 m_head = mn; 1447 goto encap_retry; 1448 } 1449 1450 c->ste_mbuf = m_head; 1451 d->ste_frags[frag - 1].ste_len |= STE_FRAG_LAST; 1452 d->ste_ctl = 1; 1453 1454 return(0); 1455 } 1456 1457 static void ste_start(ifp) 1458 struct ifnet *ifp; 1459 { 1460 struct ste_softc *sc; 1461 struct mbuf *m_head = NULL; 1462 struct ste_chain *cur_tx = NULL; 1463 int idx; 1464 1465 sc = ifp->if_softc; 1466 1467 if (!sc->ste_link) 1468 return; 1469 1470 if (ifp->if_flags & IFF_OACTIVE) 1471 return; 1472 1473 idx = sc->ste_cdata.ste_tx_prod; 1474 1475 while(sc->ste_cdata.ste_tx_chain[idx].ste_mbuf == NULL) { 1476 1477 if ((STE_TX_LIST_CNT - sc->ste_cdata.ste_tx_cnt) < 3) { 1478 ifp->if_flags |= IFF_OACTIVE; 1479 break; 1480 } 1481 1482 m_head = ifq_dequeue(&ifp->if_snd); 1483 if (m_head == NULL) 1484 break; 1485 1486 cur_tx = &sc->ste_cdata.ste_tx_chain[idx]; 1487 1488 if (ste_encap(sc, cur_tx, m_head) != 0) 1489 break; 1490 1491 cur_tx->ste_ptr->ste_next = 0; 1492 1493 if(sc->ste_tx_prev_idx < 0){ 1494 cur_tx->ste_ptr->ste_ctl = STE_TXCTL_DMAINTR | 1; 1495 /* Load address of the TX list */ 1496 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL); 1497 ste_wait(sc); 1498 1499 CSR_WRITE_4(sc, STE_TX_DMALIST_PTR, 1500 vtophys(&sc->ste_ldata->ste_tx_list[0])); 1501 1502 /* Set TX polling interval to start TX engine */ 1503 CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 64); 1504 1505 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 1506 ste_wait(sc); 1507 }else{ 1508 cur_tx->ste_ptr->ste_ctl = STE_TXCTL_DMAINTR | 1; 1509 sc->ste_cdata.ste_tx_chain[ 1510 sc->ste_tx_prev_idx].ste_ptr->ste_next 1511 = cur_tx->ste_phys; 1512 } 1513 1514 sc->ste_tx_prev_idx=idx; 1515 1516 BPF_MTAP(ifp, cur_tx->ste_mbuf); 1517 1518 STE_INC(idx, STE_TX_LIST_CNT); 1519 sc->ste_cdata.ste_tx_cnt++; 1520 ifp->if_timer = 5; 1521 sc->ste_cdata.ste_tx_prod = idx; 1522 } 1523 1524 return; 1525 } 1526 1527 static void ste_watchdog(ifp) 1528 struct ifnet *ifp; 1529 { 1530 struct ste_softc *sc; 1531 1532 sc = ifp->if_softc; 1533 1534 ifp->if_oerrors++; 1535 if_printf(ifp, "watchdog timeout\n"); 1536 1537 ste_txeoc(sc); 1538 ste_txeof(sc); 1539 ste_rxeof(sc); 1540 ste_reset(sc); 1541 ste_init(sc); 1542 1543 if (!ifq_is_empty(&ifp->if_snd)) 1544 ste_start(ifp); 1545 1546 return; 1547 } 1548 1549 static void ste_shutdown(dev) 1550 device_t dev; 1551 { 1552 struct ste_softc *sc; 1553 1554 sc = device_get_softc(dev); 1555 1556 ste_stop(sc); 1557 1558 return; 1559 } 1560