1 /* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: src/sys/pci/if_ste.c,v 1.14.2.9 2003/02/05 22:03:57 mbr Exp $ 33 * $DragonFly: src/sys/dev/netif/ste/if_ste.c,v 1.34 2006/08/01 18:10:05 swildner Exp $ 34 */ 35 36 #include <sys/param.h> 37 #include <sys/systm.h> 38 #include <sys/sockio.h> 39 #include <sys/mbuf.h> 40 #include <sys/malloc.h> 41 #include <sys/kernel.h> 42 #include <sys/socket.h> 43 #include <sys/serialize.h> 44 #include <sys/thread2.h> 45 46 #include <net/if.h> 47 #include <net/ifq_var.h> 48 #include <net/if_arp.h> 49 #include <net/ethernet.h> 50 #include <net/if_dl.h> 51 #include <net/if_media.h> 52 #include <net/vlan/if_vlan_var.h> 53 54 #include <net/bpf.h> 55 56 #include <vm/vm.h> /* for vtophys */ 57 #include <vm/pmap.h> /* for vtophys */ 58 #include <machine/bus_memio.h> 59 #include <machine/bus_pio.h> 60 #include <machine/bus.h> 61 #include <machine/resource.h> 62 #include <sys/bus.h> 63 #include <sys/rman.h> 64 65 #include "../mii_layer/mii.h" 66 #include "../mii_layer/miivar.h" 67 68 #include <bus/pci/pcidevs.h> 69 #include <bus/pci/pcireg.h> 70 #include <bus/pci/pcivar.h> 71 72 /* "controller miibus0" required. See GENERIC if you get errors here. */ 73 #include "miibus_if.h" 74 75 #define STE_USEIOSPACE 76 77 #include "if_stereg.h" 78 79 /* 80 * Various supported device vendors/types and their names. 81 */ 82 static struct ste_type ste_devs[] = { 83 { PCI_VENDOR_SUNDANCETI, PCI_PRODUCT_SUNDANCETI_ST201, 84 "Sundance ST201 10/100BaseTX" }, 85 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DL1002, 86 "D-Link DFE-550TX 10/100BaseTX" }, 87 { 0, 0, NULL } 88 }; 89 90 static int ste_probe (device_t); 91 static int ste_attach (device_t); 92 static int ste_detach (device_t); 93 static void ste_init (void *); 94 static void ste_intr (void *); 95 static void ste_rxeof (struct ste_softc *); 96 static void ste_txeoc (struct ste_softc *); 97 static void ste_txeof (struct ste_softc *); 98 static void ste_stats_update (void *); 99 static void ste_stop (struct ste_softc *); 100 static void ste_reset (struct ste_softc *); 101 static int ste_ioctl (struct ifnet *, u_long, caddr_t, 102 struct ucred *); 103 static int ste_encap (struct ste_softc *, struct ste_chain *, 104 struct mbuf *); 105 static void ste_start (struct ifnet *); 106 static void ste_watchdog (struct ifnet *); 107 static void ste_shutdown (device_t); 108 static int ste_newbuf (struct ste_softc *, 109 struct ste_chain_onefrag *, 110 struct mbuf *); 111 static int ste_ifmedia_upd (struct ifnet *); 112 static void ste_ifmedia_sts (struct ifnet *, struct ifmediareq *); 113 114 static void ste_mii_sync (struct ste_softc *); 115 static void ste_mii_send (struct ste_softc *, u_int32_t, int); 116 static int ste_mii_readreg (struct ste_softc *, 117 struct ste_mii_frame *); 118 static int ste_mii_writereg (struct ste_softc *, 119 struct ste_mii_frame *); 120 static int ste_miibus_readreg (device_t, int, int); 121 static int ste_miibus_writereg (device_t, int, int, int); 122 static void ste_miibus_statchg (device_t); 123 124 static int ste_eeprom_wait (struct ste_softc *); 125 static int ste_read_eeprom (struct ste_softc *, caddr_t, int, 126 int, int); 127 static void ste_wait (struct ste_softc *); 128 static void ste_setmulti (struct ste_softc *); 129 static int ste_init_rx_list (struct ste_softc *); 130 static void ste_init_tx_list (struct ste_softc *); 131 132 #ifdef STE_USEIOSPACE 133 #define STE_RES SYS_RES_IOPORT 134 #define STE_RID STE_PCI_LOIO 135 #else 136 #define STE_RES SYS_RES_MEMORY 137 #define STE_RID STE_PCI_LOMEM 138 #endif 139 140 static device_method_t ste_methods[] = { 141 /* Device interface */ 142 DEVMETHOD(device_probe, ste_probe), 143 DEVMETHOD(device_attach, ste_attach), 144 DEVMETHOD(device_detach, ste_detach), 145 DEVMETHOD(device_shutdown, ste_shutdown), 146 147 /* bus interface */ 148 DEVMETHOD(bus_print_child, bus_generic_print_child), 149 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 150 151 /* MII interface */ 152 DEVMETHOD(miibus_readreg, ste_miibus_readreg), 153 DEVMETHOD(miibus_writereg, ste_miibus_writereg), 154 DEVMETHOD(miibus_statchg, ste_miibus_statchg), 155 156 { 0, 0 } 157 }; 158 159 static driver_t ste_driver = { 160 "ste", 161 ste_methods, 162 sizeof(struct ste_softc) 163 }; 164 165 static devclass_t ste_devclass; 166 167 DECLARE_DUMMY_MODULE(if_ste); 168 DRIVER_MODULE(if_ste, pci, ste_driver, ste_devclass, 0, 0); 169 DRIVER_MODULE(miibus, ste, miibus_driver, miibus_devclass, 0, 0); 170 171 #define STE_SETBIT4(sc, reg, x) \ 172 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | x) 173 174 #define STE_CLRBIT4(sc, reg, x) \ 175 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~x) 176 177 #define STE_SETBIT2(sc, reg, x) \ 178 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) | x) 179 180 #define STE_CLRBIT2(sc, reg, x) \ 181 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) & ~x) 182 183 #define STE_SETBIT1(sc, reg, x) \ 184 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | x) 185 186 #define STE_CLRBIT1(sc, reg, x) \ 187 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~x) 188 189 190 #define MII_SET(x) STE_SETBIT1(sc, STE_PHYCTL, x) 191 #define MII_CLR(x) STE_CLRBIT1(sc, STE_PHYCTL, x) 192 193 /* 194 * Sync the PHYs by setting data bit and strobing the clock 32 times. 195 */ 196 static void 197 ste_mii_sync(struct ste_softc *sc) 198 { 199 int i; 200 201 MII_SET(STE_PHYCTL_MDIR|STE_PHYCTL_MDATA); 202 203 for (i = 0; i < 32; i++) { 204 MII_SET(STE_PHYCTL_MCLK); 205 DELAY(1); 206 MII_CLR(STE_PHYCTL_MCLK); 207 DELAY(1); 208 } 209 210 return; 211 } 212 213 /* 214 * Clock a series of bits through the MII. 215 */ 216 static void 217 ste_mii_send(struct ste_softc *sc, u_int32_t bits, int cnt) 218 { 219 int i; 220 221 MII_CLR(STE_PHYCTL_MCLK); 222 223 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 224 if (bits & i) { 225 MII_SET(STE_PHYCTL_MDATA); 226 } else { 227 MII_CLR(STE_PHYCTL_MDATA); 228 } 229 DELAY(1); 230 MII_CLR(STE_PHYCTL_MCLK); 231 DELAY(1); 232 MII_SET(STE_PHYCTL_MCLK); 233 } 234 } 235 236 /* 237 * Read an PHY register through the MII. 238 */ 239 static int 240 ste_mii_readreg(struct ste_softc *sc, struct ste_mii_frame *frame) 241 { 242 int i, ack; 243 244 /* 245 * Set up frame for RX. 246 */ 247 frame->mii_stdelim = STE_MII_STARTDELIM; 248 frame->mii_opcode = STE_MII_READOP; 249 frame->mii_turnaround = 0; 250 frame->mii_data = 0; 251 252 CSR_WRITE_2(sc, STE_PHYCTL, 0); 253 /* 254 * Turn on data xmit. 255 */ 256 MII_SET(STE_PHYCTL_MDIR); 257 258 ste_mii_sync(sc); 259 260 /* 261 * Send command/address info. 262 */ 263 ste_mii_send(sc, frame->mii_stdelim, 2); 264 ste_mii_send(sc, frame->mii_opcode, 2); 265 ste_mii_send(sc, frame->mii_phyaddr, 5); 266 ste_mii_send(sc, frame->mii_regaddr, 5); 267 268 /* Turn off xmit. */ 269 MII_CLR(STE_PHYCTL_MDIR); 270 271 /* Idle bit */ 272 MII_CLR((STE_PHYCTL_MCLK|STE_PHYCTL_MDATA)); 273 DELAY(1); 274 MII_SET(STE_PHYCTL_MCLK); 275 DELAY(1); 276 277 /* Check for ack */ 278 MII_CLR(STE_PHYCTL_MCLK); 279 DELAY(1); 280 ack = CSR_READ_2(sc, STE_PHYCTL) & STE_PHYCTL_MDATA; 281 MII_SET(STE_PHYCTL_MCLK); 282 DELAY(1); 283 284 /* 285 * Now try reading data bits. If the ack failed, we still 286 * need to clock through 16 cycles to keep the PHY(s) in sync. 287 */ 288 if (ack) { 289 for(i = 0; i < 16; i++) { 290 MII_CLR(STE_PHYCTL_MCLK); 291 DELAY(1); 292 MII_SET(STE_PHYCTL_MCLK); 293 DELAY(1); 294 } 295 goto fail; 296 } 297 298 for (i = 0x8000; i; i >>= 1) { 299 MII_CLR(STE_PHYCTL_MCLK); 300 DELAY(1); 301 if (!ack) { 302 if (CSR_READ_2(sc, STE_PHYCTL) & STE_PHYCTL_MDATA) 303 frame->mii_data |= i; 304 DELAY(1); 305 } 306 MII_SET(STE_PHYCTL_MCLK); 307 DELAY(1); 308 } 309 310 fail: 311 312 MII_CLR(STE_PHYCTL_MCLK); 313 DELAY(1); 314 MII_SET(STE_PHYCTL_MCLK); 315 DELAY(1); 316 317 if (ack) 318 return(1); 319 return(0); 320 } 321 322 /* 323 * Write to a PHY register through the MII. 324 */ 325 static int 326 ste_mii_writereg(struct ste_softc *sc, struct ste_mii_frame *frame) 327 { 328 /* 329 * Set up frame for TX. 330 */ 331 332 frame->mii_stdelim = STE_MII_STARTDELIM; 333 frame->mii_opcode = STE_MII_WRITEOP; 334 frame->mii_turnaround = STE_MII_TURNAROUND; 335 336 /* 337 * Turn on data output. 338 */ 339 MII_SET(STE_PHYCTL_MDIR); 340 341 ste_mii_sync(sc); 342 343 ste_mii_send(sc, frame->mii_stdelim, 2); 344 ste_mii_send(sc, frame->mii_opcode, 2); 345 ste_mii_send(sc, frame->mii_phyaddr, 5); 346 ste_mii_send(sc, frame->mii_regaddr, 5); 347 ste_mii_send(sc, frame->mii_turnaround, 2); 348 ste_mii_send(sc, frame->mii_data, 16); 349 350 /* Idle bit. */ 351 MII_SET(STE_PHYCTL_MCLK); 352 DELAY(1); 353 MII_CLR(STE_PHYCTL_MCLK); 354 DELAY(1); 355 356 /* 357 * Turn off xmit. 358 */ 359 MII_CLR(STE_PHYCTL_MDIR); 360 361 return(0); 362 } 363 364 static int 365 ste_miibus_readreg(device_t dev, int phy, int reg) 366 { 367 struct ste_softc *sc; 368 struct ste_mii_frame frame; 369 370 sc = device_get_softc(dev); 371 372 if ( sc->ste_one_phy && phy != 0 ) 373 return (0); 374 375 bzero((char *)&frame, sizeof(frame)); 376 377 frame.mii_phyaddr = phy; 378 frame.mii_regaddr = reg; 379 ste_mii_readreg(sc, &frame); 380 381 return(frame.mii_data); 382 } 383 384 static int 385 ste_miibus_writereg(device_t dev, int phy, int reg, int data) 386 { 387 struct ste_softc *sc; 388 struct ste_mii_frame frame; 389 390 sc = device_get_softc(dev); 391 bzero((char *)&frame, sizeof(frame)); 392 393 frame.mii_phyaddr = phy; 394 frame.mii_regaddr = reg; 395 frame.mii_data = data; 396 397 ste_mii_writereg(sc, &frame); 398 399 return(0); 400 } 401 402 static void 403 ste_miibus_statchg(device_t dev) 404 { 405 struct ste_softc *sc; 406 struct mii_data *mii; 407 int i; 408 409 sc = device_get_softc(dev); 410 mii = device_get_softc(sc->ste_miibus); 411 412 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 413 STE_SETBIT2(sc, STE_MACCTL0, STE_MACCTL0_FULLDUPLEX); 414 } else { 415 STE_CLRBIT2(sc, STE_MACCTL0, STE_MACCTL0_FULLDUPLEX); 416 } 417 418 STE_SETBIT4(sc, STE_ASICCTL,STE_ASICCTL_RX_RESET | 419 STE_ASICCTL_TX_RESET); 420 for (i = 0; i < STE_TIMEOUT; i++) { 421 if (!(CSR_READ_4(sc, STE_ASICCTL) & STE_ASICCTL_RESET_BUSY)) 422 break; 423 } 424 if (i == STE_TIMEOUT) 425 if_printf(&sc->arpcom.ac_if, "rx reset never completed\n"); 426 427 return; 428 } 429 430 static int 431 ste_ifmedia_upd(struct ifnet *ifp) 432 { 433 struct ste_softc *sc; 434 struct mii_data *mii; 435 436 sc = ifp->if_softc; 437 mii = device_get_softc(sc->ste_miibus); 438 sc->ste_link = 0; 439 if (mii->mii_instance) { 440 struct mii_softc *miisc; 441 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 442 miisc = LIST_NEXT(miisc, mii_list)) 443 mii_phy_reset(miisc); 444 } 445 mii_mediachg(mii); 446 447 return(0); 448 } 449 450 static void 451 ste_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 452 { 453 struct ste_softc *sc; 454 struct mii_data *mii; 455 456 sc = ifp->if_softc; 457 mii = device_get_softc(sc->ste_miibus); 458 459 mii_pollstat(mii); 460 ifmr->ifm_active = mii->mii_media_active; 461 ifmr->ifm_status = mii->mii_media_status; 462 463 return; 464 } 465 466 static void 467 ste_wait(struct ste_softc *sc) 468 { 469 int i; 470 471 for (i = 0; i < STE_TIMEOUT; i++) { 472 if (!(CSR_READ_4(sc, STE_DMACTL) & STE_DMACTL_DMA_HALTINPROG)) 473 break; 474 } 475 476 if (i == STE_TIMEOUT) 477 if_printf(&sc->arpcom.ac_if, "command never completed!\n"); 478 479 return; 480 } 481 482 /* 483 * The EEPROM is slow: give it time to come ready after issuing 484 * it a command. 485 */ 486 static int 487 ste_eeprom_wait(struct ste_softc *sc) 488 { 489 int i; 490 491 DELAY(1000); 492 493 for (i = 0; i < 100; i++) { 494 if (CSR_READ_2(sc, STE_EEPROM_CTL) & STE_EECTL_BUSY) 495 DELAY(1000); 496 else 497 break; 498 } 499 500 if (i == 100) { 501 if_printf(&sc->arpcom.ac_if, "eeprom failed to come ready\n"); 502 return(1); 503 } 504 505 return(0); 506 } 507 508 /* 509 * Read a sequence of words from the EEPROM. Note that ethernet address 510 * data is stored in the EEPROM in network byte order. 511 */ 512 static int 513 ste_read_eeprom(struct ste_softc *sc, caddr_t dest, int off, int cnt, int swap) 514 { 515 int err = 0, i; 516 u_int16_t word = 0, *ptr; 517 518 if (ste_eeprom_wait(sc)) 519 return(1); 520 521 for (i = 0; i < cnt; i++) { 522 CSR_WRITE_2(sc, STE_EEPROM_CTL, STE_EEOPCODE_READ | (off + i)); 523 err = ste_eeprom_wait(sc); 524 if (err) 525 break; 526 word = CSR_READ_2(sc, STE_EEPROM_DATA); 527 ptr = (u_int16_t *)(dest + (i * 2)); 528 if (swap) 529 *ptr = ntohs(word); 530 else 531 *ptr = word; 532 } 533 534 return(err ? 1 : 0); 535 } 536 537 static void 538 ste_setmulti(struct ste_softc *sc) 539 { 540 struct ifnet *ifp; 541 int h = 0; 542 u_int32_t hashes[2] = { 0, 0 }; 543 struct ifmultiaddr *ifma; 544 545 ifp = &sc->arpcom.ac_if; 546 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 547 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_ALLMULTI); 548 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_MULTIHASH); 549 return; 550 } 551 552 /* first, zot all the existing hash bits */ 553 CSR_WRITE_2(sc, STE_MAR0, 0); 554 CSR_WRITE_2(sc, STE_MAR1, 0); 555 CSR_WRITE_2(sc, STE_MAR2, 0); 556 CSR_WRITE_2(sc, STE_MAR3, 0); 557 558 /* now program new ones */ 559 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 560 if (ifma->ifma_addr->sa_family != AF_LINK) 561 continue; 562 h = ether_crc32_be( 563 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 564 ETHER_ADDR_LEN) & 0x3f; 565 if (h < 32) 566 hashes[0] |= (1 << h); 567 else 568 hashes[1] |= (1 << (h - 32)); 569 } 570 571 CSR_WRITE_2(sc, STE_MAR0, hashes[0] & 0xFFFF); 572 CSR_WRITE_2(sc, STE_MAR1, (hashes[0] >> 16) & 0xFFFF); 573 CSR_WRITE_2(sc, STE_MAR2, hashes[1] & 0xFFFF); 574 CSR_WRITE_2(sc, STE_MAR3, (hashes[1] >> 16) & 0xFFFF); 575 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_ALLMULTI); 576 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_MULTIHASH); 577 578 return; 579 } 580 581 static void 582 ste_intr(void *xsc) 583 { 584 struct ste_softc *sc; 585 struct ifnet *ifp; 586 u_int16_t status; 587 588 sc = xsc; 589 ifp = &sc->arpcom.ac_if; 590 591 /* See if this is really our interrupt. */ 592 if (!(CSR_READ_2(sc, STE_ISR) & STE_ISR_INTLATCH)) 593 return; 594 595 for (;;) { 596 status = CSR_READ_2(sc, STE_ISR_ACK); 597 598 if (!(status & STE_INTRS)) 599 break; 600 601 if (status & STE_ISR_RX_DMADONE) 602 ste_rxeof(sc); 603 604 if (status & STE_ISR_TX_DMADONE) 605 ste_txeof(sc); 606 607 if (status & STE_ISR_TX_DONE) 608 ste_txeoc(sc); 609 610 if (status & STE_ISR_STATS_OFLOW) { 611 callout_stop(&sc->ste_stat_timer); 612 ste_stats_update(sc); 613 } 614 615 if (status & STE_ISR_LINKEVENT) 616 mii_pollstat(device_get_softc(sc->ste_miibus)); 617 618 if (status & STE_ISR_HOSTERR) { 619 ste_reset(sc); 620 ste_init(sc); 621 } 622 } 623 624 /* Re-enable interrupts */ 625 CSR_WRITE_2(sc, STE_IMR, STE_INTRS); 626 627 if (!ifq_is_empty(&ifp->if_snd)) 628 ste_start(ifp); 629 630 return; 631 } 632 633 /* 634 * A frame has been uploaded: pass the resulting mbuf chain up to 635 * the higher level protocols. 636 */ 637 static void 638 ste_rxeof(struct ste_softc *sc) 639 { 640 struct mbuf *m; 641 struct ifnet *ifp; 642 struct ste_chain_onefrag *cur_rx; 643 int total_len = 0, count=0; 644 u_int32_t rxstat; 645 646 ifp = &sc->arpcom.ac_if; 647 648 while((rxstat = sc->ste_cdata.ste_rx_head->ste_ptr->ste_status) 649 & STE_RXSTAT_DMADONE) { 650 if ((STE_RX_LIST_CNT - count) < 3) { 651 break; 652 } 653 654 cur_rx = sc->ste_cdata.ste_rx_head; 655 sc->ste_cdata.ste_rx_head = cur_rx->ste_next; 656 657 /* 658 * If an error occurs, update stats, clear the 659 * status word and leave the mbuf cluster in place: 660 * it should simply get re-used next time this descriptor 661 * comes up in the ring. 662 */ 663 if (rxstat & STE_RXSTAT_FRAME_ERR) { 664 ifp->if_ierrors++; 665 cur_rx->ste_ptr->ste_status = 0; 666 continue; 667 } 668 669 /* 670 * If there error bit was not set, the upload complete 671 * bit should be set which means we have a valid packet. 672 * If not, something truly strange has happened. 673 */ 674 if (!(rxstat & STE_RXSTAT_DMADONE)) { 675 if_printf(ifp, "bad receive status -- packet dropped"); 676 ifp->if_ierrors++; 677 cur_rx->ste_ptr->ste_status = 0; 678 continue; 679 } 680 681 /* No errors; receive the packet. */ 682 m = cur_rx->ste_mbuf; 683 total_len = cur_rx->ste_ptr->ste_status & STE_RXSTAT_FRAMELEN; 684 685 /* 686 * Try to conjure up a new mbuf cluster. If that 687 * fails, it means we have an out of memory condition and 688 * should leave the buffer in place and continue. This will 689 * result in a lost packet, but there's little else we 690 * can do in this situation. 691 */ 692 if (ste_newbuf(sc, cur_rx, NULL) == ENOBUFS) { 693 ifp->if_ierrors++; 694 cur_rx->ste_ptr->ste_status = 0; 695 continue; 696 } 697 698 ifp->if_ipackets++; 699 m->m_pkthdr.rcvif = ifp; 700 m->m_pkthdr.len = m->m_len = total_len; 701 702 ifp->if_input(ifp, m); 703 704 cur_rx->ste_ptr->ste_status = 0; 705 count++; 706 } 707 708 return; 709 } 710 711 static void 712 ste_txeoc(struct ste_softc *sc) 713 { 714 u_int8_t txstat; 715 struct ifnet *ifp; 716 717 ifp = &sc->arpcom.ac_if; 718 719 while ((txstat = CSR_READ_1(sc, STE_TX_STATUS)) & 720 STE_TXSTATUS_TXDONE) { 721 if (txstat & STE_TXSTATUS_UNDERRUN || 722 txstat & STE_TXSTATUS_EXCESSCOLLS || 723 txstat & STE_TXSTATUS_RECLAIMERR) { 724 ifp->if_oerrors++; 725 if_printf(ifp, "transmission error: %x\n", txstat); 726 727 ste_reset(sc); 728 ste_init(sc); 729 730 if (txstat & STE_TXSTATUS_UNDERRUN && 731 sc->ste_tx_thresh < STE_PACKET_SIZE) { 732 sc->ste_tx_thresh += STE_MIN_FRAMELEN; 733 if_printf(ifp, "tx underrun, increasing tx" 734 " start threshold to %d bytes\n", 735 sc->ste_tx_thresh); 736 } 737 CSR_WRITE_2(sc, STE_TX_STARTTHRESH, sc->ste_tx_thresh); 738 CSR_WRITE_2(sc, STE_TX_RECLAIM_THRESH, 739 (STE_PACKET_SIZE >> 4)); 740 } 741 ste_init(sc); 742 CSR_WRITE_2(sc, STE_TX_STATUS, txstat); 743 } 744 745 return; 746 } 747 748 static void 749 ste_txeof(struct ste_softc *sc) 750 { 751 struct ste_chain *cur_tx = NULL; 752 struct ifnet *ifp; 753 int idx; 754 755 ifp = &sc->arpcom.ac_if; 756 757 idx = sc->ste_cdata.ste_tx_cons; 758 while(idx != sc->ste_cdata.ste_tx_prod) { 759 cur_tx = &sc->ste_cdata.ste_tx_chain[idx]; 760 761 if (!(cur_tx->ste_ptr->ste_ctl & STE_TXCTL_DMADONE)) 762 break; 763 764 if (cur_tx->ste_mbuf != NULL) { 765 m_freem(cur_tx->ste_mbuf); 766 cur_tx->ste_mbuf = NULL; 767 } 768 769 ifp->if_opackets++; 770 771 sc->ste_cdata.ste_tx_cnt--; 772 STE_INC(idx, STE_TX_LIST_CNT); 773 ifp->if_timer = 0; 774 } 775 776 sc->ste_cdata.ste_tx_cons = idx; 777 778 if (cur_tx != NULL) 779 ifp->if_flags &= ~IFF_OACTIVE; 780 781 return; 782 } 783 784 static void 785 ste_stats_update(void *xsc) 786 { 787 struct ste_softc *sc; 788 struct ifnet *ifp; 789 struct mii_data *mii; 790 791 sc = xsc; 792 ifp = &sc->arpcom.ac_if; 793 mii = device_get_softc(sc->ste_miibus); 794 795 lwkt_serialize_enter(ifp->if_serializer); 796 797 ifp->if_collisions += CSR_READ_1(sc, STE_LATE_COLLS) 798 + CSR_READ_1(sc, STE_MULTI_COLLS) 799 + CSR_READ_1(sc, STE_SINGLE_COLLS); 800 801 if (!sc->ste_link) { 802 mii_pollstat(mii); 803 if (mii->mii_media_status & IFM_ACTIVE && 804 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 805 sc->ste_link++; 806 /* 807 * we don't get a call-back on re-init so do it 808 * otherwise we get stuck in the wrong link state 809 */ 810 ste_miibus_statchg(sc->ste_dev); 811 if (!ifq_is_empty(&ifp->if_snd)) 812 ste_start(ifp); 813 } 814 } 815 816 callout_reset(&sc->ste_stat_timer, hz, ste_stats_update, sc); 817 lwkt_serialize_exit(ifp->if_serializer); 818 } 819 820 821 /* 822 * Probe for a Sundance ST201 chip. Check the PCI vendor and device 823 * IDs against our list and return a device name if we find a match. 824 */ 825 static int 826 ste_probe(device_t dev) 827 { 828 struct ste_type *t; 829 830 t = ste_devs; 831 832 while(t->ste_name != NULL) { 833 if ((pci_get_vendor(dev) == t->ste_vid) && 834 (pci_get_device(dev) == t->ste_did)) { 835 device_set_desc(dev, t->ste_name); 836 return(0); 837 } 838 t++; 839 } 840 841 return(ENXIO); 842 } 843 844 /* 845 * Attach the interface. Allocate softc structures, do ifmedia 846 * setup and ethernet/BPF attach. 847 */ 848 static int 849 ste_attach(device_t dev) 850 { 851 struct ste_softc *sc; 852 struct ifnet *ifp; 853 int error = 0, rid; 854 uint8_t eaddr[ETHER_ADDR_LEN]; 855 856 sc = device_get_softc(dev); 857 sc->ste_dev = dev; 858 859 /* 860 * Only use one PHY since this chip reports multiple 861 * Note on the DFE-550 the PHY is at 1 on the DFE-580 862 * it is at 0 & 1. It is rev 0x12. 863 */ 864 if (pci_get_vendor(dev) == PCI_VENDOR_DLINK && 865 pci_get_device(dev) == PCI_PRODUCT_DLINK_DL1002 && 866 pci_get_revid(dev) == 0x12 ) 867 sc->ste_one_phy = 1; 868 869 /* 870 * Handle power management nonsense. 871 */ 872 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 873 u_int32_t iobase, membase, irq; 874 875 /* Save important PCI config data. */ 876 iobase = pci_read_config(dev, STE_PCI_LOIO, 4); 877 membase = pci_read_config(dev, STE_PCI_LOMEM, 4); 878 irq = pci_read_config(dev, STE_PCI_INTLINE, 4); 879 880 /* Reset the power state. */ 881 device_printf(dev, "chip is in D%d power mode " 882 "-- setting to D0\n", pci_get_powerstate(dev)); 883 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 884 885 /* Restore PCI config data. */ 886 pci_write_config(dev, STE_PCI_LOIO, iobase, 4); 887 pci_write_config(dev, STE_PCI_LOMEM, membase, 4); 888 pci_write_config(dev, STE_PCI_INTLINE, irq, 4); 889 } 890 891 /* 892 * Map control/status registers. 893 */ 894 pci_enable_busmaster(dev); 895 896 rid = STE_RID; 897 sc->ste_res = bus_alloc_resource_any(dev, STE_RES, &rid, RF_ACTIVE); 898 899 if (sc->ste_res == NULL) { 900 device_printf(dev, "couldn't map ports/memory\n"); 901 error = ENXIO; 902 goto fail; 903 } 904 905 sc->ste_btag = rman_get_bustag(sc->ste_res); 906 sc->ste_bhandle = rman_get_bushandle(sc->ste_res); 907 908 rid = 0; 909 sc->ste_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 910 RF_SHAREABLE | RF_ACTIVE); 911 912 if (sc->ste_irq == NULL) { 913 device_printf(dev, "couldn't map interrupt\n"); 914 error = ENXIO; 915 goto fail; 916 } 917 918 callout_init(&sc->ste_stat_timer); 919 920 ifp = &sc->arpcom.ac_if; 921 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 922 923 /* Reset the adapter. */ 924 ste_reset(sc); 925 926 /* 927 * Get station address from the EEPROM. 928 */ 929 if (ste_read_eeprom(sc, eaddr, STE_EEADDR_NODE0, 3, 0)) { 930 device_printf(dev, "failed to read station address\n"); 931 error = ENXIO; 932 goto fail; 933 } 934 935 /* Allocate the descriptor queues. */ 936 sc->ste_ldata = contigmalloc(sizeof(struct ste_list_data), M_DEVBUF, 937 M_WAITOK, 0, 0xffffffff, PAGE_SIZE, 0); 938 939 if (sc->ste_ldata == NULL) { 940 device_printf(dev, "no memory for list buffers!\n"); 941 error = ENXIO; 942 goto fail; 943 } 944 945 bzero(sc->ste_ldata, sizeof(struct ste_list_data)); 946 947 /* Do MII setup. */ 948 if (mii_phy_probe(dev, &sc->ste_miibus, 949 ste_ifmedia_upd, ste_ifmedia_sts)) { 950 device_printf(dev, "MII without any phy!\n"); 951 error = ENXIO; 952 goto fail; 953 } 954 955 ifp->if_softc = sc; 956 ifp->if_mtu = ETHERMTU; 957 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 958 ifp->if_ioctl = ste_ioctl; 959 ifp->if_start = ste_start; 960 ifp->if_watchdog = ste_watchdog; 961 ifp->if_init = ste_init; 962 ifp->if_baudrate = 10000000; 963 ifq_set_maxlen(&ifp->if_snd, STE_TX_LIST_CNT - 1); 964 ifq_set_ready(&ifp->if_snd); 965 966 sc->ste_tx_thresh = STE_TXSTART_THRESH; 967 968 /* 969 * Call MI attach routine. 970 */ 971 ether_ifattach(ifp, eaddr, NULL); 972 973 /* 974 * Tell the upper layer(s) we support long frames. 975 */ 976 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 977 978 error = bus_setup_intr(dev, sc->ste_irq, INTR_NETSAFE, 979 ste_intr, sc, &sc->ste_intrhand, 980 ifp->if_serializer); 981 if (error) { 982 device_printf(dev, "couldn't set up irq\n"); 983 ether_ifdetach(ifp); 984 goto fail; 985 } 986 987 return 0; 988 989 fail: 990 ste_detach(dev); 991 return(error); 992 } 993 994 static int 995 ste_detach(device_t dev) 996 { 997 struct ste_softc *sc = device_get_softc(dev); 998 struct ifnet *ifp = &sc->arpcom.ac_if; 999 1000 if (device_is_attached(dev)) { 1001 lwkt_serialize_enter(ifp->if_serializer); 1002 ste_stop(sc); 1003 bus_teardown_intr(dev, sc->ste_irq, sc->ste_intrhand); 1004 lwkt_serialize_exit(ifp->if_serializer); 1005 1006 ether_ifdetach(ifp); 1007 } 1008 if (sc->ste_miibus != NULL) 1009 device_delete_child(dev, sc->ste_miibus); 1010 bus_generic_detach(dev); 1011 1012 if (sc->ste_irq != NULL) 1013 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq); 1014 if (sc->ste_res != NULL) 1015 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res); 1016 if (sc->ste_ldata != NULL) { 1017 contigfree(sc->ste_ldata, sizeof(struct ste_list_data), 1018 M_DEVBUF); 1019 } 1020 1021 return(0); 1022 } 1023 1024 static int 1025 ste_newbuf(struct ste_softc *sc, struct ste_chain_onefrag *c, 1026 struct mbuf *m) 1027 { 1028 struct mbuf *m_new = NULL; 1029 1030 if (m == NULL) { 1031 MGETHDR(m_new, MB_DONTWAIT, MT_DATA); 1032 if (m_new == NULL) 1033 return(ENOBUFS); 1034 MCLGET(m_new, MB_DONTWAIT); 1035 if (!(m_new->m_flags & M_EXT)) { 1036 m_freem(m_new); 1037 return(ENOBUFS); 1038 } 1039 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1040 } else { 1041 m_new = m; 1042 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1043 m_new->m_data = m_new->m_ext.ext_buf; 1044 } 1045 1046 m_adj(m_new, ETHER_ALIGN); 1047 1048 c->ste_mbuf = m_new; 1049 c->ste_ptr->ste_status = 0; 1050 c->ste_ptr->ste_frag.ste_addr = vtophys(mtod(m_new, caddr_t)); 1051 c->ste_ptr->ste_frag.ste_len = (1536 + EVL_ENCAPLEN) | STE_FRAG_LAST; 1052 1053 return(0); 1054 } 1055 1056 static int 1057 ste_init_rx_list(struct ste_softc *sc) 1058 { 1059 struct ste_chain_data *cd; 1060 struct ste_list_data *ld; 1061 int i; 1062 1063 cd = &sc->ste_cdata; 1064 ld = sc->ste_ldata; 1065 1066 for (i = 0; i < STE_RX_LIST_CNT; i++) { 1067 cd->ste_rx_chain[i].ste_ptr = &ld->ste_rx_list[i]; 1068 if (ste_newbuf(sc, &cd->ste_rx_chain[i], NULL) == ENOBUFS) 1069 return(ENOBUFS); 1070 if (i == (STE_RX_LIST_CNT - 1)) { 1071 cd->ste_rx_chain[i].ste_next = 1072 &cd->ste_rx_chain[0]; 1073 ld->ste_rx_list[i].ste_next = 1074 vtophys(&ld->ste_rx_list[0]); 1075 } else { 1076 cd->ste_rx_chain[i].ste_next = 1077 &cd->ste_rx_chain[i + 1]; 1078 ld->ste_rx_list[i].ste_next = 1079 vtophys(&ld->ste_rx_list[i + 1]); 1080 } 1081 ld->ste_rx_list[i].ste_status = 0; 1082 } 1083 1084 cd->ste_rx_head = &cd->ste_rx_chain[0]; 1085 1086 return(0); 1087 } 1088 1089 static void 1090 ste_init_tx_list(struct ste_softc *sc) 1091 { 1092 struct ste_chain_data *cd; 1093 struct ste_list_data *ld; 1094 int i; 1095 1096 cd = &sc->ste_cdata; 1097 ld = sc->ste_ldata; 1098 for (i = 0; i < STE_TX_LIST_CNT; i++) { 1099 cd->ste_tx_chain[i].ste_ptr = &ld->ste_tx_list[i]; 1100 cd->ste_tx_chain[i].ste_ptr->ste_next = 0; 1101 cd->ste_tx_chain[i].ste_ptr->ste_ctl = 0; 1102 cd->ste_tx_chain[i].ste_phys = vtophys(&ld->ste_tx_list[i]); 1103 if (i == (STE_TX_LIST_CNT - 1)) 1104 cd->ste_tx_chain[i].ste_next = 1105 &cd->ste_tx_chain[0]; 1106 else 1107 cd->ste_tx_chain[i].ste_next = 1108 &cd->ste_tx_chain[i + 1]; 1109 if (i == 0) 1110 cd->ste_tx_chain[i].ste_prev = 1111 &cd->ste_tx_chain[STE_TX_LIST_CNT - 1]; 1112 else 1113 cd->ste_tx_chain[i].ste_prev = 1114 &cd->ste_tx_chain[i - 1]; 1115 } 1116 1117 cd->ste_tx_prod = 0; 1118 cd->ste_tx_cons = 0; 1119 cd->ste_tx_cnt = 0; 1120 1121 return; 1122 } 1123 1124 static void 1125 ste_init(void *xsc) 1126 { 1127 struct ste_softc *sc; 1128 int i; 1129 struct ifnet *ifp; 1130 struct mii_data *mii; 1131 1132 sc = xsc; 1133 ifp = &sc->arpcom.ac_if; 1134 mii = device_get_softc(sc->ste_miibus); 1135 1136 ste_stop(sc); 1137 1138 /* Init our MAC address */ 1139 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1140 CSR_WRITE_1(sc, STE_PAR0 + i, sc->arpcom.ac_enaddr[i]); 1141 } 1142 1143 /* Init RX list */ 1144 if (ste_init_rx_list(sc) == ENOBUFS) { 1145 if_printf(ifp, "initialization failed: no " 1146 "memory for RX buffers\n"); 1147 ste_stop(sc); 1148 return; 1149 } 1150 1151 /* Set RX polling interval */ 1152 CSR_WRITE_1(sc, STE_RX_DMAPOLL_PERIOD, 1); 1153 1154 /* Init TX descriptors */ 1155 ste_init_tx_list(sc); 1156 1157 /* Set the TX freethresh value */ 1158 CSR_WRITE_1(sc, STE_TX_DMABURST_THRESH, STE_PACKET_SIZE >> 8); 1159 1160 /* Set the TX start threshold for best performance. */ 1161 CSR_WRITE_2(sc, STE_TX_STARTTHRESH, sc->ste_tx_thresh); 1162 1163 /* Set the TX reclaim threshold. */ 1164 CSR_WRITE_1(sc, STE_TX_RECLAIM_THRESH, (STE_PACKET_SIZE >> 4)); 1165 1166 /* Set up the RX filter. */ 1167 CSR_WRITE_1(sc, STE_RX_MODE, STE_RXMODE_UNICAST); 1168 1169 /* If we want promiscuous mode, set the allframes bit. */ 1170 if (ifp->if_flags & IFF_PROMISC) { 1171 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_PROMISC); 1172 } else { 1173 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_PROMISC); 1174 } 1175 1176 /* Set capture broadcast bit to accept broadcast frames. */ 1177 if (ifp->if_flags & IFF_BROADCAST) { 1178 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_BROADCAST); 1179 } else { 1180 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_BROADCAST); 1181 } 1182 1183 ste_setmulti(sc); 1184 1185 /* Load the address of the RX list. */ 1186 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_STALL); 1187 ste_wait(sc); 1188 CSR_WRITE_4(sc, STE_RX_DMALIST_PTR, 1189 vtophys(&sc->ste_ldata->ste_rx_list[0])); 1190 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL); 1191 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL); 1192 1193 /* Set TX polling interval (defer until we TX first packet */ 1194 CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 0); 1195 1196 /* Load address of the TX list */ 1197 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL); 1198 ste_wait(sc); 1199 CSR_WRITE_4(sc, STE_TX_DMALIST_PTR, 0); 1200 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 1201 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 1202 ste_wait(sc); 1203 sc->ste_tx_prev_idx=-1; 1204 1205 /* Enable receiver and transmitter */ 1206 CSR_WRITE_2(sc, STE_MACCTL0, 0); 1207 CSR_WRITE_2(sc, STE_MACCTL1, 0); 1208 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_TX_ENABLE); 1209 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_RX_ENABLE); 1210 1211 /* Enable stats counters. */ 1212 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_STATS_ENABLE); 1213 1214 /* Enable interrupts. */ 1215 CSR_WRITE_2(sc, STE_ISR, 0xFFFF); 1216 CSR_WRITE_2(sc, STE_IMR, STE_INTRS); 1217 1218 /* Accept VLAN length packets */ 1219 CSR_WRITE_2(sc, STE_MAX_FRAMELEN, ETHER_MAX_LEN + EVL_ENCAPLEN); 1220 1221 ste_ifmedia_upd(ifp); 1222 1223 ifp->if_flags |= IFF_RUNNING; 1224 ifp->if_flags &= ~IFF_OACTIVE; 1225 1226 callout_reset(&sc->ste_stat_timer, hz, ste_stats_update, sc); 1227 } 1228 1229 static void 1230 ste_stop(struct ste_softc *sc) 1231 { 1232 int i; 1233 struct ifnet *ifp; 1234 1235 ifp = &sc->arpcom.ac_if; 1236 1237 callout_stop(&sc->ste_stat_timer); 1238 1239 CSR_WRITE_2(sc, STE_IMR, 0); 1240 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_TX_DISABLE); 1241 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_RX_DISABLE); 1242 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_STATS_DISABLE); 1243 STE_SETBIT2(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL); 1244 STE_SETBIT2(sc, STE_DMACTL, STE_DMACTL_RXDMA_STALL); 1245 ste_wait(sc); 1246 /* 1247 * Try really hard to stop the RX engine or under heavy RX 1248 * data chip will write into de-allocated memory. 1249 */ 1250 ste_reset(sc); 1251 1252 sc->ste_link = 0; 1253 1254 for (i = 0; i < STE_RX_LIST_CNT; i++) { 1255 if (sc->ste_cdata.ste_rx_chain[i].ste_mbuf != NULL) { 1256 m_freem(sc->ste_cdata.ste_rx_chain[i].ste_mbuf); 1257 sc->ste_cdata.ste_rx_chain[i].ste_mbuf = NULL; 1258 } 1259 } 1260 1261 for (i = 0; i < STE_TX_LIST_CNT; i++) { 1262 if (sc->ste_cdata.ste_tx_chain[i].ste_mbuf != NULL) { 1263 m_freem(sc->ste_cdata.ste_tx_chain[i].ste_mbuf); 1264 sc->ste_cdata.ste_tx_chain[i].ste_mbuf = NULL; 1265 } 1266 } 1267 1268 bzero(sc->ste_ldata, sizeof(struct ste_list_data)); 1269 1270 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 1271 1272 return; 1273 } 1274 1275 static void 1276 ste_reset(struct ste_softc *sc) 1277 { 1278 int i; 1279 1280 STE_SETBIT4(sc, STE_ASICCTL, 1281 STE_ASICCTL_GLOBAL_RESET|STE_ASICCTL_RX_RESET| 1282 STE_ASICCTL_TX_RESET|STE_ASICCTL_DMA_RESET| 1283 STE_ASICCTL_FIFO_RESET|STE_ASICCTL_NETWORK_RESET| 1284 STE_ASICCTL_AUTOINIT_RESET|STE_ASICCTL_HOST_RESET| 1285 STE_ASICCTL_EXTRESET_RESET); 1286 1287 DELAY(100000); 1288 1289 for (i = 0; i < STE_TIMEOUT; i++) { 1290 if (!(CSR_READ_4(sc, STE_ASICCTL) & STE_ASICCTL_RESET_BUSY)) 1291 break; 1292 } 1293 1294 if (i == STE_TIMEOUT) 1295 if_printf(&sc->arpcom.ac_if, "global reset never completed\n"); 1296 1297 return; 1298 } 1299 1300 static int 1301 ste_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr) 1302 { 1303 struct ste_softc *sc; 1304 struct ifreq *ifr; 1305 struct mii_data *mii; 1306 int error = 0; 1307 1308 sc = ifp->if_softc; 1309 ifr = (struct ifreq *)data; 1310 1311 switch(command) { 1312 case SIOCSIFFLAGS: 1313 if (ifp->if_flags & IFF_UP) { 1314 if (ifp->if_flags & IFF_RUNNING && 1315 ifp->if_flags & IFF_PROMISC && 1316 !(sc->ste_if_flags & IFF_PROMISC)) { 1317 STE_SETBIT1(sc, STE_RX_MODE, 1318 STE_RXMODE_PROMISC); 1319 } else if (ifp->if_flags & IFF_RUNNING && 1320 !(ifp->if_flags & IFF_PROMISC) && 1321 sc->ste_if_flags & IFF_PROMISC) { 1322 STE_CLRBIT1(sc, STE_RX_MODE, 1323 STE_RXMODE_PROMISC); 1324 } 1325 if (!(ifp->if_flags & IFF_RUNNING)) { 1326 sc->ste_tx_thresh = STE_TXSTART_THRESH; 1327 ste_init(sc); 1328 } 1329 } else { 1330 if (ifp->if_flags & IFF_RUNNING) 1331 ste_stop(sc); 1332 } 1333 sc->ste_if_flags = ifp->if_flags; 1334 error = 0; 1335 break; 1336 case SIOCADDMULTI: 1337 case SIOCDELMULTI: 1338 ste_setmulti(sc); 1339 error = 0; 1340 break; 1341 case SIOCGIFMEDIA: 1342 case SIOCSIFMEDIA: 1343 mii = device_get_softc(sc->ste_miibus); 1344 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1345 break; 1346 default: 1347 error = ether_ioctl(ifp, command, data); 1348 break; 1349 } 1350 return(error); 1351 } 1352 1353 static int 1354 ste_encap(struct ste_softc *sc, struct ste_chain *c, struct mbuf *m_head) 1355 { 1356 int frag = 0; 1357 struct ste_frag *f = NULL; 1358 struct mbuf *m; 1359 struct ste_desc *d; 1360 int total_len = 0; 1361 1362 d = c->ste_ptr; 1363 d->ste_ctl = 0; 1364 1365 encap_retry: 1366 for (m = m_head, frag = 0; m != NULL; m = m->m_next) { 1367 if (m->m_len != 0) { 1368 if (frag == STE_MAXFRAGS) 1369 break; 1370 total_len += m->m_len; 1371 f = &d->ste_frags[frag]; 1372 f->ste_addr = vtophys(mtod(m, vm_offset_t)); 1373 f->ste_len = m->m_len; 1374 frag++; 1375 } 1376 } 1377 1378 if (m != NULL) { 1379 struct mbuf *mn; 1380 1381 /* 1382 * We ran out of segments. We have to recopy this 1383 * mbuf chain first. Bail out if we can't get the 1384 * new buffers. Code borrowed from if_fxp.c. 1385 */ 1386 MGETHDR(mn, MB_DONTWAIT, MT_DATA); 1387 if (mn == NULL) { 1388 m_freem(m_head); 1389 return ENOMEM; 1390 } 1391 if (m_head->m_pkthdr.len > MHLEN) { 1392 MCLGET(mn, MB_DONTWAIT); 1393 if ((mn->m_flags & M_EXT) == 0) { 1394 m_freem(mn); 1395 m_freem(m_head); 1396 return ENOMEM; 1397 } 1398 } 1399 m_copydata(m_head, 0, m_head->m_pkthdr.len, 1400 mtod(mn, caddr_t)); 1401 mn->m_pkthdr.len = mn->m_len = m_head->m_pkthdr.len; 1402 m_freem(m_head); 1403 m_head = mn; 1404 goto encap_retry; 1405 } 1406 1407 c->ste_mbuf = m_head; 1408 d->ste_frags[frag - 1].ste_len |= STE_FRAG_LAST; 1409 d->ste_ctl = 1; 1410 1411 return(0); 1412 } 1413 1414 static void 1415 ste_start(struct ifnet *ifp) 1416 { 1417 struct ste_softc *sc; 1418 struct mbuf *m_head = NULL; 1419 struct ste_chain *cur_tx = NULL; 1420 int idx; 1421 1422 sc = ifp->if_softc; 1423 1424 if (!sc->ste_link) 1425 return; 1426 1427 if (ifp->if_flags & IFF_OACTIVE) 1428 return; 1429 1430 idx = sc->ste_cdata.ste_tx_prod; 1431 1432 while(sc->ste_cdata.ste_tx_chain[idx].ste_mbuf == NULL) { 1433 1434 if ((STE_TX_LIST_CNT - sc->ste_cdata.ste_tx_cnt) < 3) { 1435 ifp->if_flags |= IFF_OACTIVE; 1436 break; 1437 } 1438 1439 m_head = ifq_dequeue(&ifp->if_snd, NULL); 1440 if (m_head == NULL) 1441 break; 1442 1443 cur_tx = &sc->ste_cdata.ste_tx_chain[idx]; 1444 1445 if (ste_encap(sc, cur_tx, m_head) != 0) 1446 break; 1447 1448 cur_tx->ste_ptr->ste_next = 0; 1449 1450 if(sc->ste_tx_prev_idx < 0){ 1451 cur_tx->ste_ptr->ste_ctl = STE_TXCTL_DMAINTR | 1; 1452 /* Load address of the TX list */ 1453 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL); 1454 ste_wait(sc); 1455 1456 CSR_WRITE_4(sc, STE_TX_DMALIST_PTR, 1457 vtophys(&sc->ste_ldata->ste_tx_list[0])); 1458 1459 /* Set TX polling interval to start TX engine */ 1460 CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 64); 1461 1462 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 1463 ste_wait(sc); 1464 }else{ 1465 cur_tx->ste_ptr->ste_ctl = STE_TXCTL_DMAINTR | 1; 1466 sc->ste_cdata.ste_tx_chain[ 1467 sc->ste_tx_prev_idx].ste_ptr->ste_next 1468 = cur_tx->ste_phys; 1469 } 1470 1471 sc->ste_tx_prev_idx=idx; 1472 1473 BPF_MTAP(ifp, cur_tx->ste_mbuf); 1474 1475 STE_INC(idx, STE_TX_LIST_CNT); 1476 sc->ste_cdata.ste_tx_cnt++; 1477 ifp->if_timer = 5; 1478 sc->ste_cdata.ste_tx_prod = idx; 1479 } 1480 1481 return; 1482 } 1483 1484 static void 1485 ste_watchdog(struct ifnet *ifp) 1486 { 1487 struct ste_softc *sc; 1488 1489 sc = ifp->if_softc; 1490 1491 ifp->if_oerrors++; 1492 if_printf(ifp, "watchdog timeout\n"); 1493 1494 ste_txeoc(sc); 1495 ste_txeof(sc); 1496 ste_rxeof(sc); 1497 ste_reset(sc); 1498 ste_init(sc); 1499 1500 if (!ifq_is_empty(&ifp->if_snd)) 1501 ste_start(ifp); 1502 1503 return; 1504 } 1505 1506 static void 1507 ste_shutdown(device_t dev) 1508 { 1509 struct ste_softc *sc; 1510 1511 sc = device_get_softc(dev); 1512 1513 ste_stop(sc); 1514 1515 return; 1516 } 1517