1 /* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: src/sys/pci/if_ste.c,v 1.14.2.9 2003/02/05 22:03:57 mbr Exp $ 33 */ 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/sockio.h> 38 #include <sys/mbuf.h> 39 #include <sys/malloc.h> 40 #include <sys/kernel.h> 41 #include <sys/socket.h> 42 #include <sys/serialize.h> 43 #include <sys/bus.h> 44 #include <sys/rman.h> 45 #include <sys/thread2.h> 46 #include <sys/interrupt.h> 47 48 #include <net/if.h> 49 #include <net/ifq_var.h> 50 #include <net/if_arp.h> 51 #include <net/ethernet.h> 52 #include <net/if_dl.h> 53 #include <net/if_media.h> 54 #include <net/vlan/if_vlan_var.h> 55 56 #include <net/bpf.h> 57 58 #include <vm/vm.h> /* for vtophys */ 59 #include <vm/pmap.h> /* for vtophys */ 60 61 #include "../mii_layer/mii.h" 62 #include "../mii_layer/miivar.h" 63 64 #include <bus/pci/pcidevs.h> 65 #include <bus/pci/pcireg.h> 66 #include <bus/pci/pcivar.h> 67 68 /* "controller miibus0" required. See GENERIC if you get errors here. */ 69 #include "miibus_if.h" 70 71 #define STE_USEIOSPACE 72 73 #include "if_stereg.h" 74 75 /* 76 * Various supported device vendors/types and their names. 77 */ 78 static struct ste_type ste_devs[] = { 79 { PCI_VENDOR_SUNDANCETI, PCI_PRODUCT_SUNDANCETI_ST201, 80 "Sundance ST201 10/100BaseTX" }, 81 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DL1002, 82 "D-Link DFE-550TX 10/100BaseTX" }, 83 { 0, 0, NULL } 84 }; 85 86 static int ste_probe (device_t); 87 static int ste_attach (device_t); 88 static int ste_detach (device_t); 89 static void ste_init (void *); 90 static void ste_intr (void *); 91 static void ste_rxeof (struct ste_softc *); 92 static void ste_txeoc (struct ste_softc *); 93 static void ste_txeof (struct ste_softc *); 94 static void ste_stats_update (void *); 95 static void ste_stop (struct ste_softc *); 96 static void ste_reset (struct ste_softc *); 97 static int ste_ioctl (struct ifnet *, u_long, caddr_t, 98 struct ucred *); 99 static int ste_encap (struct ste_softc *, struct ste_chain *, 100 struct mbuf *); 101 static void ste_start (struct ifnet *, struct ifaltq_subque *); 102 static void ste_watchdog (struct ifnet *); 103 static void ste_shutdown (device_t); 104 static int ste_newbuf (struct ste_softc *, 105 struct ste_chain_onefrag *, 106 struct mbuf *); 107 static int ste_ifmedia_upd (struct ifnet *); 108 static void ste_ifmedia_sts (struct ifnet *, struct ifmediareq *); 109 110 static void ste_mii_sync (struct ste_softc *); 111 static void ste_mii_send (struct ste_softc *, u_int32_t, int); 112 static int ste_mii_readreg (struct ste_softc *, 113 struct ste_mii_frame *); 114 static int ste_mii_writereg (struct ste_softc *, 115 struct ste_mii_frame *); 116 static int ste_miibus_readreg (device_t, int, int); 117 static int ste_miibus_writereg (device_t, int, int, int); 118 static void ste_miibus_statchg (device_t); 119 120 static int ste_eeprom_wait (struct ste_softc *); 121 static int ste_read_eeprom (struct ste_softc *, caddr_t, int, 122 int, int); 123 static void ste_wait (struct ste_softc *); 124 static void ste_setmulti (struct ste_softc *); 125 static int ste_init_rx_list (struct ste_softc *); 126 static void ste_init_tx_list (struct ste_softc *); 127 128 #ifdef STE_USEIOSPACE 129 #define STE_RES SYS_RES_IOPORT 130 #define STE_RID STE_PCI_LOIO 131 #else 132 #define STE_RES SYS_RES_MEMORY 133 #define STE_RID STE_PCI_LOMEM 134 #endif 135 136 static device_method_t ste_methods[] = { 137 /* Device interface */ 138 DEVMETHOD(device_probe, ste_probe), 139 DEVMETHOD(device_attach, ste_attach), 140 DEVMETHOD(device_detach, ste_detach), 141 DEVMETHOD(device_shutdown, ste_shutdown), 142 143 /* bus interface */ 144 DEVMETHOD(bus_print_child, bus_generic_print_child), 145 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 146 147 /* MII interface */ 148 DEVMETHOD(miibus_readreg, ste_miibus_readreg), 149 DEVMETHOD(miibus_writereg, ste_miibus_writereg), 150 DEVMETHOD(miibus_statchg, ste_miibus_statchg), 151 152 { 0, 0 } 153 }; 154 155 static driver_t ste_driver = { 156 "ste", 157 ste_methods, 158 sizeof(struct ste_softc) 159 }; 160 161 static devclass_t ste_devclass; 162 163 DECLARE_DUMMY_MODULE(if_ste); 164 DRIVER_MODULE(if_ste, pci, ste_driver, ste_devclass, NULL, NULL); 165 DRIVER_MODULE(miibus, ste, miibus_driver, miibus_devclass, NULL, NULL); 166 167 #define STE_SETBIT4(sc, reg, x) \ 168 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | x) 169 170 #define STE_CLRBIT4(sc, reg, x) \ 171 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~x) 172 173 #define STE_SETBIT2(sc, reg, x) \ 174 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) | x) 175 176 #define STE_CLRBIT2(sc, reg, x) \ 177 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) & ~x) 178 179 #define STE_SETBIT1(sc, reg, x) \ 180 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | x) 181 182 #define STE_CLRBIT1(sc, reg, x) \ 183 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~x) 184 185 186 #define MII_SET(x) STE_SETBIT1(sc, STE_PHYCTL, x) 187 #define MII_CLR(x) STE_CLRBIT1(sc, STE_PHYCTL, x) 188 189 /* 190 * Sync the PHYs by setting data bit and strobing the clock 32 times. 191 */ 192 static void 193 ste_mii_sync(struct ste_softc *sc) 194 { 195 int i; 196 197 MII_SET(STE_PHYCTL_MDIR|STE_PHYCTL_MDATA); 198 199 for (i = 0; i < 32; i++) { 200 MII_SET(STE_PHYCTL_MCLK); 201 DELAY(1); 202 MII_CLR(STE_PHYCTL_MCLK); 203 DELAY(1); 204 } 205 206 return; 207 } 208 209 /* 210 * Clock a series of bits through the MII. 211 */ 212 static void 213 ste_mii_send(struct ste_softc *sc, u_int32_t bits, int cnt) 214 { 215 int i; 216 217 MII_CLR(STE_PHYCTL_MCLK); 218 219 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 220 if (bits & i) { 221 MII_SET(STE_PHYCTL_MDATA); 222 } else { 223 MII_CLR(STE_PHYCTL_MDATA); 224 } 225 DELAY(1); 226 MII_CLR(STE_PHYCTL_MCLK); 227 DELAY(1); 228 MII_SET(STE_PHYCTL_MCLK); 229 } 230 } 231 232 /* 233 * Read an PHY register through the MII. 234 */ 235 static int 236 ste_mii_readreg(struct ste_softc *sc, struct ste_mii_frame *frame) 237 { 238 int i, ack; 239 240 /* 241 * Set up frame for RX. 242 */ 243 frame->mii_stdelim = STE_MII_STARTDELIM; 244 frame->mii_opcode = STE_MII_READOP; 245 frame->mii_turnaround = 0; 246 frame->mii_data = 0; 247 248 CSR_WRITE_2(sc, STE_PHYCTL, 0); 249 /* 250 * Turn on data xmit. 251 */ 252 MII_SET(STE_PHYCTL_MDIR); 253 254 ste_mii_sync(sc); 255 256 /* 257 * Send command/address info. 258 */ 259 ste_mii_send(sc, frame->mii_stdelim, 2); 260 ste_mii_send(sc, frame->mii_opcode, 2); 261 ste_mii_send(sc, frame->mii_phyaddr, 5); 262 ste_mii_send(sc, frame->mii_regaddr, 5); 263 264 /* Turn off xmit. */ 265 MII_CLR(STE_PHYCTL_MDIR); 266 267 /* Idle bit */ 268 MII_CLR((STE_PHYCTL_MCLK|STE_PHYCTL_MDATA)); 269 DELAY(1); 270 MII_SET(STE_PHYCTL_MCLK); 271 DELAY(1); 272 273 /* Check for ack */ 274 MII_CLR(STE_PHYCTL_MCLK); 275 DELAY(1); 276 ack = CSR_READ_2(sc, STE_PHYCTL) & STE_PHYCTL_MDATA; 277 MII_SET(STE_PHYCTL_MCLK); 278 DELAY(1); 279 280 /* 281 * Now try reading data bits. If the ack failed, we still 282 * need to clock through 16 cycles to keep the PHY(s) in sync. 283 */ 284 if (ack) { 285 for(i = 0; i < 16; i++) { 286 MII_CLR(STE_PHYCTL_MCLK); 287 DELAY(1); 288 MII_SET(STE_PHYCTL_MCLK); 289 DELAY(1); 290 } 291 goto fail; 292 } 293 294 for (i = 0x8000; i; i >>= 1) { 295 MII_CLR(STE_PHYCTL_MCLK); 296 DELAY(1); 297 if (!ack) { 298 if (CSR_READ_2(sc, STE_PHYCTL) & STE_PHYCTL_MDATA) 299 frame->mii_data |= i; 300 DELAY(1); 301 } 302 MII_SET(STE_PHYCTL_MCLK); 303 DELAY(1); 304 } 305 306 fail: 307 308 MII_CLR(STE_PHYCTL_MCLK); 309 DELAY(1); 310 MII_SET(STE_PHYCTL_MCLK); 311 DELAY(1); 312 313 if (ack) 314 return(1); 315 return(0); 316 } 317 318 /* 319 * Write to a PHY register through the MII. 320 */ 321 static int 322 ste_mii_writereg(struct ste_softc *sc, struct ste_mii_frame *frame) 323 { 324 /* 325 * Set up frame for TX. 326 */ 327 328 frame->mii_stdelim = STE_MII_STARTDELIM; 329 frame->mii_opcode = STE_MII_WRITEOP; 330 frame->mii_turnaround = STE_MII_TURNAROUND; 331 332 /* 333 * Turn on data output. 334 */ 335 MII_SET(STE_PHYCTL_MDIR); 336 337 ste_mii_sync(sc); 338 339 ste_mii_send(sc, frame->mii_stdelim, 2); 340 ste_mii_send(sc, frame->mii_opcode, 2); 341 ste_mii_send(sc, frame->mii_phyaddr, 5); 342 ste_mii_send(sc, frame->mii_regaddr, 5); 343 ste_mii_send(sc, frame->mii_turnaround, 2); 344 ste_mii_send(sc, frame->mii_data, 16); 345 346 /* Idle bit. */ 347 MII_SET(STE_PHYCTL_MCLK); 348 DELAY(1); 349 MII_CLR(STE_PHYCTL_MCLK); 350 DELAY(1); 351 352 /* 353 * Turn off xmit. 354 */ 355 MII_CLR(STE_PHYCTL_MDIR); 356 357 return(0); 358 } 359 360 static int 361 ste_miibus_readreg(device_t dev, int phy, int reg) 362 { 363 struct ste_softc *sc; 364 struct ste_mii_frame frame; 365 366 sc = device_get_softc(dev); 367 368 if ( sc->ste_one_phy && phy != 0 ) 369 return (0); 370 371 bzero((char *)&frame, sizeof(frame)); 372 373 frame.mii_phyaddr = phy; 374 frame.mii_regaddr = reg; 375 ste_mii_readreg(sc, &frame); 376 377 return(frame.mii_data); 378 } 379 380 static int 381 ste_miibus_writereg(device_t dev, int phy, int reg, int data) 382 { 383 struct ste_softc *sc; 384 struct ste_mii_frame frame; 385 386 sc = device_get_softc(dev); 387 bzero((char *)&frame, sizeof(frame)); 388 389 frame.mii_phyaddr = phy; 390 frame.mii_regaddr = reg; 391 frame.mii_data = data; 392 393 ste_mii_writereg(sc, &frame); 394 395 return(0); 396 } 397 398 static void 399 ste_miibus_statchg(device_t dev) 400 { 401 struct ste_softc *sc; 402 struct mii_data *mii; 403 int i; 404 405 sc = device_get_softc(dev); 406 mii = device_get_softc(sc->ste_miibus); 407 408 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 409 STE_SETBIT2(sc, STE_MACCTL0, STE_MACCTL0_FULLDUPLEX); 410 } else { 411 STE_CLRBIT2(sc, STE_MACCTL0, STE_MACCTL0_FULLDUPLEX); 412 } 413 414 STE_SETBIT4(sc, STE_ASICCTL,STE_ASICCTL_RX_RESET | 415 STE_ASICCTL_TX_RESET); 416 for (i = 0; i < STE_TIMEOUT; i++) { 417 if (!(CSR_READ_4(sc, STE_ASICCTL) & STE_ASICCTL_RESET_BUSY)) 418 break; 419 } 420 if (i == STE_TIMEOUT) 421 if_printf(&sc->arpcom.ac_if, "rx reset never completed\n"); 422 423 return; 424 } 425 426 static int 427 ste_ifmedia_upd(struct ifnet *ifp) 428 { 429 struct ste_softc *sc; 430 struct mii_data *mii; 431 432 sc = ifp->if_softc; 433 mii = device_get_softc(sc->ste_miibus); 434 sc->ste_link = 0; 435 if (mii->mii_instance) { 436 struct mii_softc *miisc; 437 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 438 miisc = LIST_NEXT(miisc, mii_list)) 439 mii_phy_reset(miisc); 440 } 441 mii_mediachg(mii); 442 443 return(0); 444 } 445 446 static void 447 ste_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 448 { 449 struct ste_softc *sc; 450 struct mii_data *mii; 451 452 sc = ifp->if_softc; 453 mii = device_get_softc(sc->ste_miibus); 454 455 mii_pollstat(mii); 456 ifmr->ifm_active = mii->mii_media_active; 457 ifmr->ifm_status = mii->mii_media_status; 458 459 return; 460 } 461 462 static void 463 ste_wait(struct ste_softc *sc) 464 { 465 int i; 466 467 for (i = 0; i < STE_TIMEOUT; i++) { 468 if (!(CSR_READ_4(sc, STE_DMACTL) & STE_DMACTL_DMA_HALTINPROG)) 469 break; 470 } 471 472 if (i == STE_TIMEOUT) 473 if_printf(&sc->arpcom.ac_if, "command never completed!\n"); 474 475 return; 476 } 477 478 /* 479 * The EEPROM is slow: give it time to come ready after issuing 480 * it a command. 481 */ 482 static int 483 ste_eeprom_wait(struct ste_softc *sc) 484 { 485 int i; 486 487 DELAY(1000); 488 489 for (i = 0; i < 100; i++) { 490 if (CSR_READ_2(sc, STE_EEPROM_CTL) & STE_EECTL_BUSY) 491 DELAY(1000); 492 else 493 break; 494 } 495 496 if (i == 100) { 497 if_printf(&sc->arpcom.ac_if, "eeprom failed to come ready\n"); 498 return(1); 499 } 500 501 return(0); 502 } 503 504 /* 505 * Read a sequence of words from the EEPROM. Note that ethernet address 506 * data is stored in the EEPROM in network byte order. 507 */ 508 static int 509 ste_read_eeprom(struct ste_softc *sc, caddr_t dest, int off, int cnt, int swap) 510 { 511 int err = 0, i; 512 u_int16_t word = 0, *ptr; 513 514 if (ste_eeprom_wait(sc)) 515 return(1); 516 517 for (i = 0; i < cnt; i++) { 518 CSR_WRITE_2(sc, STE_EEPROM_CTL, STE_EEOPCODE_READ | (off + i)); 519 err = ste_eeprom_wait(sc); 520 if (err) 521 break; 522 word = CSR_READ_2(sc, STE_EEPROM_DATA); 523 ptr = (u_int16_t *)(dest + (i * 2)); 524 if (swap) 525 *ptr = ntohs(word); 526 else 527 *ptr = word; 528 } 529 530 return(err ? 1 : 0); 531 } 532 533 static void 534 ste_setmulti(struct ste_softc *sc) 535 { 536 struct ifnet *ifp; 537 int h = 0; 538 u_int32_t hashes[2] = { 0, 0 }; 539 struct ifmultiaddr *ifma; 540 541 ifp = &sc->arpcom.ac_if; 542 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 543 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_ALLMULTI); 544 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_MULTIHASH); 545 return; 546 } 547 548 /* first, zot all the existing hash bits */ 549 CSR_WRITE_2(sc, STE_MAR0, 0); 550 CSR_WRITE_2(sc, STE_MAR1, 0); 551 CSR_WRITE_2(sc, STE_MAR2, 0); 552 CSR_WRITE_2(sc, STE_MAR3, 0); 553 554 /* now program new ones */ 555 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 556 if (ifma->ifma_addr->sa_family != AF_LINK) 557 continue; 558 h = ether_crc32_be( 559 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 560 ETHER_ADDR_LEN) & 0x3f; 561 if (h < 32) 562 hashes[0] |= (1 << h); 563 else 564 hashes[1] |= (1 << (h - 32)); 565 } 566 567 CSR_WRITE_2(sc, STE_MAR0, hashes[0] & 0xFFFF); 568 CSR_WRITE_2(sc, STE_MAR1, (hashes[0] >> 16) & 0xFFFF); 569 CSR_WRITE_2(sc, STE_MAR2, hashes[1] & 0xFFFF); 570 CSR_WRITE_2(sc, STE_MAR3, (hashes[1] >> 16) & 0xFFFF); 571 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_ALLMULTI); 572 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_MULTIHASH); 573 574 return; 575 } 576 577 static void 578 ste_intr(void *xsc) 579 { 580 struct ste_softc *sc; 581 struct ifnet *ifp; 582 u_int16_t status; 583 584 sc = xsc; 585 ifp = &sc->arpcom.ac_if; 586 587 /* See if this is really our interrupt. */ 588 if (!(CSR_READ_2(sc, STE_ISR) & STE_ISR_INTLATCH)) 589 return; 590 591 for (;;) { 592 status = CSR_READ_2(sc, STE_ISR_ACK); 593 594 if (!(status & STE_INTRS)) 595 break; 596 597 if (status & STE_ISR_RX_DMADONE) 598 ste_rxeof(sc); 599 600 if (status & STE_ISR_TX_DMADONE) 601 ste_txeof(sc); 602 603 if (status & STE_ISR_TX_DONE) 604 ste_txeoc(sc); 605 606 if (status & STE_ISR_STATS_OFLOW) { 607 callout_stop(&sc->ste_stat_timer); 608 ste_stats_update(sc); 609 } 610 611 if (status & STE_ISR_LINKEVENT) 612 mii_pollstat(device_get_softc(sc->ste_miibus)); 613 614 if (status & STE_ISR_HOSTERR) { 615 ste_reset(sc); 616 ste_init(sc); 617 } 618 } 619 620 /* Re-enable interrupts */ 621 CSR_WRITE_2(sc, STE_IMR, STE_INTRS); 622 623 if (!ifq_is_empty(&ifp->if_snd)) 624 if_devstart(ifp); 625 } 626 627 /* 628 * A frame has been uploaded: pass the resulting mbuf chain up to 629 * the higher level protocols. 630 */ 631 static void 632 ste_rxeof(struct ste_softc *sc) 633 { 634 struct mbuf *m; 635 struct ifnet *ifp; 636 struct ste_chain_onefrag *cur_rx; 637 int total_len = 0, count=0; 638 u_int32_t rxstat; 639 640 ifp = &sc->arpcom.ac_if; 641 642 while((rxstat = sc->ste_cdata.ste_rx_head->ste_ptr->ste_status) 643 & STE_RXSTAT_DMADONE) { 644 if ((STE_RX_LIST_CNT - count) < 3) { 645 break; 646 } 647 648 cur_rx = sc->ste_cdata.ste_rx_head; 649 sc->ste_cdata.ste_rx_head = cur_rx->ste_next; 650 651 /* 652 * If an error occurs, update stats, clear the 653 * status word and leave the mbuf cluster in place: 654 * it should simply get re-used next time this descriptor 655 * comes up in the ring. 656 */ 657 if (rxstat & STE_RXSTAT_FRAME_ERR) { 658 ifp->if_ierrors++; 659 cur_rx->ste_ptr->ste_status = 0; 660 continue; 661 } 662 663 /* 664 * If there error bit was not set, the upload complete 665 * bit should be set which means we have a valid packet. 666 * If not, something truly strange has happened. 667 */ 668 if (!(rxstat & STE_RXSTAT_DMADONE)) { 669 if_printf(ifp, "bad receive status -- packet dropped"); 670 ifp->if_ierrors++; 671 cur_rx->ste_ptr->ste_status = 0; 672 continue; 673 } 674 675 /* No errors; receive the packet. */ 676 m = cur_rx->ste_mbuf; 677 total_len = cur_rx->ste_ptr->ste_status & STE_RXSTAT_FRAMELEN; 678 679 /* 680 * Try to conjure up a new mbuf cluster. If that 681 * fails, it means we have an out of memory condition and 682 * should leave the buffer in place and continue. This will 683 * result in a lost packet, but there's little else we 684 * can do in this situation. 685 */ 686 if (ste_newbuf(sc, cur_rx, NULL) == ENOBUFS) { 687 ifp->if_ierrors++; 688 cur_rx->ste_ptr->ste_status = 0; 689 continue; 690 } 691 692 ifp->if_ipackets++; 693 m->m_pkthdr.rcvif = ifp; 694 m->m_pkthdr.len = m->m_len = total_len; 695 696 ifp->if_input(ifp, m); 697 698 cur_rx->ste_ptr->ste_status = 0; 699 count++; 700 } 701 702 return; 703 } 704 705 static void 706 ste_txeoc(struct ste_softc *sc) 707 { 708 u_int8_t txstat; 709 struct ifnet *ifp; 710 711 ifp = &sc->arpcom.ac_if; 712 713 while ((txstat = CSR_READ_1(sc, STE_TX_STATUS)) & 714 STE_TXSTATUS_TXDONE) { 715 if (txstat & STE_TXSTATUS_UNDERRUN || 716 txstat & STE_TXSTATUS_EXCESSCOLLS || 717 txstat & STE_TXSTATUS_RECLAIMERR) { 718 ifp->if_oerrors++; 719 if_printf(ifp, "transmission error: %x\n", txstat); 720 721 ste_reset(sc); 722 ste_init(sc); 723 724 if (txstat & STE_TXSTATUS_UNDERRUN && 725 sc->ste_tx_thresh < STE_PACKET_SIZE) { 726 sc->ste_tx_thresh += STE_MIN_FRAMELEN; 727 if_printf(ifp, "tx underrun, increasing tx" 728 " start threshold to %d bytes\n", 729 sc->ste_tx_thresh); 730 } 731 CSR_WRITE_2(sc, STE_TX_STARTTHRESH, sc->ste_tx_thresh); 732 CSR_WRITE_2(sc, STE_TX_RECLAIM_THRESH, 733 (STE_PACKET_SIZE >> 4)); 734 } 735 ste_init(sc); 736 CSR_WRITE_2(sc, STE_TX_STATUS, txstat); 737 } 738 739 return; 740 } 741 742 static void 743 ste_txeof(struct ste_softc *sc) 744 { 745 struct ste_chain *cur_tx = NULL; 746 struct ifnet *ifp; 747 int idx; 748 749 ifp = &sc->arpcom.ac_if; 750 751 idx = sc->ste_cdata.ste_tx_cons; 752 while(idx != sc->ste_cdata.ste_tx_prod) { 753 cur_tx = &sc->ste_cdata.ste_tx_chain[idx]; 754 755 if (!(cur_tx->ste_ptr->ste_ctl & STE_TXCTL_DMADONE)) 756 break; 757 758 if (cur_tx->ste_mbuf != NULL) { 759 m_freem(cur_tx->ste_mbuf); 760 cur_tx->ste_mbuf = NULL; 761 } 762 763 ifp->if_opackets++; 764 765 sc->ste_cdata.ste_tx_cnt--; 766 STE_INC(idx, STE_TX_LIST_CNT); 767 ifp->if_timer = 0; 768 } 769 770 sc->ste_cdata.ste_tx_cons = idx; 771 772 if (cur_tx != NULL) 773 ifq_clr_oactive(&ifp->if_snd); 774 775 return; 776 } 777 778 static void 779 ste_stats_update(void *xsc) 780 { 781 struct ste_softc *sc; 782 struct ifnet *ifp; 783 struct mii_data *mii; 784 785 sc = xsc; 786 ifp = &sc->arpcom.ac_if; 787 mii = device_get_softc(sc->ste_miibus); 788 789 lwkt_serialize_enter(ifp->if_serializer); 790 791 ifp->if_collisions += CSR_READ_1(sc, STE_LATE_COLLS) 792 + CSR_READ_1(sc, STE_MULTI_COLLS) 793 + CSR_READ_1(sc, STE_SINGLE_COLLS); 794 795 if (!sc->ste_link) { 796 mii_pollstat(mii); 797 if (mii->mii_media_status & IFM_ACTIVE && 798 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 799 sc->ste_link++; 800 /* 801 * we don't get a call-back on re-init so do it 802 * otherwise we get stuck in the wrong link state 803 */ 804 ste_miibus_statchg(sc->ste_dev); 805 if (!ifq_is_empty(&ifp->if_snd)) 806 if_devstart(ifp); 807 } 808 } 809 810 callout_reset(&sc->ste_stat_timer, hz, ste_stats_update, sc); 811 lwkt_serialize_exit(ifp->if_serializer); 812 } 813 814 815 /* 816 * Probe for a Sundance ST201 chip. Check the PCI vendor and device 817 * IDs against our list and return a device name if we find a match. 818 */ 819 static int 820 ste_probe(device_t dev) 821 { 822 struct ste_type *t; 823 824 t = ste_devs; 825 826 while(t->ste_name != NULL) { 827 if ((pci_get_vendor(dev) == t->ste_vid) && 828 (pci_get_device(dev) == t->ste_did)) { 829 device_set_desc(dev, t->ste_name); 830 return(0); 831 } 832 t++; 833 } 834 835 return(ENXIO); 836 } 837 838 /* 839 * Attach the interface. Allocate softc structures, do ifmedia 840 * setup and ethernet/BPF attach. 841 */ 842 static int 843 ste_attach(device_t dev) 844 { 845 struct ste_softc *sc; 846 struct ifnet *ifp; 847 int error = 0, rid; 848 uint8_t eaddr[ETHER_ADDR_LEN]; 849 850 sc = device_get_softc(dev); 851 sc->ste_dev = dev; 852 853 /* 854 * Only use one PHY since this chip reports multiple 855 * Note on the DFE-550 the PHY is at 1 on the DFE-580 856 * it is at 0 & 1. It is rev 0x12. 857 */ 858 if (pci_get_vendor(dev) == PCI_VENDOR_DLINK && 859 pci_get_device(dev) == PCI_PRODUCT_DLINK_DL1002 && 860 pci_get_revid(dev) == 0x12 ) 861 sc->ste_one_phy = 1; 862 863 /* 864 * Handle power management nonsense. 865 */ 866 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 867 u_int32_t iobase, membase, irq; 868 869 /* Save important PCI config data. */ 870 iobase = pci_read_config(dev, STE_PCI_LOIO, 4); 871 membase = pci_read_config(dev, STE_PCI_LOMEM, 4); 872 irq = pci_read_config(dev, STE_PCI_INTLINE, 4); 873 874 /* Reset the power state. */ 875 device_printf(dev, "chip is in D%d power mode " 876 "-- setting to D0\n", pci_get_powerstate(dev)); 877 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 878 879 /* Restore PCI config data. */ 880 pci_write_config(dev, STE_PCI_LOIO, iobase, 4); 881 pci_write_config(dev, STE_PCI_LOMEM, membase, 4); 882 pci_write_config(dev, STE_PCI_INTLINE, irq, 4); 883 } 884 885 /* 886 * Map control/status registers. 887 */ 888 pci_enable_busmaster(dev); 889 890 rid = STE_RID; 891 sc->ste_res = bus_alloc_resource_any(dev, STE_RES, &rid, RF_ACTIVE); 892 893 if (sc->ste_res == NULL) { 894 device_printf(dev, "couldn't map ports/memory\n"); 895 error = ENXIO; 896 goto fail; 897 } 898 899 sc->ste_btag = rman_get_bustag(sc->ste_res); 900 sc->ste_bhandle = rman_get_bushandle(sc->ste_res); 901 902 rid = 0; 903 sc->ste_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 904 RF_SHAREABLE | RF_ACTIVE); 905 906 if (sc->ste_irq == NULL) { 907 device_printf(dev, "couldn't map interrupt\n"); 908 error = ENXIO; 909 goto fail; 910 } 911 912 callout_init(&sc->ste_stat_timer); 913 914 ifp = &sc->arpcom.ac_if; 915 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 916 917 /* Reset the adapter. */ 918 ste_reset(sc); 919 920 /* 921 * Get station address from the EEPROM. 922 */ 923 if (ste_read_eeprom(sc, eaddr, STE_EEADDR_NODE0, 3, 0)) { 924 device_printf(dev, "failed to read station address\n"); 925 error = ENXIO; 926 goto fail; 927 } 928 929 /* Allocate the descriptor queues. */ 930 sc->ste_ldata = contigmalloc(sizeof(struct ste_list_data), M_DEVBUF, 931 M_WAITOK | M_ZERO, 0, 0xffffffff, PAGE_SIZE, 0); 932 933 if (sc->ste_ldata == NULL) { 934 device_printf(dev, "no memory for list buffers!\n"); 935 error = ENXIO; 936 goto fail; 937 } 938 939 /* Do MII setup. */ 940 if (mii_phy_probe(dev, &sc->ste_miibus, 941 ste_ifmedia_upd, ste_ifmedia_sts)) { 942 device_printf(dev, "MII without any phy!\n"); 943 error = ENXIO; 944 goto fail; 945 } 946 947 ifp->if_softc = sc; 948 ifp->if_mtu = ETHERMTU; 949 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 950 ifp->if_ioctl = ste_ioctl; 951 ifp->if_start = ste_start; 952 ifp->if_watchdog = ste_watchdog; 953 ifp->if_init = ste_init; 954 ifp->if_baudrate = 10000000; 955 ifq_set_maxlen(&ifp->if_snd, STE_TX_LIST_CNT - 1); 956 ifq_set_ready(&ifp->if_snd); 957 958 sc->ste_tx_thresh = STE_TXSTART_THRESH; 959 960 /* 961 * Call MI attach routine. 962 */ 963 ether_ifattach(ifp, eaddr, NULL); 964 965 /* 966 * Tell the upper layer(s) we support long frames. 967 */ 968 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 969 970 error = bus_setup_intr(dev, sc->ste_irq, INTR_MPSAFE, 971 ste_intr, sc, &sc->ste_intrhand, 972 ifp->if_serializer); 973 if (error) { 974 device_printf(dev, "couldn't set up irq\n"); 975 ether_ifdetach(ifp); 976 goto fail; 977 } 978 979 ifq_set_cpuid(&ifp->if_snd, rman_get_cpuid(sc->ste_irq)); 980 981 return 0; 982 983 fail: 984 ste_detach(dev); 985 return(error); 986 } 987 988 static int 989 ste_detach(device_t dev) 990 { 991 struct ste_softc *sc = device_get_softc(dev); 992 struct ifnet *ifp = &sc->arpcom.ac_if; 993 994 if (device_is_attached(dev)) { 995 lwkt_serialize_enter(ifp->if_serializer); 996 ste_stop(sc); 997 bus_teardown_intr(dev, sc->ste_irq, sc->ste_intrhand); 998 lwkt_serialize_exit(ifp->if_serializer); 999 1000 ether_ifdetach(ifp); 1001 } 1002 if (sc->ste_miibus != NULL) 1003 device_delete_child(dev, sc->ste_miibus); 1004 bus_generic_detach(dev); 1005 1006 if (sc->ste_irq != NULL) 1007 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq); 1008 if (sc->ste_res != NULL) 1009 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res); 1010 if (sc->ste_ldata != NULL) { 1011 contigfree(sc->ste_ldata, sizeof(struct ste_list_data), 1012 M_DEVBUF); 1013 } 1014 1015 return(0); 1016 } 1017 1018 static int 1019 ste_newbuf(struct ste_softc *sc, struct ste_chain_onefrag *c, 1020 struct mbuf *m) 1021 { 1022 struct mbuf *m_new = NULL; 1023 1024 if (m == NULL) { 1025 MGETHDR(m_new, MB_DONTWAIT, MT_DATA); 1026 if (m_new == NULL) 1027 return(ENOBUFS); 1028 MCLGET(m_new, MB_DONTWAIT); 1029 if (!(m_new->m_flags & M_EXT)) { 1030 m_freem(m_new); 1031 return(ENOBUFS); 1032 } 1033 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1034 } else { 1035 m_new = m; 1036 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1037 m_new->m_data = m_new->m_ext.ext_buf; 1038 } 1039 1040 m_adj(m_new, ETHER_ALIGN); 1041 1042 c->ste_mbuf = m_new; 1043 c->ste_ptr->ste_status = 0; 1044 c->ste_ptr->ste_frag.ste_addr = vtophys(mtod(m_new, caddr_t)); 1045 c->ste_ptr->ste_frag.ste_len = (1536 + EVL_ENCAPLEN) | STE_FRAG_LAST; 1046 1047 return(0); 1048 } 1049 1050 static int 1051 ste_init_rx_list(struct ste_softc *sc) 1052 { 1053 struct ste_chain_data *cd; 1054 struct ste_list_data *ld; 1055 int i; 1056 1057 cd = &sc->ste_cdata; 1058 ld = sc->ste_ldata; 1059 1060 for (i = 0; i < STE_RX_LIST_CNT; i++) { 1061 cd->ste_rx_chain[i].ste_ptr = &ld->ste_rx_list[i]; 1062 if (ste_newbuf(sc, &cd->ste_rx_chain[i], NULL) == ENOBUFS) 1063 return(ENOBUFS); 1064 if (i == (STE_RX_LIST_CNT - 1)) { 1065 cd->ste_rx_chain[i].ste_next = 1066 &cd->ste_rx_chain[0]; 1067 ld->ste_rx_list[i].ste_next = 1068 vtophys(&ld->ste_rx_list[0]); 1069 } else { 1070 cd->ste_rx_chain[i].ste_next = 1071 &cd->ste_rx_chain[i + 1]; 1072 ld->ste_rx_list[i].ste_next = 1073 vtophys(&ld->ste_rx_list[i + 1]); 1074 } 1075 ld->ste_rx_list[i].ste_status = 0; 1076 } 1077 1078 cd->ste_rx_head = &cd->ste_rx_chain[0]; 1079 1080 return(0); 1081 } 1082 1083 static void 1084 ste_init_tx_list(struct ste_softc *sc) 1085 { 1086 struct ste_chain_data *cd; 1087 struct ste_list_data *ld; 1088 int i; 1089 1090 cd = &sc->ste_cdata; 1091 ld = sc->ste_ldata; 1092 for (i = 0; i < STE_TX_LIST_CNT; i++) { 1093 cd->ste_tx_chain[i].ste_ptr = &ld->ste_tx_list[i]; 1094 cd->ste_tx_chain[i].ste_ptr->ste_next = 0; 1095 cd->ste_tx_chain[i].ste_ptr->ste_ctl = 0; 1096 cd->ste_tx_chain[i].ste_phys = vtophys(&ld->ste_tx_list[i]); 1097 if (i == (STE_TX_LIST_CNT - 1)) 1098 cd->ste_tx_chain[i].ste_next = 1099 &cd->ste_tx_chain[0]; 1100 else 1101 cd->ste_tx_chain[i].ste_next = 1102 &cd->ste_tx_chain[i + 1]; 1103 if (i == 0) 1104 cd->ste_tx_chain[i].ste_prev = 1105 &cd->ste_tx_chain[STE_TX_LIST_CNT - 1]; 1106 else 1107 cd->ste_tx_chain[i].ste_prev = 1108 &cd->ste_tx_chain[i - 1]; 1109 } 1110 1111 cd->ste_tx_prod = 0; 1112 cd->ste_tx_cons = 0; 1113 cd->ste_tx_cnt = 0; 1114 1115 return; 1116 } 1117 1118 static void 1119 ste_init(void *xsc) 1120 { 1121 struct ste_softc *sc; 1122 int i; 1123 struct ifnet *ifp; 1124 1125 sc = xsc; 1126 ifp = &sc->arpcom.ac_if; 1127 1128 ste_stop(sc); 1129 1130 /* Init our MAC address */ 1131 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1132 CSR_WRITE_1(sc, STE_PAR0 + i, sc->arpcom.ac_enaddr[i]); 1133 } 1134 1135 /* Init RX list */ 1136 if (ste_init_rx_list(sc) == ENOBUFS) { 1137 if_printf(ifp, "initialization failed: no " 1138 "memory for RX buffers\n"); 1139 ste_stop(sc); 1140 return; 1141 } 1142 1143 /* Set RX polling interval */ 1144 CSR_WRITE_1(sc, STE_RX_DMAPOLL_PERIOD, 1); 1145 1146 /* Init TX descriptors */ 1147 ste_init_tx_list(sc); 1148 1149 /* Set the TX freethresh value */ 1150 CSR_WRITE_1(sc, STE_TX_DMABURST_THRESH, STE_PACKET_SIZE >> 8); 1151 1152 /* Set the TX start threshold for best performance. */ 1153 CSR_WRITE_2(sc, STE_TX_STARTTHRESH, sc->ste_tx_thresh); 1154 1155 /* Set the TX reclaim threshold. */ 1156 CSR_WRITE_1(sc, STE_TX_RECLAIM_THRESH, (STE_PACKET_SIZE >> 4)); 1157 1158 /* Set up the RX filter. */ 1159 CSR_WRITE_1(sc, STE_RX_MODE, STE_RXMODE_UNICAST); 1160 1161 /* If we want promiscuous mode, set the allframes bit. */ 1162 if (ifp->if_flags & IFF_PROMISC) { 1163 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_PROMISC); 1164 } else { 1165 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_PROMISC); 1166 } 1167 1168 /* Set capture broadcast bit to accept broadcast frames. */ 1169 if (ifp->if_flags & IFF_BROADCAST) { 1170 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_BROADCAST); 1171 } else { 1172 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_BROADCAST); 1173 } 1174 1175 ste_setmulti(sc); 1176 1177 /* Load the address of the RX list. */ 1178 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_STALL); 1179 ste_wait(sc); 1180 CSR_WRITE_4(sc, STE_RX_DMALIST_PTR, 1181 vtophys(&sc->ste_ldata->ste_rx_list[0])); 1182 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL); 1183 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL); 1184 1185 /* Set TX polling interval (defer until we TX first packet */ 1186 CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 0); 1187 1188 /* Load address of the TX list */ 1189 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL); 1190 ste_wait(sc); 1191 CSR_WRITE_4(sc, STE_TX_DMALIST_PTR, 0); 1192 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 1193 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 1194 ste_wait(sc); 1195 sc->ste_tx_prev_idx=-1; 1196 1197 /* Enable receiver and transmitter */ 1198 CSR_WRITE_2(sc, STE_MACCTL0, 0); 1199 CSR_WRITE_2(sc, STE_MACCTL1, 0); 1200 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_TX_ENABLE); 1201 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_RX_ENABLE); 1202 1203 /* Enable stats counters. */ 1204 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_STATS_ENABLE); 1205 1206 /* Enable interrupts. */ 1207 CSR_WRITE_2(sc, STE_ISR, 0xFFFF); 1208 CSR_WRITE_2(sc, STE_IMR, STE_INTRS); 1209 1210 /* Accept VLAN length packets */ 1211 CSR_WRITE_2(sc, STE_MAX_FRAMELEN, ETHER_MAX_LEN + EVL_ENCAPLEN); 1212 1213 ste_ifmedia_upd(ifp); 1214 1215 ifp->if_flags |= IFF_RUNNING; 1216 ifq_clr_oactive(&ifp->if_snd); 1217 1218 callout_reset(&sc->ste_stat_timer, hz, ste_stats_update, sc); 1219 } 1220 1221 static void 1222 ste_stop(struct ste_softc *sc) 1223 { 1224 int i; 1225 struct ifnet *ifp; 1226 1227 ifp = &sc->arpcom.ac_if; 1228 1229 callout_stop(&sc->ste_stat_timer); 1230 1231 CSR_WRITE_2(sc, STE_IMR, 0); 1232 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_TX_DISABLE); 1233 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_RX_DISABLE); 1234 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_STATS_DISABLE); 1235 STE_SETBIT2(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL); 1236 STE_SETBIT2(sc, STE_DMACTL, STE_DMACTL_RXDMA_STALL); 1237 ste_wait(sc); 1238 /* 1239 * Try really hard to stop the RX engine or under heavy RX 1240 * data chip will write into de-allocated memory. 1241 */ 1242 ste_reset(sc); 1243 1244 sc->ste_link = 0; 1245 1246 for (i = 0; i < STE_RX_LIST_CNT; i++) { 1247 if (sc->ste_cdata.ste_rx_chain[i].ste_mbuf != NULL) { 1248 m_freem(sc->ste_cdata.ste_rx_chain[i].ste_mbuf); 1249 sc->ste_cdata.ste_rx_chain[i].ste_mbuf = NULL; 1250 } 1251 } 1252 1253 for (i = 0; i < STE_TX_LIST_CNT; i++) { 1254 if (sc->ste_cdata.ste_tx_chain[i].ste_mbuf != NULL) { 1255 m_freem(sc->ste_cdata.ste_tx_chain[i].ste_mbuf); 1256 sc->ste_cdata.ste_tx_chain[i].ste_mbuf = NULL; 1257 } 1258 } 1259 1260 bzero(sc->ste_ldata, sizeof(struct ste_list_data)); 1261 1262 ifp->if_flags &= ~IFF_RUNNING; 1263 ifq_clr_oactive(&ifp->if_snd); 1264 1265 return; 1266 } 1267 1268 static void 1269 ste_reset(struct ste_softc *sc) 1270 { 1271 int i; 1272 1273 STE_SETBIT4(sc, STE_ASICCTL, 1274 STE_ASICCTL_GLOBAL_RESET|STE_ASICCTL_RX_RESET| 1275 STE_ASICCTL_TX_RESET|STE_ASICCTL_DMA_RESET| 1276 STE_ASICCTL_FIFO_RESET|STE_ASICCTL_NETWORK_RESET| 1277 STE_ASICCTL_AUTOINIT_RESET|STE_ASICCTL_HOST_RESET| 1278 STE_ASICCTL_EXTRESET_RESET); 1279 1280 DELAY(100000); 1281 1282 for (i = 0; i < STE_TIMEOUT; i++) { 1283 if (!(CSR_READ_4(sc, STE_ASICCTL) & STE_ASICCTL_RESET_BUSY)) 1284 break; 1285 } 1286 1287 if (i == STE_TIMEOUT) 1288 if_printf(&sc->arpcom.ac_if, "global reset never completed\n"); 1289 1290 return; 1291 } 1292 1293 static int 1294 ste_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr) 1295 { 1296 struct ste_softc *sc; 1297 struct ifreq *ifr; 1298 struct mii_data *mii; 1299 int error = 0; 1300 1301 sc = ifp->if_softc; 1302 ifr = (struct ifreq *)data; 1303 1304 switch(command) { 1305 case SIOCSIFFLAGS: 1306 if (ifp->if_flags & IFF_UP) { 1307 if (ifp->if_flags & IFF_RUNNING && 1308 ifp->if_flags & IFF_PROMISC && 1309 !(sc->ste_if_flags & IFF_PROMISC)) { 1310 STE_SETBIT1(sc, STE_RX_MODE, 1311 STE_RXMODE_PROMISC); 1312 } else if (ifp->if_flags & IFF_RUNNING && 1313 !(ifp->if_flags & IFF_PROMISC) && 1314 sc->ste_if_flags & IFF_PROMISC) { 1315 STE_CLRBIT1(sc, STE_RX_MODE, 1316 STE_RXMODE_PROMISC); 1317 } 1318 if (!(ifp->if_flags & IFF_RUNNING)) { 1319 sc->ste_tx_thresh = STE_TXSTART_THRESH; 1320 ste_init(sc); 1321 } 1322 } else { 1323 if (ifp->if_flags & IFF_RUNNING) 1324 ste_stop(sc); 1325 } 1326 sc->ste_if_flags = ifp->if_flags; 1327 error = 0; 1328 break; 1329 case SIOCADDMULTI: 1330 case SIOCDELMULTI: 1331 ste_setmulti(sc); 1332 error = 0; 1333 break; 1334 case SIOCGIFMEDIA: 1335 case SIOCSIFMEDIA: 1336 mii = device_get_softc(sc->ste_miibus); 1337 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1338 break; 1339 default: 1340 error = ether_ioctl(ifp, command, data); 1341 break; 1342 } 1343 return(error); 1344 } 1345 1346 static int 1347 ste_encap(struct ste_softc *sc, struct ste_chain *c, struct mbuf *m_head) 1348 { 1349 int frag = 0; 1350 struct ste_frag *f = NULL; 1351 struct mbuf *m; 1352 struct ste_desc *d; 1353 int total_len = 0; 1354 1355 d = c->ste_ptr; 1356 d->ste_ctl = 0; 1357 1358 encap_retry: 1359 for (m = m_head, frag = 0; m != NULL; m = m->m_next) { 1360 if (m->m_len != 0) { 1361 if (frag == STE_MAXFRAGS) 1362 break; 1363 total_len += m->m_len; 1364 f = &d->ste_frags[frag]; 1365 f->ste_addr = vtophys(mtod(m, vm_offset_t)); 1366 f->ste_len = m->m_len; 1367 frag++; 1368 } 1369 } 1370 1371 if (m != NULL) { 1372 struct mbuf *mn; 1373 1374 /* 1375 * We ran out of segments. We have to recopy this 1376 * mbuf chain first. Bail out if we can't get the 1377 * new buffers. Code borrowed from if_fxp.c. 1378 */ 1379 MGETHDR(mn, MB_DONTWAIT, MT_DATA); 1380 if (mn == NULL) { 1381 m_freem(m_head); 1382 return ENOMEM; 1383 } 1384 if (m_head->m_pkthdr.len > MHLEN) { 1385 MCLGET(mn, MB_DONTWAIT); 1386 if ((mn->m_flags & M_EXT) == 0) { 1387 m_freem(mn); 1388 m_freem(m_head); 1389 return ENOMEM; 1390 } 1391 } 1392 m_copydata(m_head, 0, m_head->m_pkthdr.len, 1393 mtod(mn, caddr_t)); 1394 mn->m_pkthdr.len = mn->m_len = m_head->m_pkthdr.len; 1395 m_freem(m_head); 1396 m_head = mn; 1397 goto encap_retry; 1398 } 1399 1400 c->ste_mbuf = m_head; 1401 d->ste_frags[frag - 1].ste_len |= STE_FRAG_LAST; 1402 d->ste_ctl = 1; 1403 1404 return(0); 1405 } 1406 1407 static void 1408 ste_start(struct ifnet *ifp, struct ifaltq_subque *ifsq) 1409 { 1410 struct ste_softc *sc; 1411 struct mbuf *m_head = NULL; 1412 struct ste_chain *cur_tx = NULL; 1413 int idx; 1414 1415 ASSERT_ALTQ_SQ_DEFAULT(ifp, ifsq); 1416 1417 sc = ifp->if_softc; 1418 1419 if (!sc->ste_link) { 1420 ifq_purge(&ifp->if_snd); 1421 return; 1422 } 1423 1424 if ((ifp->if_flags & IFF_RUNNING) == 0 || ifq_is_oactive(&ifp->if_snd)) 1425 return; 1426 1427 idx = sc->ste_cdata.ste_tx_prod; 1428 1429 while(sc->ste_cdata.ste_tx_chain[idx].ste_mbuf == NULL) { 1430 1431 if ((STE_TX_LIST_CNT - sc->ste_cdata.ste_tx_cnt) < 3) { 1432 ifq_set_oactive(&ifp->if_snd); 1433 break; 1434 } 1435 1436 m_head = ifq_dequeue(&ifp->if_snd, NULL); 1437 if (m_head == NULL) 1438 break; 1439 1440 cur_tx = &sc->ste_cdata.ste_tx_chain[idx]; 1441 1442 if (ste_encap(sc, cur_tx, m_head) != 0) 1443 break; 1444 1445 cur_tx->ste_ptr->ste_next = 0; 1446 1447 if(sc->ste_tx_prev_idx < 0){ 1448 cur_tx->ste_ptr->ste_ctl = STE_TXCTL_DMAINTR | 1; 1449 /* Load address of the TX list */ 1450 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL); 1451 ste_wait(sc); 1452 1453 CSR_WRITE_4(sc, STE_TX_DMALIST_PTR, 1454 vtophys(&sc->ste_ldata->ste_tx_list[0])); 1455 1456 /* Set TX polling interval to start TX engine */ 1457 CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 64); 1458 1459 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 1460 ste_wait(sc); 1461 }else{ 1462 cur_tx->ste_ptr->ste_ctl = STE_TXCTL_DMAINTR | 1; 1463 sc->ste_cdata.ste_tx_chain[ 1464 sc->ste_tx_prev_idx].ste_ptr->ste_next 1465 = cur_tx->ste_phys; 1466 } 1467 1468 sc->ste_tx_prev_idx=idx; 1469 1470 BPF_MTAP(ifp, cur_tx->ste_mbuf); 1471 1472 STE_INC(idx, STE_TX_LIST_CNT); 1473 sc->ste_cdata.ste_tx_cnt++; 1474 ifp->if_timer = 5; 1475 sc->ste_cdata.ste_tx_prod = idx; 1476 } 1477 } 1478 1479 static void 1480 ste_watchdog(struct ifnet *ifp) 1481 { 1482 struct ste_softc *sc; 1483 1484 sc = ifp->if_softc; 1485 1486 ifp->if_oerrors++; 1487 if_printf(ifp, "watchdog timeout\n"); 1488 1489 ste_txeoc(sc); 1490 ste_txeof(sc); 1491 ste_rxeof(sc); 1492 ste_reset(sc); 1493 ste_init(sc); 1494 1495 if (!ifq_is_empty(&ifp->if_snd)) 1496 if_devstart(ifp); 1497 } 1498 1499 static void 1500 ste_shutdown(device_t dev) 1501 { 1502 struct ste_softc *sc; 1503 1504 sc = device_get_softc(dev); 1505 1506 ste_stop(sc); 1507 1508 return; 1509 } 1510