1 /* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: src/sys/pci/if_ste.c,v 1.14.2.9 2003/02/05 22:03:57 mbr Exp $ 33 * $DragonFly: src/sys/dev/netif/ste/if_ste.c,v 1.14 2005/01/23 20:23:22 joerg Exp $ 34 * 35 * $FreeBSD: src/sys/pci/if_ste.c,v 1.14.2.9 2003/02/05 22:03:57 mbr Exp $ 36 */ 37 38 #include <sys/param.h> 39 #include <sys/systm.h> 40 #include <sys/sockio.h> 41 #include <sys/mbuf.h> 42 #include <sys/malloc.h> 43 #include <sys/kernel.h> 44 #include <sys/socket.h> 45 46 #include <net/if.h> 47 #include <net/if_arp.h> 48 #include <net/ethernet.h> 49 #include <net/if_dl.h> 50 #include <net/if_media.h> 51 #include <net/vlan/if_vlan_var.h> 52 53 #include <net/bpf.h> 54 55 #include <vm/vm.h> /* for vtophys */ 56 #include <vm/pmap.h> /* for vtophys */ 57 #include <machine/clock.h> /* for DELAY */ 58 #include <machine/bus_memio.h> 59 #include <machine/bus_pio.h> 60 #include <machine/bus.h> 61 #include <machine/resource.h> 62 #include <sys/bus.h> 63 #include <sys/rman.h> 64 65 #include "../mii_layer/mii.h" 66 #include "../mii_layer/miivar.h" 67 68 #include <bus/pci/pcireg.h> 69 #include <bus/pci/pcivar.h> 70 71 /* "controller miibus0" required. See GENERIC if you get errors here. */ 72 #include "miibus_if.h" 73 74 #define STE_USEIOSPACE 75 76 #include "if_stereg.h" 77 78 /* 79 * Various supported device vendors/types and their names. 80 */ 81 static struct ste_type ste_devs[] = { 82 { ST_VENDORID, ST_DEVICEID_ST201, "Sundance ST201 10/100BaseTX" }, 83 { DL_VENDORID, DL_DEVICEID_550TX, "D-Link DFE-550TX 10/100BaseTX" }, 84 { 0, 0, NULL } 85 }; 86 87 static int ste_probe (device_t); 88 static int ste_attach (device_t); 89 static int ste_detach (device_t); 90 static void ste_init (void *); 91 static void ste_intr (void *); 92 static void ste_rxeof (struct ste_softc *); 93 static void ste_txeoc (struct ste_softc *); 94 static void ste_txeof (struct ste_softc *); 95 static void ste_stats_update (void *); 96 static void ste_stop (struct ste_softc *); 97 static void ste_reset (struct ste_softc *); 98 static int ste_ioctl (struct ifnet *, u_long, caddr_t, 99 struct ucred *); 100 static int ste_encap (struct ste_softc *, struct ste_chain *, 101 struct mbuf *); 102 static void ste_start (struct ifnet *); 103 static void ste_watchdog (struct ifnet *); 104 static void ste_shutdown (device_t); 105 static int ste_newbuf (struct ste_softc *, 106 struct ste_chain_onefrag *, 107 struct mbuf *); 108 static int ste_ifmedia_upd (struct ifnet *); 109 static void ste_ifmedia_sts (struct ifnet *, struct ifmediareq *); 110 111 static void ste_mii_sync (struct ste_softc *); 112 static void ste_mii_send (struct ste_softc *, u_int32_t, int); 113 static int ste_mii_readreg (struct ste_softc *, 114 struct ste_mii_frame *); 115 static int ste_mii_writereg (struct ste_softc *, 116 struct ste_mii_frame *); 117 static int ste_miibus_readreg (device_t, int, int); 118 static int ste_miibus_writereg (device_t, int, int, int); 119 static void ste_miibus_statchg (device_t); 120 121 static int ste_eeprom_wait (struct ste_softc *); 122 static int ste_read_eeprom (struct ste_softc *, caddr_t, int, 123 int, int); 124 static void ste_wait (struct ste_softc *); 125 static u_int8_t ste_calchash (caddr_t); 126 static void ste_setmulti (struct ste_softc *); 127 static int ste_init_rx_list (struct ste_softc *); 128 static void ste_init_tx_list (struct ste_softc *); 129 130 #ifdef STE_USEIOSPACE 131 #define STE_RES SYS_RES_IOPORT 132 #define STE_RID STE_PCI_LOIO 133 #else 134 #define STE_RES SYS_RES_MEMORY 135 #define STE_RID STE_PCI_LOMEM 136 #endif 137 138 static device_method_t ste_methods[] = { 139 /* Device interface */ 140 DEVMETHOD(device_probe, ste_probe), 141 DEVMETHOD(device_attach, ste_attach), 142 DEVMETHOD(device_detach, ste_detach), 143 DEVMETHOD(device_shutdown, ste_shutdown), 144 145 /* bus interface */ 146 DEVMETHOD(bus_print_child, bus_generic_print_child), 147 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 148 149 /* MII interface */ 150 DEVMETHOD(miibus_readreg, ste_miibus_readreg), 151 DEVMETHOD(miibus_writereg, ste_miibus_writereg), 152 DEVMETHOD(miibus_statchg, ste_miibus_statchg), 153 154 { 0, 0 } 155 }; 156 157 static driver_t ste_driver = { 158 "ste", 159 ste_methods, 160 sizeof(struct ste_softc) 161 }; 162 163 static devclass_t ste_devclass; 164 165 DECLARE_DUMMY_MODULE(if_ste); 166 DRIVER_MODULE(if_ste, pci, ste_driver, ste_devclass, 0, 0); 167 DRIVER_MODULE(miibus, ste, miibus_driver, miibus_devclass, 0, 0); 168 169 #define STE_SETBIT4(sc, reg, x) \ 170 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | x) 171 172 #define STE_CLRBIT4(sc, reg, x) \ 173 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~x) 174 175 #define STE_SETBIT2(sc, reg, x) \ 176 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) | x) 177 178 #define STE_CLRBIT2(sc, reg, x) \ 179 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) & ~x) 180 181 #define STE_SETBIT1(sc, reg, x) \ 182 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | x) 183 184 #define STE_CLRBIT1(sc, reg, x) \ 185 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~x) 186 187 188 #define MII_SET(x) STE_SETBIT1(sc, STE_PHYCTL, x) 189 #define MII_CLR(x) STE_CLRBIT1(sc, STE_PHYCTL, x) 190 191 /* 192 * Sync the PHYs by setting data bit and strobing the clock 32 times. 193 */ 194 static void ste_mii_sync(sc) 195 struct ste_softc *sc; 196 { 197 int i; 198 199 MII_SET(STE_PHYCTL_MDIR|STE_PHYCTL_MDATA); 200 201 for (i = 0; i < 32; i++) { 202 MII_SET(STE_PHYCTL_MCLK); 203 DELAY(1); 204 MII_CLR(STE_PHYCTL_MCLK); 205 DELAY(1); 206 } 207 208 return; 209 } 210 211 /* 212 * Clock a series of bits through the MII. 213 */ 214 static void ste_mii_send(sc, bits, cnt) 215 struct ste_softc *sc; 216 u_int32_t bits; 217 int cnt; 218 { 219 int i; 220 221 MII_CLR(STE_PHYCTL_MCLK); 222 223 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 224 if (bits & i) { 225 MII_SET(STE_PHYCTL_MDATA); 226 } else { 227 MII_CLR(STE_PHYCTL_MDATA); 228 } 229 DELAY(1); 230 MII_CLR(STE_PHYCTL_MCLK); 231 DELAY(1); 232 MII_SET(STE_PHYCTL_MCLK); 233 } 234 } 235 236 /* 237 * Read an PHY register through the MII. 238 */ 239 static int ste_mii_readreg(sc, frame) 240 struct ste_softc *sc; 241 struct ste_mii_frame *frame; 242 243 { 244 int i, ack, s; 245 246 s = splimp(); 247 248 /* 249 * Set up frame for RX. 250 */ 251 frame->mii_stdelim = STE_MII_STARTDELIM; 252 frame->mii_opcode = STE_MII_READOP; 253 frame->mii_turnaround = 0; 254 frame->mii_data = 0; 255 256 CSR_WRITE_2(sc, STE_PHYCTL, 0); 257 /* 258 * Turn on data xmit. 259 */ 260 MII_SET(STE_PHYCTL_MDIR); 261 262 ste_mii_sync(sc); 263 264 /* 265 * Send command/address info. 266 */ 267 ste_mii_send(sc, frame->mii_stdelim, 2); 268 ste_mii_send(sc, frame->mii_opcode, 2); 269 ste_mii_send(sc, frame->mii_phyaddr, 5); 270 ste_mii_send(sc, frame->mii_regaddr, 5); 271 272 /* Turn off xmit. */ 273 MII_CLR(STE_PHYCTL_MDIR); 274 275 /* Idle bit */ 276 MII_CLR((STE_PHYCTL_MCLK|STE_PHYCTL_MDATA)); 277 DELAY(1); 278 MII_SET(STE_PHYCTL_MCLK); 279 DELAY(1); 280 281 /* Check for ack */ 282 MII_CLR(STE_PHYCTL_MCLK); 283 DELAY(1); 284 ack = CSR_READ_2(sc, STE_PHYCTL) & STE_PHYCTL_MDATA; 285 MII_SET(STE_PHYCTL_MCLK); 286 DELAY(1); 287 288 /* 289 * Now try reading data bits. If the ack failed, we still 290 * need to clock through 16 cycles to keep the PHY(s) in sync. 291 */ 292 if (ack) { 293 for(i = 0; i < 16; i++) { 294 MII_CLR(STE_PHYCTL_MCLK); 295 DELAY(1); 296 MII_SET(STE_PHYCTL_MCLK); 297 DELAY(1); 298 } 299 goto fail; 300 } 301 302 for (i = 0x8000; i; i >>= 1) { 303 MII_CLR(STE_PHYCTL_MCLK); 304 DELAY(1); 305 if (!ack) { 306 if (CSR_READ_2(sc, STE_PHYCTL) & STE_PHYCTL_MDATA) 307 frame->mii_data |= i; 308 DELAY(1); 309 } 310 MII_SET(STE_PHYCTL_MCLK); 311 DELAY(1); 312 } 313 314 fail: 315 316 MII_CLR(STE_PHYCTL_MCLK); 317 DELAY(1); 318 MII_SET(STE_PHYCTL_MCLK); 319 DELAY(1); 320 321 splx(s); 322 323 if (ack) 324 return(1); 325 return(0); 326 } 327 328 /* 329 * Write to a PHY register through the MII. 330 */ 331 static int ste_mii_writereg(sc, frame) 332 struct ste_softc *sc; 333 struct ste_mii_frame *frame; 334 335 { 336 int s; 337 338 s = splimp(); 339 /* 340 * Set up frame for TX. 341 */ 342 343 frame->mii_stdelim = STE_MII_STARTDELIM; 344 frame->mii_opcode = STE_MII_WRITEOP; 345 frame->mii_turnaround = STE_MII_TURNAROUND; 346 347 /* 348 * Turn on data output. 349 */ 350 MII_SET(STE_PHYCTL_MDIR); 351 352 ste_mii_sync(sc); 353 354 ste_mii_send(sc, frame->mii_stdelim, 2); 355 ste_mii_send(sc, frame->mii_opcode, 2); 356 ste_mii_send(sc, frame->mii_phyaddr, 5); 357 ste_mii_send(sc, frame->mii_regaddr, 5); 358 ste_mii_send(sc, frame->mii_turnaround, 2); 359 ste_mii_send(sc, frame->mii_data, 16); 360 361 /* Idle bit. */ 362 MII_SET(STE_PHYCTL_MCLK); 363 DELAY(1); 364 MII_CLR(STE_PHYCTL_MCLK); 365 DELAY(1); 366 367 /* 368 * Turn off xmit. 369 */ 370 MII_CLR(STE_PHYCTL_MDIR); 371 372 splx(s); 373 374 return(0); 375 } 376 377 static int ste_miibus_readreg(dev, phy, reg) 378 device_t dev; 379 int phy, reg; 380 { 381 struct ste_softc *sc; 382 struct ste_mii_frame frame; 383 384 sc = device_get_softc(dev); 385 386 if ( sc->ste_one_phy && phy != 0 ) 387 return (0); 388 389 bzero((char *)&frame, sizeof(frame)); 390 391 frame.mii_phyaddr = phy; 392 frame.mii_regaddr = reg; 393 ste_mii_readreg(sc, &frame); 394 395 return(frame.mii_data); 396 } 397 398 static int ste_miibus_writereg(dev, phy, reg, data) 399 device_t dev; 400 int phy, reg, data; 401 { 402 struct ste_softc *sc; 403 struct ste_mii_frame frame; 404 405 sc = device_get_softc(dev); 406 bzero((char *)&frame, sizeof(frame)); 407 408 frame.mii_phyaddr = phy; 409 frame.mii_regaddr = reg; 410 frame.mii_data = data; 411 412 ste_mii_writereg(sc, &frame); 413 414 return(0); 415 } 416 417 static void ste_miibus_statchg(dev) 418 device_t dev; 419 { 420 struct ste_softc *sc; 421 struct mii_data *mii; 422 int i; 423 424 sc = device_get_softc(dev); 425 mii = device_get_softc(sc->ste_miibus); 426 427 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 428 STE_SETBIT2(sc, STE_MACCTL0, STE_MACCTL0_FULLDUPLEX); 429 } else { 430 STE_CLRBIT2(sc, STE_MACCTL0, STE_MACCTL0_FULLDUPLEX); 431 } 432 433 STE_SETBIT4(sc, STE_ASICCTL,STE_ASICCTL_RX_RESET | 434 STE_ASICCTL_TX_RESET); 435 for (i = 0; i < STE_TIMEOUT; i++) { 436 if (!(CSR_READ_4(sc, STE_ASICCTL) & STE_ASICCTL_RESET_BUSY)) 437 break; 438 } 439 if (i == STE_TIMEOUT) 440 printf("ste%d: rx reset never completed\n", sc->ste_unit); 441 442 return; 443 } 444 445 static int ste_ifmedia_upd(ifp) 446 struct ifnet *ifp; 447 { 448 struct ste_softc *sc; 449 struct mii_data *mii; 450 451 sc = ifp->if_softc; 452 mii = device_get_softc(sc->ste_miibus); 453 sc->ste_link = 0; 454 if (mii->mii_instance) { 455 struct mii_softc *miisc; 456 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 457 miisc = LIST_NEXT(miisc, mii_list)) 458 mii_phy_reset(miisc); 459 } 460 mii_mediachg(mii); 461 462 return(0); 463 } 464 465 static void ste_ifmedia_sts(ifp, ifmr) 466 struct ifnet *ifp; 467 struct ifmediareq *ifmr; 468 { 469 struct ste_softc *sc; 470 struct mii_data *mii; 471 472 sc = ifp->if_softc; 473 mii = device_get_softc(sc->ste_miibus); 474 475 mii_pollstat(mii); 476 ifmr->ifm_active = mii->mii_media_active; 477 ifmr->ifm_status = mii->mii_media_status; 478 479 return; 480 } 481 482 static void ste_wait(sc) 483 struct ste_softc *sc; 484 { 485 int i; 486 487 for (i = 0; i < STE_TIMEOUT; i++) { 488 if (!(CSR_READ_4(sc, STE_DMACTL) & STE_DMACTL_DMA_HALTINPROG)) 489 break; 490 } 491 492 if (i == STE_TIMEOUT) 493 printf("ste%d: command never completed!\n", sc->ste_unit); 494 495 return; 496 } 497 498 /* 499 * The EEPROM is slow: give it time to come ready after issuing 500 * it a command. 501 */ 502 static int ste_eeprom_wait(sc) 503 struct ste_softc *sc; 504 { 505 int i; 506 507 DELAY(1000); 508 509 for (i = 0; i < 100; i++) { 510 if (CSR_READ_2(sc, STE_EEPROM_CTL) & STE_EECTL_BUSY) 511 DELAY(1000); 512 else 513 break; 514 } 515 516 if (i == 100) { 517 printf("ste%d: eeprom failed to come ready\n", sc->ste_unit); 518 return(1); 519 } 520 521 return(0); 522 } 523 524 /* 525 * Read a sequence of words from the EEPROM. Note that ethernet address 526 * data is stored in the EEPROM in network byte order. 527 */ 528 static int ste_read_eeprom(sc, dest, off, cnt, swap) 529 struct ste_softc *sc; 530 caddr_t dest; 531 int off; 532 int cnt; 533 int swap; 534 { 535 int err = 0, i; 536 u_int16_t word = 0, *ptr; 537 538 if (ste_eeprom_wait(sc)) 539 return(1); 540 541 for (i = 0; i < cnt; i++) { 542 CSR_WRITE_2(sc, STE_EEPROM_CTL, STE_EEOPCODE_READ | (off + i)); 543 err = ste_eeprom_wait(sc); 544 if (err) 545 break; 546 word = CSR_READ_2(sc, STE_EEPROM_DATA); 547 ptr = (u_int16_t *)(dest + (i * 2)); 548 if (swap) 549 *ptr = ntohs(word); 550 else 551 *ptr = word; 552 } 553 554 return(err ? 1 : 0); 555 } 556 557 static u_int8_t ste_calchash(addr) 558 caddr_t addr; 559 { 560 561 u_int32_t crc, carry; 562 int i, j; 563 u_int8_t c; 564 565 /* Compute CRC for the address value. */ 566 crc = 0xFFFFFFFF; /* initial value */ 567 568 for (i = 0; i < 6; i++) { 569 c = *(addr + i); 570 for (j = 0; j < 8; j++) { 571 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 572 crc <<= 1; 573 c >>= 1; 574 if (carry) 575 crc = (crc ^ 0x04c11db6) | carry; 576 } 577 } 578 579 /* return the filter bit position */ 580 return(crc & 0x0000003F); 581 } 582 583 static void ste_setmulti(sc) 584 struct ste_softc *sc; 585 { 586 struct ifnet *ifp; 587 int h = 0; 588 u_int32_t hashes[2] = { 0, 0 }; 589 struct ifmultiaddr *ifma; 590 591 ifp = &sc->arpcom.ac_if; 592 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 593 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_ALLMULTI); 594 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_MULTIHASH); 595 return; 596 } 597 598 /* first, zot all the existing hash bits */ 599 CSR_WRITE_2(sc, STE_MAR0, 0); 600 CSR_WRITE_2(sc, STE_MAR1, 0); 601 CSR_WRITE_2(sc, STE_MAR2, 0); 602 CSR_WRITE_2(sc, STE_MAR3, 0); 603 604 /* now program new ones */ 605 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 606 ifma = ifma->ifma_link.le_next) { 607 if (ifma->ifma_addr->sa_family != AF_LINK) 608 continue; 609 h = ste_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 610 if (h < 32) 611 hashes[0] |= (1 << h); 612 else 613 hashes[1] |= (1 << (h - 32)); 614 } 615 616 CSR_WRITE_2(sc, STE_MAR0, hashes[0] & 0xFFFF); 617 CSR_WRITE_2(sc, STE_MAR1, (hashes[0] >> 16) & 0xFFFF); 618 CSR_WRITE_2(sc, STE_MAR2, hashes[1] & 0xFFFF); 619 CSR_WRITE_2(sc, STE_MAR3, (hashes[1] >> 16) & 0xFFFF); 620 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_ALLMULTI); 621 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_MULTIHASH); 622 623 return; 624 } 625 626 static void ste_intr(xsc) 627 void *xsc; 628 { 629 struct ste_softc *sc; 630 struct ifnet *ifp; 631 u_int16_t status; 632 633 sc = xsc; 634 ifp = &sc->arpcom.ac_if; 635 636 /* See if this is really our interrupt. */ 637 if (!(CSR_READ_2(sc, STE_ISR) & STE_ISR_INTLATCH)) 638 return; 639 640 for (;;) { 641 status = CSR_READ_2(sc, STE_ISR_ACK); 642 643 if (!(status & STE_INTRS)) 644 break; 645 646 if (status & STE_ISR_RX_DMADONE) 647 ste_rxeof(sc); 648 649 if (status & STE_ISR_TX_DMADONE) 650 ste_txeof(sc); 651 652 if (status & STE_ISR_TX_DONE) 653 ste_txeoc(sc); 654 655 if (status & STE_ISR_STATS_OFLOW) { 656 callout_stop(&sc->ste_stat_timer); 657 ste_stats_update(sc); 658 } 659 660 if (status & STE_ISR_LINKEVENT) 661 mii_pollstat(device_get_softc(sc->ste_miibus)); 662 663 if (status & STE_ISR_HOSTERR) { 664 ste_reset(sc); 665 ste_init(sc); 666 } 667 } 668 669 /* Re-enable interrupts */ 670 CSR_WRITE_2(sc, STE_IMR, STE_INTRS); 671 672 if (ifp->if_snd.ifq_head != NULL) 673 ste_start(ifp); 674 675 return; 676 } 677 678 /* 679 * A frame has been uploaded: pass the resulting mbuf chain up to 680 * the higher level protocols. 681 */ 682 static void ste_rxeof(sc) 683 struct ste_softc *sc; 684 { 685 struct mbuf *m; 686 struct ifnet *ifp; 687 struct ste_chain_onefrag *cur_rx; 688 int total_len = 0, count=0; 689 u_int32_t rxstat; 690 691 ifp = &sc->arpcom.ac_if; 692 693 while((rxstat = sc->ste_cdata.ste_rx_head->ste_ptr->ste_status) 694 & STE_RXSTAT_DMADONE) { 695 if ((STE_RX_LIST_CNT - count) < 3) { 696 break; 697 } 698 699 cur_rx = sc->ste_cdata.ste_rx_head; 700 sc->ste_cdata.ste_rx_head = cur_rx->ste_next; 701 702 /* 703 * If an error occurs, update stats, clear the 704 * status word and leave the mbuf cluster in place: 705 * it should simply get re-used next time this descriptor 706 * comes up in the ring. 707 */ 708 if (rxstat & STE_RXSTAT_FRAME_ERR) { 709 ifp->if_ierrors++; 710 cur_rx->ste_ptr->ste_status = 0; 711 continue; 712 } 713 714 /* 715 * If there error bit was not set, the upload complete 716 * bit should be set which means we have a valid packet. 717 * If not, something truly strange has happened. 718 */ 719 if (!(rxstat & STE_RXSTAT_DMADONE)) { 720 printf("ste%d: bad receive status -- packet dropped", 721 sc->ste_unit); 722 ifp->if_ierrors++; 723 cur_rx->ste_ptr->ste_status = 0; 724 continue; 725 } 726 727 /* No errors; receive the packet. */ 728 m = cur_rx->ste_mbuf; 729 total_len = cur_rx->ste_ptr->ste_status & STE_RXSTAT_FRAMELEN; 730 731 /* 732 * Try to conjure up a new mbuf cluster. If that 733 * fails, it means we have an out of memory condition and 734 * should leave the buffer in place and continue. This will 735 * result in a lost packet, but there's little else we 736 * can do in this situation. 737 */ 738 if (ste_newbuf(sc, cur_rx, NULL) == ENOBUFS) { 739 ifp->if_ierrors++; 740 cur_rx->ste_ptr->ste_status = 0; 741 continue; 742 } 743 744 ifp->if_ipackets++; 745 m->m_pkthdr.rcvif = ifp; 746 m->m_pkthdr.len = m->m_len = total_len; 747 748 (*ifp->if_input)(ifp, m); 749 750 cur_rx->ste_ptr->ste_status = 0; 751 count++; 752 } 753 754 return; 755 } 756 757 static void ste_txeoc(sc) 758 struct ste_softc *sc; 759 { 760 u_int8_t txstat; 761 struct ifnet *ifp; 762 763 ifp = &sc->arpcom.ac_if; 764 765 while ((txstat = CSR_READ_1(sc, STE_TX_STATUS)) & 766 STE_TXSTATUS_TXDONE) { 767 if (txstat & STE_TXSTATUS_UNDERRUN || 768 txstat & STE_TXSTATUS_EXCESSCOLLS || 769 txstat & STE_TXSTATUS_RECLAIMERR) { 770 ifp->if_oerrors++; 771 printf("ste%d: transmission error: %x\n", 772 sc->ste_unit, txstat); 773 774 ste_reset(sc); 775 ste_init(sc); 776 777 if (txstat & STE_TXSTATUS_UNDERRUN && 778 sc->ste_tx_thresh < STE_PACKET_SIZE) { 779 sc->ste_tx_thresh += STE_MIN_FRAMELEN; 780 printf("ste%d: tx underrun, increasing tx" 781 " start threshold to %d bytes\n", 782 sc->ste_unit, sc->ste_tx_thresh); 783 } 784 CSR_WRITE_2(sc, STE_TX_STARTTHRESH, sc->ste_tx_thresh); 785 CSR_WRITE_2(sc, STE_TX_RECLAIM_THRESH, 786 (STE_PACKET_SIZE >> 4)); 787 } 788 ste_init(sc); 789 CSR_WRITE_2(sc, STE_TX_STATUS, txstat); 790 } 791 792 return; 793 } 794 795 static void ste_txeof(sc) 796 struct ste_softc *sc; 797 { 798 struct ste_chain *cur_tx = NULL; 799 struct ifnet *ifp; 800 int idx; 801 802 ifp = &sc->arpcom.ac_if; 803 804 idx = sc->ste_cdata.ste_tx_cons; 805 while(idx != sc->ste_cdata.ste_tx_prod) { 806 cur_tx = &sc->ste_cdata.ste_tx_chain[idx]; 807 808 if (!(cur_tx->ste_ptr->ste_ctl & STE_TXCTL_DMADONE)) 809 break; 810 811 if (cur_tx->ste_mbuf != NULL) { 812 m_freem(cur_tx->ste_mbuf); 813 cur_tx->ste_mbuf = NULL; 814 } 815 816 ifp->if_opackets++; 817 818 sc->ste_cdata.ste_tx_cnt--; 819 STE_INC(idx, STE_TX_LIST_CNT); 820 ifp->if_timer = 0; 821 } 822 823 sc->ste_cdata.ste_tx_cons = idx; 824 825 if (cur_tx != NULL) 826 ifp->if_flags &= ~IFF_OACTIVE; 827 828 return; 829 } 830 831 static void ste_stats_update(xsc) 832 void *xsc; 833 { 834 struct ste_softc *sc; 835 struct ifnet *ifp; 836 struct mii_data *mii; 837 int s; 838 839 s = splimp(); 840 841 sc = xsc; 842 ifp = &sc->arpcom.ac_if; 843 mii = device_get_softc(sc->ste_miibus); 844 845 ifp->if_collisions += CSR_READ_1(sc, STE_LATE_COLLS) 846 + CSR_READ_1(sc, STE_MULTI_COLLS) 847 + CSR_READ_1(sc, STE_SINGLE_COLLS); 848 849 if (!sc->ste_link) { 850 mii_pollstat(mii); 851 if (mii->mii_media_status & IFM_ACTIVE && 852 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 853 sc->ste_link++; 854 /* 855 * we don't get a call-back on re-init so do it 856 * otherwise we get stuck in the wrong link state 857 */ 858 ste_miibus_statchg(sc->ste_dev); 859 if (ifp->if_snd.ifq_head != NULL) 860 ste_start(ifp); 861 } 862 } 863 864 callout_reset(&sc->ste_stat_timer, hz, ste_stats_update, sc); 865 splx(s); 866 867 return; 868 } 869 870 871 /* 872 * Probe for a Sundance ST201 chip. Check the PCI vendor and device 873 * IDs against our list and return a device name if we find a match. 874 */ 875 static int ste_probe(dev) 876 device_t dev; 877 { 878 struct ste_type *t; 879 880 t = ste_devs; 881 882 while(t->ste_name != NULL) { 883 if ((pci_get_vendor(dev) == t->ste_vid) && 884 (pci_get_device(dev) == t->ste_did)) { 885 device_set_desc(dev, t->ste_name); 886 return(0); 887 } 888 t++; 889 } 890 891 return(ENXIO); 892 } 893 894 /* 895 * Attach the interface. Allocate softc structures, do ifmedia 896 * setup and ethernet/BPF attach. 897 */ 898 static int ste_attach(dev) 899 device_t dev; 900 { 901 int s; 902 u_int32_t command; 903 struct ste_softc *sc; 904 struct ifnet *ifp; 905 int unit, error = 0, rid; 906 907 s = splimp(); 908 909 sc = device_get_softc(dev); 910 unit = device_get_unit(dev); 911 bzero(sc, sizeof(struct ste_softc)); 912 sc->ste_dev = dev; 913 914 /* 915 * Only use one PHY since this chip reports multiple 916 * Note on the DFE-550 the PHY is at 1 on the DFE-580 917 * it is at 0 & 1. It is rev 0x12. 918 */ 919 if (pci_get_vendor(dev) == DL_VENDORID && 920 pci_get_device(dev) == DL_DEVICEID_550TX && 921 pci_get_revid(dev) == 0x12 ) 922 sc->ste_one_phy = 1; 923 924 /* 925 * Handle power management nonsense. 926 */ 927 command = pci_read_config(dev, STE_PCI_CAPID, 4) & 0x000000FF; 928 if (command == 0x01) { 929 930 command = pci_read_config(dev, STE_PCI_PWRMGMTCTRL, 4); 931 if (command & STE_PSTATE_MASK) { 932 u_int32_t iobase, membase, irq; 933 934 /* Save important PCI config data. */ 935 iobase = pci_read_config(dev, STE_PCI_LOIO, 4); 936 membase = pci_read_config(dev, STE_PCI_LOMEM, 4); 937 irq = pci_read_config(dev, STE_PCI_INTLINE, 4); 938 939 /* Reset the power state. */ 940 printf("ste%d: chip is in D%d power mode " 941 "-- setting to D0\n", unit, command & STE_PSTATE_MASK); 942 command &= 0xFFFFFFFC; 943 pci_write_config(dev, STE_PCI_PWRMGMTCTRL, command, 4); 944 945 /* Restore PCI config data. */ 946 pci_write_config(dev, STE_PCI_LOIO, iobase, 4); 947 pci_write_config(dev, STE_PCI_LOMEM, membase, 4); 948 pci_write_config(dev, STE_PCI_INTLINE, irq, 4); 949 } 950 } 951 952 /* 953 * Map control/status registers. 954 */ 955 command = pci_read_config(dev, PCIR_COMMAND, 4); 956 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 957 pci_write_config(dev, PCIR_COMMAND, command, 4); 958 command = pci_read_config(dev, PCIR_COMMAND, 4); 959 960 #ifdef STE_USEIOSPACE 961 if (!(command & PCIM_CMD_PORTEN)) { 962 printf("ste%d: failed to enable I/O ports!\n", unit); 963 error = ENXIO; 964 goto fail; 965 } 966 #else 967 if (!(command & PCIM_CMD_MEMEN)) { 968 printf("ste%d: failed to enable memory mapping!\n", unit); 969 error = ENXIO; 970 goto fail; 971 } 972 #endif 973 974 rid = STE_RID; 975 sc->ste_res = bus_alloc_resource(dev, STE_RES, &rid, 976 0, ~0, 1, RF_ACTIVE); 977 978 if (sc->ste_res == NULL) { 979 printf ("ste%d: couldn't map ports/memory\n", unit); 980 error = ENXIO; 981 goto fail; 982 } 983 984 sc->ste_btag = rman_get_bustag(sc->ste_res); 985 sc->ste_bhandle = rman_get_bushandle(sc->ste_res); 986 987 rid = 0; 988 sc->ste_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 989 RF_SHAREABLE | RF_ACTIVE); 990 991 if (sc->ste_irq == NULL) { 992 printf("ste%d: couldn't map interrupt\n", unit); 993 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res); 994 error = ENXIO; 995 goto fail; 996 } 997 998 error = bus_setup_intr(dev, sc->ste_irq, INTR_TYPE_NET, 999 ste_intr, sc, &sc->ste_intrhand); 1000 1001 if (error) { 1002 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq); 1003 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res); 1004 printf("ste%d: couldn't set up irq\n", unit); 1005 goto fail; 1006 } 1007 1008 callout_init(&sc->ste_stat_timer); 1009 1010 /* Reset the adapter. */ 1011 ste_reset(sc); 1012 1013 /* 1014 * Get station address from the EEPROM. 1015 */ 1016 if (ste_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr, 1017 STE_EEADDR_NODE0, 3, 0)) { 1018 printf("ste%d: failed to read station address\n", unit); 1019 bus_teardown_intr(dev, sc->ste_irq, sc->ste_intrhand); 1020 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq); 1021 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res); 1022 error = ENXIO;; 1023 goto fail; 1024 } 1025 1026 sc->ste_unit = unit; 1027 1028 /* Allocate the descriptor queues. */ 1029 sc->ste_ldata = contigmalloc(sizeof(struct ste_list_data), M_DEVBUF, 1030 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 1031 1032 if (sc->ste_ldata == NULL) { 1033 printf("ste%d: no memory for list buffers!\n", unit); 1034 bus_teardown_intr(dev, sc->ste_irq, sc->ste_intrhand); 1035 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq); 1036 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res); 1037 error = ENXIO; 1038 goto fail; 1039 } 1040 1041 bzero(sc->ste_ldata, sizeof(struct ste_list_data)); 1042 1043 /* Do MII setup. */ 1044 if (mii_phy_probe(dev, &sc->ste_miibus, 1045 ste_ifmedia_upd, ste_ifmedia_sts)) { 1046 printf("ste%d: MII without any phy!\n", sc->ste_unit); 1047 bus_teardown_intr(dev, sc->ste_irq, sc->ste_intrhand); 1048 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq); 1049 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res); 1050 contigfree(sc->ste_ldata, 1051 sizeof(struct ste_list_data), M_DEVBUF); 1052 error = ENXIO; 1053 goto fail; 1054 } 1055 1056 ifp = &sc->arpcom.ac_if; 1057 ifp->if_softc = sc; 1058 if_initname(ifp, "ste", unit); 1059 ifp->if_mtu = ETHERMTU; 1060 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1061 ifp->if_ioctl = ste_ioctl; 1062 ifp->if_start = ste_start; 1063 ifp->if_watchdog = ste_watchdog; 1064 ifp->if_init = ste_init; 1065 ifp->if_baudrate = 10000000; 1066 ifp->if_snd.ifq_maxlen = STE_TX_LIST_CNT - 1; 1067 1068 sc->ste_tx_thresh = STE_TXSTART_THRESH; 1069 1070 /* 1071 * Call MI attach routine. 1072 */ 1073 ether_ifattach(ifp, sc->arpcom.ac_enaddr); 1074 1075 /* 1076 * Tell the upper layer(s) we support long frames. 1077 */ 1078 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1079 1080 fail: 1081 splx(s); 1082 return(error); 1083 } 1084 1085 static int ste_detach(dev) 1086 device_t dev; 1087 { 1088 struct ste_softc *sc; 1089 struct ifnet *ifp; 1090 int s; 1091 1092 s = splimp(); 1093 1094 sc = device_get_softc(dev); 1095 ifp = &sc->arpcom.ac_if; 1096 1097 ste_stop(sc); 1098 ether_ifdetach(ifp); 1099 1100 bus_generic_detach(dev); 1101 device_delete_child(dev, sc->ste_miibus); 1102 1103 bus_teardown_intr(dev, sc->ste_irq, sc->ste_intrhand); 1104 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq); 1105 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res); 1106 1107 contigfree(sc->ste_ldata, sizeof(struct ste_list_data), M_DEVBUF); 1108 1109 splx(s); 1110 1111 return(0); 1112 } 1113 1114 static int ste_newbuf(sc, c, m) 1115 struct ste_softc *sc; 1116 struct ste_chain_onefrag *c; 1117 struct mbuf *m; 1118 { 1119 struct mbuf *m_new = NULL; 1120 1121 if (m == NULL) { 1122 MGETHDR(m_new, MB_DONTWAIT, MT_DATA); 1123 if (m_new == NULL) 1124 return(ENOBUFS); 1125 MCLGET(m_new, MB_DONTWAIT); 1126 if (!(m_new->m_flags & M_EXT)) { 1127 m_freem(m_new); 1128 return(ENOBUFS); 1129 } 1130 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1131 } else { 1132 m_new = m; 1133 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1134 m_new->m_data = m_new->m_ext.ext_buf; 1135 } 1136 1137 m_adj(m_new, ETHER_ALIGN); 1138 1139 c->ste_mbuf = m_new; 1140 c->ste_ptr->ste_status = 0; 1141 c->ste_ptr->ste_frag.ste_addr = vtophys(mtod(m_new, caddr_t)); 1142 c->ste_ptr->ste_frag.ste_len = (1536 + EVL_ENCAPLEN) | STE_FRAG_LAST; 1143 1144 return(0); 1145 } 1146 1147 static int ste_init_rx_list(sc) 1148 struct ste_softc *sc; 1149 { 1150 struct ste_chain_data *cd; 1151 struct ste_list_data *ld; 1152 int i; 1153 1154 cd = &sc->ste_cdata; 1155 ld = sc->ste_ldata; 1156 1157 for (i = 0; i < STE_RX_LIST_CNT; i++) { 1158 cd->ste_rx_chain[i].ste_ptr = &ld->ste_rx_list[i]; 1159 if (ste_newbuf(sc, &cd->ste_rx_chain[i], NULL) == ENOBUFS) 1160 return(ENOBUFS); 1161 if (i == (STE_RX_LIST_CNT - 1)) { 1162 cd->ste_rx_chain[i].ste_next = 1163 &cd->ste_rx_chain[0]; 1164 ld->ste_rx_list[i].ste_next = 1165 vtophys(&ld->ste_rx_list[0]); 1166 } else { 1167 cd->ste_rx_chain[i].ste_next = 1168 &cd->ste_rx_chain[i + 1]; 1169 ld->ste_rx_list[i].ste_next = 1170 vtophys(&ld->ste_rx_list[i + 1]); 1171 } 1172 ld->ste_rx_list[i].ste_status = 0; 1173 } 1174 1175 cd->ste_rx_head = &cd->ste_rx_chain[0]; 1176 1177 return(0); 1178 } 1179 1180 static void ste_init_tx_list(sc) 1181 struct ste_softc *sc; 1182 { 1183 struct ste_chain_data *cd; 1184 struct ste_list_data *ld; 1185 int i; 1186 1187 cd = &sc->ste_cdata; 1188 ld = sc->ste_ldata; 1189 for (i = 0; i < STE_TX_LIST_CNT; i++) { 1190 cd->ste_tx_chain[i].ste_ptr = &ld->ste_tx_list[i]; 1191 cd->ste_tx_chain[i].ste_ptr->ste_next = 0; 1192 cd->ste_tx_chain[i].ste_ptr->ste_ctl = 0; 1193 cd->ste_tx_chain[i].ste_phys = vtophys(&ld->ste_tx_list[i]); 1194 if (i == (STE_TX_LIST_CNT - 1)) 1195 cd->ste_tx_chain[i].ste_next = 1196 &cd->ste_tx_chain[0]; 1197 else 1198 cd->ste_tx_chain[i].ste_next = 1199 &cd->ste_tx_chain[i + 1]; 1200 if (i == 0) 1201 cd->ste_tx_chain[i].ste_prev = 1202 &cd->ste_tx_chain[STE_TX_LIST_CNT - 1]; 1203 else 1204 cd->ste_tx_chain[i].ste_prev = 1205 &cd->ste_tx_chain[i - 1]; 1206 } 1207 1208 cd->ste_tx_prod = 0; 1209 cd->ste_tx_cons = 0; 1210 cd->ste_tx_cnt = 0; 1211 1212 return; 1213 } 1214 1215 static void ste_init(xsc) 1216 void *xsc; 1217 { 1218 struct ste_softc *sc; 1219 int i, s; 1220 struct ifnet *ifp; 1221 struct mii_data *mii; 1222 1223 s = splimp(); 1224 1225 sc = xsc; 1226 ifp = &sc->arpcom.ac_if; 1227 mii = device_get_softc(sc->ste_miibus); 1228 1229 ste_stop(sc); 1230 1231 /* Init our MAC address */ 1232 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1233 CSR_WRITE_1(sc, STE_PAR0 + i, sc->arpcom.ac_enaddr[i]); 1234 } 1235 1236 /* Init RX list */ 1237 if (ste_init_rx_list(sc) == ENOBUFS) { 1238 printf("ste%d: initialization failed: no " 1239 "memory for RX buffers\n", sc->ste_unit); 1240 ste_stop(sc); 1241 splx(s); 1242 return; 1243 } 1244 1245 /* Set RX polling interval */ 1246 CSR_WRITE_1(sc, STE_RX_DMAPOLL_PERIOD, 1); 1247 1248 /* Init TX descriptors */ 1249 ste_init_tx_list(sc); 1250 1251 /* Set the TX freethresh value */ 1252 CSR_WRITE_1(sc, STE_TX_DMABURST_THRESH, STE_PACKET_SIZE >> 8); 1253 1254 /* Set the TX start threshold for best performance. */ 1255 CSR_WRITE_2(sc, STE_TX_STARTTHRESH, sc->ste_tx_thresh); 1256 1257 /* Set the TX reclaim threshold. */ 1258 CSR_WRITE_1(sc, STE_TX_RECLAIM_THRESH, (STE_PACKET_SIZE >> 4)); 1259 1260 /* Set up the RX filter. */ 1261 CSR_WRITE_1(sc, STE_RX_MODE, STE_RXMODE_UNICAST); 1262 1263 /* If we want promiscuous mode, set the allframes bit. */ 1264 if (ifp->if_flags & IFF_PROMISC) { 1265 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_PROMISC); 1266 } else { 1267 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_PROMISC); 1268 } 1269 1270 /* Set capture broadcast bit to accept broadcast frames. */ 1271 if (ifp->if_flags & IFF_BROADCAST) { 1272 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_BROADCAST); 1273 } else { 1274 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_BROADCAST); 1275 } 1276 1277 ste_setmulti(sc); 1278 1279 /* Load the address of the RX list. */ 1280 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_STALL); 1281 ste_wait(sc); 1282 CSR_WRITE_4(sc, STE_RX_DMALIST_PTR, 1283 vtophys(&sc->ste_ldata->ste_rx_list[0])); 1284 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL); 1285 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL); 1286 1287 /* Set TX polling interval (defer until we TX first packet */ 1288 CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 0); 1289 1290 /* Load address of the TX list */ 1291 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL); 1292 ste_wait(sc); 1293 CSR_WRITE_4(sc, STE_TX_DMALIST_PTR, 0); 1294 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 1295 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 1296 ste_wait(sc); 1297 sc->ste_tx_prev_idx=-1; 1298 1299 /* Enable receiver and transmitter */ 1300 CSR_WRITE_2(sc, STE_MACCTL0, 0); 1301 CSR_WRITE_2(sc, STE_MACCTL1, 0); 1302 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_TX_ENABLE); 1303 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_RX_ENABLE); 1304 1305 /* Enable stats counters. */ 1306 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_STATS_ENABLE); 1307 1308 /* Enable interrupts. */ 1309 CSR_WRITE_2(sc, STE_ISR, 0xFFFF); 1310 CSR_WRITE_2(sc, STE_IMR, STE_INTRS); 1311 1312 /* Accept VLAN length packets */ 1313 CSR_WRITE_2(sc, STE_MAX_FRAMELEN, ETHER_MAX_LEN + EVL_ENCAPLEN); 1314 1315 ste_ifmedia_upd(ifp); 1316 1317 ifp->if_flags |= IFF_RUNNING; 1318 ifp->if_flags &= ~IFF_OACTIVE; 1319 1320 splx(s); 1321 1322 callout_reset(&sc->ste_stat_timer, hz, ste_stats_update, sc); 1323 1324 return; 1325 } 1326 1327 static void ste_stop(sc) 1328 struct ste_softc *sc; 1329 { 1330 int i; 1331 struct ifnet *ifp; 1332 1333 ifp = &sc->arpcom.ac_if; 1334 1335 callout_stop(&sc->ste_stat_timer); 1336 1337 CSR_WRITE_2(sc, STE_IMR, 0); 1338 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_TX_DISABLE); 1339 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_RX_DISABLE); 1340 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_STATS_DISABLE); 1341 STE_SETBIT2(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL); 1342 STE_SETBIT2(sc, STE_DMACTL, STE_DMACTL_RXDMA_STALL); 1343 ste_wait(sc); 1344 /* 1345 * Try really hard to stop the RX engine or under heavy RX 1346 * data chip will write into de-allocated memory. 1347 */ 1348 ste_reset(sc); 1349 1350 sc->ste_link = 0; 1351 1352 for (i = 0; i < STE_RX_LIST_CNT; i++) { 1353 if (sc->ste_cdata.ste_rx_chain[i].ste_mbuf != NULL) { 1354 m_freem(sc->ste_cdata.ste_rx_chain[i].ste_mbuf); 1355 sc->ste_cdata.ste_rx_chain[i].ste_mbuf = NULL; 1356 } 1357 } 1358 1359 for (i = 0; i < STE_TX_LIST_CNT; i++) { 1360 if (sc->ste_cdata.ste_tx_chain[i].ste_mbuf != NULL) { 1361 m_freem(sc->ste_cdata.ste_tx_chain[i].ste_mbuf); 1362 sc->ste_cdata.ste_tx_chain[i].ste_mbuf = NULL; 1363 } 1364 } 1365 1366 bzero(sc->ste_ldata, sizeof(struct ste_list_data)); 1367 1368 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 1369 1370 return; 1371 } 1372 1373 static void ste_reset(sc) 1374 struct ste_softc *sc; 1375 { 1376 int i; 1377 1378 STE_SETBIT4(sc, STE_ASICCTL, 1379 STE_ASICCTL_GLOBAL_RESET|STE_ASICCTL_RX_RESET| 1380 STE_ASICCTL_TX_RESET|STE_ASICCTL_DMA_RESET| 1381 STE_ASICCTL_FIFO_RESET|STE_ASICCTL_NETWORK_RESET| 1382 STE_ASICCTL_AUTOINIT_RESET|STE_ASICCTL_HOST_RESET| 1383 STE_ASICCTL_EXTRESET_RESET); 1384 1385 DELAY(100000); 1386 1387 for (i = 0; i < STE_TIMEOUT; i++) { 1388 if (!(CSR_READ_4(sc, STE_ASICCTL) & STE_ASICCTL_RESET_BUSY)) 1389 break; 1390 } 1391 1392 if (i == STE_TIMEOUT) 1393 printf("ste%d: global reset never completed\n", sc->ste_unit); 1394 1395 return; 1396 } 1397 1398 static int ste_ioctl(ifp, command, data, cr) 1399 struct ifnet *ifp; 1400 u_long command; 1401 caddr_t data; 1402 struct ucred *cr; 1403 { 1404 struct ste_softc *sc; 1405 struct ifreq *ifr; 1406 struct mii_data *mii; 1407 int error = 0, s; 1408 1409 s = splimp(); 1410 1411 sc = ifp->if_softc; 1412 ifr = (struct ifreq *)data; 1413 1414 switch(command) { 1415 case SIOCSIFADDR: 1416 case SIOCGIFADDR: 1417 case SIOCSIFMTU: 1418 error = ether_ioctl(ifp, command, data); 1419 break; 1420 case SIOCSIFFLAGS: 1421 if (ifp->if_flags & IFF_UP) { 1422 if (ifp->if_flags & IFF_RUNNING && 1423 ifp->if_flags & IFF_PROMISC && 1424 !(sc->ste_if_flags & IFF_PROMISC)) { 1425 STE_SETBIT1(sc, STE_RX_MODE, 1426 STE_RXMODE_PROMISC); 1427 } else if (ifp->if_flags & IFF_RUNNING && 1428 !(ifp->if_flags & IFF_PROMISC) && 1429 sc->ste_if_flags & IFF_PROMISC) { 1430 STE_CLRBIT1(sc, STE_RX_MODE, 1431 STE_RXMODE_PROMISC); 1432 } 1433 if (!(ifp->if_flags & IFF_RUNNING)) { 1434 sc->ste_tx_thresh = STE_TXSTART_THRESH; 1435 ste_init(sc); 1436 } 1437 } else { 1438 if (ifp->if_flags & IFF_RUNNING) 1439 ste_stop(sc); 1440 } 1441 sc->ste_if_flags = ifp->if_flags; 1442 error = 0; 1443 break; 1444 case SIOCADDMULTI: 1445 case SIOCDELMULTI: 1446 ste_setmulti(sc); 1447 error = 0; 1448 break; 1449 case SIOCGIFMEDIA: 1450 case SIOCSIFMEDIA: 1451 mii = device_get_softc(sc->ste_miibus); 1452 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1453 break; 1454 default: 1455 error = EINVAL; 1456 break; 1457 } 1458 1459 splx(s); 1460 1461 return(error); 1462 } 1463 1464 static int ste_encap(sc, c, m_head) 1465 struct ste_softc *sc; 1466 struct ste_chain *c; 1467 struct mbuf *m_head; 1468 { 1469 int frag = 0; 1470 struct ste_frag *f = NULL; 1471 struct mbuf *m; 1472 struct ste_desc *d; 1473 int total_len = 0; 1474 1475 d = c->ste_ptr; 1476 d->ste_ctl = 0; 1477 1478 encap_retry: 1479 for (m = m_head, frag = 0; m != NULL; m = m->m_next) { 1480 if (m->m_len != 0) { 1481 if (frag == STE_MAXFRAGS) 1482 break; 1483 total_len += m->m_len; 1484 f = &d->ste_frags[frag]; 1485 f->ste_addr = vtophys(mtod(m, vm_offset_t)); 1486 f->ste_len = m->m_len; 1487 frag++; 1488 } 1489 } 1490 1491 if (m != NULL) { 1492 struct mbuf *mn; 1493 1494 /* 1495 * We ran out of segments. We have to recopy this 1496 * mbuf chain first. Bail out if we can't get the 1497 * new buffers. Code borrowed from if_fxp.c. 1498 */ 1499 MGETHDR(mn, MB_DONTWAIT, MT_DATA); 1500 if (mn == NULL) { 1501 m_freem(m_head); 1502 return ENOMEM; 1503 } 1504 if (m_head->m_pkthdr.len > MHLEN) { 1505 MCLGET(mn, MB_DONTWAIT); 1506 if ((mn->m_flags & M_EXT) == 0) { 1507 m_freem(mn); 1508 m_freem(m_head); 1509 return ENOMEM; 1510 } 1511 } 1512 m_copydata(m_head, 0, m_head->m_pkthdr.len, 1513 mtod(mn, caddr_t)); 1514 mn->m_pkthdr.len = mn->m_len = m_head->m_pkthdr.len; 1515 m_freem(m_head); 1516 m_head = mn; 1517 goto encap_retry; 1518 } 1519 1520 c->ste_mbuf = m_head; 1521 d->ste_frags[frag - 1].ste_len |= STE_FRAG_LAST; 1522 d->ste_ctl = 1; 1523 1524 return(0); 1525 } 1526 1527 static void ste_start(ifp) 1528 struct ifnet *ifp; 1529 { 1530 struct ste_softc *sc; 1531 struct mbuf *m_head = NULL; 1532 struct ste_chain *cur_tx = NULL; 1533 int idx; 1534 1535 sc = ifp->if_softc; 1536 1537 if (!sc->ste_link) 1538 return; 1539 1540 if (ifp->if_flags & IFF_OACTIVE) 1541 return; 1542 1543 idx = sc->ste_cdata.ste_tx_prod; 1544 1545 while(sc->ste_cdata.ste_tx_chain[idx].ste_mbuf == NULL) { 1546 1547 if ((STE_TX_LIST_CNT - sc->ste_cdata.ste_tx_cnt) < 3) { 1548 ifp->if_flags |= IFF_OACTIVE; 1549 break; 1550 } 1551 1552 IF_DEQUEUE(&ifp->if_snd, m_head); 1553 if (m_head == NULL) 1554 break; 1555 1556 cur_tx = &sc->ste_cdata.ste_tx_chain[idx]; 1557 1558 if (ste_encap(sc, cur_tx, m_head) != 0) 1559 break; 1560 1561 cur_tx->ste_ptr->ste_next = 0; 1562 1563 if(sc->ste_tx_prev_idx < 0){ 1564 cur_tx->ste_ptr->ste_ctl = STE_TXCTL_DMAINTR | 1; 1565 /* Load address of the TX list */ 1566 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL); 1567 ste_wait(sc); 1568 1569 CSR_WRITE_4(sc, STE_TX_DMALIST_PTR, 1570 vtophys(&sc->ste_ldata->ste_tx_list[0])); 1571 1572 /* Set TX polling interval to start TX engine */ 1573 CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 64); 1574 1575 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 1576 ste_wait(sc); 1577 }else{ 1578 cur_tx->ste_ptr->ste_ctl = STE_TXCTL_DMAINTR | 1; 1579 sc->ste_cdata.ste_tx_chain[ 1580 sc->ste_tx_prev_idx].ste_ptr->ste_next 1581 = cur_tx->ste_phys; 1582 } 1583 1584 sc->ste_tx_prev_idx=idx; 1585 1586 BPF_MTAP(ifp, cur_tx->ste_mbuf); 1587 1588 STE_INC(idx, STE_TX_LIST_CNT); 1589 sc->ste_cdata.ste_tx_cnt++; 1590 ifp->if_timer = 5; 1591 sc->ste_cdata.ste_tx_prod = idx; 1592 } 1593 1594 return; 1595 } 1596 1597 static void ste_watchdog(ifp) 1598 struct ifnet *ifp; 1599 { 1600 struct ste_softc *sc; 1601 1602 sc = ifp->if_softc; 1603 1604 ifp->if_oerrors++; 1605 printf("ste%d: watchdog timeout\n", sc->ste_unit); 1606 1607 ste_txeoc(sc); 1608 ste_txeof(sc); 1609 ste_rxeof(sc); 1610 ste_reset(sc); 1611 ste_init(sc); 1612 1613 if (ifp->if_snd.ifq_head != NULL) 1614 ste_start(ifp); 1615 1616 return; 1617 } 1618 1619 static void ste_shutdown(dev) 1620 device_t dev; 1621 { 1622 struct ste_softc *sc; 1623 1624 sc = device_get_softc(dev); 1625 1626 ste_stop(sc); 1627 1628 return; 1629 } 1630