1 /* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: src/sys/pci/if_ste.c,v 1.14.2.9 2003/02/05 22:03:57 mbr Exp $ 33 * $DragonFly: src/sys/dev/netif/ste/if_ste.c,v 1.3 2003/07/26 21:56:10 rob Exp $ 34 * 35 * $FreeBSD: src/sys/pci/if_ste.c,v 1.14.2.9 2003/02/05 22:03:57 mbr Exp $ 36 */ 37 38 #include <sys/param.h> 39 #include <sys/systm.h> 40 #include <sys/sockio.h> 41 #include <sys/mbuf.h> 42 #include <sys/malloc.h> 43 #include <sys/kernel.h> 44 #include <sys/socket.h> 45 46 #include <net/if.h> 47 #include <net/if_arp.h> 48 #include <net/ethernet.h> 49 #include <net/if_dl.h> 50 #include <net/if_media.h> 51 #include <net/if_vlan_var.h> 52 53 #include <net/bpf.h> 54 55 #include <vm/vm.h> /* for vtophys */ 56 #include <vm/pmap.h> /* for vtophys */ 57 #include <machine/clock.h> /* for DELAY */ 58 #include <machine/bus_memio.h> 59 #include <machine/bus_pio.h> 60 #include <machine/bus.h> 61 #include <machine/resource.h> 62 #include <sys/bus.h> 63 #include <sys/rman.h> 64 65 #include <dev/mii/mii.h> 66 #include <dev/mii/miivar.h> 67 68 #include <pci/pcireg.h> 69 #include <pci/pcivar.h> 70 71 /* "controller miibus0" required. See GENERIC if you get errors here. */ 72 #include "miibus_if.h" 73 74 #define STE_USEIOSPACE 75 76 #include <pci/if_stereg.h> 77 78 /* 79 * Various supported device vendors/types and their names. 80 */ 81 static struct ste_type ste_devs[] = { 82 { ST_VENDORID, ST_DEVICEID_ST201, "Sundance ST201 10/100BaseTX" }, 83 { DL_VENDORID, DL_DEVICEID_550TX, "D-Link DFE-550TX 10/100BaseTX" }, 84 { 0, 0, NULL } 85 }; 86 87 static int ste_probe __P((device_t)); 88 static int ste_attach __P((device_t)); 89 static int ste_detach __P((device_t)); 90 static void ste_init __P((void *)); 91 static void ste_intr __P((void *)); 92 static void ste_rxeof __P((struct ste_softc *)); 93 static void ste_txeoc __P((struct ste_softc *)); 94 static void ste_txeof __P((struct ste_softc *)); 95 static void ste_stats_update __P((void *)); 96 static void ste_stop __P((struct ste_softc *)); 97 static void ste_reset __P((struct ste_softc *)); 98 static int ste_ioctl __P((struct ifnet *, u_long, caddr_t)); 99 static int ste_encap __P((struct ste_softc *, struct ste_chain *, 100 struct mbuf *)); 101 static void ste_start __P((struct ifnet *)); 102 static void ste_watchdog __P((struct ifnet *)); 103 static void ste_shutdown __P((device_t)); 104 static int ste_newbuf __P((struct ste_softc *, 105 struct ste_chain_onefrag *, 106 struct mbuf *)); 107 static int ste_ifmedia_upd __P((struct ifnet *)); 108 static void ste_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 109 110 static void ste_mii_sync __P((struct ste_softc *)); 111 static void ste_mii_send __P((struct ste_softc *, u_int32_t, int)); 112 static int ste_mii_readreg __P((struct ste_softc *, 113 struct ste_mii_frame *)); 114 static int ste_mii_writereg __P((struct ste_softc *, 115 struct ste_mii_frame *)); 116 static int ste_miibus_readreg __P((device_t, int, int)); 117 static int ste_miibus_writereg __P((device_t, int, int, int)); 118 static void ste_miibus_statchg __P((device_t)); 119 120 static int ste_eeprom_wait __P((struct ste_softc *)); 121 static int ste_read_eeprom __P((struct ste_softc *, caddr_t, int, 122 int, int)); 123 static void ste_wait __P((struct ste_softc *)); 124 static u_int8_t ste_calchash __P((caddr_t)); 125 static void ste_setmulti __P((struct ste_softc *)); 126 static int ste_init_rx_list __P((struct ste_softc *)); 127 static void ste_init_tx_list __P((struct ste_softc *)); 128 129 #ifdef STE_USEIOSPACE 130 #define STE_RES SYS_RES_IOPORT 131 #define STE_RID STE_PCI_LOIO 132 #else 133 #define STE_RES SYS_RES_MEMORY 134 #define STE_RID STE_PCI_LOMEM 135 #endif 136 137 static device_method_t ste_methods[] = { 138 /* Device interface */ 139 DEVMETHOD(device_probe, ste_probe), 140 DEVMETHOD(device_attach, ste_attach), 141 DEVMETHOD(device_detach, ste_detach), 142 DEVMETHOD(device_shutdown, ste_shutdown), 143 144 /* bus interface */ 145 DEVMETHOD(bus_print_child, bus_generic_print_child), 146 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 147 148 /* MII interface */ 149 DEVMETHOD(miibus_readreg, ste_miibus_readreg), 150 DEVMETHOD(miibus_writereg, ste_miibus_writereg), 151 DEVMETHOD(miibus_statchg, ste_miibus_statchg), 152 153 { 0, 0 } 154 }; 155 156 static driver_t ste_driver = { 157 "ste", 158 ste_methods, 159 sizeof(struct ste_softc) 160 }; 161 162 static devclass_t ste_devclass; 163 164 DRIVER_MODULE(if_ste, pci, ste_driver, ste_devclass, 0, 0); 165 DRIVER_MODULE(miibus, ste, miibus_driver, miibus_devclass, 0, 0); 166 167 #define STE_SETBIT4(sc, reg, x) \ 168 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | x) 169 170 #define STE_CLRBIT4(sc, reg, x) \ 171 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~x) 172 173 #define STE_SETBIT2(sc, reg, x) \ 174 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) | x) 175 176 #define STE_CLRBIT2(sc, reg, x) \ 177 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) & ~x) 178 179 #define STE_SETBIT1(sc, reg, x) \ 180 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | x) 181 182 #define STE_CLRBIT1(sc, reg, x) \ 183 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~x) 184 185 186 #define MII_SET(x) STE_SETBIT1(sc, STE_PHYCTL, x) 187 #define MII_CLR(x) STE_CLRBIT1(sc, STE_PHYCTL, x) 188 189 /* 190 * Sync the PHYs by setting data bit and strobing the clock 32 times. 191 */ 192 static void ste_mii_sync(sc) 193 struct ste_softc *sc; 194 { 195 int i; 196 197 MII_SET(STE_PHYCTL_MDIR|STE_PHYCTL_MDATA); 198 199 for (i = 0; i < 32; i++) { 200 MII_SET(STE_PHYCTL_MCLK); 201 DELAY(1); 202 MII_CLR(STE_PHYCTL_MCLK); 203 DELAY(1); 204 } 205 206 return; 207 } 208 209 /* 210 * Clock a series of bits through the MII. 211 */ 212 static void ste_mii_send(sc, bits, cnt) 213 struct ste_softc *sc; 214 u_int32_t bits; 215 int cnt; 216 { 217 int i; 218 219 MII_CLR(STE_PHYCTL_MCLK); 220 221 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 222 if (bits & i) { 223 MII_SET(STE_PHYCTL_MDATA); 224 } else { 225 MII_CLR(STE_PHYCTL_MDATA); 226 } 227 DELAY(1); 228 MII_CLR(STE_PHYCTL_MCLK); 229 DELAY(1); 230 MII_SET(STE_PHYCTL_MCLK); 231 } 232 } 233 234 /* 235 * Read an PHY register through the MII. 236 */ 237 static int ste_mii_readreg(sc, frame) 238 struct ste_softc *sc; 239 struct ste_mii_frame *frame; 240 241 { 242 int i, ack, s; 243 244 s = splimp(); 245 246 /* 247 * Set up frame for RX. 248 */ 249 frame->mii_stdelim = STE_MII_STARTDELIM; 250 frame->mii_opcode = STE_MII_READOP; 251 frame->mii_turnaround = 0; 252 frame->mii_data = 0; 253 254 CSR_WRITE_2(sc, STE_PHYCTL, 0); 255 /* 256 * Turn on data xmit. 257 */ 258 MII_SET(STE_PHYCTL_MDIR); 259 260 ste_mii_sync(sc); 261 262 /* 263 * Send command/address info. 264 */ 265 ste_mii_send(sc, frame->mii_stdelim, 2); 266 ste_mii_send(sc, frame->mii_opcode, 2); 267 ste_mii_send(sc, frame->mii_phyaddr, 5); 268 ste_mii_send(sc, frame->mii_regaddr, 5); 269 270 /* Turn off xmit. */ 271 MII_CLR(STE_PHYCTL_MDIR); 272 273 /* Idle bit */ 274 MII_CLR((STE_PHYCTL_MCLK|STE_PHYCTL_MDATA)); 275 DELAY(1); 276 MII_SET(STE_PHYCTL_MCLK); 277 DELAY(1); 278 279 /* Check for ack */ 280 MII_CLR(STE_PHYCTL_MCLK); 281 DELAY(1); 282 ack = CSR_READ_2(sc, STE_PHYCTL) & STE_PHYCTL_MDATA; 283 MII_SET(STE_PHYCTL_MCLK); 284 DELAY(1); 285 286 /* 287 * Now try reading data bits. If the ack failed, we still 288 * need to clock through 16 cycles to keep the PHY(s) in sync. 289 */ 290 if (ack) { 291 for(i = 0; i < 16; i++) { 292 MII_CLR(STE_PHYCTL_MCLK); 293 DELAY(1); 294 MII_SET(STE_PHYCTL_MCLK); 295 DELAY(1); 296 } 297 goto fail; 298 } 299 300 for (i = 0x8000; i; i >>= 1) { 301 MII_CLR(STE_PHYCTL_MCLK); 302 DELAY(1); 303 if (!ack) { 304 if (CSR_READ_2(sc, STE_PHYCTL) & STE_PHYCTL_MDATA) 305 frame->mii_data |= i; 306 DELAY(1); 307 } 308 MII_SET(STE_PHYCTL_MCLK); 309 DELAY(1); 310 } 311 312 fail: 313 314 MII_CLR(STE_PHYCTL_MCLK); 315 DELAY(1); 316 MII_SET(STE_PHYCTL_MCLK); 317 DELAY(1); 318 319 splx(s); 320 321 if (ack) 322 return(1); 323 return(0); 324 } 325 326 /* 327 * Write to a PHY register through the MII. 328 */ 329 static int ste_mii_writereg(sc, frame) 330 struct ste_softc *sc; 331 struct ste_mii_frame *frame; 332 333 { 334 int s; 335 336 s = splimp(); 337 /* 338 * Set up frame for TX. 339 */ 340 341 frame->mii_stdelim = STE_MII_STARTDELIM; 342 frame->mii_opcode = STE_MII_WRITEOP; 343 frame->mii_turnaround = STE_MII_TURNAROUND; 344 345 /* 346 * Turn on data output. 347 */ 348 MII_SET(STE_PHYCTL_MDIR); 349 350 ste_mii_sync(sc); 351 352 ste_mii_send(sc, frame->mii_stdelim, 2); 353 ste_mii_send(sc, frame->mii_opcode, 2); 354 ste_mii_send(sc, frame->mii_phyaddr, 5); 355 ste_mii_send(sc, frame->mii_regaddr, 5); 356 ste_mii_send(sc, frame->mii_turnaround, 2); 357 ste_mii_send(sc, frame->mii_data, 16); 358 359 /* Idle bit. */ 360 MII_SET(STE_PHYCTL_MCLK); 361 DELAY(1); 362 MII_CLR(STE_PHYCTL_MCLK); 363 DELAY(1); 364 365 /* 366 * Turn off xmit. 367 */ 368 MII_CLR(STE_PHYCTL_MDIR); 369 370 splx(s); 371 372 return(0); 373 } 374 375 static int ste_miibus_readreg(dev, phy, reg) 376 device_t dev; 377 int phy, reg; 378 { 379 struct ste_softc *sc; 380 struct ste_mii_frame frame; 381 382 sc = device_get_softc(dev); 383 384 if ( sc->ste_one_phy && phy != 0 ) 385 return (0); 386 387 bzero((char *)&frame, sizeof(frame)); 388 389 frame.mii_phyaddr = phy; 390 frame.mii_regaddr = reg; 391 ste_mii_readreg(sc, &frame); 392 393 return(frame.mii_data); 394 } 395 396 static int ste_miibus_writereg(dev, phy, reg, data) 397 device_t dev; 398 int phy, reg, data; 399 { 400 struct ste_softc *sc; 401 struct ste_mii_frame frame; 402 403 sc = device_get_softc(dev); 404 bzero((char *)&frame, sizeof(frame)); 405 406 frame.mii_phyaddr = phy; 407 frame.mii_regaddr = reg; 408 frame.mii_data = data; 409 410 ste_mii_writereg(sc, &frame); 411 412 return(0); 413 } 414 415 static void ste_miibus_statchg(dev) 416 device_t dev; 417 { 418 struct ste_softc *sc; 419 struct mii_data *mii; 420 int i; 421 422 sc = device_get_softc(dev); 423 mii = device_get_softc(sc->ste_miibus); 424 425 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 426 STE_SETBIT2(sc, STE_MACCTL0, STE_MACCTL0_FULLDUPLEX); 427 } else { 428 STE_CLRBIT2(sc, STE_MACCTL0, STE_MACCTL0_FULLDUPLEX); 429 } 430 431 STE_SETBIT4(sc, STE_ASICCTL,STE_ASICCTL_RX_RESET | 432 STE_ASICCTL_TX_RESET); 433 for (i = 0; i < STE_TIMEOUT; i++) { 434 if (!(CSR_READ_4(sc, STE_ASICCTL) & STE_ASICCTL_RESET_BUSY)) 435 break; 436 } 437 if (i == STE_TIMEOUT) 438 printf("ste%d: rx reset never completed\n", sc->ste_unit); 439 440 return; 441 } 442 443 static int ste_ifmedia_upd(ifp) 444 struct ifnet *ifp; 445 { 446 struct ste_softc *sc; 447 struct mii_data *mii; 448 449 sc = ifp->if_softc; 450 mii = device_get_softc(sc->ste_miibus); 451 sc->ste_link = 0; 452 if (mii->mii_instance) { 453 struct mii_softc *miisc; 454 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 455 miisc = LIST_NEXT(miisc, mii_list)) 456 mii_phy_reset(miisc); 457 } 458 mii_mediachg(mii); 459 460 return(0); 461 } 462 463 static void ste_ifmedia_sts(ifp, ifmr) 464 struct ifnet *ifp; 465 struct ifmediareq *ifmr; 466 { 467 struct ste_softc *sc; 468 struct mii_data *mii; 469 470 sc = ifp->if_softc; 471 mii = device_get_softc(sc->ste_miibus); 472 473 mii_pollstat(mii); 474 ifmr->ifm_active = mii->mii_media_active; 475 ifmr->ifm_status = mii->mii_media_status; 476 477 return; 478 } 479 480 static void ste_wait(sc) 481 struct ste_softc *sc; 482 { 483 int i; 484 485 for (i = 0; i < STE_TIMEOUT; i++) { 486 if (!(CSR_READ_4(sc, STE_DMACTL) & STE_DMACTL_DMA_HALTINPROG)) 487 break; 488 } 489 490 if (i == STE_TIMEOUT) 491 printf("ste%d: command never completed!\n", sc->ste_unit); 492 493 return; 494 } 495 496 /* 497 * The EEPROM is slow: give it time to come ready after issuing 498 * it a command. 499 */ 500 static int ste_eeprom_wait(sc) 501 struct ste_softc *sc; 502 { 503 int i; 504 505 DELAY(1000); 506 507 for (i = 0; i < 100; i++) { 508 if (CSR_READ_2(sc, STE_EEPROM_CTL) & STE_EECTL_BUSY) 509 DELAY(1000); 510 else 511 break; 512 } 513 514 if (i == 100) { 515 printf("ste%d: eeprom failed to come ready\n", sc->ste_unit); 516 return(1); 517 } 518 519 return(0); 520 } 521 522 /* 523 * Read a sequence of words from the EEPROM. Note that ethernet address 524 * data is stored in the EEPROM in network byte order. 525 */ 526 static int ste_read_eeprom(sc, dest, off, cnt, swap) 527 struct ste_softc *sc; 528 caddr_t dest; 529 int off; 530 int cnt; 531 int swap; 532 { 533 int err = 0, i; 534 u_int16_t word = 0, *ptr; 535 536 if (ste_eeprom_wait(sc)) 537 return(1); 538 539 for (i = 0; i < cnt; i++) { 540 CSR_WRITE_2(sc, STE_EEPROM_CTL, STE_EEOPCODE_READ | (off + i)); 541 err = ste_eeprom_wait(sc); 542 if (err) 543 break; 544 word = CSR_READ_2(sc, STE_EEPROM_DATA); 545 ptr = (u_int16_t *)(dest + (i * 2)); 546 if (swap) 547 *ptr = ntohs(word); 548 else 549 *ptr = word; 550 } 551 552 return(err ? 1 : 0); 553 } 554 555 static u_int8_t ste_calchash(addr) 556 caddr_t addr; 557 { 558 559 u_int32_t crc, carry; 560 int i, j; 561 u_int8_t c; 562 563 /* Compute CRC for the address value. */ 564 crc = 0xFFFFFFFF; /* initial value */ 565 566 for (i = 0; i < 6; i++) { 567 c = *(addr + i); 568 for (j = 0; j < 8; j++) { 569 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 570 crc <<= 1; 571 c >>= 1; 572 if (carry) 573 crc = (crc ^ 0x04c11db6) | carry; 574 } 575 } 576 577 /* return the filter bit position */ 578 return(crc & 0x0000003F); 579 } 580 581 static void ste_setmulti(sc) 582 struct ste_softc *sc; 583 { 584 struct ifnet *ifp; 585 int h = 0; 586 u_int32_t hashes[2] = { 0, 0 }; 587 struct ifmultiaddr *ifma; 588 589 ifp = &sc->arpcom.ac_if; 590 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 591 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_ALLMULTI); 592 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_MULTIHASH); 593 return; 594 } 595 596 /* first, zot all the existing hash bits */ 597 CSR_WRITE_2(sc, STE_MAR0, 0); 598 CSR_WRITE_2(sc, STE_MAR1, 0); 599 CSR_WRITE_2(sc, STE_MAR2, 0); 600 CSR_WRITE_2(sc, STE_MAR3, 0); 601 602 /* now program new ones */ 603 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 604 ifma = ifma->ifma_link.le_next) { 605 if (ifma->ifma_addr->sa_family != AF_LINK) 606 continue; 607 h = ste_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 608 if (h < 32) 609 hashes[0] |= (1 << h); 610 else 611 hashes[1] |= (1 << (h - 32)); 612 } 613 614 CSR_WRITE_2(sc, STE_MAR0, hashes[0] & 0xFFFF); 615 CSR_WRITE_2(sc, STE_MAR1, (hashes[0] >> 16) & 0xFFFF); 616 CSR_WRITE_2(sc, STE_MAR2, hashes[1] & 0xFFFF); 617 CSR_WRITE_2(sc, STE_MAR3, (hashes[1] >> 16) & 0xFFFF); 618 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_ALLMULTI); 619 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_MULTIHASH); 620 621 return; 622 } 623 624 static void ste_intr(xsc) 625 void *xsc; 626 { 627 struct ste_softc *sc; 628 struct ifnet *ifp; 629 u_int16_t status; 630 631 sc = xsc; 632 ifp = &sc->arpcom.ac_if; 633 634 /* See if this is really our interrupt. */ 635 if (!(CSR_READ_2(sc, STE_ISR) & STE_ISR_INTLATCH)) 636 return; 637 638 for (;;) { 639 status = CSR_READ_2(sc, STE_ISR_ACK); 640 641 if (!(status & STE_INTRS)) 642 break; 643 644 if (status & STE_ISR_RX_DMADONE) 645 ste_rxeof(sc); 646 647 if (status & STE_ISR_TX_DMADONE) 648 ste_txeof(sc); 649 650 if (status & STE_ISR_TX_DONE) 651 ste_txeoc(sc); 652 653 if (status & STE_ISR_STATS_OFLOW) { 654 untimeout(ste_stats_update, sc, sc->ste_stat_ch); 655 ste_stats_update(sc); 656 } 657 658 if (status & STE_ISR_LINKEVENT) 659 mii_pollstat(device_get_softc(sc->ste_miibus)); 660 661 if (status & STE_ISR_HOSTERR) { 662 ste_reset(sc); 663 ste_init(sc); 664 } 665 } 666 667 /* Re-enable interrupts */ 668 CSR_WRITE_2(sc, STE_IMR, STE_INTRS); 669 670 if (ifp->if_snd.ifq_head != NULL) 671 ste_start(ifp); 672 673 return; 674 } 675 676 /* 677 * A frame has been uploaded: pass the resulting mbuf chain up to 678 * the higher level protocols. 679 */ 680 static void ste_rxeof(sc) 681 struct ste_softc *sc; 682 { 683 struct ether_header *eh; 684 struct mbuf *m; 685 struct ifnet *ifp; 686 struct ste_chain_onefrag *cur_rx; 687 int total_len = 0, count=0; 688 u_int32_t rxstat; 689 690 ifp = &sc->arpcom.ac_if; 691 692 while((rxstat = sc->ste_cdata.ste_rx_head->ste_ptr->ste_status) 693 & STE_RXSTAT_DMADONE) { 694 if ((STE_RX_LIST_CNT - count) < 3) { 695 break; 696 } 697 698 cur_rx = sc->ste_cdata.ste_rx_head; 699 sc->ste_cdata.ste_rx_head = cur_rx->ste_next; 700 701 /* 702 * If an error occurs, update stats, clear the 703 * status word and leave the mbuf cluster in place: 704 * it should simply get re-used next time this descriptor 705 * comes up in the ring. 706 */ 707 if (rxstat & STE_RXSTAT_FRAME_ERR) { 708 ifp->if_ierrors++; 709 cur_rx->ste_ptr->ste_status = 0; 710 continue; 711 } 712 713 /* 714 * If there error bit was not set, the upload complete 715 * bit should be set which means we have a valid packet. 716 * If not, something truly strange has happened. 717 */ 718 if (!(rxstat & STE_RXSTAT_DMADONE)) { 719 printf("ste%d: bad receive status -- packet dropped", 720 sc->ste_unit); 721 ifp->if_ierrors++; 722 cur_rx->ste_ptr->ste_status = 0; 723 continue; 724 } 725 726 /* No errors; receive the packet. */ 727 m = cur_rx->ste_mbuf; 728 total_len = cur_rx->ste_ptr->ste_status & STE_RXSTAT_FRAMELEN; 729 730 /* 731 * Try to conjure up a new mbuf cluster. If that 732 * fails, it means we have an out of memory condition and 733 * should leave the buffer in place and continue. This will 734 * result in a lost packet, but there's little else we 735 * can do in this situation. 736 */ 737 if (ste_newbuf(sc, cur_rx, NULL) == ENOBUFS) { 738 ifp->if_ierrors++; 739 cur_rx->ste_ptr->ste_status = 0; 740 continue; 741 } 742 743 ifp->if_ipackets++; 744 eh = mtod(m, struct ether_header *); 745 m->m_pkthdr.rcvif = ifp; 746 m->m_pkthdr.len = m->m_len = total_len; 747 748 /* Remove header from mbuf and pass it on. */ 749 m_adj(m, sizeof(struct ether_header)); 750 ether_input(ifp, eh, m); 751 752 cur_rx->ste_ptr->ste_status = 0; 753 count++; 754 } 755 756 return; 757 } 758 759 static void ste_txeoc(sc) 760 struct ste_softc *sc; 761 { 762 u_int8_t txstat; 763 struct ifnet *ifp; 764 765 ifp = &sc->arpcom.ac_if; 766 767 while ((txstat = CSR_READ_1(sc, STE_TX_STATUS)) & 768 STE_TXSTATUS_TXDONE) { 769 if (txstat & STE_TXSTATUS_UNDERRUN || 770 txstat & STE_TXSTATUS_EXCESSCOLLS || 771 txstat & STE_TXSTATUS_RECLAIMERR) { 772 ifp->if_oerrors++; 773 printf("ste%d: transmission error: %x\n", 774 sc->ste_unit, txstat); 775 776 ste_reset(sc); 777 ste_init(sc); 778 779 if (txstat & STE_TXSTATUS_UNDERRUN && 780 sc->ste_tx_thresh < STE_PACKET_SIZE) { 781 sc->ste_tx_thresh += STE_MIN_FRAMELEN; 782 printf("ste%d: tx underrun, increasing tx" 783 " start threshold to %d bytes\n", 784 sc->ste_unit, sc->ste_tx_thresh); 785 } 786 CSR_WRITE_2(sc, STE_TX_STARTTHRESH, sc->ste_tx_thresh); 787 CSR_WRITE_2(sc, STE_TX_RECLAIM_THRESH, 788 (STE_PACKET_SIZE >> 4)); 789 } 790 ste_init(sc); 791 CSR_WRITE_2(sc, STE_TX_STATUS, txstat); 792 } 793 794 return; 795 } 796 797 static void ste_txeof(sc) 798 struct ste_softc *sc; 799 { 800 struct ste_chain *cur_tx = NULL; 801 struct ifnet *ifp; 802 int idx; 803 804 ifp = &sc->arpcom.ac_if; 805 806 idx = sc->ste_cdata.ste_tx_cons; 807 while(idx != sc->ste_cdata.ste_tx_prod) { 808 cur_tx = &sc->ste_cdata.ste_tx_chain[idx]; 809 810 if (!(cur_tx->ste_ptr->ste_ctl & STE_TXCTL_DMADONE)) 811 break; 812 813 if (cur_tx->ste_mbuf != NULL) { 814 m_freem(cur_tx->ste_mbuf); 815 cur_tx->ste_mbuf = NULL; 816 } 817 818 ifp->if_opackets++; 819 820 sc->ste_cdata.ste_tx_cnt--; 821 STE_INC(idx, STE_TX_LIST_CNT); 822 ifp->if_timer = 0; 823 } 824 825 sc->ste_cdata.ste_tx_cons = idx; 826 827 if (cur_tx != NULL) 828 ifp->if_flags &= ~IFF_OACTIVE; 829 830 return; 831 } 832 833 static void ste_stats_update(xsc) 834 void *xsc; 835 { 836 struct ste_softc *sc; 837 struct ifnet *ifp; 838 struct mii_data *mii; 839 int s; 840 841 s = splimp(); 842 843 sc = xsc; 844 ifp = &sc->arpcom.ac_if; 845 mii = device_get_softc(sc->ste_miibus); 846 847 ifp->if_collisions += CSR_READ_1(sc, STE_LATE_COLLS) 848 + CSR_READ_1(sc, STE_MULTI_COLLS) 849 + CSR_READ_1(sc, STE_SINGLE_COLLS); 850 851 if (!sc->ste_link) { 852 mii_pollstat(mii); 853 if (mii->mii_media_status & IFM_ACTIVE && 854 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 855 sc->ste_link++; 856 /* 857 * we don't get a call-back on re-init so do it 858 * otherwise we get stuck in the wrong link state 859 */ 860 ste_miibus_statchg(sc->ste_dev); 861 if (ifp->if_snd.ifq_head != NULL) 862 ste_start(ifp); 863 } 864 } 865 866 sc->ste_stat_ch = timeout(ste_stats_update, sc, hz); 867 splx(s); 868 869 return; 870 } 871 872 873 /* 874 * Probe for a Sundance ST201 chip. Check the PCI vendor and device 875 * IDs against our list and return a device name if we find a match. 876 */ 877 static int ste_probe(dev) 878 device_t dev; 879 { 880 struct ste_type *t; 881 882 t = ste_devs; 883 884 while(t->ste_name != NULL) { 885 if ((pci_get_vendor(dev) == t->ste_vid) && 886 (pci_get_device(dev) == t->ste_did)) { 887 device_set_desc(dev, t->ste_name); 888 return(0); 889 } 890 t++; 891 } 892 893 return(ENXIO); 894 } 895 896 /* 897 * Attach the interface. Allocate softc structures, do ifmedia 898 * setup and ethernet/BPF attach. 899 */ 900 static int ste_attach(dev) 901 device_t dev; 902 { 903 int s; 904 u_int32_t command; 905 struct ste_softc *sc; 906 struct ifnet *ifp; 907 int unit, error = 0, rid; 908 909 s = splimp(); 910 911 sc = device_get_softc(dev); 912 unit = device_get_unit(dev); 913 bzero(sc, sizeof(struct ste_softc)); 914 sc->ste_dev = dev; 915 916 /* 917 * Only use one PHY since this chip reports multiple 918 * Note on the DFE-550 the PHY is at 1 on the DFE-580 919 * it is at 0 & 1. It is rev 0x12. 920 */ 921 if (pci_get_vendor(dev) == DL_VENDORID && 922 pci_get_device(dev) == DL_DEVICEID_550TX && 923 pci_get_revid(dev) == 0x12 ) 924 sc->ste_one_phy = 1; 925 926 /* 927 * Handle power management nonsense. 928 */ 929 command = pci_read_config(dev, STE_PCI_CAPID, 4) & 0x000000FF; 930 if (command == 0x01) { 931 932 command = pci_read_config(dev, STE_PCI_PWRMGMTCTRL, 4); 933 if (command & STE_PSTATE_MASK) { 934 u_int32_t iobase, membase, irq; 935 936 /* Save important PCI config data. */ 937 iobase = pci_read_config(dev, STE_PCI_LOIO, 4); 938 membase = pci_read_config(dev, STE_PCI_LOMEM, 4); 939 irq = pci_read_config(dev, STE_PCI_INTLINE, 4); 940 941 /* Reset the power state. */ 942 printf("ste%d: chip is in D%d power mode " 943 "-- setting to D0\n", unit, command & STE_PSTATE_MASK); 944 command &= 0xFFFFFFFC; 945 pci_write_config(dev, STE_PCI_PWRMGMTCTRL, command, 4); 946 947 /* Restore PCI config data. */ 948 pci_write_config(dev, STE_PCI_LOIO, iobase, 4); 949 pci_write_config(dev, STE_PCI_LOMEM, membase, 4); 950 pci_write_config(dev, STE_PCI_INTLINE, irq, 4); 951 } 952 } 953 954 /* 955 * Map control/status registers. 956 */ 957 command = pci_read_config(dev, PCIR_COMMAND, 4); 958 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 959 pci_write_config(dev, PCIR_COMMAND, command, 4); 960 command = pci_read_config(dev, PCIR_COMMAND, 4); 961 962 #ifdef STE_USEIOSPACE 963 if (!(command & PCIM_CMD_PORTEN)) { 964 printf("ste%d: failed to enable I/O ports!\n", unit); 965 error = ENXIO; 966 goto fail; 967 } 968 #else 969 if (!(command & PCIM_CMD_MEMEN)) { 970 printf("ste%d: failed to enable memory mapping!\n", unit); 971 error = ENXIO; 972 goto fail; 973 } 974 #endif 975 976 rid = STE_RID; 977 sc->ste_res = bus_alloc_resource(dev, STE_RES, &rid, 978 0, ~0, 1, RF_ACTIVE); 979 980 if (sc->ste_res == NULL) { 981 printf ("ste%d: couldn't map ports/memory\n", unit); 982 error = ENXIO; 983 goto fail; 984 } 985 986 sc->ste_btag = rman_get_bustag(sc->ste_res); 987 sc->ste_bhandle = rman_get_bushandle(sc->ste_res); 988 989 rid = 0; 990 sc->ste_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 991 RF_SHAREABLE | RF_ACTIVE); 992 993 if (sc->ste_irq == NULL) { 994 printf("ste%d: couldn't map interrupt\n", unit); 995 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res); 996 error = ENXIO; 997 goto fail; 998 } 999 1000 error = bus_setup_intr(dev, sc->ste_irq, INTR_TYPE_NET, 1001 ste_intr, sc, &sc->ste_intrhand); 1002 1003 if (error) { 1004 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq); 1005 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res); 1006 printf("ste%d: couldn't set up irq\n", unit); 1007 goto fail; 1008 } 1009 1010 callout_handle_init(&sc->ste_stat_ch); 1011 1012 /* Reset the adapter. */ 1013 ste_reset(sc); 1014 1015 /* 1016 * Get station address from the EEPROM. 1017 */ 1018 if (ste_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr, 1019 STE_EEADDR_NODE0, 3, 0)) { 1020 printf("ste%d: failed to read station address\n", unit); 1021 bus_teardown_intr(dev, sc->ste_irq, sc->ste_intrhand); 1022 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq); 1023 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res); 1024 error = ENXIO;; 1025 goto fail; 1026 } 1027 1028 /* 1029 * A Sundance chip was detected. Inform the world. 1030 */ 1031 printf("ste%d: Ethernet address: %6D\n", unit, 1032 sc->arpcom.ac_enaddr, ":"); 1033 1034 sc->ste_unit = unit; 1035 1036 /* Allocate the descriptor queues. */ 1037 sc->ste_ldata = contigmalloc(sizeof(struct ste_list_data), M_DEVBUF, 1038 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 1039 1040 if (sc->ste_ldata == NULL) { 1041 printf("ste%d: no memory for list buffers!\n", unit); 1042 bus_teardown_intr(dev, sc->ste_irq, sc->ste_intrhand); 1043 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq); 1044 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res); 1045 error = ENXIO; 1046 goto fail; 1047 } 1048 1049 bzero(sc->ste_ldata, sizeof(struct ste_list_data)); 1050 1051 /* Do MII setup. */ 1052 if (mii_phy_probe(dev, &sc->ste_miibus, 1053 ste_ifmedia_upd, ste_ifmedia_sts)) { 1054 printf("ste%d: MII without any phy!\n", sc->ste_unit); 1055 bus_teardown_intr(dev, sc->ste_irq, sc->ste_intrhand); 1056 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq); 1057 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res); 1058 contigfree(sc->ste_ldata, 1059 sizeof(struct ste_list_data), M_DEVBUF); 1060 error = ENXIO; 1061 goto fail; 1062 } 1063 1064 ifp = &sc->arpcom.ac_if; 1065 ifp->if_softc = sc; 1066 ifp->if_unit = unit; 1067 ifp->if_name = "ste"; 1068 ifp->if_mtu = ETHERMTU; 1069 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1070 ifp->if_ioctl = ste_ioctl; 1071 ifp->if_output = ether_output; 1072 ifp->if_start = ste_start; 1073 ifp->if_watchdog = ste_watchdog; 1074 ifp->if_init = ste_init; 1075 ifp->if_baudrate = 10000000; 1076 ifp->if_snd.ifq_maxlen = STE_TX_LIST_CNT - 1; 1077 1078 sc->ste_tx_thresh = STE_TXSTART_THRESH; 1079 1080 /* 1081 * Call MI attach routine. 1082 */ 1083 ether_ifattach(ifp, ETHER_BPF_SUPPORTED); 1084 1085 /* 1086 * Tell the upper layer(s) we support long frames. 1087 */ 1088 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1089 1090 fail: 1091 splx(s); 1092 return(error); 1093 } 1094 1095 static int ste_detach(dev) 1096 device_t dev; 1097 { 1098 struct ste_softc *sc; 1099 struct ifnet *ifp; 1100 int s; 1101 1102 s = splimp(); 1103 1104 sc = device_get_softc(dev); 1105 ifp = &sc->arpcom.ac_if; 1106 1107 ste_stop(sc); 1108 ether_ifdetach(ifp, ETHER_BPF_SUPPORTED); 1109 1110 bus_generic_detach(dev); 1111 device_delete_child(dev, sc->ste_miibus); 1112 1113 bus_teardown_intr(dev, sc->ste_irq, sc->ste_intrhand); 1114 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq); 1115 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res); 1116 1117 contigfree(sc->ste_ldata, sizeof(struct ste_list_data), M_DEVBUF); 1118 1119 splx(s); 1120 1121 return(0); 1122 } 1123 1124 static int ste_newbuf(sc, c, m) 1125 struct ste_softc *sc; 1126 struct ste_chain_onefrag *c; 1127 struct mbuf *m; 1128 { 1129 struct mbuf *m_new = NULL; 1130 1131 if (m == NULL) { 1132 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1133 if (m_new == NULL) 1134 return(ENOBUFS); 1135 MCLGET(m_new, M_DONTWAIT); 1136 if (!(m_new->m_flags & M_EXT)) { 1137 m_freem(m_new); 1138 return(ENOBUFS); 1139 } 1140 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1141 } else { 1142 m_new = m; 1143 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1144 m_new->m_data = m_new->m_ext.ext_buf; 1145 } 1146 1147 m_adj(m_new, ETHER_ALIGN); 1148 1149 c->ste_mbuf = m_new; 1150 c->ste_ptr->ste_status = 0; 1151 c->ste_ptr->ste_frag.ste_addr = vtophys(mtod(m_new, caddr_t)); 1152 c->ste_ptr->ste_frag.ste_len = (1536 + EVL_ENCAPLEN) | STE_FRAG_LAST; 1153 1154 return(0); 1155 } 1156 1157 static int ste_init_rx_list(sc) 1158 struct ste_softc *sc; 1159 { 1160 struct ste_chain_data *cd; 1161 struct ste_list_data *ld; 1162 int i; 1163 1164 cd = &sc->ste_cdata; 1165 ld = sc->ste_ldata; 1166 1167 for (i = 0; i < STE_RX_LIST_CNT; i++) { 1168 cd->ste_rx_chain[i].ste_ptr = &ld->ste_rx_list[i]; 1169 if (ste_newbuf(sc, &cd->ste_rx_chain[i], NULL) == ENOBUFS) 1170 return(ENOBUFS); 1171 if (i == (STE_RX_LIST_CNT - 1)) { 1172 cd->ste_rx_chain[i].ste_next = 1173 &cd->ste_rx_chain[0]; 1174 ld->ste_rx_list[i].ste_next = 1175 vtophys(&ld->ste_rx_list[0]); 1176 } else { 1177 cd->ste_rx_chain[i].ste_next = 1178 &cd->ste_rx_chain[i + 1]; 1179 ld->ste_rx_list[i].ste_next = 1180 vtophys(&ld->ste_rx_list[i + 1]); 1181 } 1182 ld->ste_rx_list[i].ste_status = 0; 1183 } 1184 1185 cd->ste_rx_head = &cd->ste_rx_chain[0]; 1186 1187 return(0); 1188 } 1189 1190 static void ste_init_tx_list(sc) 1191 struct ste_softc *sc; 1192 { 1193 struct ste_chain_data *cd; 1194 struct ste_list_data *ld; 1195 int i; 1196 1197 cd = &sc->ste_cdata; 1198 ld = sc->ste_ldata; 1199 for (i = 0; i < STE_TX_LIST_CNT; i++) { 1200 cd->ste_tx_chain[i].ste_ptr = &ld->ste_tx_list[i]; 1201 cd->ste_tx_chain[i].ste_ptr->ste_next = 0; 1202 cd->ste_tx_chain[i].ste_ptr->ste_ctl = 0; 1203 cd->ste_tx_chain[i].ste_phys = vtophys(&ld->ste_tx_list[i]); 1204 if (i == (STE_TX_LIST_CNT - 1)) 1205 cd->ste_tx_chain[i].ste_next = 1206 &cd->ste_tx_chain[0]; 1207 else 1208 cd->ste_tx_chain[i].ste_next = 1209 &cd->ste_tx_chain[i + 1]; 1210 if (i == 0) 1211 cd->ste_tx_chain[i].ste_prev = 1212 &cd->ste_tx_chain[STE_TX_LIST_CNT - 1]; 1213 else 1214 cd->ste_tx_chain[i].ste_prev = 1215 &cd->ste_tx_chain[i - 1]; 1216 } 1217 1218 cd->ste_tx_prod = 0; 1219 cd->ste_tx_cons = 0; 1220 cd->ste_tx_cnt = 0; 1221 1222 return; 1223 } 1224 1225 static void ste_init(xsc) 1226 void *xsc; 1227 { 1228 struct ste_softc *sc; 1229 int i, s; 1230 struct ifnet *ifp; 1231 struct mii_data *mii; 1232 1233 s = splimp(); 1234 1235 sc = xsc; 1236 ifp = &sc->arpcom.ac_if; 1237 mii = device_get_softc(sc->ste_miibus); 1238 1239 ste_stop(sc); 1240 1241 /* Init our MAC address */ 1242 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1243 CSR_WRITE_1(sc, STE_PAR0 + i, sc->arpcom.ac_enaddr[i]); 1244 } 1245 1246 /* Init RX list */ 1247 if (ste_init_rx_list(sc) == ENOBUFS) { 1248 printf("ste%d: initialization failed: no " 1249 "memory for RX buffers\n", sc->ste_unit); 1250 ste_stop(sc); 1251 splx(s); 1252 return; 1253 } 1254 1255 /* Set RX polling interval */ 1256 CSR_WRITE_1(sc, STE_RX_DMAPOLL_PERIOD, 1); 1257 1258 /* Init TX descriptors */ 1259 ste_init_tx_list(sc); 1260 1261 /* Set the TX freethresh value */ 1262 CSR_WRITE_1(sc, STE_TX_DMABURST_THRESH, STE_PACKET_SIZE >> 8); 1263 1264 /* Set the TX start threshold for best performance. */ 1265 CSR_WRITE_2(sc, STE_TX_STARTTHRESH, sc->ste_tx_thresh); 1266 1267 /* Set the TX reclaim threshold. */ 1268 CSR_WRITE_1(sc, STE_TX_RECLAIM_THRESH, (STE_PACKET_SIZE >> 4)); 1269 1270 /* Set up the RX filter. */ 1271 CSR_WRITE_1(sc, STE_RX_MODE, STE_RXMODE_UNICAST); 1272 1273 /* If we want promiscuous mode, set the allframes bit. */ 1274 if (ifp->if_flags & IFF_PROMISC) { 1275 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_PROMISC); 1276 } else { 1277 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_PROMISC); 1278 } 1279 1280 /* Set capture broadcast bit to accept broadcast frames. */ 1281 if (ifp->if_flags & IFF_BROADCAST) { 1282 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_BROADCAST); 1283 } else { 1284 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_BROADCAST); 1285 } 1286 1287 ste_setmulti(sc); 1288 1289 /* Load the address of the RX list. */ 1290 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_STALL); 1291 ste_wait(sc); 1292 CSR_WRITE_4(sc, STE_RX_DMALIST_PTR, 1293 vtophys(&sc->ste_ldata->ste_rx_list[0])); 1294 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL); 1295 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL); 1296 1297 /* Set TX polling interval (defer until we TX first packet */ 1298 CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 0); 1299 1300 /* Load address of the TX list */ 1301 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL); 1302 ste_wait(sc); 1303 CSR_WRITE_4(sc, STE_TX_DMALIST_PTR, 0); 1304 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 1305 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 1306 ste_wait(sc); 1307 sc->ste_tx_prev_idx=-1; 1308 1309 /* Enable receiver and transmitter */ 1310 CSR_WRITE_2(sc, STE_MACCTL0, 0); 1311 CSR_WRITE_2(sc, STE_MACCTL1, 0); 1312 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_TX_ENABLE); 1313 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_RX_ENABLE); 1314 1315 /* Enable stats counters. */ 1316 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_STATS_ENABLE); 1317 1318 /* Enable interrupts. */ 1319 CSR_WRITE_2(sc, STE_ISR, 0xFFFF); 1320 CSR_WRITE_2(sc, STE_IMR, STE_INTRS); 1321 1322 /* Accept VLAN length packets */ 1323 CSR_WRITE_2(sc, STE_MAX_FRAMELEN, ETHER_MAX_LEN + EVL_ENCAPLEN); 1324 1325 ste_ifmedia_upd(ifp); 1326 1327 ifp->if_flags |= IFF_RUNNING; 1328 ifp->if_flags &= ~IFF_OACTIVE; 1329 1330 splx(s); 1331 1332 sc->ste_stat_ch = timeout(ste_stats_update, sc, hz); 1333 1334 return; 1335 } 1336 1337 static void ste_stop(sc) 1338 struct ste_softc *sc; 1339 { 1340 int i; 1341 struct ifnet *ifp; 1342 1343 ifp = &sc->arpcom.ac_if; 1344 1345 untimeout(ste_stats_update, sc, sc->ste_stat_ch); 1346 1347 CSR_WRITE_2(sc, STE_IMR, 0); 1348 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_TX_DISABLE); 1349 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_RX_DISABLE); 1350 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_STATS_DISABLE); 1351 STE_SETBIT2(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL); 1352 STE_SETBIT2(sc, STE_DMACTL, STE_DMACTL_RXDMA_STALL); 1353 ste_wait(sc); 1354 /* 1355 * Try really hard to stop the RX engine or under heavy RX 1356 * data chip will write into de-allocated memory. 1357 */ 1358 ste_reset(sc); 1359 1360 sc->ste_link = 0; 1361 1362 for (i = 0; i < STE_RX_LIST_CNT; i++) { 1363 if (sc->ste_cdata.ste_rx_chain[i].ste_mbuf != NULL) { 1364 m_freem(sc->ste_cdata.ste_rx_chain[i].ste_mbuf); 1365 sc->ste_cdata.ste_rx_chain[i].ste_mbuf = NULL; 1366 } 1367 } 1368 1369 for (i = 0; i < STE_TX_LIST_CNT; i++) { 1370 if (sc->ste_cdata.ste_tx_chain[i].ste_mbuf != NULL) { 1371 m_freem(sc->ste_cdata.ste_tx_chain[i].ste_mbuf); 1372 sc->ste_cdata.ste_tx_chain[i].ste_mbuf = NULL; 1373 } 1374 } 1375 1376 bzero(sc->ste_ldata, sizeof(struct ste_list_data)); 1377 1378 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 1379 1380 return; 1381 } 1382 1383 static void ste_reset(sc) 1384 struct ste_softc *sc; 1385 { 1386 int i; 1387 1388 STE_SETBIT4(sc, STE_ASICCTL, 1389 STE_ASICCTL_GLOBAL_RESET|STE_ASICCTL_RX_RESET| 1390 STE_ASICCTL_TX_RESET|STE_ASICCTL_DMA_RESET| 1391 STE_ASICCTL_FIFO_RESET|STE_ASICCTL_NETWORK_RESET| 1392 STE_ASICCTL_AUTOINIT_RESET|STE_ASICCTL_HOST_RESET| 1393 STE_ASICCTL_EXTRESET_RESET); 1394 1395 DELAY(100000); 1396 1397 for (i = 0; i < STE_TIMEOUT; i++) { 1398 if (!(CSR_READ_4(sc, STE_ASICCTL) & STE_ASICCTL_RESET_BUSY)) 1399 break; 1400 } 1401 1402 if (i == STE_TIMEOUT) 1403 printf("ste%d: global reset never completed\n", sc->ste_unit); 1404 1405 return; 1406 } 1407 1408 static int ste_ioctl(ifp, command, data) 1409 struct ifnet *ifp; 1410 u_long command; 1411 caddr_t data; 1412 { 1413 struct ste_softc *sc; 1414 struct ifreq *ifr; 1415 struct mii_data *mii; 1416 int error = 0, s; 1417 1418 s = splimp(); 1419 1420 sc = ifp->if_softc; 1421 ifr = (struct ifreq *)data; 1422 1423 switch(command) { 1424 case SIOCSIFADDR: 1425 case SIOCGIFADDR: 1426 case SIOCSIFMTU: 1427 error = ether_ioctl(ifp, command, data); 1428 break; 1429 case SIOCSIFFLAGS: 1430 if (ifp->if_flags & IFF_UP) { 1431 if (ifp->if_flags & IFF_RUNNING && 1432 ifp->if_flags & IFF_PROMISC && 1433 !(sc->ste_if_flags & IFF_PROMISC)) { 1434 STE_SETBIT1(sc, STE_RX_MODE, 1435 STE_RXMODE_PROMISC); 1436 } else if (ifp->if_flags & IFF_RUNNING && 1437 !(ifp->if_flags & IFF_PROMISC) && 1438 sc->ste_if_flags & IFF_PROMISC) { 1439 STE_CLRBIT1(sc, STE_RX_MODE, 1440 STE_RXMODE_PROMISC); 1441 } 1442 if (!(ifp->if_flags & IFF_RUNNING)) { 1443 sc->ste_tx_thresh = STE_TXSTART_THRESH; 1444 ste_init(sc); 1445 } 1446 } else { 1447 if (ifp->if_flags & IFF_RUNNING) 1448 ste_stop(sc); 1449 } 1450 sc->ste_if_flags = ifp->if_flags; 1451 error = 0; 1452 break; 1453 case SIOCADDMULTI: 1454 case SIOCDELMULTI: 1455 ste_setmulti(sc); 1456 error = 0; 1457 break; 1458 case SIOCGIFMEDIA: 1459 case SIOCSIFMEDIA: 1460 mii = device_get_softc(sc->ste_miibus); 1461 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1462 break; 1463 default: 1464 error = EINVAL; 1465 break; 1466 } 1467 1468 splx(s); 1469 1470 return(error); 1471 } 1472 1473 static int ste_encap(sc, c, m_head) 1474 struct ste_softc *sc; 1475 struct ste_chain *c; 1476 struct mbuf *m_head; 1477 { 1478 int frag = 0; 1479 struct ste_frag *f = NULL; 1480 struct mbuf *m; 1481 struct ste_desc *d; 1482 int total_len = 0; 1483 1484 d = c->ste_ptr; 1485 d->ste_ctl = 0; 1486 1487 encap_retry: 1488 for (m = m_head, frag = 0; m != NULL; m = m->m_next) { 1489 if (m->m_len != 0) { 1490 if (frag == STE_MAXFRAGS) 1491 break; 1492 total_len += m->m_len; 1493 f = &d->ste_frags[frag]; 1494 f->ste_addr = vtophys(mtod(m, vm_offset_t)); 1495 f->ste_len = m->m_len; 1496 frag++; 1497 } 1498 } 1499 1500 if (m != NULL) { 1501 struct mbuf *mn; 1502 1503 /* 1504 * We ran out of segments. We have to recopy this 1505 * mbuf chain first. Bail out if we can't get the 1506 * new buffers. Code borrowed from if_fxp.c. 1507 */ 1508 MGETHDR(mn, M_DONTWAIT, MT_DATA); 1509 if (mn == NULL) { 1510 m_freem(m_head); 1511 return ENOMEM; 1512 } 1513 if (m_head->m_pkthdr.len > MHLEN) { 1514 MCLGET(mn, M_DONTWAIT); 1515 if ((mn->m_flags & M_EXT) == 0) { 1516 m_freem(mn); 1517 m_freem(m_head); 1518 return ENOMEM; 1519 } 1520 } 1521 m_copydata(m_head, 0, m_head->m_pkthdr.len, 1522 mtod(mn, caddr_t)); 1523 mn->m_pkthdr.len = mn->m_len = m_head->m_pkthdr.len; 1524 m_freem(m_head); 1525 m_head = mn; 1526 goto encap_retry; 1527 } 1528 1529 c->ste_mbuf = m_head; 1530 d->ste_frags[frag - 1].ste_len |= STE_FRAG_LAST; 1531 d->ste_ctl = 1; 1532 1533 return(0); 1534 } 1535 1536 static void ste_start(ifp) 1537 struct ifnet *ifp; 1538 { 1539 struct ste_softc *sc; 1540 struct mbuf *m_head = NULL; 1541 struct ste_chain *cur_tx = NULL; 1542 int idx; 1543 1544 sc = ifp->if_softc; 1545 1546 if (!sc->ste_link) 1547 return; 1548 1549 if (ifp->if_flags & IFF_OACTIVE) 1550 return; 1551 1552 idx = sc->ste_cdata.ste_tx_prod; 1553 1554 while(sc->ste_cdata.ste_tx_chain[idx].ste_mbuf == NULL) { 1555 1556 if ((STE_TX_LIST_CNT - sc->ste_cdata.ste_tx_cnt) < 3) { 1557 ifp->if_flags |= IFF_OACTIVE; 1558 break; 1559 } 1560 1561 IF_DEQUEUE(&ifp->if_snd, m_head); 1562 if (m_head == NULL) 1563 break; 1564 1565 cur_tx = &sc->ste_cdata.ste_tx_chain[idx]; 1566 1567 if (ste_encap(sc, cur_tx, m_head) != 0) 1568 break; 1569 1570 cur_tx->ste_ptr->ste_next = 0; 1571 1572 if(sc->ste_tx_prev_idx < 0){ 1573 cur_tx->ste_ptr->ste_ctl = STE_TXCTL_DMAINTR | 1; 1574 /* Load address of the TX list */ 1575 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL); 1576 ste_wait(sc); 1577 1578 CSR_WRITE_4(sc, STE_TX_DMALIST_PTR, 1579 vtophys(&sc->ste_ldata->ste_tx_list[0])); 1580 1581 /* Set TX polling interval to start TX engine */ 1582 CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 64); 1583 1584 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 1585 ste_wait(sc); 1586 }else{ 1587 cur_tx->ste_ptr->ste_ctl = STE_TXCTL_DMAINTR | 1; 1588 sc->ste_cdata.ste_tx_chain[ 1589 sc->ste_tx_prev_idx].ste_ptr->ste_next 1590 = cur_tx->ste_phys; 1591 } 1592 1593 sc->ste_tx_prev_idx=idx; 1594 1595 /* 1596 * If there's a BPF listener, bounce a copy of this frame 1597 * to him. 1598 */ 1599 if (ifp->if_bpf) 1600 bpf_mtap(ifp, cur_tx->ste_mbuf); 1601 1602 STE_INC(idx, STE_TX_LIST_CNT); 1603 sc->ste_cdata.ste_tx_cnt++; 1604 ifp->if_timer = 5; 1605 sc->ste_cdata.ste_tx_prod = idx; 1606 } 1607 1608 return; 1609 } 1610 1611 static void ste_watchdog(ifp) 1612 struct ifnet *ifp; 1613 { 1614 struct ste_softc *sc; 1615 1616 sc = ifp->if_softc; 1617 1618 ifp->if_oerrors++; 1619 printf("ste%d: watchdog timeout\n", sc->ste_unit); 1620 1621 ste_txeoc(sc); 1622 ste_txeof(sc); 1623 ste_rxeof(sc); 1624 ste_reset(sc); 1625 ste_init(sc); 1626 1627 if (ifp->if_snd.ifq_head != NULL) 1628 ste_start(ifp); 1629 1630 return; 1631 } 1632 1633 static void ste_shutdown(dev) 1634 device_t dev; 1635 { 1636 struct ste_softc *sc; 1637 1638 sc = device_get_softc(dev); 1639 1640 ste_stop(sc); 1641 1642 return; 1643 } 1644