1 /* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: src/sys/pci/if_ste.c,v 1.14.2.9 2003/02/05 22:03:57 mbr Exp $ 33 * $DragonFly: src/sys/dev/netif/ste/if_ste.c,v 1.33 2005/12/31 14:08:00 sephe Exp $ 34 */ 35 36 #include <sys/param.h> 37 #include <sys/systm.h> 38 #include <sys/sockio.h> 39 #include <sys/mbuf.h> 40 #include <sys/malloc.h> 41 #include <sys/kernel.h> 42 #include <sys/socket.h> 43 #include <sys/serialize.h> 44 #include <sys/thread2.h> 45 46 #include <net/if.h> 47 #include <net/ifq_var.h> 48 #include <net/if_arp.h> 49 #include <net/ethernet.h> 50 #include <net/if_dl.h> 51 #include <net/if_media.h> 52 #include <net/vlan/if_vlan_var.h> 53 54 #include <net/bpf.h> 55 56 #include <vm/vm.h> /* for vtophys */ 57 #include <vm/pmap.h> /* for vtophys */ 58 #include <machine/bus_memio.h> 59 #include <machine/bus_pio.h> 60 #include <machine/bus.h> 61 #include <machine/resource.h> 62 #include <sys/bus.h> 63 #include <sys/rman.h> 64 65 #include "../mii_layer/mii.h" 66 #include "../mii_layer/miivar.h" 67 68 #include <bus/pci/pcireg.h> 69 #include <bus/pci/pcivar.h> 70 71 /* "controller miibus0" required. See GENERIC if you get errors here. */ 72 #include "miibus_if.h" 73 74 #define STE_USEIOSPACE 75 76 #include "if_stereg.h" 77 78 /* 79 * Various supported device vendors/types and their names. 80 */ 81 static struct ste_type ste_devs[] = { 82 { ST_VENDORID, ST_DEVICEID_ST201, "Sundance ST201 10/100BaseTX" }, 83 { DL_VENDORID, DL_DEVICEID_550TX, "D-Link DFE-550TX 10/100BaseTX" }, 84 { 0, 0, NULL } 85 }; 86 87 static int ste_probe (device_t); 88 static int ste_attach (device_t); 89 static int ste_detach (device_t); 90 static void ste_init (void *); 91 static void ste_intr (void *); 92 static void ste_rxeof (struct ste_softc *); 93 static void ste_txeoc (struct ste_softc *); 94 static void ste_txeof (struct ste_softc *); 95 static void ste_stats_update (void *); 96 static void ste_stop (struct ste_softc *); 97 static void ste_reset (struct ste_softc *); 98 static int ste_ioctl (struct ifnet *, u_long, caddr_t, 99 struct ucred *); 100 static int ste_encap (struct ste_softc *, struct ste_chain *, 101 struct mbuf *); 102 static void ste_start (struct ifnet *); 103 static void ste_watchdog (struct ifnet *); 104 static void ste_shutdown (device_t); 105 static int ste_newbuf (struct ste_softc *, 106 struct ste_chain_onefrag *, 107 struct mbuf *); 108 static int ste_ifmedia_upd (struct ifnet *); 109 static void ste_ifmedia_sts (struct ifnet *, struct ifmediareq *); 110 111 static void ste_mii_sync (struct ste_softc *); 112 static void ste_mii_send (struct ste_softc *, u_int32_t, int); 113 static int ste_mii_readreg (struct ste_softc *, 114 struct ste_mii_frame *); 115 static int ste_mii_writereg (struct ste_softc *, 116 struct ste_mii_frame *); 117 static int ste_miibus_readreg (device_t, int, int); 118 static int ste_miibus_writereg (device_t, int, int, int); 119 static void ste_miibus_statchg (device_t); 120 121 static int ste_eeprom_wait (struct ste_softc *); 122 static int ste_read_eeprom (struct ste_softc *, caddr_t, int, 123 int, int); 124 static void ste_wait (struct ste_softc *); 125 static void ste_setmulti (struct ste_softc *); 126 static int ste_init_rx_list (struct ste_softc *); 127 static void ste_init_tx_list (struct ste_softc *); 128 129 #ifdef STE_USEIOSPACE 130 #define STE_RES SYS_RES_IOPORT 131 #define STE_RID STE_PCI_LOIO 132 #else 133 #define STE_RES SYS_RES_MEMORY 134 #define STE_RID STE_PCI_LOMEM 135 #endif 136 137 static device_method_t ste_methods[] = { 138 /* Device interface */ 139 DEVMETHOD(device_probe, ste_probe), 140 DEVMETHOD(device_attach, ste_attach), 141 DEVMETHOD(device_detach, ste_detach), 142 DEVMETHOD(device_shutdown, ste_shutdown), 143 144 /* bus interface */ 145 DEVMETHOD(bus_print_child, bus_generic_print_child), 146 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 147 148 /* MII interface */ 149 DEVMETHOD(miibus_readreg, ste_miibus_readreg), 150 DEVMETHOD(miibus_writereg, ste_miibus_writereg), 151 DEVMETHOD(miibus_statchg, ste_miibus_statchg), 152 153 { 0, 0 } 154 }; 155 156 static driver_t ste_driver = { 157 "ste", 158 ste_methods, 159 sizeof(struct ste_softc) 160 }; 161 162 static devclass_t ste_devclass; 163 164 DECLARE_DUMMY_MODULE(if_ste); 165 DRIVER_MODULE(if_ste, pci, ste_driver, ste_devclass, 0, 0); 166 DRIVER_MODULE(miibus, ste, miibus_driver, miibus_devclass, 0, 0); 167 168 #define STE_SETBIT4(sc, reg, x) \ 169 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | x) 170 171 #define STE_CLRBIT4(sc, reg, x) \ 172 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~x) 173 174 #define STE_SETBIT2(sc, reg, x) \ 175 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) | x) 176 177 #define STE_CLRBIT2(sc, reg, x) \ 178 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) & ~x) 179 180 #define STE_SETBIT1(sc, reg, x) \ 181 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | x) 182 183 #define STE_CLRBIT1(sc, reg, x) \ 184 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~x) 185 186 187 #define MII_SET(x) STE_SETBIT1(sc, STE_PHYCTL, x) 188 #define MII_CLR(x) STE_CLRBIT1(sc, STE_PHYCTL, x) 189 190 /* 191 * Sync the PHYs by setting data bit and strobing the clock 32 times. 192 */ 193 static void 194 ste_mii_sync(struct ste_softc *sc) 195 { 196 int i; 197 198 MII_SET(STE_PHYCTL_MDIR|STE_PHYCTL_MDATA); 199 200 for (i = 0; i < 32; i++) { 201 MII_SET(STE_PHYCTL_MCLK); 202 DELAY(1); 203 MII_CLR(STE_PHYCTL_MCLK); 204 DELAY(1); 205 } 206 207 return; 208 } 209 210 /* 211 * Clock a series of bits through the MII. 212 */ 213 static void 214 ste_mii_send(struct ste_softc *sc, u_int32_t bits, int cnt) 215 { 216 int i; 217 218 MII_CLR(STE_PHYCTL_MCLK); 219 220 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 221 if (bits & i) { 222 MII_SET(STE_PHYCTL_MDATA); 223 } else { 224 MII_CLR(STE_PHYCTL_MDATA); 225 } 226 DELAY(1); 227 MII_CLR(STE_PHYCTL_MCLK); 228 DELAY(1); 229 MII_SET(STE_PHYCTL_MCLK); 230 } 231 } 232 233 /* 234 * Read an PHY register through the MII. 235 */ 236 static int 237 ste_mii_readreg(struct ste_softc *sc, struct ste_mii_frame *frame) 238 { 239 int i, ack; 240 241 /* 242 * Set up frame for RX. 243 */ 244 frame->mii_stdelim = STE_MII_STARTDELIM; 245 frame->mii_opcode = STE_MII_READOP; 246 frame->mii_turnaround = 0; 247 frame->mii_data = 0; 248 249 CSR_WRITE_2(sc, STE_PHYCTL, 0); 250 /* 251 * Turn on data xmit. 252 */ 253 MII_SET(STE_PHYCTL_MDIR); 254 255 ste_mii_sync(sc); 256 257 /* 258 * Send command/address info. 259 */ 260 ste_mii_send(sc, frame->mii_stdelim, 2); 261 ste_mii_send(sc, frame->mii_opcode, 2); 262 ste_mii_send(sc, frame->mii_phyaddr, 5); 263 ste_mii_send(sc, frame->mii_regaddr, 5); 264 265 /* Turn off xmit. */ 266 MII_CLR(STE_PHYCTL_MDIR); 267 268 /* Idle bit */ 269 MII_CLR((STE_PHYCTL_MCLK|STE_PHYCTL_MDATA)); 270 DELAY(1); 271 MII_SET(STE_PHYCTL_MCLK); 272 DELAY(1); 273 274 /* Check for ack */ 275 MII_CLR(STE_PHYCTL_MCLK); 276 DELAY(1); 277 ack = CSR_READ_2(sc, STE_PHYCTL) & STE_PHYCTL_MDATA; 278 MII_SET(STE_PHYCTL_MCLK); 279 DELAY(1); 280 281 /* 282 * Now try reading data bits. If the ack failed, we still 283 * need to clock through 16 cycles to keep the PHY(s) in sync. 284 */ 285 if (ack) { 286 for(i = 0; i < 16; i++) { 287 MII_CLR(STE_PHYCTL_MCLK); 288 DELAY(1); 289 MII_SET(STE_PHYCTL_MCLK); 290 DELAY(1); 291 } 292 goto fail; 293 } 294 295 for (i = 0x8000; i; i >>= 1) { 296 MII_CLR(STE_PHYCTL_MCLK); 297 DELAY(1); 298 if (!ack) { 299 if (CSR_READ_2(sc, STE_PHYCTL) & STE_PHYCTL_MDATA) 300 frame->mii_data |= i; 301 DELAY(1); 302 } 303 MII_SET(STE_PHYCTL_MCLK); 304 DELAY(1); 305 } 306 307 fail: 308 309 MII_CLR(STE_PHYCTL_MCLK); 310 DELAY(1); 311 MII_SET(STE_PHYCTL_MCLK); 312 DELAY(1); 313 314 if (ack) 315 return(1); 316 return(0); 317 } 318 319 /* 320 * Write to a PHY register through the MII. 321 */ 322 static int 323 ste_mii_writereg(struct ste_softc *sc, struct ste_mii_frame *frame) 324 { 325 /* 326 * Set up frame for TX. 327 */ 328 329 frame->mii_stdelim = STE_MII_STARTDELIM; 330 frame->mii_opcode = STE_MII_WRITEOP; 331 frame->mii_turnaround = STE_MII_TURNAROUND; 332 333 /* 334 * Turn on data output. 335 */ 336 MII_SET(STE_PHYCTL_MDIR); 337 338 ste_mii_sync(sc); 339 340 ste_mii_send(sc, frame->mii_stdelim, 2); 341 ste_mii_send(sc, frame->mii_opcode, 2); 342 ste_mii_send(sc, frame->mii_phyaddr, 5); 343 ste_mii_send(sc, frame->mii_regaddr, 5); 344 ste_mii_send(sc, frame->mii_turnaround, 2); 345 ste_mii_send(sc, frame->mii_data, 16); 346 347 /* Idle bit. */ 348 MII_SET(STE_PHYCTL_MCLK); 349 DELAY(1); 350 MII_CLR(STE_PHYCTL_MCLK); 351 DELAY(1); 352 353 /* 354 * Turn off xmit. 355 */ 356 MII_CLR(STE_PHYCTL_MDIR); 357 358 return(0); 359 } 360 361 static int 362 ste_miibus_readreg(device_t dev, int phy, int reg) 363 { 364 struct ste_softc *sc; 365 struct ste_mii_frame frame; 366 367 sc = device_get_softc(dev); 368 369 if ( sc->ste_one_phy && phy != 0 ) 370 return (0); 371 372 bzero((char *)&frame, sizeof(frame)); 373 374 frame.mii_phyaddr = phy; 375 frame.mii_regaddr = reg; 376 ste_mii_readreg(sc, &frame); 377 378 return(frame.mii_data); 379 } 380 381 static int 382 ste_miibus_writereg(device_t dev, int phy, int reg, int data) 383 { 384 struct ste_softc *sc; 385 struct ste_mii_frame frame; 386 387 sc = device_get_softc(dev); 388 bzero((char *)&frame, sizeof(frame)); 389 390 frame.mii_phyaddr = phy; 391 frame.mii_regaddr = reg; 392 frame.mii_data = data; 393 394 ste_mii_writereg(sc, &frame); 395 396 return(0); 397 } 398 399 static void 400 ste_miibus_statchg(device_t dev) 401 { 402 struct ste_softc *sc; 403 struct mii_data *mii; 404 int i; 405 406 sc = device_get_softc(dev); 407 mii = device_get_softc(sc->ste_miibus); 408 409 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 410 STE_SETBIT2(sc, STE_MACCTL0, STE_MACCTL0_FULLDUPLEX); 411 } else { 412 STE_CLRBIT2(sc, STE_MACCTL0, STE_MACCTL0_FULLDUPLEX); 413 } 414 415 STE_SETBIT4(sc, STE_ASICCTL,STE_ASICCTL_RX_RESET | 416 STE_ASICCTL_TX_RESET); 417 for (i = 0; i < STE_TIMEOUT; i++) { 418 if (!(CSR_READ_4(sc, STE_ASICCTL) & STE_ASICCTL_RESET_BUSY)) 419 break; 420 } 421 if (i == STE_TIMEOUT) 422 if_printf(&sc->arpcom.ac_if, "rx reset never completed\n"); 423 424 return; 425 } 426 427 static int 428 ste_ifmedia_upd(struct ifnet *ifp) 429 { 430 struct ste_softc *sc; 431 struct mii_data *mii; 432 433 sc = ifp->if_softc; 434 mii = device_get_softc(sc->ste_miibus); 435 sc->ste_link = 0; 436 if (mii->mii_instance) { 437 struct mii_softc *miisc; 438 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 439 miisc = LIST_NEXT(miisc, mii_list)) 440 mii_phy_reset(miisc); 441 } 442 mii_mediachg(mii); 443 444 return(0); 445 } 446 447 static void 448 ste_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 449 { 450 struct ste_softc *sc; 451 struct mii_data *mii; 452 453 sc = ifp->if_softc; 454 mii = device_get_softc(sc->ste_miibus); 455 456 mii_pollstat(mii); 457 ifmr->ifm_active = mii->mii_media_active; 458 ifmr->ifm_status = mii->mii_media_status; 459 460 return; 461 } 462 463 static void 464 ste_wait(struct ste_softc *sc) 465 { 466 int i; 467 468 for (i = 0; i < STE_TIMEOUT; i++) { 469 if (!(CSR_READ_4(sc, STE_DMACTL) & STE_DMACTL_DMA_HALTINPROG)) 470 break; 471 } 472 473 if (i == STE_TIMEOUT) 474 if_printf(&sc->arpcom.ac_if, "command never completed!\n"); 475 476 return; 477 } 478 479 /* 480 * The EEPROM is slow: give it time to come ready after issuing 481 * it a command. 482 */ 483 static int 484 ste_eeprom_wait(struct ste_softc *sc) 485 { 486 int i; 487 488 DELAY(1000); 489 490 for (i = 0; i < 100; i++) { 491 if (CSR_READ_2(sc, STE_EEPROM_CTL) & STE_EECTL_BUSY) 492 DELAY(1000); 493 else 494 break; 495 } 496 497 if (i == 100) { 498 if_printf(&sc->arpcom.ac_if, "eeprom failed to come ready\n"); 499 return(1); 500 } 501 502 return(0); 503 } 504 505 /* 506 * Read a sequence of words from the EEPROM. Note that ethernet address 507 * data is stored in the EEPROM in network byte order. 508 */ 509 static int 510 ste_read_eeprom(struct ste_softc *sc, caddr_t dest, int off, int cnt, int swap) 511 { 512 int err = 0, i; 513 u_int16_t word = 0, *ptr; 514 515 if (ste_eeprom_wait(sc)) 516 return(1); 517 518 for (i = 0; i < cnt; i++) { 519 CSR_WRITE_2(sc, STE_EEPROM_CTL, STE_EEOPCODE_READ | (off + i)); 520 err = ste_eeprom_wait(sc); 521 if (err) 522 break; 523 word = CSR_READ_2(sc, STE_EEPROM_DATA); 524 ptr = (u_int16_t *)(dest + (i * 2)); 525 if (swap) 526 *ptr = ntohs(word); 527 else 528 *ptr = word; 529 } 530 531 return(err ? 1 : 0); 532 } 533 534 static void 535 ste_setmulti(struct ste_softc *sc) 536 { 537 struct ifnet *ifp; 538 int h = 0; 539 u_int32_t hashes[2] = { 0, 0 }; 540 struct ifmultiaddr *ifma; 541 542 ifp = &sc->arpcom.ac_if; 543 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 544 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_ALLMULTI); 545 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_MULTIHASH); 546 return; 547 } 548 549 /* first, zot all the existing hash bits */ 550 CSR_WRITE_2(sc, STE_MAR0, 0); 551 CSR_WRITE_2(sc, STE_MAR1, 0); 552 CSR_WRITE_2(sc, STE_MAR2, 0); 553 CSR_WRITE_2(sc, STE_MAR3, 0); 554 555 /* now program new ones */ 556 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 557 if (ifma->ifma_addr->sa_family != AF_LINK) 558 continue; 559 h = ether_crc32_be( 560 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 561 ETHER_ADDR_LEN) & 0x3f; 562 if (h < 32) 563 hashes[0] |= (1 << h); 564 else 565 hashes[1] |= (1 << (h - 32)); 566 } 567 568 CSR_WRITE_2(sc, STE_MAR0, hashes[0] & 0xFFFF); 569 CSR_WRITE_2(sc, STE_MAR1, (hashes[0] >> 16) & 0xFFFF); 570 CSR_WRITE_2(sc, STE_MAR2, hashes[1] & 0xFFFF); 571 CSR_WRITE_2(sc, STE_MAR3, (hashes[1] >> 16) & 0xFFFF); 572 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_ALLMULTI); 573 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_MULTIHASH); 574 575 return; 576 } 577 578 static void 579 ste_intr(void *xsc) 580 { 581 struct ste_softc *sc; 582 struct ifnet *ifp; 583 u_int16_t status; 584 585 sc = xsc; 586 ifp = &sc->arpcom.ac_if; 587 588 /* See if this is really our interrupt. */ 589 if (!(CSR_READ_2(sc, STE_ISR) & STE_ISR_INTLATCH)) 590 return; 591 592 for (;;) { 593 status = CSR_READ_2(sc, STE_ISR_ACK); 594 595 if (!(status & STE_INTRS)) 596 break; 597 598 if (status & STE_ISR_RX_DMADONE) 599 ste_rxeof(sc); 600 601 if (status & STE_ISR_TX_DMADONE) 602 ste_txeof(sc); 603 604 if (status & STE_ISR_TX_DONE) 605 ste_txeoc(sc); 606 607 if (status & STE_ISR_STATS_OFLOW) { 608 callout_stop(&sc->ste_stat_timer); 609 ste_stats_update(sc); 610 } 611 612 if (status & STE_ISR_LINKEVENT) 613 mii_pollstat(device_get_softc(sc->ste_miibus)); 614 615 if (status & STE_ISR_HOSTERR) { 616 ste_reset(sc); 617 ste_init(sc); 618 } 619 } 620 621 /* Re-enable interrupts */ 622 CSR_WRITE_2(sc, STE_IMR, STE_INTRS); 623 624 if (!ifq_is_empty(&ifp->if_snd)) 625 ste_start(ifp); 626 627 return; 628 } 629 630 /* 631 * A frame has been uploaded: pass the resulting mbuf chain up to 632 * the higher level protocols. 633 */ 634 static void 635 ste_rxeof(struct ste_softc *sc) 636 { 637 struct mbuf *m; 638 struct ifnet *ifp; 639 struct ste_chain_onefrag *cur_rx; 640 int total_len = 0, count=0; 641 u_int32_t rxstat; 642 643 ifp = &sc->arpcom.ac_if; 644 645 while((rxstat = sc->ste_cdata.ste_rx_head->ste_ptr->ste_status) 646 & STE_RXSTAT_DMADONE) { 647 if ((STE_RX_LIST_CNT - count) < 3) { 648 break; 649 } 650 651 cur_rx = sc->ste_cdata.ste_rx_head; 652 sc->ste_cdata.ste_rx_head = cur_rx->ste_next; 653 654 /* 655 * If an error occurs, update stats, clear the 656 * status word and leave the mbuf cluster in place: 657 * it should simply get re-used next time this descriptor 658 * comes up in the ring. 659 */ 660 if (rxstat & STE_RXSTAT_FRAME_ERR) { 661 ifp->if_ierrors++; 662 cur_rx->ste_ptr->ste_status = 0; 663 continue; 664 } 665 666 /* 667 * If there error bit was not set, the upload complete 668 * bit should be set which means we have a valid packet. 669 * If not, something truly strange has happened. 670 */ 671 if (!(rxstat & STE_RXSTAT_DMADONE)) { 672 if_printf(ifp, "bad receive status -- packet dropped"); 673 ifp->if_ierrors++; 674 cur_rx->ste_ptr->ste_status = 0; 675 continue; 676 } 677 678 /* No errors; receive the packet. */ 679 m = cur_rx->ste_mbuf; 680 total_len = cur_rx->ste_ptr->ste_status & STE_RXSTAT_FRAMELEN; 681 682 /* 683 * Try to conjure up a new mbuf cluster. If that 684 * fails, it means we have an out of memory condition and 685 * should leave the buffer in place and continue. This will 686 * result in a lost packet, but there's little else we 687 * can do in this situation. 688 */ 689 if (ste_newbuf(sc, cur_rx, NULL) == ENOBUFS) { 690 ifp->if_ierrors++; 691 cur_rx->ste_ptr->ste_status = 0; 692 continue; 693 } 694 695 ifp->if_ipackets++; 696 m->m_pkthdr.rcvif = ifp; 697 m->m_pkthdr.len = m->m_len = total_len; 698 699 ifp->if_input(ifp, m); 700 701 cur_rx->ste_ptr->ste_status = 0; 702 count++; 703 } 704 705 return; 706 } 707 708 static void 709 ste_txeoc(struct ste_softc *sc) 710 { 711 u_int8_t txstat; 712 struct ifnet *ifp; 713 714 ifp = &sc->arpcom.ac_if; 715 716 while ((txstat = CSR_READ_1(sc, STE_TX_STATUS)) & 717 STE_TXSTATUS_TXDONE) { 718 if (txstat & STE_TXSTATUS_UNDERRUN || 719 txstat & STE_TXSTATUS_EXCESSCOLLS || 720 txstat & STE_TXSTATUS_RECLAIMERR) { 721 ifp->if_oerrors++; 722 if_printf(ifp, "transmission error: %x\n", txstat); 723 724 ste_reset(sc); 725 ste_init(sc); 726 727 if (txstat & STE_TXSTATUS_UNDERRUN && 728 sc->ste_tx_thresh < STE_PACKET_SIZE) { 729 sc->ste_tx_thresh += STE_MIN_FRAMELEN; 730 if_printf(ifp, "tx underrun, increasing tx" 731 " start threshold to %d bytes\n", 732 sc->ste_tx_thresh); 733 } 734 CSR_WRITE_2(sc, STE_TX_STARTTHRESH, sc->ste_tx_thresh); 735 CSR_WRITE_2(sc, STE_TX_RECLAIM_THRESH, 736 (STE_PACKET_SIZE >> 4)); 737 } 738 ste_init(sc); 739 CSR_WRITE_2(sc, STE_TX_STATUS, txstat); 740 } 741 742 return; 743 } 744 745 static void 746 ste_txeof(struct ste_softc *sc) 747 { 748 struct ste_chain *cur_tx = NULL; 749 struct ifnet *ifp; 750 int idx; 751 752 ifp = &sc->arpcom.ac_if; 753 754 idx = sc->ste_cdata.ste_tx_cons; 755 while(idx != sc->ste_cdata.ste_tx_prod) { 756 cur_tx = &sc->ste_cdata.ste_tx_chain[idx]; 757 758 if (!(cur_tx->ste_ptr->ste_ctl & STE_TXCTL_DMADONE)) 759 break; 760 761 if (cur_tx->ste_mbuf != NULL) { 762 m_freem(cur_tx->ste_mbuf); 763 cur_tx->ste_mbuf = NULL; 764 } 765 766 ifp->if_opackets++; 767 768 sc->ste_cdata.ste_tx_cnt--; 769 STE_INC(idx, STE_TX_LIST_CNT); 770 ifp->if_timer = 0; 771 } 772 773 sc->ste_cdata.ste_tx_cons = idx; 774 775 if (cur_tx != NULL) 776 ifp->if_flags &= ~IFF_OACTIVE; 777 778 return; 779 } 780 781 static void 782 ste_stats_update(void *xsc) 783 { 784 struct ste_softc *sc; 785 struct ifnet *ifp; 786 struct mii_data *mii; 787 788 sc = xsc; 789 ifp = &sc->arpcom.ac_if; 790 mii = device_get_softc(sc->ste_miibus); 791 792 lwkt_serialize_enter(ifp->if_serializer); 793 794 ifp->if_collisions += CSR_READ_1(sc, STE_LATE_COLLS) 795 + CSR_READ_1(sc, STE_MULTI_COLLS) 796 + CSR_READ_1(sc, STE_SINGLE_COLLS); 797 798 if (!sc->ste_link) { 799 mii_pollstat(mii); 800 if (mii->mii_media_status & IFM_ACTIVE && 801 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 802 sc->ste_link++; 803 /* 804 * we don't get a call-back on re-init so do it 805 * otherwise we get stuck in the wrong link state 806 */ 807 ste_miibus_statchg(sc->ste_dev); 808 if (!ifq_is_empty(&ifp->if_snd)) 809 ste_start(ifp); 810 } 811 } 812 813 callout_reset(&sc->ste_stat_timer, hz, ste_stats_update, sc); 814 lwkt_serialize_exit(ifp->if_serializer); 815 } 816 817 818 /* 819 * Probe for a Sundance ST201 chip. Check the PCI vendor and device 820 * IDs against our list and return a device name if we find a match. 821 */ 822 static int 823 ste_probe(device_t dev) 824 { 825 struct ste_type *t; 826 827 t = ste_devs; 828 829 while(t->ste_name != NULL) { 830 if ((pci_get_vendor(dev) == t->ste_vid) && 831 (pci_get_device(dev) == t->ste_did)) { 832 device_set_desc(dev, t->ste_name); 833 return(0); 834 } 835 t++; 836 } 837 838 return(ENXIO); 839 } 840 841 /* 842 * Attach the interface. Allocate softc structures, do ifmedia 843 * setup and ethernet/BPF attach. 844 */ 845 static int 846 ste_attach(device_t dev) 847 { 848 struct ste_softc *sc; 849 struct ifnet *ifp; 850 int error = 0, rid; 851 uint8_t eaddr[ETHER_ADDR_LEN]; 852 853 sc = device_get_softc(dev); 854 sc->ste_dev = dev; 855 856 /* 857 * Only use one PHY since this chip reports multiple 858 * Note on the DFE-550 the PHY is at 1 on the DFE-580 859 * it is at 0 & 1. It is rev 0x12. 860 */ 861 if (pci_get_vendor(dev) == DL_VENDORID && 862 pci_get_device(dev) == DL_DEVICEID_550TX && 863 pci_get_revid(dev) == 0x12 ) 864 sc->ste_one_phy = 1; 865 866 /* 867 * Handle power management nonsense. 868 */ 869 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 870 u_int32_t iobase, membase, irq; 871 872 /* Save important PCI config data. */ 873 iobase = pci_read_config(dev, STE_PCI_LOIO, 4); 874 membase = pci_read_config(dev, STE_PCI_LOMEM, 4); 875 irq = pci_read_config(dev, STE_PCI_INTLINE, 4); 876 877 /* Reset the power state. */ 878 device_printf(dev, "chip is in D%d power mode " 879 "-- setting to D0\n", pci_get_powerstate(dev)); 880 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 881 882 /* Restore PCI config data. */ 883 pci_write_config(dev, STE_PCI_LOIO, iobase, 4); 884 pci_write_config(dev, STE_PCI_LOMEM, membase, 4); 885 pci_write_config(dev, STE_PCI_INTLINE, irq, 4); 886 } 887 888 /* 889 * Map control/status registers. 890 */ 891 pci_enable_busmaster(dev); 892 893 rid = STE_RID; 894 sc->ste_res = bus_alloc_resource_any(dev, STE_RES, &rid, RF_ACTIVE); 895 896 if (sc->ste_res == NULL) { 897 device_printf(dev, "couldn't map ports/memory\n"); 898 error = ENXIO; 899 goto fail; 900 } 901 902 sc->ste_btag = rman_get_bustag(sc->ste_res); 903 sc->ste_bhandle = rman_get_bushandle(sc->ste_res); 904 905 rid = 0; 906 sc->ste_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 907 RF_SHAREABLE | RF_ACTIVE); 908 909 if (sc->ste_irq == NULL) { 910 device_printf(dev, "couldn't map interrupt\n"); 911 error = ENXIO; 912 goto fail; 913 } 914 915 callout_init(&sc->ste_stat_timer); 916 917 ifp = &sc->arpcom.ac_if; 918 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 919 920 /* Reset the adapter. */ 921 ste_reset(sc); 922 923 /* 924 * Get station address from the EEPROM. 925 */ 926 if (ste_read_eeprom(sc, eaddr, STE_EEADDR_NODE0, 3, 0)) { 927 device_printf(dev, "failed to read station address\n"); 928 error = ENXIO; 929 goto fail; 930 } 931 932 /* Allocate the descriptor queues. */ 933 sc->ste_ldata = contigmalloc(sizeof(struct ste_list_data), M_DEVBUF, 934 M_WAITOK, 0, 0xffffffff, PAGE_SIZE, 0); 935 936 if (sc->ste_ldata == NULL) { 937 device_printf(dev, "no memory for list buffers!\n"); 938 error = ENXIO; 939 goto fail; 940 } 941 942 bzero(sc->ste_ldata, sizeof(struct ste_list_data)); 943 944 /* Do MII setup. */ 945 if (mii_phy_probe(dev, &sc->ste_miibus, 946 ste_ifmedia_upd, ste_ifmedia_sts)) { 947 device_printf(dev, "MII without any phy!\n"); 948 error = ENXIO; 949 goto fail; 950 } 951 952 ifp->if_softc = sc; 953 ifp->if_mtu = ETHERMTU; 954 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 955 ifp->if_ioctl = ste_ioctl; 956 ifp->if_start = ste_start; 957 ifp->if_watchdog = ste_watchdog; 958 ifp->if_init = ste_init; 959 ifp->if_baudrate = 10000000; 960 ifq_set_maxlen(&ifp->if_snd, STE_TX_LIST_CNT - 1); 961 ifq_set_ready(&ifp->if_snd); 962 963 sc->ste_tx_thresh = STE_TXSTART_THRESH; 964 965 /* 966 * Call MI attach routine. 967 */ 968 ether_ifattach(ifp, eaddr, NULL); 969 970 /* 971 * Tell the upper layer(s) we support long frames. 972 */ 973 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 974 975 error = bus_setup_intr(dev, sc->ste_irq, INTR_NETSAFE, 976 ste_intr, sc, &sc->ste_intrhand, 977 ifp->if_serializer); 978 if (error) { 979 device_printf(dev, "couldn't set up irq\n"); 980 ether_ifdetach(ifp); 981 goto fail; 982 } 983 984 return 0; 985 986 fail: 987 ste_detach(dev); 988 return(error); 989 } 990 991 static int 992 ste_detach(device_t dev) 993 { 994 struct ste_softc *sc = device_get_softc(dev); 995 struct ifnet *ifp = &sc->arpcom.ac_if; 996 997 if (device_is_attached(dev)) { 998 lwkt_serialize_enter(ifp->if_serializer); 999 ste_stop(sc); 1000 bus_teardown_intr(dev, sc->ste_irq, sc->ste_intrhand); 1001 lwkt_serialize_exit(ifp->if_serializer); 1002 1003 ether_ifdetach(ifp); 1004 } 1005 if (sc->ste_miibus != NULL) 1006 device_delete_child(dev, sc->ste_miibus); 1007 bus_generic_detach(dev); 1008 1009 if (sc->ste_irq != NULL) 1010 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq); 1011 if (sc->ste_res != NULL) 1012 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res); 1013 if (sc->ste_ldata != NULL) { 1014 contigfree(sc->ste_ldata, sizeof(struct ste_list_data), 1015 M_DEVBUF); 1016 } 1017 1018 return(0); 1019 } 1020 1021 static int 1022 ste_newbuf(struct ste_softc *sc, struct ste_chain_onefrag *c, 1023 struct mbuf *m) 1024 { 1025 struct mbuf *m_new = NULL; 1026 1027 if (m == NULL) { 1028 MGETHDR(m_new, MB_DONTWAIT, MT_DATA); 1029 if (m_new == NULL) 1030 return(ENOBUFS); 1031 MCLGET(m_new, MB_DONTWAIT); 1032 if (!(m_new->m_flags & M_EXT)) { 1033 m_freem(m_new); 1034 return(ENOBUFS); 1035 } 1036 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1037 } else { 1038 m_new = m; 1039 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1040 m_new->m_data = m_new->m_ext.ext_buf; 1041 } 1042 1043 m_adj(m_new, ETHER_ALIGN); 1044 1045 c->ste_mbuf = m_new; 1046 c->ste_ptr->ste_status = 0; 1047 c->ste_ptr->ste_frag.ste_addr = vtophys(mtod(m_new, caddr_t)); 1048 c->ste_ptr->ste_frag.ste_len = (1536 + EVL_ENCAPLEN) | STE_FRAG_LAST; 1049 1050 return(0); 1051 } 1052 1053 static int 1054 ste_init_rx_list(struct ste_softc *sc) 1055 { 1056 struct ste_chain_data *cd; 1057 struct ste_list_data *ld; 1058 int i; 1059 1060 cd = &sc->ste_cdata; 1061 ld = sc->ste_ldata; 1062 1063 for (i = 0; i < STE_RX_LIST_CNT; i++) { 1064 cd->ste_rx_chain[i].ste_ptr = &ld->ste_rx_list[i]; 1065 if (ste_newbuf(sc, &cd->ste_rx_chain[i], NULL) == ENOBUFS) 1066 return(ENOBUFS); 1067 if (i == (STE_RX_LIST_CNT - 1)) { 1068 cd->ste_rx_chain[i].ste_next = 1069 &cd->ste_rx_chain[0]; 1070 ld->ste_rx_list[i].ste_next = 1071 vtophys(&ld->ste_rx_list[0]); 1072 } else { 1073 cd->ste_rx_chain[i].ste_next = 1074 &cd->ste_rx_chain[i + 1]; 1075 ld->ste_rx_list[i].ste_next = 1076 vtophys(&ld->ste_rx_list[i + 1]); 1077 } 1078 ld->ste_rx_list[i].ste_status = 0; 1079 } 1080 1081 cd->ste_rx_head = &cd->ste_rx_chain[0]; 1082 1083 return(0); 1084 } 1085 1086 static void 1087 ste_init_tx_list(struct ste_softc *sc) 1088 { 1089 struct ste_chain_data *cd; 1090 struct ste_list_data *ld; 1091 int i; 1092 1093 cd = &sc->ste_cdata; 1094 ld = sc->ste_ldata; 1095 for (i = 0; i < STE_TX_LIST_CNT; i++) { 1096 cd->ste_tx_chain[i].ste_ptr = &ld->ste_tx_list[i]; 1097 cd->ste_tx_chain[i].ste_ptr->ste_next = 0; 1098 cd->ste_tx_chain[i].ste_ptr->ste_ctl = 0; 1099 cd->ste_tx_chain[i].ste_phys = vtophys(&ld->ste_tx_list[i]); 1100 if (i == (STE_TX_LIST_CNT - 1)) 1101 cd->ste_tx_chain[i].ste_next = 1102 &cd->ste_tx_chain[0]; 1103 else 1104 cd->ste_tx_chain[i].ste_next = 1105 &cd->ste_tx_chain[i + 1]; 1106 if (i == 0) 1107 cd->ste_tx_chain[i].ste_prev = 1108 &cd->ste_tx_chain[STE_TX_LIST_CNT - 1]; 1109 else 1110 cd->ste_tx_chain[i].ste_prev = 1111 &cd->ste_tx_chain[i - 1]; 1112 } 1113 1114 cd->ste_tx_prod = 0; 1115 cd->ste_tx_cons = 0; 1116 cd->ste_tx_cnt = 0; 1117 1118 return; 1119 } 1120 1121 static void 1122 ste_init(void *xsc) 1123 { 1124 struct ste_softc *sc; 1125 int i; 1126 struct ifnet *ifp; 1127 struct mii_data *mii; 1128 1129 sc = xsc; 1130 ifp = &sc->arpcom.ac_if; 1131 mii = device_get_softc(sc->ste_miibus); 1132 1133 ste_stop(sc); 1134 1135 /* Init our MAC address */ 1136 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1137 CSR_WRITE_1(sc, STE_PAR0 + i, sc->arpcom.ac_enaddr[i]); 1138 } 1139 1140 /* Init RX list */ 1141 if (ste_init_rx_list(sc) == ENOBUFS) { 1142 if_printf(ifp, "initialization failed: no " 1143 "memory for RX buffers\n"); 1144 ste_stop(sc); 1145 return; 1146 } 1147 1148 /* Set RX polling interval */ 1149 CSR_WRITE_1(sc, STE_RX_DMAPOLL_PERIOD, 1); 1150 1151 /* Init TX descriptors */ 1152 ste_init_tx_list(sc); 1153 1154 /* Set the TX freethresh value */ 1155 CSR_WRITE_1(sc, STE_TX_DMABURST_THRESH, STE_PACKET_SIZE >> 8); 1156 1157 /* Set the TX start threshold for best performance. */ 1158 CSR_WRITE_2(sc, STE_TX_STARTTHRESH, sc->ste_tx_thresh); 1159 1160 /* Set the TX reclaim threshold. */ 1161 CSR_WRITE_1(sc, STE_TX_RECLAIM_THRESH, (STE_PACKET_SIZE >> 4)); 1162 1163 /* Set up the RX filter. */ 1164 CSR_WRITE_1(sc, STE_RX_MODE, STE_RXMODE_UNICAST); 1165 1166 /* If we want promiscuous mode, set the allframes bit. */ 1167 if (ifp->if_flags & IFF_PROMISC) { 1168 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_PROMISC); 1169 } else { 1170 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_PROMISC); 1171 } 1172 1173 /* Set capture broadcast bit to accept broadcast frames. */ 1174 if (ifp->if_flags & IFF_BROADCAST) { 1175 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_BROADCAST); 1176 } else { 1177 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_BROADCAST); 1178 } 1179 1180 ste_setmulti(sc); 1181 1182 /* Load the address of the RX list. */ 1183 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_STALL); 1184 ste_wait(sc); 1185 CSR_WRITE_4(sc, STE_RX_DMALIST_PTR, 1186 vtophys(&sc->ste_ldata->ste_rx_list[0])); 1187 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL); 1188 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL); 1189 1190 /* Set TX polling interval (defer until we TX first packet */ 1191 CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 0); 1192 1193 /* Load address of the TX list */ 1194 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL); 1195 ste_wait(sc); 1196 CSR_WRITE_4(sc, STE_TX_DMALIST_PTR, 0); 1197 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 1198 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 1199 ste_wait(sc); 1200 sc->ste_tx_prev_idx=-1; 1201 1202 /* Enable receiver and transmitter */ 1203 CSR_WRITE_2(sc, STE_MACCTL0, 0); 1204 CSR_WRITE_2(sc, STE_MACCTL1, 0); 1205 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_TX_ENABLE); 1206 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_RX_ENABLE); 1207 1208 /* Enable stats counters. */ 1209 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_STATS_ENABLE); 1210 1211 /* Enable interrupts. */ 1212 CSR_WRITE_2(sc, STE_ISR, 0xFFFF); 1213 CSR_WRITE_2(sc, STE_IMR, STE_INTRS); 1214 1215 /* Accept VLAN length packets */ 1216 CSR_WRITE_2(sc, STE_MAX_FRAMELEN, ETHER_MAX_LEN + EVL_ENCAPLEN); 1217 1218 ste_ifmedia_upd(ifp); 1219 1220 ifp->if_flags |= IFF_RUNNING; 1221 ifp->if_flags &= ~IFF_OACTIVE; 1222 1223 callout_reset(&sc->ste_stat_timer, hz, ste_stats_update, sc); 1224 } 1225 1226 static void 1227 ste_stop(struct ste_softc *sc) 1228 { 1229 int i; 1230 struct ifnet *ifp; 1231 1232 ifp = &sc->arpcom.ac_if; 1233 1234 callout_stop(&sc->ste_stat_timer); 1235 1236 CSR_WRITE_2(sc, STE_IMR, 0); 1237 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_TX_DISABLE); 1238 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_RX_DISABLE); 1239 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_STATS_DISABLE); 1240 STE_SETBIT2(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL); 1241 STE_SETBIT2(sc, STE_DMACTL, STE_DMACTL_RXDMA_STALL); 1242 ste_wait(sc); 1243 /* 1244 * Try really hard to stop the RX engine or under heavy RX 1245 * data chip will write into de-allocated memory. 1246 */ 1247 ste_reset(sc); 1248 1249 sc->ste_link = 0; 1250 1251 for (i = 0; i < STE_RX_LIST_CNT; i++) { 1252 if (sc->ste_cdata.ste_rx_chain[i].ste_mbuf != NULL) { 1253 m_freem(sc->ste_cdata.ste_rx_chain[i].ste_mbuf); 1254 sc->ste_cdata.ste_rx_chain[i].ste_mbuf = NULL; 1255 } 1256 } 1257 1258 for (i = 0; i < STE_TX_LIST_CNT; i++) { 1259 if (sc->ste_cdata.ste_tx_chain[i].ste_mbuf != NULL) { 1260 m_freem(sc->ste_cdata.ste_tx_chain[i].ste_mbuf); 1261 sc->ste_cdata.ste_tx_chain[i].ste_mbuf = NULL; 1262 } 1263 } 1264 1265 bzero(sc->ste_ldata, sizeof(struct ste_list_data)); 1266 1267 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 1268 1269 return; 1270 } 1271 1272 static void 1273 ste_reset(struct ste_softc *sc) 1274 { 1275 int i; 1276 1277 STE_SETBIT4(sc, STE_ASICCTL, 1278 STE_ASICCTL_GLOBAL_RESET|STE_ASICCTL_RX_RESET| 1279 STE_ASICCTL_TX_RESET|STE_ASICCTL_DMA_RESET| 1280 STE_ASICCTL_FIFO_RESET|STE_ASICCTL_NETWORK_RESET| 1281 STE_ASICCTL_AUTOINIT_RESET|STE_ASICCTL_HOST_RESET| 1282 STE_ASICCTL_EXTRESET_RESET); 1283 1284 DELAY(100000); 1285 1286 for (i = 0; i < STE_TIMEOUT; i++) { 1287 if (!(CSR_READ_4(sc, STE_ASICCTL) & STE_ASICCTL_RESET_BUSY)) 1288 break; 1289 } 1290 1291 if (i == STE_TIMEOUT) 1292 if_printf(&sc->arpcom.ac_if, "global reset never completed\n"); 1293 1294 return; 1295 } 1296 1297 static int 1298 ste_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr) 1299 { 1300 struct ste_softc *sc; 1301 struct ifreq *ifr; 1302 struct mii_data *mii; 1303 int error = 0; 1304 1305 sc = ifp->if_softc; 1306 ifr = (struct ifreq *)data; 1307 1308 switch(command) { 1309 case SIOCSIFFLAGS: 1310 if (ifp->if_flags & IFF_UP) { 1311 if (ifp->if_flags & IFF_RUNNING && 1312 ifp->if_flags & IFF_PROMISC && 1313 !(sc->ste_if_flags & IFF_PROMISC)) { 1314 STE_SETBIT1(sc, STE_RX_MODE, 1315 STE_RXMODE_PROMISC); 1316 } else if (ifp->if_flags & IFF_RUNNING && 1317 !(ifp->if_flags & IFF_PROMISC) && 1318 sc->ste_if_flags & IFF_PROMISC) { 1319 STE_CLRBIT1(sc, STE_RX_MODE, 1320 STE_RXMODE_PROMISC); 1321 } 1322 if (!(ifp->if_flags & IFF_RUNNING)) { 1323 sc->ste_tx_thresh = STE_TXSTART_THRESH; 1324 ste_init(sc); 1325 } 1326 } else { 1327 if (ifp->if_flags & IFF_RUNNING) 1328 ste_stop(sc); 1329 } 1330 sc->ste_if_flags = ifp->if_flags; 1331 error = 0; 1332 break; 1333 case SIOCADDMULTI: 1334 case SIOCDELMULTI: 1335 ste_setmulti(sc); 1336 error = 0; 1337 break; 1338 case SIOCGIFMEDIA: 1339 case SIOCSIFMEDIA: 1340 mii = device_get_softc(sc->ste_miibus); 1341 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1342 break; 1343 default: 1344 error = ether_ioctl(ifp, command, data); 1345 break; 1346 } 1347 return(error); 1348 } 1349 1350 static int 1351 ste_encap(struct ste_softc *sc, struct ste_chain *c, struct mbuf *m_head) 1352 { 1353 int frag = 0; 1354 struct ste_frag *f = NULL; 1355 struct mbuf *m; 1356 struct ste_desc *d; 1357 int total_len = 0; 1358 1359 d = c->ste_ptr; 1360 d->ste_ctl = 0; 1361 1362 encap_retry: 1363 for (m = m_head, frag = 0; m != NULL; m = m->m_next) { 1364 if (m->m_len != 0) { 1365 if (frag == STE_MAXFRAGS) 1366 break; 1367 total_len += m->m_len; 1368 f = &d->ste_frags[frag]; 1369 f->ste_addr = vtophys(mtod(m, vm_offset_t)); 1370 f->ste_len = m->m_len; 1371 frag++; 1372 } 1373 } 1374 1375 if (m != NULL) { 1376 struct mbuf *mn; 1377 1378 /* 1379 * We ran out of segments. We have to recopy this 1380 * mbuf chain first. Bail out if we can't get the 1381 * new buffers. Code borrowed from if_fxp.c. 1382 */ 1383 MGETHDR(mn, MB_DONTWAIT, MT_DATA); 1384 if (mn == NULL) { 1385 m_freem(m_head); 1386 return ENOMEM; 1387 } 1388 if (m_head->m_pkthdr.len > MHLEN) { 1389 MCLGET(mn, MB_DONTWAIT); 1390 if ((mn->m_flags & M_EXT) == 0) { 1391 m_freem(mn); 1392 m_freem(m_head); 1393 return ENOMEM; 1394 } 1395 } 1396 m_copydata(m_head, 0, m_head->m_pkthdr.len, 1397 mtod(mn, caddr_t)); 1398 mn->m_pkthdr.len = mn->m_len = m_head->m_pkthdr.len; 1399 m_freem(m_head); 1400 m_head = mn; 1401 goto encap_retry; 1402 } 1403 1404 c->ste_mbuf = m_head; 1405 d->ste_frags[frag - 1].ste_len |= STE_FRAG_LAST; 1406 d->ste_ctl = 1; 1407 1408 return(0); 1409 } 1410 1411 static void 1412 ste_start(struct ifnet *ifp) 1413 { 1414 struct ste_softc *sc; 1415 struct mbuf *m_head = NULL; 1416 struct ste_chain *cur_tx = NULL; 1417 int idx; 1418 1419 sc = ifp->if_softc; 1420 1421 if (!sc->ste_link) 1422 return; 1423 1424 if (ifp->if_flags & IFF_OACTIVE) 1425 return; 1426 1427 idx = sc->ste_cdata.ste_tx_prod; 1428 1429 while(sc->ste_cdata.ste_tx_chain[idx].ste_mbuf == NULL) { 1430 1431 if ((STE_TX_LIST_CNT - sc->ste_cdata.ste_tx_cnt) < 3) { 1432 ifp->if_flags |= IFF_OACTIVE; 1433 break; 1434 } 1435 1436 m_head = ifq_dequeue(&ifp->if_snd, NULL); 1437 if (m_head == NULL) 1438 break; 1439 1440 cur_tx = &sc->ste_cdata.ste_tx_chain[idx]; 1441 1442 if (ste_encap(sc, cur_tx, m_head) != 0) 1443 break; 1444 1445 cur_tx->ste_ptr->ste_next = 0; 1446 1447 if(sc->ste_tx_prev_idx < 0){ 1448 cur_tx->ste_ptr->ste_ctl = STE_TXCTL_DMAINTR | 1; 1449 /* Load address of the TX list */ 1450 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL); 1451 ste_wait(sc); 1452 1453 CSR_WRITE_4(sc, STE_TX_DMALIST_PTR, 1454 vtophys(&sc->ste_ldata->ste_tx_list[0])); 1455 1456 /* Set TX polling interval to start TX engine */ 1457 CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 64); 1458 1459 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 1460 ste_wait(sc); 1461 }else{ 1462 cur_tx->ste_ptr->ste_ctl = STE_TXCTL_DMAINTR | 1; 1463 sc->ste_cdata.ste_tx_chain[ 1464 sc->ste_tx_prev_idx].ste_ptr->ste_next 1465 = cur_tx->ste_phys; 1466 } 1467 1468 sc->ste_tx_prev_idx=idx; 1469 1470 BPF_MTAP(ifp, cur_tx->ste_mbuf); 1471 1472 STE_INC(idx, STE_TX_LIST_CNT); 1473 sc->ste_cdata.ste_tx_cnt++; 1474 ifp->if_timer = 5; 1475 sc->ste_cdata.ste_tx_prod = idx; 1476 } 1477 1478 return; 1479 } 1480 1481 static void 1482 ste_watchdog(struct ifnet *ifp) 1483 { 1484 struct ste_softc *sc; 1485 1486 sc = ifp->if_softc; 1487 1488 ifp->if_oerrors++; 1489 if_printf(ifp, "watchdog timeout\n"); 1490 1491 ste_txeoc(sc); 1492 ste_txeof(sc); 1493 ste_rxeof(sc); 1494 ste_reset(sc); 1495 ste_init(sc); 1496 1497 if (!ifq_is_empty(&ifp->if_snd)) 1498 ste_start(ifp); 1499 1500 return; 1501 } 1502 1503 static void 1504 ste_shutdown(device_t dev) 1505 { 1506 struct ste_softc *sc; 1507 1508 sc = device_get_softc(dev); 1509 1510 ste_stop(sc); 1511 1512 return; 1513 } 1514