1*86d7f5d3SJohn Marino /* 2*86d7f5d3SJohn Marino * Copyright (c) 1997, 1998, 1999 3*86d7f5d3SJohn Marino * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4*86d7f5d3SJohn Marino * 5*86d7f5d3SJohn Marino * Redistribution and use in source and binary forms, with or without 6*86d7f5d3SJohn Marino * modification, are permitted provided that the following conditions 7*86d7f5d3SJohn Marino * are met: 8*86d7f5d3SJohn Marino * 1. Redistributions of source code must retain the above copyright 9*86d7f5d3SJohn Marino * notice, this list of conditions and the following disclaimer. 10*86d7f5d3SJohn Marino * 2. Redistributions in binary form must reproduce the above copyright 11*86d7f5d3SJohn Marino * notice, this list of conditions and the following disclaimer in the 12*86d7f5d3SJohn Marino * documentation and/or other materials provided with the distribution. 13*86d7f5d3SJohn Marino * 3. All advertising materials mentioning features or use of this software 14*86d7f5d3SJohn Marino * must display the following acknowledgement: 15*86d7f5d3SJohn Marino * This product includes software developed by Bill Paul. 16*86d7f5d3SJohn Marino * 4. Neither the name of the author nor the names of any co-contributors 17*86d7f5d3SJohn Marino * may be used to endorse or promote products derived from this software 18*86d7f5d3SJohn Marino * without specific prior written permission. 19*86d7f5d3SJohn Marino * 20*86d7f5d3SJohn Marino * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21*86d7f5d3SJohn Marino * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22*86d7f5d3SJohn Marino * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23*86d7f5d3SJohn Marino * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24*86d7f5d3SJohn Marino * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25*86d7f5d3SJohn Marino * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26*86d7f5d3SJohn Marino * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27*86d7f5d3SJohn Marino * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28*86d7f5d3SJohn Marino * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29*86d7f5d3SJohn Marino * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30*86d7f5d3SJohn Marino * THE POSSIBILITY OF SUCH DAMAGE. 31*86d7f5d3SJohn Marino * 32*86d7f5d3SJohn Marino * $FreeBSD: src/sys/pci/if_stereg.h,v 1.5.2.3 2002/08/21 15:26:01 ambrisko Exp $ 33*86d7f5d3SJohn Marino * $DragonFly: src/sys/dev/netif/ste/if_stereg.h,v 1.7 2006/08/01 18:10:05 swildner Exp $ 34*86d7f5d3SJohn Marino */ 35*86d7f5d3SJohn Marino 36*86d7f5d3SJohn Marino /* 37*86d7f5d3SJohn Marino * Register definitions for the Sundance Technologies ST201 PCI 38*86d7f5d3SJohn Marino * fast ethernet controller. The register space is 128 bytes long and 39*86d7f5d3SJohn Marino * can be accessed using either PCI I/O space or PCI memory mapping. 40*86d7f5d3SJohn Marino * There are 32-bit, 16-bit and 8-bit registers. 41*86d7f5d3SJohn Marino */ 42*86d7f5d3SJohn Marino 43*86d7f5d3SJohn Marino #define STE_DMACTL 0x00 44*86d7f5d3SJohn Marino #define STE_TX_DMALIST_PTR 0x04 45*86d7f5d3SJohn Marino #define STE_TX_DMABURST_THRESH 0x08 46*86d7f5d3SJohn Marino #define STE_TX_DMAURG_THRESH 0x09 47*86d7f5d3SJohn Marino #define STE_TX_DMAPOLL_PERIOD 0x0A 48*86d7f5d3SJohn Marino #define STE_RX_DMASTATUS 0x0C 49*86d7f5d3SJohn Marino #define STE_RX_DMALIST_PTR 0x10 50*86d7f5d3SJohn Marino #define STE_RX_DMABURST_THRESH 0x14 51*86d7f5d3SJohn Marino #define STE_RX_DMAURG_THRESH 0x15 52*86d7f5d3SJohn Marino #define STE_RX_DMAPOLL_PERIOD 0x16 53*86d7f5d3SJohn Marino #define STE_DEBUGCTL 0x1A 54*86d7f5d3SJohn Marino #define STE_ASICCTL 0x30 55*86d7f5d3SJohn Marino #define STE_EEPROM_DATA 0x34 56*86d7f5d3SJohn Marino #define STE_EEPROM_CTL 0x36 57*86d7f5d3SJohn Marino #define STE_FIFOCTL 0x3A 58*86d7f5d3SJohn Marino #define STE_TX_STARTTHRESH 0x3C 59*86d7f5d3SJohn Marino #define STE_RX_EARLYTHRESH 0x3E 60*86d7f5d3SJohn Marino #define STE_EXT_ROMADDR 0x40 61*86d7f5d3SJohn Marino #define STE_EXT_ROMDATA 0x44 62*86d7f5d3SJohn Marino #define STE_WAKE_EVENT 0x45 63*86d7f5d3SJohn Marino #define STE_TX_STATUS 0x46 64*86d7f5d3SJohn Marino #define STE_TX_FRAMEID 0x47 65*86d7f5d3SJohn Marino #define STE_COUNTDOWN 0x48 66*86d7f5d3SJohn Marino #define STE_ISR_ACK 0x4A 67*86d7f5d3SJohn Marino #define STE_IMR 0x4C 68*86d7f5d3SJohn Marino #define STE_ISR 0x4E 69*86d7f5d3SJohn Marino #define STE_MACCTL0 0x50 70*86d7f5d3SJohn Marino #define STE_MACCTL1 0x52 71*86d7f5d3SJohn Marino #define STE_PAR0 0x54 72*86d7f5d3SJohn Marino #define STE_PAR1 0x56 73*86d7f5d3SJohn Marino #define STE_PAR2 0x58 74*86d7f5d3SJohn Marino #define STE_MAX_FRAMELEN 0x5A 75*86d7f5d3SJohn Marino #define STE_RX_MODE 0x5C 76*86d7f5d3SJohn Marino #define STE_TX_RECLAIM_THRESH 0x5D 77*86d7f5d3SJohn Marino #define STE_PHYCTL 0x5E 78*86d7f5d3SJohn Marino #define STE_MAR0 0x60 79*86d7f5d3SJohn Marino #define STE_MAR1 0x62 80*86d7f5d3SJohn Marino #define STE_MAR2 0x64 81*86d7f5d3SJohn Marino #define STE_MAR3 0x66 82*86d7f5d3SJohn Marino #define STE_STATS 0x68 83*86d7f5d3SJohn Marino 84*86d7f5d3SJohn Marino #define STE_LATE_COLLS 0x75 85*86d7f5d3SJohn Marino #define STE_MULTI_COLLS 0x76 86*86d7f5d3SJohn Marino #define STE_SINGLE_COLLS 0x77 87*86d7f5d3SJohn Marino 88*86d7f5d3SJohn Marino #define STE_DMACTL_RXDMA_STOPPED 0x00000001 89*86d7f5d3SJohn Marino #define STE_DMACTL_TXDMA_CMPREQ 0x00000002 90*86d7f5d3SJohn Marino #define STE_DMACTL_TXDMA_STOPPED 0x00000004 91*86d7f5d3SJohn Marino #define STE_DMACTL_RXDMA_COMPLETE 0x00000008 92*86d7f5d3SJohn Marino #define STE_DMACTL_TXDMA_COMPLETE 0x00000010 93*86d7f5d3SJohn Marino #define STE_DMACTL_RXDMA_STALL 0x00000100 94*86d7f5d3SJohn Marino #define STE_DMACTL_RXDMA_UNSTALL 0x00000200 95*86d7f5d3SJohn Marino #define STE_DMACTL_TXDMA_STALL 0x00000400 96*86d7f5d3SJohn Marino #define STE_DMACTL_TXDMA_UNSTALL 0x00000800 97*86d7f5d3SJohn Marino #define STE_DMACTL_TXDMA_INPROG 0x00004000 98*86d7f5d3SJohn Marino #define STE_DMACTL_DMA_HALTINPROG 0x00008000 99*86d7f5d3SJohn Marino #define STE_DMACTL_RXEARLY_ENABLE 0x00020000 100*86d7f5d3SJohn Marino #define STE_DMACTL_COUNTDOWN_SPEED 0x00040000 101*86d7f5d3SJohn Marino #define STE_DMACTL_COUNTDOWN_MODE 0x00080000 102*86d7f5d3SJohn Marino #define STE_DMACTL_MWI_DISABLE 0x00100000 103*86d7f5d3SJohn Marino #define STE_DMACTL_RX_DISCARD_OFLOWS 0x00400000 104*86d7f5d3SJohn Marino #define STE_DMACTL_COUNTDOWN_ENABLE 0x00800000 105*86d7f5d3SJohn Marino #define STE_DMACTL_TARGET_ABORT 0x40000000 106*86d7f5d3SJohn Marino #define STE_DMACTL_MASTER_ABORT 0x80000000 107*86d7f5d3SJohn Marino 108*86d7f5d3SJohn Marino /* 109*86d7f5d3SJohn Marino * TX DMA burst thresh is the number of 32-byte blocks that 110*86d7f5d3SJohn Marino * must be loaded into the TX Fifo before a TXDMA burst request 111*86d7f5d3SJohn Marino * will be issued. 112*86d7f5d3SJohn Marino */ 113*86d7f5d3SJohn Marino #define STE_TXDMABURST_THRESH 0x1F 114*86d7f5d3SJohn Marino 115*86d7f5d3SJohn Marino /* 116*86d7f5d3SJohn Marino * The number of 32-byte blocks in the TX FIFO falls below the 117*86d7f5d3SJohn Marino * TX DMA urgent threshold, a TX DMA urgent request will be 118*86d7f5d3SJohn Marino * generated. 119*86d7f5d3SJohn Marino */ 120*86d7f5d3SJohn Marino #define STE_TXDMAURG_THRESH 0x3F 121*86d7f5d3SJohn Marino 122*86d7f5d3SJohn Marino /* 123*86d7f5d3SJohn Marino * Number of 320ns intervals between polls of the TXDMA next 124*86d7f5d3SJohn Marino * descriptor pointer (if we're using polling mode). 125*86d7f5d3SJohn Marino */ 126*86d7f5d3SJohn Marino #define STE_TXDMA_POLL_PERIOD 0x7F 127*86d7f5d3SJohn Marino 128*86d7f5d3SJohn Marino #define STE_RX_DMASTATUS_FRAMELEN 0x00001FFF 129*86d7f5d3SJohn Marino #define STE_RX_DMASTATUS_RXERR 0x00004000 130*86d7f5d3SJohn Marino #define STE_RX_DMASTATUS_DMADONE 0x00008000 131*86d7f5d3SJohn Marino #define STE_RX_DMASTATUS_FIFO_OFLOW 0x00010000 132*86d7f5d3SJohn Marino #define STE_RX_DMASTATUS_RUNT 0x00020000 133*86d7f5d3SJohn Marino #define STE_RX_DMASTATUS_ALIGNERR 0x00040000 134*86d7f5d3SJohn Marino #define STE_RX_DMASTATUS_CRCERR 0x00080000 135*86d7f5d3SJohn Marino #define STE_RX_DMASTATUS_GIANT 0x00100000 136*86d7f5d3SJohn Marino #define STE_RX_DMASTATUS_DRIBBLE 0x00800000 137*86d7f5d3SJohn Marino #define STE_RX_DMASTATUS_DMA_OFLOW 0x01000000 138*86d7f5d3SJohn Marino 139*86d7f5d3SJohn Marino /* 140*86d7f5d3SJohn Marino * RX DMA burst thresh is the number of 32-byte blocks that 141*86d7f5d3SJohn Marino * must be present in the RX FIFO before a RXDMA bus master 142*86d7f5d3SJohn Marino * request will be issued. 143*86d7f5d3SJohn Marino */ 144*86d7f5d3SJohn Marino #define STE_RXDMABURST_THRESH 0xFF 145*86d7f5d3SJohn Marino 146*86d7f5d3SJohn Marino /* 147*86d7f5d3SJohn Marino * The number of 32-byte blocks in the RX FIFO falls below the 148*86d7f5d3SJohn Marino * RX DMA urgent threshold, a RX DMA urgent request will be 149*86d7f5d3SJohn Marino * generated. 150*86d7f5d3SJohn Marino */ 151*86d7f5d3SJohn Marino #define STE_RXDMAURG_THRESH 0x1F 152*86d7f5d3SJohn Marino 153*86d7f5d3SJohn Marino /* 154*86d7f5d3SJohn Marino * Number of 320ns intervals between polls of the RXDMA complete 155*86d7f5d3SJohn Marino * bit in the status field on the current RX descriptor (if we're 156*86d7f5d3SJohn Marino * using polling mode). 157*86d7f5d3SJohn Marino */ 158*86d7f5d3SJohn Marino #define STE_RXDMA_POLL_PERIOD 0x7F 159*86d7f5d3SJohn Marino 160*86d7f5d3SJohn Marino #define STE_DEBUGCTL_GPIO0_CTL 0x0001 161*86d7f5d3SJohn Marino #define STE_DEBUGCTL_GPIO1_CTL 0x0002 162*86d7f5d3SJohn Marino #define STE_DEBUGCTL_GPIO0_DATA 0x0004 163*86d7f5d3SJohn Marino #define STE_DEBUGCTL_GPIO1_DATA 0x0008 164*86d7f5d3SJohn Marino 165*86d7f5d3SJohn Marino #define STE_ASICCTL_ROMSIZE 0x00000002 166*86d7f5d3SJohn Marino #define STE_ASICCTL_TX_LARGEPKTS 0x00000004 167*86d7f5d3SJohn Marino #define STE_ASICCTL_RX_LARGEPKTS 0x00000008 168*86d7f5d3SJohn Marino #define STE_ASICCTL_EXTROM_DISABLE 0x00000010 169*86d7f5d3SJohn Marino #define STE_ASICCTL_PHYSPEED_10 0x00000020 170*86d7f5d3SJohn Marino #define STE_ASICCTL_PHYSPEED_100 0x00000040 171*86d7f5d3SJohn Marino #define STE_ASICCTL_PHYMEDIA 0x00000080 172*86d7f5d3SJohn Marino #define STE_ASICCTL_FORCEDCONFIG 0x00000700 173*86d7f5d3SJohn Marino #define STE_ASICCTL_D3RESET_DISABLE 0x00000800 174*86d7f5d3SJohn Marino #define STE_ASICCTL_SPEEDUPMODE 0x00002000 175*86d7f5d3SJohn Marino #define STE_ASICCTL_LEDMODE 0x00004000 176*86d7f5d3SJohn Marino #define STE_ASICCTL_RSTOUT_POLARITY 0x00008000 177*86d7f5d3SJohn Marino #define STE_ASICCTL_GLOBAL_RESET 0x00010000 178*86d7f5d3SJohn Marino #define STE_ASICCTL_RX_RESET 0x00020000 179*86d7f5d3SJohn Marino #define STE_ASICCTL_TX_RESET 0x00040000 180*86d7f5d3SJohn Marino #define STE_ASICCTL_DMA_RESET 0x00080000 181*86d7f5d3SJohn Marino #define STE_ASICCTL_FIFO_RESET 0x00100000 182*86d7f5d3SJohn Marino #define STE_ASICCTL_NETWORK_RESET 0x00200000 183*86d7f5d3SJohn Marino #define STE_ASICCTL_HOST_RESET 0x00400000 184*86d7f5d3SJohn Marino #define STE_ASICCTL_AUTOINIT_RESET 0x00800000 185*86d7f5d3SJohn Marino #define STE_ASICCTL_EXTRESET_RESET 0x01000000 186*86d7f5d3SJohn Marino #define STE_ASICCTL_SOFTINTR 0x02000000 187*86d7f5d3SJohn Marino #define STE_ASICCTL_RESET_BUSY 0x04000000 188*86d7f5d3SJohn Marino 189*86d7f5d3SJohn Marino #define STE_ASICCTL1_GLOBAL_RESET 0x0001 190*86d7f5d3SJohn Marino #define STE_ASICCTL1_RX_RESET 0x0002 191*86d7f5d3SJohn Marino #define STE_ASICCTL1_TX_RESET 0x0004 192*86d7f5d3SJohn Marino #define STE_ASICCTL1_DMA_RESET 0x0008 193*86d7f5d3SJohn Marino #define STE_ASICCTL1_FIFO_RESET 0x0010 194*86d7f5d3SJohn Marino #define STE_ASICCTL1_NETWORK_RESET 0x0020 195*86d7f5d3SJohn Marino #define STE_ASICCTL1_HOST_RESET 0x0040 196*86d7f5d3SJohn Marino #define STE_ASICCTL1_AUTOINIT_RESET 0x0080 197*86d7f5d3SJohn Marino #define STE_ASICCTL1_EXTRESET_RESET 0x0100 198*86d7f5d3SJohn Marino #define STE_ASICCTL1_SOFTINTR 0x0200 199*86d7f5d3SJohn Marino #define STE_ASICCTL1_RESET_BUSY 0x0400 200*86d7f5d3SJohn Marino 201*86d7f5d3SJohn Marino #define STE_EECTL_ADDR 0x00FF 202*86d7f5d3SJohn Marino #define STE_EECTL_OPCODE 0x0300 203*86d7f5d3SJohn Marino #define STE_EECTL_BUSY 0x1000 204*86d7f5d3SJohn Marino 205*86d7f5d3SJohn Marino #define STE_EEOPCODE_WRITE 0x0100 206*86d7f5d3SJohn Marino #define STE_EEOPCODE_READ 0x0200 207*86d7f5d3SJohn Marino #define STE_EEOPCODE_ERASE 0x0300 208*86d7f5d3SJohn Marino 209*86d7f5d3SJohn Marino #define STE_FIFOCTL_RAMTESTMODE 0x0001 210*86d7f5d3SJohn Marino #define STE_FIFOCTL_OVERRUNMODE 0x0200 211*86d7f5d3SJohn Marino #define STE_FIFOCTL_RXFIFOFULL 0x0800 212*86d7f5d3SJohn Marino #define STE_FIFOCTL_TX_BUSY 0x4000 213*86d7f5d3SJohn Marino #define STE_FIFOCTL_RX_BUSY 0x8000 214*86d7f5d3SJohn Marino 215*86d7f5d3SJohn Marino /* 216*86d7f5d3SJohn Marino * The number of bytes that must in present in the TX FIFO before 217*86d7f5d3SJohn Marino * transmission begins. Value should be in increments of 4 bytes. 218*86d7f5d3SJohn Marino */ 219*86d7f5d3SJohn Marino #define STE_TXSTART_THRESH 0x1FFC 220*86d7f5d3SJohn Marino 221*86d7f5d3SJohn Marino /* 222*86d7f5d3SJohn Marino * Number of bytes that must be present in the RX FIFO before 223*86d7f5d3SJohn Marino * an RX EARLY interrupt is generated. 224*86d7f5d3SJohn Marino */ 225*86d7f5d3SJohn Marino #define STE_RXEARLY_THRESH 0x1FFC 226*86d7f5d3SJohn Marino 227*86d7f5d3SJohn Marino #define STE_WAKEEVENT_WAKEPKT_ENB 0x01 228*86d7f5d3SJohn Marino #define STE_WAKEEVENT_MAGICPKT_ENB 0x02 229*86d7f5d3SJohn Marino #define STE_WAKEEVENT_LINKEVT_ENB 0x04 230*86d7f5d3SJohn Marino #define STE_WAKEEVENT_WAKEPOLARITY 0x08 231*86d7f5d3SJohn Marino #define STE_WAKEEVENT_WAKEPKTEVENT 0x10 232*86d7f5d3SJohn Marino #define STE_WAKEEVENT_MAGICPKTEVENT 0x20 233*86d7f5d3SJohn Marino #define STE_WAKEEVENT_LINKEVENT 0x40 234*86d7f5d3SJohn Marino #define STE_WAKEEVENT_WAKEONLAN_ENB 0x80 235*86d7f5d3SJohn Marino 236*86d7f5d3SJohn Marino #define STE_TXSTATUS_RECLAIMERR 0x02 237*86d7f5d3SJohn Marino #define STE_TXSTATUS_STATSOFLOW 0x04 238*86d7f5d3SJohn Marino #define STE_TXSTATUS_EXCESSCOLLS 0x08 239*86d7f5d3SJohn Marino #define STE_TXSTATUS_UNDERRUN 0x10 240*86d7f5d3SJohn Marino #define STE_TXSTATUS_TXINTR_REQ 0x40 241*86d7f5d3SJohn Marino #define STE_TXSTATUS_TXDONE 0x80 242*86d7f5d3SJohn Marino 243*86d7f5d3SJohn Marino #define STE_ISRACK_INTLATCH 0x0001 244*86d7f5d3SJohn Marino #define STE_ISRACK_HOSTERR 0x0002 245*86d7f5d3SJohn Marino #define STE_ISRACK_TX_DONE 0x0004 246*86d7f5d3SJohn Marino #define STE_ISRACK_MACCTL_FRAME 0x0008 247*86d7f5d3SJohn Marino #define STE_ISRACK_RX_DONE 0x0010 248*86d7f5d3SJohn Marino #define STE_ISRACK_RX_EARLY 0x0020 249*86d7f5d3SJohn Marino #define STE_ISRACK_SOFTINTR 0x0040 250*86d7f5d3SJohn Marino #define STE_ISRACK_STATS_OFLOW 0x0080 251*86d7f5d3SJohn Marino #define STE_ISRACK_LINKEVENT 0x0100 252*86d7f5d3SJohn Marino #define STE_ISRACK_TX_DMADONE 0x0200 253*86d7f5d3SJohn Marino #define STE_ISRACK_RX_DMADONE 0x0400 254*86d7f5d3SJohn Marino 255*86d7f5d3SJohn Marino #define STE_IMR_HOSTERR 0x0002 256*86d7f5d3SJohn Marino #define STE_IMR_TX_DONE 0x0004 257*86d7f5d3SJohn Marino #define STE_IMR_MACCTL_FRAME 0x0008 258*86d7f5d3SJohn Marino #define STE_IMR_RX_DONE 0x0010 259*86d7f5d3SJohn Marino #define STE_IMR_RX_EARLY 0x0020 260*86d7f5d3SJohn Marino #define STE_IMR_SOFTINTR 0x0040 261*86d7f5d3SJohn Marino #define STE_IMR_STATS_OFLOW 0x0080 262*86d7f5d3SJohn Marino #define STE_IMR_LINKEVENT 0x0100 263*86d7f5d3SJohn Marino #define STE_IMR_TX_DMADONE 0x0200 264*86d7f5d3SJohn Marino #define STE_IMR_RX_DMADONE 0x0400 265*86d7f5d3SJohn Marino 266*86d7f5d3SJohn Marino #define STE_INTRS \ 267*86d7f5d3SJohn Marino (STE_IMR_RX_DMADONE|STE_IMR_TX_DMADONE| \ 268*86d7f5d3SJohn Marino STE_IMR_TX_DONE|STE_IMR_HOSTERR| \ 269*86d7f5d3SJohn Marino STE_IMR_LINKEVENT) 270*86d7f5d3SJohn Marino 271*86d7f5d3SJohn Marino #define STE_ISR_INTLATCH 0x0001 272*86d7f5d3SJohn Marino #define STE_ISR_HOSTERR 0x0002 273*86d7f5d3SJohn Marino #define STE_ISR_TX_DONE 0x0004 274*86d7f5d3SJohn Marino #define STE_ISR_MACCTL_FRAME 0x0008 275*86d7f5d3SJohn Marino #define STE_ISR_RX_DONE 0x0010 276*86d7f5d3SJohn Marino #define STE_ISR_RX_EARLY 0x0020 277*86d7f5d3SJohn Marino #define STE_ISR_SOFTINTR 0x0040 278*86d7f5d3SJohn Marino #define STE_ISR_STATS_OFLOW 0x0080 279*86d7f5d3SJohn Marino #define STE_ISR_LINKEVENT 0x0100 280*86d7f5d3SJohn Marino #define STE_ISR_TX_DMADONE 0x0200 281*86d7f5d3SJohn Marino #define STE_ISR_RX_DMADONE 0x0400 282*86d7f5d3SJohn Marino 283*86d7f5d3SJohn Marino /* 284*86d7f5d3SJohn Marino * Note: the Sundance manual gives the impression that the's 285*86d7f5d3SJohn Marino * only one 32-bit MACCTL register. In fact, there are two 286*86d7f5d3SJohn Marino * 16-bit registers side by side, and you have to access them 287*86d7f5d3SJohn Marino * separately. 288*86d7f5d3SJohn Marino */ 289*86d7f5d3SJohn Marino #define STE_MACCTL0_IPG 0x0003 290*86d7f5d3SJohn Marino #define STE_MACCTL0_FULLDUPLEX 0x0020 291*86d7f5d3SJohn Marino #define STE_MACCTL0_RX_GIANTS 0x0040 292*86d7f5d3SJohn Marino #define STE_MACCTL0_FLOWCTL_ENABLE 0x0100 293*86d7f5d3SJohn Marino #define STE_MACCTL0_RX_FCS 0x0200 294*86d7f5d3SJohn Marino #define STE_MACCTL0_FIFOLOOPBK 0x0400 295*86d7f5d3SJohn Marino #define STE_MACCTL0_MACLOOPBK 0x0800 296*86d7f5d3SJohn Marino 297*86d7f5d3SJohn Marino #define STE_MACCTL1_COLLDETECT 0x0001 298*86d7f5d3SJohn Marino #define STE_MACCTL1_CARRSENSE 0x0002 299*86d7f5d3SJohn Marino #define STE_MACCTL1_TX_BUSY 0x0004 300*86d7f5d3SJohn Marino #define STE_MACCTL1_TX_ERROR 0x0008 301*86d7f5d3SJohn Marino #define STE_MACCTL1_STATS_ENABLE 0x0020 302*86d7f5d3SJohn Marino #define STE_MACCTL1_STATS_DISABLE 0x0040 303*86d7f5d3SJohn Marino #define STE_MACCTL1_STATS_ENABLED 0x0080 304*86d7f5d3SJohn Marino #define STE_MACCTL1_TX_ENABLE 0x0100 305*86d7f5d3SJohn Marino #define STE_MACCTL1_TX_DISABLE 0x0200 306*86d7f5d3SJohn Marino #define STE_MACCTL1_TX_ENABLED 0x0400 307*86d7f5d3SJohn Marino #define STE_MACCTL1_RX_ENABLE 0x0800 308*86d7f5d3SJohn Marino #define STE_MACCTL1_RX_DISABLE 0x1000 309*86d7f5d3SJohn Marino #define STE_MACCTL1_RX_ENABLED 0x2000 310*86d7f5d3SJohn Marino #define STE_MACCTL1_PAUSED 0x4000 311*86d7f5d3SJohn Marino 312*86d7f5d3SJohn Marino #define STE_IPG_96BT 0x00000000 313*86d7f5d3SJohn Marino #define STE_IPG_128BT 0x00000001 314*86d7f5d3SJohn Marino #define STE_IPG_224BT 0x00000002 315*86d7f5d3SJohn Marino #define STE_IPG_544BT 0x00000003 316*86d7f5d3SJohn Marino 317*86d7f5d3SJohn Marino #define STE_RXMODE_UNICAST 0x01 318*86d7f5d3SJohn Marino #define STE_RXMODE_ALLMULTI 0x02 319*86d7f5d3SJohn Marino #define STE_RXMODE_BROADCAST 0x04 320*86d7f5d3SJohn Marino #define STE_RXMODE_PROMISC 0x08 321*86d7f5d3SJohn Marino #define STE_RXMODE_MULTIHASH 0x10 322*86d7f5d3SJohn Marino #define STE_RXMODE_ALLIPMULTI 0x20 323*86d7f5d3SJohn Marino 324*86d7f5d3SJohn Marino #define STE_PHYCTL_MCLK 0x01 325*86d7f5d3SJohn Marino #define STE_PHYCTL_MDATA 0x02 326*86d7f5d3SJohn Marino #define STE_PHYCTL_MDIR 0x04 327*86d7f5d3SJohn Marino #define STE_PHYCTL_CLK25_DISABLE 0x08 328*86d7f5d3SJohn Marino #define STE_PHYCTL_DUPLEXPOLARITY 0x10 329*86d7f5d3SJohn Marino #define STE_PHYCTL_DUPLEXSTAT 0x20 330*86d7f5d3SJohn Marino #define STE_PHYCTL_SPEEDSTAT 0x40 331*86d7f5d3SJohn Marino #define STE_PHYCTL_LINKSTAT 0x80 332*86d7f5d3SJohn Marino 333*86d7f5d3SJohn Marino /* 334*86d7f5d3SJohn Marino * EEPROM offsets. 335*86d7f5d3SJohn Marino */ 336*86d7f5d3SJohn Marino #define STE_EEADDR_CONFIGPARM 0x00 337*86d7f5d3SJohn Marino #define STE_EEADDR_ASICCTL 0x02 338*86d7f5d3SJohn Marino #define STE_EEADDR_SUBSYS_ID 0x04 339*86d7f5d3SJohn Marino #define STE_EEADDR_SUBVEN_ID 0x08 340*86d7f5d3SJohn Marino 341*86d7f5d3SJohn Marino #define STE_EEADDR_NODE0 0x10 342*86d7f5d3SJohn Marino #define STE_EEADDR_NODE1 0x12 343*86d7f5d3SJohn Marino #define STE_EEADDR_NODE2 0x14 344*86d7f5d3SJohn Marino 345*86d7f5d3SJohn Marino /* PCI registers */ 346*86d7f5d3SJohn Marino #define STE_PCI_VENDOR_ID 0x00 347*86d7f5d3SJohn Marino #define STE_PCI_DEVICE_ID 0x02 348*86d7f5d3SJohn Marino #define STE_PCI_COMMAND 0x04 349*86d7f5d3SJohn Marino #define STE_PCI_STATUS 0x06 350*86d7f5d3SJohn Marino #define STE_PCI_CLASSCODE 0x09 351*86d7f5d3SJohn Marino #define STE_PCI_LATENCY_TIMER 0x0D 352*86d7f5d3SJohn Marino #define STE_PCI_HEADER_TYPE 0x0E 353*86d7f5d3SJohn Marino #define STE_PCI_LOIO 0x10 354*86d7f5d3SJohn Marino #define STE_PCI_LOMEM 0x14 355*86d7f5d3SJohn Marino #define STE_PCI_BIOSROM 0x30 356*86d7f5d3SJohn Marino #define STE_PCI_INTLINE 0x3C 357*86d7f5d3SJohn Marino #define STE_PCI_INTPIN 0x3D 358*86d7f5d3SJohn Marino #define STE_PCI_MINGNT 0x3E 359*86d7f5d3SJohn Marino #define STE_PCI_MINLAT 0x0F 360*86d7f5d3SJohn Marino 361*86d7f5d3SJohn Marino #define STE_PCI_CAPID 0x50 /* 8 bits */ 362*86d7f5d3SJohn Marino #define STE_PCI_NEXTPTR 0x51 /* 8 bits */ 363*86d7f5d3SJohn Marino #define STE_PCI_PWRMGMTCAP 0x52 /* 16 bits */ 364*86d7f5d3SJohn Marino #define STE_PCI_PWRMGMTCTRL 0x54 /* 16 bits */ 365*86d7f5d3SJohn Marino 366*86d7f5d3SJohn Marino #define STE_PME_EN 0x0010 367*86d7f5d3SJohn Marino #define STE_PME_STATUS 0x8000 368*86d7f5d3SJohn Marino 369*86d7f5d3SJohn Marino 370*86d7f5d3SJohn Marino struct ste_stats { 371*86d7f5d3SJohn Marino u_int32_t ste_rx_bytes; 372*86d7f5d3SJohn Marino u_int32_t ste_tx_bytes; 373*86d7f5d3SJohn Marino u_int16_t ste_tx_frames; 374*86d7f5d3SJohn Marino u_int16_t ste_rx_frames; 375*86d7f5d3SJohn Marino u_int8_t ste_carrsense_errs; 376*86d7f5d3SJohn Marino u_int8_t ste_late_colls; 377*86d7f5d3SJohn Marino u_int8_t ste_multi_colls; 378*86d7f5d3SJohn Marino u_int8_t ste_single_colls; 379*86d7f5d3SJohn Marino u_int8_t ste_tx_frames_defered; 380*86d7f5d3SJohn Marino u_int8_t ste_rx_lost_frames; 381*86d7f5d3SJohn Marino u_int8_t ste_tx_excess_defers; 382*86d7f5d3SJohn Marino u_int8_t ste_tx_abort_excess_colls; 383*86d7f5d3SJohn Marino u_int8_t ste_tx_bcast_frames; 384*86d7f5d3SJohn Marino u_int8_t ste_rx_bcast_frames; 385*86d7f5d3SJohn Marino u_int8_t ste_tx_mcast_frames; 386*86d7f5d3SJohn Marino u_int8_t ste_rx_mcast_frames; 387*86d7f5d3SJohn Marino }; 388*86d7f5d3SJohn Marino 389*86d7f5d3SJohn Marino struct ste_frag { 390*86d7f5d3SJohn Marino u_int32_t ste_addr; 391*86d7f5d3SJohn Marino u_int32_t ste_len; 392*86d7f5d3SJohn Marino }; 393*86d7f5d3SJohn Marino 394*86d7f5d3SJohn Marino #define STE_FRAG_LAST 0x80000000 395*86d7f5d3SJohn Marino #define STE_FRAG_LEN 0x00001FFF 396*86d7f5d3SJohn Marino 397*86d7f5d3SJohn Marino #define STE_MAXFRAGS 8 398*86d7f5d3SJohn Marino 399*86d7f5d3SJohn Marino struct ste_desc { 400*86d7f5d3SJohn Marino u_int32_t ste_next; 401*86d7f5d3SJohn Marino u_int32_t ste_ctl; 402*86d7f5d3SJohn Marino struct ste_frag ste_frags[STE_MAXFRAGS]; 403*86d7f5d3SJohn Marino }; 404*86d7f5d3SJohn Marino 405*86d7f5d3SJohn Marino struct ste_desc_onefrag { 406*86d7f5d3SJohn Marino u_int32_t ste_next; 407*86d7f5d3SJohn Marino u_int32_t ste_status; 408*86d7f5d3SJohn Marino struct ste_frag ste_frag; 409*86d7f5d3SJohn Marino }; 410*86d7f5d3SJohn Marino 411*86d7f5d3SJohn Marino #define STE_TXCTL_WORDALIGN 0x00000003 412*86d7f5d3SJohn Marino #define STE_TXCTL_FRAMEID 0x000003FC 413*86d7f5d3SJohn Marino #define STE_TXCTL_NOCRC 0x00002000 414*86d7f5d3SJohn Marino #define STE_TXCTL_TXINTR 0x00008000 415*86d7f5d3SJohn Marino #define STE_TXCTL_DMADONE 0x00010000 416*86d7f5d3SJohn Marino #define STE_TXCTL_DMAINTR 0x80000000 417*86d7f5d3SJohn Marino 418*86d7f5d3SJohn Marino #define STE_RXSTAT_FRAMELEN 0x00001FFF 419*86d7f5d3SJohn Marino #define STE_RXSTAT_FRAME_ERR 0x00004000 420*86d7f5d3SJohn Marino #define STE_RXSTAT_DMADONE 0x00008000 421*86d7f5d3SJohn Marino #define STE_RXSTAT_FIFO_OFLOW 0x00010000 422*86d7f5d3SJohn Marino #define STE_RXSTAT_RUNT 0x00020000 423*86d7f5d3SJohn Marino #define STE_RXSTAT_ALIGNERR 0x00040000 424*86d7f5d3SJohn Marino #define STE_RXSTAT_CRCERR 0x00080000 425*86d7f5d3SJohn Marino #define STE_RXSTAT_GIANT 0x00100000 426*86d7f5d3SJohn Marino #define STE_RXSTAT_DRIBBLEBITS 0x00800000 427*86d7f5d3SJohn Marino #define STE_RXSTAT_DMA_OFLOW 0x01000000 428*86d7f5d3SJohn Marino #define STE_RXATAT_ONEBUF 0x10000000 429*86d7f5d3SJohn Marino 430*86d7f5d3SJohn Marino /* 431*86d7f5d3SJohn Marino * register space access macros 432*86d7f5d3SJohn Marino */ 433*86d7f5d3SJohn Marino #define CSR_WRITE_4(sc, reg, val) \ 434*86d7f5d3SJohn Marino bus_space_write_4(sc->ste_btag, sc->ste_bhandle, reg, val) 435*86d7f5d3SJohn Marino #define CSR_WRITE_2(sc, reg, val) \ 436*86d7f5d3SJohn Marino bus_space_write_2(sc->ste_btag, sc->ste_bhandle, reg, val) 437*86d7f5d3SJohn Marino #define CSR_WRITE_1(sc, reg, val) \ 438*86d7f5d3SJohn Marino bus_space_write_1(sc->ste_btag, sc->ste_bhandle, reg, val) 439*86d7f5d3SJohn Marino 440*86d7f5d3SJohn Marino #define CSR_READ_4(sc, reg) \ 441*86d7f5d3SJohn Marino bus_space_read_4(sc->ste_btag, sc->ste_bhandle, reg) 442*86d7f5d3SJohn Marino #define CSR_READ_2(sc, reg) \ 443*86d7f5d3SJohn Marino bus_space_read_2(sc->ste_btag, sc->ste_bhandle, reg) 444*86d7f5d3SJohn Marino #define CSR_READ_1(sc, reg) \ 445*86d7f5d3SJohn Marino bus_space_read_1(sc->ste_btag, sc->ste_bhandle, reg) 446*86d7f5d3SJohn Marino 447*86d7f5d3SJohn Marino #define STE_TIMEOUT 1000 448*86d7f5d3SJohn Marino #define STE_MIN_FRAMELEN 60 449*86d7f5d3SJohn Marino #define STE_PACKET_SIZE 1536 450*86d7f5d3SJohn Marino #define ETHER_ALIGN 2 451*86d7f5d3SJohn Marino #define STE_RX_LIST_CNT 64 452*86d7f5d3SJohn Marino #define STE_TX_LIST_CNT 64 453*86d7f5d3SJohn Marino #define STE_INC(x, y) (x) = (x + 1) % y 454*86d7f5d3SJohn Marino #define STE_NEXT(x, y) (x + 1) % y 455*86d7f5d3SJohn Marino 456*86d7f5d3SJohn Marino struct ste_type { 457*86d7f5d3SJohn Marino u_int16_t ste_vid; 458*86d7f5d3SJohn Marino u_int16_t ste_did; 459*86d7f5d3SJohn Marino char *ste_name; 460*86d7f5d3SJohn Marino }; 461*86d7f5d3SJohn Marino 462*86d7f5d3SJohn Marino struct ste_list_data { 463*86d7f5d3SJohn Marino struct ste_desc_onefrag ste_rx_list[STE_RX_LIST_CNT]; 464*86d7f5d3SJohn Marino struct ste_desc ste_tx_list[STE_TX_LIST_CNT]; 465*86d7f5d3SJohn Marino u_int8_t ste_pad[STE_MIN_FRAMELEN]; 466*86d7f5d3SJohn Marino }; 467*86d7f5d3SJohn Marino 468*86d7f5d3SJohn Marino struct ste_chain { 469*86d7f5d3SJohn Marino struct ste_desc *ste_ptr; 470*86d7f5d3SJohn Marino struct mbuf *ste_mbuf; 471*86d7f5d3SJohn Marino struct ste_chain *ste_next; 472*86d7f5d3SJohn Marino struct ste_chain *ste_prev; 473*86d7f5d3SJohn Marino u_int32_t ste_phys; 474*86d7f5d3SJohn Marino }; 475*86d7f5d3SJohn Marino 476*86d7f5d3SJohn Marino struct ste_chain_onefrag { 477*86d7f5d3SJohn Marino struct ste_desc_onefrag *ste_ptr; 478*86d7f5d3SJohn Marino struct mbuf *ste_mbuf; 479*86d7f5d3SJohn Marino struct ste_chain_onefrag *ste_next; 480*86d7f5d3SJohn Marino }; 481*86d7f5d3SJohn Marino 482*86d7f5d3SJohn Marino struct ste_chain_data { 483*86d7f5d3SJohn Marino struct ste_chain_onefrag ste_rx_chain[STE_RX_LIST_CNT]; 484*86d7f5d3SJohn Marino struct ste_chain ste_tx_chain[STE_TX_LIST_CNT]; 485*86d7f5d3SJohn Marino struct ste_chain_onefrag *ste_rx_head; 486*86d7f5d3SJohn Marino 487*86d7f5d3SJohn Marino int ste_tx_prod; 488*86d7f5d3SJohn Marino int ste_tx_cons; 489*86d7f5d3SJohn Marino int ste_tx_cnt; 490*86d7f5d3SJohn Marino }; 491*86d7f5d3SJohn Marino 492*86d7f5d3SJohn Marino struct ste_softc { 493*86d7f5d3SJohn Marino struct arpcom arpcom; 494*86d7f5d3SJohn Marino bus_space_tag_t ste_btag; 495*86d7f5d3SJohn Marino bus_space_handle_t ste_bhandle; 496*86d7f5d3SJohn Marino struct resource *ste_res; 497*86d7f5d3SJohn Marino struct resource *ste_irq; 498*86d7f5d3SJohn Marino void *ste_intrhand; 499*86d7f5d3SJohn Marino struct ste_type *ste_info; 500*86d7f5d3SJohn Marino device_t ste_miibus; 501*86d7f5d3SJohn Marino device_t ste_dev; 502*86d7f5d3SJohn Marino int ste_tx_thresh; 503*86d7f5d3SJohn Marino u_int8_t ste_link; 504*86d7f5d3SJohn Marino int ste_if_flags; 505*86d7f5d3SJohn Marino int ste_tx_prev_idx; 506*86d7f5d3SJohn Marino struct ste_list_data *ste_ldata; 507*86d7f5d3SJohn Marino struct ste_chain_data ste_cdata; 508*86d7f5d3SJohn Marino struct callout ste_stat_timer; 509*86d7f5d3SJohn Marino u_int8_t ste_one_phy; 510*86d7f5d3SJohn Marino }; 511*86d7f5d3SJohn Marino 512*86d7f5d3SJohn Marino struct ste_mii_frame { 513*86d7f5d3SJohn Marino u_int8_t mii_stdelim; 514*86d7f5d3SJohn Marino u_int8_t mii_opcode; 515*86d7f5d3SJohn Marino u_int8_t mii_phyaddr; 516*86d7f5d3SJohn Marino u_int8_t mii_regaddr; 517*86d7f5d3SJohn Marino u_int8_t mii_turnaround; 518*86d7f5d3SJohn Marino u_int16_t mii_data; 519*86d7f5d3SJohn Marino }; 520*86d7f5d3SJohn Marino 521*86d7f5d3SJohn Marino /* 522*86d7f5d3SJohn Marino * MII constants 523*86d7f5d3SJohn Marino */ 524*86d7f5d3SJohn Marino #define STE_MII_STARTDELIM 0x01 525*86d7f5d3SJohn Marino #define STE_MII_READOP 0x02 526*86d7f5d3SJohn Marino #define STE_MII_WRITEOP 0x01 527*86d7f5d3SJohn Marino #define STE_MII_TURNAROUND 0x02 528