1 /* $NetBSD: if_stgereg.h,v 1.3 2003/02/10 21:10:07 christos Exp $ */ 2 /* $FreeBSD: src/sys/dev/stge/if_stgereg.h,v 1.1 2006/07/25 00:37:09 yongari Exp $ */ 3 /* $DragonFly: src/sys/dev/netif/stge/if_stgereg.h,v 1.1 2006/11/16 13:43:55 sephe Exp $ */ 4 5 /*- 6 * Copyright (c) 2001 The NetBSD Foundation, Inc. 7 * All rights reserved. 8 * 9 * This code is derived from software contributed to The NetBSD Foundation 10 * by Jason R. Thorpe. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 3. All advertising materials mentioning features or use of this software 21 * must display the following acknowledgement: 22 * This product includes software developed by the NetBSD 23 * Foundation, Inc. and its contributors. 24 * 4. Neither the name of The NetBSD Foundation nor the names of its 25 * contributors may be used to endorse or promote products derived 26 * from this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 29 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 30 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 31 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 32 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 33 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 34 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 35 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 36 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 37 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 38 * POSSIBILITY OF SUCH DAMAGE. 39 */ 40 41 /* 42 * Sundance Technology PCI vendor ID 43 */ 44 #define VENDOR_SUNDANCETI 0x13f0 45 46 /* 47 * Tamarack Microelectronics PCI vendor ID 48 */ 49 #define VENDOR_TAMARACK 0x143d 50 51 /* 52 * D-Link Systems PCI vendor ID 53 */ 54 #define VENDOR_DLINK 0x1186 55 56 /* 57 * Antares Microsystems PCI vendor ID 58 */ 59 #define VENDOR_ANTARES 0x1754 60 61 /* 62 * Sundance Technology device ID 63 */ 64 #define DEVICEID_SUNDANCETI_ST1023 0x1023 65 #define DEVICEID_SUNDANCETI_ST2021 0x2021 66 #define DEVICEID_TAMARACK_TC9021 0x1021 67 #define DEVICEID_TAMARACK_TC9021_ALT 0x9021 68 69 /* 70 * D-Link Systems device ID 71 */ 72 #define DEVICEID_DLINK_DL2000 0x4000 73 74 /* 75 * Antares Microsystems device ID 76 */ 77 #define DEVICEID_ANTARES_TC9021 0x1021 78 79 /* 80 * Register description for the Sundance Tech. TC9021 10/100/1000 81 * Ethernet controller. 82 * 83 * Note that while DMA addresses are all in 64-bit fields, only 84 * the lower 40 bits of a DMA address are valid. 85 */ 86 #if BUS_SPACE_MAXADDR > BUS_SPACE_MAXADDR_32BIT 87 #define STGE_DMA_MAXADDR 0xFFFFFFFFFFULL 88 #else 89 #define STGE_DMA_MAXADDR BUS_SPACE_MAXADDR 90 #endif 91 92 #define STGE_PCIR_LOIO PCIR_BAR(0) 93 #define STGE_PCIR_LOMEM PCIR_BAR(1) 94 95 /* 96 * Register access macros 97 */ 98 #define CSR_WRITE_4(_sc, reg, val) \ 99 bus_space_write_4((_sc)->sc_btag, (_sc)->sc_bhandle, (reg), (val)) 100 #define CSR_WRITE_2(_sc, reg, val) \ 101 bus_space_write_2((_sc)->sc_btag, (_sc)->sc_bhandle, (reg), (val)) 102 #define CSR_WRITE_1(_sc, reg, val) \ 103 bus_space_write_1((_sc)->sc_btag, (_sc)->sc_bhandle, (reg), (val)) 104 105 #define CSR_READ_4(_sc, reg) \ 106 bus_space_read_4((_sc)->sc_btag, (_sc)->sc_bhandle, (reg)) 107 #define CSR_READ_2(_sc, reg) \ 108 bus_space_read_2((_sc)->sc_btag, (_sc)->sc_bhandle, (reg)) 109 #define CSR_READ_1(_sc, reg) \ 110 bus_space_read_1((_sc)->sc_btag, (_sc)->sc_bhandle, (reg)) 111 112 /* 113 * TC9021 buffer fragment descriptor. 114 */ 115 struct stge_frag { 116 uint64_t frag_word0; /* address, length */ 117 }; 118 119 #define FRAG_ADDR(x) (((uint64_t)(x)) << 0) 120 #define FRAG_ADDR_MASK FRAG_ADDR(0xfffffffffULL) 121 #define FRAG_LEN(x) (((uint64_t)(x)) << 48) 122 #define FRAG_LEN_MASK FRAG_LEN(0xffffULL) 123 124 /* 125 * TC9021 Transmit Frame Descriptor. Note the number of fragments 126 * here is arbitrary, but we can't have any more than 15. 127 */ 128 #define STGE_NTXFRAGS 15 129 struct stge_tfd { 130 uint64_t tfd_next; /* next TFD in list */ 131 uint64_t tfd_control; /* control bits */ 132 /* the buffer fragments */ 133 struct stge_frag tfd_frags[STGE_NTXFRAGS]; 134 }; 135 136 #define TFD_FrameId(x) ((x) << 0) 137 #define TFD_FrameId_MAX 0xffff 138 #define TFD_WordAlign(x) ((x) << 16) 139 #define TFD_WordAlign_dword 0 /* align to dword in TxFIFO */ 140 #define TFD_WordAlign_word 2 /* align to word in TxFIFO */ 141 #define TFD_WordAlign_disable 1 /* disable alignment */ 142 #define TFD_TCPChecksumEnable (1ULL << 18) 143 #define TFD_UDPChecksumEnable (1ULL << 19) 144 #define TFD_IPChecksumEnable (1ULL << 20) 145 #define TFD_FcsAppendDisable (1ULL << 21) 146 #define TFD_TxIndicate (1ULL << 22) 147 #define TFD_TxDMAIndicate (1ULL << 23) 148 #define TFD_FragCount(x) ((x) << 24) 149 #define TFD_VLANTagInsert (1ULL << 28) 150 #define TFD_TFDDone (1ULL << 31) 151 #define TFD_VID(x) (((uint64_t)(x)) << 32) 152 #define TFD_CFI (1ULL << 44) 153 #define TFD_UserPriority(x) (((uint64_t)(x)) << 45) 154 155 /* 156 * TC9021 Receive Frame Descriptor. Each RFD has a single fragment 157 * in it, and the chip tells us the beginning and end of the frame. 158 */ 159 struct stge_rfd { 160 uint64_t rfd_next; /* next RFD in list */ 161 uint64_t rfd_status; /* status bits */ 162 struct stge_frag rfd_frag; /* the buffer */ 163 }; 164 165 /* Low word of rfd_status */ 166 #define RFD_RxStatus(x) ((x) & 0xffffffff) 167 #define RFD_RxDMAFrameLen(x) ((x) & 0xffff) 168 #define RFD_RxFIFOOverrun 0x00010000 169 #define RFD_RxRuntFrame 0x00020000 170 #define RFD_RxAlignmentError 0x00040000 171 #define RFD_RxFCSError 0x00080000 172 #define RFD_RxOversizedFrame 0x00100000 173 #define RFD_RxLengthError 0x00200000 174 #define RFD_VLANDetected 0x00400000 175 #define RFD_TCPDetected 0x00800000 176 #define RFD_TCPError 0x01000000 177 #define RFD_UDPDetected 0x02000000 178 #define RFD_UDPError 0x04000000 179 #define RFD_IPDetected 0x08000000 180 #define RFD_IPError 0x10000000 181 #define RFD_FrameStart 0x20000000 182 #define RFD_FrameEnd 0x40000000 183 #define RFD_RFDDone 0x80000000 184 /* High word of rfd_status */ 185 #define RFD_TCI(x) ((((uint64_t)(x)) >> 32) & 0xffff) 186 187 /* 188 * EEPROM offsets. 189 */ 190 #define STGE_EEPROM_ConfigParam 0x00 191 #define STGE_EEPROM_AsicCtrl 0x01 192 #define STGE_EEPROM_SubSystemVendorId 0x02 193 #define STGE_EEPROM_SubSystemId 0x03 194 #define STGE_EEPROM_LEDMode 0x06 195 #define STGE_EEPROM_StationAddress0 0x10 196 #define STGE_EEPROM_StationAddress1 0x11 197 #define STGE_EEPROM_StationAddress2 0x12 198 199 /* 200 * The TC9021 register space. 201 */ 202 203 #define STGE_DMACtrl 0x00 204 #define DMAC_RxDMAComplete (1U << 3) 205 #define DMAC_RxDMAPollNow (1U << 4) 206 #define DMAC_TxDMAComplete (1U << 11) 207 #define DMAC_TxDMAPollNow (1U << 12) 208 #define DMAC_TxDMAInProg (1U << 15) 209 #define DMAC_RxEarlyDisable (1U << 16) 210 #define DMAC_MWIDisable (1U << 18) 211 #define DMAC_TxWriteBackDisable (1U << 19) 212 #define DMAC_TxBurstLimit(x) ((x) << 20) 213 #define DMAC_TargetAbort (1U << 30) 214 #define DMAC_MasterAbort (1U << 31) 215 216 #define STGE_RxDMAStatus 0x08 217 218 #define STGE_TFDListPtrLo 0x10 219 220 #define STGE_TFDListPtrHi 0x14 221 222 #define STGE_TxDMABurstThresh 0x18 /* 8-bit */ 223 224 #define STGE_TxDMAUrgentThresh 0x19 /* 8-bit */ 225 226 #define STGE_TxDMAPollPeriod 0x1a /* 8-bit, 320ns increments */ 227 228 #define STGE_RFDListPtrLo 0x1c 229 230 #define STGE_RFDListPtrHi 0x20 231 232 #define STGE_RxDMABurstThresh 0x24 /* 8-bit */ 233 234 #define STGE_RxDMAUrgentThresh 0x25 /* 8-bit */ 235 236 #define STGE_RxDMAPollPeriod 0x26 /* 8-bit, 320ns increments */ 237 238 #define STGE_RxDMAIntCtrl 0x28 239 #define RDIC_RxFrameCount(x) ((x) & 0xff) 240 #define RDIC_PriorityThresh(x) ((x) << 10) 241 #define RDIC_RxDMAWaitTime(x) ((x) << 16) 242 /* 243 * Number of receive frames transferred via DMA before a Rx interrupt is issued. 244 */ 245 #define STGE_RXINT_NFRAME_DEFAULT 8 246 #define STGE_RXINT_NFRAME_MIN 1 247 #define STGE_RXINT_NFRAME_MAX 255 248 /* 249 * Maximum amount of time (in 64ns increments) to wait before issuing a Rx 250 * interrupt if number of frames recevied is less than STGE_RXINT_NFRAME 251 * (STGE_RXINT_NFRAME_MIN <= STGE_RXINT_NFRAME <= STGE_RXINT_NFRAME_MAX) 252 */ 253 #define STGE_RXINT_DMAWAIT_DEFAULT 30 /* 30us */ 254 #define STGE_RXINT_DMAWAIT_MIN 0 255 #define STGE_RXINT_DMAWAIT_MAX 4194 256 #define STGE_RXINT_USECS2TICK(x) (((x) * 1000)/64) 257 258 #define STGE_DebugCtrl 0x2c /* 16-bit */ 259 #define DC_GPIO0Ctrl (1U << 0) 260 #define DC_GPIO1Ctrl (1U << 1) 261 #define DC_GPIO0 (1U << 2) 262 #define DC_GPIO1 (1U << 3) 263 264 #define STGE_AsicCtrl 0x30 265 #define AC_ExpRomDisable (1U << 0) 266 #define AC_ExpRomSize (1U << 1) 267 #define AC_PhySpeed10 (1U << 4) 268 #define AC_PhySpeed100 (1U << 5) 269 #define AC_PhySpeed1000 (1U << 6) 270 #define AC_PhyMedia (1U << 7) 271 #define AC_ForcedConfig(x) ((x) << 8) 272 #define AC_ForcedConfig_MASK AC_ForcedConfig(7) 273 #define AC_D3ResetDisable (1U << 11) 274 #define AC_SpeedupMode (1U << 13) 275 #define AC_LEDMode (1U << 14) 276 #define AC_RstOutPolarity (1U << 15) 277 #define AC_GlobalReset (1U << 16) 278 #define AC_RxReset (1U << 17) 279 #define AC_TxReset (1U << 18) 280 #define AC_DMA (1U << 19) 281 #define AC_FIFO (1U << 20) 282 #define AC_Network (1U << 21) 283 #define AC_Host (1U << 22) 284 #define AC_AutoInit (1U << 23) 285 #define AC_RstOut (1U << 24) 286 #define AC_InterruptRequest (1U << 25) 287 #define AC_ResetBusy (1U << 26) 288 #define AC_LEDSpeed (1U << 27) 289 #define AC_LEDModeBit1 (1U << 29) 290 291 #define STGE_FIFOCtrl 0x38 /* 16-bit */ 292 #define FC_RAMTestMode (1U << 0) 293 #define FC_Transmitting (1U << 14) 294 #define FC_Receiving (1U << 15) 295 296 #define STGE_RxEarlyThresh 0x3a /* 16-bit */ 297 298 #define STGE_FlowOffThresh 0x3c /* 16-bit */ 299 300 #define STGE_FlowOnTresh 0x3e /* 16-bit */ 301 302 #define STGE_TxStartThresh 0x44 /* 16-bit */ 303 304 #define STGE_EepromData 0x48 /* 16-bit */ 305 306 #define STGE_EepromCtrl 0x4a /* 16-bit */ 307 #define EC_EepromAddress(x) ((x) & 0xff) 308 #define EC_EepromOpcode(x) ((x) << 8) 309 #define EC_OP_WE 0 310 #define EC_OP_WR 1 311 #define EC_OP_RR 2 312 #define EC_OP_ER 3 313 #define EC_EepromBusy (1U << 15) 314 315 #define STGE_ExpRomAddr 0x4c 316 317 #define STGE_ExpRomData 0x50 /* 8-bit */ 318 319 #define STGE_WakeEvent 0x51 /* 8-bit */ 320 321 #define STGE_Countdown 0x54 322 #define CD_Count(x) ((x) & 0xffff) 323 #define CD_CountdownSpeed (1U << 24) 324 #define CD_CountdownMode (1U << 25) 325 #define CD_CountdownIntEnabled (1U << 26) 326 327 #define STGE_IntStatusAck 0x5a /* 16-bit */ 328 329 #define STGE_IntEnable 0x5c /* 16-bit */ 330 331 #define STGE_IntStatus 0x5e /* 16-bit */ 332 333 #define IS_InterruptStatus (1U << 0) 334 #define IS_HostError (1U << 1) 335 #define IS_TxComplete (1U << 2) 336 #define IS_MACControlFrame (1U << 3) 337 #define IS_RxComplete (1U << 4) 338 #define IS_RxEarly (1U << 5) 339 #define IS_InRequested (1U << 6) 340 #define IS_UpdateStats (1U << 7) 341 #define IS_LinkEvent (1U << 8) 342 #define IS_TxDMAComplete (1U << 9) 343 #define IS_RxDMAComplete (1U << 10) 344 #define IS_RFDListEnd (1U << 11) 345 #define IS_RxDMAPriority (1U << 12) 346 347 #define STGE_TxStatus 0x60 348 #define TS_TxError (1U << 0) 349 #define TS_LateCollision (1U << 2) 350 #define TS_MaxCollisions (1U << 3) 351 #define TS_TxUnderrun (1U << 4) 352 #define TS_TxIndicateReqd (1U << 6) 353 #define TS_TxComplete (1U << 7) 354 #define TS_TxFrameId_get(x) ((x) >> 16) 355 356 #define STGE_MACCtrl 0x6c 357 #define MC_IFSSelect(x) ((x) & 3) 358 #define MC_IFS96bit 0 359 #define MC_IFS1024bit 1 360 #define MC_IFS1792bit 2 361 #define MC_IFS4352bit 3 362 363 #define MC_DuplexSelect (1U << 5) 364 #define MC_RcvLargeFrames (1U << 6) 365 #define MC_TxFlowControlEnable (1U << 7) 366 #define MC_RxFlowControlEnable (1U << 8) 367 #define MC_RcvFCS (1U << 9) 368 #define MC_FIFOLoopback (1U << 10) 369 #define MC_MACLoopback (1U << 11) 370 #define MC_AutoVLANtagging (1U << 12) 371 #define MC_AutoVLANuntagging (1U << 13) 372 #define MC_CollisionDetect (1U << 16) 373 #define MC_CarrierSense (1U << 17) 374 #define MC_StatisticsEnable (1U << 21) 375 #define MC_StatisticsDisable (1U << 22) 376 #define MC_StatisticsEnabled (1U << 23) 377 #define MC_TxEnable (1U << 24) 378 #define MC_TxDisable (1U << 25) 379 #define MC_TxEnabled (1U << 26) 380 #define MC_RxEnable (1U << 27) 381 #define MC_RxDisable (1U << 28) 382 #define MC_RxEnabled (1U << 29) 383 #define MC_Paused (1U << 30) 384 #define MC_MASK 0x7fe33fa3 385 386 #define STGE_VLANTag 0x70 387 388 #define STGE_PhySet 0x75 /* 8-bit */ 389 #define PS_MemLenb9b (1U << 0) 390 #define PS_MemLen (1U << 1) 391 #define PS_NonCompdet (1U << 2) 392 393 #define STGE_PhyCtrl 0x76 /* 8-bit */ 394 #define PC_MgmtClk (1U << 0) 395 #define PC_MgmtData (1U << 1) 396 #define PC_MgmtDir (1U << 2) /* MAC->PHY */ 397 #define PC_PhyDuplexPolarity (1U << 3) 398 #define PC_PhyDuplexStatus (1U << 4) 399 #define PC_PhyLnkPolarity (1U << 5) 400 #define PC_LinkSpeed(x) (((x) >> 6) & 3) 401 #define PC_LinkSpeed_Down 0 402 #define PC_LinkSpeed_10 1 403 #define PC_LinkSpeed_100 2 404 #define PC_LinkSpeed_1000 3 405 406 #define STGE_StationAddress0 0x78 /* 16-bit */ 407 408 #define STGE_StationAddress1 0x7a /* 16-bit */ 409 410 #define STGE_StationAddress2 0x7c /* 16-bit */ 411 412 #define STGE_VLANHashTable 0x7e /* 16-bit */ 413 414 #define STGE_VLANId 0x80 415 416 #define STGE_MaxFrameSize 0x86 417 418 #define STGE_ReceiveMode 0x88 /* 16-bit */ 419 #define RM_ReceiveUnicast (1U << 0) 420 #define RM_ReceiveMulticast (1U << 1) 421 #define RM_ReceiveBroadcast (1U << 2) 422 #define RM_ReceiveAllFrames (1U << 3) 423 #define RM_ReceiveMulticastHash (1U << 4) 424 #define RM_ReceiveIPMulticast (1U << 5) 425 #define RM_ReceiveVLANMatch (1U << 8) 426 #define RM_ReceiveVLANHash (1U << 9) 427 428 #define STGE_HashTable0 0x8c 429 430 #define STGE_HashTable1 0x90 431 432 #define STGE_RMONStatisticsMask 0x98 /* set to disable */ 433 434 #define STGE_StatisticsMask 0x9c /* set to disable */ 435 436 #define STGE_RxJumboFrames 0xbc /* 16-bit */ 437 438 #define STGE_TCPCheckSumErrors 0xc0 /* 16-bit */ 439 440 #define STGE_IPCheckSumErrors 0xc2 /* 16-bit */ 441 442 #define STGE_UDPCheckSumErrors 0xc4 /* 16-bit */ 443 444 #define STGE_TxJumboFrames 0xf4 /* 16-bit */ 445 446 /* 447 * TC9021 statistics. Available memory and I/O mapped. 448 */ 449 450 #define STGE_OctetRcvOk 0xa8 451 452 #define STGE_McstOctetRcvdOk 0xac 453 454 #define STGE_BcstOctetRcvdOk 0xb0 455 456 #define STGE_FramesRcvdOk 0xb4 457 458 #define STGE_McstFramesRcvdOk 0xb8 459 460 #define STGE_BcstFramesRcvdOk 0xbe /* 16-bit */ 461 462 #define STGE_MacControlFramesRcvd 0xc6 /* 16-bit */ 463 464 #define STGE_FrameTooLongErrors 0xc8 /* 16-bit */ 465 466 #define STGE_InRangeLengthErrors 0xca /* 16-bit */ 467 468 #define STGE_FramesCheckSeqErrors 0xcc /* 16-bit */ 469 470 #define STGE_FramesLostRxErrors 0xce /* 16-bit */ 471 472 #define STGE_OctetXmtdOk 0xd0 473 474 #define STGE_McstOctetXmtdOk 0xd4 475 476 #define STGE_BcstOctetXmtdOk 0xd8 477 478 #define STGE_FramesXmtdOk 0xdc 479 480 #define STGE_McstFramesXmtdOk 0xe0 481 482 #define STGE_FramesWDeferredXmt 0xe4 483 484 #define STGE_LateCollisions 0xe8 485 486 #define STGE_MultiColFrames 0xec 487 488 #define STGE_SingleColFrames 0xf0 489 490 #define STGE_BcstFramesXmtdOk 0xf6 /* 16-bit */ 491 492 #define STGE_CarrierSenseErrors 0xf8 /* 16-bit */ 493 494 #define STGE_MacControlFramesXmtd 0xfa /* 16-bit */ 495 496 #define STGE_FramesAbortXSColls 0xfc /* 16-bit */ 497 498 #define STGE_FramesWEXDeferal 0xfe /* 16-bit */ 499 500 /* 501 * RMON-compatible statistics. Only accessible if memory-mapped. 502 */ 503 504 #define STGE_EtherStatsCollisions 0x100 505 506 #define STGE_EtherStatsOctetsTransmit 0x104 507 508 #define STGE_EtherStatsPktsTransmit 0x108 509 510 #define STGE_EtherStatsPkts64OctetsTransmit 0x10c 511 512 #define STGE_EtherStatsPkts64to127OctetsTransmit 0x110 513 514 #define STGE_EtherStatsPkts128to255OctetsTransmit 0x114 515 516 #define STGE_EtherStatsPkts256to511OctetsTransmit 0x118 517 518 #define STGE_EtherStatsPkts512to1023OctetsTransmit 0x11c 519 520 #define STGE_EtherStatsPkts1024to1518OctetsTransmit 0x120 521 522 #define STGE_EtherStatsCRCAlignErrors 0x124 523 524 #define STGE_EtherStatsUndersizePkts 0x128 525 526 #define STGE_EtherStatsFragments 0x12c 527 528 #define STGE_EtherStatsJabbers 0x130 529 530 #define STGE_EtherStatsOctets 0x134 531 532 #define STGE_EtherStatsPkts 0x138 533 534 #define STGE_EtherStatsPkts64Octets 0x13c 535 536 #define STGE_EtherStatsPkts65to127Octets 0x140 537 538 #define STGE_EtherStatsPkts128to255Octets 0x144 539 540 #define STGE_EtherStatsPkts256to511Octets 0x148 541 542 #define STGE_EtherStatsPkts512to1023Octets 0x14c 543 544 #define STGE_EtherStatsPkts1024to1518Octets 0x150 545 546 /* 547 * MII constants 548 */ 549 #define STGE_MII_STARTDELIM 0x01 550 #define STGE_MII_READOP 0x02 551 #define STGE_MII_WRITEOP 0x01 552 #define STGE_MII_TURNAROUND 0x02 553 554 #define STGE_RESET_NONE 0x00 555 #define STGE_RESET_TX 0x01 556 #define STGE_RESET_RX 0x02 557 #define STGE_RESET_FULL 0x04 558