1 /* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: src/sys/pci/if_ti.c,v 1.25.2.14 2002/02/15 04:20:20 silby Exp $ 33 * $DragonFly: src/sys/dev/netif/ti/if_ti.c,v 1.42 2006/10/25 20:55:59 dillon Exp $ 34 */ 35 36 /* 37 * Alteon Networks Tigon PCI gigabit ethernet driver for FreeBSD. 38 * Manuals, sample driver and firmware source kits are available 39 * from http://www.alteon.com/support/openkits. 40 * 41 * Written by Bill Paul <wpaul@ctr.columbia.edu> 42 * Electrical Engineering Department 43 * Columbia University, New York City 44 */ 45 46 /* 47 * The Alteon Networks Tigon chip contains an embedded R4000 CPU, 48 * gigabit MAC, dual DMA channels and a PCI interface unit. NICs 49 * using the Tigon may have anywhere from 512K to 2MB of SRAM. The 50 * Tigon supports hardware IP, TCP and UCP checksumming, multicast 51 * filtering and jumbo (9014 byte) frames. The hardware is largely 52 * controlled by firmware, which must be loaded into the NIC during 53 * initialization. 54 * 55 * The Tigon 2 contains 2 R4000 CPUs and requires a newer firmware 56 * revision, which supports new features such as extended commands, 57 * extended jumbo receive ring desciptors and a mini receive ring. 58 * 59 * Alteon Networks is to be commended for releasing such a vast amount 60 * of development material for the Tigon NIC without requiring an NDA 61 * (although they really should have done it a long time ago). With 62 * any luck, the other vendors will finally wise up and follow Alteon's 63 * stellar example. 64 * 65 * The firmware for the Tigon 1 and 2 NICs is compiled directly into 66 * this driver by #including it as a C header file. This bloats the 67 * driver somewhat, but it's the easiest method considering that the 68 * driver code and firmware code need to be kept in sync. The source 69 * for the firmware is not provided with the FreeBSD distribution since 70 * compiling it requires a GNU toolchain targeted for mips-sgi-irix5.3. 71 * 72 * The following people deserve special thanks: 73 * - Terry Murphy of 3Com, for providing a 3c985 Tigon 1 board 74 * for testing 75 * - Raymond Lee of Netgear, for providing a pair of Netgear 76 * GA620 Tigon 2 boards for testing 77 * - Ulf Zimmermann, for bringing the GA260 to my attention and 78 * convincing me to write this driver. 79 * - Andrew Gallatin for providing FreeBSD/Alpha support. 80 */ 81 82 #include <sys/param.h> 83 #include <sys/systm.h> 84 #include <sys/sockio.h> 85 #include <sys/mbuf.h> 86 #include <sys/malloc.h> 87 #include <sys/kernel.h> 88 #include <sys/socket.h> 89 #include <sys/queue.h> 90 #include <sys/serialize.h> 91 #include <sys/bus.h> 92 #include <sys/rman.h> 93 #include <sys/thread2.h> 94 95 #include <net/if.h> 96 #include <net/ifq_var.h> 97 #include <net/if_arp.h> 98 #include <net/ethernet.h> 99 #include <net/if_dl.h> 100 #include <net/if_media.h> 101 #include <net/if_types.h> 102 #include <net/vlan/if_vlan_var.h> 103 104 #include <net/bpf.h> 105 106 #include <netinet/in_systm.h> 107 #include <netinet/in.h> 108 #include <netinet/ip.h> 109 110 #include <vm/vm.h> /* for vtophys */ 111 #include <vm/pmap.h> /* for vtophys */ 112 113 #include <bus/pci/pcireg.h> 114 #include <bus/pci/pcivar.h> 115 116 #include "if_tireg.h" 117 #include "ti_fw.h" 118 #include "ti_fw2.h" 119 120 /* 121 * Temporarily disable the checksum offload support for now. 122 * Tests with ftp.freesoftware.com show that after about 12 hours, 123 * the firmware will begin calculating completely bogus TX checksums 124 * and refuse to stop until the interface is reset. Unfortunately, 125 * there isn't enough time to fully debug this before the 4.1 126 * release, so this will need to stay off for now. 127 */ 128 #ifdef notdef 129 #define TI_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_IP_FRAGS) 130 #else 131 #define TI_CSUM_FEATURES 0 132 #endif 133 134 /* 135 * Various supported device vendors/types and their names. 136 */ 137 138 static struct ti_type ti_devs[] = { 139 { ALT_VENDORID, ALT_DEVICEID_ACENIC, 140 "Alteon AceNIC 1000baseSX Gigabit Ethernet" }, 141 { ALT_VENDORID, ALT_DEVICEID_ACENIC_COPPER, 142 "Alteon AceNIC 1000baseT Gigabit Ethernet" }, 143 { TC_VENDORID, TC_DEVICEID_3C985, 144 "3Com 3c985-SX Gigabit Ethernet" }, 145 { NG_VENDORID, NG_DEVICEID_GA620, 146 "Netgear GA620 1000baseSX Gigabit Ethernet" }, 147 { NG_VENDORID, NG_DEVICEID_GA620T, 148 "Netgear GA620 1000baseT Gigabit Ethernet" }, 149 { SGI_VENDORID, SGI_DEVICEID_TIGON, 150 "Silicon Graphics Gigabit Ethernet" }, 151 { DEC_VENDORID, DEC_DEVICEID_FARALLON_PN9000SX, 152 "Farallon PN9000SX Gigabit Ethernet" }, 153 { 0, 0, NULL } 154 }; 155 156 static int ti_probe(device_t); 157 static int ti_attach(device_t); 158 static int ti_detach(device_t); 159 static void ti_txeof(struct ti_softc *); 160 static void ti_rxeof(struct ti_softc *); 161 162 static void ti_stats_update(struct ti_softc *); 163 static int ti_encap(struct ti_softc *, struct mbuf *, uint32_t *); 164 165 static void ti_intr(void *); 166 static void ti_start(struct ifnet *); 167 static int ti_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *); 168 static void ti_init(void *); 169 static void ti_init2(struct ti_softc *); 170 static void ti_stop(struct ti_softc *); 171 static void ti_watchdog(struct ifnet *); 172 static void ti_shutdown(device_t); 173 static int ti_ifmedia_upd(struct ifnet *); 174 static void ti_ifmedia_sts(struct ifnet *, struct ifmediareq *); 175 176 static uint32_t ti_eeprom_putbyte(struct ti_softc *, int); 177 static uint8_t ti_eeprom_getbyte(struct ti_softc *, int, uint8_t *); 178 static int ti_read_eeprom(struct ti_softc *, caddr_t, int, int); 179 180 static void ti_add_mcast(struct ti_softc *, struct ether_addr *); 181 static void ti_del_mcast(struct ti_softc *, struct ether_addr *); 182 static void ti_setmulti(struct ti_softc *); 183 184 static void ti_mem(struct ti_softc *, uint32_t, uint32_t, caddr_t); 185 static void ti_loadfw(struct ti_softc *); 186 static void ti_cmd(struct ti_softc *, struct ti_cmd_desc *); 187 static void ti_cmd_ext(struct ti_softc *, struct ti_cmd_desc *, 188 caddr_t, int); 189 static void ti_handle_events(struct ti_softc *); 190 static int ti_alloc_jumbo_mem(struct ti_softc *); 191 static struct ti_jslot * 192 ti_jalloc(struct ti_softc *); 193 static void ti_jfree(void *); 194 static void ti_jref(void *); 195 static int ti_newbuf_std(struct ti_softc *, int, struct mbuf *); 196 static int ti_newbuf_mini(struct ti_softc *, int, struct mbuf *); 197 static int ti_newbuf_jumbo(struct ti_softc *, int, struct mbuf *); 198 static int ti_init_rx_ring_std(struct ti_softc *); 199 static void ti_free_rx_ring_std(struct ti_softc *); 200 static int ti_init_rx_ring_jumbo(struct ti_softc *); 201 static void ti_free_rx_ring_jumbo(struct ti_softc *); 202 static int ti_init_rx_ring_mini(struct ti_softc *); 203 static void ti_free_rx_ring_mini(struct ti_softc *); 204 static void ti_free_tx_ring(struct ti_softc *); 205 static int ti_init_tx_ring(struct ti_softc *); 206 207 static int ti_64bitslot_war(struct ti_softc *); 208 static int ti_chipinit(struct ti_softc *); 209 static int ti_gibinit(struct ti_softc *); 210 211 static device_method_t ti_methods[] = { 212 /* Device interface */ 213 DEVMETHOD(device_probe, ti_probe), 214 DEVMETHOD(device_attach, ti_attach), 215 DEVMETHOD(device_detach, ti_detach), 216 DEVMETHOD(device_shutdown, ti_shutdown), 217 { 0, 0 } 218 }; 219 220 221 static DEFINE_CLASS_0(ti, ti_driver, ti_methods, sizeof(struct ti_softc)); 222 static devclass_t ti_devclass; 223 224 DECLARE_DUMMY_MODULE(if_ti); 225 DRIVER_MODULE(if_ti, pci, ti_driver, ti_devclass, 0, 0); 226 227 /* 228 * Send an instruction or address to the EEPROM, check for ACK. 229 */ 230 static uint32_t 231 ti_eeprom_putbyte(struct ti_softc *sc, int byte) 232 { 233 int ack = 0, i; 234 235 /* 236 * Make sure we're in TX mode. 237 */ 238 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 239 240 /* 241 * Feed in each bit and stobe the clock. 242 */ 243 for (i = 0x80; i; i >>= 1) { 244 if (byte & i) 245 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); 246 else 247 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); 248 DELAY(1); 249 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 250 DELAY(1); 251 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 252 } 253 254 /* 255 * Turn off TX mode. 256 */ 257 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 258 259 /* 260 * Check for ack. 261 */ 262 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 263 ack = CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN; 264 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 265 266 return(ack); 267 } 268 269 /* 270 * Read a byte of data stored in the EEPROM at address 'addr.' 271 * We have to send two address bytes since the EEPROM can hold 272 * more than 256 bytes of data. 273 */ 274 static uint8_t 275 ti_eeprom_getbyte(struct ti_softc *sc, int addr, uint8_t *dest) 276 { 277 struct ifnet *ifp = &sc->arpcom.ac_if; 278 int i; 279 uint8_t byte = 0; 280 281 EEPROM_START; 282 283 /* 284 * Send write control code to EEPROM. 285 */ 286 if (ti_eeprom_putbyte(sc, EEPROM_CTL_WRITE)) { 287 if_printf(ifp, "failed to send write command, status: %x\n", 288 CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 289 return(1); 290 } 291 292 /* 293 * Send first byte of address of byte we want to read. 294 */ 295 if (ti_eeprom_putbyte(sc, (addr >> 8) & 0xFF)) { 296 if_printf(ifp, "failed to send address, status: %x\n", 297 CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 298 return(1); 299 } 300 /* 301 * Send second byte address of byte we want to read. 302 */ 303 if (ti_eeprom_putbyte(sc, addr & 0xFF)) { 304 if_printf(ifp, "failed to send address, status: %x\n", 305 CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 306 return(1); 307 } 308 309 EEPROM_STOP; 310 EEPROM_START; 311 /* 312 * Send read control code to EEPROM. 313 */ 314 if (ti_eeprom_putbyte(sc, EEPROM_CTL_READ)) { 315 if_printf(ifp, "failed to send read command, status: %x\n", 316 CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 317 return(1); 318 } 319 320 /* 321 * Start reading bits from EEPROM. 322 */ 323 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 324 for (i = 0x80; i; i >>= 1) { 325 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 326 DELAY(1); 327 if (CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN) 328 byte |= i; 329 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 330 DELAY(1); 331 } 332 333 EEPROM_STOP; 334 335 /* 336 * No ACK generated for read, so just return byte. 337 */ 338 339 *dest = byte; 340 341 return(0); 342 } 343 344 /* 345 * Read a sequence of bytes from the EEPROM. 346 */ 347 static int 348 ti_read_eeprom(struct ti_softc *sc, caddr_t dest, int off, int cnt) 349 { 350 int err = 0, i; 351 uint8_t byte = 0; 352 353 for (i = 0; i < cnt; i++) { 354 err = ti_eeprom_getbyte(sc, off + i, &byte); 355 if (err) 356 break; 357 *(dest + i) = byte; 358 } 359 360 return(err ? 1 : 0); 361 } 362 363 /* 364 * NIC memory access function. Can be used to either clear a section 365 * of NIC local memory or (if buf is non-NULL) copy data into it. 366 */ 367 static void 368 ti_mem(struct ti_softc *sc, uint32_t addr, uint32_t len, caddr_t buf) 369 { 370 int cnt, segptr, segsize; 371 caddr_t ti_winbase, ptr; 372 373 segptr = addr; 374 cnt = len; 375 ti_winbase = (caddr_t)(sc->ti_vhandle + TI_WINDOW); 376 ptr = buf; 377 378 while(cnt) { 379 if (cnt < TI_WINLEN) 380 segsize = cnt; 381 else 382 segsize = TI_WINLEN - (segptr % TI_WINLEN); 383 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1))); 384 if (buf == NULL) 385 bzero((char *)ti_winbase + (segptr & 386 (TI_WINLEN - 1)), segsize); 387 else { 388 bcopy((char *)ptr, (char *)ti_winbase + 389 (segptr & (TI_WINLEN - 1)), segsize); 390 ptr += segsize; 391 } 392 segptr += segsize; 393 cnt -= segsize; 394 } 395 } 396 397 /* 398 * Load firmware image into the NIC. Check that the firmware revision 399 * is acceptable and see if we want the firmware for the Tigon 1 or 400 * Tigon 2. 401 */ 402 static void 403 ti_loadfw(struct ti_softc *sc) 404 { 405 struct ifnet *ifp = &sc->arpcom.ac_if; 406 407 switch(sc->ti_hwrev) { 408 case TI_HWREV_TIGON: 409 if (tigonFwReleaseMajor != TI_FIRMWARE_MAJOR || 410 tigonFwReleaseMinor != TI_FIRMWARE_MINOR || 411 tigonFwReleaseFix != TI_FIRMWARE_FIX) { 412 if_printf(ifp, "firmware revision mismatch; want " 413 "%d.%d.%d, got %d.%d.%d\n", 414 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR, 415 TI_FIRMWARE_FIX, tigonFwReleaseMajor, 416 tigonFwReleaseMinor, tigonFwReleaseFix); 417 return; 418 } 419 ti_mem(sc, tigonFwTextAddr, tigonFwTextLen, 420 (caddr_t)tigonFwText); 421 ti_mem(sc, tigonFwDataAddr, tigonFwDataLen, 422 (caddr_t)tigonFwData); 423 ti_mem(sc, tigonFwRodataAddr, tigonFwRodataLen, 424 (caddr_t)tigonFwRodata); 425 ti_mem(sc, tigonFwBssAddr, tigonFwBssLen, NULL); 426 ti_mem(sc, tigonFwSbssAddr, tigonFwSbssLen, NULL); 427 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigonFwStartAddr); 428 break; 429 case TI_HWREV_TIGON_II: 430 if (tigon2FwReleaseMajor != TI_FIRMWARE_MAJOR || 431 tigon2FwReleaseMinor != TI_FIRMWARE_MINOR || 432 tigon2FwReleaseFix != TI_FIRMWARE_FIX) { 433 if_printf(ifp, "firmware revision mismatch; want " 434 "%d.%d.%d, got %d.%d.%d\n", 435 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR, 436 TI_FIRMWARE_FIX, tigon2FwReleaseMajor, 437 tigon2FwReleaseMinor, tigon2FwReleaseFix); 438 return; 439 } 440 ti_mem(sc, tigon2FwTextAddr, tigon2FwTextLen, 441 (caddr_t)tigon2FwText); 442 ti_mem(sc, tigon2FwDataAddr, tigon2FwDataLen, 443 (caddr_t)tigon2FwData); 444 ti_mem(sc, tigon2FwRodataAddr, tigon2FwRodataLen, 445 (caddr_t)tigon2FwRodata); 446 ti_mem(sc, tigon2FwBssAddr, tigon2FwBssLen, NULL); 447 ti_mem(sc, tigon2FwSbssAddr, tigon2FwSbssLen, NULL); 448 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigon2FwStartAddr); 449 break; 450 default: 451 if_printf(ifp, "can't load firmware: unknown hardware rev\n"); 452 break; 453 } 454 } 455 456 /* 457 * Send the NIC a command via the command ring. 458 */ 459 static void 460 ti_cmd(struct ti_softc *sc, struct ti_cmd_desc *cmd) 461 { 462 uint32_t index; 463 464 if (sc->ti_rdata->ti_cmd_ring == NULL) 465 return; 466 467 index = sc->ti_cmd_saved_prodidx; 468 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(uint32_t *)(cmd)); 469 TI_INC(index, TI_CMD_RING_CNT); 470 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index); 471 sc->ti_cmd_saved_prodidx = index; 472 } 473 474 /* 475 * Send the NIC an extended command. The 'len' parameter specifies the 476 * number of command slots to include after the initial command. 477 */ 478 static void 479 ti_cmd_ext(struct ti_softc *sc, struct ti_cmd_desc *cmd, caddr_t arg, int len) 480 { 481 uint32_t index; 482 int i; 483 484 if (sc->ti_rdata->ti_cmd_ring == NULL) 485 return; 486 487 index = sc->ti_cmd_saved_prodidx; 488 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(uint32_t *)(cmd)); 489 TI_INC(index, TI_CMD_RING_CNT); 490 for (i = 0; i < len; i++) { 491 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), 492 *(uint32_t *)(&arg[i * 4])); 493 TI_INC(index, TI_CMD_RING_CNT); 494 } 495 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index); 496 sc->ti_cmd_saved_prodidx = index; 497 } 498 499 /* 500 * Handle events that have triggered interrupts. 501 */ 502 static void 503 ti_handle_events(struct ti_softc *sc) 504 { 505 struct ifnet *ifp = &sc->arpcom.ac_if; 506 struct ti_event_desc *e; 507 508 if (sc->ti_rdata->ti_event_ring == NULL) 509 return; 510 511 while (sc->ti_ev_saved_considx != sc->ti_ev_prodidx.ti_idx) { 512 e = &sc->ti_rdata->ti_event_ring[sc->ti_ev_saved_considx]; 513 switch(e->ti_event) { 514 case TI_EV_LINKSTAT_CHANGED: 515 sc->ti_linkstat = e->ti_code; 516 if (e->ti_code == TI_EV_CODE_LINK_UP) { 517 if_printf(ifp, "10/100 link up\n"); 518 } else if (e->ti_code == TI_EV_CODE_GIG_LINK_UP) { 519 if_printf(ifp, "gigabit link up\n"); 520 } else if (e->ti_code == TI_EV_CODE_LINK_DOWN) { 521 if_printf(ifp, "link down\n"); 522 } 523 break; 524 case TI_EV_ERROR: 525 if (e->ti_code == TI_EV_CODE_ERR_INVAL_CMD) { 526 if_printf(ifp, "invalid command\n"); 527 } else if (e->ti_code == TI_EV_CODE_ERR_UNIMP_CMD) { 528 if_printf(ifp, "unknown command\n"); 529 } else if (e->ti_code == TI_EV_CODE_ERR_BADCFG) { 530 if_printf(ifp, "bad config data\n"); 531 } 532 break; 533 case TI_EV_FIRMWARE_UP: 534 ti_init2(sc); 535 break; 536 case TI_EV_STATS_UPDATED: 537 ti_stats_update(sc); 538 break; 539 case TI_EV_RESET_JUMBO_RING: 540 case TI_EV_MCAST_UPDATED: 541 /* Who cares. */ 542 break; 543 default: 544 if_printf(ifp, "unknown event: %d\n", e->ti_event); 545 break; 546 } 547 /* Advance the consumer index. */ 548 TI_INC(sc->ti_ev_saved_considx, TI_EVENT_RING_CNT); 549 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, sc->ti_ev_saved_considx); 550 } 551 } 552 553 /* 554 * Memory management for the jumbo receive ring is a pain in the 555 * butt. We need to allocate at least 9018 bytes of space per frame, 556 * _and_ it has to be contiguous (unless you use the extended 557 * jumbo descriptor format). Using malloc() all the time won't 558 * work: malloc() allocates memory in powers of two, which means we 559 * would end up wasting a considerable amount of space by allocating 560 * 9K chunks. We don't have a jumbo mbuf cluster pool. Thus, we have 561 * to do our own memory management. 562 * 563 * The driver needs to allocate a contiguous chunk of memory at boot 564 * time. We then chop this up ourselves into 9K pieces and use them 565 * as external mbuf storage. 566 * 567 * One issue here is how much memory to allocate. The jumbo ring has 568 * 256 slots in it, but at 9K per slot than can consume over 2MB of 569 * RAM. This is a bit much, especially considering we also need 570 * RAM for the standard ring and mini ring (on the Tigon 2). To 571 * save space, we only actually allocate enough memory for 64 slots 572 * by default, which works out to between 500 and 600K. This can 573 * be tuned by changing a #define in if_tireg.h. 574 */ 575 576 static int 577 ti_alloc_jumbo_mem(struct ti_softc *sc) 578 { 579 struct ti_jslot *entry; 580 caddr_t ptr; 581 int i; 582 583 /* Grab a big chunk o' storage. */ 584 sc->ti_cdata.ti_jumbo_buf = contigmalloc(TI_JMEM, M_DEVBUF, 585 M_WAITOK, 0, 0xffffffff, PAGE_SIZE, 0); 586 587 if (sc->ti_cdata.ti_jumbo_buf == NULL) { 588 if_printf(&sc->arpcom.ac_if, "no memory for jumbo buffers!\n"); 589 return(ENOBUFS); 590 } 591 592 SLIST_INIT(&sc->ti_jfree_listhead); 593 594 /* 595 * Now divide it up into 9K pieces and save the addresses 596 * in an array. Note that we play an evil trick here by using 597 * the first few bytes in the buffer to hold the the address 598 * of the softc structure for this interface. This is because 599 * ti_jfree() needs it, but it is called by the mbuf management 600 * code which will not pass it to us explicitly. 601 */ 602 ptr = sc->ti_cdata.ti_jumbo_buf; 603 for (i = 0; i < TI_JSLOTS; i++) { 604 entry = &sc->ti_cdata.ti_jslots[i]; 605 entry->ti_sc = sc; 606 entry->ti_buf = ptr; 607 entry->ti_inuse = 0; 608 entry->ti_slot = i; 609 SLIST_INSERT_HEAD(&sc->ti_jfree_listhead, entry, jslot_link); 610 ptr += TI_JLEN; 611 } 612 613 return(0); 614 } 615 616 /* 617 * Allocate a jumbo buffer. 618 */ 619 static struct ti_jslot * 620 ti_jalloc(struct ti_softc *sc) 621 { 622 struct ti_jslot *entry; 623 624 lwkt_serialize_enter(&sc->ti_jslot_serializer); 625 entry = SLIST_FIRST(&sc->ti_jfree_listhead); 626 if (entry) { 627 SLIST_REMOVE_HEAD(&sc->ti_jfree_listhead, jslot_link); 628 entry->ti_inuse = 1; 629 } else { 630 if_printf(&sc->arpcom.ac_if, "no free jumbo buffers\n"); 631 } 632 lwkt_serialize_exit(&sc->ti_jslot_serializer); 633 return(entry); 634 } 635 636 /* 637 * Adjust usage count on a jumbo buffer. In general this doesn't 638 * get used much because our jumbo buffers don't get passed around 639 * too much, but it's implemented for correctness. 640 */ 641 static void 642 ti_jref(void *arg) 643 { 644 struct ti_jslot *entry = (struct ti_jslot *)arg; 645 struct ti_softc *sc = entry->ti_sc; 646 647 if (sc == NULL) 648 panic("ti_jref: can't find softc pointer!"); 649 650 if (&sc->ti_cdata.ti_jslots[entry->ti_slot] != entry) 651 panic("ti_jref: asked to reference buffer " 652 "that we don't manage!"); 653 if (entry->ti_inuse == 0) 654 panic("ti_jref: buffer already free!"); 655 atomic_add_int(&entry->ti_inuse, 1); 656 } 657 658 /* 659 * Release a jumbo buffer. 660 */ 661 static void 662 ti_jfree(void *arg) 663 { 664 struct ti_jslot *entry = (struct ti_jslot *)arg; 665 struct ti_softc *sc = entry->ti_sc; 666 667 if (sc == NULL) 668 panic("ti_jref: can't find softc pointer!"); 669 670 if (&sc->ti_cdata.ti_jslots[entry->ti_slot] != entry) 671 panic("ti_jref: asked to reference buffer " 672 "that we don't manage!"); 673 if (entry->ti_inuse == 0) 674 panic("ti_jref: buffer already free!"); 675 lwkt_serialize_enter(&sc->ti_jslot_serializer); 676 atomic_subtract_int(&entry->ti_inuse, 1); 677 if (entry->ti_inuse == 0) 678 SLIST_INSERT_HEAD(&sc->ti_jfree_listhead, entry, jslot_link); 679 lwkt_serialize_exit(&sc->ti_jslot_serializer); 680 } 681 682 683 /* 684 * Intialize a standard receive ring descriptor. 685 */ 686 static int 687 ti_newbuf_std(struct ti_softc *sc, int i, struct mbuf *m) 688 { 689 struct mbuf *m_new; 690 struct ti_rx_desc *r; 691 692 if (m == NULL) { 693 m_new = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR); 694 if (m_new == NULL) 695 return (ENOBUFS); 696 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 697 } else { 698 m_new = m; 699 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 700 m_new->m_data = m_new->m_ext.ext_buf; 701 } 702 703 704 m_adj(m_new, ETHER_ALIGN); 705 sc->ti_cdata.ti_rx_std_chain[i] = m_new; 706 r = &sc->ti_rdata->ti_rx_std_ring[i]; 707 TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t)); 708 r->ti_type = TI_BDTYPE_RECV_BD; 709 r->ti_flags = 0; 710 if (sc->arpcom.ac_if.if_hwassist) 711 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM; 712 r->ti_len = m_new->m_len; 713 r->ti_idx = i; 714 715 return(0); 716 } 717 718 /* 719 * Intialize a mini receive ring descriptor. This only applies to 720 * the Tigon 2. 721 */ 722 static int 723 ti_newbuf_mini(struct ti_softc *sc, int i, struct mbuf *m) 724 { 725 struct mbuf *m_new; 726 struct ti_rx_desc *r; 727 728 if (m == NULL) { 729 MGETHDR(m_new, MB_DONTWAIT, MT_DATA); 730 if (m_new == NULL) { 731 return(ENOBUFS); 732 } 733 m_new->m_len = m_new->m_pkthdr.len = MHLEN; 734 } else { 735 m_new = m; 736 m_new->m_data = m_new->m_pktdat; 737 m_new->m_len = m_new->m_pkthdr.len = MHLEN; 738 } 739 740 m_adj(m_new, ETHER_ALIGN); 741 r = &sc->ti_rdata->ti_rx_mini_ring[i]; 742 sc->ti_cdata.ti_rx_mini_chain[i] = m_new; 743 TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t)); 744 r->ti_type = TI_BDTYPE_RECV_BD; 745 r->ti_flags = TI_BDFLAG_MINI_RING; 746 if (sc->arpcom.ac_if.if_hwassist) 747 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM; 748 r->ti_len = m_new->m_len; 749 r->ti_idx = i; 750 751 return(0); 752 } 753 754 /* 755 * Initialize a jumbo receive ring descriptor. This allocates 756 * a jumbo buffer from the pool managed internally by the driver. 757 */ 758 static int 759 ti_newbuf_jumbo(struct ti_softc *sc, int i, struct mbuf *m) 760 { 761 struct mbuf *m_new; 762 struct ti_rx_desc *r; 763 struct ti_jslot *buf; 764 765 if (m == NULL) { 766 /* Allocate the mbuf. */ 767 MGETHDR(m_new, MB_DONTWAIT, MT_DATA); 768 if (m_new == NULL) { 769 return(ENOBUFS); 770 } 771 772 /* Allocate the jumbo buffer */ 773 buf = ti_jalloc(sc); 774 if (buf == NULL) { 775 m_freem(m_new); 776 if_printf(&sc->arpcom.ac_if, "jumbo allocation failed " 777 "-- packet dropped!\n"); 778 return(ENOBUFS); 779 } 780 781 /* Attach the buffer to the mbuf. */ 782 m_new->m_ext.ext_arg = buf; 783 m_new->m_ext.ext_free = ti_jfree; 784 m_new->m_ext.ext_ref = ti_jref; 785 m_new->m_ext.ext_size = TI_JUMBO_FRAMELEN; 786 787 m_new->m_data = m_new->m_ext.ext_buf; 788 m_new->m_flags |= M_EXT; 789 m_new->m_len = m_new->m_pkthdr.len = m_new->m_ext.ext_size; 790 } else { 791 m_new = m; 792 m_new->m_data = m_new->m_ext.ext_buf; 793 m_new->m_ext.ext_size = TI_JUMBO_FRAMELEN; 794 } 795 796 m_adj(m_new, ETHER_ALIGN); 797 /* Set up the descriptor. */ 798 r = &sc->ti_rdata->ti_rx_jumbo_ring[i]; 799 sc->ti_cdata.ti_rx_jumbo_chain[i] = m_new; 800 TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t)); 801 r->ti_type = TI_BDTYPE_RECV_JUMBO_BD; 802 r->ti_flags = TI_BDFLAG_JUMBO_RING; 803 if (sc->arpcom.ac_if.if_hwassist) 804 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM; 805 r->ti_len = m_new->m_len; 806 r->ti_idx = i; 807 808 return(0); 809 } 810 811 /* 812 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 813 * that's 1MB or memory, which is a lot. For now, we fill only the first 814 * 256 ring entries and hope that our CPU is fast enough to keep up with 815 * the NIC. 816 */ 817 static int 818 ti_init_rx_ring_std(struct ti_softc *sc) 819 { 820 int i; 821 struct ti_cmd_desc cmd; 822 823 for (i = 0; i < TI_SSLOTS; i++) { 824 if (ti_newbuf_std(sc, i, NULL) == ENOBUFS) 825 return(ENOBUFS); 826 }; 827 828 TI_UPDATE_STDPROD(sc, i - 1); 829 sc->ti_std = i - 1; 830 831 return(0); 832 } 833 834 static void 835 ti_free_rx_ring_std(struct ti_softc *sc) 836 { 837 int i; 838 839 for (i = 0; i < TI_STD_RX_RING_CNT; i++) { 840 if (sc->ti_cdata.ti_rx_std_chain[i] != NULL) { 841 m_freem(sc->ti_cdata.ti_rx_std_chain[i]); 842 sc->ti_cdata.ti_rx_std_chain[i] = NULL; 843 } 844 bzero(&sc->ti_rdata->ti_rx_std_ring[i], 845 sizeof(struct ti_rx_desc)); 846 } 847 } 848 849 static int 850 ti_init_rx_ring_jumbo(struct ti_softc *sc) 851 { 852 int i; 853 struct ti_cmd_desc cmd; 854 855 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) { 856 if (ti_newbuf_jumbo(sc, i, NULL) == ENOBUFS) 857 return(ENOBUFS); 858 } 859 860 TI_UPDATE_JUMBOPROD(sc, i - 1); 861 sc->ti_jumbo = i - 1; 862 863 return(0); 864 } 865 866 static void 867 ti_free_rx_ring_jumbo(struct ti_softc *sc) 868 { 869 int i; 870 871 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) { 872 if (sc->ti_cdata.ti_rx_jumbo_chain[i] != NULL) { 873 m_freem(sc->ti_cdata.ti_rx_jumbo_chain[i]); 874 sc->ti_cdata.ti_rx_jumbo_chain[i] = NULL; 875 } 876 bzero(&sc->ti_rdata->ti_rx_jumbo_ring[i], 877 sizeof(struct ti_rx_desc)); 878 } 879 } 880 881 static int 882 ti_init_rx_ring_mini(struct ti_softc *sc) 883 { 884 int i; 885 886 for (i = 0; i < TI_MSLOTS; i++) { 887 if (ti_newbuf_mini(sc, i, NULL) == ENOBUFS) 888 return(ENOBUFS); 889 } 890 891 TI_UPDATE_MINIPROD(sc, i - 1); 892 sc->ti_mini = i - 1; 893 894 return(0); 895 } 896 897 static void 898 ti_free_rx_ring_mini(struct ti_softc *sc) 899 { 900 int i; 901 902 for (i = 0; i < TI_MINI_RX_RING_CNT; i++) { 903 if (sc->ti_cdata.ti_rx_mini_chain[i] != NULL) { 904 m_freem(sc->ti_cdata.ti_rx_mini_chain[i]); 905 sc->ti_cdata.ti_rx_mini_chain[i] = NULL; 906 } 907 bzero(&sc->ti_rdata->ti_rx_mini_ring[i], 908 sizeof(struct ti_rx_desc)); 909 } 910 } 911 912 static void 913 ti_free_tx_ring(struct ti_softc *sc) 914 { 915 int i; 916 917 if (sc->ti_rdata->ti_tx_ring == NULL) 918 return; 919 920 for (i = 0; i < TI_TX_RING_CNT; i++) { 921 if (sc->ti_cdata.ti_tx_chain[i] != NULL) { 922 m_freem(sc->ti_cdata.ti_tx_chain[i]); 923 sc->ti_cdata.ti_tx_chain[i] = NULL; 924 } 925 bzero(&sc->ti_rdata->ti_tx_ring[i], 926 sizeof(struct ti_tx_desc)); 927 } 928 } 929 930 static int 931 ti_init_tx_ring(struct ti_softc *sc) 932 { 933 sc->ti_txcnt = 0; 934 sc->ti_tx_saved_considx = 0; 935 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, 0); 936 return(0); 937 } 938 939 /* 940 * The Tigon 2 firmware has a new way to add/delete multicast addresses, 941 * but we have to support the old way too so that Tigon 1 cards will 942 * work. 943 */ 944 static void 945 ti_add_mcast(struct ti_softc *sc, struct ether_addr *addr) 946 { 947 struct ti_cmd_desc cmd; 948 uint16_t *m; 949 uint32_t ext[2] = {0, 0}; 950 951 m = (uint16_t *)&addr->octet[0]; 952 953 switch(sc->ti_hwrev) { 954 case TI_HWREV_TIGON: 955 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0])); 956 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2])); 957 TI_DO_CMD(TI_CMD_ADD_MCAST_ADDR, 0, 0); 958 break; 959 case TI_HWREV_TIGON_II: 960 ext[0] = htons(m[0]); 961 ext[1] = (htons(m[1]) << 16) | htons(m[2]); 962 TI_DO_CMD_EXT(TI_CMD_EXT_ADD_MCAST, 0, 0, (caddr_t)&ext, 2); 963 break; 964 default: 965 if_printf(&sc->arpcom.ac_if, "unknown hwrev\n"); 966 break; 967 } 968 } 969 970 static void 971 ti_del_mcast(struct ti_softc *sc, struct ether_addr *addr) 972 { 973 struct ti_cmd_desc cmd; 974 uint16_t *m; 975 uint32_t ext[2] = {0, 0}; 976 977 m = (uint16_t *)&addr->octet[0]; 978 979 switch(sc->ti_hwrev) { 980 case TI_HWREV_TIGON: 981 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0])); 982 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2])); 983 TI_DO_CMD(TI_CMD_DEL_MCAST_ADDR, 0, 0); 984 break; 985 case TI_HWREV_TIGON_II: 986 ext[0] = htons(m[0]); 987 ext[1] = (htons(m[1]) << 16) | htons(m[2]); 988 TI_DO_CMD_EXT(TI_CMD_EXT_DEL_MCAST, 0, 0, (caddr_t)&ext, 2); 989 break; 990 default: 991 if_printf(&sc->arpcom.ac_if, "unknown hwrev\n"); 992 break; 993 } 994 } 995 996 /* 997 * Configure the Tigon's multicast address filter. 998 * 999 * The actual multicast table management is a bit of a pain, thanks to 1000 * slight brain damage on the part of both Alteon and us. With our 1001 * multicast code, we are only alerted when the multicast address table 1002 * changes and at that point we only have the current list of addresses: 1003 * we only know the current state, not the previous state, so we don't 1004 * actually know what addresses were removed or added. The firmware has 1005 * state, but we can't get our grubby mits on it, and there is no 'delete 1006 * all multicast addresses' command. Hence, we have to maintain our own 1007 * state so we know what addresses have been programmed into the NIC at 1008 * any given time. 1009 */ 1010 static void 1011 ti_setmulti(struct ti_softc *sc) 1012 { 1013 struct ifnet *ifp = &sc->arpcom.ac_if; 1014 struct ifmultiaddr *ifma; 1015 struct ti_cmd_desc cmd; 1016 struct ti_mc_entry *mc; 1017 uint32_t intrs; 1018 1019 if (ifp->if_flags & IFF_ALLMULTI) { 1020 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_ENB, 0); 1021 return; 1022 } 1023 1024 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_DIS, 0); 1025 1026 /* Disable interrupts. */ 1027 intrs = CSR_READ_4(sc, TI_MB_HOSTINTR); 1028 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 1029 1030 /* First, zot all the existing filters. */ 1031 while (sc->ti_mc_listhead.slh_first != NULL) { 1032 mc = sc->ti_mc_listhead.slh_first; 1033 ti_del_mcast(sc, &mc->mc_addr); 1034 SLIST_REMOVE_HEAD(&sc->ti_mc_listhead, mc_entries); 1035 kfree(mc, M_DEVBUF); 1036 } 1037 1038 /* Now program new ones. */ 1039 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1040 if (ifma->ifma_addr->sa_family != AF_LINK) 1041 continue; 1042 mc = kmalloc(sizeof(struct ti_mc_entry), M_DEVBUF, M_INTWAIT); 1043 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 1044 &mc->mc_addr, ETHER_ADDR_LEN); 1045 SLIST_INSERT_HEAD(&sc->ti_mc_listhead, mc, mc_entries); 1046 ti_add_mcast(sc, &mc->mc_addr); 1047 } 1048 1049 /* Re-enable interrupts. */ 1050 CSR_WRITE_4(sc, TI_MB_HOSTINTR, intrs); 1051 } 1052 1053 /* 1054 * Check to see if the BIOS has configured us for a 64 bit slot when 1055 * we aren't actually in one. If we detect this condition, we can work 1056 * around it on the Tigon 2 by setting a bit in the PCI state register, 1057 * but for the Tigon 1 we must give up and abort the interface attach. 1058 */ 1059 static int 1060 ti_64bitslot_war(struct ti_softc *sc) 1061 { 1062 if ((CSR_READ_4(sc, TI_PCI_STATE) & TI_PCISTATE_32BIT_BUS) == 0) { 1063 CSR_WRITE_4(sc, 0x600, 0); 1064 CSR_WRITE_4(sc, 0x604, 0); 1065 CSR_WRITE_4(sc, 0x600, 0x5555AAAA); 1066 if (CSR_READ_4(sc, 0x604) == 0x5555AAAA) { 1067 if (sc->ti_hwrev == TI_HWREV_TIGON) 1068 return(EINVAL); 1069 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_32BIT_BUS); 1070 return(0); 1071 } 1072 } 1073 1074 return(0); 1075 } 1076 1077 /* 1078 * Do endian, PCI and DMA initialization. Also check the on-board ROM 1079 * self-test results. 1080 */ 1081 static int 1082 ti_chipinit(struct ti_softc *sc) 1083 { 1084 struct ifnet *ifp = &sc->arpcom.ac_if; 1085 uint32_t cacheline; 1086 uint32_t pci_writemax = 0; 1087 1088 /* Initialize link to down state. */ 1089 sc->ti_linkstat = TI_EV_CODE_LINK_DOWN; 1090 1091 if (ifp->if_capenable & IFCAP_HWCSUM) 1092 ifp->if_hwassist = TI_CSUM_FEATURES; 1093 else 1094 ifp->if_hwassist = 0; 1095 1096 /* Set endianness before we access any non-PCI registers. */ 1097 #if BYTE_ORDER == BIG_ENDIAN 1098 CSR_WRITE_4(sc, TI_MISC_HOST_CTL, 1099 TI_MHC_BIGENDIAN_INIT | (TI_MHC_BIGENDIAN_INIT << 24)); 1100 #else 1101 CSR_WRITE_4(sc, TI_MISC_HOST_CTL, 1102 TI_MHC_LITTLEENDIAN_INIT | (TI_MHC_LITTLEENDIAN_INIT << 24)); 1103 #endif 1104 1105 /* Check the ROM failed bit to see if self-tests passed. */ 1106 if (CSR_READ_4(sc, TI_CPU_STATE) & TI_CPUSTATE_ROMFAIL) { 1107 if_printf(ifp, "board self-diagnostics failed!\n"); 1108 return(ENODEV); 1109 } 1110 1111 /* Halt the CPU. */ 1112 TI_SETBIT(sc, TI_CPU_STATE, TI_CPUSTATE_HALT); 1113 1114 /* Figure out the hardware revision. */ 1115 switch(CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_CHIP_REV_MASK) { 1116 case TI_REV_TIGON_I: 1117 sc->ti_hwrev = TI_HWREV_TIGON; 1118 break; 1119 case TI_REV_TIGON_II: 1120 sc->ti_hwrev = TI_HWREV_TIGON_II; 1121 break; 1122 default: 1123 if_printf(ifp, "unsupported chip revision\n"); 1124 return(ENODEV); 1125 } 1126 1127 /* Do special setup for Tigon 2. */ 1128 if (sc->ti_hwrev == TI_HWREV_TIGON_II) { 1129 TI_SETBIT(sc, TI_CPU_CTL_B, TI_CPUSTATE_HALT); 1130 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_SRAM_BANK_512K); 1131 TI_SETBIT(sc, TI_MISC_CONF, TI_MCR_SRAM_SYNCHRONOUS); 1132 } 1133 1134 /* Set up the PCI state register. */ 1135 CSR_WRITE_4(sc, TI_PCI_STATE, TI_PCI_READ_CMD|TI_PCI_WRITE_CMD); 1136 if (sc->ti_hwrev == TI_HWREV_TIGON_II) { 1137 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_USE_MEM_RD_MULT); 1138 } 1139 1140 /* Clear the read/write max DMA parameters. */ 1141 TI_CLRBIT(sc, TI_PCI_STATE, (TI_PCISTATE_WRITE_MAXDMA| 1142 TI_PCISTATE_READ_MAXDMA)); 1143 1144 /* Get cache line size. */ 1145 cacheline = CSR_READ_4(sc, TI_PCI_BIST) & 0xFF; 1146 1147 /* 1148 * If the system has set enabled the PCI memory write 1149 * and invalidate command in the command register, set 1150 * the write max parameter accordingly. This is necessary 1151 * to use MWI with the Tigon 2. 1152 */ 1153 if (CSR_READ_4(sc, TI_PCI_CMDSTAT) & PCIM_CMD_MWIEN) { 1154 switch(cacheline) { 1155 case 1: 1156 case 4: 1157 case 8: 1158 case 16: 1159 case 32: 1160 case 64: 1161 break; 1162 default: 1163 /* Disable PCI memory write and invalidate. */ 1164 if (bootverbose) { 1165 if_printf(ifp, "cache line size %d not " 1166 "supported; disabling PCI MWI\n", 1167 cacheline); 1168 } 1169 CSR_WRITE_4(sc, TI_PCI_CMDSTAT, CSR_READ_4(sc, 1170 TI_PCI_CMDSTAT) & ~PCIM_CMD_MWIEN); 1171 break; 1172 } 1173 } 1174 1175 TI_SETBIT(sc, TI_PCI_STATE, pci_writemax); 1176 1177 /* This sets the min dma param all the way up (0xff). */ 1178 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_MINDMA); 1179 1180 /* Configure DMA variables. */ 1181 #if BYTE_ORDER == BIG_ENDIAN 1182 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_BD | 1183 TI_OPMODE_BYTESWAP_DATA | TI_OPMODE_WORDSWAP_BD | 1184 TI_OPMODE_WARN_ENB | TI_OPMODE_FATAL_ENB | 1185 TI_OPMODE_DONT_FRAG_JUMBO); 1186 #else 1187 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_DATA| 1188 TI_OPMODE_WORDSWAP_BD|TI_OPMODE_DONT_FRAG_JUMBO| 1189 TI_OPMODE_WARN_ENB|TI_OPMODE_FATAL_ENB); 1190 #endif 1191 1192 /* 1193 * Only allow 1 DMA channel to be active at a time. 1194 * I don't think this is a good idea, but without it 1195 * the firmware racks up lots of nicDmaReadRingFull 1196 * errors. This is not compatible with hardware checksums. 1197 */ 1198 if (ifp->if_hwassist == 0) 1199 TI_SETBIT(sc, TI_GCR_OPMODE, TI_OPMODE_1_DMA_ACTIVE); 1200 1201 /* Recommended settings from Tigon manual. */ 1202 CSR_WRITE_4(sc, TI_GCR_DMA_WRITECFG, TI_DMA_STATE_THRESH_8W); 1203 CSR_WRITE_4(sc, TI_GCR_DMA_READCFG, TI_DMA_STATE_THRESH_8W); 1204 1205 if (ti_64bitslot_war(sc)) { 1206 if_printf(ifp, "bios thinks we're in a 64 bit slot, " 1207 "but we aren't"); 1208 return(EINVAL); 1209 } 1210 1211 return(0); 1212 } 1213 1214 /* 1215 * Initialize the general information block and firmware, and 1216 * start the CPU(s) running. 1217 */ 1218 static int 1219 ti_gibinit(struct ti_softc *sc) 1220 { 1221 struct ifnet *ifp = &sc->arpcom.ac_if; 1222 struct ti_rcb *rcb; 1223 int i; 1224 1225 /* Disable interrupts for now. */ 1226 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 1227 1228 /* Tell the chip where to find the general information block. */ 1229 CSR_WRITE_4(sc, TI_GCR_GENINFO_HI, 0); 1230 CSR_WRITE_4(sc, TI_GCR_GENINFO_LO, vtophys(&sc->ti_rdata->ti_info)); 1231 1232 /* Load the firmware into SRAM. */ 1233 ti_loadfw(sc); 1234 1235 /* Set up the contents of the general info and ring control blocks. */ 1236 1237 /* Set up the event ring and producer pointer. */ 1238 rcb = &sc->ti_rdata->ti_info.ti_ev_rcb; 1239 1240 TI_HOSTADDR(rcb->ti_hostaddr) = vtophys(&sc->ti_rdata->ti_event_ring); 1241 rcb->ti_flags = 0; 1242 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_ev_prodidx_ptr) = 1243 vtophys(&sc->ti_ev_prodidx); 1244 sc->ti_ev_prodidx.ti_idx = 0; 1245 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, 0); 1246 sc->ti_ev_saved_considx = 0; 1247 1248 /* Set up the command ring and producer mailbox. */ 1249 rcb = &sc->ti_rdata->ti_info.ti_cmd_rcb; 1250 1251 sc->ti_rdata->ti_cmd_ring = 1252 (struct ti_cmd_desc *)(sc->ti_vhandle + TI_GCR_CMDRING); 1253 TI_HOSTADDR(rcb->ti_hostaddr) = TI_GCR_NIC_ADDR(TI_GCR_CMDRING); 1254 rcb->ti_flags = 0; 1255 rcb->ti_max_len = 0; 1256 for (i = 0; i < TI_CMD_RING_CNT; i++) 1257 CSR_WRITE_4(sc, TI_GCR_CMDRING + (i * 4), 0); 1258 CSR_WRITE_4(sc, TI_GCR_CMDCONS_IDX, 0); 1259 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, 0); 1260 sc->ti_cmd_saved_prodidx = 0; 1261 1262 /* 1263 * Assign the address of the stats refresh buffer. 1264 * We re-use the current stats buffer for this to 1265 * conserve memory. 1266 */ 1267 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_refresh_stats_ptr) = 1268 vtophys(&sc->ti_rdata->ti_info.ti_stats); 1269 1270 /* Set up the standard receive ring. */ 1271 rcb = &sc->ti_rdata->ti_info.ti_std_rx_rcb; 1272 TI_HOSTADDR(rcb->ti_hostaddr) = vtophys(&sc->ti_rdata->ti_rx_std_ring); 1273 rcb->ti_max_len = TI_FRAMELEN; 1274 rcb->ti_flags = 0; 1275 if (ifp->if_hwassist) 1276 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 1277 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 1278 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1279 1280 /* Set up the jumbo receive ring. */ 1281 rcb = &sc->ti_rdata->ti_info.ti_jumbo_rx_rcb; 1282 TI_HOSTADDR(rcb->ti_hostaddr) = 1283 vtophys(&sc->ti_rdata->ti_rx_jumbo_ring); 1284 rcb->ti_max_len = TI_JUMBO_FRAMELEN; 1285 rcb->ti_flags = 0; 1286 if (ifp->if_hwassist) 1287 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 1288 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 1289 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1290 1291 /* 1292 * Set up the mini ring. Only activated on the 1293 * Tigon 2 but the slot in the config block is 1294 * still there on the Tigon 1. 1295 */ 1296 rcb = &sc->ti_rdata->ti_info.ti_mini_rx_rcb; 1297 TI_HOSTADDR(rcb->ti_hostaddr) = 1298 vtophys(&sc->ti_rdata->ti_rx_mini_ring); 1299 rcb->ti_max_len = MHLEN - ETHER_ALIGN; 1300 if (sc->ti_hwrev == TI_HWREV_TIGON) 1301 rcb->ti_flags = TI_RCB_FLAG_RING_DISABLED; 1302 else 1303 rcb->ti_flags = 0; 1304 if (ifp->if_hwassist) 1305 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 1306 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 1307 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1308 1309 /* 1310 * Set up the receive return ring. 1311 */ 1312 rcb = &sc->ti_rdata->ti_info.ti_return_rcb; 1313 TI_HOSTADDR(rcb->ti_hostaddr) = 1314 vtophys(&sc->ti_rdata->ti_rx_return_ring); 1315 rcb->ti_flags = 0; 1316 rcb->ti_max_len = TI_RETURN_RING_CNT; 1317 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_return_prodidx_ptr) = 1318 vtophys(&sc->ti_return_prodidx); 1319 1320 /* 1321 * Set up the tx ring. Note: for the Tigon 2, we have the option 1322 * of putting the transmit ring in the host's address space and 1323 * letting the chip DMA it instead of leaving the ring in the NIC's 1324 * memory and accessing it through the shared memory region. We 1325 * do this for the Tigon 2, but it doesn't work on the Tigon 1, 1326 * so we have to revert to the shared memory scheme if we detect 1327 * a Tigon 1 chip. 1328 */ 1329 CSR_WRITE_4(sc, TI_WINBASE, TI_TX_RING_BASE); 1330 if (sc->ti_hwrev == TI_HWREV_TIGON) { 1331 sc->ti_rdata->ti_tx_ring_nic = 1332 (struct ti_tx_desc *)(sc->ti_vhandle + TI_WINDOW); 1333 } 1334 bzero(sc->ti_rdata->ti_tx_ring, 1335 TI_TX_RING_CNT * sizeof(struct ti_tx_desc)); 1336 rcb = &sc->ti_rdata->ti_info.ti_tx_rcb; 1337 if (sc->ti_hwrev == TI_HWREV_TIGON) 1338 rcb->ti_flags = 0; 1339 else 1340 rcb->ti_flags = TI_RCB_FLAG_HOST_RING; 1341 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1342 if (ifp->if_hwassist) 1343 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 1344 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 1345 rcb->ti_max_len = TI_TX_RING_CNT; 1346 if (sc->ti_hwrev == TI_HWREV_TIGON) 1347 TI_HOSTADDR(rcb->ti_hostaddr) = TI_TX_RING_BASE; 1348 else 1349 TI_HOSTADDR(rcb->ti_hostaddr) = 1350 vtophys(&sc->ti_rdata->ti_tx_ring); 1351 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_tx_considx_ptr) = 1352 vtophys(&sc->ti_tx_considx); 1353 1354 /* Set up tuneables */ 1355 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 1356 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, 1357 (sc->ti_rx_coal_ticks / 10)); 1358 else 1359 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, sc->ti_rx_coal_ticks); 1360 CSR_WRITE_4(sc, TI_GCR_TX_COAL_TICKS, sc->ti_tx_coal_ticks); 1361 CSR_WRITE_4(sc, TI_GCR_STAT_TICKS, sc->ti_stat_ticks); 1362 CSR_WRITE_4(sc, TI_GCR_RX_MAX_COAL_BD, sc->ti_rx_max_coal_bds); 1363 CSR_WRITE_4(sc, TI_GCR_TX_MAX_COAL_BD, sc->ti_tx_max_coal_bds); 1364 CSR_WRITE_4(sc, TI_GCR_TX_BUFFER_RATIO, sc->ti_tx_buf_ratio); 1365 1366 /* Turn interrupts on. */ 1367 CSR_WRITE_4(sc, TI_GCR_MASK_INTRS, 0); 1368 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 1369 1370 /* Start CPU. */ 1371 TI_CLRBIT(sc, TI_CPU_STATE, (TI_CPUSTATE_HALT|TI_CPUSTATE_STEP)); 1372 1373 return(0); 1374 } 1375 1376 /* 1377 * Probe for a Tigon chip. Check the PCI vendor and device IDs 1378 * against our list and return its name if we find a match. 1379 */ 1380 static int 1381 ti_probe(device_t dev) 1382 { 1383 struct ti_type *t; 1384 uint16_t vendor, product; 1385 1386 vendor = pci_get_vendor(dev); 1387 product = pci_get_device(dev); 1388 1389 for (t = ti_devs; t->ti_name != NULL; t++) { 1390 if (vendor == t->ti_vid && product == t->ti_did) { 1391 device_set_desc(dev, t->ti_name); 1392 return(0); 1393 } 1394 } 1395 1396 return(ENXIO); 1397 } 1398 1399 static int 1400 ti_attach(device_t dev) 1401 { 1402 struct ti_softc *sc; 1403 struct ifnet *ifp; 1404 int error = 0, rid; 1405 uint8_t eaddr[ETHER_ADDR_LEN]; 1406 1407 sc = device_get_softc(dev); 1408 ifp = &sc->arpcom.ac_if; 1409 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1410 ifp->if_capabilities = IFCAP_HWCSUM; 1411 ifp->if_capenable = ifp->if_capabilities; 1412 1413 pci_enable_busmaster(dev); 1414 1415 /* 1416 * Initialize media before any possible error may occur, 1417 * so we can destroy it unconditionally, if an error occurs later on. 1418 */ 1419 ifmedia_init(&sc->ifmedia, IFM_IMASK, ti_ifmedia_upd, ti_ifmedia_sts); 1420 1421 rid = TI_PCI_LOMEM; 1422 sc->ti_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 1423 RF_ACTIVE); 1424 1425 if (sc->ti_res == NULL) { 1426 device_printf(dev, "couldn't map memory\n"); 1427 error = ENXIO; 1428 goto fail; 1429 } 1430 1431 sc->ti_btag = rman_get_bustag(sc->ti_res); 1432 sc->ti_bhandle = rman_get_bushandle(sc->ti_res); 1433 sc->ti_vhandle = (vm_offset_t)rman_get_virtual(sc->ti_res); 1434 1435 /* Allocate interrupt */ 1436 rid = 0; 1437 sc->ti_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1438 RF_SHAREABLE | RF_ACTIVE); 1439 if (sc->ti_irq == NULL) { 1440 device_printf(dev, "couldn't map interrupt\n"); 1441 error = ENXIO; 1442 goto fail; 1443 } 1444 1445 if (ti_chipinit(sc)) { 1446 device_printf(dev, "chip initialization failed\n"); 1447 error = ENXIO; 1448 goto fail; 1449 } 1450 1451 /* Zero out the NIC's on-board SRAM. */ 1452 ti_mem(sc, 0x2000, 0x100000 - 0x2000, NULL); 1453 1454 /* Init again -- zeroing memory may have clobbered some registers. */ 1455 if (ti_chipinit(sc)) { 1456 device_printf(dev, "chip initialization failed\n"); 1457 error = ENXIO; 1458 goto fail; 1459 } 1460 1461 /* 1462 * Get station address from the EEPROM. Note: the manual states 1463 * that the MAC address is at offset 0x8c, however the data is 1464 * stored as two longwords (since that's how it's loaded into 1465 * the NIC). This means the MAC address is actually preceeded 1466 * by two zero bytes. We need to skip over those. 1467 */ 1468 if (ti_read_eeprom(sc, eaddr, TI_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) { 1469 device_printf(dev, "failed to read station address\n"); 1470 error = ENXIO; 1471 goto fail; 1472 } 1473 1474 /* Allocate the general information block and ring buffers. */ 1475 sc->ti_rdata = contigmalloc(sizeof(struct ti_ring_data), M_DEVBUF, 1476 M_WAITOK, 0, 0xffffffff, PAGE_SIZE, 0); 1477 1478 if (sc->ti_rdata == NULL) { 1479 device_printf(dev, "no memory for list buffers!\n"); 1480 error = ENXIO; 1481 goto fail; 1482 } 1483 1484 bzero(sc->ti_rdata, sizeof(struct ti_ring_data)); 1485 1486 /* Try to allocate memory for jumbo buffers. */ 1487 if (ti_alloc_jumbo_mem(sc)) { 1488 device_printf(dev, "jumbo buffer allocation failed\n"); 1489 error = ENXIO; 1490 goto fail; 1491 } 1492 1493 /* 1494 * We really need a better way to tell a 1000baseTX card 1495 * from a 1000baseSX one, since in theory there could be 1496 * OEMed 1000baseTX cards from lame vendors who aren't 1497 * clever enough to change the PCI ID. For the moment 1498 * though, the AceNIC is the only copper card available. 1499 */ 1500 if (pci_get_vendor(dev) == ALT_VENDORID && 1501 pci_get_device(dev) == ALT_DEVICEID_ACENIC_COPPER) 1502 sc->ti_copper = 1; 1503 /* Ok, it's not the only copper card available. */ 1504 if (pci_get_vendor(dev) == NG_VENDORID && 1505 pci_get_device(dev) == NG_DEVICEID_GA620T) 1506 sc->ti_copper = 1; 1507 1508 /* Set default tuneable values. */ 1509 sc->ti_stat_ticks = 2 * TI_TICKS_PER_SEC; 1510 sc->ti_rx_coal_ticks = TI_TICKS_PER_SEC / 5000; 1511 sc->ti_tx_coal_ticks = TI_TICKS_PER_SEC / 500; 1512 sc->ti_rx_max_coal_bds = 64; 1513 sc->ti_tx_max_coal_bds = 128; 1514 sc->ti_tx_buf_ratio = 21; 1515 1516 /* Set up ifnet structure */ 1517 ifp->if_softc = sc; 1518 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1519 ifp->if_ioctl = ti_ioctl; 1520 ifp->if_start = ti_start; 1521 ifp->if_watchdog = ti_watchdog; 1522 ifp->if_init = ti_init; 1523 ifp->if_mtu = ETHERMTU; 1524 ifq_set_maxlen(&ifp->if_snd, TI_TX_RING_CNT - 1); 1525 ifq_set_ready(&ifp->if_snd); 1526 1527 /* Set up ifmedia support. */ 1528 if (sc->ti_copper) { 1529 /* 1530 * Copper cards allow manual 10/100 mode selection, 1531 * but not manual 1000baseTX mode selection. Why? 1532 * Becuase currently there's no way to specify the 1533 * master/slave setting through the firmware interface, 1534 * so Alteon decided to just bag it and handle it 1535 * via autonegotiation. 1536 */ 1537 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL); 1538 ifmedia_add(&sc->ifmedia, 1539 IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL); 1540 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_TX, 0, NULL); 1541 ifmedia_add(&sc->ifmedia, 1542 IFM_ETHER|IFM_100_TX|IFM_FDX, 0, NULL); 1543 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_1000_T, 0, NULL); 1544 ifmedia_add(&sc->ifmedia, 1545 IFM_ETHER|IFM_1000_T | IFM_FDX, 0, NULL); 1546 } else { 1547 /* Fiber cards don't support 10/100 modes. */ 1548 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL); 1549 ifmedia_add(&sc->ifmedia, 1550 IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL); 1551 } 1552 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 1553 ifmedia_set(&sc->ifmedia, IFM_ETHER|IFM_AUTO); 1554 1555 /* 1556 * Call MI attach routine. 1557 */ 1558 ether_ifattach(ifp, eaddr, NULL); 1559 1560 error = bus_setup_intr(dev, sc->ti_irq, INTR_NETSAFE, 1561 ti_intr, sc, &sc->ti_intrhand, 1562 ifp->if_serializer); 1563 if (error) { 1564 device_printf(dev, "couldn't set up irq\n"); 1565 ether_ifdetach(ifp); 1566 goto fail; 1567 } 1568 return 0; 1569 1570 fail: 1571 ti_detach(dev); 1572 return(error); 1573 } 1574 1575 static int 1576 ti_detach(device_t dev) 1577 { 1578 struct ti_softc *sc = device_get_softc(dev); 1579 struct ifnet *ifp = &sc->arpcom.ac_if; 1580 1581 if (device_is_attached(dev)) { 1582 lwkt_serialize_enter(ifp->if_serializer); 1583 ti_stop(sc); 1584 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 1585 lwkt_serialize_exit(ifp->if_serializer); 1586 1587 ether_ifdetach(ifp); 1588 } 1589 1590 if (sc->ti_irq != NULL) 1591 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 1592 if (sc->ti_res != NULL) { 1593 bus_release_resource(dev, SYS_RES_MEMORY, 1594 TI_PCI_LOMEM, sc->ti_res); 1595 } 1596 if (sc->ti_cdata.ti_jumbo_buf != NULL) 1597 contigfree(sc->ti_cdata.ti_jumbo_buf, TI_JMEM, M_DEVBUF); 1598 if (sc->ti_rdata != NULL) 1599 contigfree(sc->ti_rdata, sizeof(struct ti_ring_data), M_DEVBUF); 1600 ifmedia_removeall(&sc->ifmedia); 1601 1602 1603 return(0); 1604 } 1605 1606 /* 1607 * Frame reception handling. This is called if there's a frame 1608 * on the receive return list. 1609 * 1610 * Note: we have to be able to handle three possibilities here: 1611 * 1) the frame is from the mini receive ring (can only happen) 1612 * on Tigon 2 boards) 1613 * 2) the frame is from the jumbo recieve ring 1614 * 3) the frame is from the standard receive ring 1615 */ 1616 static void 1617 ti_rxeof(struct ti_softc *sc) 1618 { 1619 struct ifnet *ifp = &sc->arpcom.ac_if; 1620 struct ti_cmd_desc cmd; 1621 1622 while(sc->ti_rx_saved_considx != sc->ti_return_prodidx.ti_idx) { 1623 struct ti_rx_desc *cur_rx; 1624 uint32_t rxidx; 1625 struct mbuf *m; 1626 uint16_t vlan_tag = 0; 1627 int have_tag = 0; 1628 1629 cur_rx = 1630 &sc->ti_rdata->ti_rx_return_ring[sc->ti_rx_saved_considx]; 1631 rxidx = cur_rx->ti_idx; 1632 TI_INC(sc->ti_rx_saved_considx, TI_RETURN_RING_CNT); 1633 1634 if (cur_rx->ti_flags & TI_BDFLAG_VLAN_TAG) { 1635 have_tag = 1; 1636 vlan_tag = cur_rx->ti_vlan_tag & 0xfff; 1637 } 1638 1639 if (cur_rx->ti_flags & TI_BDFLAG_JUMBO_RING) { 1640 TI_INC(sc->ti_jumbo, TI_JUMBO_RX_RING_CNT); 1641 m = sc->ti_cdata.ti_rx_jumbo_chain[rxidx]; 1642 sc->ti_cdata.ti_rx_jumbo_chain[rxidx] = NULL; 1643 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 1644 ifp->if_ierrors++; 1645 ti_newbuf_jumbo(sc, sc->ti_jumbo, m); 1646 continue; 1647 } 1648 if (ti_newbuf_jumbo(sc, sc->ti_jumbo, NULL) == ENOBUFS) { 1649 ifp->if_ierrors++; 1650 ti_newbuf_jumbo(sc, sc->ti_jumbo, m); 1651 continue; 1652 } 1653 } else if (cur_rx->ti_flags & TI_BDFLAG_MINI_RING) { 1654 TI_INC(sc->ti_mini, TI_MINI_RX_RING_CNT); 1655 m = sc->ti_cdata.ti_rx_mini_chain[rxidx]; 1656 sc->ti_cdata.ti_rx_mini_chain[rxidx] = NULL; 1657 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 1658 ifp->if_ierrors++; 1659 ti_newbuf_mini(sc, sc->ti_mini, m); 1660 continue; 1661 } 1662 if (ti_newbuf_mini(sc, sc->ti_mini, NULL) == ENOBUFS) { 1663 ifp->if_ierrors++; 1664 ti_newbuf_mini(sc, sc->ti_mini, m); 1665 continue; 1666 } 1667 } else { 1668 TI_INC(sc->ti_std, TI_STD_RX_RING_CNT); 1669 m = sc->ti_cdata.ti_rx_std_chain[rxidx]; 1670 sc->ti_cdata.ti_rx_std_chain[rxidx] = NULL; 1671 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 1672 ifp->if_ierrors++; 1673 ti_newbuf_std(sc, sc->ti_std, m); 1674 continue; 1675 } 1676 if (ti_newbuf_std(sc, sc->ti_std, NULL) == ENOBUFS) { 1677 ifp->if_ierrors++; 1678 ti_newbuf_std(sc, sc->ti_std, m); 1679 continue; 1680 } 1681 } 1682 1683 m->m_pkthdr.len = m->m_len = cur_rx->ti_len; 1684 ifp->if_ipackets++; 1685 m->m_pkthdr.rcvif = ifp; 1686 1687 if (ifp->if_hwassist) { 1688 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED | 1689 CSUM_DATA_VALID; 1690 if ((cur_rx->ti_ip_cksum ^ 0xffff) == 0) 1691 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1692 m->m_pkthdr.csum_data = cur_rx->ti_tcp_udp_cksum; 1693 } 1694 1695 /* 1696 * If we received a packet with a vlan tag, pass it 1697 * to vlan_input() instead of ether_input(). 1698 */ 1699 lwkt_serialize_enter(ifp->if_serializer); 1700 if (have_tag) 1701 VLAN_INPUT_TAG(m, vlan_tag); 1702 else 1703 ifp->if_input(ifp, m); 1704 lwkt_serialize_exit(ifp->if_serializer); 1705 } 1706 1707 /* Only necessary on the Tigon 1. */ 1708 if (sc->ti_hwrev == TI_HWREV_TIGON) 1709 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 1710 sc->ti_rx_saved_considx); 1711 1712 TI_UPDATE_STDPROD(sc, sc->ti_std); 1713 TI_UPDATE_MINIPROD(sc, sc->ti_mini); 1714 TI_UPDATE_JUMBOPROD(sc, sc->ti_jumbo); 1715 } 1716 1717 static void 1718 ti_txeof(struct ti_softc *sc) 1719 { 1720 struct ifnet *ifp = &sc->arpcom.ac_if; 1721 struct ti_tx_desc *cur_tx = NULL; 1722 1723 /* 1724 * Go through our tx ring and free mbufs for those 1725 * frames that have been sent. 1726 */ 1727 while (sc->ti_tx_saved_considx != sc->ti_tx_considx.ti_idx) { 1728 uint32_t idx = 0; 1729 1730 idx = sc->ti_tx_saved_considx; 1731 if (sc->ti_hwrev != TI_HWREV_TIGON) { 1732 if (idx > 383) 1733 CSR_WRITE_4(sc, TI_WINBASE, 1734 TI_TX_RING_BASE + 6144); 1735 else if (idx > 255) 1736 CSR_WRITE_4(sc, TI_WINBASE, 1737 TI_TX_RING_BASE + 4096); 1738 else if (idx > 127) 1739 CSR_WRITE_4(sc, TI_WINBASE, 1740 TI_TX_RING_BASE + 2048); 1741 else 1742 CSR_WRITE_4(sc, TI_WINBASE, 1743 TI_TX_RING_BASE); 1744 cur_tx = &sc->ti_rdata->ti_tx_ring_nic[idx % 128]; 1745 } else 1746 cur_tx = &sc->ti_rdata->ti_tx_ring[idx]; 1747 if (cur_tx->ti_flags & TI_BDFLAG_END) 1748 ifp->if_opackets++; 1749 if (sc->ti_cdata.ti_tx_chain[idx] != NULL) { 1750 m_freem(sc->ti_cdata.ti_tx_chain[idx]); 1751 sc->ti_cdata.ti_tx_chain[idx] = NULL; 1752 } 1753 sc->ti_txcnt--; 1754 TI_INC(sc->ti_tx_saved_considx, TI_TX_RING_CNT); 1755 ifp->if_timer = 0; 1756 } 1757 1758 if (cur_tx != NULL) 1759 ifp->if_flags &= ~IFF_OACTIVE; 1760 } 1761 1762 static void 1763 ti_intr(void *xsc) 1764 { 1765 struct ti_softc *sc = xsc; 1766 struct ifnet *ifp = &sc->arpcom.ac_if; 1767 1768 #ifdef notdef 1769 /* Avoid this for now -- checking this register is expensive. */ 1770 /* Make sure this is really our interrupt. */ 1771 if ((CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_INTSTATE) == 0) 1772 return; 1773 #endif 1774 1775 /* Ack interrupt and stop others from occuring. */ 1776 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 1777 1778 if (ifp->if_flags & IFF_RUNNING) { 1779 /* Check RX return ring producer/consumer */ 1780 ti_rxeof(sc); 1781 1782 /* Check TX ring producer/consumer */ 1783 ti_txeof(sc); 1784 } 1785 1786 ti_handle_events(sc); 1787 1788 /* Re-enable interrupts. */ 1789 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 1790 1791 if ((ifp->if_flags & IFF_RUNNING) && !ifq_is_empty(&ifp->if_snd)) 1792 ti_start(ifp); 1793 } 1794 1795 static void 1796 ti_stats_update(struct ti_softc *sc) 1797 { 1798 struct ifnet *ifp = &sc->arpcom.ac_if; 1799 1800 ifp->if_collisions += 1801 (sc->ti_rdata->ti_info.ti_stats.dot3StatsSingleCollisionFrames + 1802 sc->ti_rdata->ti_info.ti_stats.dot3StatsMultipleCollisionFrames + 1803 sc->ti_rdata->ti_info.ti_stats.dot3StatsExcessiveCollisions + 1804 sc->ti_rdata->ti_info.ti_stats.dot3StatsLateCollisions) - 1805 ifp->if_collisions; 1806 } 1807 1808 /* 1809 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 1810 * pointers to descriptors. 1811 */ 1812 static int 1813 ti_encap(struct ti_softc *sc, struct mbuf *m_head, uint32_t *txidx) 1814 { 1815 struct ti_tx_desc *f = NULL; 1816 struct mbuf *m; 1817 struct ifvlan *ifv = NULL; 1818 uint32_t cnt = 0, cur, frag; 1819 uint16_t csum_flags = 0; 1820 1821 if ((m_head->m_flags & (M_PROTO1|M_PKTHDR)) == (M_PROTO1|M_PKTHDR) && 1822 m_head->m_pkthdr.rcvif != NULL && 1823 m_head->m_pkthdr.rcvif->if_type == IFT_L2VLAN) 1824 ifv = m_head->m_pkthdr.rcvif->if_softc; 1825 1826 m = m_head; 1827 cur = frag = *txidx; 1828 1829 if (m_head->m_pkthdr.csum_flags) { 1830 if (m_head->m_pkthdr.csum_flags & CSUM_IP) 1831 csum_flags |= TI_BDFLAG_IP_CKSUM; 1832 if (m_head->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) 1833 csum_flags |= TI_BDFLAG_TCP_UDP_CKSUM; 1834 if (m_head->m_flags & M_LASTFRAG) 1835 csum_flags |= TI_BDFLAG_IP_FRAG_END; 1836 else if (m_head->m_flags & M_FRAG) 1837 csum_flags |= TI_BDFLAG_IP_FRAG; 1838 } 1839 /* 1840 * Start packing the mbufs in this chain into 1841 * the fragment pointers. Stop when we run out 1842 * of fragments or hit the end of the mbuf chain. 1843 */ 1844 for (m = m_head; m != NULL; m = m->m_next) { 1845 if (m->m_len != 0) { 1846 if (sc->ti_hwrev == TI_HWREV_TIGON) { 1847 if (frag > 383) 1848 CSR_WRITE_4(sc, TI_WINBASE, 1849 TI_TX_RING_BASE + 6144); 1850 else if (frag > 255) 1851 CSR_WRITE_4(sc, TI_WINBASE, 1852 TI_TX_RING_BASE + 4096); 1853 else if (frag > 127) 1854 CSR_WRITE_4(sc, TI_WINBASE, 1855 TI_TX_RING_BASE + 2048); 1856 else 1857 CSR_WRITE_4(sc, TI_WINBASE, 1858 TI_TX_RING_BASE); 1859 f = &sc->ti_rdata->ti_tx_ring_nic[frag % 128]; 1860 } else 1861 f = &sc->ti_rdata->ti_tx_ring[frag]; 1862 if (sc->ti_cdata.ti_tx_chain[frag] != NULL) 1863 break; 1864 TI_HOSTADDR(f->ti_addr) = vtophys(mtod(m, vm_offset_t)); 1865 f->ti_len = m->m_len; 1866 f->ti_flags = csum_flags; 1867 1868 if (ifv != NULL) { 1869 f->ti_flags |= TI_BDFLAG_VLAN_TAG; 1870 f->ti_vlan_tag = ifv->ifv_tag & 0xfff; 1871 } else { 1872 f->ti_vlan_tag = 0; 1873 } 1874 1875 /* 1876 * Sanity check: avoid coming within 16 descriptors 1877 * of the end of the ring. 1878 */ 1879 if ((TI_TX_RING_CNT - (sc->ti_txcnt + cnt)) < 16) 1880 return(ENOBUFS); 1881 cur = frag; 1882 TI_INC(frag, TI_TX_RING_CNT); 1883 cnt++; 1884 } 1885 } 1886 1887 if (m != NULL) 1888 return(ENOBUFS); 1889 1890 if (frag == sc->ti_tx_saved_considx) 1891 return(ENOBUFS); 1892 1893 if (sc->ti_hwrev == TI_HWREV_TIGON) 1894 sc->ti_rdata->ti_tx_ring_nic[cur % 128].ti_flags |= 1895 TI_BDFLAG_END; 1896 else 1897 sc->ti_rdata->ti_tx_ring[cur].ti_flags |= TI_BDFLAG_END; 1898 sc->ti_cdata.ti_tx_chain[cur] = m_head; 1899 sc->ti_txcnt += cnt; 1900 1901 *txidx = frag; 1902 1903 return(0); 1904 } 1905 1906 /* 1907 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1908 * to the mbuf data regions directly in the transmit descriptors. 1909 */ 1910 static void 1911 ti_start(struct ifnet *ifp) 1912 { 1913 struct ti_softc *sc = ifp->if_softc; 1914 struct mbuf *m_head = NULL; 1915 uint32_t prodidx = 0; 1916 int need_trans; 1917 1918 prodidx = CSR_READ_4(sc, TI_MB_SENDPROD_IDX); 1919 1920 need_trans = 0; 1921 while(sc->ti_cdata.ti_tx_chain[prodidx] == NULL) { 1922 m_head = ifq_poll(&ifp->if_snd); 1923 if (m_head == NULL) 1924 break; 1925 1926 /* 1927 * XXX 1928 * safety overkill. If this is a fragmented packet chain 1929 * with delayed TCP/UDP checksums, then only encapsulate 1930 * it if we have enough descriptors to handle the entire 1931 * chain at once. 1932 * (paranoia -- may not actually be needed) 1933 */ 1934 if (m_head->m_flags & M_FIRSTFRAG && 1935 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) { 1936 if ((TI_TX_RING_CNT - sc->ti_txcnt) < 1937 m_head->m_pkthdr.csum_data + 16) { 1938 ifp->if_flags |= IFF_OACTIVE; 1939 break; 1940 } 1941 } 1942 1943 /* 1944 * Pack the data into the transmit ring. If we 1945 * don't have room, set the OACTIVE flag and wait 1946 * for the NIC to drain the ring. 1947 */ 1948 if (ti_encap(sc, m_head, &prodidx)) { 1949 ifp->if_flags |= IFF_OACTIVE; 1950 break; 1951 } 1952 ifq_dequeue(&ifp->if_snd, m_head); 1953 need_trans = 1; 1954 1955 BPF_MTAP(ifp, m_head); 1956 } 1957 1958 if (!need_trans) 1959 return; 1960 1961 /* Transmit */ 1962 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, prodidx); 1963 1964 /* 1965 * Set a timeout in case the chip goes out to lunch. 1966 */ 1967 ifp->if_timer = 5; 1968 } 1969 1970 static void 1971 ti_init(void *xsc) 1972 { 1973 struct ti_softc *sc = xsc; 1974 1975 /* Cancel pending I/O and flush buffers. */ 1976 ti_stop(sc); 1977 1978 /* Init the gen info block, ring control blocks and firmware. */ 1979 if (ti_gibinit(sc)) { 1980 if_printf(&sc->arpcom.ac_if, "initialization failure\n"); 1981 return; 1982 } 1983 } 1984 1985 static void 1986 ti_init2(struct ti_softc *sc) 1987 { 1988 struct ifnet *ifp = &sc->arpcom.ac_if; 1989 struct ti_cmd_desc cmd; 1990 uint16_t *m; 1991 struct ifmedia *ifm; 1992 int tmp; 1993 1994 /* Specify MTU and interface index. */ 1995 CSR_WRITE_4(sc, TI_GCR_IFINDEX, ifp->if_dunit); 1996 CSR_WRITE_4(sc, TI_GCR_IFMTU, ifp->if_mtu + 1997 ETHER_HDR_LEN + ETHER_CRC_LEN); 1998 TI_DO_CMD(TI_CMD_UPDATE_GENCOM, 0, 0); 1999 2000 /* Load our MAC address. */ 2001 m = (uint16_t *)&sc->arpcom.ac_enaddr[0]; 2002 CSR_WRITE_4(sc, TI_GCR_PAR0, htons(m[0])); 2003 CSR_WRITE_4(sc, TI_GCR_PAR1, (htons(m[1]) << 16) | htons(m[2])); 2004 TI_DO_CMD(TI_CMD_SET_MAC_ADDR, 0, 0); 2005 2006 /* Enable or disable promiscuous mode as needed. */ 2007 if (ifp->if_flags & IFF_PROMISC) 2008 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_ENB, 0); 2009 else 2010 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_DIS, 0); 2011 2012 /* Program multicast filter. */ 2013 ti_setmulti(sc); 2014 2015 /* 2016 * If this is a Tigon 1, we should tell the 2017 * firmware to use software packet filtering. 2018 */ 2019 if (sc->ti_hwrev == TI_HWREV_TIGON) 2020 TI_DO_CMD(TI_CMD_FDR_FILTERING, TI_CMD_CODE_FILT_ENB, 0); 2021 2022 /* Init RX ring. */ 2023 ti_init_rx_ring_std(sc); 2024 2025 /* Init jumbo RX ring. */ 2026 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 2027 ti_init_rx_ring_jumbo(sc); 2028 2029 /* 2030 * If this is a Tigon 2, we can also configure the 2031 * mini ring. 2032 */ 2033 if (sc->ti_hwrev == TI_HWREV_TIGON_II) 2034 ti_init_rx_ring_mini(sc); 2035 2036 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 0); 2037 sc->ti_rx_saved_considx = 0; 2038 2039 /* Init TX ring. */ 2040 ti_init_tx_ring(sc); 2041 2042 /* Tell firmware we're alive. */ 2043 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_UP, 0); 2044 2045 /* Enable host interrupts. */ 2046 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 2047 2048 ifp->if_flags |= IFF_RUNNING; 2049 ifp->if_flags &= ~IFF_OACTIVE; 2050 2051 /* 2052 * Make sure to set media properly. We have to do this 2053 * here since we have to issue commands in order to set 2054 * the link negotiation and we can't issue commands until 2055 * the firmware is running. 2056 */ 2057 ifm = &sc->ifmedia; 2058 tmp = ifm->ifm_media; 2059 ifm->ifm_media = ifm->ifm_cur->ifm_media; 2060 ti_ifmedia_upd(ifp); 2061 ifm->ifm_media = tmp; 2062 } 2063 2064 /* 2065 * Set media options. 2066 */ 2067 static int 2068 ti_ifmedia_upd(struct ifnet *ifp) 2069 { 2070 struct ti_softc *sc = ifp->if_softc; 2071 struct ifmedia *ifm = &sc->ifmedia; 2072 struct ti_cmd_desc cmd; 2073 2074 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 2075 return(EINVAL); 2076 2077 switch(IFM_SUBTYPE(ifm->ifm_media)) { 2078 case IFM_AUTO: 2079 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF | TI_GLNK_1000MB | 2080 TI_GLNK_FULL_DUPLEX | TI_GLNK_RX_FLOWCTL_Y | 2081 TI_GLNK_AUTONEGENB | TI_GLNK_ENB); 2082 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_100MB | TI_LNK_10MB | 2083 TI_LNK_FULL_DUPLEX | TI_LNK_HALF_DUPLEX | 2084 TI_LNK_AUTONEGENB | TI_LNK_ENB); 2085 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 2086 TI_CMD_CODE_NEGOTIATE_BOTH, 0); 2087 break; 2088 case IFM_1000_SX: 2089 case IFM_1000_T: 2090 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB | 2091 TI_GLNK_RX_FLOWCTL_Y | TI_GLNK_ENB); 2092 CSR_WRITE_4(sc, TI_GCR_LINK, 0); 2093 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 2094 TI_SETBIT(sc, TI_GCR_GLINK, TI_GLNK_FULL_DUPLEX); 2095 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 2096 TI_CMD_CODE_NEGOTIATE_GIGABIT, 0); 2097 break; 2098 case IFM_100_FX: 2099 case IFM_10_FL: 2100 case IFM_100_TX: 2101 case IFM_10_T: 2102 CSR_WRITE_4(sc, TI_GCR_GLINK, 0); 2103 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_ENB | TI_LNK_PREF); 2104 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_100_FX || 2105 IFM_SUBTYPE(ifm->ifm_media) == IFM_100_TX) 2106 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_100MB); 2107 else 2108 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_10MB); 2109 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 2110 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_FULL_DUPLEX); 2111 else 2112 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_HALF_DUPLEX); 2113 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 2114 TI_CMD_CODE_NEGOTIATE_10_100, 0); 2115 break; 2116 } 2117 2118 return(0); 2119 } 2120 2121 /* 2122 * Report current media status. 2123 */ 2124 static void 2125 ti_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 2126 { 2127 struct ti_softc *sc = ifp->if_softc; 2128 uint32_t media = 0; 2129 2130 ifmr->ifm_status = IFM_AVALID; 2131 ifmr->ifm_active = IFM_ETHER; 2132 2133 if (sc->ti_linkstat == TI_EV_CODE_LINK_DOWN) 2134 return; 2135 2136 ifmr->ifm_status |= IFM_ACTIVE; 2137 2138 if (sc->ti_linkstat == TI_EV_CODE_GIG_LINK_UP) { 2139 media = CSR_READ_4(sc, TI_GCR_GLINK_STAT); 2140 if (sc->ti_copper) 2141 ifmr->ifm_active |= IFM_1000_T; 2142 else 2143 ifmr->ifm_active |= IFM_1000_SX; 2144 if (media & TI_GLNK_FULL_DUPLEX) 2145 ifmr->ifm_active |= IFM_FDX; 2146 else 2147 ifmr->ifm_active |= IFM_HDX; 2148 } else if (sc->ti_linkstat == TI_EV_CODE_LINK_UP) { 2149 media = CSR_READ_4(sc, TI_GCR_LINK_STAT); 2150 if (sc->ti_copper) { 2151 if (media & TI_LNK_100MB) 2152 ifmr->ifm_active |= IFM_100_TX; 2153 if (media & TI_LNK_10MB) 2154 ifmr->ifm_active |= IFM_10_T; 2155 } else { 2156 if (media & TI_LNK_100MB) 2157 ifmr->ifm_active |= IFM_100_FX; 2158 if (media & TI_LNK_10MB) 2159 ifmr->ifm_active |= IFM_10_FL; 2160 } 2161 if (media & TI_LNK_FULL_DUPLEX) 2162 ifmr->ifm_active |= IFM_FDX; 2163 if (media & TI_LNK_HALF_DUPLEX) 2164 ifmr->ifm_active |= IFM_HDX; 2165 } 2166 } 2167 2168 static int 2169 ti_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr) 2170 { 2171 struct ti_softc *sc = ifp->if_softc; 2172 struct ifreq *ifr = (struct ifreq *) data; 2173 struct ti_cmd_desc cmd; 2174 int error = 0, mask; 2175 2176 switch(command) { 2177 case SIOCSIFMTU: 2178 if (ifr->ifr_mtu > TI_JUMBO_MTU) 2179 error = EINVAL; 2180 else { 2181 ifp->if_mtu = ifr->ifr_mtu; 2182 ti_init(sc); 2183 } 2184 break; 2185 case SIOCSIFFLAGS: 2186 if (ifp->if_flags & IFF_UP) { 2187 /* 2188 * If only the state of the PROMISC flag changed, 2189 * then just use the 'set promisc mode' command 2190 * instead of reinitializing the entire NIC. Doing 2191 * a full re-init means reloading the firmware and 2192 * waiting for it to start up, which may take a 2193 * second or two. 2194 */ 2195 if (ifp->if_flags & IFF_RUNNING && 2196 ifp->if_flags & IFF_PROMISC && 2197 !(sc->ti_if_flags & IFF_PROMISC)) { 2198 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, 2199 TI_CMD_CODE_PROMISC_ENB, 0); 2200 } else if (ifp->if_flags & IFF_RUNNING && 2201 !(ifp->if_flags & IFF_PROMISC) && 2202 sc->ti_if_flags & IFF_PROMISC) { 2203 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, 2204 TI_CMD_CODE_PROMISC_DIS, 0); 2205 } else 2206 ti_init(sc); 2207 } else if (ifp->if_flags & IFF_RUNNING) { 2208 ti_stop(sc); 2209 } 2210 sc->ti_if_flags = ifp->if_flags; 2211 error = 0; 2212 break; 2213 case SIOCADDMULTI: 2214 case SIOCDELMULTI: 2215 if (ifp->if_flags & IFF_RUNNING) { 2216 ti_setmulti(sc); 2217 error = 0; 2218 } 2219 break; 2220 case SIOCSIFMEDIA: 2221 case SIOCGIFMEDIA: 2222 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command); 2223 break; 2224 case SIOCSIFCAP: 2225 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 2226 if (mask & IFCAP_HWCSUM) { 2227 if (IFCAP_HWCSUM & ifp->if_capenable) 2228 ifp->if_capenable &= ~IFCAP_HWCSUM; 2229 else 2230 ifp->if_capenable |= IFCAP_HWCSUM; 2231 if (ifp->if_flags & IFF_RUNNING) 2232 ti_init(sc); 2233 } 2234 error = 0; 2235 break; 2236 default: 2237 error = ether_ioctl(ifp, command, data); 2238 break; 2239 } 2240 return(error); 2241 } 2242 2243 static void 2244 ti_watchdog(struct ifnet *ifp) 2245 { 2246 struct ti_softc *sc = ifp->if_softc; 2247 2248 if_printf(ifp, "watchdog timeout -- resetting\n"); 2249 ti_stop(sc); 2250 ti_init(sc); 2251 2252 ifp->if_oerrors++; 2253 2254 if (!ifq_is_empty(&ifp->if_snd)) 2255 ifp->if_start(ifp); 2256 } 2257 2258 /* 2259 * Stop the adapter and free any mbufs allocated to the 2260 * RX and TX lists. 2261 */ 2262 static void 2263 ti_stop(struct ti_softc *sc) 2264 { 2265 struct ifnet *ifp = &sc->arpcom.ac_if; 2266 struct ti_cmd_desc cmd; 2267 2268 /* Disable host interrupts. */ 2269 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 2270 /* 2271 * Tell firmware we're shutting down. 2272 */ 2273 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_DOWN, 0); 2274 2275 /* Halt and reinitialize. */ 2276 ti_chipinit(sc); 2277 ti_mem(sc, 0x2000, 0x100000 - 0x2000, NULL); 2278 ti_chipinit(sc); 2279 2280 /* Free the RX lists. */ 2281 ti_free_rx_ring_std(sc); 2282 2283 /* Free jumbo RX list. */ 2284 ti_free_rx_ring_jumbo(sc); 2285 2286 /* Free mini RX list. */ 2287 ti_free_rx_ring_mini(sc); 2288 2289 /* Free TX buffers. */ 2290 ti_free_tx_ring(sc); 2291 2292 sc->ti_ev_prodidx.ti_idx = 0; 2293 sc->ti_return_prodidx.ti_idx = 0; 2294 sc->ti_tx_considx.ti_idx = 0; 2295 sc->ti_tx_saved_considx = TI_TXCONS_UNSET; 2296 2297 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2298 } 2299 2300 /* 2301 * Stop all chip I/O so that the kernel's probe routines don't 2302 * get confused by errant DMAs when rebooting. 2303 */ 2304 static void 2305 ti_shutdown(device_t dev) 2306 { 2307 struct ti_softc *sc = device_get_softc(dev); 2308 2309 ti_chipinit(sc); 2310 } 2311