1 /* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: src/sys/pci/if_ti.c,v 1.25.2.14 2002/02/15 04:20:20 silby Exp $ 33 * $DragonFly: src/sys/dev/netif/ti/if_ti.c,v 1.40 2005/12/31 14:08:00 sephe Exp $ 34 */ 35 36 /* 37 * Alteon Networks Tigon PCI gigabit ethernet driver for FreeBSD. 38 * Manuals, sample driver and firmware source kits are available 39 * from http://www.alteon.com/support/openkits. 40 * 41 * Written by Bill Paul <wpaul@ctr.columbia.edu> 42 * Electrical Engineering Department 43 * Columbia University, New York City 44 */ 45 46 /* 47 * The Alteon Networks Tigon chip contains an embedded R4000 CPU, 48 * gigabit MAC, dual DMA channels and a PCI interface unit. NICs 49 * using the Tigon may have anywhere from 512K to 2MB of SRAM. The 50 * Tigon supports hardware IP, TCP and UCP checksumming, multicast 51 * filtering and jumbo (9014 byte) frames. The hardware is largely 52 * controlled by firmware, which must be loaded into the NIC during 53 * initialization. 54 * 55 * The Tigon 2 contains 2 R4000 CPUs and requires a newer firmware 56 * revision, which supports new features such as extended commands, 57 * extended jumbo receive ring desciptors and a mini receive ring. 58 * 59 * Alteon Networks is to be commended for releasing such a vast amount 60 * of development material for the Tigon NIC without requiring an NDA 61 * (although they really should have done it a long time ago). With 62 * any luck, the other vendors will finally wise up and follow Alteon's 63 * stellar example. 64 * 65 * The firmware for the Tigon 1 and 2 NICs is compiled directly into 66 * this driver by #including it as a C header file. This bloats the 67 * driver somewhat, but it's the easiest method considering that the 68 * driver code and firmware code need to be kept in sync. The source 69 * for the firmware is not provided with the FreeBSD distribution since 70 * compiling it requires a GNU toolchain targeted for mips-sgi-irix5.3. 71 * 72 * The following people deserve special thanks: 73 * - Terry Murphy of 3Com, for providing a 3c985 Tigon 1 board 74 * for testing 75 * - Raymond Lee of Netgear, for providing a pair of Netgear 76 * GA620 Tigon 2 boards for testing 77 * - Ulf Zimmermann, for bringing the GA260 to my attention and 78 * convincing me to write this driver. 79 * - Andrew Gallatin for providing FreeBSD/Alpha support. 80 */ 81 82 #include <sys/param.h> 83 #include <sys/systm.h> 84 #include <sys/sockio.h> 85 #include <sys/mbuf.h> 86 #include <sys/malloc.h> 87 #include <sys/kernel.h> 88 #include <sys/socket.h> 89 #include <sys/queue.h> 90 #include <sys/serialize.h> 91 #include <sys/thread2.h> 92 93 #include <net/if.h> 94 #include <net/ifq_var.h> 95 #include <net/if_arp.h> 96 #include <net/ethernet.h> 97 #include <net/if_dl.h> 98 #include <net/if_media.h> 99 #include <net/if_types.h> 100 #include <net/vlan/if_vlan_var.h> 101 102 #include <net/bpf.h> 103 104 #include <netinet/in_systm.h> 105 #include <netinet/in.h> 106 #include <netinet/ip.h> 107 108 #include <vm/vm.h> /* for vtophys */ 109 #include <vm/pmap.h> /* for vtophys */ 110 #include <machine/bus.h> 111 #include <machine/resource.h> 112 #include <sys/bus.h> 113 #include <sys/rman.h> 114 115 #include <bus/pci/pcireg.h> 116 #include <bus/pci/pcivar.h> 117 118 #include "if_tireg.h" 119 #include "ti_fw.h" 120 #include "ti_fw2.h" 121 122 /* 123 * Temporarily disable the checksum offload support for now. 124 * Tests with ftp.freesoftware.com show that after about 12 hours, 125 * the firmware will begin calculating completely bogus TX checksums 126 * and refuse to stop until the interface is reset. Unfortunately, 127 * there isn't enough time to fully debug this before the 4.1 128 * release, so this will need to stay off for now. 129 */ 130 #ifdef notdef 131 #define TI_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_IP_FRAGS) 132 #else 133 #define TI_CSUM_FEATURES 0 134 #endif 135 136 /* 137 * Various supported device vendors/types and their names. 138 */ 139 140 static struct ti_type ti_devs[] = { 141 { ALT_VENDORID, ALT_DEVICEID_ACENIC, 142 "Alteon AceNIC 1000baseSX Gigabit Ethernet" }, 143 { ALT_VENDORID, ALT_DEVICEID_ACENIC_COPPER, 144 "Alteon AceNIC 1000baseT Gigabit Ethernet" }, 145 { TC_VENDORID, TC_DEVICEID_3C985, 146 "3Com 3c985-SX Gigabit Ethernet" }, 147 { NG_VENDORID, NG_DEVICEID_GA620, 148 "Netgear GA620 1000baseSX Gigabit Ethernet" }, 149 { NG_VENDORID, NG_DEVICEID_GA620T, 150 "Netgear GA620 1000baseT Gigabit Ethernet" }, 151 { SGI_VENDORID, SGI_DEVICEID_TIGON, 152 "Silicon Graphics Gigabit Ethernet" }, 153 { DEC_VENDORID, DEC_DEVICEID_FARALLON_PN9000SX, 154 "Farallon PN9000SX Gigabit Ethernet" }, 155 { 0, 0, NULL } 156 }; 157 158 static int ti_probe(device_t); 159 static int ti_attach(device_t); 160 static int ti_detach(device_t); 161 static void ti_txeof(struct ti_softc *); 162 static void ti_rxeof(struct ti_softc *); 163 164 static void ti_stats_update(struct ti_softc *); 165 static int ti_encap(struct ti_softc *, struct mbuf *, uint32_t *); 166 167 static void ti_intr(void *); 168 static void ti_start(struct ifnet *); 169 static int ti_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *); 170 static void ti_init(void *); 171 static void ti_init2(struct ti_softc *); 172 static void ti_stop(struct ti_softc *); 173 static void ti_watchdog(struct ifnet *); 174 static void ti_shutdown(device_t); 175 static int ti_ifmedia_upd(struct ifnet *); 176 static void ti_ifmedia_sts(struct ifnet *, struct ifmediareq *); 177 178 static uint32_t ti_eeprom_putbyte(struct ti_softc *, int); 179 static uint8_t ti_eeprom_getbyte(struct ti_softc *, int, uint8_t *); 180 static int ti_read_eeprom(struct ti_softc *, caddr_t, int, int); 181 182 static void ti_add_mcast(struct ti_softc *, struct ether_addr *); 183 static void ti_del_mcast(struct ti_softc *, struct ether_addr *); 184 static void ti_setmulti(struct ti_softc *); 185 186 static void ti_mem(struct ti_softc *, uint32_t, uint32_t, caddr_t); 187 static void ti_loadfw(struct ti_softc *); 188 static void ti_cmd(struct ti_softc *, struct ti_cmd_desc *); 189 static void ti_cmd_ext(struct ti_softc *, struct ti_cmd_desc *, 190 caddr_t, int); 191 static void ti_handle_events(struct ti_softc *); 192 static int ti_alloc_jumbo_mem(struct ti_softc *); 193 static struct ti_jslot * 194 ti_jalloc(struct ti_softc *); 195 static void ti_jfree(void *); 196 static void ti_jref(void *); 197 static int ti_newbuf_std(struct ti_softc *, int, struct mbuf *); 198 static int ti_newbuf_mini(struct ti_softc *, int, struct mbuf *); 199 static int ti_newbuf_jumbo(struct ti_softc *, int, struct mbuf *); 200 static int ti_init_rx_ring_std(struct ti_softc *); 201 static void ti_free_rx_ring_std(struct ti_softc *); 202 static int ti_init_rx_ring_jumbo(struct ti_softc *); 203 static void ti_free_rx_ring_jumbo(struct ti_softc *); 204 static int ti_init_rx_ring_mini(struct ti_softc *); 205 static void ti_free_rx_ring_mini(struct ti_softc *); 206 static void ti_free_tx_ring(struct ti_softc *); 207 static int ti_init_tx_ring(struct ti_softc *); 208 209 static int ti_64bitslot_war(struct ti_softc *); 210 static int ti_chipinit(struct ti_softc *); 211 static int ti_gibinit(struct ti_softc *); 212 213 static device_method_t ti_methods[] = { 214 /* Device interface */ 215 DEVMETHOD(device_probe, ti_probe), 216 DEVMETHOD(device_attach, ti_attach), 217 DEVMETHOD(device_detach, ti_detach), 218 DEVMETHOD(device_shutdown, ti_shutdown), 219 { 0, 0 } 220 }; 221 222 223 static DEFINE_CLASS_0(ti, ti_driver, ti_methods, sizeof(struct ti_softc)); 224 static devclass_t ti_devclass; 225 226 DECLARE_DUMMY_MODULE(if_ti); 227 DRIVER_MODULE(if_ti, pci, ti_driver, ti_devclass, 0, 0); 228 229 /* 230 * Send an instruction or address to the EEPROM, check for ACK. 231 */ 232 static uint32_t 233 ti_eeprom_putbyte(struct ti_softc *sc, int byte) 234 { 235 int ack = 0, i; 236 237 /* 238 * Make sure we're in TX mode. 239 */ 240 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 241 242 /* 243 * Feed in each bit and stobe the clock. 244 */ 245 for (i = 0x80; i; i >>= 1) { 246 if (byte & i) 247 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); 248 else 249 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); 250 DELAY(1); 251 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 252 DELAY(1); 253 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 254 } 255 256 /* 257 * Turn off TX mode. 258 */ 259 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 260 261 /* 262 * Check for ack. 263 */ 264 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 265 ack = CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN; 266 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 267 268 return(ack); 269 } 270 271 /* 272 * Read a byte of data stored in the EEPROM at address 'addr.' 273 * We have to send two address bytes since the EEPROM can hold 274 * more than 256 bytes of data. 275 */ 276 static uint8_t 277 ti_eeprom_getbyte(struct ti_softc *sc, int addr, uint8_t *dest) 278 { 279 struct ifnet *ifp = &sc->arpcom.ac_if; 280 int i; 281 uint8_t byte = 0; 282 283 EEPROM_START; 284 285 /* 286 * Send write control code to EEPROM. 287 */ 288 if (ti_eeprom_putbyte(sc, EEPROM_CTL_WRITE)) { 289 if_printf(ifp, "failed to send write command, status: %x\n", 290 CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 291 return(1); 292 } 293 294 /* 295 * Send first byte of address of byte we want to read. 296 */ 297 if (ti_eeprom_putbyte(sc, (addr >> 8) & 0xFF)) { 298 if_printf(ifp, "failed to send address, status: %x\n", 299 CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 300 return(1); 301 } 302 /* 303 * Send second byte address of byte we want to read. 304 */ 305 if (ti_eeprom_putbyte(sc, addr & 0xFF)) { 306 if_printf(ifp, "failed to send address, status: %x\n", 307 CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 308 return(1); 309 } 310 311 EEPROM_STOP; 312 EEPROM_START; 313 /* 314 * Send read control code to EEPROM. 315 */ 316 if (ti_eeprom_putbyte(sc, EEPROM_CTL_READ)) { 317 if_printf(ifp, "failed to send read command, status: %x\n", 318 CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 319 return(1); 320 } 321 322 /* 323 * Start reading bits from EEPROM. 324 */ 325 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 326 for (i = 0x80; i; i >>= 1) { 327 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 328 DELAY(1); 329 if (CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN) 330 byte |= i; 331 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 332 DELAY(1); 333 } 334 335 EEPROM_STOP; 336 337 /* 338 * No ACK generated for read, so just return byte. 339 */ 340 341 *dest = byte; 342 343 return(0); 344 } 345 346 /* 347 * Read a sequence of bytes from the EEPROM. 348 */ 349 static int 350 ti_read_eeprom(struct ti_softc *sc, caddr_t dest, int off, int cnt) 351 { 352 int err = 0, i; 353 uint8_t byte = 0; 354 355 for (i = 0; i < cnt; i++) { 356 err = ti_eeprom_getbyte(sc, off + i, &byte); 357 if (err) 358 break; 359 *(dest + i) = byte; 360 } 361 362 return(err ? 1 : 0); 363 } 364 365 /* 366 * NIC memory access function. Can be used to either clear a section 367 * of NIC local memory or (if buf is non-NULL) copy data into it. 368 */ 369 static void 370 ti_mem(struct ti_softc *sc, uint32_t addr, uint32_t len, caddr_t buf) 371 { 372 int cnt, segptr, segsize; 373 caddr_t ti_winbase, ptr; 374 375 segptr = addr; 376 cnt = len; 377 ti_winbase = (caddr_t)(sc->ti_vhandle + TI_WINDOW); 378 ptr = buf; 379 380 while(cnt) { 381 if (cnt < TI_WINLEN) 382 segsize = cnt; 383 else 384 segsize = TI_WINLEN - (segptr % TI_WINLEN); 385 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1))); 386 if (buf == NULL) 387 bzero((char *)ti_winbase + (segptr & 388 (TI_WINLEN - 1)), segsize); 389 else { 390 bcopy((char *)ptr, (char *)ti_winbase + 391 (segptr & (TI_WINLEN - 1)), segsize); 392 ptr += segsize; 393 } 394 segptr += segsize; 395 cnt -= segsize; 396 } 397 } 398 399 /* 400 * Load firmware image into the NIC. Check that the firmware revision 401 * is acceptable and see if we want the firmware for the Tigon 1 or 402 * Tigon 2. 403 */ 404 static void 405 ti_loadfw(struct ti_softc *sc) 406 { 407 struct ifnet *ifp = &sc->arpcom.ac_if; 408 409 switch(sc->ti_hwrev) { 410 case TI_HWREV_TIGON: 411 if (tigonFwReleaseMajor != TI_FIRMWARE_MAJOR || 412 tigonFwReleaseMinor != TI_FIRMWARE_MINOR || 413 tigonFwReleaseFix != TI_FIRMWARE_FIX) { 414 if_printf(ifp, "firmware revision mismatch; want " 415 "%d.%d.%d, got %d.%d.%d\n", 416 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR, 417 TI_FIRMWARE_FIX, tigonFwReleaseMajor, 418 tigonFwReleaseMinor, tigonFwReleaseFix); 419 return; 420 } 421 ti_mem(sc, tigonFwTextAddr, tigonFwTextLen, 422 (caddr_t)tigonFwText); 423 ti_mem(sc, tigonFwDataAddr, tigonFwDataLen, 424 (caddr_t)tigonFwData); 425 ti_mem(sc, tigonFwRodataAddr, tigonFwRodataLen, 426 (caddr_t)tigonFwRodata); 427 ti_mem(sc, tigonFwBssAddr, tigonFwBssLen, NULL); 428 ti_mem(sc, tigonFwSbssAddr, tigonFwSbssLen, NULL); 429 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigonFwStartAddr); 430 break; 431 case TI_HWREV_TIGON_II: 432 if (tigon2FwReleaseMajor != TI_FIRMWARE_MAJOR || 433 tigon2FwReleaseMinor != TI_FIRMWARE_MINOR || 434 tigon2FwReleaseFix != TI_FIRMWARE_FIX) { 435 if_printf(ifp, "firmware revision mismatch; want " 436 "%d.%d.%d, got %d.%d.%d\n", 437 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR, 438 TI_FIRMWARE_FIX, tigon2FwReleaseMajor, 439 tigon2FwReleaseMinor, tigon2FwReleaseFix); 440 return; 441 } 442 ti_mem(sc, tigon2FwTextAddr, tigon2FwTextLen, 443 (caddr_t)tigon2FwText); 444 ti_mem(sc, tigon2FwDataAddr, tigon2FwDataLen, 445 (caddr_t)tigon2FwData); 446 ti_mem(sc, tigon2FwRodataAddr, tigon2FwRodataLen, 447 (caddr_t)tigon2FwRodata); 448 ti_mem(sc, tigon2FwBssAddr, tigon2FwBssLen, NULL); 449 ti_mem(sc, tigon2FwSbssAddr, tigon2FwSbssLen, NULL); 450 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigon2FwStartAddr); 451 break; 452 default: 453 if_printf(ifp, "can't load firmware: unknown hardware rev\n"); 454 break; 455 } 456 } 457 458 /* 459 * Send the NIC a command via the command ring. 460 */ 461 static void 462 ti_cmd(struct ti_softc *sc, struct ti_cmd_desc *cmd) 463 { 464 uint32_t index; 465 466 if (sc->ti_rdata->ti_cmd_ring == NULL) 467 return; 468 469 index = sc->ti_cmd_saved_prodidx; 470 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(uint32_t *)(cmd)); 471 TI_INC(index, TI_CMD_RING_CNT); 472 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index); 473 sc->ti_cmd_saved_prodidx = index; 474 } 475 476 /* 477 * Send the NIC an extended command. The 'len' parameter specifies the 478 * number of command slots to include after the initial command. 479 */ 480 static void 481 ti_cmd_ext(struct ti_softc *sc, struct ti_cmd_desc *cmd, caddr_t arg, int len) 482 { 483 uint32_t index; 484 int i; 485 486 if (sc->ti_rdata->ti_cmd_ring == NULL) 487 return; 488 489 index = sc->ti_cmd_saved_prodidx; 490 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(uint32_t *)(cmd)); 491 TI_INC(index, TI_CMD_RING_CNT); 492 for (i = 0; i < len; i++) { 493 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), 494 *(uint32_t *)(&arg[i * 4])); 495 TI_INC(index, TI_CMD_RING_CNT); 496 } 497 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index); 498 sc->ti_cmd_saved_prodidx = index; 499 } 500 501 /* 502 * Handle events that have triggered interrupts. 503 */ 504 static void 505 ti_handle_events(struct ti_softc *sc) 506 { 507 struct ifnet *ifp = &sc->arpcom.ac_if; 508 struct ti_event_desc *e; 509 510 if (sc->ti_rdata->ti_event_ring == NULL) 511 return; 512 513 while (sc->ti_ev_saved_considx != sc->ti_ev_prodidx.ti_idx) { 514 e = &sc->ti_rdata->ti_event_ring[sc->ti_ev_saved_considx]; 515 switch(e->ti_event) { 516 case TI_EV_LINKSTAT_CHANGED: 517 sc->ti_linkstat = e->ti_code; 518 if (e->ti_code == TI_EV_CODE_LINK_UP) { 519 if_printf(ifp, "10/100 link up\n"); 520 } else if (e->ti_code == TI_EV_CODE_GIG_LINK_UP) { 521 if_printf(ifp, "gigabit link up\n"); 522 } else if (e->ti_code == TI_EV_CODE_LINK_DOWN) { 523 if_printf(ifp, "link down\n"); 524 } 525 break; 526 case TI_EV_ERROR: 527 if (e->ti_code == TI_EV_CODE_ERR_INVAL_CMD) { 528 if_printf(ifp, "invalid command\n"); 529 } else if (e->ti_code == TI_EV_CODE_ERR_UNIMP_CMD) { 530 if_printf(ifp, "unknown command\n"); 531 } else if (e->ti_code == TI_EV_CODE_ERR_BADCFG) { 532 if_printf(ifp, "bad config data\n"); 533 } 534 break; 535 case TI_EV_FIRMWARE_UP: 536 ti_init2(sc); 537 break; 538 case TI_EV_STATS_UPDATED: 539 ti_stats_update(sc); 540 break; 541 case TI_EV_RESET_JUMBO_RING: 542 case TI_EV_MCAST_UPDATED: 543 /* Who cares. */ 544 break; 545 default: 546 if_printf(ifp, "unknown event: %d\n", e->ti_event); 547 break; 548 } 549 /* Advance the consumer index. */ 550 TI_INC(sc->ti_ev_saved_considx, TI_EVENT_RING_CNT); 551 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, sc->ti_ev_saved_considx); 552 } 553 } 554 555 /* 556 * Memory management for the jumbo receive ring is a pain in the 557 * butt. We need to allocate at least 9018 bytes of space per frame, 558 * _and_ it has to be contiguous (unless you use the extended 559 * jumbo descriptor format). Using malloc() all the time won't 560 * work: malloc() allocates memory in powers of two, which means we 561 * would end up wasting a considerable amount of space by allocating 562 * 9K chunks. We don't have a jumbo mbuf cluster pool. Thus, we have 563 * to do our own memory management. 564 * 565 * The driver needs to allocate a contiguous chunk of memory at boot 566 * time. We then chop this up ourselves into 9K pieces and use them 567 * as external mbuf storage. 568 * 569 * One issue here is how much memory to allocate. The jumbo ring has 570 * 256 slots in it, but at 9K per slot than can consume over 2MB of 571 * RAM. This is a bit much, especially considering we also need 572 * RAM for the standard ring and mini ring (on the Tigon 2). To 573 * save space, we only actually allocate enough memory for 64 slots 574 * by default, which works out to between 500 and 600K. This can 575 * be tuned by changing a #define in if_tireg.h. 576 */ 577 578 static int 579 ti_alloc_jumbo_mem(struct ti_softc *sc) 580 { 581 struct ti_jslot *entry; 582 caddr_t ptr; 583 int i; 584 585 /* Grab a big chunk o' storage. */ 586 sc->ti_cdata.ti_jumbo_buf = contigmalloc(TI_JMEM, M_DEVBUF, 587 M_WAITOK, 0, 0xffffffff, PAGE_SIZE, 0); 588 589 if (sc->ti_cdata.ti_jumbo_buf == NULL) { 590 if_printf(&sc->arpcom.ac_if, "no memory for jumbo buffers!\n"); 591 return(ENOBUFS); 592 } 593 594 SLIST_INIT(&sc->ti_jfree_listhead); 595 596 /* 597 * Now divide it up into 9K pieces and save the addresses 598 * in an array. Note that we play an evil trick here by using 599 * the first few bytes in the buffer to hold the the address 600 * of the softc structure for this interface. This is because 601 * ti_jfree() needs it, but it is called by the mbuf management 602 * code which will not pass it to us explicitly. 603 */ 604 ptr = sc->ti_cdata.ti_jumbo_buf; 605 for (i = 0; i < TI_JSLOTS; i++) { 606 entry = &sc->ti_cdata.ti_jslots[i]; 607 entry->ti_sc = sc; 608 entry->ti_buf = ptr; 609 entry->ti_inuse = 0; 610 entry->ti_slot = i; 611 SLIST_INSERT_HEAD(&sc->ti_jfree_listhead, entry, jslot_link); 612 ptr += TI_JLEN; 613 } 614 615 return(0); 616 } 617 618 /* 619 * Allocate a jumbo buffer. 620 */ 621 static struct ti_jslot * 622 ti_jalloc(struct ti_softc *sc) 623 { 624 struct ti_jslot *entry; 625 626 lwkt_serialize_enter(&sc->ti_jslot_serializer); 627 entry = SLIST_FIRST(&sc->ti_jfree_listhead); 628 if (entry) { 629 SLIST_REMOVE_HEAD(&sc->ti_jfree_listhead, jslot_link); 630 entry->ti_inuse = 1; 631 } else { 632 if_printf(&sc->arpcom.ac_if, "no free jumbo buffers\n"); 633 } 634 lwkt_serialize_exit(&sc->ti_jslot_serializer); 635 return(entry); 636 } 637 638 /* 639 * Adjust usage count on a jumbo buffer. In general this doesn't 640 * get used much because our jumbo buffers don't get passed around 641 * too much, but it's implemented for correctness. 642 */ 643 static void 644 ti_jref(void *arg) 645 { 646 struct ti_jslot *entry = (struct ti_jslot *)arg; 647 struct ti_softc *sc = entry->ti_sc; 648 649 if (sc == NULL) 650 panic("ti_jref: can't find softc pointer!"); 651 652 if (&sc->ti_cdata.ti_jslots[entry->ti_slot] != entry) 653 panic("ti_jref: asked to reference buffer " 654 "that we don't manage!"); 655 if (entry->ti_inuse == 0) 656 panic("ti_jref: buffer already free!"); 657 atomic_add_int(&entry->ti_inuse, 1); 658 } 659 660 /* 661 * Release a jumbo buffer. 662 */ 663 static void 664 ti_jfree(void *arg) 665 { 666 struct ti_jslot *entry = (struct ti_jslot *)arg; 667 struct ti_softc *sc = entry->ti_sc; 668 669 if (sc == NULL) 670 panic("ti_jref: can't find softc pointer!"); 671 672 if (&sc->ti_cdata.ti_jslots[entry->ti_slot] != entry) 673 panic("ti_jref: asked to reference buffer " 674 "that we don't manage!"); 675 if (entry->ti_inuse == 0) 676 panic("ti_jref: buffer already free!"); 677 lwkt_serialize_enter(&sc->ti_jslot_serializer); 678 atomic_subtract_int(&entry->ti_inuse, 1); 679 if (entry->ti_inuse == 0) 680 SLIST_INSERT_HEAD(&sc->ti_jfree_listhead, entry, jslot_link); 681 lwkt_serialize_exit(&sc->ti_jslot_serializer); 682 } 683 684 685 /* 686 * Intialize a standard receive ring descriptor. 687 */ 688 static int 689 ti_newbuf_std(struct ti_softc *sc, int i, struct mbuf *m) 690 { 691 struct mbuf *m_new; 692 struct ti_rx_desc *r; 693 694 if (m == NULL) { 695 m_new = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR); 696 if (m_new == NULL) 697 return (ENOBUFS); 698 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 699 } else { 700 m_new = m; 701 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 702 m_new->m_data = m_new->m_ext.ext_buf; 703 } 704 705 706 m_adj(m_new, ETHER_ALIGN); 707 sc->ti_cdata.ti_rx_std_chain[i] = m_new; 708 r = &sc->ti_rdata->ti_rx_std_ring[i]; 709 TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t)); 710 r->ti_type = TI_BDTYPE_RECV_BD; 711 r->ti_flags = 0; 712 if (sc->arpcom.ac_if.if_hwassist) 713 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM; 714 r->ti_len = m_new->m_len; 715 r->ti_idx = i; 716 717 return(0); 718 } 719 720 /* 721 * Intialize a mini receive ring descriptor. This only applies to 722 * the Tigon 2. 723 */ 724 static int 725 ti_newbuf_mini(struct ti_softc *sc, int i, struct mbuf *m) 726 { 727 struct mbuf *m_new; 728 struct ti_rx_desc *r; 729 730 if (m == NULL) { 731 MGETHDR(m_new, MB_DONTWAIT, MT_DATA); 732 if (m_new == NULL) { 733 return(ENOBUFS); 734 } 735 m_new->m_len = m_new->m_pkthdr.len = MHLEN; 736 } else { 737 m_new = m; 738 m_new->m_data = m_new->m_pktdat; 739 m_new->m_len = m_new->m_pkthdr.len = MHLEN; 740 } 741 742 m_adj(m_new, ETHER_ALIGN); 743 r = &sc->ti_rdata->ti_rx_mini_ring[i]; 744 sc->ti_cdata.ti_rx_mini_chain[i] = m_new; 745 TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t)); 746 r->ti_type = TI_BDTYPE_RECV_BD; 747 r->ti_flags = TI_BDFLAG_MINI_RING; 748 if (sc->arpcom.ac_if.if_hwassist) 749 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM; 750 r->ti_len = m_new->m_len; 751 r->ti_idx = i; 752 753 return(0); 754 } 755 756 /* 757 * Initialize a jumbo receive ring descriptor. This allocates 758 * a jumbo buffer from the pool managed internally by the driver. 759 */ 760 static int 761 ti_newbuf_jumbo(struct ti_softc *sc, int i, struct mbuf *m) 762 { 763 struct mbuf *m_new; 764 struct ti_rx_desc *r; 765 struct ti_jslot *buf; 766 767 if (m == NULL) { 768 /* Allocate the mbuf. */ 769 MGETHDR(m_new, MB_DONTWAIT, MT_DATA); 770 if (m_new == NULL) { 771 return(ENOBUFS); 772 } 773 774 /* Allocate the jumbo buffer */ 775 buf = ti_jalloc(sc); 776 if (buf == NULL) { 777 m_freem(m_new); 778 if_printf(&sc->arpcom.ac_if, "jumbo allocation failed " 779 "-- packet dropped!\n"); 780 return(ENOBUFS); 781 } 782 783 /* Attach the buffer to the mbuf. */ 784 m_new->m_ext.ext_arg = buf; 785 m_new->m_ext.ext_free = ti_jfree; 786 m_new->m_ext.ext_ref = ti_jref; 787 m_new->m_ext.ext_size = TI_JUMBO_FRAMELEN; 788 789 m_new->m_data = m_new->m_ext.ext_buf; 790 m_new->m_flags |= M_EXT; 791 m_new->m_len = m_new->m_pkthdr.len = m_new->m_ext.ext_size; 792 } else { 793 m_new = m; 794 m_new->m_data = m_new->m_ext.ext_buf; 795 m_new->m_ext.ext_size = TI_JUMBO_FRAMELEN; 796 } 797 798 m_adj(m_new, ETHER_ALIGN); 799 /* Set up the descriptor. */ 800 r = &sc->ti_rdata->ti_rx_jumbo_ring[i]; 801 sc->ti_cdata.ti_rx_jumbo_chain[i] = m_new; 802 TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t)); 803 r->ti_type = TI_BDTYPE_RECV_JUMBO_BD; 804 r->ti_flags = TI_BDFLAG_JUMBO_RING; 805 if (sc->arpcom.ac_if.if_hwassist) 806 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM; 807 r->ti_len = m_new->m_len; 808 r->ti_idx = i; 809 810 return(0); 811 } 812 813 /* 814 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 815 * that's 1MB or memory, which is a lot. For now, we fill only the first 816 * 256 ring entries and hope that our CPU is fast enough to keep up with 817 * the NIC. 818 */ 819 static int 820 ti_init_rx_ring_std(struct ti_softc *sc) 821 { 822 int i; 823 struct ti_cmd_desc cmd; 824 825 for (i = 0; i < TI_SSLOTS; i++) { 826 if (ti_newbuf_std(sc, i, NULL) == ENOBUFS) 827 return(ENOBUFS); 828 }; 829 830 TI_UPDATE_STDPROD(sc, i - 1); 831 sc->ti_std = i - 1; 832 833 return(0); 834 } 835 836 static void 837 ti_free_rx_ring_std(struct ti_softc *sc) 838 { 839 int i; 840 841 for (i = 0; i < TI_STD_RX_RING_CNT; i++) { 842 if (sc->ti_cdata.ti_rx_std_chain[i] != NULL) { 843 m_freem(sc->ti_cdata.ti_rx_std_chain[i]); 844 sc->ti_cdata.ti_rx_std_chain[i] = NULL; 845 } 846 bzero(&sc->ti_rdata->ti_rx_std_ring[i], 847 sizeof(struct ti_rx_desc)); 848 } 849 } 850 851 static int 852 ti_init_rx_ring_jumbo(struct ti_softc *sc) 853 { 854 int i; 855 struct ti_cmd_desc cmd; 856 857 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) { 858 if (ti_newbuf_jumbo(sc, i, NULL) == ENOBUFS) 859 return(ENOBUFS); 860 } 861 862 TI_UPDATE_JUMBOPROD(sc, i - 1); 863 sc->ti_jumbo = i - 1; 864 865 return(0); 866 } 867 868 static void 869 ti_free_rx_ring_jumbo(struct ti_softc *sc) 870 { 871 int i; 872 873 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) { 874 if (sc->ti_cdata.ti_rx_jumbo_chain[i] != NULL) { 875 m_freem(sc->ti_cdata.ti_rx_jumbo_chain[i]); 876 sc->ti_cdata.ti_rx_jumbo_chain[i] = NULL; 877 } 878 bzero(&sc->ti_rdata->ti_rx_jumbo_ring[i], 879 sizeof(struct ti_rx_desc)); 880 } 881 } 882 883 static int 884 ti_init_rx_ring_mini(struct ti_softc *sc) 885 { 886 int i; 887 888 for (i = 0; i < TI_MSLOTS; i++) { 889 if (ti_newbuf_mini(sc, i, NULL) == ENOBUFS) 890 return(ENOBUFS); 891 } 892 893 TI_UPDATE_MINIPROD(sc, i - 1); 894 sc->ti_mini = i - 1; 895 896 return(0); 897 } 898 899 static void 900 ti_free_rx_ring_mini(struct ti_softc *sc) 901 { 902 int i; 903 904 for (i = 0; i < TI_MINI_RX_RING_CNT; i++) { 905 if (sc->ti_cdata.ti_rx_mini_chain[i] != NULL) { 906 m_freem(sc->ti_cdata.ti_rx_mini_chain[i]); 907 sc->ti_cdata.ti_rx_mini_chain[i] = NULL; 908 } 909 bzero(&sc->ti_rdata->ti_rx_mini_ring[i], 910 sizeof(struct ti_rx_desc)); 911 } 912 } 913 914 static void 915 ti_free_tx_ring(struct ti_softc *sc) 916 { 917 int i; 918 919 if (sc->ti_rdata->ti_tx_ring == NULL) 920 return; 921 922 for (i = 0; i < TI_TX_RING_CNT; i++) { 923 if (sc->ti_cdata.ti_tx_chain[i] != NULL) { 924 m_freem(sc->ti_cdata.ti_tx_chain[i]); 925 sc->ti_cdata.ti_tx_chain[i] = NULL; 926 } 927 bzero(&sc->ti_rdata->ti_tx_ring[i], 928 sizeof(struct ti_tx_desc)); 929 } 930 } 931 932 static int 933 ti_init_tx_ring(struct ti_softc *sc) 934 { 935 sc->ti_txcnt = 0; 936 sc->ti_tx_saved_considx = 0; 937 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, 0); 938 return(0); 939 } 940 941 /* 942 * The Tigon 2 firmware has a new way to add/delete multicast addresses, 943 * but we have to support the old way too so that Tigon 1 cards will 944 * work. 945 */ 946 static void 947 ti_add_mcast(struct ti_softc *sc, struct ether_addr *addr) 948 { 949 struct ti_cmd_desc cmd; 950 uint16_t *m; 951 uint32_t ext[2] = {0, 0}; 952 953 m = (uint16_t *)&addr->octet[0]; 954 955 switch(sc->ti_hwrev) { 956 case TI_HWREV_TIGON: 957 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0])); 958 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2])); 959 TI_DO_CMD(TI_CMD_ADD_MCAST_ADDR, 0, 0); 960 break; 961 case TI_HWREV_TIGON_II: 962 ext[0] = htons(m[0]); 963 ext[1] = (htons(m[1]) << 16) | htons(m[2]); 964 TI_DO_CMD_EXT(TI_CMD_EXT_ADD_MCAST, 0, 0, (caddr_t)&ext, 2); 965 break; 966 default: 967 if_printf(&sc->arpcom.ac_if, "unknown hwrev\n"); 968 break; 969 } 970 } 971 972 static void 973 ti_del_mcast(struct ti_softc *sc, struct ether_addr *addr) 974 { 975 struct ti_cmd_desc cmd; 976 uint16_t *m; 977 uint32_t ext[2] = {0, 0}; 978 979 m = (uint16_t *)&addr->octet[0]; 980 981 switch(sc->ti_hwrev) { 982 case TI_HWREV_TIGON: 983 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0])); 984 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2])); 985 TI_DO_CMD(TI_CMD_DEL_MCAST_ADDR, 0, 0); 986 break; 987 case TI_HWREV_TIGON_II: 988 ext[0] = htons(m[0]); 989 ext[1] = (htons(m[1]) << 16) | htons(m[2]); 990 TI_DO_CMD_EXT(TI_CMD_EXT_DEL_MCAST, 0, 0, (caddr_t)&ext, 2); 991 break; 992 default: 993 if_printf(&sc->arpcom.ac_if, "unknown hwrev\n"); 994 break; 995 } 996 } 997 998 /* 999 * Configure the Tigon's multicast address filter. 1000 * 1001 * The actual multicast table management is a bit of a pain, thanks to 1002 * slight brain damage on the part of both Alteon and us. With our 1003 * multicast code, we are only alerted when the multicast address table 1004 * changes and at that point we only have the current list of addresses: 1005 * we only know the current state, not the previous state, so we don't 1006 * actually know what addresses were removed or added. The firmware has 1007 * state, but we can't get our grubby mits on it, and there is no 'delete 1008 * all multicast addresses' command. Hence, we have to maintain our own 1009 * state so we know what addresses have been programmed into the NIC at 1010 * any given time. 1011 */ 1012 static void 1013 ti_setmulti(struct ti_softc *sc) 1014 { 1015 struct ifnet *ifp = &sc->arpcom.ac_if; 1016 struct ifmultiaddr *ifma; 1017 struct ti_cmd_desc cmd; 1018 struct ti_mc_entry *mc; 1019 uint32_t intrs; 1020 1021 if (ifp->if_flags & IFF_ALLMULTI) { 1022 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_ENB, 0); 1023 return; 1024 } 1025 1026 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_DIS, 0); 1027 1028 /* Disable interrupts. */ 1029 intrs = CSR_READ_4(sc, TI_MB_HOSTINTR); 1030 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 1031 1032 /* First, zot all the existing filters. */ 1033 while (sc->ti_mc_listhead.slh_first != NULL) { 1034 mc = sc->ti_mc_listhead.slh_first; 1035 ti_del_mcast(sc, &mc->mc_addr); 1036 SLIST_REMOVE_HEAD(&sc->ti_mc_listhead, mc_entries); 1037 free(mc, M_DEVBUF); 1038 } 1039 1040 /* Now program new ones. */ 1041 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1042 if (ifma->ifma_addr->sa_family != AF_LINK) 1043 continue; 1044 mc = malloc(sizeof(struct ti_mc_entry), M_DEVBUF, M_INTWAIT); 1045 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 1046 &mc->mc_addr, ETHER_ADDR_LEN); 1047 SLIST_INSERT_HEAD(&sc->ti_mc_listhead, mc, mc_entries); 1048 ti_add_mcast(sc, &mc->mc_addr); 1049 } 1050 1051 /* Re-enable interrupts. */ 1052 CSR_WRITE_4(sc, TI_MB_HOSTINTR, intrs); 1053 } 1054 1055 /* 1056 * Check to see if the BIOS has configured us for a 64 bit slot when 1057 * we aren't actually in one. If we detect this condition, we can work 1058 * around it on the Tigon 2 by setting a bit in the PCI state register, 1059 * but for the Tigon 1 we must give up and abort the interface attach. 1060 */ 1061 static int 1062 ti_64bitslot_war(struct ti_softc *sc) 1063 { 1064 if ((CSR_READ_4(sc, TI_PCI_STATE) & TI_PCISTATE_32BIT_BUS) == 0) { 1065 CSR_WRITE_4(sc, 0x600, 0); 1066 CSR_WRITE_4(sc, 0x604, 0); 1067 CSR_WRITE_4(sc, 0x600, 0x5555AAAA); 1068 if (CSR_READ_4(sc, 0x604) == 0x5555AAAA) { 1069 if (sc->ti_hwrev == TI_HWREV_TIGON) 1070 return(EINVAL); 1071 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_32BIT_BUS); 1072 return(0); 1073 } 1074 } 1075 1076 return(0); 1077 } 1078 1079 /* 1080 * Do endian, PCI and DMA initialization. Also check the on-board ROM 1081 * self-test results. 1082 */ 1083 static int 1084 ti_chipinit(struct ti_softc *sc) 1085 { 1086 struct ifnet *ifp = &sc->arpcom.ac_if; 1087 uint32_t cacheline; 1088 uint32_t pci_writemax = 0; 1089 1090 /* Initialize link to down state. */ 1091 sc->ti_linkstat = TI_EV_CODE_LINK_DOWN; 1092 1093 if (ifp->if_capenable & IFCAP_HWCSUM) 1094 ifp->if_hwassist = TI_CSUM_FEATURES; 1095 else 1096 ifp->if_hwassist = 0; 1097 1098 /* Set endianness before we access any non-PCI registers. */ 1099 #if BYTE_ORDER == BIG_ENDIAN 1100 CSR_WRITE_4(sc, TI_MISC_HOST_CTL, 1101 TI_MHC_BIGENDIAN_INIT | (TI_MHC_BIGENDIAN_INIT << 24)); 1102 #else 1103 CSR_WRITE_4(sc, TI_MISC_HOST_CTL, 1104 TI_MHC_LITTLEENDIAN_INIT | (TI_MHC_LITTLEENDIAN_INIT << 24)); 1105 #endif 1106 1107 /* Check the ROM failed bit to see if self-tests passed. */ 1108 if (CSR_READ_4(sc, TI_CPU_STATE) & TI_CPUSTATE_ROMFAIL) { 1109 if_printf(ifp, "board self-diagnostics failed!\n"); 1110 return(ENODEV); 1111 } 1112 1113 /* Halt the CPU. */ 1114 TI_SETBIT(sc, TI_CPU_STATE, TI_CPUSTATE_HALT); 1115 1116 /* Figure out the hardware revision. */ 1117 switch(CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_CHIP_REV_MASK) { 1118 case TI_REV_TIGON_I: 1119 sc->ti_hwrev = TI_HWREV_TIGON; 1120 break; 1121 case TI_REV_TIGON_II: 1122 sc->ti_hwrev = TI_HWREV_TIGON_II; 1123 break; 1124 default: 1125 if_printf(ifp, "unsupported chip revision\n"); 1126 return(ENODEV); 1127 } 1128 1129 /* Do special setup for Tigon 2. */ 1130 if (sc->ti_hwrev == TI_HWREV_TIGON_II) { 1131 TI_SETBIT(sc, TI_CPU_CTL_B, TI_CPUSTATE_HALT); 1132 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_SRAM_BANK_512K); 1133 TI_SETBIT(sc, TI_MISC_CONF, TI_MCR_SRAM_SYNCHRONOUS); 1134 } 1135 1136 /* Set up the PCI state register. */ 1137 CSR_WRITE_4(sc, TI_PCI_STATE, TI_PCI_READ_CMD|TI_PCI_WRITE_CMD); 1138 if (sc->ti_hwrev == TI_HWREV_TIGON_II) { 1139 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_USE_MEM_RD_MULT); 1140 } 1141 1142 /* Clear the read/write max DMA parameters. */ 1143 TI_CLRBIT(sc, TI_PCI_STATE, (TI_PCISTATE_WRITE_MAXDMA| 1144 TI_PCISTATE_READ_MAXDMA)); 1145 1146 /* Get cache line size. */ 1147 cacheline = CSR_READ_4(sc, TI_PCI_BIST) & 0xFF; 1148 1149 /* 1150 * If the system has set enabled the PCI memory write 1151 * and invalidate command in the command register, set 1152 * the write max parameter accordingly. This is necessary 1153 * to use MWI with the Tigon 2. 1154 */ 1155 if (CSR_READ_4(sc, TI_PCI_CMDSTAT) & PCIM_CMD_MWIEN) { 1156 switch(cacheline) { 1157 case 1: 1158 case 4: 1159 case 8: 1160 case 16: 1161 case 32: 1162 case 64: 1163 break; 1164 default: 1165 /* Disable PCI memory write and invalidate. */ 1166 if (bootverbose) { 1167 if_printf(ifp, "cache line size %d not " 1168 "supported; disabling PCI MWI\n", 1169 cacheline); 1170 } 1171 CSR_WRITE_4(sc, TI_PCI_CMDSTAT, CSR_READ_4(sc, 1172 TI_PCI_CMDSTAT) & ~PCIM_CMD_MWIEN); 1173 break; 1174 } 1175 } 1176 1177 TI_SETBIT(sc, TI_PCI_STATE, pci_writemax); 1178 1179 /* This sets the min dma param all the way up (0xff). */ 1180 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_MINDMA); 1181 1182 /* Configure DMA variables. */ 1183 #if BYTE_ORDER == BIG_ENDIAN 1184 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_BD | 1185 TI_OPMODE_BYTESWAP_DATA | TI_OPMODE_WORDSWAP_BD | 1186 TI_OPMODE_WARN_ENB | TI_OPMODE_FATAL_ENB | 1187 TI_OPMODE_DONT_FRAG_JUMBO); 1188 #else 1189 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_DATA| 1190 TI_OPMODE_WORDSWAP_BD|TI_OPMODE_DONT_FRAG_JUMBO| 1191 TI_OPMODE_WARN_ENB|TI_OPMODE_FATAL_ENB); 1192 #endif 1193 1194 /* 1195 * Only allow 1 DMA channel to be active at a time. 1196 * I don't think this is a good idea, but without it 1197 * the firmware racks up lots of nicDmaReadRingFull 1198 * errors. This is not compatible with hardware checksums. 1199 */ 1200 if (ifp->if_hwassist == 0) 1201 TI_SETBIT(sc, TI_GCR_OPMODE, TI_OPMODE_1_DMA_ACTIVE); 1202 1203 /* Recommended settings from Tigon manual. */ 1204 CSR_WRITE_4(sc, TI_GCR_DMA_WRITECFG, TI_DMA_STATE_THRESH_8W); 1205 CSR_WRITE_4(sc, TI_GCR_DMA_READCFG, TI_DMA_STATE_THRESH_8W); 1206 1207 if (ti_64bitslot_war(sc)) { 1208 if_printf(ifp, "bios thinks we're in a 64 bit slot, " 1209 "but we aren't"); 1210 return(EINVAL); 1211 } 1212 1213 return(0); 1214 } 1215 1216 /* 1217 * Initialize the general information block and firmware, and 1218 * start the CPU(s) running. 1219 */ 1220 static int 1221 ti_gibinit(struct ti_softc *sc) 1222 { 1223 struct ifnet *ifp = &sc->arpcom.ac_if; 1224 struct ti_rcb *rcb; 1225 int i; 1226 1227 /* Disable interrupts for now. */ 1228 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 1229 1230 /* Tell the chip where to find the general information block. */ 1231 CSR_WRITE_4(sc, TI_GCR_GENINFO_HI, 0); 1232 CSR_WRITE_4(sc, TI_GCR_GENINFO_LO, vtophys(&sc->ti_rdata->ti_info)); 1233 1234 /* Load the firmware into SRAM. */ 1235 ti_loadfw(sc); 1236 1237 /* Set up the contents of the general info and ring control blocks. */ 1238 1239 /* Set up the event ring and producer pointer. */ 1240 rcb = &sc->ti_rdata->ti_info.ti_ev_rcb; 1241 1242 TI_HOSTADDR(rcb->ti_hostaddr) = vtophys(&sc->ti_rdata->ti_event_ring); 1243 rcb->ti_flags = 0; 1244 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_ev_prodidx_ptr) = 1245 vtophys(&sc->ti_ev_prodidx); 1246 sc->ti_ev_prodidx.ti_idx = 0; 1247 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, 0); 1248 sc->ti_ev_saved_considx = 0; 1249 1250 /* Set up the command ring and producer mailbox. */ 1251 rcb = &sc->ti_rdata->ti_info.ti_cmd_rcb; 1252 1253 sc->ti_rdata->ti_cmd_ring = 1254 (struct ti_cmd_desc *)(sc->ti_vhandle + TI_GCR_CMDRING); 1255 TI_HOSTADDR(rcb->ti_hostaddr) = TI_GCR_NIC_ADDR(TI_GCR_CMDRING); 1256 rcb->ti_flags = 0; 1257 rcb->ti_max_len = 0; 1258 for (i = 0; i < TI_CMD_RING_CNT; i++) 1259 CSR_WRITE_4(sc, TI_GCR_CMDRING + (i * 4), 0); 1260 CSR_WRITE_4(sc, TI_GCR_CMDCONS_IDX, 0); 1261 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, 0); 1262 sc->ti_cmd_saved_prodidx = 0; 1263 1264 /* 1265 * Assign the address of the stats refresh buffer. 1266 * We re-use the current stats buffer for this to 1267 * conserve memory. 1268 */ 1269 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_refresh_stats_ptr) = 1270 vtophys(&sc->ti_rdata->ti_info.ti_stats); 1271 1272 /* Set up the standard receive ring. */ 1273 rcb = &sc->ti_rdata->ti_info.ti_std_rx_rcb; 1274 TI_HOSTADDR(rcb->ti_hostaddr) = vtophys(&sc->ti_rdata->ti_rx_std_ring); 1275 rcb->ti_max_len = TI_FRAMELEN; 1276 rcb->ti_flags = 0; 1277 if (ifp->if_hwassist) 1278 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 1279 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 1280 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1281 1282 /* Set up the jumbo receive ring. */ 1283 rcb = &sc->ti_rdata->ti_info.ti_jumbo_rx_rcb; 1284 TI_HOSTADDR(rcb->ti_hostaddr) = 1285 vtophys(&sc->ti_rdata->ti_rx_jumbo_ring); 1286 rcb->ti_max_len = TI_JUMBO_FRAMELEN; 1287 rcb->ti_flags = 0; 1288 if (ifp->if_hwassist) 1289 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 1290 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 1291 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1292 1293 /* 1294 * Set up the mini ring. Only activated on the 1295 * Tigon 2 but the slot in the config block is 1296 * still there on the Tigon 1. 1297 */ 1298 rcb = &sc->ti_rdata->ti_info.ti_mini_rx_rcb; 1299 TI_HOSTADDR(rcb->ti_hostaddr) = 1300 vtophys(&sc->ti_rdata->ti_rx_mini_ring); 1301 rcb->ti_max_len = MHLEN - ETHER_ALIGN; 1302 if (sc->ti_hwrev == TI_HWREV_TIGON) 1303 rcb->ti_flags = TI_RCB_FLAG_RING_DISABLED; 1304 else 1305 rcb->ti_flags = 0; 1306 if (ifp->if_hwassist) 1307 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 1308 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 1309 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1310 1311 /* 1312 * Set up the receive return ring. 1313 */ 1314 rcb = &sc->ti_rdata->ti_info.ti_return_rcb; 1315 TI_HOSTADDR(rcb->ti_hostaddr) = 1316 vtophys(&sc->ti_rdata->ti_rx_return_ring); 1317 rcb->ti_flags = 0; 1318 rcb->ti_max_len = TI_RETURN_RING_CNT; 1319 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_return_prodidx_ptr) = 1320 vtophys(&sc->ti_return_prodidx); 1321 1322 /* 1323 * Set up the tx ring. Note: for the Tigon 2, we have the option 1324 * of putting the transmit ring in the host's address space and 1325 * letting the chip DMA it instead of leaving the ring in the NIC's 1326 * memory and accessing it through the shared memory region. We 1327 * do this for the Tigon 2, but it doesn't work on the Tigon 1, 1328 * so we have to revert to the shared memory scheme if we detect 1329 * a Tigon 1 chip. 1330 */ 1331 CSR_WRITE_4(sc, TI_WINBASE, TI_TX_RING_BASE); 1332 if (sc->ti_hwrev == TI_HWREV_TIGON) { 1333 sc->ti_rdata->ti_tx_ring_nic = 1334 (struct ti_tx_desc *)(sc->ti_vhandle + TI_WINDOW); 1335 } 1336 bzero(sc->ti_rdata->ti_tx_ring, 1337 TI_TX_RING_CNT * sizeof(struct ti_tx_desc)); 1338 rcb = &sc->ti_rdata->ti_info.ti_tx_rcb; 1339 if (sc->ti_hwrev == TI_HWREV_TIGON) 1340 rcb->ti_flags = 0; 1341 else 1342 rcb->ti_flags = TI_RCB_FLAG_HOST_RING; 1343 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1344 if (ifp->if_hwassist) 1345 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 1346 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 1347 rcb->ti_max_len = TI_TX_RING_CNT; 1348 if (sc->ti_hwrev == TI_HWREV_TIGON) 1349 TI_HOSTADDR(rcb->ti_hostaddr) = TI_TX_RING_BASE; 1350 else 1351 TI_HOSTADDR(rcb->ti_hostaddr) = 1352 vtophys(&sc->ti_rdata->ti_tx_ring); 1353 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_tx_considx_ptr) = 1354 vtophys(&sc->ti_tx_considx); 1355 1356 /* Set up tuneables */ 1357 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 1358 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, 1359 (sc->ti_rx_coal_ticks / 10)); 1360 else 1361 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, sc->ti_rx_coal_ticks); 1362 CSR_WRITE_4(sc, TI_GCR_TX_COAL_TICKS, sc->ti_tx_coal_ticks); 1363 CSR_WRITE_4(sc, TI_GCR_STAT_TICKS, sc->ti_stat_ticks); 1364 CSR_WRITE_4(sc, TI_GCR_RX_MAX_COAL_BD, sc->ti_rx_max_coal_bds); 1365 CSR_WRITE_4(sc, TI_GCR_TX_MAX_COAL_BD, sc->ti_tx_max_coal_bds); 1366 CSR_WRITE_4(sc, TI_GCR_TX_BUFFER_RATIO, sc->ti_tx_buf_ratio); 1367 1368 /* Turn interrupts on. */ 1369 CSR_WRITE_4(sc, TI_GCR_MASK_INTRS, 0); 1370 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 1371 1372 /* Start CPU. */ 1373 TI_CLRBIT(sc, TI_CPU_STATE, (TI_CPUSTATE_HALT|TI_CPUSTATE_STEP)); 1374 1375 return(0); 1376 } 1377 1378 /* 1379 * Probe for a Tigon chip. Check the PCI vendor and device IDs 1380 * against our list and return its name if we find a match. 1381 */ 1382 static int 1383 ti_probe(device_t dev) 1384 { 1385 struct ti_type *t; 1386 uint16_t vendor, product; 1387 1388 vendor = pci_get_vendor(dev); 1389 product = pci_get_device(dev); 1390 1391 for (t = ti_devs; t->ti_name != NULL; t++) { 1392 if (vendor == t->ti_vid && product == t->ti_did) { 1393 device_set_desc(dev, t->ti_name); 1394 return(0); 1395 } 1396 } 1397 1398 return(ENXIO); 1399 } 1400 1401 static int 1402 ti_attach(device_t dev) 1403 { 1404 struct ti_softc *sc; 1405 struct ifnet *ifp; 1406 int error = 0, rid; 1407 uint8_t eaddr[ETHER_ADDR_LEN]; 1408 1409 sc = device_get_softc(dev); 1410 ifp = &sc->arpcom.ac_if; 1411 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1412 ifp->if_capabilities = IFCAP_HWCSUM; 1413 ifp->if_capenable = ifp->if_capabilities; 1414 1415 pci_enable_busmaster(dev); 1416 1417 /* 1418 * Initialize media before any possible error may occur, 1419 * so we can destroy it unconditionally, if an error occurs later on. 1420 */ 1421 ifmedia_init(&sc->ifmedia, IFM_IMASK, ti_ifmedia_upd, ti_ifmedia_sts); 1422 1423 rid = TI_PCI_LOMEM; 1424 sc->ti_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 1425 RF_ACTIVE); 1426 1427 if (sc->ti_res == NULL) { 1428 device_printf(dev, "couldn't map memory\n"); 1429 error = ENXIO; 1430 goto fail; 1431 } 1432 1433 sc->ti_btag = rman_get_bustag(sc->ti_res); 1434 sc->ti_bhandle = rman_get_bushandle(sc->ti_res); 1435 sc->ti_vhandle = (vm_offset_t)rman_get_virtual(sc->ti_res); 1436 1437 /* Allocate interrupt */ 1438 rid = 0; 1439 sc->ti_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1440 RF_SHAREABLE | RF_ACTIVE); 1441 if (sc->ti_irq == NULL) { 1442 device_printf(dev, "couldn't map interrupt\n"); 1443 error = ENXIO; 1444 goto fail; 1445 } 1446 1447 if (ti_chipinit(sc)) { 1448 device_printf(dev, "chip initialization failed\n"); 1449 error = ENXIO; 1450 goto fail; 1451 } 1452 1453 /* Zero out the NIC's on-board SRAM. */ 1454 ti_mem(sc, 0x2000, 0x100000 - 0x2000, NULL); 1455 1456 /* Init again -- zeroing memory may have clobbered some registers. */ 1457 if (ti_chipinit(sc)) { 1458 device_printf(dev, "chip initialization failed\n"); 1459 error = ENXIO; 1460 goto fail; 1461 } 1462 1463 /* 1464 * Get station address from the EEPROM. Note: the manual states 1465 * that the MAC address is at offset 0x8c, however the data is 1466 * stored as two longwords (since that's how it's loaded into 1467 * the NIC). This means the MAC address is actually preceeded 1468 * by two zero bytes. We need to skip over those. 1469 */ 1470 if (ti_read_eeprom(sc, eaddr, TI_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) { 1471 device_printf(dev, "failed to read station address\n"); 1472 error = ENXIO; 1473 goto fail; 1474 } 1475 1476 /* Allocate the general information block and ring buffers. */ 1477 sc->ti_rdata = contigmalloc(sizeof(struct ti_ring_data), M_DEVBUF, 1478 M_WAITOK, 0, 0xffffffff, PAGE_SIZE, 0); 1479 1480 if (sc->ti_rdata == NULL) { 1481 device_printf(dev, "no memory for list buffers!\n"); 1482 error = ENXIO; 1483 goto fail; 1484 } 1485 1486 bzero(sc->ti_rdata, sizeof(struct ti_ring_data)); 1487 1488 /* Try to allocate memory for jumbo buffers. */ 1489 if (ti_alloc_jumbo_mem(sc)) { 1490 device_printf(dev, "jumbo buffer allocation failed\n"); 1491 error = ENXIO; 1492 goto fail; 1493 } 1494 1495 /* 1496 * We really need a better way to tell a 1000baseTX card 1497 * from a 1000baseSX one, since in theory there could be 1498 * OEMed 1000baseTX cards from lame vendors who aren't 1499 * clever enough to change the PCI ID. For the moment 1500 * though, the AceNIC is the only copper card available. 1501 */ 1502 if (pci_get_vendor(dev) == ALT_VENDORID && 1503 pci_get_device(dev) == ALT_DEVICEID_ACENIC_COPPER) 1504 sc->ti_copper = 1; 1505 /* Ok, it's not the only copper card available. */ 1506 if (pci_get_vendor(dev) == NG_VENDORID && 1507 pci_get_device(dev) == NG_DEVICEID_GA620T) 1508 sc->ti_copper = 1; 1509 1510 /* Set default tuneable values. */ 1511 sc->ti_stat_ticks = 2 * TI_TICKS_PER_SEC; 1512 sc->ti_rx_coal_ticks = TI_TICKS_PER_SEC / 5000; 1513 sc->ti_tx_coal_ticks = TI_TICKS_PER_SEC / 500; 1514 sc->ti_rx_max_coal_bds = 64; 1515 sc->ti_tx_max_coal_bds = 128; 1516 sc->ti_tx_buf_ratio = 21; 1517 1518 /* Set up ifnet structure */ 1519 ifp->if_softc = sc; 1520 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1521 ifp->if_ioctl = ti_ioctl; 1522 ifp->if_start = ti_start; 1523 ifp->if_watchdog = ti_watchdog; 1524 ifp->if_init = ti_init; 1525 ifp->if_mtu = ETHERMTU; 1526 ifq_set_maxlen(&ifp->if_snd, TI_TX_RING_CNT - 1); 1527 ifq_set_ready(&ifp->if_snd); 1528 1529 /* Set up ifmedia support. */ 1530 if (sc->ti_copper) { 1531 /* 1532 * Copper cards allow manual 10/100 mode selection, 1533 * but not manual 1000baseTX mode selection. Why? 1534 * Becuase currently there's no way to specify the 1535 * master/slave setting through the firmware interface, 1536 * so Alteon decided to just bag it and handle it 1537 * via autonegotiation. 1538 */ 1539 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL); 1540 ifmedia_add(&sc->ifmedia, 1541 IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL); 1542 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_TX, 0, NULL); 1543 ifmedia_add(&sc->ifmedia, 1544 IFM_ETHER|IFM_100_TX|IFM_FDX, 0, NULL); 1545 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_1000_T, 0, NULL); 1546 ifmedia_add(&sc->ifmedia, 1547 IFM_ETHER|IFM_1000_T | IFM_FDX, 0, NULL); 1548 } else { 1549 /* Fiber cards don't support 10/100 modes. */ 1550 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL); 1551 ifmedia_add(&sc->ifmedia, 1552 IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL); 1553 } 1554 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 1555 ifmedia_set(&sc->ifmedia, IFM_ETHER|IFM_AUTO); 1556 1557 /* 1558 * Call MI attach routine. 1559 */ 1560 ether_ifattach(ifp, eaddr, NULL); 1561 1562 error = bus_setup_intr(dev, sc->ti_irq, INTR_NETSAFE, 1563 ti_intr, sc, &sc->ti_intrhand, 1564 ifp->if_serializer); 1565 if (error) { 1566 device_printf(dev, "couldn't set up irq\n"); 1567 ether_ifdetach(ifp); 1568 goto fail; 1569 } 1570 return 0; 1571 1572 fail: 1573 ti_detach(dev); 1574 return(error); 1575 } 1576 1577 static int 1578 ti_detach(device_t dev) 1579 { 1580 struct ti_softc *sc = device_get_softc(dev); 1581 struct ifnet *ifp = &sc->arpcom.ac_if; 1582 1583 if (device_is_attached(dev)) { 1584 lwkt_serialize_enter(ifp->if_serializer); 1585 ti_stop(sc); 1586 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 1587 lwkt_serialize_exit(ifp->if_serializer); 1588 1589 ether_ifdetach(ifp); 1590 } 1591 1592 if (sc->ti_irq != NULL) 1593 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 1594 if (sc->ti_res != NULL) { 1595 bus_release_resource(dev, SYS_RES_MEMORY, 1596 TI_PCI_LOMEM, sc->ti_res); 1597 } 1598 if (sc->ti_cdata.ti_jumbo_buf != NULL) 1599 contigfree(sc->ti_cdata.ti_jumbo_buf, TI_JMEM, M_DEVBUF); 1600 if (sc->ti_rdata != NULL) 1601 contigfree(sc->ti_rdata, sizeof(struct ti_ring_data), M_DEVBUF); 1602 ifmedia_removeall(&sc->ifmedia); 1603 1604 1605 return(0); 1606 } 1607 1608 /* 1609 * Frame reception handling. This is called if there's a frame 1610 * on the receive return list. 1611 * 1612 * Note: we have to be able to handle three possibilities here: 1613 * 1) the frame is from the mini receive ring (can only happen) 1614 * on Tigon 2 boards) 1615 * 2) the frame is from the jumbo recieve ring 1616 * 3) the frame is from the standard receive ring 1617 */ 1618 static void 1619 ti_rxeof(struct ti_softc *sc) 1620 { 1621 struct ifnet *ifp = &sc->arpcom.ac_if; 1622 struct ti_cmd_desc cmd; 1623 1624 while(sc->ti_rx_saved_considx != sc->ti_return_prodidx.ti_idx) { 1625 struct ti_rx_desc *cur_rx; 1626 uint32_t rxidx; 1627 struct mbuf *m; 1628 uint16_t vlan_tag = 0; 1629 int have_tag = 0; 1630 1631 cur_rx = 1632 &sc->ti_rdata->ti_rx_return_ring[sc->ti_rx_saved_considx]; 1633 rxidx = cur_rx->ti_idx; 1634 TI_INC(sc->ti_rx_saved_considx, TI_RETURN_RING_CNT); 1635 1636 if (cur_rx->ti_flags & TI_BDFLAG_VLAN_TAG) { 1637 have_tag = 1; 1638 vlan_tag = cur_rx->ti_vlan_tag & 0xfff; 1639 } 1640 1641 if (cur_rx->ti_flags & TI_BDFLAG_JUMBO_RING) { 1642 TI_INC(sc->ti_jumbo, TI_JUMBO_RX_RING_CNT); 1643 m = sc->ti_cdata.ti_rx_jumbo_chain[rxidx]; 1644 sc->ti_cdata.ti_rx_jumbo_chain[rxidx] = NULL; 1645 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 1646 ifp->if_ierrors++; 1647 ti_newbuf_jumbo(sc, sc->ti_jumbo, m); 1648 continue; 1649 } 1650 if (ti_newbuf_jumbo(sc, sc->ti_jumbo, NULL) == ENOBUFS) { 1651 ifp->if_ierrors++; 1652 ti_newbuf_jumbo(sc, sc->ti_jumbo, m); 1653 continue; 1654 } 1655 } else if (cur_rx->ti_flags & TI_BDFLAG_MINI_RING) { 1656 TI_INC(sc->ti_mini, TI_MINI_RX_RING_CNT); 1657 m = sc->ti_cdata.ti_rx_mini_chain[rxidx]; 1658 sc->ti_cdata.ti_rx_mini_chain[rxidx] = NULL; 1659 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 1660 ifp->if_ierrors++; 1661 ti_newbuf_mini(sc, sc->ti_mini, m); 1662 continue; 1663 } 1664 if (ti_newbuf_mini(sc, sc->ti_mini, NULL) == ENOBUFS) { 1665 ifp->if_ierrors++; 1666 ti_newbuf_mini(sc, sc->ti_mini, m); 1667 continue; 1668 } 1669 } else { 1670 TI_INC(sc->ti_std, TI_STD_RX_RING_CNT); 1671 m = sc->ti_cdata.ti_rx_std_chain[rxidx]; 1672 sc->ti_cdata.ti_rx_std_chain[rxidx] = NULL; 1673 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 1674 ifp->if_ierrors++; 1675 ti_newbuf_std(sc, sc->ti_std, m); 1676 continue; 1677 } 1678 if (ti_newbuf_std(sc, sc->ti_std, NULL) == ENOBUFS) { 1679 ifp->if_ierrors++; 1680 ti_newbuf_std(sc, sc->ti_std, m); 1681 continue; 1682 } 1683 } 1684 1685 m->m_pkthdr.len = m->m_len = cur_rx->ti_len; 1686 ifp->if_ipackets++; 1687 m->m_pkthdr.rcvif = ifp; 1688 1689 if (ifp->if_hwassist) { 1690 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED | 1691 CSUM_DATA_VALID; 1692 if ((cur_rx->ti_ip_cksum ^ 0xffff) == 0) 1693 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1694 m->m_pkthdr.csum_data = cur_rx->ti_tcp_udp_cksum; 1695 } 1696 1697 /* 1698 * If we received a packet with a vlan tag, pass it 1699 * to vlan_input() instead of ether_input(). 1700 */ 1701 lwkt_serialize_enter(ifp->if_serializer); 1702 if (have_tag) 1703 VLAN_INPUT_TAG(m, vlan_tag); 1704 else 1705 ifp->if_input(ifp, m); 1706 lwkt_serialize_exit(ifp->if_serializer); 1707 } 1708 1709 /* Only necessary on the Tigon 1. */ 1710 if (sc->ti_hwrev == TI_HWREV_TIGON) 1711 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 1712 sc->ti_rx_saved_considx); 1713 1714 TI_UPDATE_STDPROD(sc, sc->ti_std); 1715 TI_UPDATE_MINIPROD(sc, sc->ti_mini); 1716 TI_UPDATE_JUMBOPROD(sc, sc->ti_jumbo); 1717 } 1718 1719 static void 1720 ti_txeof(struct ti_softc *sc) 1721 { 1722 struct ifnet *ifp = &sc->arpcom.ac_if; 1723 struct ti_tx_desc *cur_tx = NULL; 1724 1725 /* 1726 * Go through our tx ring and free mbufs for those 1727 * frames that have been sent. 1728 */ 1729 while (sc->ti_tx_saved_considx != sc->ti_tx_considx.ti_idx) { 1730 uint32_t idx = 0; 1731 1732 idx = sc->ti_tx_saved_considx; 1733 if (sc->ti_hwrev != TI_HWREV_TIGON) { 1734 if (idx > 383) 1735 CSR_WRITE_4(sc, TI_WINBASE, 1736 TI_TX_RING_BASE + 6144); 1737 else if (idx > 255) 1738 CSR_WRITE_4(sc, TI_WINBASE, 1739 TI_TX_RING_BASE + 4096); 1740 else if (idx > 127) 1741 CSR_WRITE_4(sc, TI_WINBASE, 1742 TI_TX_RING_BASE + 2048); 1743 else 1744 CSR_WRITE_4(sc, TI_WINBASE, 1745 TI_TX_RING_BASE); 1746 cur_tx = &sc->ti_rdata->ti_tx_ring_nic[idx % 128]; 1747 } else 1748 cur_tx = &sc->ti_rdata->ti_tx_ring[idx]; 1749 if (cur_tx->ti_flags & TI_BDFLAG_END) 1750 ifp->if_opackets++; 1751 if (sc->ti_cdata.ti_tx_chain[idx] != NULL) { 1752 m_freem(sc->ti_cdata.ti_tx_chain[idx]); 1753 sc->ti_cdata.ti_tx_chain[idx] = NULL; 1754 } 1755 sc->ti_txcnt--; 1756 TI_INC(sc->ti_tx_saved_considx, TI_TX_RING_CNT); 1757 ifp->if_timer = 0; 1758 } 1759 1760 if (cur_tx != NULL) 1761 ifp->if_flags &= ~IFF_OACTIVE; 1762 } 1763 1764 static void 1765 ti_intr(void *xsc) 1766 { 1767 struct ti_softc *sc = xsc; 1768 struct ifnet *ifp = &sc->arpcom.ac_if; 1769 1770 #ifdef notdef 1771 /* Avoid this for now -- checking this register is expensive. */ 1772 /* Make sure this is really our interrupt. */ 1773 if ((CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_INTSTATE) == 0) 1774 return; 1775 #endif 1776 1777 /* Ack interrupt and stop others from occuring. */ 1778 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 1779 1780 if (ifp->if_flags & IFF_RUNNING) { 1781 /* Check RX return ring producer/consumer */ 1782 ti_rxeof(sc); 1783 1784 /* Check TX ring producer/consumer */ 1785 ti_txeof(sc); 1786 } 1787 1788 ti_handle_events(sc); 1789 1790 /* Re-enable interrupts. */ 1791 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 1792 1793 if ((ifp->if_flags & IFF_RUNNING) && !ifq_is_empty(&ifp->if_snd)) 1794 ti_start(ifp); 1795 } 1796 1797 static void 1798 ti_stats_update(struct ti_softc *sc) 1799 { 1800 struct ifnet *ifp = &sc->arpcom.ac_if; 1801 1802 ifp->if_collisions += 1803 (sc->ti_rdata->ti_info.ti_stats.dot3StatsSingleCollisionFrames + 1804 sc->ti_rdata->ti_info.ti_stats.dot3StatsMultipleCollisionFrames + 1805 sc->ti_rdata->ti_info.ti_stats.dot3StatsExcessiveCollisions + 1806 sc->ti_rdata->ti_info.ti_stats.dot3StatsLateCollisions) - 1807 ifp->if_collisions; 1808 } 1809 1810 /* 1811 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 1812 * pointers to descriptors. 1813 */ 1814 static int 1815 ti_encap(struct ti_softc *sc, struct mbuf *m_head, uint32_t *txidx) 1816 { 1817 struct ti_tx_desc *f = NULL; 1818 struct mbuf *m; 1819 struct ifvlan *ifv = NULL; 1820 uint32_t cnt = 0, cur, frag; 1821 uint16_t csum_flags = 0; 1822 1823 if ((m_head->m_flags & (M_PROTO1|M_PKTHDR)) == (M_PROTO1|M_PKTHDR) && 1824 m_head->m_pkthdr.rcvif != NULL && 1825 m_head->m_pkthdr.rcvif->if_type == IFT_L2VLAN) 1826 ifv = m_head->m_pkthdr.rcvif->if_softc; 1827 1828 m = m_head; 1829 cur = frag = *txidx; 1830 1831 if (m_head->m_pkthdr.csum_flags) { 1832 if (m_head->m_pkthdr.csum_flags & CSUM_IP) 1833 csum_flags |= TI_BDFLAG_IP_CKSUM; 1834 if (m_head->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) 1835 csum_flags |= TI_BDFLAG_TCP_UDP_CKSUM; 1836 if (m_head->m_flags & M_LASTFRAG) 1837 csum_flags |= TI_BDFLAG_IP_FRAG_END; 1838 else if (m_head->m_flags & M_FRAG) 1839 csum_flags |= TI_BDFLAG_IP_FRAG; 1840 } 1841 /* 1842 * Start packing the mbufs in this chain into 1843 * the fragment pointers. Stop when we run out 1844 * of fragments or hit the end of the mbuf chain. 1845 */ 1846 for (m = m_head; m != NULL; m = m->m_next) { 1847 if (m->m_len != 0) { 1848 if (sc->ti_hwrev == TI_HWREV_TIGON) { 1849 if (frag > 383) 1850 CSR_WRITE_4(sc, TI_WINBASE, 1851 TI_TX_RING_BASE + 6144); 1852 else if (frag > 255) 1853 CSR_WRITE_4(sc, TI_WINBASE, 1854 TI_TX_RING_BASE + 4096); 1855 else if (frag > 127) 1856 CSR_WRITE_4(sc, TI_WINBASE, 1857 TI_TX_RING_BASE + 2048); 1858 else 1859 CSR_WRITE_4(sc, TI_WINBASE, 1860 TI_TX_RING_BASE); 1861 f = &sc->ti_rdata->ti_tx_ring_nic[frag % 128]; 1862 } else 1863 f = &sc->ti_rdata->ti_tx_ring[frag]; 1864 if (sc->ti_cdata.ti_tx_chain[frag] != NULL) 1865 break; 1866 TI_HOSTADDR(f->ti_addr) = vtophys(mtod(m, vm_offset_t)); 1867 f->ti_len = m->m_len; 1868 f->ti_flags = csum_flags; 1869 1870 if (ifv != NULL) { 1871 f->ti_flags |= TI_BDFLAG_VLAN_TAG; 1872 f->ti_vlan_tag = ifv->ifv_tag & 0xfff; 1873 } else { 1874 f->ti_vlan_tag = 0; 1875 } 1876 1877 /* 1878 * Sanity check: avoid coming within 16 descriptors 1879 * of the end of the ring. 1880 */ 1881 if ((TI_TX_RING_CNT - (sc->ti_txcnt + cnt)) < 16) 1882 return(ENOBUFS); 1883 cur = frag; 1884 TI_INC(frag, TI_TX_RING_CNT); 1885 cnt++; 1886 } 1887 } 1888 1889 if (m != NULL) 1890 return(ENOBUFS); 1891 1892 if (frag == sc->ti_tx_saved_considx) 1893 return(ENOBUFS); 1894 1895 if (sc->ti_hwrev == TI_HWREV_TIGON) 1896 sc->ti_rdata->ti_tx_ring_nic[cur % 128].ti_flags |= 1897 TI_BDFLAG_END; 1898 else 1899 sc->ti_rdata->ti_tx_ring[cur].ti_flags |= TI_BDFLAG_END; 1900 sc->ti_cdata.ti_tx_chain[cur] = m_head; 1901 sc->ti_txcnt += cnt; 1902 1903 *txidx = frag; 1904 1905 return(0); 1906 } 1907 1908 /* 1909 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1910 * to the mbuf data regions directly in the transmit descriptors. 1911 */ 1912 static void 1913 ti_start(struct ifnet *ifp) 1914 { 1915 struct ti_softc *sc = ifp->if_softc; 1916 struct mbuf *m_head = NULL; 1917 uint32_t prodidx = 0; 1918 int need_trans; 1919 1920 prodidx = CSR_READ_4(sc, TI_MB_SENDPROD_IDX); 1921 1922 need_trans = 0; 1923 while(sc->ti_cdata.ti_tx_chain[prodidx] == NULL) { 1924 m_head = ifq_poll(&ifp->if_snd); 1925 if (m_head == NULL) 1926 break; 1927 1928 /* 1929 * XXX 1930 * safety overkill. If this is a fragmented packet chain 1931 * with delayed TCP/UDP checksums, then only encapsulate 1932 * it if we have enough descriptors to handle the entire 1933 * chain at once. 1934 * (paranoia -- may not actually be needed) 1935 */ 1936 if (m_head->m_flags & M_FIRSTFRAG && 1937 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) { 1938 if ((TI_TX_RING_CNT - sc->ti_txcnt) < 1939 m_head->m_pkthdr.csum_data + 16) { 1940 ifp->if_flags |= IFF_OACTIVE; 1941 break; 1942 } 1943 } 1944 1945 /* 1946 * Pack the data into the transmit ring. If we 1947 * don't have room, set the OACTIVE flag and wait 1948 * for the NIC to drain the ring. 1949 */ 1950 if (ti_encap(sc, m_head, &prodidx)) { 1951 ifp->if_flags |= IFF_OACTIVE; 1952 break; 1953 } 1954 ifq_dequeue(&ifp->if_snd, m_head); 1955 need_trans = 1; 1956 1957 BPF_MTAP(ifp, m_head); 1958 } 1959 1960 if (!need_trans) 1961 return; 1962 1963 /* Transmit */ 1964 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, prodidx); 1965 1966 /* 1967 * Set a timeout in case the chip goes out to lunch. 1968 */ 1969 ifp->if_timer = 5; 1970 } 1971 1972 static void 1973 ti_init(void *xsc) 1974 { 1975 struct ti_softc *sc = xsc; 1976 1977 /* Cancel pending I/O and flush buffers. */ 1978 ti_stop(sc); 1979 1980 /* Init the gen info block, ring control blocks and firmware. */ 1981 if (ti_gibinit(sc)) { 1982 if_printf(&sc->arpcom.ac_if, "initialization failure\n"); 1983 return; 1984 } 1985 } 1986 1987 static void 1988 ti_init2(struct ti_softc *sc) 1989 { 1990 struct ifnet *ifp = &sc->arpcom.ac_if; 1991 struct ti_cmd_desc cmd; 1992 uint16_t *m; 1993 struct ifmedia *ifm; 1994 int tmp; 1995 1996 /* Specify MTU and interface index. */ 1997 CSR_WRITE_4(sc, TI_GCR_IFINDEX, ifp->if_dunit); 1998 CSR_WRITE_4(sc, TI_GCR_IFMTU, ifp->if_mtu + 1999 ETHER_HDR_LEN + ETHER_CRC_LEN); 2000 TI_DO_CMD(TI_CMD_UPDATE_GENCOM, 0, 0); 2001 2002 /* Load our MAC address. */ 2003 m = (uint16_t *)&sc->arpcom.ac_enaddr[0]; 2004 CSR_WRITE_4(sc, TI_GCR_PAR0, htons(m[0])); 2005 CSR_WRITE_4(sc, TI_GCR_PAR1, (htons(m[1]) << 16) | htons(m[2])); 2006 TI_DO_CMD(TI_CMD_SET_MAC_ADDR, 0, 0); 2007 2008 /* Enable or disable promiscuous mode as needed. */ 2009 if (ifp->if_flags & IFF_PROMISC) 2010 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_ENB, 0); 2011 else 2012 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_DIS, 0); 2013 2014 /* Program multicast filter. */ 2015 ti_setmulti(sc); 2016 2017 /* 2018 * If this is a Tigon 1, we should tell the 2019 * firmware to use software packet filtering. 2020 */ 2021 if (sc->ti_hwrev == TI_HWREV_TIGON) 2022 TI_DO_CMD(TI_CMD_FDR_FILTERING, TI_CMD_CODE_FILT_ENB, 0); 2023 2024 /* Init RX ring. */ 2025 ti_init_rx_ring_std(sc); 2026 2027 /* Init jumbo RX ring. */ 2028 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 2029 ti_init_rx_ring_jumbo(sc); 2030 2031 /* 2032 * If this is a Tigon 2, we can also configure the 2033 * mini ring. 2034 */ 2035 if (sc->ti_hwrev == TI_HWREV_TIGON_II) 2036 ti_init_rx_ring_mini(sc); 2037 2038 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 0); 2039 sc->ti_rx_saved_considx = 0; 2040 2041 /* Init TX ring. */ 2042 ti_init_tx_ring(sc); 2043 2044 /* Tell firmware we're alive. */ 2045 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_UP, 0); 2046 2047 /* Enable host interrupts. */ 2048 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 2049 2050 ifp->if_flags |= IFF_RUNNING; 2051 ifp->if_flags &= ~IFF_OACTIVE; 2052 2053 /* 2054 * Make sure to set media properly. We have to do this 2055 * here since we have to issue commands in order to set 2056 * the link negotiation and we can't issue commands until 2057 * the firmware is running. 2058 */ 2059 ifm = &sc->ifmedia; 2060 tmp = ifm->ifm_media; 2061 ifm->ifm_media = ifm->ifm_cur->ifm_media; 2062 ti_ifmedia_upd(ifp); 2063 ifm->ifm_media = tmp; 2064 } 2065 2066 /* 2067 * Set media options. 2068 */ 2069 static int 2070 ti_ifmedia_upd(struct ifnet *ifp) 2071 { 2072 struct ti_softc *sc = ifp->if_softc; 2073 struct ifmedia *ifm = &sc->ifmedia; 2074 struct ti_cmd_desc cmd; 2075 2076 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 2077 return(EINVAL); 2078 2079 switch(IFM_SUBTYPE(ifm->ifm_media)) { 2080 case IFM_AUTO: 2081 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF | TI_GLNK_1000MB | 2082 TI_GLNK_FULL_DUPLEX | TI_GLNK_RX_FLOWCTL_Y | 2083 TI_GLNK_AUTONEGENB | TI_GLNK_ENB); 2084 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_100MB | TI_LNK_10MB | 2085 TI_LNK_FULL_DUPLEX | TI_LNK_HALF_DUPLEX | 2086 TI_LNK_AUTONEGENB | TI_LNK_ENB); 2087 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 2088 TI_CMD_CODE_NEGOTIATE_BOTH, 0); 2089 break; 2090 case IFM_1000_SX: 2091 case IFM_1000_T: 2092 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB | 2093 TI_GLNK_RX_FLOWCTL_Y | TI_GLNK_ENB); 2094 CSR_WRITE_4(sc, TI_GCR_LINK, 0); 2095 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 2096 TI_SETBIT(sc, TI_GCR_GLINK, TI_GLNK_FULL_DUPLEX); 2097 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 2098 TI_CMD_CODE_NEGOTIATE_GIGABIT, 0); 2099 break; 2100 case IFM_100_FX: 2101 case IFM_10_FL: 2102 case IFM_100_TX: 2103 case IFM_10_T: 2104 CSR_WRITE_4(sc, TI_GCR_GLINK, 0); 2105 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_ENB | TI_LNK_PREF); 2106 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_100_FX || 2107 IFM_SUBTYPE(ifm->ifm_media) == IFM_100_TX) 2108 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_100MB); 2109 else 2110 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_10MB); 2111 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 2112 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_FULL_DUPLEX); 2113 else 2114 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_HALF_DUPLEX); 2115 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 2116 TI_CMD_CODE_NEGOTIATE_10_100, 0); 2117 break; 2118 } 2119 2120 return(0); 2121 } 2122 2123 /* 2124 * Report current media status. 2125 */ 2126 static void 2127 ti_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 2128 { 2129 struct ti_softc *sc = ifp->if_softc; 2130 uint32_t media = 0; 2131 2132 ifmr->ifm_status = IFM_AVALID; 2133 ifmr->ifm_active = IFM_ETHER; 2134 2135 if (sc->ti_linkstat == TI_EV_CODE_LINK_DOWN) 2136 return; 2137 2138 ifmr->ifm_status |= IFM_ACTIVE; 2139 2140 if (sc->ti_linkstat == TI_EV_CODE_GIG_LINK_UP) { 2141 media = CSR_READ_4(sc, TI_GCR_GLINK_STAT); 2142 if (sc->ti_copper) 2143 ifmr->ifm_active |= IFM_1000_T; 2144 else 2145 ifmr->ifm_active |= IFM_1000_SX; 2146 if (media & TI_GLNK_FULL_DUPLEX) 2147 ifmr->ifm_active |= IFM_FDX; 2148 else 2149 ifmr->ifm_active |= IFM_HDX; 2150 } else if (sc->ti_linkstat == TI_EV_CODE_LINK_UP) { 2151 media = CSR_READ_4(sc, TI_GCR_LINK_STAT); 2152 if (sc->ti_copper) { 2153 if (media & TI_LNK_100MB) 2154 ifmr->ifm_active |= IFM_100_TX; 2155 if (media & TI_LNK_10MB) 2156 ifmr->ifm_active |= IFM_10_T; 2157 } else { 2158 if (media & TI_LNK_100MB) 2159 ifmr->ifm_active |= IFM_100_FX; 2160 if (media & TI_LNK_10MB) 2161 ifmr->ifm_active |= IFM_10_FL; 2162 } 2163 if (media & TI_LNK_FULL_DUPLEX) 2164 ifmr->ifm_active |= IFM_FDX; 2165 if (media & TI_LNK_HALF_DUPLEX) 2166 ifmr->ifm_active |= IFM_HDX; 2167 } 2168 } 2169 2170 static int 2171 ti_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr) 2172 { 2173 struct ti_softc *sc = ifp->if_softc; 2174 struct ifreq *ifr = (struct ifreq *) data; 2175 struct ti_cmd_desc cmd; 2176 int error = 0, mask; 2177 2178 switch(command) { 2179 case SIOCSIFMTU: 2180 if (ifr->ifr_mtu > TI_JUMBO_MTU) 2181 error = EINVAL; 2182 else { 2183 ifp->if_mtu = ifr->ifr_mtu; 2184 ti_init(sc); 2185 } 2186 break; 2187 case SIOCSIFFLAGS: 2188 if (ifp->if_flags & IFF_UP) { 2189 /* 2190 * If only the state of the PROMISC flag changed, 2191 * then just use the 'set promisc mode' command 2192 * instead of reinitializing the entire NIC. Doing 2193 * a full re-init means reloading the firmware and 2194 * waiting for it to start up, which may take a 2195 * second or two. 2196 */ 2197 if (ifp->if_flags & IFF_RUNNING && 2198 ifp->if_flags & IFF_PROMISC && 2199 !(sc->ti_if_flags & IFF_PROMISC)) { 2200 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, 2201 TI_CMD_CODE_PROMISC_ENB, 0); 2202 } else if (ifp->if_flags & IFF_RUNNING && 2203 !(ifp->if_flags & IFF_PROMISC) && 2204 sc->ti_if_flags & IFF_PROMISC) { 2205 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, 2206 TI_CMD_CODE_PROMISC_DIS, 0); 2207 } else 2208 ti_init(sc); 2209 } else if (ifp->if_flags & IFF_RUNNING) { 2210 ti_stop(sc); 2211 } 2212 sc->ti_if_flags = ifp->if_flags; 2213 error = 0; 2214 break; 2215 case SIOCADDMULTI: 2216 case SIOCDELMULTI: 2217 if (ifp->if_flags & IFF_RUNNING) { 2218 ti_setmulti(sc); 2219 error = 0; 2220 } 2221 break; 2222 case SIOCSIFMEDIA: 2223 case SIOCGIFMEDIA: 2224 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command); 2225 break; 2226 case SIOCSIFCAP: 2227 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 2228 if (mask & IFCAP_HWCSUM) { 2229 if (IFCAP_HWCSUM & ifp->if_capenable) 2230 ifp->if_capenable &= ~IFCAP_HWCSUM; 2231 else 2232 ifp->if_capenable |= IFCAP_HWCSUM; 2233 if (ifp->if_flags & IFF_RUNNING) 2234 ti_init(sc); 2235 } 2236 error = 0; 2237 break; 2238 default: 2239 error = ether_ioctl(ifp, command, data); 2240 break; 2241 } 2242 return(error); 2243 } 2244 2245 static void 2246 ti_watchdog(struct ifnet *ifp) 2247 { 2248 struct ti_softc *sc = ifp->if_softc; 2249 2250 if_printf(ifp, "watchdog timeout -- resetting\n"); 2251 ti_stop(sc); 2252 ti_init(sc); 2253 2254 ifp->if_oerrors++; 2255 2256 if (!ifq_is_empty(&ifp->if_snd)) 2257 ifp->if_start(ifp); 2258 } 2259 2260 /* 2261 * Stop the adapter and free any mbufs allocated to the 2262 * RX and TX lists. 2263 */ 2264 static void 2265 ti_stop(struct ti_softc *sc) 2266 { 2267 struct ifnet *ifp = &sc->arpcom.ac_if; 2268 struct ti_cmd_desc cmd; 2269 2270 /* Disable host interrupts. */ 2271 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 2272 /* 2273 * Tell firmware we're shutting down. 2274 */ 2275 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_DOWN, 0); 2276 2277 /* Halt and reinitialize. */ 2278 ti_chipinit(sc); 2279 ti_mem(sc, 0x2000, 0x100000 - 0x2000, NULL); 2280 ti_chipinit(sc); 2281 2282 /* Free the RX lists. */ 2283 ti_free_rx_ring_std(sc); 2284 2285 /* Free jumbo RX list. */ 2286 ti_free_rx_ring_jumbo(sc); 2287 2288 /* Free mini RX list. */ 2289 ti_free_rx_ring_mini(sc); 2290 2291 /* Free TX buffers. */ 2292 ti_free_tx_ring(sc); 2293 2294 sc->ti_ev_prodidx.ti_idx = 0; 2295 sc->ti_return_prodidx.ti_idx = 0; 2296 sc->ti_tx_considx.ti_idx = 0; 2297 sc->ti_tx_saved_considx = TI_TXCONS_UNSET; 2298 2299 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2300 } 2301 2302 /* 2303 * Stop all chip I/O so that the kernel's probe routines don't 2304 * get confused by errant DMAs when rebooting. 2305 */ 2306 static void 2307 ti_shutdown(device_t dev) 2308 { 2309 struct ti_softc *sc = device_get_softc(dev); 2310 2311 ti_chipinit(sc); 2312 } 2313