1 /* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: src/sys/pci/if_ti.c,v 1.25.2.14 2002/02/15 04:20:20 silby Exp $ 33 * $DragonFly: src/sys/dev/netif/ti/if_ti.c,v 1.14 2004/07/29 08:46:23 dillon Exp $ 34 * 35 * $FreeBSD: src/sys/pci/if_ti.c,v 1.25.2.14 2002/02/15 04:20:20 silby Exp $ 36 */ 37 38 /* 39 * Alteon Networks Tigon PCI gigabit ethernet driver for FreeBSD. 40 * Manuals, sample driver and firmware source kits are available 41 * from http://www.alteon.com/support/openkits. 42 * 43 * Written by Bill Paul <wpaul@ctr.columbia.edu> 44 * Electrical Engineering Department 45 * Columbia University, New York City 46 */ 47 48 /* 49 * The Alteon Networks Tigon chip contains an embedded R4000 CPU, 50 * gigabit MAC, dual DMA channels and a PCI interface unit. NICs 51 * using the Tigon may have anywhere from 512K to 2MB of SRAM. The 52 * Tigon supports hardware IP, TCP and UCP checksumming, multicast 53 * filtering and jumbo (9014 byte) frames. The hardware is largely 54 * controlled by firmware, which must be loaded into the NIC during 55 * initialization. 56 * 57 * The Tigon 2 contains 2 R4000 CPUs and requires a newer firmware 58 * revision, which supports new features such as extended commands, 59 * extended jumbo receive ring desciptors and a mini receive ring. 60 * 61 * Alteon Networks is to be commended for releasing such a vast amount 62 * of development material for the Tigon NIC without requiring an NDA 63 * (although they really should have done it a long time ago). With 64 * any luck, the other vendors will finally wise up and follow Alteon's 65 * stellar example. 66 * 67 * The firmware for the Tigon 1 and 2 NICs is compiled directly into 68 * this driver by #including it as a C header file. This bloats the 69 * driver somewhat, but it's the easiest method considering that the 70 * driver code and firmware code need to be kept in sync. The source 71 * for the firmware is not provided with the FreeBSD distribution since 72 * compiling it requires a GNU toolchain targeted for mips-sgi-irix5.3. 73 * 74 * The following people deserve special thanks: 75 * - Terry Murphy of 3Com, for providing a 3c985 Tigon 1 board 76 * for testing 77 * - Raymond Lee of Netgear, for providing a pair of Netgear 78 * GA620 Tigon 2 boards for testing 79 * - Ulf Zimmermann, for bringing the GA260 to my attention and 80 * convincing me to write this driver. 81 * - Andrew Gallatin for providing FreeBSD/Alpha support. 82 */ 83 84 #include <sys/param.h> 85 #include <sys/systm.h> 86 #include <sys/sockio.h> 87 #include <sys/mbuf.h> 88 #include <sys/malloc.h> 89 #include <sys/kernel.h> 90 #include <sys/socket.h> 91 #include <sys/queue.h> 92 93 #include <net/if.h> 94 #include <net/if_arp.h> 95 #include <net/ethernet.h> 96 #include <net/if_dl.h> 97 #include <net/if_media.h> 98 #include <net/if_types.h> 99 #include <net/vlan/if_vlan_var.h> 100 101 #include <net/bpf.h> 102 103 #include <netinet/in_systm.h> 104 #include <netinet/in.h> 105 #include <netinet/ip.h> 106 107 #include <vm/vm.h> /* for vtophys */ 108 #include <vm/pmap.h> /* for vtophys */ 109 #include <machine/clock.h> /* for DELAY */ 110 #include <machine/bus_memio.h> 111 #include <machine/bus.h> 112 #include <machine/resource.h> 113 #include <sys/bus.h> 114 #include <sys/rman.h> 115 116 #include <bus/pci/pcireg.h> 117 #include <bus/pci/pcivar.h> 118 119 #include "if_tireg.h" 120 #include "ti_fw.h" 121 #include "ti_fw2.h" 122 123 /* 124 * Temporarily disable the checksum offload support for now. 125 * Tests with ftp.freesoftware.com show that after about 12 hours, 126 * the firmware will begin calculating completely bogus TX checksums 127 * and refuse to stop until the interface is reset. Unfortunately, 128 * there isn't enough time to fully debug this before the 4.1 129 * release, so this will need to stay off for now. 130 */ 131 #ifdef notdef 132 #define TI_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_IP_FRAGS) 133 #else 134 #define TI_CSUM_FEATURES 0 135 #endif 136 137 /* 138 * Various supported device vendors/types and their names. 139 */ 140 141 static struct ti_type ti_devs[] = { 142 { ALT_VENDORID, ALT_DEVICEID_ACENIC, 143 "Alteon AceNIC 1000baseSX Gigabit Ethernet" }, 144 { ALT_VENDORID, ALT_DEVICEID_ACENIC_COPPER, 145 "Alteon AceNIC 1000baseT Gigabit Ethernet" }, 146 { TC_VENDORID, TC_DEVICEID_3C985, 147 "3Com 3c985-SX Gigabit Ethernet" }, 148 { NG_VENDORID, NG_DEVICEID_GA620, 149 "Netgear GA620 1000baseSX Gigabit Ethernet" }, 150 { NG_VENDORID, NG_DEVICEID_GA620T, 151 "Netgear GA620 1000baseT Gigabit Ethernet" }, 152 { SGI_VENDORID, SGI_DEVICEID_TIGON, 153 "Silicon Graphics Gigabit Ethernet" }, 154 { DEC_VENDORID, DEC_DEVICEID_FARALLON_PN9000SX, 155 "Farallon PN9000SX Gigabit Ethernet" }, 156 { 0, 0, NULL } 157 }; 158 159 static int ti_probe (device_t); 160 static int ti_attach (device_t); 161 static int ti_detach (device_t); 162 static void ti_txeof (struct ti_softc *); 163 static void ti_rxeof (struct ti_softc *); 164 165 static void ti_stats_update (struct ti_softc *); 166 static int ti_encap (struct ti_softc *, struct mbuf *, 167 u_int32_t *); 168 169 static void ti_intr (void *); 170 static void ti_start (struct ifnet *); 171 static int ti_ioctl (struct ifnet *, u_long, caddr_t, 172 struct ucred *); 173 static void ti_init (void *); 174 static void ti_init2 (struct ti_softc *); 175 static void ti_stop (struct ti_softc *); 176 static void ti_watchdog (struct ifnet *); 177 static void ti_shutdown (device_t); 178 static int ti_ifmedia_upd (struct ifnet *); 179 static void ti_ifmedia_sts (struct ifnet *, struct ifmediareq *); 180 181 static u_int32_t ti_eeprom_putbyte (struct ti_softc *, int); 182 static u_int8_t ti_eeprom_getbyte (struct ti_softc *, 183 int, u_int8_t *); 184 static int ti_read_eeprom (struct ti_softc *, caddr_t, int, int); 185 186 static void ti_add_mcast (struct ti_softc *, struct ether_addr *); 187 static void ti_del_mcast (struct ti_softc *, struct ether_addr *); 188 static void ti_setmulti (struct ti_softc *); 189 190 static void ti_mem (struct ti_softc *, u_int32_t, 191 u_int32_t, caddr_t); 192 static void ti_loadfw (struct ti_softc *); 193 static void ti_cmd (struct ti_softc *, struct ti_cmd_desc *); 194 static void ti_cmd_ext (struct ti_softc *, struct ti_cmd_desc *, 195 caddr_t, int); 196 static void ti_handle_events (struct ti_softc *); 197 static int ti_alloc_jumbo_mem (struct ti_softc *); 198 static void *ti_jalloc (struct ti_softc *); 199 static void ti_jfree (caddr_t, u_int); 200 static void ti_jref (caddr_t, u_int); 201 static int ti_newbuf_std (struct ti_softc *, int, struct mbuf *); 202 static int ti_newbuf_mini (struct ti_softc *, int, struct mbuf *); 203 static int ti_newbuf_jumbo (struct ti_softc *, int, struct mbuf *); 204 static int ti_init_rx_ring_std (struct ti_softc *); 205 static void ti_free_rx_ring_std (struct ti_softc *); 206 static int ti_init_rx_ring_jumbo (struct ti_softc *); 207 static void ti_free_rx_ring_jumbo (struct ti_softc *); 208 static int ti_init_rx_ring_mini (struct ti_softc *); 209 static void ti_free_rx_ring_mini (struct ti_softc *); 210 static void ti_free_tx_ring (struct ti_softc *); 211 static int ti_init_tx_ring (struct ti_softc *); 212 213 static int ti_64bitslot_war (struct ti_softc *); 214 static int ti_chipinit (struct ti_softc *); 215 static int ti_gibinit (struct ti_softc *); 216 217 static device_method_t ti_methods[] = { 218 /* Device interface */ 219 DEVMETHOD(device_probe, ti_probe), 220 DEVMETHOD(device_attach, ti_attach), 221 DEVMETHOD(device_detach, ti_detach), 222 DEVMETHOD(device_shutdown, ti_shutdown), 223 { 0, 0 } 224 }; 225 226 static driver_t ti_driver = { 227 "ti", 228 ti_methods, 229 sizeof(struct ti_softc) 230 }; 231 232 static devclass_t ti_devclass; 233 234 DECLARE_DUMMY_MODULE(if_ti); 235 DRIVER_MODULE(if_ti, pci, ti_driver, ti_devclass, 0, 0); 236 237 /* 238 * Send an instruction or address to the EEPROM, check for ACK. 239 */ 240 static u_int32_t ti_eeprom_putbyte(sc, byte) 241 struct ti_softc *sc; 242 int byte; 243 { 244 int i, ack = 0; 245 246 /* 247 * Make sure we're in TX mode. 248 */ 249 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 250 251 /* 252 * Feed in each bit and stobe the clock. 253 */ 254 for (i = 0x80; i; i >>= 1) { 255 if (byte & i) { 256 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); 257 } else { 258 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); 259 } 260 DELAY(1); 261 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 262 DELAY(1); 263 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 264 } 265 266 /* 267 * Turn off TX mode. 268 */ 269 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 270 271 /* 272 * Check for ack. 273 */ 274 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 275 ack = CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN; 276 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 277 278 return(ack); 279 } 280 281 /* 282 * Read a byte of data stored in the EEPROM at address 'addr.' 283 * We have to send two address bytes since the EEPROM can hold 284 * more than 256 bytes of data. 285 */ 286 static u_int8_t ti_eeprom_getbyte(sc, addr, dest) 287 struct ti_softc *sc; 288 int addr; 289 u_int8_t *dest; 290 { 291 int i; 292 u_int8_t byte = 0; 293 294 EEPROM_START; 295 296 /* 297 * Send write control code to EEPROM. 298 */ 299 if (ti_eeprom_putbyte(sc, EEPROM_CTL_WRITE)) { 300 printf("ti%d: failed to send write command, status: %x\n", 301 sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 302 return(1); 303 } 304 305 /* 306 * Send first byte of address of byte we want to read. 307 */ 308 if (ti_eeprom_putbyte(sc, (addr >> 8) & 0xFF)) { 309 printf("ti%d: failed to send address, status: %x\n", 310 sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 311 return(1); 312 } 313 /* 314 * Send second byte address of byte we want to read. 315 */ 316 if (ti_eeprom_putbyte(sc, addr & 0xFF)) { 317 printf("ti%d: failed to send address, status: %x\n", 318 sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 319 return(1); 320 } 321 322 EEPROM_STOP; 323 EEPROM_START; 324 /* 325 * Send read control code to EEPROM. 326 */ 327 if (ti_eeprom_putbyte(sc, EEPROM_CTL_READ)) { 328 printf("ti%d: failed to send read command, status: %x\n", 329 sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 330 return(1); 331 } 332 333 /* 334 * Start reading bits from EEPROM. 335 */ 336 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 337 for (i = 0x80; i; i >>= 1) { 338 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 339 DELAY(1); 340 if (CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN) 341 byte |= i; 342 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 343 DELAY(1); 344 } 345 346 EEPROM_STOP; 347 348 /* 349 * No ACK generated for read, so just return byte. 350 */ 351 352 *dest = byte; 353 354 return(0); 355 } 356 357 /* 358 * Read a sequence of bytes from the EEPROM. 359 */ 360 static int ti_read_eeprom(sc, dest, off, cnt) 361 struct ti_softc *sc; 362 caddr_t dest; 363 int off; 364 int cnt; 365 { 366 int err = 0, i; 367 u_int8_t byte = 0; 368 369 for (i = 0; i < cnt; i++) { 370 err = ti_eeprom_getbyte(sc, off + i, &byte); 371 if (err) 372 break; 373 *(dest + i) = byte; 374 } 375 376 return(err ? 1 : 0); 377 } 378 379 /* 380 * NIC memory access function. Can be used to either clear a section 381 * of NIC local memory or (if buf is non-NULL) copy data into it. 382 */ 383 static void ti_mem(sc, addr, len, buf) 384 struct ti_softc *sc; 385 u_int32_t addr, len; 386 caddr_t buf; 387 { 388 int segptr, segsize, cnt; 389 caddr_t ti_winbase, ptr; 390 391 segptr = addr; 392 cnt = len; 393 ti_winbase = (caddr_t)(sc->ti_vhandle + TI_WINDOW); 394 ptr = buf; 395 396 while(cnt) { 397 if (cnt < TI_WINLEN) 398 segsize = cnt; 399 else 400 segsize = TI_WINLEN - (segptr % TI_WINLEN); 401 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1))); 402 if (buf == NULL) 403 bzero((char *)ti_winbase + (segptr & 404 (TI_WINLEN - 1)), segsize); 405 else { 406 bcopy((char *)ptr, (char *)ti_winbase + 407 (segptr & (TI_WINLEN - 1)), segsize); 408 ptr += segsize; 409 } 410 segptr += segsize; 411 cnt -= segsize; 412 } 413 414 return; 415 } 416 417 /* 418 * Load firmware image into the NIC. Check that the firmware revision 419 * is acceptable and see if we want the firmware for the Tigon 1 or 420 * Tigon 2. 421 */ 422 static void ti_loadfw(sc) 423 struct ti_softc *sc; 424 { 425 switch(sc->ti_hwrev) { 426 case TI_HWREV_TIGON: 427 if (tigonFwReleaseMajor != TI_FIRMWARE_MAJOR || 428 tigonFwReleaseMinor != TI_FIRMWARE_MINOR || 429 tigonFwReleaseFix != TI_FIRMWARE_FIX) { 430 printf("ti%d: firmware revision mismatch; want " 431 "%d.%d.%d, got %d.%d.%d\n", sc->ti_unit, 432 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR, 433 TI_FIRMWARE_FIX, tigonFwReleaseMajor, 434 tigonFwReleaseMinor, tigonFwReleaseFix); 435 return; 436 } 437 ti_mem(sc, tigonFwTextAddr, tigonFwTextLen, 438 (caddr_t)tigonFwText); 439 ti_mem(sc, tigonFwDataAddr, tigonFwDataLen, 440 (caddr_t)tigonFwData); 441 ti_mem(sc, tigonFwRodataAddr, tigonFwRodataLen, 442 (caddr_t)tigonFwRodata); 443 ti_mem(sc, tigonFwBssAddr, tigonFwBssLen, NULL); 444 ti_mem(sc, tigonFwSbssAddr, tigonFwSbssLen, NULL); 445 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigonFwStartAddr); 446 break; 447 case TI_HWREV_TIGON_II: 448 if (tigon2FwReleaseMajor != TI_FIRMWARE_MAJOR || 449 tigon2FwReleaseMinor != TI_FIRMWARE_MINOR || 450 tigon2FwReleaseFix != TI_FIRMWARE_FIX) { 451 printf("ti%d: firmware revision mismatch; want " 452 "%d.%d.%d, got %d.%d.%d\n", sc->ti_unit, 453 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR, 454 TI_FIRMWARE_FIX, tigon2FwReleaseMajor, 455 tigon2FwReleaseMinor, tigon2FwReleaseFix); 456 return; 457 } 458 ti_mem(sc, tigon2FwTextAddr, tigon2FwTextLen, 459 (caddr_t)tigon2FwText); 460 ti_mem(sc, tigon2FwDataAddr, tigon2FwDataLen, 461 (caddr_t)tigon2FwData); 462 ti_mem(sc, tigon2FwRodataAddr, tigon2FwRodataLen, 463 (caddr_t)tigon2FwRodata); 464 ti_mem(sc, tigon2FwBssAddr, tigon2FwBssLen, NULL); 465 ti_mem(sc, tigon2FwSbssAddr, tigon2FwSbssLen, NULL); 466 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigon2FwStartAddr); 467 break; 468 default: 469 printf("ti%d: can't load firmware: unknown hardware rev\n", 470 sc->ti_unit); 471 break; 472 } 473 474 return; 475 } 476 477 /* 478 * Send the NIC a command via the command ring. 479 */ 480 static void ti_cmd(sc, cmd) 481 struct ti_softc *sc; 482 struct ti_cmd_desc *cmd; 483 { 484 u_int32_t index; 485 486 if (sc->ti_rdata->ti_cmd_ring == NULL) 487 return; 488 489 index = sc->ti_cmd_saved_prodidx; 490 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(u_int32_t *)(cmd)); 491 TI_INC(index, TI_CMD_RING_CNT); 492 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index); 493 sc->ti_cmd_saved_prodidx = index; 494 495 return; 496 } 497 498 /* 499 * Send the NIC an extended command. The 'len' parameter specifies the 500 * number of command slots to include after the initial command. 501 */ 502 static void ti_cmd_ext(sc, cmd, arg, len) 503 struct ti_softc *sc; 504 struct ti_cmd_desc *cmd; 505 caddr_t arg; 506 int len; 507 { 508 u_int32_t index; 509 int i; 510 511 if (sc->ti_rdata->ti_cmd_ring == NULL) 512 return; 513 514 index = sc->ti_cmd_saved_prodidx; 515 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(u_int32_t *)(cmd)); 516 TI_INC(index, TI_CMD_RING_CNT); 517 for (i = 0; i < len; i++) { 518 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), 519 *(u_int32_t *)(&arg[i * 4])); 520 TI_INC(index, TI_CMD_RING_CNT); 521 } 522 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index); 523 sc->ti_cmd_saved_prodidx = index; 524 525 return; 526 } 527 528 /* 529 * Handle events that have triggered interrupts. 530 */ 531 static void ti_handle_events(sc) 532 struct ti_softc *sc; 533 { 534 struct ti_event_desc *e; 535 536 if (sc->ti_rdata->ti_event_ring == NULL) 537 return; 538 539 while (sc->ti_ev_saved_considx != sc->ti_ev_prodidx.ti_idx) { 540 e = &sc->ti_rdata->ti_event_ring[sc->ti_ev_saved_considx]; 541 switch(e->ti_event) { 542 case TI_EV_LINKSTAT_CHANGED: 543 sc->ti_linkstat = e->ti_code; 544 if (e->ti_code == TI_EV_CODE_LINK_UP) 545 printf("ti%d: 10/100 link up\n", sc->ti_unit); 546 else if (e->ti_code == TI_EV_CODE_GIG_LINK_UP) 547 printf("ti%d: gigabit link up\n", sc->ti_unit); 548 else if (e->ti_code == TI_EV_CODE_LINK_DOWN) 549 printf("ti%d: link down\n", sc->ti_unit); 550 break; 551 case TI_EV_ERROR: 552 if (e->ti_code == TI_EV_CODE_ERR_INVAL_CMD) 553 printf("ti%d: invalid command\n", sc->ti_unit); 554 else if (e->ti_code == TI_EV_CODE_ERR_UNIMP_CMD) 555 printf("ti%d: unknown command\n", sc->ti_unit); 556 else if (e->ti_code == TI_EV_CODE_ERR_BADCFG) 557 printf("ti%d: bad config data\n", sc->ti_unit); 558 break; 559 case TI_EV_FIRMWARE_UP: 560 ti_init2(sc); 561 break; 562 case TI_EV_STATS_UPDATED: 563 ti_stats_update(sc); 564 break; 565 case TI_EV_RESET_JUMBO_RING: 566 case TI_EV_MCAST_UPDATED: 567 /* Who cares. */ 568 break; 569 default: 570 printf("ti%d: unknown event: %d\n", 571 sc->ti_unit, e->ti_event); 572 break; 573 } 574 /* Advance the consumer index. */ 575 TI_INC(sc->ti_ev_saved_considx, TI_EVENT_RING_CNT); 576 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, sc->ti_ev_saved_considx); 577 } 578 579 return; 580 } 581 582 /* 583 * Memory management for the jumbo receive ring is a pain in the 584 * butt. We need to allocate at least 9018 bytes of space per frame, 585 * _and_ it has to be contiguous (unless you use the extended 586 * jumbo descriptor format). Using malloc() all the time won't 587 * work: malloc() allocates memory in powers of two, which means we 588 * would end up wasting a considerable amount of space by allocating 589 * 9K chunks. We don't have a jumbo mbuf cluster pool. Thus, we have 590 * to do our own memory management. 591 * 592 * The driver needs to allocate a contiguous chunk of memory at boot 593 * time. We then chop this up ourselves into 9K pieces and use them 594 * as external mbuf storage. 595 * 596 * One issue here is how much memory to allocate. The jumbo ring has 597 * 256 slots in it, but at 9K per slot than can consume over 2MB of 598 * RAM. This is a bit much, especially considering we also need 599 * RAM for the standard ring and mini ring (on the Tigon 2). To 600 * save space, we only actually allocate enough memory for 64 slots 601 * by default, which works out to between 500 and 600K. This can 602 * be tuned by changing a #define in if_tireg.h. 603 */ 604 605 static int ti_alloc_jumbo_mem(sc) 606 struct ti_softc *sc; 607 { 608 caddr_t ptr; 609 int i; 610 struct ti_jpool_entry *entry; 611 612 /* Grab a big chunk o' storage. */ 613 sc->ti_cdata.ti_jumbo_buf = contigmalloc(TI_JMEM, M_DEVBUF, 614 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 615 616 if (sc->ti_cdata.ti_jumbo_buf == NULL) { 617 printf("ti%d: no memory for jumbo buffers!\n", sc->ti_unit); 618 return(ENOBUFS); 619 } 620 621 SLIST_INIT(&sc->ti_jfree_listhead); 622 SLIST_INIT(&sc->ti_jinuse_listhead); 623 624 /* 625 * Now divide it up into 9K pieces and save the addresses 626 * in an array. Note that we play an evil trick here by using 627 * the first few bytes in the buffer to hold the the address 628 * of the softc structure for this interface. This is because 629 * ti_jfree() needs it, but it is called by the mbuf management 630 * code which will not pass it to us explicitly. 631 */ 632 ptr = sc->ti_cdata.ti_jumbo_buf; 633 for (i = 0; i < TI_JSLOTS; i++) { 634 u_int64_t **aptr; 635 aptr = (u_int64_t **)ptr; 636 aptr[0] = (u_int64_t *)sc; 637 ptr += sizeof(u_int64_t); 638 sc->ti_cdata.ti_jslots[i].ti_buf = ptr; 639 sc->ti_cdata.ti_jslots[i].ti_inuse = 0; 640 ptr += (TI_JLEN - sizeof(u_int64_t)); 641 entry = malloc(sizeof(struct ti_jpool_entry), 642 M_DEVBUF, M_WAITOK); 643 if (entry == NULL) { 644 contigfree(sc->ti_cdata.ti_jumbo_buf, TI_JMEM, 645 M_DEVBUF); 646 sc->ti_cdata.ti_jumbo_buf = NULL; 647 printf("ti%d: no memory for jumbo " 648 "buffer queue!\n", sc->ti_unit); 649 return(ENOBUFS); 650 } 651 entry->slot = i; 652 SLIST_INSERT_HEAD(&sc->ti_jfree_listhead, entry, jpool_entries); 653 } 654 655 return(0); 656 } 657 658 /* 659 * Allocate a jumbo buffer. 660 */ 661 static void *ti_jalloc(sc) 662 struct ti_softc *sc; 663 { 664 struct ti_jpool_entry *entry; 665 666 entry = SLIST_FIRST(&sc->ti_jfree_listhead); 667 668 if (entry == NULL) { 669 printf("ti%d: no free jumbo buffers\n", sc->ti_unit); 670 return(NULL); 671 } 672 673 SLIST_REMOVE_HEAD(&sc->ti_jfree_listhead, jpool_entries); 674 SLIST_INSERT_HEAD(&sc->ti_jinuse_listhead, entry, jpool_entries); 675 sc->ti_cdata.ti_jslots[entry->slot].ti_inuse = 1; 676 return(sc->ti_cdata.ti_jslots[entry->slot].ti_buf); 677 } 678 679 /* 680 * Adjust usage count on a jumbo buffer. In general this doesn't 681 * get used much because our jumbo buffers don't get passed around 682 * too much, but it's implemented for correctness. 683 */ 684 static void ti_jref(buf, size) 685 caddr_t buf; 686 u_int size; 687 { 688 struct ti_softc *sc; 689 u_int64_t **aptr; 690 int i; 691 692 /* Extract the softc struct pointer. */ 693 aptr = (u_int64_t **)(buf - sizeof(u_int64_t)); 694 sc = (struct ti_softc *)(aptr[0]); 695 696 if (sc == NULL) 697 panic("ti_jref: can't find softc pointer!"); 698 699 if (size != TI_JUMBO_FRAMELEN) 700 panic("ti_jref: adjusting refcount of buf of wrong size!"); 701 702 /* calculate the slot this buffer belongs to */ 703 704 i = ((vm_offset_t)aptr 705 - (vm_offset_t)sc->ti_cdata.ti_jumbo_buf) / TI_JLEN; 706 707 if ((i < 0) || (i >= TI_JSLOTS)) 708 panic("ti_jref: asked to reference buffer " 709 "that we don't manage!"); 710 else if (sc->ti_cdata.ti_jslots[i].ti_inuse == 0) 711 panic("ti_jref: buffer already free!"); 712 else 713 sc->ti_cdata.ti_jslots[i].ti_inuse++; 714 715 return; 716 } 717 718 /* 719 * Release a jumbo buffer. 720 */ 721 static void ti_jfree(buf, size) 722 caddr_t buf; 723 u_int size; 724 { 725 struct ti_softc *sc; 726 u_int64_t **aptr; 727 int i; 728 struct ti_jpool_entry *entry; 729 730 /* Extract the softc struct pointer. */ 731 aptr = (u_int64_t **)(buf - sizeof(u_int64_t)); 732 sc = (struct ti_softc *)(aptr[0]); 733 734 if (sc == NULL) 735 panic("ti_jfree: can't find softc pointer!"); 736 737 if (size != TI_JUMBO_FRAMELEN) 738 panic("ti_jfree: freeing buffer of wrong size!"); 739 740 /* calculate the slot this buffer belongs to */ 741 742 i = ((vm_offset_t)aptr 743 - (vm_offset_t)sc->ti_cdata.ti_jumbo_buf) / TI_JLEN; 744 745 if ((i < 0) || (i >= TI_JSLOTS)) 746 panic("ti_jfree: asked to free buffer that we don't manage!"); 747 else if (sc->ti_cdata.ti_jslots[i].ti_inuse == 0) 748 panic("ti_jfree: buffer already free!"); 749 else { 750 sc->ti_cdata.ti_jslots[i].ti_inuse--; 751 if(sc->ti_cdata.ti_jslots[i].ti_inuse == 0) { 752 entry = SLIST_FIRST(&sc->ti_jinuse_listhead); 753 if (entry == NULL) 754 panic("ti_jfree: buffer not in use!"); 755 entry->slot = i; 756 SLIST_REMOVE_HEAD(&sc->ti_jinuse_listhead, 757 jpool_entries); 758 SLIST_INSERT_HEAD(&sc->ti_jfree_listhead, 759 entry, jpool_entries); 760 } 761 } 762 763 return; 764 } 765 766 767 /* 768 * Intialize a standard receive ring descriptor. 769 */ 770 static int ti_newbuf_std(sc, i, m) 771 struct ti_softc *sc; 772 int i; 773 struct mbuf *m; 774 { 775 struct mbuf *m_new = NULL; 776 struct ti_rx_desc *r; 777 778 if (m == NULL) { 779 MGETHDR(m_new, MB_DONTWAIT, MT_DATA); 780 if (m_new == NULL) 781 return(ENOBUFS); 782 783 MCLGET(m_new, MB_DONTWAIT); 784 if (!(m_new->m_flags & M_EXT)) { 785 m_freem(m_new); 786 return(ENOBUFS); 787 } 788 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 789 } else { 790 m_new = m; 791 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 792 m_new->m_data = m_new->m_ext.ext_buf; 793 } 794 795 m_adj(m_new, ETHER_ALIGN); 796 sc->ti_cdata.ti_rx_std_chain[i] = m_new; 797 r = &sc->ti_rdata->ti_rx_std_ring[i]; 798 TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t)); 799 r->ti_type = TI_BDTYPE_RECV_BD; 800 r->ti_flags = 0; 801 if (sc->arpcom.ac_if.if_hwassist) 802 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM; 803 r->ti_len = m_new->m_len; 804 r->ti_idx = i; 805 806 return(0); 807 } 808 809 /* 810 * Intialize a mini receive ring descriptor. This only applies to 811 * the Tigon 2. 812 */ 813 static int ti_newbuf_mini(sc, i, m) 814 struct ti_softc *sc; 815 int i; 816 struct mbuf *m; 817 { 818 struct mbuf *m_new = NULL; 819 struct ti_rx_desc *r; 820 821 if (m == NULL) { 822 MGETHDR(m_new, MB_DONTWAIT, MT_DATA); 823 if (m_new == NULL) { 824 return(ENOBUFS); 825 } 826 m_new->m_len = m_new->m_pkthdr.len = MHLEN; 827 } else { 828 m_new = m; 829 m_new->m_data = m_new->m_pktdat; 830 m_new->m_len = m_new->m_pkthdr.len = MHLEN; 831 } 832 833 m_adj(m_new, ETHER_ALIGN); 834 r = &sc->ti_rdata->ti_rx_mini_ring[i]; 835 sc->ti_cdata.ti_rx_mini_chain[i] = m_new; 836 TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t)); 837 r->ti_type = TI_BDTYPE_RECV_BD; 838 r->ti_flags = TI_BDFLAG_MINI_RING; 839 if (sc->arpcom.ac_if.if_hwassist) 840 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM; 841 r->ti_len = m_new->m_len; 842 r->ti_idx = i; 843 844 return(0); 845 } 846 847 /* 848 * Initialize a jumbo receive ring descriptor. This allocates 849 * a jumbo buffer from the pool managed internally by the driver. 850 */ 851 static int ti_newbuf_jumbo(sc, i, m) 852 struct ti_softc *sc; 853 int i; 854 struct mbuf *m; 855 { 856 struct mbuf *m_new = NULL; 857 struct ti_rx_desc *r; 858 859 if (m == NULL) { 860 caddr_t *buf = NULL; 861 862 /* Allocate the mbuf. */ 863 MGETHDR(m_new, MB_DONTWAIT, MT_DATA); 864 if (m_new == NULL) { 865 return(ENOBUFS); 866 } 867 868 /* Allocate the jumbo buffer */ 869 buf = ti_jalloc(sc); 870 if (buf == NULL) { 871 m_freem(m_new); 872 printf("ti%d: jumbo allocation failed " 873 "-- packet dropped!\n", sc->ti_unit); 874 return(ENOBUFS); 875 } 876 877 /* Attach the buffer to the mbuf. */ 878 m_new->m_data = m_new->m_ext.ext_buf = (void *)buf; 879 m_new->m_flags |= M_EXT | M_EXT_OLD; 880 m_new->m_len = m_new->m_pkthdr.len = 881 m_new->m_ext.ext_size = TI_JUMBO_FRAMELEN; 882 m_new->m_ext.ext_nfree.old = ti_jfree; 883 m_new->m_ext.ext_nref.old = ti_jref; 884 } else { 885 m_new = m; 886 m_new->m_data = m_new->m_ext.ext_buf; 887 m_new->m_ext.ext_size = TI_JUMBO_FRAMELEN; 888 } 889 890 m_adj(m_new, ETHER_ALIGN); 891 /* Set up the descriptor. */ 892 r = &sc->ti_rdata->ti_rx_jumbo_ring[i]; 893 sc->ti_cdata.ti_rx_jumbo_chain[i] = m_new; 894 TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t)); 895 r->ti_type = TI_BDTYPE_RECV_JUMBO_BD; 896 r->ti_flags = TI_BDFLAG_JUMBO_RING; 897 if (sc->arpcom.ac_if.if_hwassist) 898 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM; 899 r->ti_len = m_new->m_len; 900 r->ti_idx = i; 901 902 return(0); 903 } 904 905 /* 906 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 907 * that's 1MB or memory, which is a lot. For now, we fill only the first 908 * 256 ring entries and hope that our CPU is fast enough to keep up with 909 * the NIC. 910 */ 911 static int ti_init_rx_ring_std(sc) 912 struct ti_softc *sc; 913 { 914 int i; 915 struct ti_cmd_desc cmd; 916 917 for (i = 0; i < TI_SSLOTS; i++) { 918 if (ti_newbuf_std(sc, i, NULL) == ENOBUFS) 919 return(ENOBUFS); 920 }; 921 922 TI_UPDATE_STDPROD(sc, i - 1); 923 sc->ti_std = i - 1; 924 925 return(0); 926 } 927 928 static void ti_free_rx_ring_std(sc) 929 struct ti_softc *sc; 930 { 931 int i; 932 933 for (i = 0; i < TI_STD_RX_RING_CNT; i++) { 934 if (sc->ti_cdata.ti_rx_std_chain[i] != NULL) { 935 m_freem(sc->ti_cdata.ti_rx_std_chain[i]); 936 sc->ti_cdata.ti_rx_std_chain[i] = NULL; 937 } 938 bzero((char *)&sc->ti_rdata->ti_rx_std_ring[i], 939 sizeof(struct ti_rx_desc)); 940 } 941 942 return; 943 } 944 945 static int ti_init_rx_ring_jumbo(sc) 946 struct ti_softc *sc; 947 { 948 int i; 949 struct ti_cmd_desc cmd; 950 951 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) { 952 if (ti_newbuf_jumbo(sc, i, NULL) == ENOBUFS) 953 return(ENOBUFS); 954 }; 955 956 TI_UPDATE_JUMBOPROD(sc, i - 1); 957 sc->ti_jumbo = i - 1; 958 959 return(0); 960 } 961 962 static void ti_free_rx_ring_jumbo(sc) 963 struct ti_softc *sc; 964 { 965 int i; 966 967 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) { 968 if (sc->ti_cdata.ti_rx_jumbo_chain[i] != NULL) { 969 m_freem(sc->ti_cdata.ti_rx_jumbo_chain[i]); 970 sc->ti_cdata.ti_rx_jumbo_chain[i] = NULL; 971 } 972 bzero((char *)&sc->ti_rdata->ti_rx_jumbo_ring[i], 973 sizeof(struct ti_rx_desc)); 974 } 975 976 return; 977 } 978 979 static int ti_init_rx_ring_mini(sc) 980 struct ti_softc *sc; 981 { 982 int i; 983 984 for (i = 0; i < TI_MSLOTS; i++) { 985 if (ti_newbuf_mini(sc, i, NULL) == ENOBUFS) 986 return(ENOBUFS); 987 }; 988 989 TI_UPDATE_MINIPROD(sc, i - 1); 990 sc->ti_mini = i - 1; 991 992 return(0); 993 } 994 995 static void ti_free_rx_ring_mini(sc) 996 struct ti_softc *sc; 997 { 998 int i; 999 1000 for (i = 0; i < TI_MINI_RX_RING_CNT; i++) { 1001 if (sc->ti_cdata.ti_rx_mini_chain[i] != NULL) { 1002 m_freem(sc->ti_cdata.ti_rx_mini_chain[i]); 1003 sc->ti_cdata.ti_rx_mini_chain[i] = NULL; 1004 } 1005 bzero((char *)&sc->ti_rdata->ti_rx_mini_ring[i], 1006 sizeof(struct ti_rx_desc)); 1007 } 1008 1009 return; 1010 } 1011 1012 static void ti_free_tx_ring(sc) 1013 struct ti_softc *sc; 1014 { 1015 int i; 1016 1017 if (sc->ti_rdata->ti_tx_ring == NULL) 1018 return; 1019 1020 for (i = 0; i < TI_TX_RING_CNT; i++) { 1021 if (sc->ti_cdata.ti_tx_chain[i] != NULL) { 1022 m_freem(sc->ti_cdata.ti_tx_chain[i]); 1023 sc->ti_cdata.ti_tx_chain[i] = NULL; 1024 } 1025 bzero((char *)&sc->ti_rdata->ti_tx_ring[i], 1026 sizeof(struct ti_tx_desc)); 1027 } 1028 1029 return; 1030 } 1031 1032 static int ti_init_tx_ring(sc) 1033 struct ti_softc *sc; 1034 { 1035 sc->ti_txcnt = 0; 1036 sc->ti_tx_saved_considx = 0; 1037 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, 0); 1038 return(0); 1039 } 1040 1041 /* 1042 * The Tigon 2 firmware has a new way to add/delete multicast addresses, 1043 * but we have to support the old way too so that Tigon 1 cards will 1044 * work. 1045 */ 1046 void ti_add_mcast(sc, addr) 1047 struct ti_softc *sc; 1048 struct ether_addr *addr; 1049 { 1050 struct ti_cmd_desc cmd; 1051 u_int16_t *m; 1052 u_int32_t ext[2] = {0, 0}; 1053 1054 m = (u_int16_t *)&addr->octet[0]; 1055 1056 switch(sc->ti_hwrev) { 1057 case TI_HWREV_TIGON: 1058 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0])); 1059 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2])); 1060 TI_DO_CMD(TI_CMD_ADD_MCAST_ADDR, 0, 0); 1061 break; 1062 case TI_HWREV_TIGON_II: 1063 ext[0] = htons(m[0]); 1064 ext[1] = (htons(m[1]) << 16) | htons(m[2]); 1065 TI_DO_CMD_EXT(TI_CMD_EXT_ADD_MCAST, 0, 0, (caddr_t)&ext, 2); 1066 break; 1067 default: 1068 printf("ti%d: unknown hwrev\n", sc->ti_unit); 1069 break; 1070 } 1071 1072 return; 1073 } 1074 1075 void ti_del_mcast(sc, addr) 1076 struct ti_softc *sc; 1077 struct ether_addr *addr; 1078 { 1079 struct ti_cmd_desc cmd; 1080 u_int16_t *m; 1081 u_int32_t ext[2] = {0, 0}; 1082 1083 m = (u_int16_t *)&addr->octet[0]; 1084 1085 switch(sc->ti_hwrev) { 1086 case TI_HWREV_TIGON: 1087 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0])); 1088 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2])); 1089 TI_DO_CMD(TI_CMD_DEL_MCAST_ADDR, 0, 0); 1090 break; 1091 case TI_HWREV_TIGON_II: 1092 ext[0] = htons(m[0]); 1093 ext[1] = (htons(m[1]) << 16) | htons(m[2]); 1094 TI_DO_CMD_EXT(TI_CMD_EXT_DEL_MCAST, 0, 0, (caddr_t)&ext, 2); 1095 break; 1096 default: 1097 printf("ti%d: unknown hwrev\n", sc->ti_unit); 1098 break; 1099 } 1100 1101 return; 1102 } 1103 1104 /* 1105 * Configure the Tigon's multicast address filter. 1106 * 1107 * The actual multicast table management is a bit of a pain, thanks to 1108 * slight brain damage on the part of both Alteon and us. With our 1109 * multicast code, we are only alerted when the multicast address table 1110 * changes and at that point we only have the current list of addresses: 1111 * we only know the current state, not the previous state, so we don't 1112 * actually know what addresses were removed or added. The firmware has 1113 * state, but we can't get our grubby mits on it, and there is no 'delete 1114 * all multicast addresses' command. Hence, we have to maintain our own 1115 * state so we know what addresses have been programmed into the NIC at 1116 * any given time. 1117 */ 1118 static void ti_setmulti(sc) 1119 struct ti_softc *sc; 1120 { 1121 struct ifnet *ifp; 1122 struct ifmultiaddr *ifma; 1123 struct ti_cmd_desc cmd; 1124 struct ti_mc_entry *mc; 1125 u_int32_t intrs; 1126 1127 ifp = &sc->arpcom.ac_if; 1128 1129 if (ifp->if_flags & IFF_ALLMULTI) { 1130 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_ENB, 0); 1131 return; 1132 } else { 1133 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_DIS, 0); 1134 } 1135 1136 /* Disable interrupts. */ 1137 intrs = CSR_READ_4(sc, TI_MB_HOSTINTR); 1138 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 1139 1140 /* First, zot all the existing filters. */ 1141 while (sc->ti_mc_listhead.slh_first != NULL) { 1142 mc = sc->ti_mc_listhead.slh_first; 1143 ti_del_mcast(sc, &mc->mc_addr); 1144 SLIST_REMOVE_HEAD(&sc->ti_mc_listhead, mc_entries); 1145 free(mc, M_DEVBUF); 1146 } 1147 1148 /* Now program new ones. */ 1149 for (ifma = ifp->if_multiaddrs.lh_first; 1150 ifma != NULL; ifma = ifma->ifma_link.le_next) { 1151 if (ifma->ifma_addr->sa_family != AF_LINK) 1152 continue; 1153 mc = malloc(sizeof(struct ti_mc_entry), M_DEVBUF, M_INTWAIT); 1154 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 1155 (char *)&mc->mc_addr, ETHER_ADDR_LEN); 1156 SLIST_INSERT_HEAD(&sc->ti_mc_listhead, mc, mc_entries); 1157 ti_add_mcast(sc, &mc->mc_addr); 1158 } 1159 1160 /* Re-enable interrupts. */ 1161 CSR_WRITE_4(sc, TI_MB_HOSTINTR, intrs); 1162 1163 return; 1164 } 1165 1166 /* 1167 * Check to see if the BIOS has configured us for a 64 bit slot when 1168 * we aren't actually in one. If we detect this condition, we can work 1169 * around it on the Tigon 2 by setting a bit in the PCI state register, 1170 * but for the Tigon 1 we must give up and abort the interface attach. 1171 */ 1172 static int ti_64bitslot_war(sc) 1173 struct ti_softc *sc; 1174 { 1175 if (!(CSR_READ_4(sc, TI_PCI_STATE) & TI_PCISTATE_32BIT_BUS)) { 1176 CSR_WRITE_4(sc, 0x600, 0); 1177 CSR_WRITE_4(sc, 0x604, 0); 1178 CSR_WRITE_4(sc, 0x600, 0x5555AAAA); 1179 if (CSR_READ_4(sc, 0x604) == 0x5555AAAA) { 1180 if (sc->ti_hwrev == TI_HWREV_TIGON) 1181 return(EINVAL); 1182 else { 1183 TI_SETBIT(sc, TI_PCI_STATE, 1184 TI_PCISTATE_32BIT_BUS); 1185 return(0); 1186 } 1187 } 1188 } 1189 1190 return(0); 1191 } 1192 1193 /* 1194 * Do endian, PCI and DMA initialization. Also check the on-board ROM 1195 * self-test results. 1196 */ 1197 static int ti_chipinit(sc) 1198 struct ti_softc *sc; 1199 { 1200 u_int32_t cacheline; 1201 u_int32_t pci_writemax = 0; 1202 1203 /* Initialize link to down state. */ 1204 sc->ti_linkstat = TI_EV_CODE_LINK_DOWN; 1205 1206 if (sc->arpcom.ac_if.if_capenable & IFCAP_HWCSUM) 1207 sc->arpcom.ac_if.if_hwassist = TI_CSUM_FEATURES; 1208 else 1209 sc->arpcom.ac_if.if_hwassist = 0; 1210 1211 /* Set endianness before we access any non-PCI registers. */ 1212 #if BYTE_ORDER == BIG_ENDIAN 1213 CSR_WRITE_4(sc, TI_MISC_HOST_CTL, 1214 TI_MHC_BIGENDIAN_INIT | (TI_MHC_BIGENDIAN_INIT << 24)); 1215 #else 1216 CSR_WRITE_4(sc, TI_MISC_HOST_CTL, 1217 TI_MHC_LITTLEENDIAN_INIT | (TI_MHC_LITTLEENDIAN_INIT << 24)); 1218 #endif 1219 1220 /* Check the ROM failed bit to see if self-tests passed. */ 1221 if (CSR_READ_4(sc, TI_CPU_STATE) & TI_CPUSTATE_ROMFAIL) { 1222 printf("ti%d: board self-diagnostics failed!\n", sc->ti_unit); 1223 return(ENODEV); 1224 } 1225 1226 /* Halt the CPU. */ 1227 TI_SETBIT(sc, TI_CPU_STATE, TI_CPUSTATE_HALT); 1228 1229 /* Figure out the hardware revision. */ 1230 switch(CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_CHIP_REV_MASK) { 1231 case TI_REV_TIGON_I: 1232 sc->ti_hwrev = TI_HWREV_TIGON; 1233 break; 1234 case TI_REV_TIGON_II: 1235 sc->ti_hwrev = TI_HWREV_TIGON_II; 1236 break; 1237 default: 1238 printf("ti%d: unsupported chip revision\n", sc->ti_unit); 1239 return(ENODEV); 1240 } 1241 1242 /* Do special setup for Tigon 2. */ 1243 if (sc->ti_hwrev == TI_HWREV_TIGON_II) { 1244 TI_SETBIT(sc, TI_CPU_CTL_B, TI_CPUSTATE_HALT); 1245 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_SRAM_BANK_512K); 1246 TI_SETBIT(sc, TI_MISC_CONF, TI_MCR_SRAM_SYNCHRONOUS); 1247 } 1248 1249 /* Set up the PCI state register. */ 1250 CSR_WRITE_4(sc, TI_PCI_STATE, TI_PCI_READ_CMD|TI_PCI_WRITE_CMD); 1251 if (sc->ti_hwrev == TI_HWREV_TIGON_II) { 1252 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_USE_MEM_RD_MULT); 1253 } 1254 1255 /* Clear the read/write max DMA parameters. */ 1256 TI_CLRBIT(sc, TI_PCI_STATE, (TI_PCISTATE_WRITE_MAXDMA| 1257 TI_PCISTATE_READ_MAXDMA)); 1258 1259 /* Get cache line size. */ 1260 cacheline = CSR_READ_4(sc, TI_PCI_BIST) & 0xFF; 1261 1262 /* 1263 * If the system has set enabled the PCI memory write 1264 * and invalidate command in the command register, set 1265 * the write max parameter accordingly. This is necessary 1266 * to use MWI with the Tigon 2. 1267 */ 1268 if (CSR_READ_4(sc, TI_PCI_CMDSTAT) & PCIM_CMD_MWIEN) { 1269 switch(cacheline) { 1270 case 1: 1271 case 4: 1272 case 8: 1273 case 16: 1274 case 32: 1275 case 64: 1276 break; 1277 default: 1278 /* Disable PCI memory write and invalidate. */ 1279 if (bootverbose) 1280 printf("ti%d: cache line size %d not " 1281 "supported; disabling PCI MWI\n", 1282 sc->ti_unit, cacheline); 1283 CSR_WRITE_4(sc, TI_PCI_CMDSTAT, CSR_READ_4(sc, 1284 TI_PCI_CMDSTAT) & ~PCIM_CMD_MWIEN); 1285 break; 1286 } 1287 } 1288 1289 #ifdef __brokenalpha__ 1290 /* 1291 * From the Alteon sample driver: 1292 * Must insure that we do not cross an 8K (bytes) boundary 1293 * for DMA reads. Our highest limit is 1K bytes. This is a 1294 * restriction on some ALPHA platforms with early revision 1295 * 21174 PCI chipsets, such as the AlphaPC 164lx 1296 */ 1297 TI_SETBIT(sc, TI_PCI_STATE, pci_writemax|TI_PCI_READMAX_1024); 1298 #else 1299 TI_SETBIT(sc, TI_PCI_STATE, pci_writemax); 1300 #endif 1301 1302 /* This sets the min dma param all the way up (0xff). */ 1303 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_MINDMA); 1304 1305 /* Configure DMA variables. */ 1306 #if BYTE_ORDER == BIG_ENDIAN 1307 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_BD | 1308 TI_OPMODE_BYTESWAP_DATA | TI_OPMODE_WORDSWAP_BD | 1309 TI_OPMODE_WARN_ENB | TI_OPMODE_FATAL_ENB | 1310 TI_OPMODE_DONT_FRAG_JUMBO); 1311 #else 1312 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_DATA| 1313 TI_OPMODE_WORDSWAP_BD|TI_OPMODE_DONT_FRAG_JUMBO| 1314 TI_OPMODE_WARN_ENB|TI_OPMODE_FATAL_ENB); 1315 #endif 1316 1317 /* 1318 * Only allow 1 DMA channel to be active at a time. 1319 * I don't think this is a good idea, but without it 1320 * the firmware racks up lots of nicDmaReadRingFull 1321 * errors. This is not compatible with hardware checksums. 1322 */ 1323 if (sc->arpcom.ac_if.if_hwassist == 0) 1324 TI_SETBIT(sc, TI_GCR_OPMODE, TI_OPMODE_1_DMA_ACTIVE); 1325 1326 /* Recommended settings from Tigon manual. */ 1327 CSR_WRITE_4(sc, TI_GCR_DMA_WRITECFG, TI_DMA_STATE_THRESH_8W); 1328 CSR_WRITE_4(sc, TI_GCR_DMA_READCFG, TI_DMA_STATE_THRESH_8W); 1329 1330 if (ti_64bitslot_war(sc)) { 1331 printf("ti%d: bios thinks we're in a 64 bit slot, " 1332 "but we aren't", sc->ti_unit); 1333 return(EINVAL); 1334 } 1335 1336 return(0); 1337 } 1338 1339 /* 1340 * Initialize the general information block and firmware, and 1341 * start the CPU(s) running. 1342 */ 1343 static int ti_gibinit(sc) 1344 struct ti_softc *sc; 1345 { 1346 struct ti_rcb *rcb; 1347 int i; 1348 struct ifnet *ifp; 1349 1350 ifp = &sc->arpcom.ac_if; 1351 1352 /* Disable interrupts for now. */ 1353 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 1354 1355 /* Tell the chip where to find the general information block. */ 1356 CSR_WRITE_4(sc, TI_GCR_GENINFO_HI, 0); 1357 CSR_WRITE_4(sc, TI_GCR_GENINFO_LO, vtophys(&sc->ti_rdata->ti_info)); 1358 1359 /* Load the firmware into SRAM. */ 1360 ti_loadfw(sc); 1361 1362 /* Set up the contents of the general info and ring control blocks. */ 1363 1364 /* Set up the event ring and producer pointer. */ 1365 rcb = &sc->ti_rdata->ti_info.ti_ev_rcb; 1366 1367 TI_HOSTADDR(rcb->ti_hostaddr) = vtophys(&sc->ti_rdata->ti_event_ring); 1368 rcb->ti_flags = 0; 1369 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_ev_prodidx_ptr) = 1370 vtophys(&sc->ti_ev_prodidx); 1371 sc->ti_ev_prodidx.ti_idx = 0; 1372 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, 0); 1373 sc->ti_ev_saved_considx = 0; 1374 1375 /* Set up the command ring and producer mailbox. */ 1376 rcb = &sc->ti_rdata->ti_info.ti_cmd_rcb; 1377 1378 sc->ti_rdata->ti_cmd_ring = 1379 (struct ti_cmd_desc *)(sc->ti_vhandle + TI_GCR_CMDRING); 1380 TI_HOSTADDR(rcb->ti_hostaddr) = TI_GCR_NIC_ADDR(TI_GCR_CMDRING); 1381 rcb->ti_flags = 0; 1382 rcb->ti_max_len = 0; 1383 for (i = 0; i < TI_CMD_RING_CNT; i++) { 1384 CSR_WRITE_4(sc, TI_GCR_CMDRING + (i * 4), 0); 1385 } 1386 CSR_WRITE_4(sc, TI_GCR_CMDCONS_IDX, 0); 1387 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, 0); 1388 sc->ti_cmd_saved_prodidx = 0; 1389 1390 /* 1391 * Assign the address of the stats refresh buffer. 1392 * We re-use the current stats buffer for this to 1393 * conserve memory. 1394 */ 1395 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_refresh_stats_ptr) = 1396 vtophys(&sc->ti_rdata->ti_info.ti_stats); 1397 1398 /* Set up the standard receive ring. */ 1399 rcb = &sc->ti_rdata->ti_info.ti_std_rx_rcb; 1400 TI_HOSTADDR(rcb->ti_hostaddr) = vtophys(&sc->ti_rdata->ti_rx_std_ring); 1401 rcb->ti_max_len = TI_FRAMELEN; 1402 rcb->ti_flags = 0; 1403 if (sc->arpcom.ac_if.if_hwassist) 1404 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 1405 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 1406 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1407 1408 /* Set up the jumbo receive ring. */ 1409 rcb = &sc->ti_rdata->ti_info.ti_jumbo_rx_rcb; 1410 TI_HOSTADDR(rcb->ti_hostaddr) = 1411 vtophys(&sc->ti_rdata->ti_rx_jumbo_ring); 1412 rcb->ti_max_len = TI_JUMBO_FRAMELEN; 1413 rcb->ti_flags = 0; 1414 if (sc->arpcom.ac_if.if_hwassist) 1415 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 1416 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 1417 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1418 1419 /* 1420 * Set up the mini ring. Only activated on the 1421 * Tigon 2 but the slot in the config block is 1422 * still there on the Tigon 1. 1423 */ 1424 rcb = &sc->ti_rdata->ti_info.ti_mini_rx_rcb; 1425 TI_HOSTADDR(rcb->ti_hostaddr) = 1426 vtophys(&sc->ti_rdata->ti_rx_mini_ring); 1427 rcb->ti_max_len = MHLEN - ETHER_ALIGN; 1428 if (sc->ti_hwrev == TI_HWREV_TIGON) 1429 rcb->ti_flags = TI_RCB_FLAG_RING_DISABLED; 1430 else 1431 rcb->ti_flags = 0; 1432 if (sc->arpcom.ac_if.if_hwassist) 1433 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 1434 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 1435 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1436 1437 /* 1438 * Set up the receive return ring. 1439 */ 1440 rcb = &sc->ti_rdata->ti_info.ti_return_rcb; 1441 TI_HOSTADDR(rcb->ti_hostaddr) = 1442 vtophys(&sc->ti_rdata->ti_rx_return_ring); 1443 rcb->ti_flags = 0; 1444 rcb->ti_max_len = TI_RETURN_RING_CNT; 1445 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_return_prodidx_ptr) = 1446 vtophys(&sc->ti_return_prodidx); 1447 1448 /* 1449 * Set up the tx ring. Note: for the Tigon 2, we have the option 1450 * of putting the transmit ring in the host's address space and 1451 * letting the chip DMA it instead of leaving the ring in the NIC's 1452 * memory and accessing it through the shared memory region. We 1453 * do this for the Tigon 2, but it doesn't work on the Tigon 1, 1454 * so we have to revert to the shared memory scheme if we detect 1455 * a Tigon 1 chip. 1456 */ 1457 CSR_WRITE_4(sc, TI_WINBASE, TI_TX_RING_BASE); 1458 if (sc->ti_hwrev == TI_HWREV_TIGON) { 1459 sc->ti_rdata->ti_tx_ring_nic = 1460 (struct ti_tx_desc *)(sc->ti_vhandle + TI_WINDOW); 1461 } 1462 bzero((char *)sc->ti_rdata->ti_tx_ring, 1463 TI_TX_RING_CNT * sizeof(struct ti_tx_desc)); 1464 rcb = &sc->ti_rdata->ti_info.ti_tx_rcb; 1465 if (sc->ti_hwrev == TI_HWREV_TIGON) 1466 rcb->ti_flags = 0; 1467 else 1468 rcb->ti_flags = TI_RCB_FLAG_HOST_RING; 1469 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1470 if (sc->arpcom.ac_if.if_hwassist) 1471 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 1472 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 1473 rcb->ti_max_len = TI_TX_RING_CNT; 1474 if (sc->ti_hwrev == TI_HWREV_TIGON) 1475 TI_HOSTADDR(rcb->ti_hostaddr) = TI_TX_RING_BASE; 1476 else 1477 TI_HOSTADDR(rcb->ti_hostaddr) = 1478 vtophys(&sc->ti_rdata->ti_tx_ring); 1479 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_tx_considx_ptr) = 1480 vtophys(&sc->ti_tx_considx); 1481 1482 /* Set up tuneables */ 1483 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 1484 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, 1485 (sc->ti_rx_coal_ticks / 10)); 1486 else 1487 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, sc->ti_rx_coal_ticks); 1488 CSR_WRITE_4(sc, TI_GCR_TX_COAL_TICKS, sc->ti_tx_coal_ticks); 1489 CSR_WRITE_4(sc, TI_GCR_STAT_TICKS, sc->ti_stat_ticks); 1490 CSR_WRITE_4(sc, TI_GCR_RX_MAX_COAL_BD, sc->ti_rx_max_coal_bds); 1491 CSR_WRITE_4(sc, TI_GCR_TX_MAX_COAL_BD, sc->ti_tx_max_coal_bds); 1492 CSR_WRITE_4(sc, TI_GCR_TX_BUFFER_RATIO, sc->ti_tx_buf_ratio); 1493 1494 /* Turn interrupts on. */ 1495 CSR_WRITE_4(sc, TI_GCR_MASK_INTRS, 0); 1496 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 1497 1498 /* Start CPU. */ 1499 TI_CLRBIT(sc, TI_CPU_STATE, (TI_CPUSTATE_HALT|TI_CPUSTATE_STEP)); 1500 1501 return(0); 1502 } 1503 1504 /* 1505 * Probe for a Tigon chip. Check the PCI vendor and device IDs 1506 * against our list and return its name if we find a match. 1507 */ 1508 static int ti_probe(dev) 1509 device_t dev; 1510 { 1511 struct ti_type *t; 1512 1513 t = ti_devs; 1514 1515 while(t->ti_name != NULL) { 1516 if ((pci_get_vendor(dev) == t->ti_vid) && 1517 (pci_get_device(dev) == t->ti_did)) { 1518 device_set_desc(dev, t->ti_name); 1519 return(0); 1520 } 1521 t++; 1522 } 1523 1524 return(ENXIO); 1525 } 1526 1527 static int ti_attach(dev) 1528 device_t dev; 1529 { 1530 int s; 1531 u_int32_t command; 1532 struct ifnet *ifp; 1533 struct ti_softc *sc; 1534 int unit, error = 0, rid; 1535 1536 s = splimp(); 1537 1538 sc = device_get_softc(dev); 1539 unit = device_get_unit(dev); 1540 bzero(sc, sizeof(struct ti_softc)); 1541 sc->arpcom.ac_if.if_capabilities = IFCAP_HWCSUM; 1542 sc->arpcom.ac_if.if_capenable = sc->arpcom.ac_if.if_capabilities; 1543 1544 /* 1545 * Map control/status registers. 1546 */ 1547 command = pci_read_config(dev, PCIR_COMMAND, 4); 1548 command |= (PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 1549 pci_write_config(dev, PCIR_COMMAND, command, 4); 1550 command = pci_read_config(dev, PCIR_COMMAND, 4); 1551 1552 if (!(command & PCIM_CMD_MEMEN)) { 1553 printf("ti%d: failed to enable memory mapping!\n", unit); 1554 error = ENXIO; 1555 goto fail; 1556 } 1557 1558 rid = TI_PCI_LOMEM; 1559 sc->ti_res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 1560 0, ~0, 1, RF_ACTIVE); 1561 1562 if (sc->ti_res == NULL) { 1563 printf ("ti%d: couldn't map memory\n", unit); 1564 error = ENXIO; 1565 goto fail; 1566 } 1567 1568 sc->ti_btag = rman_get_bustag(sc->ti_res); 1569 sc->ti_bhandle = rman_get_bushandle(sc->ti_res); 1570 sc->ti_vhandle = (vm_offset_t)rman_get_virtual(sc->ti_res); 1571 1572 /* 1573 * XXX FIXME: rman_get_virtual() on the alpha is currently 1574 * broken and returns a physical address instead of a kernel 1575 * virtual address. Consequently, we need to do a little 1576 * extra mangling of the vhandle on the alpha. This should 1577 * eventually be fixed! The whole idea here is to get rid 1578 * of platform dependencies. 1579 */ 1580 #ifdef __alpha__ 1581 if (pci_cvt_to_bwx(sc->ti_vhandle)) 1582 sc->ti_vhandle = pci_cvt_to_bwx(sc->ti_vhandle); 1583 else 1584 sc->ti_vhandle = pci_cvt_to_dense(sc->ti_vhandle); 1585 sc->ti_vhandle = ALPHA_PHYS_TO_K0SEG(sc->ti_vhandle); 1586 #endif 1587 1588 /* Allocate interrupt */ 1589 rid = 0; 1590 1591 sc->ti_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 1592 RF_SHAREABLE | RF_ACTIVE); 1593 1594 if (sc->ti_irq == NULL) { 1595 printf("ti%d: couldn't map interrupt\n", unit); 1596 error = ENXIO; 1597 goto fail; 1598 } 1599 1600 error = bus_setup_intr(dev, sc->ti_irq, INTR_TYPE_NET, 1601 ti_intr, sc, &sc->ti_intrhand); 1602 1603 if (error) { 1604 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 1605 bus_release_resource(dev, SYS_RES_MEMORY, 1606 TI_PCI_LOMEM, sc->ti_res); 1607 printf("ti%d: couldn't set up irq\n", unit); 1608 goto fail; 1609 } 1610 1611 sc->ti_unit = unit; 1612 1613 if (ti_chipinit(sc)) { 1614 printf("ti%d: chip initialization failed\n", sc->ti_unit); 1615 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 1616 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 1617 bus_release_resource(dev, SYS_RES_MEMORY, 1618 TI_PCI_LOMEM, sc->ti_res); 1619 error = ENXIO; 1620 goto fail; 1621 } 1622 1623 /* Zero out the NIC's on-board SRAM. */ 1624 ti_mem(sc, 0x2000, 0x100000 - 0x2000, NULL); 1625 1626 /* Init again -- zeroing memory may have clobbered some registers. */ 1627 if (ti_chipinit(sc)) { 1628 printf("ti%d: chip initialization failed\n", sc->ti_unit); 1629 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 1630 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 1631 bus_release_resource(dev, SYS_RES_MEMORY, 1632 TI_PCI_LOMEM, sc->ti_res); 1633 error = ENXIO; 1634 goto fail; 1635 } 1636 1637 /* 1638 * Get station address from the EEPROM. Note: the manual states 1639 * that the MAC address is at offset 0x8c, however the data is 1640 * stored as two longwords (since that's how it's loaded into 1641 * the NIC). This means the MAC address is actually preceeded 1642 * by two zero bytes. We need to skip over those. 1643 */ 1644 if (ti_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr, 1645 TI_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) { 1646 printf("ti%d: failed to read station address\n", unit); 1647 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 1648 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 1649 bus_release_resource(dev, SYS_RES_MEMORY, 1650 TI_PCI_LOMEM, sc->ti_res); 1651 error = ENXIO; 1652 goto fail; 1653 } 1654 1655 /* Allocate the general information block and ring buffers. */ 1656 sc->ti_rdata = contigmalloc(sizeof(struct ti_ring_data), M_DEVBUF, 1657 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 1658 1659 if (sc->ti_rdata == NULL) { 1660 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 1661 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 1662 bus_release_resource(dev, SYS_RES_MEMORY, 1663 TI_PCI_LOMEM, sc->ti_res); 1664 error = ENXIO; 1665 printf("ti%d: no memory for list buffers!\n", sc->ti_unit); 1666 goto fail; 1667 } 1668 1669 bzero(sc->ti_rdata, sizeof(struct ti_ring_data)); 1670 1671 /* Try to allocate memory for jumbo buffers. */ 1672 if (ti_alloc_jumbo_mem(sc)) { 1673 printf("ti%d: jumbo buffer allocation failed\n", sc->ti_unit); 1674 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 1675 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 1676 bus_release_resource(dev, SYS_RES_MEMORY, 1677 TI_PCI_LOMEM, sc->ti_res); 1678 contigfree(sc->ti_rdata, sizeof(struct ti_ring_data), 1679 M_DEVBUF); 1680 error = ENXIO; 1681 goto fail; 1682 } 1683 1684 /* 1685 * We really need a better way to tell a 1000baseTX card 1686 * from a 1000baseSX one, since in theory there could be 1687 * OEMed 1000baseTX cards from lame vendors who aren't 1688 * clever enough to change the PCI ID. For the moment 1689 * though, the AceNIC is the only copper card available. 1690 */ 1691 if (pci_get_vendor(dev) == ALT_VENDORID && 1692 pci_get_device(dev) == ALT_DEVICEID_ACENIC_COPPER) 1693 sc->ti_copper = 1; 1694 /* Ok, it's not the only copper card available. */ 1695 if (pci_get_vendor(dev) == NG_VENDORID && 1696 pci_get_device(dev) == NG_DEVICEID_GA620T) 1697 sc->ti_copper = 1; 1698 1699 /* Set default tuneable values. */ 1700 sc->ti_stat_ticks = 2 * TI_TICKS_PER_SEC; 1701 sc->ti_rx_coal_ticks = TI_TICKS_PER_SEC / 5000; 1702 sc->ti_tx_coal_ticks = TI_TICKS_PER_SEC / 500; 1703 sc->ti_rx_max_coal_bds = 64; 1704 sc->ti_tx_max_coal_bds = 128; 1705 sc->ti_tx_buf_ratio = 21; 1706 1707 /* Set up ifnet structure */ 1708 ifp = &sc->arpcom.ac_if; 1709 ifp->if_softc = sc; 1710 if_initname(ifp, "ti", sc->ti_unit); 1711 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1712 ifp->if_ioctl = ti_ioctl; 1713 ifp->if_start = ti_start; 1714 ifp->if_watchdog = ti_watchdog; 1715 ifp->if_init = ti_init; 1716 ifp->if_mtu = ETHERMTU; 1717 ifp->if_snd.ifq_maxlen = TI_TX_RING_CNT - 1; 1718 1719 /* Set up ifmedia support. */ 1720 ifmedia_init(&sc->ifmedia, IFM_IMASK, ti_ifmedia_upd, ti_ifmedia_sts); 1721 if (sc->ti_copper) { 1722 /* 1723 * Copper cards allow manual 10/100 mode selection, 1724 * but not manual 1000baseTX mode selection. Why? 1725 * Becuase currently there's no way to specify the 1726 * master/slave setting through the firmware interface, 1727 * so Alteon decided to just bag it and handle it 1728 * via autonegotiation. 1729 */ 1730 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL); 1731 ifmedia_add(&sc->ifmedia, 1732 IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL); 1733 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_TX, 0, NULL); 1734 ifmedia_add(&sc->ifmedia, 1735 IFM_ETHER|IFM_100_TX|IFM_FDX, 0, NULL); 1736 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_TX, 0, NULL); 1737 ifmedia_add(&sc->ifmedia, 1738 IFM_ETHER|IFM_1000_TX|IFM_FDX, 0, NULL); 1739 } else { 1740 /* Fiber cards don't support 10/100 modes. */ 1741 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL); 1742 ifmedia_add(&sc->ifmedia, 1743 IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL); 1744 } 1745 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 1746 ifmedia_set(&sc->ifmedia, IFM_ETHER|IFM_AUTO); 1747 1748 /* 1749 * Call MI attach routine. 1750 */ 1751 ether_ifattach(ifp, sc->arpcom.ac_enaddr); 1752 1753 fail: 1754 splx(s); 1755 1756 return(error); 1757 } 1758 1759 static int ti_detach(dev) 1760 device_t dev; 1761 { 1762 struct ti_softc *sc; 1763 struct ifnet *ifp; 1764 int s; 1765 1766 s = splimp(); 1767 1768 sc = device_get_softc(dev); 1769 ifp = &sc->arpcom.ac_if; 1770 1771 ether_ifdetach(ifp); 1772 ti_stop(sc); 1773 1774 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 1775 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 1776 bus_release_resource(dev, SYS_RES_MEMORY, TI_PCI_LOMEM, sc->ti_res); 1777 1778 contigfree(sc->ti_cdata.ti_jumbo_buf, TI_JMEM, M_DEVBUF); 1779 contigfree(sc->ti_rdata, sizeof(struct ti_ring_data), M_DEVBUF); 1780 ifmedia_removeall(&sc->ifmedia); 1781 1782 splx(s); 1783 1784 return(0); 1785 } 1786 1787 /* 1788 * Frame reception handling. This is called if there's a frame 1789 * on the receive return list. 1790 * 1791 * Note: we have to be able to handle three possibilities here: 1792 * 1) the frame is from the mini receive ring (can only happen) 1793 * on Tigon 2 boards) 1794 * 2) the frame is from the jumbo recieve ring 1795 * 3) the frame is from the standard receive ring 1796 */ 1797 1798 static void ti_rxeof(sc) 1799 struct ti_softc *sc; 1800 { 1801 struct ifnet *ifp; 1802 struct ti_cmd_desc cmd; 1803 1804 ifp = &sc->arpcom.ac_if; 1805 1806 while(sc->ti_rx_saved_considx != sc->ti_return_prodidx.ti_idx) { 1807 struct ti_rx_desc *cur_rx; 1808 u_int32_t rxidx; 1809 struct mbuf *m = NULL; 1810 u_int16_t vlan_tag = 0; 1811 int have_tag = 0; 1812 1813 cur_rx = 1814 &sc->ti_rdata->ti_rx_return_ring[sc->ti_rx_saved_considx]; 1815 rxidx = cur_rx->ti_idx; 1816 TI_INC(sc->ti_rx_saved_considx, TI_RETURN_RING_CNT); 1817 1818 if (cur_rx->ti_flags & TI_BDFLAG_VLAN_TAG) { 1819 have_tag = 1; 1820 vlan_tag = cur_rx->ti_vlan_tag & 0xfff; 1821 } 1822 1823 if (cur_rx->ti_flags & TI_BDFLAG_JUMBO_RING) { 1824 TI_INC(sc->ti_jumbo, TI_JUMBO_RX_RING_CNT); 1825 m = sc->ti_cdata.ti_rx_jumbo_chain[rxidx]; 1826 sc->ti_cdata.ti_rx_jumbo_chain[rxidx] = NULL; 1827 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 1828 ifp->if_ierrors++; 1829 ti_newbuf_jumbo(sc, sc->ti_jumbo, m); 1830 continue; 1831 } 1832 if (ti_newbuf_jumbo(sc, sc->ti_jumbo, NULL) == ENOBUFS) { 1833 ifp->if_ierrors++; 1834 ti_newbuf_jumbo(sc, sc->ti_jumbo, m); 1835 continue; 1836 } 1837 } else if (cur_rx->ti_flags & TI_BDFLAG_MINI_RING) { 1838 TI_INC(sc->ti_mini, TI_MINI_RX_RING_CNT); 1839 m = sc->ti_cdata.ti_rx_mini_chain[rxidx]; 1840 sc->ti_cdata.ti_rx_mini_chain[rxidx] = NULL; 1841 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 1842 ifp->if_ierrors++; 1843 ti_newbuf_mini(sc, sc->ti_mini, m); 1844 continue; 1845 } 1846 if (ti_newbuf_mini(sc, sc->ti_mini, NULL) == ENOBUFS) { 1847 ifp->if_ierrors++; 1848 ti_newbuf_mini(sc, sc->ti_mini, m); 1849 continue; 1850 } 1851 } else { 1852 TI_INC(sc->ti_std, TI_STD_RX_RING_CNT); 1853 m = sc->ti_cdata.ti_rx_std_chain[rxidx]; 1854 sc->ti_cdata.ti_rx_std_chain[rxidx] = NULL; 1855 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 1856 ifp->if_ierrors++; 1857 ti_newbuf_std(sc, sc->ti_std, m); 1858 continue; 1859 } 1860 if (ti_newbuf_std(sc, sc->ti_std, NULL) == ENOBUFS) { 1861 ifp->if_ierrors++; 1862 ti_newbuf_std(sc, sc->ti_std, m); 1863 continue; 1864 } 1865 } 1866 1867 m->m_pkthdr.len = m->m_len = cur_rx->ti_len; 1868 ifp->if_ipackets++; 1869 m->m_pkthdr.rcvif = ifp; 1870 1871 if (ifp->if_hwassist) { 1872 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED | 1873 CSUM_DATA_VALID; 1874 if ((cur_rx->ti_ip_cksum ^ 0xffff) == 0) 1875 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1876 m->m_pkthdr.csum_data = cur_rx->ti_tcp_udp_cksum; 1877 } 1878 1879 /* 1880 * If we received a packet with a vlan tag, pass it 1881 * to vlan_input() instead of ether_input(). 1882 */ 1883 if (have_tag) { 1884 VLAN_INPUT_TAG(m, vlan_tag); 1885 have_tag = vlan_tag = 0; 1886 } else { 1887 (*ifp->if_input)(ifp, m); 1888 } 1889 } 1890 1891 /* Only necessary on the Tigon 1. */ 1892 if (sc->ti_hwrev == TI_HWREV_TIGON) 1893 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 1894 sc->ti_rx_saved_considx); 1895 1896 TI_UPDATE_STDPROD(sc, sc->ti_std); 1897 TI_UPDATE_MINIPROD(sc, sc->ti_mini); 1898 TI_UPDATE_JUMBOPROD(sc, sc->ti_jumbo); 1899 1900 return; 1901 } 1902 1903 static void ti_txeof(sc) 1904 struct ti_softc *sc; 1905 { 1906 struct ti_tx_desc *cur_tx = NULL; 1907 struct ifnet *ifp; 1908 1909 ifp = &sc->arpcom.ac_if; 1910 1911 /* 1912 * Go through our tx ring and free mbufs for those 1913 * frames that have been sent. 1914 */ 1915 while (sc->ti_tx_saved_considx != sc->ti_tx_considx.ti_idx) { 1916 u_int32_t idx = 0; 1917 1918 idx = sc->ti_tx_saved_considx; 1919 if (sc->ti_hwrev == TI_HWREV_TIGON) { 1920 if (idx > 383) 1921 CSR_WRITE_4(sc, TI_WINBASE, 1922 TI_TX_RING_BASE + 6144); 1923 else if (idx > 255) 1924 CSR_WRITE_4(sc, TI_WINBASE, 1925 TI_TX_RING_BASE + 4096); 1926 else if (idx > 127) 1927 CSR_WRITE_4(sc, TI_WINBASE, 1928 TI_TX_RING_BASE + 2048); 1929 else 1930 CSR_WRITE_4(sc, TI_WINBASE, 1931 TI_TX_RING_BASE); 1932 cur_tx = &sc->ti_rdata->ti_tx_ring_nic[idx % 128]; 1933 } else 1934 cur_tx = &sc->ti_rdata->ti_tx_ring[idx]; 1935 if (cur_tx->ti_flags & TI_BDFLAG_END) 1936 ifp->if_opackets++; 1937 if (sc->ti_cdata.ti_tx_chain[idx] != NULL) { 1938 m_freem(sc->ti_cdata.ti_tx_chain[idx]); 1939 sc->ti_cdata.ti_tx_chain[idx] = NULL; 1940 } 1941 sc->ti_txcnt--; 1942 TI_INC(sc->ti_tx_saved_considx, TI_TX_RING_CNT); 1943 ifp->if_timer = 0; 1944 } 1945 1946 if (cur_tx != NULL) 1947 ifp->if_flags &= ~IFF_OACTIVE; 1948 1949 return; 1950 } 1951 1952 static void ti_intr(xsc) 1953 void *xsc; 1954 { 1955 struct ti_softc *sc; 1956 struct ifnet *ifp; 1957 1958 sc = xsc; 1959 ifp = &sc->arpcom.ac_if; 1960 1961 #ifdef notdef 1962 /* Avoid this for now -- checking this register is expensive. */ 1963 /* Make sure this is really our interrupt. */ 1964 if (!(CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_INTSTATE)) 1965 return; 1966 #endif 1967 1968 /* Ack interrupt and stop others from occuring. */ 1969 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 1970 1971 if (ifp->if_flags & IFF_RUNNING) { 1972 /* Check RX return ring producer/consumer */ 1973 ti_rxeof(sc); 1974 1975 /* Check TX ring producer/consumer */ 1976 ti_txeof(sc); 1977 } 1978 1979 ti_handle_events(sc); 1980 1981 /* Re-enable interrupts. */ 1982 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 1983 1984 if (ifp->if_flags & IFF_RUNNING && ifp->if_snd.ifq_head != NULL) 1985 ti_start(ifp); 1986 1987 return; 1988 } 1989 1990 static void ti_stats_update(sc) 1991 struct ti_softc *sc; 1992 { 1993 struct ifnet *ifp; 1994 1995 ifp = &sc->arpcom.ac_if; 1996 1997 ifp->if_collisions += 1998 (sc->ti_rdata->ti_info.ti_stats.dot3StatsSingleCollisionFrames + 1999 sc->ti_rdata->ti_info.ti_stats.dot3StatsMultipleCollisionFrames + 2000 sc->ti_rdata->ti_info.ti_stats.dot3StatsExcessiveCollisions + 2001 sc->ti_rdata->ti_info.ti_stats.dot3StatsLateCollisions) - 2002 ifp->if_collisions; 2003 2004 return; 2005 } 2006 2007 /* 2008 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 2009 * pointers to descriptors. 2010 */ 2011 static int ti_encap(sc, m_head, txidx) 2012 struct ti_softc *sc; 2013 struct mbuf *m_head; 2014 u_int32_t *txidx; 2015 { 2016 struct ti_tx_desc *f = NULL; 2017 struct mbuf *m; 2018 u_int32_t frag, cur, cnt = 0; 2019 u_int16_t csum_flags = 0; 2020 struct ifvlan *ifv = NULL; 2021 2022 if ((m_head->m_flags & (M_PROTO1|M_PKTHDR)) == (M_PROTO1|M_PKTHDR) && 2023 m_head->m_pkthdr.rcvif != NULL && 2024 m_head->m_pkthdr.rcvif->if_type == IFT_L2VLAN) 2025 ifv = m_head->m_pkthdr.rcvif->if_softc; 2026 2027 m = m_head; 2028 cur = frag = *txidx; 2029 2030 if (m_head->m_pkthdr.csum_flags) { 2031 if (m_head->m_pkthdr.csum_flags & CSUM_IP) 2032 csum_flags |= TI_BDFLAG_IP_CKSUM; 2033 if (m_head->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) 2034 csum_flags |= TI_BDFLAG_TCP_UDP_CKSUM; 2035 if (m_head->m_flags & M_LASTFRAG) 2036 csum_flags |= TI_BDFLAG_IP_FRAG_END; 2037 else if (m_head->m_flags & M_FRAG) 2038 csum_flags |= TI_BDFLAG_IP_FRAG; 2039 } 2040 /* 2041 * Start packing the mbufs in this chain into 2042 * the fragment pointers. Stop when we run out 2043 * of fragments or hit the end of the mbuf chain. 2044 */ 2045 for (m = m_head; m != NULL; m = m->m_next) { 2046 if (m->m_len != 0) { 2047 if (sc->ti_hwrev == TI_HWREV_TIGON) { 2048 if (frag > 383) 2049 CSR_WRITE_4(sc, TI_WINBASE, 2050 TI_TX_RING_BASE + 6144); 2051 else if (frag > 255) 2052 CSR_WRITE_4(sc, TI_WINBASE, 2053 TI_TX_RING_BASE + 4096); 2054 else if (frag > 127) 2055 CSR_WRITE_4(sc, TI_WINBASE, 2056 TI_TX_RING_BASE + 2048); 2057 else 2058 CSR_WRITE_4(sc, TI_WINBASE, 2059 TI_TX_RING_BASE); 2060 f = &sc->ti_rdata->ti_tx_ring_nic[frag % 128]; 2061 } else 2062 f = &sc->ti_rdata->ti_tx_ring[frag]; 2063 if (sc->ti_cdata.ti_tx_chain[frag] != NULL) 2064 break; 2065 TI_HOSTADDR(f->ti_addr) = vtophys(mtod(m, vm_offset_t)); 2066 f->ti_len = m->m_len; 2067 f->ti_flags = csum_flags; 2068 2069 if (ifv != NULL) { 2070 f->ti_flags |= TI_BDFLAG_VLAN_TAG; 2071 f->ti_vlan_tag = ifv->ifv_tag & 0xfff; 2072 } else { 2073 f->ti_vlan_tag = 0; 2074 } 2075 2076 /* 2077 * Sanity check: avoid coming within 16 descriptors 2078 * of the end of the ring. 2079 */ 2080 if ((TI_TX_RING_CNT - (sc->ti_txcnt + cnt)) < 16) 2081 return(ENOBUFS); 2082 cur = frag; 2083 TI_INC(frag, TI_TX_RING_CNT); 2084 cnt++; 2085 } 2086 } 2087 2088 if (m != NULL) 2089 return(ENOBUFS); 2090 2091 if (frag == sc->ti_tx_saved_considx) 2092 return(ENOBUFS); 2093 2094 if (sc->ti_hwrev == TI_HWREV_TIGON) 2095 sc->ti_rdata->ti_tx_ring_nic[cur % 128].ti_flags |= 2096 TI_BDFLAG_END; 2097 else 2098 sc->ti_rdata->ti_tx_ring[cur].ti_flags |= TI_BDFLAG_END; 2099 sc->ti_cdata.ti_tx_chain[cur] = m_head; 2100 sc->ti_txcnt += cnt; 2101 2102 *txidx = frag; 2103 2104 return(0); 2105 } 2106 2107 /* 2108 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 2109 * to the mbuf data regions directly in the transmit descriptors. 2110 */ 2111 static void ti_start(ifp) 2112 struct ifnet *ifp; 2113 { 2114 struct ti_softc *sc; 2115 struct mbuf *m_head = NULL; 2116 u_int32_t prodidx = 0; 2117 2118 sc = ifp->if_softc; 2119 2120 prodidx = CSR_READ_4(sc, TI_MB_SENDPROD_IDX); 2121 2122 while(sc->ti_cdata.ti_tx_chain[prodidx] == NULL) { 2123 IF_DEQUEUE(&ifp->if_snd, m_head); 2124 if (m_head == NULL) 2125 break; 2126 2127 /* 2128 * XXX 2129 * safety overkill. If this is a fragmented packet chain 2130 * with delayed TCP/UDP checksums, then only encapsulate 2131 * it if we have enough descriptors to handle the entire 2132 * chain at once. 2133 * (paranoia -- may not actually be needed) 2134 */ 2135 if (m_head->m_flags & M_FIRSTFRAG && 2136 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) { 2137 if ((TI_TX_RING_CNT - sc->ti_txcnt) < 2138 m_head->m_pkthdr.csum_data + 16) { 2139 IF_PREPEND(&ifp->if_snd, m_head); 2140 ifp->if_flags |= IFF_OACTIVE; 2141 break; 2142 } 2143 } 2144 2145 /* 2146 * Pack the data into the transmit ring. If we 2147 * don't have room, set the OACTIVE flag and wait 2148 * for the NIC to drain the ring. 2149 */ 2150 if (ti_encap(sc, m_head, &prodidx)) { 2151 IF_PREPEND(&ifp->if_snd, m_head); 2152 ifp->if_flags |= IFF_OACTIVE; 2153 break; 2154 } 2155 2156 /* 2157 * If there's a BPF listener, bounce a copy of this frame 2158 * to him. 2159 */ 2160 if (ifp->if_bpf) 2161 bpf_mtap(ifp, m_head); 2162 } 2163 2164 /* Transmit */ 2165 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, prodidx); 2166 2167 /* 2168 * Set a timeout in case the chip goes out to lunch. 2169 */ 2170 ifp->if_timer = 5; 2171 2172 return; 2173 } 2174 2175 static void ti_init(xsc) 2176 void *xsc; 2177 { 2178 struct ti_softc *sc = xsc; 2179 int s; 2180 2181 s = splimp(); 2182 2183 /* Cancel pending I/O and flush buffers. */ 2184 ti_stop(sc); 2185 2186 /* Init the gen info block, ring control blocks and firmware. */ 2187 if (ti_gibinit(sc)) { 2188 printf("ti%d: initialization failure\n", sc->ti_unit); 2189 splx(s); 2190 return; 2191 } 2192 2193 splx(s); 2194 2195 return; 2196 } 2197 2198 static void ti_init2(sc) 2199 struct ti_softc *sc; 2200 { 2201 struct ti_cmd_desc cmd; 2202 struct ifnet *ifp; 2203 u_int16_t *m; 2204 struct ifmedia *ifm; 2205 int tmp; 2206 2207 ifp = &sc->arpcom.ac_if; 2208 2209 /* Specify MTU and interface index. */ 2210 CSR_WRITE_4(sc, TI_GCR_IFINDEX, ifp->if_dunit); 2211 CSR_WRITE_4(sc, TI_GCR_IFMTU, ifp->if_mtu + 2212 ETHER_HDR_LEN + ETHER_CRC_LEN); 2213 TI_DO_CMD(TI_CMD_UPDATE_GENCOM, 0, 0); 2214 2215 /* Load our MAC address. */ 2216 m = (u_int16_t *)&sc->arpcom.ac_enaddr[0]; 2217 CSR_WRITE_4(sc, TI_GCR_PAR0, htons(m[0])); 2218 CSR_WRITE_4(sc, TI_GCR_PAR1, (htons(m[1]) << 16) | htons(m[2])); 2219 TI_DO_CMD(TI_CMD_SET_MAC_ADDR, 0, 0); 2220 2221 /* Enable or disable promiscuous mode as needed. */ 2222 if (ifp->if_flags & IFF_PROMISC) { 2223 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_ENB, 0); 2224 } else { 2225 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_DIS, 0); 2226 } 2227 2228 /* Program multicast filter. */ 2229 ti_setmulti(sc); 2230 2231 /* 2232 * If this is a Tigon 1, we should tell the 2233 * firmware to use software packet filtering. 2234 */ 2235 if (sc->ti_hwrev == TI_HWREV_TIGON) { 2236 TI_DO_CMD(TI_CMD_FDR_FILTERING, TI_CMD_CODE_FILT_ENB, 0); 2237 } 2238 2239 /* Init RX ring. */ 2240 ti_init_rx_ring_std(sc); 2241 2242 /* Init jumbo RX ring. */ 2243 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 2244 ti_init_rx_ring_jumbo(sc); 2245 2246 /* 2247 * If this is a Tigon 2, we can also configure the 2248 * mini ring. 2249 */ 2250 if (sc->ti_hwrev == TI_HWREV_TIGON_II) 2251 ti_init_rx_ring_mini(sc); 2252 2253 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 0); 2254 sc->ti_rx_saved_considx = 0; 2255 2256 /* Init TX ring. */ 2257 ti_init_tx_ring(sc); 2258 2259 /* Tell firmware we're alive. */ 2260 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_UP, 0); 2261 2262 /* Enable host interrupts. */ 2263 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 2264 2265 ifp->if_flags |= IFF_RUNNING; 2266 ifp->if_flags &= ~IFF_OACTIVE; 2267 2268 /* 2269 * Make sure to set media properly. We have to do this 2270 * here since we have to issue commands in order to set 2271 * the link negotiation and we can't issue commands until 2272 * the firmware is running. 2273 */ 2274 ifm = &sc->ifmedia; 2275 tmp = ifm->ifm_media; 2276 ifm->ifm_media = ifm->ifm_cur->ifm_media; 2277 ti_ifmedia_upd(ifp); 2278 ifm->ifm_media = tmp; 2279 2280 return; 2281 } 2282 2283 /* 2284 * Set media options. 2285 */ 2286 static int ti_ifmedia_upd(ifp) 2287 struct ifnet *ifp; 2288 { 2289 struct ti_softc *sc; 2290 struct ifmedia *ifm; 2291 struct ti_cmd_desc cmd; 2292 2293 sc = ifp->if_softc; 2294 ifm = &sc->ifmedia; 2295 2296 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 2297 return(EINVAL); 2298 2299 switch(IFM_SUBTYPE(ifm->ifm_media)) { 2300 case IFM_AUTO: 2301 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB| 2302 TI_GLNK_FULL_DUPLEX|TI_GLNK_RX_FLOWCTL_Y| 2303 TI_GLNK_AUTONEGENB|TI_GLNK_ENB); 2304 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_100MB|TI_LNK_10MB| 2305 TI_LNK_FULL_DUPLEX|TI_LNK_HALF_DUPLEX| 2306 TI_LNK_AUTONEGENB|TI_LNK_ENB); 2307 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 2308 TI_CMD_CODE_NEGOTIATE_BOTH, 0); 2309 break; 2310 case IFM_1000_SX: 2311 case IFM_1000_TX: 2312 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB| 2313 TI_GLNK_RX_FLOWCTL_Y|TI_GLNK_ENB); 2314 CSR_WRITE_4(sc, TI_GCR_LINK, 0); 2315 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 2316 TI_SETBIT(sc, TI_GCR_GLINK, TI_GLNK_FULL_DUPLEX); 2317 } 2318 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 2319 TI_CMD_CODE_NEGOTIATE_GIGABIT, 0); 2320 break; 2321 case IFM_100_FX: 2322 case IFM_10_FL: 2323 case IFM_100_TX: 2324 case IFM_10_T: 2325 CSR_WRITE_4(sc, TI_GCR_GLINK, 0); 2326 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_ENB|TI_LNK_PREF); 2327 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_100_FX || 2328 IFM_SUBTYPE(ifm->ifm_media) == IFM_100_TX) { 2329 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_100MB); 2330 } else { 2331 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_10MB); 2332 } 2333 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 2334 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_FULL_DUPLEX); 2335 } else { 2336 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_HALF_DUPLEX); 2337 } 2338 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 2339 TI_CMD_CODE_NEGOTIATE_10_100, 0); 2340 break; 2341 } 2342 2343 return(0); 2344 } 2345 2346 /* 2347 * Report current media status. 2348 */ 2349 static void ti_ifmedia_sts(ifp, ifmr) 2350 struct ifnet *ifp; 2351 struct ifmediareq *ifmr; 2352 { 2353 struct ti_softc *sc; 2354 u_int32_t media = 0; 2355 2356 sc = ifp->if_softc; 2357 2358 ifmr->ifm_status = IFM_AVALID; 2359 ifmr->ifm_active = IFM_ETHER; 2360 2361 if (sc->ti_linkstat == TI_EV_CODE_LINK_DOWN) 2362 return; 2363 2364 ifmr->ifm_status |= IFM_ACTIVE; 2365 2366 if (sc->ti_linkstat == TI_EV_CODE_GIG_LINK_UP) { 2367 media = CSR_READ_4(sc, TI_GCR_GLINK_STAT); 2368 if (sc->ti_copper) 2369 ifmr->ifm_active |= IFM_1000_TX; 2370 else 2371 ifmr->ifm_active |= IFM_1000_SX; 2372 if (media & TI_GLNK_FULL_DUPLEX) 2373 ifmr->ifm_active |= IFM_FDX; 2374 else 2375 ifmr->ifm_active |= IFM_HDX; 2376 } else if (sc->ti_linkstat == TI_EV_CODE_LINK_UP) { 2377 media = CSR_READ_4(sc, TI_GCR_LINK_STAT); 2378 if (sc->ti_copper) { 2379 if (media & TI_LNK_100MB) 2380 ifmr->ifm_active |= IFM_100_TX; 2381 if (media & TI_LNK_10MB) 2382 ifmr->ifm_active |= IFM_10_T; 2383 } else { 2384 if (media & TI_LNK_100MB) 2385 ifmr->ifm_active |= IFM_100_FX; 2386 if (media & TI_LNK_10MB) 2387 ifmr->ifm_active |= IFM_10_FL; 2388 } 2389 if (media & TI_LNK_FULL_DUPLEX) 2390 ifmr->ifm_active |= IFM_FDX; 2391 if (media & TI_LNK_HALF_DUPLEX) 2392 ifmr->ifm_active |= IFM_HDX; 2393 } 2394 2395 return; 2396 } 2397 2398 static int ti_ioctl(ifp, command, data, cr) 2399 struct ifnet *ifp; 2400 u_long command; 2401 caddr_t data; 2402 struct ucred *cr; 2403 { 2404 struct ti_softc *sc = ifp->if_softc; 2405 struct ifreq *ifr = (struct ifreq *) data; 2406 int s, mask, error = 0; 2407 struct ti_cmd_desc cmd; 2408 2409 s = splimp(); 2410 2411 switch(command) { 2412 case SIOCSIFADDR: 2413 case SIOCGIFADDR: 2414 error = ether_ioctl(ifp, command, data); 2415 break; 2416 case SIOCSIFMTU: 2417 if (ifr->ifr_mtu > TI_JUMBO_MTU) 2418 error = EINVAL; 2419 else { 2420 ifp->if_mtu = ifr->ifr_mtu; 2421 ti_init(sc); 2422 } 2423 break; 2424 case SIOCSIFFLAGS: 2425 if (ifp->if_flags & IFF_UP) { 2426 /* 2427 * If only the state of the PROMISC flag changed, 2428 * then just use the 'set promisc mode' command 2429 * instead of reinitializing the entire NIC. Doing 2430 * a full re-init means reloading the firmware and 2431 * waiting for it to start up, which may take a 2432 * second or two. 2433 */ 2434 if (ifp->if_flags & IFF_RUNNING && 2435 ifp->if_flags & IFF_PROMISC && 2436 !(sc->ti_if_flags & IFF_PROMISC)) { 2437 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, 2438 TI_CMD_CODE_PROMISC_ENB, 0); 2439 } else if (ifp->if_flags & IFF_RUNNING && 2440 !(ifp->if_flags & IFF_PROMISC) && 2441 sc->ti_if_flags & IFF_PROMISC) { 2442 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, 2443 TI_CMD_CODE_PROMISC_DIS, 0); 2444 } else 2445 ti_init(sc); 2446 } else { 2447 if (ifp->if_flags & IFF_RUNNING) { 2448 ti_stop(sc); 2449 } 2450 } 2451 sc->ti_if_flags = ifp->if_flags; 2452 error = 0; 2453 break; 2454 case SIOCADDMULTI: 2455 case SIOCDELMULTI: 2456 if (ifp->if_flags & IFF_RUNNING) { 2457 ti_setmulti(sc); 2458 error = 0; 2459 } 2460 break; 2461 case SIOCSIFMEDIA: 2462 case SIOCGIFMEDIA: 2463 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command); 2464 break; 2465 case SIOCSIFCAP: 2466 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 2467 if (mask & IFCAP_HWCSUM) { 2468 if (IFCAP_HWCSUM & ifp->if_capenable) 2469 ifp->if_capenable &= ~IFCAP_HWCSUM; 2470 else 2471 ifp->if_capenable |= IFCAP_HWCSUM; 2472 if (ifp->if_flags & IFF_RUNNING) 2473 ti_init(sc); 2474 } 2475 error = 0; 2476 break; 2477 default: 2478 error = EINVAL; 2479 break; 2480 } 2481 2482 (void)splx(s); 2483 2484 return(error); 2485 } 2486 2487 static void ti_watchdog(ifp) 2488 struct ifnet *ifp; 2489 { 2490 struct ti_softc *sc; 2491 2492 sc = ifp->if_softc; 2493 2494 printf("ti%d: watchdog timeout -- resetting\n", sc->ti_unit); 2495 ti_stop(sc); 2496 ti_init(sc); 2497 2498 ifp->if_oerrors++; 2499 2500 return; 2501 } 2502 2503 /* 2504 * Stop the adapter and free any mbufs allocated to the 2505 * RX and TX lists. 2506 */ 2507 static void ti_stop(sc) 2508 struct ti_softc *sc; 2509 { 2510 struct ifnet *ifp; 2511 struct ti_cmd_desc cmd; 2512 2513 ifp = &sc->arpcom.ac_if; 2514 2515 /* Disable host interrupts. */ 2516 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 2517 /* 2518 * Tell firmware we're shutting down. 2519 */ 2520 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_DOWN, 0); 2521 2522 /* Halt and reinitialize. */ 2523 ti_chipinit(sc); 2524 ti_mem(sc, 0x2000, 0x100000 - 0x2000, NULL); 2525 ti_chipinit(sc); 2526 2527 /* Free the RX lists. */ 2528 ti_free_rx_ring_std(sc); 2529 2530 /* Free jumbo RX list. */ 2531 ti_free_rx_ring_jumbo(sc); 2532 2533 /* Free mini RX list. */ 2534 ti_free_rx_ring_mini(sc); 2535 2536 /* Free TX buffers. */ 2537 ti_free_tx_ring(sc); 2538 2539 sc->ti_ev_prodidx.ti_idx = 0; 2540 sc->ti_return_prodidx.ti_idx = 0; 2541 sc->ti_tx_considx.ti_idx = 0; 2542 sc->ti_tx_saved_considx = TI_TXCONS_UNSET; 2543 2544 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2545 2546 return; 2547 } 2548 2549 /* 2550 * Stop all chip I/O so that the kernel's probe routines don't 2551 * get confused by errant DMAs when rebooting. 2552 */ 2553 static void ti_shutdown(dev) 2554 device_t dev; 2555 { 2556 struct ti_softc *sc; 2557 2558 sc = device_get_softc(dev); 2559 2560 ti_chipinit(sc); 2561 2562 return; 2563 } 2564