1 /* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: src/sys/pci/if_ti.c,v 1.25.2.14 2002/02/15 04:20:20 silby Exp $ 33 * $DragonFly: src/sys/dev/netif/ti/if_ti.c,v 1.34 2005/06/14 14:19:22 joerg Exp $ 34 */ 35 36 /* 37 * Alteon Networks Tigon PCI gigabit ethernet driver for FreeBSD. 38 * Manuals, sample driver and firmware source kits are available 39 * from http://www.alteon.com/support/openkits. 40 * 41 * Written by Bill Paul <wpaul@ctr.columbia.edu> 42 * Electrical Engineering Department 43 * Columbia University, New York City 44 */ 45 46 /* 47 * The Alteon Networks Tigon chip contains an embedded R4000 CPU, 48 * gigabit MAC, dual DMA channels and a PCI interface unit. NICs 49 * using the Tigon may have anywhere from 512K to 2MB of SRAM. The 50 * Tigon supports hardware IP, TCP and UCP checksumming, multicast 51 * filtering and jumbo (9014 byte) frames. The hardware is largely 52 * controlled by firmware, which must be loaded into the NIC during 53 * initialization. 54 * 55 * The Tigon 2 contains 2 R4000 CPUs and requires a newer firmware 56 * revision, which supports new features such as extended commands, 57 * extended jumbo receive ring desciptors and a mini receive ring. 58 * 59 * Alteon Networks is to be commended for releasing such a vast amount 60 * of development material for the Tigon NIC without requiring an NDA 61 * (although they really should have done it a long time ago). With 62 * any luck, the other vendors will finally wise up and follow Alteon's 63 * stellar example. 64 * 65 * The firmware for the Tigon 1 and 2 NICs is compiled directly into 66 * this driver by #including it as a C header file. This bloats the 67 * driver somewhat, but it's the easiest method considering that the 68 * driver code and firmware code need to be kept in sync. The source 69 * for the firmware is not provided with the FreeBSD distribution since 70 * compiling it requires a GNU toolchain targeted for mips-sgi-irix5.3. 71 * 72 * The following people deserve special thanks: 73 * - Terry Murphy of 3Com, for providing a 3c985 Tigon 1 board 74 * for testing 75 * - Raymond Lee of Netgear, for providing a pair of Netgear 76 * GA620 Tigon 2 boards for testing 77 * - Ulf Zimmermann, for bringing the GA260 to my attention and 78 * convincing me to write this driver. 79 * - Andrew Gallatin for providing FreeBSD/Alpha support. 80 */ 81 82 #include <sys/param.h> 83 #include <sys/systm.h> 84 #include <sys/sockio.h> 85 #include <sys/mbuf.h> 86 #include <sys/malloc.h> 87 #include <sys/kernel.h> 88 #include <sys/socket.h> 89 #include <sys/queue.h> 90 #include <sys/thread2.h> 91 92 #include <net/if.h> 93 #include <net/ifq_var.h> 94 #include <net/if_arp.h> 95 #include <net/ethernet.h> 96 #include <net/if_dl.h> 97 #include <net/if_media.h> 98 #include <net/if_types.h> 99 #include <net/vlan/if_vlan_var.h> 100 101 #include <net/bpf.h> 102 103 #include <netinet/in_systm.h> 104 #include <netinet/in.h> 105 #include <netinet/ip.h> 106 107 #include <vm/vm.h> /* for vtophys */ 108 #include <vm/pmap.h> /* for vtophys */ 109 #include <machine/bus.h> 110 #include <machine/resource.h> 111 #include <sys/bus.h> 112 #include <sys/rman.h> 113 114 #include <bus/pci/pcireg.h> 115 #include <bus/pci/pcivar.h> 116 117 #include "if_tireg.h" 118 #include "ti_fw.h" 119 #include "ti_fw2.h" 120 121 /* 122 * Temporarily disable the checksum offload support for now. 123 * Tests with ftp.freesoftware.com show that after about 12 hours, 124 * the firmware will begin calculating completely bogus TX checksums 125 * and refuse to stop until the interface is reset. Unfortunately, 126 * there isn't enough time to fully debug this before the 4.1 127 * release, so this will need to stay off for now. 128 */ 129 #ifdef notdef 130 #define TI_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_IP_FRAGS) 131 #else 132 #define TI_CSUM_FEATURES 0 133 #endif 134 135 /* 136 * Various supported device vendors/types and their names. 137 */ 138 139 static struct ti_type ti_devs[] = { 140 { ALT_VENDORID, ALT_DEVICEID_ACENIC, 141 "Alteon AceNIC 1000baseSX Gigabit Ethernet" }, 142 { ALT_VENDORID, ALT_DEVICEID_ACENIC_COPPER, 143 "Alteon AceNIC 1000baseT Gigabit Ethernet" }, 144 { TC_VENDORID, TC_DEVICEID_3C985, 145 "3Com 3c985-SX Gigabit Ethernet" }, 146 { NG_VENDORID, NG_DEVICEID_GA620, 147 "Netgear GA620 1000baseSX Gigabit Ethernet" }, 148 { NG_VENDORID, NG_DEVICEID_GA620T, 149 "Netgear GA620 1000baseT Gigabit Ethernet" }, 150 { SGI_VENDORID, SGI_DEVICEID_TIGON, 151 "Silicon Graphics Gigabit Ethernet" }, 152 { DEC_VENDORID, DEC_DEVICEID_FARALLON_PN9000SX, 153 "Farallon PN9000SX Gigabit Ethernet" }, 154 { 0, 0, NULL } 155 }; 156 157 static int ti_probe(device_t); 158 static int ti_attach(device_t); 159 static int ti_detach(device_t); 160 static void ti_txeof(struct ti_softc *); 161 static void ti_rxeof(struct ti_softc *); 162 163 static void ti_stats_update(struct ti_softc *); 164 static int ti_encap(struct ti_softc *, struct mbuf *, uint32_t *); 165 166 static void ti_intr(void *); 167 static void ti_start(struct ifnet *); 168 static int ti_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *); 169 static void ti_init(void *); 170 static void ti_init2(struct ti_softc *); 171 static void ti_stop(struct ti_softc *); 172 static void ti_watchdog(struct ifnet *); 173 static void ti_shutdown(device_t); 174 static int ti_ifmedia_upd(struct ifnet *); 175 static void ti_ifmedia_sts(struct ifnet *, struct ifmediareq *); 176 177 static uint32_t ti_eeprom_putbyte(struct ti_softc *, int); 178 static uint8_t ti_eeprom_getbyte(struct ti_softc *, int, uint8_t *); 179 static int ti_read_eeprom(struct ti_softc *, caddr_t, int, int); 180 181 static void ti_add_mcast(struct ti_softc *, struct ether_addr *); 182 static void ti_del_mcast(struct ti_softc *, struct ether_addr *); 183 static void ti_setmulti(struct ti_softc *); 184 185 static void ti_mem(struct ti_softc *, uint32_t, uint32_t, caddr_t); 186 static void ti_loadfw(struct ti_softc *); 187 static void ti_cmd(struct ti_softc *, struct ti_cmd_desc *); 188 static void ti_cmd_ext(struct ti_softc *, struct ti_cmd_desc *, 189 caddr_t, int); 190 static void ti_handle_events(struct ti_softc *); 191 static int ti_alloc_jumbo_mem(struct ti_softc *); 192 static struct ti_jslot * 193 ti_jalloc(struct ti_softc *); 194 static void ti_jfree(void *); 195 static void ti_jref(void *); 196 static int ti_newbuf_std(struct ti_softc *, int, struct mbuf *); 197 static int ti_newbuf_mini(struct ti_softc *, int, struct mbuf *); 198 static int ti_newbuf_jumbo(struct ti_softc *, int, struct mbuf *); 199 static int ti_init_rx_ring_std(struct ti_softc *); 200 static void ti_free_rx_ring_std(struct ti_softc *); 201 static int ti_init_rx_ring_jumbo(struct ti_softc *); 202 static void ti_free_rx_ring_jumbo(struct ti_softc *); 203 static int ti_init_rx_ring_mini(struct ti_softc *); 204 static void ti_free_rx_ring_mini(struct ti_softc *); 205 static void ti_free_tx_ring(struct ti_softc *); 206 static int ti_init_tx_ring(struct ti_softc *); 207 208 static int ti_64bitslot_war(struct ti_softc *); 209 static int ti_chipinit(struct ti_softc *); 210 static int ti_gibinit(struct ti_softc *); 211 212 static device_method_t ti_methods[] = { 213 /* Device interface */ 214 DEVMETHOD(device_probe, ti_probe), 215 DEVMETHOD(device_attach, ti_attach), 216 DEVMETHOD(device_detach, ti_detach), 217 DEVMETHOD(device_shutdown, ti_shutdown), 218 { 0, 0 } 219 }; 220 221 222 static DEFINE_CLASS_0(ti, ti_driver, ti_methods, sizeof(struct ti_softc)); 223 static devclass_t ti_devclass; 224 225 DECLARE_DUMMY_MODULE(if_ti); 226 DRIVER_MODULE(if_ti, pci, ti_driver, ti_devclass, 0, 0); 227 228 /* 229 * Send an instruction or address to the EEPROM, check for ACK. 230 */ 231 static uint32_t 232 ti_eeprom_putbyte(struct ti_softc *sc, int byte) 233 { 234 int ack = 0, i; 235 236 /* 237 * Make sure we're in TX mode. 238 */ 239 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 240 241 /* 242 * Feed in each bit and stobe the clock. 243 */ 244 for (i = 0x80; i; i >>= 1) { 245 if (byte & i) 246 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); 247 else 248 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); 249 DELAY(1); 250 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 251 DELAY(1); 252 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 253 } 254 255 /* 256 * Turn off TX mode. 257 */ 258 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 259 260 /* 261 * Check for ack. 262 */ 263 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 264 ack = CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN; 265 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 266 267 return(ack); 268 } 269 270 /* 271 * Read a byte of data stored in the EEPROM at address 'addr.' 272 * We have to send two address bytes since the EEPROM can hold 273 * more than 256 bytes of data. 274 */ 275 static uint8_t 276 ti_eeprom_getbyte(struct ti_softc *sc, int addr, uint8_t *dest) 277 { 278 struct ifnet *ifp = &sc->arpcom.ac_if; 279 int i; 280 uint8_t byte = 0; 281 282 EEPROM_START; 283 284 /* 285 * Send write control code to EEPROM. 286 */ 287 if (ti_eeprom_putbyte(sc, EEPROM_CTL_WRITE)) { 288 if_printf(ifp, "failed to send write command, status: %x\n", 289 CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 290 return(1); 291 } 292 293 /* 294 * Send first byte of address of byte we want to read. 295 */ 296 if (ti_eeprom_putbyte(sc, (addr >> 8) & 0xFF)) { 297 if_printf(ifp, "failed to send address, status: %x\n", 298 CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 299 return(1); 300 } 301 /* 302 * Send second byte address of byte we want to read. 303 */ 304 if (ti_eeprom_putbyte(sc, addr & 0xFF)) { 305 if_printf(ifp, "failed to send address, status: %x\n", 306 CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 307 return(1); 308 } 309 310 EEPROM_STOP; 311 EEPROM_START; 312 /* 313 * Send read control code to EEPROM. 314 */ 315 if (ti_eeprom_putbyte(sc, EEPROM_CTL_READ)) { 316 if_printf(ifp, "failed to send read command, status: %x\n", 317 CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 318 return(1); 319 } 320 321 /* 322 * Start reading bits from EEPROM. 323 */ 324 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 325 for (i = 0x80; i; i >>= 1) { 326 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 327 DELAY(1); 328 if (CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN) 329 byte |= i; 330 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 331 DELAY(1); 332 } 333 334 EEPROM_STOP; 335 336 /* 337 * No ACK generated for read, so just return byte. 338 */ 339 340 *dest = byte; 341 342 return(0); 343 } 344 345 /* 346 * Read a sequence of bytes from the EEPROM. 347 */ 348 static int 349 ti_read_eeprom(struct ti_softc *sc, caddr_t dest, int off, int cnt) 350 { 351 int err = 0, i; 352 uint8_t byte = 0; 353 354 for (i = 0; i < cnt; i++) { 355 err = ti_eeprom_getbyte(sc, off + i, &byte); 356 if (err) 357 break; 358 *(dest + i) = byte; 359 } 360 361 return(err ? 1 : 0); 362 } 363 364 /* 365 * NIC memory access function. Can be used to either clear a section 366 * of NIC local memory or (if buf is non-NULL) copy data into it. 367 */ 368 static void 369 ti_mem(struct ti_softc *sc, uint32_t addr, uint32_t len, caddr_t buf) 370 { 371 int cnt, segptr, segsize; 372 caddr_t ti_winbase, ptr; 373 374 segptr = addr; 375 cnt = len; 376 ti_winbase = (caddr_t)(sc->ti_vhandle + TI_WINDOW); 377 ptr = buf; 378 379 while(cnt) { 380 if (cnt < TI_WINLEN) 381 segsize = cnt; 382 else 383 segsize = TI_WINLEN - (segptr % TI_WINLEN); 384 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1))); 385 if (buf == NULL) 386 bzero((char *)ti_winbase + (segptr & 387 (TI_WINLEN - 1)), segsize); 388 else { 389 bcopy((char *)ptr, (char *)ti_winbase + 390 (segptr & (TI_WINLEN - 1)), segsize); 391 ptr += segsize; 392 } 393 segptr += segsize; 394 cnt -= segsize; 395 } 396 } 397 398 /* 399 * Load firmware image into the NIC. Check that the firmware revision 400 * is acceptable and see if we want the firmware for the Tigon 1 or 401 * Tigon 2. 402 */ 403 static void 404 ti_loadfw(struct ti_softc *sc) 405 { 406 struct ifnet *ifp = &sc->arpcom.ac_if; 407 408 switch(sc->ti_hwrev) { 409 case TI_HWREV_TIGON: 410 if (tigonFwReleaseMajor != TI_FIRMWARE_MAJOR || 411 tigonFwReleaseMinor != TI_FIRMWARE_MINOR || 412 tigonFwReleaseFix != TI_FIRMWARE_FIX) { 413 if_printf(ifp, "firmware revision mismatch; want " 414 "%d.%d.%d, got %d.%d.%d\n", 415 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR, 416 TI_FIRMWARE_FIX, tigonFwReleaseMajor, 417 tigonFwReleaseMinor, tigonFwReleaseFix); 418 return; 419 } 420 ti_mem(sc, tigonFwTextAddr, tigonFwTextLen, 421 (caddr_t)tigonFwText); 422 ti_mem(sc, tigonFwDataAddr, tigonFwDataLen, 423 (caddr_t)tigonFwData); 424 ti_mem(sc, tigonFwRodataAddr, tigonFwRodataLen, 425 (caddr_t)tigonFwRodata); 426 ti_mem(sc, tigonFwBssAddr, tigonFwBssLen, NULL); 427 ti_mem(sc, tigonFwSbssAddr, tigonFwSbssLen, NULL); 428 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigonFwStartAddr); 429 break; 430 case TI_HWREV_TIGON_II: 431 if (tigon2FwReleaseMajor != TI_FIRMWARE_MAJOR || 432 tigon2FwReleaseMinor != TI_FIRMWARE_MINOR || 433 tigon2FwReleaseFix != TI_FIRMWARE_FIX) { 434 if_printf(ifp, "firmware revision mismatch; want " 435 "%d.%d.%d, got %d.%d.%d\n", 436 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR, 437 TI_FIRMWARE_FIX, tigon2FwReleaseMajor, 438 tigon2FwReleaseMinor, tigon2FwReleaseFix); 439 return; 440 } 441 ti_mem(sc, tigon2FwTextAddr, tigon2FwTextLen, 442 (caddr_t)tigon2FwText); 443 ti_mem(sc, tigon2FwDataAddr, tigon2FwDataLen, 444 (caddr_t)tigon2FwData); 445 ti_mem(sc, tigon2FwRodataAddr, tigon2FwRodataLen, 446 (caddr_t)tigon2FwRodata); 447 ti_mem(sc, tigon2FwBssAddr, tigon2FwBssLen, NULL); 448 ti_mem(sc, tigon2FwSbssAddr, tigon2FwSbssLen, NULL); 449 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigon2FwStartAddr); 450 break; 451 default: 452 if_printf(ifp, "can't load firmware: unknown hardware rev\n"); 453 break; 454 } 455 } 456 457 /* 458 * Send the NIC a command via the command ring. 459 */ 460 static void 461 ti_cmd(struct ti_softc *sc, struct ti_cmd_desc *cmd) 462 { 463 uint32_t index; 464 465 if (sc->ti_rdata->ti_cmd_ring == NULL) 466 return; 467 468 index = sc->ti_cmd_saved_prodidx; 469 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(uint32_t *)(cmd)); 470 TI_INC(index, TI_CMD_RING_CNT); 471 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index); 472 sc->ti_cmd_saved_prodidx = index; 473 } 474 475 /* 476 * Send the NIC an extended command. The 'len' parameter specifies the 477 * number of command slots to include after the initial command. 478 */ 479 static void 480 ti_cmd_ext(struct ti_softc *sc, struct ti_cmd_desc *cmd, caddr_t arg, int len) 481 { 482 uint32_t index; 483 int i; 484 485 if (sc->ti_rdata->ti_cmd_ring == NULL) 486 return; 487 488 index = sc->ti_cmd_saved_prodidx; 489 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(uint32_t *)(cmd)); 490 TI_INC(index, TI_CMD_RING_CNT); 491 for (i = 0; i < len; i++) { 492 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), 493 *(uint32_t *)(&arg[i * 4])); 494 TI_INC(index, TI_CMD_RING_CNT); 495 } 496 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index); 497 sc->ti_cmd_saved_prodidx = index; 498 } 499 500 /* 501 * Handle events that have triggered interrupts. 502 */ 503 static void 504 ti_handle_events(struct ti_softc *sc) 505 { 506 struct ifnet *ifp = &sc->arpcom.ac_if; 507 struct ti_event_desc *e; 508 509 if (sc->ti_rdata->ti_event_ring == NULL) 510 return; 511 512 while (sc->ti_ev_saved_considx != sc->ti_ev_prodidx.ti_idx) { 513 e = &sc->ti_rdata->ti_event_ring[sc->ti_ev_saved_considx]; 514 switch(e->ti_event) { 515 case TI_EV_LINKSTAT_CHANGED: 516 sc->ti_linkstat = e->ti_code; 517 if (e->ti_code == TI_EV_CODE_LINK_UP) { 518 if_printf(ifp, "10/100 link up\n"); 519 } else if (e->ti_code == TI_EV_CODE_GIG_LINK_UP) { 520 if_printf(ifp, "gigabit link up\n"); 521 } else if (e->ti_code == TI_EV_CODE_LINK_DOWN) { 522 if_printf(ifp, "link down\n"); 523 } 524 break; 525 case TI_EV_ERROR: 526 if (e->ti_code == TI_EV_CODE_ERR_INVAL_CMD) { 527 if_printf(ifp, "invalid command\n"); 528 } else if (e->ti_code == TI_EV_CODE_ERR_UNIMP_CMD) { 529 if_printf(ifp, "unknown command\n"); 530 } else if (e->ti_code == TI_EV_CODE_ERR_BADCFG) { 531 if_printf(ifp, "bad config data\n"); 532 } 533 break; 534 case TI_EV_FIRMWARE_UP: 535 ti_init2(sc); 536 break; 537 case TI_EV_STATS_UPDATED: 538 ti_stats_update(sc); 539 break; 540 case TI_EV_RESET_JUMBO_RING: 541 case TI_EV_MCAST_UPDATED: 542 /* Who cares. */ 543 break; 544 default: 545 if_printf(ifp, "unknown event: %d\n", e->ti_event); 546 break; 547 } 548 /* Advance the consumer index. */ 549 TI_INC(sc->ti_ev_saved_considx, TI_EVENT_RING_CNT); 550 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, sc->ti_ev_saved_considx); 551 } 552 } 553 554 /* 555 * Memory management for the jumbo receive ring is a pain in the 556 * butt. We need to allocate at least 9018 bytes of space per frame, 557 * _and_ it has to be contiguous (unless you use the extended 558 * jumbo descriptor format). Using malloc() all the time won't 559 * work: malloc() allocates memory in powers of two, which means we 560 * would end up wasting a considerable amount of space by allocating 561 * 9K chunks. We don't have a jumbo mbuf cluster pool. Thus, we have 562 * to do our own memory management. 563 * 564 * The driver needs to allocate a contiguous chunk of memory at boot 565 * time. We then chop this up ourselves into 9K pieces and use them 566 * as external mbuf storage. 567 * 568 * One issue here is how much memory to allocate. The jumbo ring has 569 * 256 slots in it, but at 9K per slot than can consume over 2MB of 570 * RAM. This is a bit much, especially considering we also need 571 * RAM for the standard ring and mini ring (on the Tigon 2). To 572 * save space, we only actually allocate enough memory for 64 slots 573 * by default, which works out to between 500 and 600K. This can 574 * be tuned by changing a #define in if_tireg.h. 575 */ 576 577 static int 578 ti_alloc_jumbo_mem(struct ti_softc *sc) 579 { 580 struct ti_jslot *entry; 581 caddr_t ptr; 582 int i; 583 584 /* Grab a big chunk o' storage. */ 585 sc->ti_cdata.ti_jumbo_buf = contigmalloc(TI_JMEM, M_DEVBUF, 586 M_WAITOK, 0, 0xffffffff, PAGE_SIZE, 0); 587 588 if (sc->ti_cdata.ti_jumbo_buf == NULL) { 589 if_printf(&sc->arpcom.ac_if, "no memory for jumbo buffers!\n"); 590 return(ENOBUFS); 591 } 592 593 SLIST_INIT(&sc->ti_jfree_listhead); 594 595 /* 596 * Now divide it up into 9K pieces and save the addresses 597 * in an array. Note that we play an evil trick here by using 598 * the first few bytes in the buffer to hold the the address 599 * of the softc structure for this interface. This is because 600 * ti_jfree() needs it, but it is called by the mbuf management 601 * code which will not pass it to us explicitly. 602 */ 603 ptr = sc->ti_cdata.ti_jumbo_buf; 604 for (i = 0; i < TI_JSLOTS; i++) { 605 entry = &sc->ti_cdata.ti_jslots[i]; 606 entry->ti_sc = sc; 607 entry->ti_buf = ptr; 608 entry->ti_inuse = 0; 609 entry->ti_slot = i; 610 SLIST_INSERT_HEAD(&sc->ti_jfree_listhead, entry, jslot_link); 611 ptr += TI_JLEN; 612 } 613 614 return(0); 615 } 616 617 /* 618 * Allocate a jumbo buffer. 619 */ 620 static struct ti_jslot * 621 ti_jalloc(struct ti_softc *sc) 622 { 623 struct ti_jslot *entry; 624 625 entry = SLIST_FIRST(&sc->ti_jfree_listhead); 626 627 if (entry == NULL) { 628 if_printf(&sc->arpcom.ac_if, "no free jumbo buffers\n"); 629 return(NULL); 630 } 631 632 SLIST_REMOVE_HEAD(&sc->ti_jfree_listhead, jslot_link); 633 entry->ti_inuse = 1; 634 return(entry); 635 } 636 637 /* 638 * Adjust usage count on a jumbo buffer. In general this doesn't 639 * get used much because our jumbo buffers don't get passed around 640 * too much, but it's implemented for correctness. 641 */ 642 static void 643 ti_jref(void *arg) 644 { 645 struct ti_jslot *entry = (struct ti_jslot *)arg; 646 struct ti_softc *sc = entry->ti_sc; 647 648 if (sc == NULL) 649 panic("ti_jref: can't find softc pointer!"); 650 651 if (&sc->ti_cdata.ti_jslots[entry->ti_slot] != entry) 652 panic("ti_jref: asked to reference buffer " 653 "that we don't manage!"); 654 if (entry->ti_inuse == 0) 655 panic("ti_jref: buffer already free!"); 656 entry->ti_inuse++; 657 } 658 659 /* 660 * Release a jumbo buffer. 661 */ 662 static void 663 ti_jfree(void *arg) 664 { 665 struct ti_jslot *entry = (struct ti_jslot *)arg; 666 struct ti_softc *sc = entry->ti_sc; 667 668 if (sc == NULL) 669 panic("ti_jref: can't find softc pointer!"); 670 671 if (&sc->ti_cdata.ti_jslots[entry->ti_slot] != entry) 672 panic("ti_jref: asked to reference buffer " 673 "that we don't manage!"); 674 if (entry->ti_inuse == 0) 675 panic("ti_jref: buffer already free!"); 676 if (--entry->ti_inuse == 0) 677 SLIST_INSERT_HEAD(&sc->ti_jfree_listhead, entry, jslot_link); 678 } 679 680 681 /* 682 * Intialize a standard receive ring descriptor. 683 */ 684 static int 685 ti_newbuf_std(struct ti_softc *sc, int i, struct mbuf *m) 686 { 687 struct mbuf *m_new; 688 struct ti_rx_desc *r; 689 690 if (m == NULL) { 691 m_new = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR); 692 if (m_new == NULL) 693 return (ENOBUFS); 694 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 695 } else { 696 m_new = m; 697 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 698 m_new->m_data = m_new->m_ext.ext_buf; 699 } 700 701 702 m_adj(m_new, ETHER_ALIGN); 703 sc->ti_cdata.ti_rx_std_chain[i] = m_new; 704 r = &sc->ti_rdata->ti_rx_std_ring[i]; 705 TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t)); 706 r->ti_type = TI_BDTYPE_RECV_BD; 707 r->ti_flags = 0; 708 if (sc->arpcom.ac_if.if_hwassist) 709 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM; 710 r->ti_len = m_new->m_len; 711 r->ti_idx = i; 712 713 return(0); 714 } 715 716 /* 717 * Intialize a mini receive ring descriptor. This only applies to 718 * the Tigon 2. 719 */ 720 static int 721 ti_newbuf_mini(struct ti_softc *sc, int i, struct mbuf *m) 722 { 723 struct mbuf *m_new; 724 struct ti_rx_desc *r; 725 726 if (m == NULL) { 727 MGETHDR(m_new, MB_DONTWAIT, MT_DATA); 728 if (m_new == NULL) { 729 return(ENOBUFS); 730 } 731 m_new->m_len = m_new->m_pkthdr.len = MHLEN; 732 } else { 733 m_new = m; 734 m_new->m_data = m_new->m_pktdat; 735 m_new->m_len = m_new->m_pkthdr.len = MHLEN; 736 } 737 738 m_adj(m_new, ETHER_ALIGN); 739 r = &sc->ti_rdata->ti_rx_mini_ring[i]; 740 sc->ti_cdata.ti_rx_mini_chain[i] = m_new; 741 TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t)); 742 r->ti_type = TI_BDTYPE_RECV_BD; 743 r->ti_flags = TI_BDFLAG_MINI_RING; 744 if (sc->arpcom.ac_if.if_hwassist) 745 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM; 746 r->ti_len = m_new->m_len; 747 r->ti_idx = i; 748 749 return(0); 750 } 751 752 /* 753 * Initialize a jumbo receive ring descriptor. This allocates 754 * a jumbo buffer from the pool managed internally by the driver. 755 */ 756 static int 757 ti_newbuf_jumbo(struct ti_softc *sc, int i, struct mbuf *m) 758 { 759 struct mbuf *m_new; 760 struct ti_rx_desc *r; 761 struct ti_jslot *buf; 762 763 if (m == NULL) { 764 /* Allocate the mbuf. */ 765 MGETHDR(m_new, MB_DONTWAIT, MT_DATA); 766 if (m_new == NULL) { 767 return(ENOBUFS); 768 } 769 770 /* Allocate the jumbo buffer */ 771 buf = ti_jalloc(sc); 772 if (buf == NULL) { 773 m_freem(m_new); 774 if_printf(&sc->arpcom.ac_if, "jumbo allocation failed " 775 "-- packet dropped!\n"); 776 return(ENOBUFS); 777 } 778 779 /* Attach the buffer to the mbuf. */ 780 m_new->m_ext.ext_arg = buf; 781 m_new->m_ext.ext_free = ti_jfree; 782 m_new->m_ext.ext_ref = ti_jref; 783 m_new->m_ext.ext_size = TI_JUMBO_FRAMELEN; 784 785 m_new->m_data = m_new->m_ext.ext_buf; 786 m_new->m_flags |= M_EXT; 787 m_new->m_len = m_new->m_pkthdr.len = m_new->m_ext.ext_size; 788 } else { 789 m_new = m; 790 m_new->m_data = m_new->m_ext.ext_buf; 791 m_new->m_ext.ext_size = TI_JUMBO_FRAMELEN; 792 } 793 794 m_adj(m_new, ETHER_ALIGN); 795 /* Set up the descriptor. */ 796 r = &sc->ti_rdata->ti_rx_jumbo_ring[i]; 797 sc->ti_cdata.ti_rx_jumbo_chain[i] = m_new; 798 TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t)); 799 r->ti_type = TI_BDTYPE_RECV_JUMBO_BD; 800 r->ti_flags = TI_BDFLAG_JUMBO_RING; 801 if (sc->arpcom.ac_if.if_hwassist) 802 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM; 803 r->ti_len = m_new->m_len; 804 r->ti_idx = i; 805 806 return(0); 807 } 808 809 /* 810 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 811 * that's 1MB or memory, which is a lot. For now, we fill only the first 812 * 256 ring entries and hope that our CPU is fast enough to keep up with 813 * the NIC. 814 */ 815 static int 816 ti_init_rx_ring_std(struct ti_softc *sc) 817 { 818 int i; 819 struct ti_cmd_desc cmd; 820 821 for (i = 0; i < TI_SSLOTS; i++) { 822 if (ti_newbuf_std(sc, i, NULL) == ENOBUFS) 823 return(ENOBUFS); 824 }; 825 826 TI_UPDATE_STDPROD(sc, i - 1); 827 sc->ti_std = i - 1; 828 829 return(0); 830 } 831 832 static void 833 ti_free_rx_ring_std(struct ti_softc *sc) 834 { 835 int i; 836 837 for (i = 0; i < TI_STD_RX_RING_CNT; i++) { 838 if (sc->ti_cdata.ti_rx_std_chain[i] != NULL) { 839 m_freem(sc->ti_cdata.ti_rx_std_chain[i]); 840 sc->ti_cdata.ti_rx_std_chain[i] = NULL; 841 } 842 bzero(&sc->ti_rdata->ti_rx_std_ring[i], 843 sizeof(struct ti_rx_desc)); 844 } 845 } 846 847 static int 848 ti_init_rx_ring_jumbo(struct ti_softc *sc) 849 { 850 int i; 851 struct ti_cmd_desc cmd; 852 853 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) { 854 if (ti_newbuf_jumbo(sc, i, NULL) == ENOBUFS) 855 return(ENOBUFS); 856 } 857 858 TI_UPDATE_JUMBOPROD(sc, i - 1); 859 sc->ti_jumbo = i - 1; 860 861 return(0); 862 } 863 864 static void 865 ti_free_rx_ring_jumbo(struct ti_softc *sc) 866 { 867 int i; 868 869 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) { 870 if (sc->ti_cdata.ti_rx_jumbo_chain[i] != NULL) { 871 m_freem(sc->ti_cdata.ti_rx_jumbo_chain[i]); 872 sc->ti_cdata.ti_rx_jumbo_chain[i] = NULL; 873 } 874 bzero(&sc->ti_rdata->ti_rx_jumbo_ring[i], 875 sizeof(struct ti_rx_desc)); 876 } 877 } 878 879 static int 880 ti_init_rx_ring_mini(struct ti_softc *sc) 881 { 882 int i; 883 884 for (i = 0; i < TI_MSLOTS; i++) { 885 if (ti_newbuf_mini(sc, i, NULL) == ENOBUFS) 886 return(ENOBUFS); 887 } 888 889 TI_UPDATE_MINIPROD(sc, i - 1); 890 sc->ti_mini = i - 1; 891 892 return(0); 893 } 894 895 static void 896 ti_free_rx_ring_mini(struct ti_softc *sc) 897 { 898 int i; 899 900 for (i = 0; i < TI_MINI_RX_RING_CNT; i++) { 901 if (sc->ti_cdata.ti_rx_mini_chain[i] != NULL) { 902 m_freem(sc->ti_cdata.ti_rx_mini_chain[i]); 903 sc->ti_cdata.ti_rx_mini_chain[i] = NULL; 904 } 905 bzero(&sc->ti_rdata->ti_rx_mini_ring[i], 906 sizeof(struct ti_rx_desc)); 907 } 908 } 909 910 static void 911 ti_free_tx_ring(struct ti_softc *sc) 912 { 913 int i; 914 915 if (sc->ti_rdata->ti_tx_ring == NULL) 916 return; 917 918 for (i = 0; i < TI_TX_RING_CNT; i++) { 919 if (sc->ti_cdata.ti_tx_chain[i] != NULL) { 920 m_freem(sc->ti_cdata.ti_tx_chain[i]); 921 sc->ti_cdata.ti_tx_chain[i] = NULL; 922 } 923 bzero(&sc->ti_rdata->ti_tx_ring[i], 924 sizeof(struct ti_tx_desc)); 925 } 926 } 927 928 static int 929 ti_init_tx_ring(struct ti_softc *sc) 930 { 931 sc->ti_txcnt = 0; 932 sc->ti_tx_saved_considx = 0; 933 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, 0); 934 return(0); 935 } 936 937 /* 938 * The Tigon 2 firmware has a new way to add/delete multicast addresses, 939 * but we have to support the old way too so that Tigon 1 cards will 940 * work. 941 */ 942 static void 943 ti_add_mcast(struct ti_softc *sc, struct ether_addr *addr) 944 { 945 struct ti_cmd_desc cmd; 946 uint16_t *m; 947 uint32_t ext[2] = {0, 0}; 948 949 m = (uint16_t *)&addr->octet[0]; 950 951 switch(sc->ti_hwrev) { 952 case TI_HWREV_TIGON: 953 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0])); 954 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2])); 955 TI_DO_CMD(TI_CMD_ADD_MCAST_ADDR, 0, 0); 956 break; 957 case TI_HWREV_TIGON_II: 958 ext[0] = htons(m[0]); 959 ext[1] = (htons(m[1]) << 16) | htons(m[2]); 960 TI_DO_CMD_EXT(TI_CMD_EXT_ADD_MCAST, 0, 0, (caddr_t)&ext, 2); 961 break; 962 default: 963 if_printf(&sc->arpcom.ac_if, "unknown hwrev\n"); 964 break; 965 } 966 } 967 968 static void 969 ti_del_mcast(struct ti_softc *sc, struct ether_addr *addr) 970 { 971 struct ti_cmd_desc cmd; 972 uint16_t *m; 973 uint32_t ext[2] = {0, 0}; 974 975 m = (uint16_t *)&addr->octet[0]; 976 977 switch(sc->ti_hwrev) { 978 case TI_HWREV_TIGON: 979 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0])); 980 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2])); 981 TI_DO_CMD(TI_CMD_DEL_MCAST_ADDR, 0, 0); 982 break; 983 case TI_HWREV_TIGON_II: 984 ext[0] = htons(m[0]); 985 ext[1] = (htons(m[1]) << 16) | htons(m[2]); 986 TI_DO_CMD_EXT(TI_CMD_EXT_DEL_MCAST, 0, 0, (caddr_t)&ext, 2); 987 break; 988 default: 989 if_printf(&sc->arpcom.ac_if, "unknown hwrev\n"); 990 break; 991 } 992 } 993 994 /* 995 * Configure the Tigon's multicast address filter. 996 * 997 * The actual multicast table management is a bit of a pain, thanks to 998 * slight brain damage on the part of both Alteon and us. With our 999 * multicast code, we are only alerted when the multicast address table 1000 * changes and at that point we only have the current list of addresses: 1001 * we only know the current state, not the previous state, so we don't 1002 * actually know what addresses were removed or added. The firmware has 1003 * state, but we can't get our grubby mits on it, and there is no 'delete 1004 * all multicast addresses' command. Hence, we have to maintain our own 1005 * state so we know what addresses have been programmed into the NIC at 1006 * any given time. 1007 */ 1008 static void 1009 ti_setmulti(struct ti_softc *sc) 1010 { 1011 struct ifnet *ifp = &sc->arpcom.ac_if; 1012 struct ifmultiaddr *ifma; 1013 struct ti_cmd_desc cmd; 1014 struct ti_mc_entry *mc; 1015 uint32_t intrs; 1016 1017 if (ifp->if_flags & IFF_ALLMULTI) { 1018 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_ENB, 0); 1019 return; 1020 } 1021 1022 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_DIS, 0); 1023 1024 /* Disable interrupts. */ 1025 intrs = CSR_READ_4(sc, TI_MB_HOSTINTR); 1026 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 1027 1028 /* First, zot all the existing filters. */ 1029 while (sc->ti_mc_listhead.slh_first != NULL) { 1030 mc = sc->ti_mc_listhead.slh_first; 1031 ti_del_mcast(sc, &mc->mc_addr); 1032 SLIST_REMOVE_HEAD(&sc->ti_mc_listhead, mc_entries); 1033 free(mc, M_DEVBUF); 1034 } 1035 1036 /* Now program new ones. */ 1037 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1038 if (ifma->ifma_addr->sa_family != AF_LINK) 1039 continue; 1040 mc = malloc(sizeof(struct ti_mc_entry), M_DEVBUF, M_INTWAIT); 1041 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 1042 &mc->mc_addr, ETHER_ADDR_LEN); 1043 SLIST_INSERT_HEAD(&sc->ti_mc_listhead, mc, mc_entries); 1044 ti_add_mcast(sc, &mc->mc_addr); 1045 } 1046 1047 /* Re-enable interrupts. */ 1048 CSR_WRITE_4(sc, TI_MB_HOSTINTR, intrs); 1049 } 1050 1051 /* 1052 * Check to see if the BIOS has configured us for a 64 bit slot when 1053 * we aren't actually in one. If we detect this condition, we can work 1054 * around it on the Tigon 2 by setting a bit in the PCI state register, 1055 * but for the Tigon 1 we must give up and abort the interface attach. 1056 */ 1057 static int 1058 ti_64bitslot_war(struct ti_softc *sc) 1059 { 1060 if ((CSR_READ_4(sc, TI_PCI_STATE) & TI_PCISTATE_32BIT_BUS) == 0) { 1061 CSR_WRITE_4(sc, 0x600, 0); 1062 CSR_WRITE_4(sc, 0x604, 0); 1063 CSR_WRITE_4(sc, 0x600, 0x5555AAAA); 1064 if (CSR_READ_4(sc, 0x604) == 0x5555AAAA) { 1065 if (sc->ti_hwrev == TI_HWREV_TIGON) 1066 return(EINVAL); 1067 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_32BIT_BUS); 1068 return(0); 1069 } 1070 } 1071 1072 return(0); 1073 } 1074 1075 /* 1076 * Do endian, PCI and DMA initialization. Also check the on-board ROM 1077 * self-test results. 1078 */ 1079 static int 1080 ti_chipinit(struct ti_softc *sc) 1081 { 1082 struct ifnet *ifp = &sc->arpcom.ac_if; 1083 uint32_t cacheline; 1084 uint32_t pci_writemax = 0; 1085 1086 /* Initialize link to down state. */ 1087 sc->ti_linkstat = TI_EV_CODE_LINK_DOWN; 1088 1089 if (ifp->if_capenable & IFCAP_HWCSUM) 1090 ifp->if_hwassist = TI_CSUM_FEATURES; 1091 else 1092 ifp->if_hwassist = 0; 1093 1094 /* Set endianness before we access any non-PCI registers. */ 1095 #if BYTE_ORDER == BIG_ENDIAN 1096 CSR_WRITE_4(sc, TI_MISC_HOST_CTL, 1097 TI_MHC_BIGENDIAN_INIT | (TI_MHC_BIGENDIAN_INIT << 24)); 1098 #else 1099 CSR_WRITE_4(sc, TI_MISC_HOST_CTL, 1100 TI_MHC_LITTLEENDIAN_INIT | (TI_MHC_LITTLEENDIAN_INIT << 24)); 1101 #endif 1102 1103 /* Check the ROM failed bit to see if self-tests passed. */ 1104 if (CSR_READ_4(sc, TI_CPU_STATE) & TI_CPUSTATE_ROMFAIL) { 1105 if_printf(ifp, "board self-diagnostics failed!\n"); 1106 return(ENODEV); 1107 } 1108 1109 /* Halt the CPU. */ 1110 TI_SETBIT(sc, TI_CPU_STATE, TI_CPUSTATE_HALT); 1111 1112 /* Figure out the hardware revision. */ 1113 switch(CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_CHIP_REV_MASK) { 1114 case TI_REV_TIGON_I: 1115 sc->ti_hwrev = TI_HWREV_TIGON; 1116 break; 1117 case TI_REV_TIGON_II: 1118 sc->ti_hwrev = TI_HWREV_TIGON_II; 1119 break; 1120 default: 1121 if_printf(ifp, "unsupported chip revision\n"); 1122 return(ENODEV); 1123 } 1124 1125 /* Do special setup for Tigon 2. */ 1126 if (sc->ti_hwrev == TI_HWREV_TIGON_II) { 1127 TI_SETBIT(sc, TI_CPU_CTL_B, TI_CPUSTATE_HALT); 1128 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_SRAM_BANK_512K); 1129 TI_SETBIT(sc, TI_MISC_CONF, TI_MCR_SRAM_SYNCHRONOUS); 1130 } 1131 1132 /* Set up the PCI state register. */ 1133 CSR_WRITE_4(sc, TI_PCI_STATE, TI_PCI_READ_CMD|TI_PCI_WRITE_CMD); 1134 if (sc->ti_hwrev == TI_HWREV_TIGON_II) { 1135 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_USE_MEM_RD_MULT); 1136 } 1137 1138 /* Clear the read/write max DMA parameters. */ 1139 TI_CLRBIT(sc, TI_PCI_STATE, (TI_PCISTATE_WRITE_MAXDMA| 1140 TI_PCISTATE_READ_MAXDMA)); 1141 1142 /* Get cache line size. */ 1143 cacheline = CSR_READ_4(sc, TI_PCI_BIST) & 0xFF; 1144 1145 /* 1146 * If the system has set enabled the PCI memory write 1147 * and invalidate command in the command register, set 1148 * the write max parameter accordingly. This is necessary 1149 * to use MWI with the Tigon 2. 1150 */ 1151 if (CSR_READ_4(sc, TI_PCI_CMDSTAT) & PCIM_CMD_MWIEN) { 1152 switch(cacheline) { 1153 case 1: 1154 case 4: 1155 case 8: 1156 case 16: 1157 case 32: 1158 case 64: 1159 break; 1160 default: 1161 /* Disable PCI memory write and invalidate. */ 1162 if (bootverbose) { 1163 if_printf(ifp, "cache line size %d not " 1164 "supported; disabling PCI MWI\n", 1165 cacheline); 1166 } 1167 CSR_WRITE_4(sc, TI_PCI_CMDSTAT, CSR_READ_4(sc, 1168 TI_PCI_CMDSTAT) & ~PCIM_CMD_MWIEN); 1169 break; 1170 } 1171 } 1172 1173 TI_SETBIT(sc, TI_PCI_STATE, pci_writemax); 1174 1175 /* This sets the min dma param all the way up (0xff). */ 1176 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_MINDMA); 1177 1178 /* Configure DMA variables. */ 1179 #if BYTE_ORDER == BIG_ENDIAN 1180 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_BD | 1181 TI_OPMODE_BYTESWAP_DATA | TI_OPMODE_WORDSWAP_BD | 1182 TI_OPMODE_WARN_ENB | TI_OPMODE_FATAL_ENB | 1183 TI_OPMODE_DONT_FRAG_JUMBO); 1184 #else 1185 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_DATA| 1186 TI_OPMODE_WORDSWAP_BD|TI_OPMODE_DONT_FRAG_JUMBO| 1187 TI_OPMODE_WARN_ENB|TI_OPMODE_FATAL_ENB); 1188 #endif 1189 1190 /* 1191 * Only allow 1 DMA channel to be active at a time. 1192 * I don't think this is a good idea, but without it 1193 * the firmware racks up lots of nicDmaReadRingFull 1194 * errors. This is not compatible with hardware checksums. 1195 */ 1196 if (ifp->if_hwassist == 0) 1197 TI_SETBIT(sc, TI_GCR_OPMODE, TI_OPMODE_1_DMA_ACTIVE); 1198 1199 /* Recommended settings from Tigon manual. */ 1200 CSR_WRITE_4(sc, TI_GCR_DMA_WRITECFG, TI_DMA_STATE_THRESH_8W); 1201 CSR_WRITE_4(sc, TI_GCR_DMA_READCFG, TI_DMA_STATE_THRESH_8W); 1202 1203 if (ti_64bitslot_war(sc)) { 1204 if_printf(ifp, "bios thinks we're in a 64 bit slot, " 1205 "but we aren't"); 1206 return(EINVAL); 1207 } 1208 1209 return(0); 1210 } 1211 1212 /* 1213 * Initialize the general information block and firmware, and 1214 * start the CPU(s) running. 1215 */ 1216 static int 1217 ti_gibinit(struct ti_softc *sc) 1218 { 1219 struct ifnet *ifp = &sc->arpcom.ac_if; 1220 struct ti_rcb *rcb; 1221 int i; 1222 1223 /* Disable interrupts for now. */ 1224 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 1225 1226 /* Tell the chip where to find the general information block. */ 1227 CSR_WRITE_4(sc, TI_GCR_GENINFO_HI, 0); 1228 CSR_WRITE_4(sc, TI_GCR_GENINFO_LO, vtophys(&sc->ti_rdata->ti_info)); 1229 1230 /* Load the firmware into SRAM. */ 1231 ti_loadfw(sc); 1232 1233 /* Set up the contents of the general info and ring control blocks. */ 1234 1235 /* Set up the event ring and producer pointer. */ 1236 rcb = &sc->ti_rdata->ti_info.ti_ev_rcb; 1237 1238 TI_HOSTADDR(rcb->ti_hostaddr) = vtophys(&sc->ti_rdata->ti_event_ring); 1239 rcb->ti_flags = 0; 1240 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_ev_prodidx_ptr) = 1241 vtophys(&sc->ti_ev_prodidx); 1242 sc->ti_ev_prodidx.ti_idx = 0; 1243 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, 0); 1244 sc->ti_ev_saved_considx = 0; 1245 1246 /* Set up the command ring and producer mailbox. */ 1247 rcb = &sc->ti_rdata->ti_info.ti_cmd_rcb; 1248 1249 sc->ti_rdata->ti_cmd_ring = 1250 (struct ti_cmd_desc *)(sc->ti_vhandle + TI_GCR_CMDRING); 1251 TI_HOSTADDR(rcb->ti_hostaddr) = TI_GCR_NIC_ADDR(TI_GCR_CMDRING); 1252 rcb->ti_flags = 0; 1253 rcb->ti_max_len = 0; 1254 for (i = 0; i < TI_CMD_RING_CNT; i++) 1255 CSR_WRITE_4(sc, TI_GCR_CMDRING + (i * 4), 0); 1256 CSR_WRITE_4(sc, TI_GCR_CMDCONS_IDX, 0); 1257 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, 0); 1258 sc->ti_cmd_saved_prodidx = 0; 1259 1260 /* 1261 * Assign the address of the stats refresh buffer. 1262 * We re-use the current stats buffer for this to 1263 * conserve memory. 1264 */ 1265 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_refresh_stats_ptr) = 1266 vtophys(&sc->ti_rdata->ti_info.ti_stats); 1267 1268 /* Set up the standard receive ring. */ 1269 rcb = &sc->ti_rdata->ti_info.ti_std_rx_rcb; 1270 TI_HOSTADDR(rcb->ti_hostaddr) = vtophys(&sc->ti_rdata->ti_rx_std_ring); 1271 rcb->ti_max_len = TI_FRAMELEN; 1272 rcb->ti_flags = 0; 1273 if (ifp->if_hwassist) 1274 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 1275 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 1276 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1277 1278 /* Set up the jumbo receive ring. */ 1279 rcb = &sc->ti_rdata->ti_info.ti_jumbo_rx_rcb; 1280 TI_HOSTADDR(rcb->ti_hostaddr) = 1281 vtophys(&sc->ti_rdata->ti_rx_jumbo_ring); 1282 rcb->ti_max_len = TI_JUMBO_FRAMELEN; 1283 rcb->ti_flags = 0; 1284 if (ifp->if_hwassist) 1285 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 1286 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 1287 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1288 1289 /* 1290 * Set up the mini ring. Only activated on the 1291 * Tigon 2 but the slot in the config block is 1292 * still there on the Tigon 1. 1293 */ 1294 rcb = &sc->ti_rdata->ti_info.ti_mini_rx_rcb; 1295 TI_HOSTADDR(rcb->ti_hostaddr) = 1296 vtophys(&sc->ti_rdata->ti_rx_mini_ring); 1297 rcb->ti_max_len = MHLEN - ETHER_ALIGN; 1298 if (sc->ti_hwrev == TI_HWREV_TIGON) 1299 rcb->ti_flags = TI_RCB_FLAG_RING_DISABLED; 1300 else 1301 rcb->ti_flags = 0; 1302 if (ifp->if_hwassist) 1303 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 1304 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 1305 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1306 1307 /* 1308 * Set up the receive return ring. 1309 */ 1310 rcb = &sc->ti_rdata->ti_info.ti_return_rcb; 1311 TI_HOSTADDR(rcb->ti_hostaddr) = 1312 vtophys(&sc->ti_rdata->ti_rx_return_ring); 1313 rcb->ti_flags = 0; 1314 rcb->ti_max_len = TI_RETURN_RING_CNT; 1315 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_return_prodidx_ptr) = 1316 vtophys(&sc->ti_return_prodidx); 1317 1318 /* 1319 * Set up the tx ring. Note: for the Tigon 2, we have the option 1320 * of putting the transmit ring in the host's address space and 1321 * letting the chip DMA it instead of leaving the ring in the NIC's 1322 * memory and accessing it through the shared memory region. We 1323 * do this for the Tigon 2, but it doesn't work on the Tigon 1, 1324 * so we have to revert to the shared memory scheme if we detect 1325 * a Tigon 1 chip. 1326 */ 1327 CSR_WRITE_4(sc, TI_WINBASE, TI_TX_RING_BASE); 1328 if (sc->ti_hwrev == TI_HWREV_TIGON) { 1329 sc->ti_rdata->ti_tx_ring_nic = 1330 (struct ti_tx_desc *)(sc->ti_vhandle + TI_WINDOW); 1331 } 1332 bzero(sc->ti_rdata->ti_tx_ring, 1333 TI_TX_RING_CNT * sizeof(struct ti_tx_desc)); 1334 rcb = &sc->ti_rdata->ti_info.ti_tx_rcb; 1335 if (sc->ti_hwrev == TI_HWREV_TIGON) 1336 rcb->ti_flags = 0; 1337 else 1338 rcb->ti_flags = TI_RCB_FLAG_HOST_RING; 1339 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1340 if (ifp->if_hwassist) 1341 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 1342 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 1343 rcb->ti_max_len = TI_TX_RING_CNT; 1344 if (sc->ti_hwrev == TI_HWREV_TIGON) 1345 TI_HOSTADDR(rcb->ti_hostaddr) = TI_TX_RING_BASE; 1346 else 1347 TI_HOSTADDR(rcb->ti_hostaddr) = 1348 vtophys(&sc->ti_rdata->ti_tx_ring); 1349 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_tx_considx_ptr) = 1350 vtophys(&sc->ti_tx_considx); 1351 1352 /* Set up tuneables */ 1353 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 1354 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, 1355 (sc->ti_rx_coal_ticks / 10)); 1356 else 1357 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, sc->ti_rx_coal_ticks); 1358 CSR_WRITE_4(sc, TI_GCR_TX_COAL_TICKS, sc->ti_tx_coal_ticks); 1359 CSR_WRITE_4(sc, TI_GCR_STAT_TICKS, sc->ti_stat_ticks); 1360 CSR_WRITE_4(sc, TI_GCR_RX_MAX_COAL_BD, sc->ti_rx_max_coal_bds); 1361 CSR_WRITE_4(sc, TI_GCR_TX_MAX_COAL_BD, sc->ti_tx_max_coal_bds); 1362 CSR_WRITE_4(sc, TI_GCR_TX_BUFFER_RATIO, sc->ti_tx_buf_ratio); 1363 1364 /* Turn interrupts on. */ 1365 CSR_WRITE_4(sc, TI_GCR_MASK_INTRS, 0); 1366 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 1367 1368 /* Start CPU. */ 1369 TI_CLRBIT(sc, TI_CPU_STATE, (TI_CPUSTATE_HALT|TI_CPUSTATE_STEP)); 1370 1371 return(0); 1372 } 1373 1374 /* 1375 * Probe for a Tigon chip. Check the PCI vendor and device IDs 1376 * against our list and return its name if we find a match. 1377 */ 1378 static int 1379 ti_probe(device_t dev) 1380 { 1381 struct ti_type *t; 1382 uint16_t vendor, product; 1383 1384 vendor = pci_get_vendor(dev); 1385 product = pci_get_device(dev); 1386 1387 for (t = ti_devs; t->ti_name != NULL; t++) { 1388 if (vendor == t->ti_vid && product == t->ti_did) { 1389 device_set_desc(dev, t->ti_name); 1390 return(0); 1391 } 1392 } 1393 1394 return(ENXIO); 1395 } 1396 1397 static int 1398 ti_attach(device_t dev) 1399 { 1400 struct ti_softc *sc; 1401 struct ifnet *ifp; 1402 int error = 0, rid; 1403 uint8_t eaddr[ETHER_ADDR_LEN]; 1404 1405 sc = device_get_softc(dev); 1406 ifp = &sc->arpcom.ac_if; 1407 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1408 ifp->if_capabilities = IFCAP_HWCSUM; 1409 ifp->if_capenable = ifp->if_capabilities; 1410 1411 pci_enable_busmaster(dev); 1412 1413 /* 1414 * Initialize media before any possible error may occur, 1415 * so we can destroy it unconditionally, if an error occurs later on. 1416 */ 1417 ifmedia_init(&sc->ifmedia, IFM_IMASK, ti_ifmedia_upd, ti_ifmedia_sts); 1418 1419 rid = TI_PCI_LOMEM; 1420 sc->ti_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 1421 RF_ACTIVE); 1422 1423 if (sc->ti_res == NULL) { 1424 device_printf(dev, "couldn't map memory\n"); 1425 error = ENXIO; 1426 goto fail; 1427 } 1428 1429 sc->ti_btag = rman_get_bustag(sc->ti_res); 1430 sc->ti_bhandle = rman_get_bushandle(sc->ti_res); 1431 sc->ti_vhandle = (vm_offset_t)rman_get_virtual(sc->ti_res); 1432 1433 /* Allocate interrupt */ 1434 rid = 0; 1435 sc->ti_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1436 RF_SHAREABLE | RF_ACTIVE); 1437 if (sc->ti_irq == NULL) { 1438 device_printf(dev, "couldn't map interrupt\n"); 1439 error = ENXIO; 1440 goto fail; 1441 } 1442 1443 if (ti_chipinit(sc)) { 1444 device_printf(dev, "chip initialization failed\n"); 1445 error = ENXIO; 1446 goto fail; 1447 } 1448 1449 /* Zero out the NIC's on-board SRAM. */ 1450 ti_mem(sc, 0x2000, 0x100000 - 0x2000, NULL); 1451 1452 /* Init again -- zeroing memory may have clobbered some registers. */ 1453 if (ti_chipinit(sc)) { 1454 device_printf(dev, "chip initialization failed\n"); 1455 error = ENXIO; 1456 goto fail; 1457 } 1458 1459 /* 1460 * Get station address from the EEPROM. Note: the manual states 1461 * that the MAC address is at offset 0x8c, however the data is 1462 * stored as two longwords (since that's how it's loaded into 1463 * the NIC). This means the MAC address is actually preceeded 1464 * by two zero bytes. We need to skip over those. 1465 */ 1466 if (ti_read_eeprom(sc, eaddr, TI_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) { 1467 device_printf(dev, "failed to read station address\n"); 1468 error = ENXIO; 1469 goto fail; 1470 } 1471 1472 /* Allocate the general information block and ring buffers. */ 1473 sc->ti_rdata = contigmalloc(sizeof(struct ti_ring_data), M_DEVBUF, 1474 M_WAITOK, 0, 0xffffffff, PAGE_SIZE, 0); 1475 1476 if (sc->ti_rdata == NULL) { 1477 device_printf(dev, "no memory for list buffers!\n"); 1478 error = ENXIO; 1479 goto fail; 1480 } 1481 1482 bzero(sc->ti_rdata, sizeof(struct ti_ring_data)); 1483 1484 /* Try to allocate memory for jumbo buffers. */ 1485 if (ti_alloc_jumbo_mem(sc)) { 1486 device_printf(dev, "jumbo buffer allocation failed\n"); 1487 error = ENXIO; 1488 goto fail; 1489 } 1490 1491 /* 1492 * We really need a better way to tell a 1000baseTX card 1493 * from a 1000baseSX one, since in theory there could be 1494 * OEMed 1000baseTX cards from lame vendors who aren't 1495 * clever enough to change the PCI ID. For the moment 1496 * though, the AceNIC is the only copper card available. 1497 */ 1498 if (pci_get_vendor(dev) == ALT_VENDORID && 1499 pci_get_device(dev) == ALT_DEVICEID_ACENIC_COPPER) 1500 sc->ti_copper = 1; 1501 /* Ok, it's not the only copper card available. */ 1502 if (pci_get_vendor(dev) == NG_VENDORID && 1503 pci_get_device(dev) == NG_DEVICEID_GA620T) 1504 sc->ti_copper = 1; 1505 1506 /* Set default tuneable values. */ 1507 sc->ti_stat_ticks = 2 * TI_TICKS_PER_SEC; 1508 sc->ti_rx_coal_ticks = TI_TICKS_PER_SEC / 5000; 1509 sc->ti_tx_coal_ticks = TI_TICKS_PER_SEC / 500; 1510 sc->ti_rx_max_coal_bds = 64; 1511 sc->ti_tx_max_coal_bds = 128; 1512 sc->ti_tx_buf_ratio = 21; 1513 1514 /* Set up ifnet structure */ 1515 ifp->if_softc = sc; 1516 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1517 ifp->if_ioctl = ti_ioctl; 1518 ifp->if_start = ti_start; 1519 ifp->if_watchdog = ti_watchdog; 1520 ifp->if_init = ti_init; 1521 ifp->if_mtu = ETHERMTU; 1522 ifq_set_maxlen(&ifp->if_snd, TI_TX_RING_CNT - 1); 1523 ifq_set_ready(&ifp->if_snd); 1524 1525 /* Set up ifmedia support. */ 1526 if (sc->ti_copper) { 1527 /* 1528 * Copper cards allow manual 10/100 mode selection, 1529 * but not manual 1000baseTX mode selection. Why? 1530 * Becuase currently there's no way to specify the 1531 * master/slave setting through the firmware interface, 1532 * so Alteon decided to just bag it and handle it 1533 * via autonegotiation. 1534 */ 1535 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL); 1536 ifmedia_add(&sc->ifmedia, 1537 IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL); 1538 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_TX, 0, NULL); 1539 ifmedia_add(&sc->ifmedia, 1540 IFM_ETHER|IFM_100_TX|IFM_FDX, 0, NULL); 1541 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_1000_T, 0, NULL); 1542 ifmedia_add(&sc->ifmedia, 1543 IFM_ETHER|IFM_1000_T | IFM_FDX, 0, NULL); 1544 } else { 1545 /* Fiber cards don't support 10/100 modes. */ 1546 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL); 1547 ifmedia_add(&sc->ifmedia, 1548 IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL); 1549 } 1550 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 1551 ifmedia_set(&sc->ifmedia, IFM_ETHER|IFM_AUTO); 1552 1553 /* 1554 * Call MI attach routine. 1555 */ 1556 ether_ifattach(ifp, eaddr); 1557 1558 error = bus_setup_intr(dev, sc->ti_irq, INTR_TYPE_NET, 1559 ti_intr, sc, &sc->ti_intrhand, NULL); 1560 if (error) { 1561 device_printf(dev, "couldn't set up irq\n"); 1562 ether_ifdetach(ifp); 1563 goto fail; 1564 } 1565 return 0; 1566 1567 fail: 1568 ti_detach(dev); 1569 return(error); 1570 } 1571 1572 static int 1573 ti_detach(device_t dev) 1574 { 1575 struct ti_softc *sc = device_get_softc(dev); 1576 struct ifnet *ifp = &sc->arpcom.ac_if; 1577 1578 crit_enter(); 1579 1580 if (device_is_attached(dev)) { 1581 if (bus_child_present(dev)) 1582 ti_stop(sc); 1583 ether_ifdetach(ifp); 1584 } 1585 1586 if (sc->ti_intrhand != NULL) 1587 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 1588 1589 crit_exit(); 1590 1591 if (sc->ti_irq != NULL) 1592 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 1593 if (sc->ti_res != NULL) { 1594 bus_release_resource(dev, SYS_RES_MEMORY, 1595 TI_PCI_LOMEM, sc->ti_res); 1596 } 1597 if (sc->ti_cdata.ti_jumbo_buf != NULL) 1598 contigfree(sc->ti_cdata.ti_jumbo_buf, TI_JMEM, M_DEVBUF); 1599 if (sc->ti_rdata != NULL) 1600 contigfree(sc->ti_rdata, sizeof(struct ti_ring_data), M_DEVBUF); 1601 ifmedia_removeall(&sc->ifmedia); 1602 1603 return(0); 1604 } 1605 1606 /* 1607 * Frame reception handling. This is called if there's a frame 1608 * on the receive return list. 1609 * 1610 * Note: we have to be able to handle three possibilities here: 1611 * 1) the frame is from the mini receive ring (can only happen) 1612 * on Tigon 2 boards) 1613 * 2) the frame is from the jumbo recieve ring 1614 * 3) the frame is from the standard receive ring 1615 */ 1616 static void 1617 ti_rxeof(struct ti_softc *sc) 1618 { 1619 struct ifnet *ifp = &sc->arpcom.ac_if; 1620 struct ti_cmd_desc cmd; 1621 1622 while(sc->ti_rx_saved_considx != sc->ti_return_prodidx.ti_idx) { 1623 struct ti_rx_desc *cur_rx; 1624 uint32_t rxidx; 1625 struct mbuf *m; 1626 uint16_t vlan_tag = 0; 1627 int have_tag = 0; 1628 1629 cur_rx = 1630 &sc->ti_rdata->ti_rx_return_ring[sc->ti_rx_saved_considx]; 1631 rxidx = cur_rx->ti_idx; 1632 TI_INC(sc->ti_rx_saved_considx, TI_RETURN_RING_CNT); 1633 1634 if (cur_rx->ti_flags & TI_BDFLAG_VLAN_TAG) { 1635 have_tag = 1; 1636 vlan_tag = cur_rx->ti_vlan_tag & 0xfff; 1637 } 1638 1639 if (cur_rx->ti_flags & TI_BDFLAG_JUMBO_RING) { 1640 TI_INC(sc->ti_jumbo, TI_JUMBO_RX_RING_CNT); 1641 m = sc->ti_cdata.ti_rx_jumbo_chain[rxidx]; 1642 sc->ti_cdata.ti_rx_jumbo_chain[rxidx] = NULL; 1643 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 1644 ifp->if_ierrors++; 1645 ti_newbuf_jumbo(sc, sc->ti_jumbo, m); 1646 continue; 1647 } 1648 if (ti_newbuf_jumbo(sc, sc->ti_jumbo, NULL) == ENOBUFS) { 1649 ifp->if_ierrors++; 1650 ti_newbuf_jumbo(sc, sc->ti_jumbo, m); 1651 continue; 1652 } 1653 } else if (cur_rx->ti_flags & TI_BDFLAG_MINI_RING) { 1654 TI_INC(sc->ti_mini, TI_MINI_RX_RING_CNT); 1655 m = sc->ti_cdata.ti_rx_mini_chain[rxidx]; 1656 sc->ti_cdata.ti_rx_mini_chain[rxidx] = NULL; 1657 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 1658 ifp->if_ierrors++; 1659 ti_newbuf_mini(sc, sc->ti_mini, m); 1660 continue; 1661 } 1662 if (ti_newbuf_mini(sc, sc->ti_mini, NULL) == ENOBUFS) { 1663 ifp->if_ierrors++; 1664 ti_newbuf_mini(sc, sc->ti_mini, m); 1665 continue; 1666 } 1667 } else { 1668 TI_INC(sc->ti_std, TI_STD_RX_RING_CNT); 1669 m = sc->ti_cdata.ti_rx_std_chain[rxidx]; 1670 sc->ti_cdata.ti_rx_std_chain[rxidx] = NULL; 1671 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 1672 ifp->if_ierrors++; 1673 ti_newbuf_std(sc, sc->ti_std, m); 1674 continue; 1675 } 1676 if (ti_newbuf_std(sc, sc->ti_std, NULL) == ENOBUFS) { 1677 ifp->if_ierrors++; 1678 ti_newbuf_std(sc, sc->ti_std, m); 1679 continue; 1680 } 1681 } 1682 1683 m->m_pkthdr.len = m->m_len = cur_rx->ti_len; 1684 ifp->if_ipackets++; 1685 m->m_pkthdr.rcvif = ifp; 1686 1687 if (ifp->if_hwassist) { 1688 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED | 1689 CSUM_DATA_VALID; 1690 if ((cur_rx->ti_ip_cksum ^ 0xffff) == 0) 1691 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1692 m->m_pkthdr.csum_data = cur_rx->ti_tcp_udp_cksum; 1693 } 1694 1695 /* 1696 * If we received a packet with a vlan tag, pass it 1697 * to vlan_input() instead of ether_input(). 1698 */ 1699 if (have_tag) 1700 VLAN_INPUT_TAG(m, vlan_tag); 1701 else 1702 (*ifp->if_input)(ifp, m); 1703 } 1704 1705 /* Only necessary on the Tigon 1. */ 1706 if (sc->ti_hwrev == TI_HWREV_TIGON) 1707 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 1708 sc->ti_rx_saved_considx); 1709 1710 TI_UPDATE_STDPROD(sc, sc->ti_std); 1711 TI_UPDATE_MINIPROD(sc, sc->ti_mini); 1712 TI_UPDATE_JUMBOPROD(sc, sc->ti_jumbo); 1713 } 1714 1715 static void 1716 ti_txeof(struct ti_softc *sc) 1717 { 1718 struct ifnet *ifp = &sc->arpcom.ac_if; 1719 struct ti_tx_desc *cur_tx = NULL; 1720 1721 /* 1722 * Go through our tx ring and free mbufs for those 1723 * frames that have been sent. 1724 */ 1725 while (sc->ti_tx_saved_considx != sc->ti_tx_considx.ti_idx) { 1726 uint32_t idx = 0; 1727 1728 idx = sc->ti_tx_saved_considx; 1729 if (sc->ti_hwrev != TI_HWREV_TIGON) { 1730 if (idx > 383) 1731 CSR_WRITE_4(sc, TI_WINBASE, 1732 TI_TX_RING_BASE + 6144); 1733 else if (idx > 255) 1734 CSR_WRITE_4(sc, TI_WINBASE, 1735 TI_TX_RING_BASE + 4096); 1736 else if (idx > 127) 1737 CSR_WRITE_4(sc, TI_WINBASE, 1738 TI_TX_RING_BASE + 2048); 1739 else 1740 CSR_WRITE_4(sc, TI_WINBASE, 1741 TI_TX_RING_BASE); 1742 cur_tx = &sc->ti_rdata->ti_tx_ring_nic[idx % 128]; 1743 } else 1744 cur_tx = &sc->ti_rdata->ti_tx_ring[idx]; 1745 if (cur_tx->ti_flags & TI_BDFLAG_END) 1746 ifp->if_opackets++; 1747 if (sc->ti_cdata.ti_tx_chain[idx] != NULL) { 1748 m_freem(sc->ti_cdata.ti_tx_chain[idx]); 1749 sc->ti_cdata.ti_tx_chain[idx] = NULL; 1750 } 1751 sc->ti_txcnt--; 1752 TI_INC(sc->ti_tx_saved_considx, TI_TX_RING_CNT); 1753 ifp->if_timer = 0; 1754 } 1755 1756 if (cur_tx != NULL) 1757 ifp->if_flags &= ~IFF_OACTIVE; 1758 } 1759 1760 static void 1761 ti_intr(void *xsc) 1762 { 1763 struct ti_softc *sc = xsc; 1764 struct ifnet *ifp = &sc->arpcom.ac_if; 1765 1766 #ifdef notdef 1767 /* Avoid this for now -- checking this register is expensive. */ 1768 /* Make sure this is really our interrupt. */ 1769 if ((CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_INTSTATE) == 0) 1770 return; 1771 #endif 1772 1773 /* Ack interrupt and stop others from occuring. */ 1774 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 1775 1776 if (ifp->if_flags & IFF_RUNNING) { 1777 /* Check RX return ring producer/consumer */ 1778 ti_rxeof(sc); 1779 1780 /* Check TX ring producer/consumer */ 1781 ti_txeof(sc); 1782 } 1783 1784 ti_handle_events(sc); 1785 1786 /* Re-enable interrupts. */ 1787 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 1788 1789 if ((ifp->if_flags & IFF_RUNNING) && !ifq_is_empty(&ifp->if_snd)) 1790 ti_start(ifp); 1791 } 1792 1793 static void 1794 ti_stats_update(struct ti_softc *sc) 1795 { 1796 struct ifnet *ifp = &sc->arpcom.ac_if; 1797 1798 ifp->if_collisions += 1799 (sc->ti_rdata->ti_info.ti_stats.dot3StatsSingleCollisionFrames + 1800 sc->ti_rdata->ti_info.ti_stats.dot3StatsMultipleCollisionFrames + 1801 sc->ti_rdata->ti_info.ti_stats.dot3StatsExcessiveCollisions + 1802 sc->ti_rdata->ti_info.ti_stats.dot3StatsLateCollisions) - 1803 ifp->if_collisions; 1804 } 1805 1806 /* 1807 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 1808 * pointers to descriptors. 1809 */ 1810 static int 1811 ti_encap(struct ti_softc *sc, struct mbuf *m_head, uint32_t *txidx) 1812 { 1813 struct ti_tx_desc *f = NULL; 1814 struct mbuf *m; 1815 struct ifvlan *ifv = NULL; 1816 uint32_t cnt = 0, cur, frag; 1817 uint16_t csum_flags = 0; 1818 1819 if ((m_head->m_flags & (M_PROTO1|M_PKTHDR)) == (M_PROTO1|M_PKTHDR) && 1820 m_head->m_pkthdr.rcvif != NULL && 1821 m_head->m_pkthdr.rcvif->if_type == IFT_L2VLAN) 1822 ifv = m_head->m_pkthdr.rcvif->if_softc; 1823 1824 m = m_head; 1825 cur = frag = *txidx; 1826 1827 if (m_head->m_pkthdr.csum_flags) { 1828 if (m_head->m_pkthdr.csum_flags & CSUM_IP) 1829 csum_flags |= TI_BDFLAG_IP_CKSUM; 1830 if (m_head->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) 1831 csum_flags |= TI_BDFLAG_TCP_UDP_CKSUM; 1832 if (m_head->m_flags & M_LASTFRAG) 1833 csum_flags |= TI_BDFLAG_IP_FRAG_END; 1834 else if (m_head->m_flags & M_FRAG) 1835 csum_flags |= TI_BDFLAG_IP_FRAG; 1836 } 1837 /* 1838 * Start packing the mbufs in this chain into 1839 * the fragment pointers. Stop when we run out 1840 * of fragments or hit the end of the mbuf chain. 1841 */ 1842 for (m = m_head; m != NULL; m = m->m_next) { 1843 if (m->m_len != 0) { 1844 if (sc->ti_hwrev == TI_HWREV_TIGON) { 1845 if (frag > 383) 1846 CSR_WRITE_4(sc, TI_WINBASE, 1847 TI_TX_RING_BASE + 6144); 1848 else if (frag > 255) 1849 CSR_WRITE_4(sc, TI_WINBASE, 1850 TI_TX_RING_BASE + 4096); 1851 else if (frag > 127) 1852 CSR_WRITE_4(sc, TI_WINBASE, 1853 TI_TX_RING_BASE + 2048); 1854 else 1855 CSR_WRITE_4(sc, TI_WINBASE, 1856 TI_TX_RING_BASE); 1857 f = &sc->ti_rdata->ti_tx_ring_nic[frag % 128]; 1858 } else 1859 f = &sc->ti_rdata->ti_tx_ring[frag]; 1860 if (sc->ti_cdata.ti_tx_chain[frag] != NULL) 1861 break; 1862 TI_HOSTADDR(f->ti_addr) = vtophys(mtod(m, vm_offset_t)); 1863 f->ti_len = m->m_len; 1864 f->ti_flags = csum_flags; 1865 1866 if (ifv != NULL) { 1867 f->ti_flags |= TI_BDFLAG_VLAN_TAG; 1868 f->ti_vlan_tag = ifv->ifv_tag & 0xfff; 1869 } else { 1870 f->ti_vlan_tag = 0; 1871 } 1872 1873 /* 1874 * Sanity check: avoid coming within 16 descriptors 1875 * of the end of the ring. 1876 */ 1877 if ((TI_TX_RING_CNT - (sc->ti_txcnt + cnt)) < 16) 1878 return(ENOBUFS); 1879 cur = frag; 1880 TI_INC(frag, TI_TX_RING_CNT); 1881 cnt++; 1882 } 1883 } 1884 1885 if (m != NULL) 1886 return(ENOBUFS); 1887 1888 if (frag == sc->ti_tx_saved_considx) 1889 return(ENOBUFS); 1890 1891 if (sc->ti_hwrev == TI_HWREV_TIGON) 1892 sc->ti_rdata->ti_tx_ring_nic[cur % 128].ti_flags |= 1893 TI_BDFLAG_END; 1894 else 1895 sc->ti_rdata->ti_tx_ring[cur].ti_flags |= TI_BDFLAG_END; 1896 sc->ti_cdata.ti_tx_chain[cur] = m_head; 1897 sc->ti_txcnt += cnt; 1898 1899 *txidx = frag; 1900 1901 return(0); 1902 } 1903 1904 /* 1905 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1906 * to the mbuf data regions directly in the transmit descriptors. 1907 */ 1908 static void 1909 ti_start(struct ifnet *ifp) 1910 { 1911 struct ti_softc *sc = ifp->if_softc; 1912 struct mbuf *m_head = NULL; 1913 uint32_t prodidx = 0; 1914 1915 prodidx = CSR_READ_4(sc, TI_MB_SENDPROD_IDX); 1916 1917 while(sc->ti_cdata.ti_tx_chain[prodidx] == NULL) { 1918 m_head = ifq_poll(&ifp->if_snd); 1919 if (m_head == NULL) 1920 break; 1921 1922 /* 1923 * XXX 1924 * safety overkill. If this is a fragmented packet chain 1925 * with delayed TCP/UDP checksums, then only encapsulate 1926 * it if we have enough descriptors to handle the entire 1927 * chain at once. 1928 * (paranoia -- may not actually be needed) 1929 */ 1930 if (m_head->m_flags & M_FIRSTFRAG && 1931 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) { 1932 if ((TI_TX_RING_CNT - sc->ti_txcnt) < 1933 m_head->m_pkthdr.csum_data + 16) { 1934 ifp->if_flags |= IFF_OACTIVE; 1935 break; 1936 } 1937 } 1938 1939 /* 1940 * Pack the data into the transmit ring. If we 1941 * don't have room, set the OACTIVE flag and wait 1942 * for the NIC to drain the ring. 1943 */ 1944 if (ti_encap(sc, m_head, &prodidx)) { 1945 ifp->if_flags |= IFF_OACTIVE; 1946 break; 1947 } 1948 1949 m_head = ifq_dequeue(&ifp->if_snd); 1950 BPF_MTAP(ifp, m_head); 1951 } 1952 1953 /* Transmit */ 1954 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, prodidx); 1955 1956 /* 1957 * Set a timeout in case the chip goes out to lunch. 1958 */ 1959 ifp->if_timer = 5; 1960 } 1961 1962 static void 1963 ti_init(void *xsc) 1964 { 1965 struct ti_softc *sc = xsc; 1966 1967 crit_enter(); 1968 1969 /* Cancel pending I/O and flush buffers. */ 1970 ti_stop(sc); 1971 1972 /* Init the gen info block, ring control blocks and firmware. */ 1973 if (ti_gibinit(sc)) { 1974 if_printf(&sc->arpcom.ac_if, "initialization failure\n"); 1975 crit_exit(); 1976 return; 1977 } 1978 1979 crit_exit(); 1980 } 1981 1982 static void 1983 ti_init2(struct ti_softc *sc) 1984 { 1985 struct ifnet *ifp = &sc->arpcom.ac_if; 1986 struct ti_cmd_desc cmd; 1987 uint16_t *m; 1988 struct ifmedia *ifm; 1989 int tmp; 1990 1991 /* Specify MTU and interface index. */ 1992 CSR_WRITE_4(sc, TI_GCR_IFINDEX, ifp->if_dunit); 1993 CSR_WRITE_4(sc, TI_GCR_IFMTU, ifp->if_mtu + 1994 ETHER_HDR_LEN + ETHER_CRC_LEN); 1995 TI_DO_CMD(TI_CMD_UPDATE_GENCOM, 0, 0); 1996 1997 /* Load our MAC address. */ 1998 m = (uint16_t *)&sc->arpcom.ac_enaddr[0]; 1999 CSR_WRITE_4(sc, TI_GCR_PAR0, htons(m[0])); 2000 CSR_WRITE_4(sc, TI_GCR_PAR1, (htons(m[1]) << 16) | htons(m[2])); 2001 TI_DO_CMD(TI_CMD_SET_MAC_ADDR, 0, 0); 2002 2003 /* Enable or disable promiscuous mode as needed. */ 2004 if (ifp->if_flags & IFF_PROMISC) 2005 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_ENB, 0); 2006 else 2007 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_DIS, 0); 2008 2009 /* Program multicast filter. */ 2010 ti_setmulti(sc); 2011 2012 /* 2013 * If this is a Tigon 1, we should tell the 2014 * firmware to use software packet filtering. 2015 */ 2016 if (sc->ti_hwrev == TI_HWREV_TIGON) 2017 TI_DO_CMD(TI_CMD_FDR_FILTERING, TI_CMD_CODE_FILT_ENB, 0); 2018 2019 /* Init RX ring. */ 2020 ti_init_rx_ring_std(sc); 2021 2022 /* Init jumbo RX ring. */ 2023 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 2024 ti_init_rx_ring_jumbo(sc); 2025 2026 /* 2027 * If this is a Tigon 2, we can also configure the 2028 * mini ring. 2029 */ 2030 if (sc->ti_hwrev == TI_HWREV_TIGON_II) 2031 ti_init_rx_ring_mini(sc); 2032 2033 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 0); 2034 sc->ti_rx_saved_considx = 0; 2035 2036 /* Init TX ring. */ 2037 ti_init_tx_ring(sc); 2038 2039 /* Tell firmware we're alive. */ 2040 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_UP, 0); 2041 2042 /* Enable host interrupts. */ 2043 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 2044 2045 ifp->if_flags |= IFF_RUNNING; 2046 ifp->if_flags &= ~IFF_OACTIVE; 2047 2048 /* 2049 * Make sure to set media properly. We have to do this 2050 * here since we have to issue commands in order to set 2051 * the link negotiation and we can't issue commands until 2052 * the firmware is running. 2053 */ 2054 ifm = &sc->ifmedia; 2055 tmp = ifm->ifm_media; 2056 ifm->ifm_media = ifm->ifm_cur->ifm_media; 2057 ti_ifmedia_upd(ifp); 2058 ifm->ifm_media = tmp; 2059 } 2060 2061 /* 2062 * Set media options. 2063 */ 2064 static int 2065 ti_ifmedia_upd(struct ifnet *ifp) 2066 { 2067 struct ti_softc *sc = ifp->if_softc; 2068 struct ifmedia *ifm = &sc->ifmedia; 2069 struct ti_cmd_desc cmd; 2070 2071 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 2072 return(EINVAL); 2073 2074 switch(IFM_SUBTYPE(ifm->ifm_media)) { 2075 case IFM_AUTO: 2076 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF | TI_GLNK_1000MB | 2077 TI_GLNK_FULL_DUPLEX | TI_GLNK_RX_FLOWCTL_Y | 2078 TI_GLNK_AUTONEGENB | TI_GLNK_ENB); 2079 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_100MB | TI_LNK_10MB | 2080 TI_LNK_FULL_DUPLEX | TI_LNK_HALF_DUPLEX | 2081 TI_LNK_AUTONEGENB | TI_LNK_ENB); 2082 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 2083 TI_CMD_CODE_NEGOTIATE_BOTH, 0); 2084 break; 2085 case IFM_1000_SX: 2086 case IFM_1000_T: 2087 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB | 2088 TI_GLNK_RX_FLOWCTL_Y | TI_GLNK_ENB); 2089 CSR_WRITE_4(sc, TI_GCR_LINK, 0); 2090 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 2091 TI_SETBIT(sc, TI_GCR_GLINK, TI_GLNK_FULL_DUPLEX); 2092 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 2093 TI_CMD_CODE_NEGOTIATE_GIGABIT, 0); 2094 break; 2095 case IFM_100_FX: 2096 case IFM_10_FL: 2097 case IFM_100_TX: 2098 case IFM_10_T: 2099 CSR_WRITE_4(sc, TI_GCR_GLINK, 0); 2100 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_ENB | TI_LNK_PREF); 2101 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_100_FX || 2102 IFM_SUBTYPE(ifm->ifm_media) == IFM_100_TX) 2103 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_100MB); 2104 else 2105 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_10MB); 2106 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 2107 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_FULL_DUPLEX); 2108 else 2109 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_HALF_DUPLEX); 2110 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 2111 TI_CMD_CODE_NEGOTIATE_10_100, 0); 2112 break; 2113 } 2114 2115 return(0); 2116 } 2117 2118 /* 2119 * Report current media status. 2120 */ 2121 static void 2122 ti_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 2123 { 2124 struct ti_softc *sc = ifp->if_softc; 2125 uint32_t media = 0; 2126 2127 ifmr->ifm_status = IFM_AVALID; 2128 ifmr->ifm_active = IFM_ETHER; 2129 2130 if (sc->ti_linkstat == TI_EV_CODE_LINK_DOWN) 2131 return; 2132 2133 ifmr->ifm_status |= IFM_ACTIVE; 2134 2135 if (sc->ti_linkstat == TI_EV_CODE_GIG_LINK_UP) { 2136 media = CSR_READ_4(sc, TI_GCR_GLINK_STAT); 2137 if (sc->ti_copper) 2138 ifmr->ifm_active |= IFM_1000_T; 2139 else 2140 ifmr->ifm_active |= IFM_1000_SX; 2141 if (media & TI_GLNK_FULL_DUPLEX) 2142 ifmr->ifm_active |= IFM_FDX; 2143 else 2144 ifmr->ifm_active |= IFM_HDX; 2145 } else if (sc->ti_linkstat == TI_EV_CODE_LINK_UP) { 2146 media = CSR_READ_4(sc, TI_GCR_LINK_STAT); 2147 if (sc->ti_copper) { 2148 if (media & TI_LNK_100MB) 2149 ifmr->ifm_active |= IFM_100_TX; 2150 if (media & TI_LNK_10MB) 2151 ifmr->ifm_active |= IFM_10_T; 2152 } else { 2153 if (media & TI_LNK_100MB) 2154 ifmr->ifm_active |= IFM_100_FX; 2155 if (media & TI_LNK_10MB) 2156 ifmr->ifm_active |= IFM_10_FL; 2157 } 2158 if (media & TI_LNK_FULL_DUPLEX) 2159 ifmr->ifm_active |= IFM_FDX; 2160 if (media & TI_LNK_HALF_DUPLEX) 2161 ifmr->ifm_active |= IFM_HDX; 2162 } 2163 } 2164 2165 static int 2166 ti_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr) 2167 { 2168 struct ti_softc *sc = ifp->if_softc; 2169 struct ifreq *ifr = (struct ifreq *) data; 2170 struct ti_cmd_desc cmd; 2171 int error = 0, mask; 2172 2173 crit_enter(); 2174 2175 switch(command) { 2176 case SIOCSIFMTU: 2177 if (ifr->ifr_mtu > TI_JUMBO_MTU) 2178 error = EINVAL; 2179 else { 2180 ifp->if_mtu = ifr->ifr_mtu; 2181 ti_init(sc); 2182 } 2183 break; 2184 case SIOCSIFFLAGS: 2185 if (ifp->if_flags & IFF_UP) { 2186 /* 2187 * If only the state of the PROMISC flag changed, 2188 * then just use the 'set promisc mode' command 2189 * instead of reinitializing the entire NIC. Doing 2190 * a full re-init means reloading the firmware and 2191 * waiting for it to start up, which may take a 2192 * second or two. 2193 */ 2194 if (ifp->if_flags & IFF_RUNNING && 2195 ifp->if_flags & IFF_PROMISC && 2196 !(sc->ti_if_flags & IFF_PROMISC)) { 2197 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, 2198 TI_CMD_CODE_PROMISC_ENB, 0); 2199 } else if (ifp->if_flags & IFF_RUNNING && 2200 !(ifp->if_flags & IFF_PROMISC) && 2201 sc->ti_if_flags & IFF_PROMISC) { 2202 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, 2203 TI_CMD_CODE_PROMISC_DIS, 0); 2204 } else 2205 ti_init(sc); 2206 } else if (ifp->if_flags & IFF_RUNNING) { 2207 ti_stop(sc); 2208 } 2209 sc->ti_if_flags = ifp->if_flags; 2210 error = 0; 2211 break; 2212 case SIOCADDMULTI: 2213 case SIOCDELMULTI: 2214 if (ifp->if_flags & IFF_RUNNING) { 2215 ti_setmulti(sc); 2216 error = 0; 2217 } 2218 break; 2219 case SIOCSIFMEDIA: 2220 case SIOCGIFMEDIA: 2221 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command); 2222 break; 2223 case SIOCSIFCAP: 2224 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 2225 if (mask & IFCAP_HWCSUM) { 2226 if (IFCAP_HWCSUM & ifp->if_capenable) 2227 ifp->if_capenable &= ~IFCAP_HWCSUM; 2228 else 2229 ifp->if_capenable |= IFCAP_HWCSUM; 2230 if (ifp->if_flags & IFF_RUNNING) 2231 ti_init(sc); 2232 } 2233 error = 0; 2234 break; 2235 default: 2236 error = ether_ioctl(ifp, command, data); 2237 break; 2238 } 2239 2240 crit_exit(); 2241 2242 return(error); 2243 } 2244 2245 static void 2246 ti_watchdog(struct ifnet *ifp) 2247 { 2248 struct ti_softc *sc = ifp->if_softc; 2249 2250 if_printf(ifp, "watchdog timeout -- resetting\n"); 2251 ti_stop(sc); 2252 ti_init(sc); 2253 2254 ifp->if_oerrors++; 2255 } 2256 2257 /* 2258 * Stop the adapter and free any mbufs allocated to the 2259 * RX and TX lists. 2260 */ 2261 static void 2262 ti_stop(struct ti_softc *sc) 2263 { 2264 struct ifnet *ifp = &sc->arpcom.ac_if; 2265 struct ti_cmd_desc cmd; 2266 2267 /* Disable host interrupts. */ 2268 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 2269 /* 2270 * Tell firmware we're shutting down. 2271 */ 2272 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_DOWN, 0); 2273 2274 /* Halt and reinitialize. */ 2275 ti_chipinit(sc); 2276 ti_mem(sc, 0x2000, 0x100000 - 0x2000, NULL); 2277 ti_chipinit(sc); 2278 2279 /* Free the RX lists. */ 2280 ti_free_rx_ring_std(sc); 2281 2282 /* Free jumbo RX list. */ 2283 ti_free_rx_ring_jumbo(sc); 2284 2285 /* Free mini RX list. */ 2286 ti_free_rx_ring_mini(sc); 2287 2288 /* Free TX buffers. */ 2289 ti_free_tx_ring(sc); 2290 2291 sc->ti_ev_prodidx.ti_idx = 0; 2292 sc->ti_return_prodidx.ti_idx = 0; 2293 sc->ti_tx_considx.ti_idx = 0; 2294 sc->ti_tx_saved_considx = TI_TXCONS_UNSET; 2295 2296 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2297 } 2298 2299 /* 2300 * Stop all chip I/O so that the kernel's probe routines don't 2301 * get confused by errant DMAs when rebooting. 2302 */ 2303 static void 2304 ti_shutdown(device_t dev) 2305 { 2306 struct ti_softc *sc = device_get_softc(dev); 2307 2308 ti_chipinit(sc); 2309 } 2310