1 /* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: src/sys/pci/if_ti.c,v 1.25.2.14 2002/02/15 04:20:20 silby Exp $ 33 */ 34 35 /* 36 * Alteon Networks Tigon PCI gigabit ethernet driver for FreeBSD. 37 * Manuals, sample driver and firmware source kits are available 38 * from http://www.alteon.com/support/openkits. 39 * 40 * Written by Bill Paul <wpaul@ctr.columbia.edu> 41 * Electrical Engineering Department 42 * Columbia University, New York City 43 */ 44 45 /* 46 * The Alteon Networks Tigon chip contains an embedded R4000 CPU, 47 * gigabit MAC, dual DMA channels and a PCI interface unit. NICs 48 * using the Tigon may have anywhere from 512K to 2MB of SRAM. The 49 * Tigon supports hardware IP, TCP and UCP checksumming, multicast 50 * filtering and jumbo (9014 byte) frames. The hardware is largely 51 * controlled by firmware, which must be loaded into the NIC during 52 * initialization. 53 * 54 * The Tigon 2 contains 2 R4000 CPUs and requires a newer firmware 55 * revision, which supports new features such as extended commands, 56 * extended jumbo receive ring desciptors and a mini receive ring. 57 * 58 * Alteon Networks is to be commended for releasing such a vast amount 59 * of development material for the Tigon NIC without requiring an NDA 60 * (although they really should have done it a long time ago). With 61 * any luck, the other vendors will finally wise up and follow Alteon's 62 * stellar example. 63 * 64 * The firmware for the Tigon 1 and 2 NICs is compiled directly into 65 * this driver by #including it as a C header file. This bloats the 66 * driver somewhat, but it's the easiest method considering that the 67 * driver code and firmware code need to be kept in sync. The source 68 * for the firmware is not provided with the FreeBSD distribution since 69 * compiling it requires a GNU toolchain targeted for mips-sgi-irix5.3. 70 * 71 * The following people deserve special thanks: 72 * - Terry Murphy of 3Com, for providing a 3c985 Tigon 1 board 73 * for testing 74 * - Raymond Lee of Netgear, for providing a pair of Netgear 75 * GA620 Tigon 2 boards for testing 76 * - Ulf Zimmermann, for bringing the GA260 to my attention and 77 * convincing me to write this driver. 78 * - Andrew Gallatin for providing FreeBSD/Alpha support. 79 */ 80 81 #include <sys/param.h> 82 #include <sys/systm.h> 83 #include <sys/sockio.h> 84 #include <sys/mbuf.h> 85 #include <sys/malloc.h> 86 #include <sys/kernel.h> 87 #include <sys/socket.h> 88 #include <sys/queue.h> 89 #include <sys/serialize.h> 90 #include <sys/bus.h> 91 #include <sys/rman.h> 92 #include <sys/interrupt.h> 93 94 #include <net/if.h> 95 #include <net/ifq_var.h> 96 #include <net/if_arp.h> 97 #include <net/ethernet.h> 98 #include <net/if_dl.h> 99 #include <net/if_media.h> 100 #include <net/if_types.h> 101 #include <net/vlan/if_vlan_var.h> 102 #include <net/vlan/if_vlan_ether.h> 103 104 #include <net/bpf.h> 105 106 #include <netinet/in_systm.h> 107 #include <netinet/in.h> 108 #include <netinet/ip.h> 109 110 #include <vm/vm.h> /* for vtophys */ 111 #include <vm/pmap.h> /* for vtophys */ 112 113 #include <bus/pci/pcireg.h> 114 #include <bus/pci/pcivar.h> 115 116 #include "if_tireg.h" 117 #include "ti_fw.h" 118 #include "ti_fw2.h" 119 120 /* 121 * Temporarily disable the checksum offload support for now. 122 * Tests with ftp.freesoftware.com show that after about 12 hours, 123 * the firmware will begin calculating completely bogus TX checksums 124 * and refuse to stop until the interface is reset. Unfortunately, 125 * there isn't enough time to fully debug this before the 4.1 126 * release, so this will need to stay off for now. 127 */ 128 #ifdef notdef 129 #define TI_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_IP_FRAGS) 130 #else 131 #define TI_CSUM_FEATURES 0 132 #endif 133 134 /* 135 * Various supported device vendors/types and their names. 136 */ 137 138 static struct ti_type ti_devs[] = { 139 { ALT_VENDORID, ALT_DEVICEID_ACENIC, 140 "Alteon AceNIC 1000baseSX Gigabit Ethernet" }, 141 { ALT_VENDORID, ALT_DEVICEID_ACENIC_COPPER, 142 "Alteon AceNIC 1000baseT Gigabit Ethernet" }, 143 { TC_VENDORID, TC_DEVICEID_3C985, 144 "3Com 3c985-SX Gigabit Ethernet" }, 145 { NG_VENDORID, NG_DEVICEID_GA620, 146 "Netgear GA620 1000baseSX Gigabit Ethernet" }, 147 { NG_VENDORID, NG_DEVICEID_GA620T, 148 "Netgear GA620 1000baseT Gigabit Ethernet" }, 149 { SGI_VENDORID, SGI_DEVICEID_TIGON, 150 "Silicon Graphics Gigabit Ethernet" }, 151 { DEC_VENDORID, DEC_DEVICEID_FARALLON_PN9000SX, 152 "Farallon PN9000SX Gigabit Ethernet" }, 153 { 0, 0, NULL } 154 }; 155 156 static int ti_probe(device_t); 157 static int ti_attach(device_t); 158 static int ti_detach(device_t); 159 static void ti_txeof(struct ti_softc *); 160 static void ti_rxeof(struct ti_softc *); 161 162 static void ti_stats_update(struct ti_softc *); 163 static int ti_encap(struct ti_softc *, struct mbuf *, uint32_t *); 164 165 static void ti_intr(void *); 166 static void ti_start(struct ifnet *, struct ifaltq_subque *); 167 static int ti_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *); 168 static void ti_init(void *); 169 static void ti_init2(struct ti_softc *); 170 static void ti_stop(struct ti_softc *); 171 static void ti_watchdog(struct ifnet *); 172 static void ti_shutdown(device_t); 173 static int ti_ifmedia_upd(struct ifnet *); 174 static void ti_ifmedia_sts(struct ifnet *, struct ifmediareq *); 175 176 static uint32_t ti_eeprom_putbyte(struct ti_softc *, int); 177 static uint8_t ti_eeprom_getbyte(struct ti_softc *, int, uint8_t *); 178 static int ti_read_eeprom(struct ti_softc *, caddr_t, int, int); 179 180 static void ti_add_mcast(struct ti_softc *, struct ether_addr *); 181 static void ti_del_mcast(struct ti_softc *, struct ether_addr *); 182 static void ti_setmulti(struct ti_softc *); 183 184 static void ti_mem(struct ti_softc *, uint32_t, uint32_t, caddr_t); 185 static void ti_loadfw(struct ti_softc *); 186 static void ti_cmd(struct ti_softc *, struct ti_cmd_desc *); 187 static void ti_cmd_ext(struct ti_softc *, struct ti_cmd_desc *, 188 caddr_t, int); 189 static void ti_handle_events(struct ti_softc *); 190 static int ti_alloc_jumbo_mem(struct ti_softc *); 191 static struct ti_jslot * 192 ti_jalloc(struct ti_softc *); 193 static void ti_jfree(void *); 194 static void ti_jref(void *); 195 static int ti_newbuf_std(struct ti_softc *, int, struct mbuf *); 196 static int ti_newbuf_mini(struct ti_softc *, int, struct mbuf *); 197 static int ti_newbuf_jumbo(struct ti_softc *, int, struct mbuf *); 198 static int ti_init_rx_ring_std(struct ti_softc *); 199 static void ti_free_rx_ring_std(struct ti_softc *); 200 static int ti_init_rx_ring_jumbo(struct ti_softc *); 201 static void ti_free_rx_ring_jumbo(struct ti_softc *); 202 static int ti_init_rx_ring_mini(struct ti_softc *); 203 static void ti_free_rx_ring_mini(struct ti_softc *); 204 static void ti_free_tx_ring(struct ti_softc *); 205 static int ti_init_tx_ring(struct ti_softc *); 206 207 static int ti_64bitslot_war(struct ti_softc *); 208 static int ti_chipinit(struct ti_softc *); 209 static int ti_gibinit(struct ti_softc *); 210 211 static device_method_t ti_methods[] = { 212 /* Device interface */ 213 DEVMETHOD(device_probe, ti_probe), 214 DEVMETHOD(device_attach, ti_attach), 215 DEVMETHOD(device_detach, ti_detach), 216 DEVMETHOD(device_shutdown, ti_shutdown), 217 DEVMETHOD_END 218 }; 219 220 221 static DEFINE_CLASS_0(ti, ti_driver, ti_methods, sizeof(struct ti_softc)); 222 static devclass_t ti_devclass; 223 224 DECLARE_DUMMY_MODULE(if_ti); 225 DRIVER_MODULE(if_ti, pci, ti_driver, ti_devclass, NULL, NULL); 226 227 /* 228 * Send an instruction or address to the EEPROM, check for ACK. 229 */ 230 static uint32_t 231 ti_eeprom_putbyte(struct ti_softc *sc, int byte) 232 { 233 int ack = 0, i; 234 235 /* 236 * Make sure we're in TX mode. 237 */ 238 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 239 240 /* 241 * Feed in each bit and stobe the clock. 242 */ 243 for (i = 0x80; i; i >>= 1) { 244 if (byte & i) 245 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); 246 else 247 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); 248 DELAY(1); 249 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 250 DELAY(1); 251 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 252 } 253 254 /* 255 * Turn off TX mode. 256 */ 257 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 258 259 /* 260 * Check for ack. 261 */ 262 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 263 ack = CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN; 264 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 265 266 return(ack); 267 } 268 269 /* 270 * Read a byte of data stored in the EEPROM at address 'addr.' 271 * We have to send two address bytes since the EEPROM can hold 272 * more than 256 bytes of data. 273 */ 274 static uint8_t 275 ti_eeprom_getbyte(struct ti_softc *sc, int addr, uint8_t *dest) 276 { 277 struct ifnet *ifp = &sc->arpcom.ac_if; 278 int i; 279 uint8_t byte = 0; 280 281 EEPROM_START; 282 283 /* 284 * Send write control code to EEPROM. 285 */ 286 if (ti_eeprom_putbyte(sc, EEPROM_CTL_WRITE)) { 287 if_printf(ifp, "failed to send write command, status: %x\n", 288 CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 289 return(1); 290 } 291 292 /* 293 * Send first byte of address of byte we want to read. 294 */ 295 if (ti_eeprom_putbyte(sc, (addr >> 8) & 0xFF)) { 296 if_printf(ifp, "failed to send address, status: %x\n", 297 CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 298 return(1); 299 } 300 /* 301 * Send second byte address of byte we want to read. 302 */ 303 if (ti_eeprom_putbyte(sc, addr & 0xFF)) { 304 if_printf(ifp, "failed to send address, status: %x\n", 305 CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 306 return(1); 307 } 308 309 EEPROM_STOP; 310 EEPROM_START; 311 /* 312 * Send read control code to EEPROM. 313 */ 314 if (ti_eeprom_putbyte(sc, EEPROM_CTL_READ)) { 315 if_printf(ifp, "failed to send read command, status: %x\n", 316 CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 317 return(1); 318 } 319 320 /* 321 * Start reading bits from EEPROM. 322 */ 323 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 324 for (i = 0x80; i; i >>= 1) { 325 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 326 DELAY(1); 327 if (CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN) 328 byte |= i; 329 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 330 DELAY(1); 331 } 332 333 EEPROM_STOP; 334 335 /* 336 * No ACK generated for read, so just return byte. 337 */ 338 339 *dest = byte; 340 341 return(0); 342 } 343 344 /* 345 * Read a sequence of bytes from the EEPROM. 346 */ 347 static int 348 ti_read_eeprom(struct ti_softc *sc, caddr_t dest, int off, int cnt) 349 { 350 int err = 0, i; 351 uint8_t byte = 0; 352 353 for (i = 0; i < cnt; i++) { 354 err = ti_eeprom_getbyte(sc, off + i, &byte); 355 if (err) 356 break; 357 *(dest + i) = byte; 358 } 359 360 return(err ? 1 : 0); 361 } 362 363 /* 364 * NIC memory access function. Can be used to either clear a section 365 * of NIC local memory or (if buf is non-NULL) copy data into it. 366 */ 367 static void 368 ti_mem(struct ti_softc *sc, uint32_t addr, uint32_t len, caddr_t buf) 369 { 370 int cnt, segptr, segsize; 371 caddr_t ti_winbase, ptr; 372 373 segptr = addr; 374 cnt = len; 375 ti_winbase = (caddr_t)(sc->ti_vhandle + TI_WINDOW); 376 ptr = buf; 377 378 while(cnt) { 379 if (cnt < TI_WINLEN) 380 segsize = cnt; 381 else 382 segsize = TI_WINLEN - (segptr % TI_WINLEN); 383 CSR_WRITE_4(sc, TI_WINBASE, rounddown2(segptr, TI_WINLEN)); 384 if (buf == NULL) 385 bzero((char *)ti_winbase + (segptr & 386 (TI_WINLEN - 1)), segsize); 387 else { 388 bcopy((char *)ptr, (char *)ti_winbase + 389 (segptr & (TI_WINLEN - 1)), segsize); 390 ptr += segsize; 391 } 392 segptr += segsize; 393 cnt -= segsize; 394 } 395 } 396 397 /* 398 * Load firmware image into the NIC. Check that the firmware revision 399 * is acceptable and see if we want the firmware for the Tigon 1 or 400 * Tigon 2. 401 */ 402 static void 403 ti_loadfw(struct ti_softc *sc) 404 { 405 struct ifnet *ifp = &sc->arpcom.ac_if; 406 407 switch(sc->ti_hwrev) { 408 case TI_HWREV_TIGON: 409 if (tigonFwReleaseMajor != TI_FIRMWARE_MAJOR || 410 tigonFwReleaseMinor != TI_FIRMWARE_MINOR || 411 tigonFwReleaseFix != TI_FIRMWARE_FIX) { 412 if_printf(ifp, "firmware revision mismatch; want " 413 "%d.%d.%d, got %d.%d.%d\n", 414 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR, 415 TI_FIRMWARE_FIX, tigonFwReleaseMajor, 416 tigonFwReleaseMinor, tigonFwReleaseFix); 417 return; 418 } 419 ti_mem(sc, tigonFwTextAddr, tigonFwTextLen, 420 (caddr_t)tigonFwText); 421 ti_mem(sc, tigonFwDataAddr, tigonFwDataLen, 422 (caddr_t)tigonFwData); 423 ti_mem(sc, tigonFwRodataAddr, tigonFwRodataLen, 424 (caddr_t)tigonFwRodata); 425 ti_mem(sc, tigonFwBssAddr, tigonFwBssLen, NULL); 426 ti_mem(sc, tigonFwSbssAddr, tigonFwSbssLen, NULL); 427 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigonFwStartAddr); 428 break; 429 case TI_HWREV_TIGON_II: 430 if (tigon2FwReleaseMajor != TI_FIRMWARE_MAJOR || 431 tigon2FwReleaseMinor != TI_FIRMWARE_MINOR || 432 tigon2FwReleaseFix != TI_FIRMWARE_FIX) { 433 if_printf(ifp, "firmware revision mismatch; want " 434 "%d.%d.%d, got %d.%d.%d\n", 435 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR, 436 TI_FIRMWARE_FIX, tigon2FwReleaseMajor, 437 tigon2FwReleaseMinor, tigon2FwReleaseFix); 438 return; 439 } 440 ti_mem(sc, tigon2FwTextAddr, tigon2FwTextLen, 441 (caddr_t)tigon2FwText); 442 ti_mem(sc, tigon2FwDataAddr, tigon2FwDataLen, 443 (caddr_t)tigon2FwData); 444 ti_mem(sc, tigon2FwRodataAddr, tigon2FwRodataLen, 445 (caddr_t)tigon2FwRodata); 446 ti_mem(sc, tigon2FwBssAddr, tigon2FwBssLen, NULL); 447 ti_mem(sc, tigon2FwSbssAddr, tigon2FwSbssLen, NULL); 448 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigon2FwStartAddr); 449 break; 450 default: 451 if_printf(ifp, "can't load firmware: unknown hardware rev\n"); 452 break; 453 } 454 } 455 456 /* 457 * Send the NIC a command via the command ring. 458 */ 459 static void 460 ti_cmd(struct ti_softc *sc, struct ti_cmd_desc *cmd) 461 { 462 uint32_t index; 463 464 if (sc->ti_rdata->ti_cmd_ring == NULL) 465 return; 466 467 index = sc->ti_cmd_saved_prodidx; 468 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(uint32_t *)(cmd)); 469 TI_INC(index, TI_CMD_RING_CNT); 470 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index); 471 sc->ti_cmd_saved_prodidx = index; 472 } 473 474 /* 475 * Send the NIC an extended command. The 'len' parameter specifies the 476 * number of command slots to include after the initial command. 477 */ 478 static void 479 ti_cmd_ext(struct ti_softc *sc, struct ti_cmd_desc *cmd, caddr_t arg, int len) 480 { 481 uint32_t index; 482 int i; 483 484 if (sc->ti_rdata->ti_cmd_ring == NULL) 485 return; 486 487 index = sc->ti_cmd_saved_prodidx; 488 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(uint32_t *)(cmd)); 489 TI_INC(index, TI_CMD_RING_CNT); 490 for (i = 0; i < len; i++) { 491 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), 492 *(uint32_t *)(&arg[i * 4])); 493 TI_INC(index, TI_CMD_RING_CNT); 494 } 495 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index); 496 sc->ti_cmd_saved_prodidx = index; 497 } 498 499 /* 500 * Handle events that have triggered interrupts. 501 */ 502 static void 503 ti_handle_events(struct ti_softc *sc) 504 { 505 struct ifnet *ifp = &sc->arpcom.ac_if; 506 struct ti_event_desc *e; 507 508 if (sc->ti_rdata->ti_event_ring == NULL) 509 return; 510 511 while (sc->ti_ev_saved_considx != sc->ti_ev_prodidx.ti_idx) { 512 e = &sc->ti_rdata->ti_event_ring[sc->ti_ev_saved_considx]; 513 switch(e->ti_event) { 514 case TI_EV_LINKSTAT_CHANGED: 515 sc->ti_linkstat = e->ti_code; 516 if (e->ti_code == TI_EV_CODE_LINK_UP) { 517 if_printf(ifp, "10/100 link up\n"); 518 } else if (e->ti_code == TI_EV_CODE_GIG_LINK_UP) { 519 if_printf(ifp, "gigabit link up\n"); 520 } else if (e->ti_code == TI_EV_CODE_LINK_DOWN) { 521 if_printf(ifp, "link down\n"); 522 } 523 break; 524 case TI_EV_ERROR: 525 if (e->ti_code == TI_EV_CODE_ERR_INVAL_CMD) { 526 if_printf(ifp, "invalid command\n"); 527 } else if (e->ti_code == TI_EV_CODE_ERR_UNIMP_CMD) { 528 if_printf(ifp, "unknown command\n"); 529 } else if (e->ti_code == TI_EV_CODE_ERR_BADCFG) { 530 if_printf(ifp, "bad config data\n"); 531 } 532 break; 533 case TI_EV_FIRMWARE_UP: 534 ti_init2(sc); 535 break; 536 case TI_EV_STATS_UPDATED: 537 ti_stats_update(sc); 538 break; 539 case TI_EV_RESET_JUMBO_RING: 540 case TI_EV_MCAST_UPDATED: 541 /* Who cares. */ 542 break; 543 default: 544 if_printf(ifp, "unknown event: %d\n", e->ti_event); 545 break; 546 } 547 /* Advance the consumer index. */ 548 TI_INC(sc->ti_ev_saved_considx, TI_EVENT_RING_CNT); 549 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, sc->ti_ev_saved_considx); 550 } 551 } 552 553 /* 554 * Memory management for the jumbo receive ring is a pain in the 555 * butt. We need to allocate at least 9018 bytes of space per frame, 556 * _and_ it has to be contiguous (unless you use the extended 557 * jumbo descriptor format). Using malloc() all the time won't 558 * work: malloc() allocates memory in powers of two, which means we 559 * would end up wasting a considerable amount of space by allocating 560 * 9K chunks. We don't have a jumbo mbuf cluster pool. Thus, we have 561 * to do our own memory management. 562 * 563 * The driver needs to allocate a contiguous chunk of memory at boot 564 * time. We then chop this up ourselves into 9K pieces and use them 565 * as external mbuf storage. 566 * 567 * One issue here is how much memory to allocate. The jumbo ring has 568 * 256 slots in it, but at 9K per slot than can consume over 2MB of 569 * RAM. This is a bit much, especially considering we also need 570 * RAM for the standard ring and mini ring (on the Tigon 2). To 571 * save space, we only actually allocate enough memory for 64 slots 572 * by default, which works out to between 500 and 600K. This can 573 * be tuned by changing a #define in if_tireg.h. 574 */ 575 576 static int 577 ti_alloc_jumbo_mem(struct ti_softc *sc) 578 { 579 struct ti_jslot *entry; 580 caddr_t ptr; 581 int i; 582 583 /* Grab a big chunk o' storage. */ 584 sc->ti_cdata.ti_jumbo_buf = contigmalloc(TI_JMEM, M_DEVBUF, 585 M_WAITOK, 0, 0xffffffff, PAGE_SIZE, 0); 586 587 if (sc->ti_cdata.ti_jumbo_buf == NULL) { 588 if_printf(&sc->arpcom.ac_if, "no memory for jumbo buffers!\n"); 589 return(ENOBUFS); 590 } 591 592 lwkt_serialize_init(&sc->ti_jslot_serializer); 593 SLIST_INIT(&sc->ti_jfree_listhead); 594 595 /* 596 * Now divide it up into 9K pieces and save the addresses 597 * in an array. Note that we play an evil trick here by using 598 * the first few bytes in the buffer to hold the the address 599 * of the softc structure for this interface. This is because 600 * ti_jfree() needs it, but it is called by the mbuf management 601 * code which will not pass it to us explicitly. 602 */ 603 ptr = sc->ti_cdata.ti_jumbo_buf; 604 for (i = 0; i < TI_JSLOTS; i++) { 605 entry = &sc->ti_cdata.ti_jslots[i]; 606 entry->ti_sc = sc; 607 entry->ti_buf = ptr; 608 entry->ti_inuse = 0; 609 entry->ti_slot = i; 610 SLIST_INSERT_HEAD(&sc->ti_jfree_listhead, entry, jslot_link); 611 ptr += TI_JLEN; 612 } 613 614 return(0); 615 } 616 617 /* 618 * Allocate a jumbo buffer. 619 */ 620 static struct ti_jslot * 621 ti_jalloc(struct ti_softc *sc) 622 { 623 struct ti_jslot *entry; 624 625 lwkt_serialize_enter(&sc->ti_jslot_serializer); 626 entry = SLIST_FIRST(&sc->ti_jfree_listhead); 627 if (entry) { 628 SLIST_REMOVE_HEAD(&sc->ti_jfree_listhead, jslot_link); 629 entry->ti_inuse = 1; 630 } else { 631 if_printf(&sc->arpcom.ac_if, "no free jumbo buffers\n"); 632 } 633 lwkt_serialize_exit(&sc->ti_jslot_serializer); 634 return(entry); 635 } 636 637 /* 638 * Adjust usage count on a jumbo buffer. In general this doesn't 639 * get used much because our jumbo buffers don't get passed around 640 * too much, but it's implemented for correctness. 641 */ 642 static void 643 ti_jref(void *arg) 644 { 645 struct ti_jslot *entry = (struct ti_jslot *)arg; 646 struct ti_softc *sc = entry->ti_sc; 647 648 if (sc == NULL) 649 panic("ti_jref: can't find softc pointer!"); 650 651 if (&sc->ti_cdata.ti_jslots[entry->ti_slot] != entry) 652 panic("ti_jref: asked to reference buffer " 653 "that we don't manage!"); 654 if (entry->ti_inuse == 0) 655 panic("ti_jref: buffer already free!"); 656 atomic_add_int(&entry->ti_inuse, 1); 657 } 658 659 /* 660 * Release a jumbo buffer. 661 */ 662 static void 663 ti_jfree(void *arg) 664 { 665 struct ti_jslot *entry = (struct ti_jslot *)arg; 666 struct ti_softc *sc = entry->ti_sc; 667 668 if (sc == NULL) 669 panic("ti_jref: can't find softc pointer!"); 670 671 if (&sc->ti_cdata.ti_jslots[entry->ti_slot] != entry) 672 panic("ti_jref: asked to reference buffer " 673 "that we don't manage!"); 674 if (entry->ti_inuse == 0) 675 panic("ti_jref: buffer already free!"); 676 lwkt_serialize_enter(&sc->ti_jslot_serializer); 677 atomic_subtract_int(&entry->ti_inuse, 1); 678 if (entry->ti_inuse == 0) 679 SLIST_INSERT_HEAD(&sc->ti_jfree_listhead, entry, jslot_link); 680 lwkt_serialize_exit(&sc->ti_jslot_serializer); 681 } 682 683 684 /* 685 * Intialize a standard receive ring descriptor. 686 */ 687 static int 688 ti_newbuf_std(struct ti_softc *sc, int i, struct mbuf *m) 689 { 690 struct mbuf *m_new; 691 struct ti_rx_desc *r; 692 693 if (m == NULL) { 694 m_new = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 695 if (m_new == NULL) 696 return (ENOBUFS); 697 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 698 } else { 699 m_new = m; 700 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 701 m_new->m_data = m_new->m_ext.ext_buf; 702 } 703 704 705 m_adj(m_new, ETHER_ALIGN); 706 sc->ti_cdata.ti_rx_std_chain[i] = m_new; 707 r = &sc->ti_rdata->ti_rx_std_ring[i]; 708 TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t)); 709 r->ti_type = TI_BDTYPE_RECV_BD; 710 r->ti_flags = 0; 711 if (sc->arpcom.ac_if.if_hwassist) 712 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM; 713 r->ti_len = m_new->m_len; 714 r->ti_idx = i; 715 716 return(0); 717 } 718 719 /* 720 * Intialize a mini receive ring descriptor. This only applies to 721 * the Tigon 2. 722 */ 723 static int 724 ti_newbuf_mini(struct ti_softc *sc, int i, struct mbuf *m) 725 { 726 struct mbuf *m_new; 727 struct ti_rx_desc *r; 728 729 if (m == NULL) { 730 MGETHDR(m_new, M_NOWAIT, MT_DATA); 731 if (m_new == NULL) { 732 return(ENOBUFS); 733 } 734 m_new->m_len = m_new->m_pkthdr.len = MHLEN; 735 } else { 736 m_new = m; 737 m_new->m_data = m_new->m_pktdat; 738 m_new->m_len = m_new->m_pkthdr.len = MHLEN; 739 } 740 741 m_adj(m_new, ETHER_ALIGN); 742 r = &sc->ti_rdata->ti_rx_mini_ring[i]; 743 sc->ti_cdata.ti_rx_mini_chain[i] = m_new; 744 TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t)); 745 r->ti_type = TI_BDTYPE_RECV_BD; 746 r->ti_flags = TI_BDFLAG_MINI_RING; 747 if (sc->arpcom.ac_if.if_hwassist) 748 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM; 749 r->ti_len = m_new->m_len; 750 r->ti_idx = i; 751 752 return(0); 753 } 754 755 /* 756 * Initialize a jumbo receive ring descriptor. This allocates 757 * a jumbo buffer from the pool managed internally by the driver. 758 */ 759 static int 760 ti_newbuf_jumbo(struct ti_softc *sc, int i, struct mbuf *m) 761 { 762 struct mbuf *m_new; 763 struct ti_rx_desc *r; 764 struct ti_jslot *buf; 765 766 if (m == NULL) { 767 /* Allocate the mbuf. */ 768 MGETHDR(m_new, M_NOWAIT, MT_DATA); 769 if (m_new == NULL) { 770 return(ENOBUFS); 771 } 772 773 /* Allocate the jumbo buffer */ 774 buf = ti_jalloc(sc); 775 if (buf == NULL) { 776 m_freem(m_new); 777 if_printf(&sc->arpcom.ac_if, "jumbo allocation failed " 778 "-- packet dropped!\n"); 779 return(ENOBUFS); 780 } 781 782 /* Attach the buffer to the mbuf. */ 783 m_new->m_ext.ext_arg = buf; 784 m_new->m_ext.ext_buf = buf->ti_buf; 785 m_new->m_ext.ext_free = ti_jfree; 786 m_new->m_ext.ext_ref = ti_jref; 787 m_new->m_ext.ext_size = TI_JUMBO_FRAMELEN; 788 789 m_new->m_flags |= M_EXT; 790 } else { 791 /* 792 * We're re-using a previously allocated mbuf; 793 * be sure to re-init pointers and lengths to 794 * default values. 795 */ 796 KKASSERT(m->m_flags & M_EXT); 797 m_new = m; 798 } 799 m_new->m_data = m_new->m_ext.ext_buf; 800 m_new->m_len = m_new->m_pkthdr.len = m_new->m_ext.ext_size; 801 802 m_adj(m_new, ETHER_ALIGN); 803 /* Set up the descriptor. */ 804 r = &sc->ti_rdata->ti_rx_jumbo_ring[i]; 805 sc->ti_cdata.ti_rx_jumbo_chain[i] = m_new; 806 TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t)); 807 r->ti_type = TI_BDTYPE_RECV_JUMBO_BD; 808 r->ti_flags = TI_BDFLAG_JUMBO_RING; 809 if (sc->arpcom.ac_if.if_hwassist) 810 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM; 811 r->ti_len = m_new->m_len; 812 r->ti_idx = i; 813 814 return(0); 815 } 816 817 /* 818 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 819 * that's 1MB or memory, which is a lot. For now, we fill only the first 820 * 256 ring entries and hope that our CPU is fast enough to keep up with 821 * the NIC. 822 */ 823 static int 824 ti_init_rx_ring_std(struct ti_softc *sc) 825 { 826 int i; 827 struct ti_cmd_desc cmd; 828 829 for (i = 0; i < TI_SSLOTS; i++) { 830 if (ti_newbuf_std(sc, i, NULL) == ENOBUFS) 831 return(ENOBUFS); 832 } 833 834 TI_UPDATE_STDPROD(sc, i - 1); 835 sc->ti_std = i - 1; 836 837 return(0); 838 } 839 840 static void 841 ti_free_rx_ring_std(struct ti_softc *sc) 842 { 843 int i; 844 845 for (i = 0; i < TI_STD_RX_RING_CNT; i++) { 846 if (sc->ti_cdata.ti_rx_std_chain[i] != NULL) { 847 m_freem(sc->ti_cdata.ti_rx_std_chain[i]); 848 sc->ti_cdata.ti_rx_std_chain[i] = NULL; 849 } 850 bzero(&sc->ti_rdata->ti_rx_std_ring[i], 851 sizeof(struct ti_rx_desc)); 852 } 853 } 854 855 static int 856 ti_init_rx_ring_jumbo(struct ti_softc *sc) 857 { 858 int i; 859 struct ti_cmd_desc cmd; 860 861 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) { 862 if (ti_newbuf_jumbo(sc, i, NULL) == ENOBUFS) 863 return(ENOBUFS); 864 } 865 866 TI_UPDATE_JUMBOPROD(sc, i - 1); 867 sc->ti_jumbo = i - 1; 868 869 return(0); 870 } 871 872 static void 873 ti_free_rx_ring_jumbo(struct ti_softc *sc) 874 { 875 int i; 876 877 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) { 878 if (sc->ti_cdata.ti_rx_jumbo_chain[i] != NULL) { 879 m_freem(sc->ti_cdata.ti_rx_jumbo_chain[i]); 880 sc->ti_cdata.ti_rx_jumbo_chain[i] = NULL; 881 } 882 bzero(&sc->ti_rdata->ti_rx_jumbo_ring[i], 883 sizeof(struct ti_rx_desc)); 884 } 885 } 886 887 static int 888 ti_init_rx_ring_mini(struct ti_softc *sc) 889 { 890 int i; 891 892 for (i = 0; i < TI_MSLOTS; i++) { 893 if (ti_newbuf_mini(sc, i, NULL) == ENOBUFS) 894 return(ENOBUFS); 895 } 896 897 TI_UPDATE_MINIPROD(sc, i - 1); 898 sc->ti_mini = i - 1; 899 900 return(0); 901 } 902 903 static void 904 ti_free_rx_ring_mini(struct ti_softc *sc) 905 { 906 int i; 907 908 for (i = 0; i < TI_MINI_RX_RING_CNT; i++) { 909 if (sc->ti_cdata.ti_rx_mini_chain[i] != NULL) { 910 m_freem(sc->ti_cdata.ti_rx_mini_chain[i]); 911 sc->ti_cdata.ti_rx_mini_chain[i] = NULL; 912 } 913 bzero(&sc->ti_rdata->ti_rx_mini_ring[i], 914 sizeof(struct ti_rx_desc)); 915 } 916 } 917 918 static void 919 ti_free_tx_ring(struct ti_softc *sc) 920 { 921 int i; 922 923 if (sc->ti_rdata->ti_tx_ring == NULL) 924 return; 925 926 for (i = 0; i < TI_TX_RING_CNT; i++) { 927 if (sc->ti_cdata.ti_tx_chain[i] != NULL) { 928 m_freem(sc->ti_cdata.ti_tx_chain[i]); 929 sc->ti_cdata.ti_tx_chain[i] = NULL; 930 } 931 bzero(&sc->ti_rdata->ti_tx_ring[i], 932 sizeof(struct ti_tx_desc)); 933 } 934 } 935 936 static int 937 ti_init_tx_ring(struct ti_softc *sc) 938 { 939 sc->ti_txcnt = 0; 940 sc->ti_tx_saved_considx = 0; 941 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, 0); 942 return(0); 943 } 944 945 /* 946 * The Tigon 2 firmware has a new way to add/delete multicast addresses, 947 * but we have to support the old way too so that Tigon 1 cards will 948 * work. 949 */ 950 static void 951 ti_add_mcast(struct ti_softc *sc, struct ether_addr *addr) 952 { 953 struct ti_cmd_desc cmd; 954 uint16_t *m; 955 uint32_t ext[2] = {0, 0}; 956 957 m = (uint16_t *)&addr->octet[0]; 958 959 switch(sc->ti_hwrev) { 960 case TI_HWREV_TIGON: 961 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0])); 962 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2])); 963 TI_DO_CMD(TI_CMD_ADD_MCAST_ADDR, 0, 0); 964 break; 965 case TI_HWREV_TIGON_II: 966 ext[0] = htons(m[0]); 967 ext[1] = (htons(m[1]) << 16) | htons(m[2]); 968 TI_DO_CMD_EXT(TI_CMD_EXT_ADD_MCAST, 0, 0, (caddr_t)&ext, 2); 969 break; 970 default: 971 if_printf(&sc->arpcom.ac_if, "unknown hwrev\n"); 972 break; 973 } 974 } 975 976 static void 977 ti_del_mcast(struct ti_softc *sc, struct ether_addr *addr) 978 { 979 struct ti_cmd_desc cmd; 980 uint16_t *m; 981 uint32_t ext[2] = {0, 0}; 982 983 m = (uint16_t *)&addr->octet[0]; 984 985 switch(sc->ti_hwrev) { 986 case TI_HWREV_TIGON: 987 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0])); 988 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2])); 989 TI_DO_CMD(TI_CMD_DEL_MCAST_ADDR, 0, 0); 990 break; 991 case TI_HWREV_TIGON_II: 992 ext[0] = htons(m[0]); 993 ext[1] = (htons(m[1]) << 16) | htons(m[2]); 994 TI_DO_CMD_EXT(TI_CMD_EXT_DEL_MCAST, 0, 0, (caddr_t)&ext, 2); 995 break; 996 default: 997 if_printf(&sc->arpcom.ac_if, "unknown hwrev\n"); 998 break; 999 } 1000 } 1001 1002 /* 1003 * Configure the Tigon's multicast address filter. 1004 * 1005 * The actual multicast table management is a bit of a pain, thanks to 1006 * slight brain damage on the part of both Alteon and us. With our 1007 * multicast code, we are only alerted when the multicast address table 1008 * changes and at that point we only have the current list of addresses: 1009 * we only know the current state, not the previous state, so we don't 1010 * actually know what addresses were removed or added. The firmware has 1011 * state, but we can't get our grubby mits on it, and there is no 'delete 1012 * all multicast addresses' command. Hence, we have to maintain our own 1013 * state so we know what addresses have been programmed into the NIC at 1014 * any given time. 1015 */ 1016 static void 1017 ti_setmulti(struct ti_softc *sc) 1018 { 1019 struct ifnet *ifp = &sc->arpcom.ac_if; 1020 struct ifmultiaddr *ifma; 1021 struct ti_cmd_desc cmd; 1022 struct ti_mc_entry *mc; 1023 uint32_t intrs; 1024 1025 if (ifp->if_flags & IFF_ALLMULTI) { 1026 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_ENB, 0); 1027 return; 1028 } 1029 1030 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_DIS, 0); 1031 1032 /* Disable interrupts. */ 1033 intrs = CSR_READ_4(sc, TI_MB_HOSTINTR); 1034 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 1035 1036 /* First, zot all the existing filters. */ 1037 while (sc->ti_mc_listhead.slh_first != NULL) { 1038 mc = sc->ti_mc_listhead.slh_first; 1039 ti_del_mcast(sc, &mc->mc_addr); 1040 SLIST_REMOVE_HEAD(&sc->ti_mc_listhead, mc_entries); 1041 kfree(mc, M_DEVBUF); 1042 } 1043 1044 /* Now program new ones. */ 1045 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1046 if (ifma->ifma_addr->sa_family != AF_LINK) 1047 continue; 1048 mc = kmalloc(sizeof(struct ti_mc_entry), M_DEVBUF, M_INTWAIT); 1049 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 1050 &mc->mc_addr, ETHER_ADDR_LEN); 1051 SLIST_INSERT_HEAD(&sc->ti_mc_listhead, mc, mc_entries); 1052 ti_add_mcast(sc, &mc->mc_addr); 1053 } 1054 1055 /* Re-enable interrupts. */ 1056 CSR_WRITE_4(sc, TI_MB_HOSTINTR, intrs); 1057 } 1058 1059 /* 1060 * Check to see if the BIOS has configured us for a 64 bit slot when 1061 * we aren't actually in one. If we detect this condition, we can work 1062 * around it on the Tigon 2 by setting a bit in the PCI state register, 1063 * but for the Tigon 1 we must give up and abort the interface attach. 1064 */ 1065 static int 1066 ti_64bitslot_war(struct ti_softc *sc) 1067 { 1068 if ((CSR_READ_4(sc, TI_PCI_STATE) & TI_PCISTATE_32BIT_BUS) == 0) { 1069 CSR_WRITE_4(sc, 0x600, 0); 1070 CSR_WRITE_4(sc, 0x604, 0); 1071 CSR_WRITE_4(sc, 0x600, 0x5555AAAA); 1072 if (CSR_READ_4(sc, 0x604) == 0x5555AAAA) { 1073 if (sc->ti_hwrev == TI_HWREV_TIGON) 1074 return(EINVAL); 1075 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_32BIT_BUS); 1076 return(0); 1077 } 1078 } 1079 1080 return(0); 1081 } 1082 1083 /* 1084 * Do endian, PCI and DMA initialization. Also check the on-board ROM 1085 * self-test results. 1086 */ 1087 static int 1088 ti_chipinit(struct ti_softc *sc) 1089 { 1090 struct ifnet *ifp = &sc->arpcom.ac_if; 1091 uint32_t cacheline; 1092 uint32_t pci_writemax = 0; 1093 1094 /* Initialize link to down state. */ 1095 sc->ti_linkstat = TI_EV_CODE_LINK_DOWN; 1096 1097 if (ifp->if_capenable & IFCAP_HWCSUM) 1098 ifp->if_hwassist = TI_CSUM_FEATURES; 1099 else 1100 ifp->if_hwassist = 0; 1101 1102 /* Set endianness before we access any non-PCI registers. */ 1103 #if BYTE_ORDER == BIG_ENDIAN 1104 CSR_WRITE_4(sc, TI_MISC_HOST_CTL, 1105 TI_MHC_BIGENDIAN_INIT | (TI_MHC_BIGENDIAN_INIT << 24)); 1106 #else 1107 CSR_WRITE_4(sc, TI_MISC_HOST_CTL, 1108 TI_MHC_LITTLEENDIAN_INIT | (TI_MHC_LITTLEENDIAN_INIT << 24)); 1109 #endif 1110 1111 /* Check the ROM failed bit to see if self-tests passed. */ 1112 if (CSR_READ_4(sc, TI_CPU_STATE) & TI_CPUSTATE_ROMFAIL) { 1113 if_printf(ifp, "board self-diagnostics failed!\n"); 1114 return(ENODEV); 1115 } 1116 1117 /* Halt the CPU. */ 1118 TI_SETBIT(sc, TI_CPU_STATE, TI_CPUSTATE_HALT); 1119 1120 /* Figure out the hardware revision. */ 1121 switch(CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_CHIP_REV_MASK) { 1122 case TI_REV_TIGON_I: 1123 sc->ti_hwrev = TI_HWREV_TIGON; 1124 break; 1125 case TI_REV_TIGON_II: 1126 sc->ti_hwrev = TI_HWREV_TIGON_II; 1127 break; 1128 default: 1129 if_printf(ifp, "unsupported chip revision\n"); 1130 return(ENODEV); 1131 } 1132 1133 /* Do special setup for Tigon 2. */ 1134 if (sc->ti_hwrev == TI_HWREV_TIGON_II) { 1135 TI_SETBIT(sc, TI_CPU_CTL_B, TI_CPUSTATE_HALT); 1136 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_SRAM_BANK_512K); 1137 TI_SETBIT(sc, TI_MISC_CONF, TI_MCR_SRAM_SYNCHRONOUS); 1138 } 1139 1140 /* Set up the PCI state register. */ 1141 CSR_WRITE_4(sc, TI_PCI_STATE, TI_PCI_READ_CMD|TI_PCI_WRITE_CMD); 1142 if (sc->ti_hwrev == TI_HWREV_TIGON_II) { 1143 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_USE_MEM_RD_MULT); 1144 } 1145 1146 /* Clear the read/write max DMA parameters. */ 1147 TI_CLRBIT(sc, TI_PCI_STATE, (TI_PCISTATE_WRITE_MAXDMA| 1148 TI_PCISTATE_READ_MAXDMA)); 1149 1150 /* Get cache line size. */ 1151 cacheline = CSR_READ_4(sc, TI_PCI_BIST) & 0xFF; 1152 1153 /* 1154 * If the system has set enabled the PCI memory write 1155 * and invalidate command in the command register, set 1156 * the write max parameter accordingly. This is necessary 1157 * to use MWI with the Tigon 2. 1158 */ 1159 if (CSR_READ_4(sc, TI_PCI_CMDSTAT) & PCIM_CMD_MWIEN) { 1160 switch(cacheline) { 1161 case 1: 1162 case 4: 1163 case 8: 1164 case 16: 1165 case 32: 1166 case 64: 1167 break; 1168 default: 1169 /* Disable PCI memory write and invalidate. */ 1170 if (bootverbose) { 1171 if_printf(ifp, "cache line size %d not " 1172 "supported; disabling PCI MWI\n", 1173 cacheline); 1174 } 1175 CSR_WRITE_4(sc, TI_PCI_CMDSTAT, CSR_READ_4(sc, 1176 TI_PCI_CMDSTAT) & ~PCIM_CMD_MWIEN); 1177 break; 1178 } 1179 } 1180 1181 TI_SETBIT(sc, TI_PCI_STATE, pci_writemax); 1182 1183 /* This sets the min dma param all the way up (0xff). */ 1184 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_MINDMA); 1185 1186 /* Configure DMA variables. */ 1187 #if BYTE_ORDER == BIG_ENDIAN 1188 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_BD | 1189 TI_OPMODE_BYTESWAP_DATA | TI_OPMODE_WORDSWAP_BD | 1190 TI_OPMODE_WARN_ENB | TI_OPMODE_FATAL_ENB | 1191 TI_OPMODE_DONT_FRAG_JUMBO); 1192 #else 1193 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_DATA| 1194 TI_OPMODE_WORDSWAP_BD|TI_OPMODE_DONT_FRAG_JUMBO| 1195 TI_OPMODE_WARN_ENB|TI_OPMODE_FATAL_ENB); 1196 #endif 1197 1198 /* 1199 * Only allow 1 DMA channel to be active at a time. 1200 * I don't think this is a good idea, but without it 1201 * the firmware racks up lots of nicDmaReadRingFull 1202 * errors. This is not compatible with hardware checksums. 1203 */ 1204 if (ifp->if_hwassist == 0) 1205 TI_SETBIT(sc, TI_GCR_OPMODE, TI_OPMODE_1_DMA_ACTIVE); 1206 1207 /* Recommended settings from Tigon manual. */ 1208 CSR_WRITE_4(sc, TI_GCR_DMA_WRITECFG, TI_DMA_STATE_THRESH_8W); 1209 CSR_WRITE_4(sc, TI_GCR_DMA_READCFG, TI_DMA_STATE_THRESH_8W); 1210 1211 if (ti_64bitslot_war(sc)) { 1212 if_printf(ifp, "bios thinks we're in a 64 bit slot, " 1213 "but we aren't"); 1214 return(EINVAL); 1215 } 1216 1217 return(0); 1218 } 1219 1220 /* 1221 * Initialize the general information block and firmware, and 1222 * start the CPU(s) running. 1223 */ 1224 static int 1225 ti_gibinit(struct ti_softc *sc) 1226 { 1227 struct ifnet *ifp = &sc->arpcom.ac_if; 1228 struct ti_rcb *rcb; 1229 int i; 1230 1231 /* Disable interrupts for now. */ 1232 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 1233 1234 /* Tell the chip where to find the general information block. */ 1235 CSR_WRITE_4(sc, TI_GCR_GENINFO_HI, 0); 1236 CSR_WRITE_4(sc, TI_GCR_GENINFO_LO, vtophys(&sc->ti_rdata->ti_info)); 1237 1238 /* Load the firmware into SRAM. */ 1239 ti_loadfw(sc); 1240 1241 /* Set up the contents of the general info and ring control blocks. */ 1242 1243 /* Set up the event ring and producer pointer. */ 1244 rcb = &sc->ti_rdata->ti_info.ti_ev_rcb; 1245 1246 TI_HOSTADDR(rcb->ti_hostaddr) = vtophys(&sc->ti_rdata->ti_event_ring); 1247 rcb->ti_flags = 0; 1248 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_ev_prodidx_ptr) = 1249 vtophys(&sc->ti_ev_prodidx); 1250 sc->ti_ev_prodidx.ti_idx = 0; 1251 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, 0); 1252 sc->ti_ev_saved_considx = 0; 1253 1254 /* Set up the command ring and producer mailbox. */ 1255 rcb = &sc->ti_rdata->ti_info.ti_cmd_rcb; 1256 1257 sc->ti_rdata->ti_cmd_ring = 1258 (struct ti_cmd_desc *)(sc->ti_vhandle + TI_GCR_CMDRING); 1259 TI_HOSTADDR(rcb->ti_hostaddr) = TI_GCR_NIC_ADDR(TI_GCR_CMDRING); 1260 rcb->ti_flags = 0; 1261 rcb->ti_max_len = 0; 1262 for (i = 0; i < TI_CMD_RING_CNT; i++) 1263 CSR_WRITE_4(sc, TI_GCR_CMDRING + (i * 4), 0); 1264 CSR_WRITE_4(sc, TI_GCR_CMDCONS_IDX, 0); 1265 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, 0); 1266 sc->ti_cmd_saved_prodidx = 0; 1267 1268 /* 1269 * Assign the address of the stats refresh buffer. 1270 * We re-use the current stats buffer for this to 1271 * conserve memory. 1272 */ 1273 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_refresh_stats_ptr) = 1274 vtophys(&sc->ti_rdata->ti_info.ti_stats); 1275 1276 /* Set up the standard receive ring. */ 1277 rcb = &sc->ti_rdata->ti_info.ti_std_rx_rcb; 1278 TI_HOSTADDR(rcb->ti_hostaddr) = vtophys(&sc->ti_rdata->ti_rx_std_ring); 1279 rcb->ti_max_len = TI_FRAMELEN; 1280 rcb->ti_flags = 0; 1281 if (ifp->if_hwassist) 1282 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 1283 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 1284 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1285 1286 /* Set up the jumbo receive ring. */ 1287 rcb = &sc->ti_rdata->ti_info.ti_jumbo_rx_rcb; 1288 TI_HOSTADDR(rcb->ti_hostaddr) = 1289 vtophys(&sc->ti_rdata->ti_rx_jumbo_ring); 1290 rcb->ti_max_len = TI_JUMBO_FRAMELEN; 1291 rcb->ti_flags = 0; 1292 if (ifp->if_hwassist) 1293 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 1294 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 1295 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1296 1297 /* 1298 * Set up the mini ring. Only activated on the 1299 * Tigon 2 but the slot in the config block is 1300 * still there on the Tigon 1. 1301 */ 1302 rcb = &sc->ti_rdata->ti_info.ti_mini_rx_rcb; 1303 TI_HOSTADDR(rcb->ti_hostaddr) = 1304 vtophys(&sc->ti_rdata->ti_rx_mini_ring); 1305 rcb->ti_max_len = MHLEN - ETHER_ALIGN; 1306 if (sc->ti_hwrev == TI_HWREV_TIGON) 1307 rcb->ti_flags = TI_RCB_FLAG_RING_DISABLED; 1308 else 1309 rcb->ti_flags = 0; 1310 if (ifp->if_hwassist) 1311 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 1312 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 1313 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1314 1315 /* 1316 * Set up the receive return ring. 1317 */ 1318 rcb = &sc->ti_rdata->ti_info.ti_return_rcb; 1319 TI_HOSTADDR(rcb->ti_hostaddr) = 1320 vtophys(&sc->ti_rdata->ti_rx_return_ring); 1321 rcb->ti_flags = 0; 1322 rcb->ti_max_len = TI_RETURN_RING_CNT; 1323 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_return_prodidx_ptr) = 1324 vtophys(&sc->ti_return_prodidx); 1325 1326 /* 1327 * Set up the tx ring. Note: for the Tigon 2, we have the option 1328 * of putting the transmit ring in the host's address space and 1329 * letting the chip DMA it instead of leaving the ring in the NIC's 1330 * memory and accessing it through the shared memory region. We 1331 * do this for the Tigon 2, but it doesn't work on the Tigon 1, 1332 * so we have to revert to the shared memory scheme if we detect 1333 * a Tigon 1 chip. 1334 */ 1335 CSR_WRITE_4(sc, TI_WINBASE, TI_TX_RING_BASE); 1336 if (sc->ti_hwrev == TI_HWREV_TIGON) { 1337 sc->ti_rdata->ti_tx_ring_nic = 1338 (struct ti_tx_desc *)(sc->ti_vhandle + TI_WINDOW); 1339 } 1340 bzero(sc->ti_rdata->ti_tx_ring, 1341 TI_TX_RING_CNT * sizeof(struct ti_tx_desc)); 1342 rcb = &sc->ti_rdata->ti_info.ti_tx_rcb; 1343 if (sc->ti_hwrev == TI_HWREV_TIGON) 1344 rcb->ti_flags = 0; 1345 else 1346 rcb->ti_flags = TI_RCB_FLAG_HOST_RING; 1347 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1348 if (ifp->if_hwassist) 1349 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 1350 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 1351 rcb->ti_max_len = TI_TX_RING_CNT; 1352 if (sc->ti_hwrev == TI_HWREV_TIGON) 1353 TI_HOSTADDR(rcb->ti_hostaddr) = TI_TX_RING_BASE; 1354 else 1355 TI_HOSTADDR(rcb->ti_hostaddr) = 1356 vtophys(&sc->ti_rdata->ti_tx_ring); 1357 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_tx_considx_ptr) = 1358 vtophys(&sc->ti_tx_considx); 1359 1360 /* Set up tuneables */ 1361 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 1362 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, 1363 (sc->ti_rx_coal_ticks / 10)); 1364 else 1365 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, sc->ti_rx_coal_ticks); 1366 CSR_WRITE_4(sc, TI_GCR_TX_COAL_TICKS, sc->ti_tx_coal_ticks); 1367 CSR_WRITE_4(sc, TI_GCR_STAT_TICKS, sc->ti_stat_ticks); 1368 CSR_WRITE_4(sc, TI_GCR_RX_MAX_COAL_BD, sc->ti_rx_max_coal_bds); 1369 CSR_WRITE_4(sc, TI_GCR_TX_MAX_COAL_BD, sc->ti_tx_max_coal_bds); 1370 CSR_WRITE_4(sc, TI_GCR_TX_BUFFER_RATIO, sc->ti_tx_buf_ratio); 1371 1372 /* Turn interrupts on. */ 1373 CSR_WRITE_4(sc, TI_GCR_MASK_INTRS, 0); 1374 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 1375 1376 /* Start CPU. */ 1377 TI_CLRBIT(sc, TI_CPU_STATE, (TI_CPUSTATE_HALT|TI_CPUSTATE_STEP)); 1378 1379 return(0); 1380 } 1381 1382 /* 1383 * Probe for a Tigon chip. Check the PCI vendor and device IDs 1384 * against our list and return its name if we find a match. 1385 */ 1386 static int 1387 ti_probe(device_t dev) 1388 { 1389 struct ti_type *t; 1390 uint16_t vendor, product; 1391 1392 vendor = pci_get_vendor(dev); 1393 product = pci_get_device(dev); 1394 1395 for (t = ti_devs; t->ti_name != NULL; t++) { 1396 if (vendor == t->ti_vid && product == t->ti_did) { 1397 device_set_desc(dev, t->ti_name); 1398 return(0); 1399 } 1400 } 1401 1402 return(ENXIO); 1403 } 1404 1405 static int 1406 ti_attach(device_t dev) 1407 { 1408 struct ti_softc *sc; 1409 struct ifnet *ifp; 1410 int error = 0, rid; 1411 uint8_t eaddr[ETHER_ADDR_LEN]; 1412 1413 sc = device_get_softc(dev); 1414 ifp = &sc->arpcom.ac_if; 1415 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1416 ifp->if_capabilities = IFCAP_HWCSUM | 1417 IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU; 1418 ifp->if_capenable = ifp->if_capabilities; 1419 1420 pci_enable_busmaster(dev); 1421 1422 /* 1423 * Initialize media before any possible error may occur, 1424 * so we can destroy it unconditionally, if an error occurs later on. 1425 */ 1426 ifmedia_init(&sc->ifmedia, IFM_IMASK, ti_ifmedia_upd, ti_ifmedia_sts); 1427 1428 rid = TI_PCI_LOMEM; 1429 sc->ti_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 1430 RF_ACTIVE); 1431 1432 if (sc->ti_res == NULL) { 1433 device_printf(dev, "couldn't map memory\n"); 1434 error = ENXIO; 1435 goto fail; 1436 } 1437 1438 sc->ti_btag = rman_get_bustag(sc->ti_res); 1439 sc->ti_bhandle = rman_get_bushandle(sc->ti_res); 1440 sc->ti_vhandle = (vm_offset_t)rman_get_virtual(sc->ti_res); 1441 1442 /* Allocate interrupt */ 1443 rid = 0; 1444 sc->ti_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1445 RF_SHAREABLE | RF_ACTIVE); 1446 if (sc->ti_irq == NULL) { 1447 device_printf(dev, "couldn't map interrupt\n"); 1448 error = ENXIO; 1449 goto fail; 1450 } 1451 1452 if (ti_chipinit(sc)) { 1453 device_printf(dev, "chip initialization failed\n"); 1454 error = ENXIO; 1455 goto fail; 1456 } 1457 1458 /* Zero out the NIC's on-board SRAM. */ 1459 ti_mem(sc, 0x2000, 0x100000 - 0x2000, NULL); 1460 1461 /* Init again -- zeroing memory may have clobbered some registers. */ 1462 if (ti_chipinit(sc)) { 1463 device_printf(dev, "chip initialization failed\n"); 1464 error = ENXIO; 1465 goto fail; 1466 } 1467 1468 /* 1469 * Get station address from the EEPROM. Note: the manual states 1470 * that the MAC address is at offset 0x8c, however the data is 1471 * stored as two longwords (since that's how it's loaded into 1472 * the NIC). This means the MAC address is actually preceeded 1473 * by two zero bytes. We need to skip over those. 1474 */ 1475 if (ti_read_eeprom(sc, eaddr, TI_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) { 1476 device_printf(dev, "failed to read station address\n"); 1477 error = ENXIO; 1478 goto fail; 1479 } 1480 1481 /* Allocate the general information block and ring buffers. */ 1482 sc->ti_rdata = contigmalloc(sizeof(struct ti_ring_data), M_DEVBUF, 1483 M_WAITOK | M_ZERO, 0, 0xffffffff, PAGE_SIZE, 0); 1484 1485 if (sc->ti_rdata == NULL) { 1486 device_printf(dev, "no memory for list buffers!\n"); 1487 error = ENXIO; 1488 goto fail; 1489 } 1490 1491 /* Try to allocate memory for jumbo buffers. */ 1492 if (ti_alloc_jumbo_mem(sc)) { 1493 device_printf(dev, "jumbo buffer allocation failed\n"); 1494 error = ENXIO; 1495 goto fail; 1496 } 1497 1498 /* 1499 * We really need a better way to tell a 1000baseT card 1500 * from a 1000baseSX one, since in theory there could be 1501 * OEMed 1000baseT cards from lame vendors who aren't 1502 * clever enough to change the PCI ID. For the moment 1503 * though, the AceNIC is the only copper card available. 1504 */ 1505 if (pci_get_vendor(dev) == ALT_VENDORID && 1506 pci_get_device(dev) == ALT_DEVICEID_ACENIC_COPPER) 1507 sc->ti_copper = 1; 1508 /* Ok, it's not the only copper card available. */ 1509 if (pci_get_vendor(dev) == NG_VENDORID && 1510 pci_get_device(dev) == NG_DEVICEID_GA620T) 1511 sc->ti_copper = 1; 1512 1513 /* Set default tuneable values. */ 1514 sc->ti_stat_ticks = 2 * TI_TICKS_PER_SEC; 1515 sc->ti_rx_coal_ticks = TI_TICKS_PER_SEC / 5000; 1516 sc->ti_tx_coal_ticks = TI_TICKS_PER_SEC / 500; 1517 sc->ti_rx_max_coal_bds = 64; 1518 sc->ti_tx_max_coal_bds = 128; 1519 sc->ti_tx_buf_ratio = 21; 1520 1521 /* Set up ifnet structure */ 1522 ifp->if_softc = sc; 1523 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1524 ifp->if_ioctl = ti_ioctl; 1525 ifp->if_start = ti_start; 1526 ifp->if_watchdog = ti_watchdog; 1527 ifp->if_init = ti_init; 1528 ifp->if_mtu = ETHERMTU; 1529 ifq_set_maxlen(&ifp->if_snd, TI_TX_RING_CNT - 1); 1530 ifq_set_ready(&ifp->if_snd); 1531 1532 /* Set up ifmedia support. */ 1533 if (sc->ti_copper) { 1534 /* 1535 * Copper cards allow manual 10/100 mode selection, 1536 * but not manual 1000baseT mode selection. Why? 1537 * Becuase currently there's no way to specify the 1538 * master/slave setting through the firmware interface, 1539 * so Alteon decided to just bag it and handle it 1540 * via autonegotiation. 1541 */ 1542 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL); 1543 ifmedia_add(&sc->ifmedia, 1544 IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL); 1545 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_TX, 0, NULL); 1546 ifmedia_add(&sc->ifmedia, 1547 IFM_ETHER|IFM_100_TX|IFM_FDX, 0, NULL); 1548 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_1000_T, 0, NULL); 1549 ifmedia_add(&sc->ifmedia, 1550 IFM_ETHER|IFM_1000_T | IFM_FDX, 0, NULL); 1551 } else { 1552 /* Fiber cards don't support 10/100 modes. */ 1553 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL); 1554 ifmedia_add(&sc->ifmedia, 1555 IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL); 1556 } 1557 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 1558 ifmedia_set(&sc->ifmedia, IFM_ETHER|IFM_AUTO); 1559 1560 /* 1561 * Call MI attach routine. 1562 */ 1563 ether_ifattach(ifp, eaddr, NULL); 1564 1565 ifq_set_cpuid(&ifp->if_snd, rman_get_cpuid(sc->ti_irq)); 1566 1567 error = bus_setup_intr(dev, sc->ti_irq, INTR_MPSAFE, 1568 ti_intr, sc, &sc->ti_intrhand, 1569 ifp->if_serializer); 1570 if (error) { 1571 device_printf(dev, "couldn't set up irq\n"); 1572 ether_ifdetach(ifp); 1573 goto fail; 1574 } 1575 1576 return 0; 1577 fail: 1578 ti_detach(dev); 1579 return(error); 1580 } 1581 1582 static int 1583 ti_detach(device_t dev) 1584 { 1585 struct ti_softc *sc = device_get_softc(dev); 1586 struct ifnet *ifp = &sc->arpcom.ac_if; 1587 1588 if (device_is_attached(dev)) { 1589 lwkt_serialize_enter(ifp->if_serializer); 1590 ti_stop(sc); 1591 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 1592 lwkt_serialize_exit(ifp->if_serializer); 1593 1594 ether_ifdetach(ifp); 1595 } 1596 1597 if (sc->ti_irq != NULL) 1598 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 1599 if (sc->ti_res != NULL) { 1600 bus_release_resource(dev, SYS_RES_MEMORY, 1601 TI_PCI_LOMEM, sc->ti_res); 1602 } 1603 if (sc->ti_cdata.ti_jumbo_buf != NULL) 1604 contigfree(sc->ti_cdata.ti_jumbo_buf, TI_JMEM, M_DEVBUF); 1605 if (sc->ti_rdata != NULL) 1606 contigfree(sc->ti_rdata, sizeof(struct ti_ring_data), M_DEVBUF); 1607 ifmedia_removeall(&sc->ifmedia); 1608 1609 1610 return(0); 1611 } 1612 1613 /* 1614 * Frame reception handling. This is called if there's a frame 1615 * on the receive return list. 1616 * 1617 * Note: we have to be able to handle three possibilities here: 1618 * 1) the frame is from the mini receive ring (can only happen) 1619 * on Tigon 2 boards) 1620 * 2) the frame is from the jumbo recieve ring 1621 * 3) the frame is from the standard receive ring 1622 */ 1623 static void 1624 ti_rxeof(struct ti_softc *sc) 1625 { 1626 struct ifnet *ifp = &sc->arpcom.ac_if; 1627 struct ti_cmd_desc cmd; 1628 1629 while(sc->ti_rx_saved_considx != sc->ti_return_prodidx.ti_idx) { 1630 struct ti_rx_desc *cur_rx; 1631 uint32_t rxidx; 1632 struct mbuf *m; 1633 uint16_t vlan_tag = 0; 1634 int have_tag = 0; 1635 1636 cur_rx = 1637 &sc->ti_rdata->ti_rx_return_ring[sc->ti_rx_saved_considx]; 1638 rxidx = cur_rx->ti_idx; 1639 TI_INC(sc->ti_rx_saved_considx, TI_RETURN_RING_CNT); 1640 1641 if (cur_rx->ti_flags & TI_BDFLAG_VLAN_TAG) { 1642 have_tag = 1; 1643 vlan_tag = cur_rx->ti_vlan_tag & 0xfff; 1644 } 1645 1646 if (cur_rx->ti_flags & TI_BDFLAG_JUMBO_RING) { 1647 TI_INC(sc->ti_jumbo, TI_JUMBO_RX_RING_CNT); 1648 m = sc->ti_cdata.ti_rx_jumbo_chain[rxidx]; 1649 sc->ti_cdata.ti_rx_jumbo_chain[rxidx] = NULL; 1650 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 1651 IFNET_STAT_INC(ifp, ierrors, 1); 1652 ti_newbuf_jumbo(sc, sc->ti_jumbo, m); 1653 continue; 1654 } 1655 if (ti_newbuf_jumbo(sc, sc->ti_jumbo, NULL) == ENOBUFS) { 1656 IFNET_STAT_INC(ifp, ierrors, 1); 1657 ti_newbuf_jumbo(sc, sc->ti_jumbo, m); 1658 continue; 1659 } 1660 } else if (cur_rx->ti_flags & TI_BDFLAG_MINI_RING) { 1661 TI_INC(sc->ti_mini, TI_MINI_RX_RING_CNT); 1662 m = sc->ti_cdata.ti_rx_mini_chain[rxidx]; 1663 sc->ti_cdata.ti_rx_mini_chain[rxidx] = NULL; 1664 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 1665 IFNET_STAT_INC(ifp, ierrors, 1); 1666 ti_newbuf_mini(sc, sc->ti_mini, m); 1667 continue; 1668 } 1669 if (ti_newbuf_mini(sc, sc->ti_mini, NULL) == ENOBUFS) { 1670 IFNET_STAT_INC(ifp, ierrors, 1); 1671 ti_newbuf_mini(sc, sc->ti_mini, m); 1672 continue; 1673 } 1674 } else { 1675 TI_INC(sc->ti_std, TI_STD_RX_RING_CNT); 1676 m = sc->ti_cdata.ti_rx_std_chain[rxidx]; 1677 sc->ti_cdata.ti_rx_std_chain[rxidx] = NULL; 1678 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 1679 IFNET_STAT_INC(ifp, ierrors, 1); 1680 ti_newbuf_std(sc, sc->ti_std, m); 1681 continue; 1682 } 1683 if (ti_newbuf_std(sc, sc->ti_std, NULL) == ENOBUFS) { 1684 IFNET_STAT_INC(ifp, ierrors, 1); 1685 ti_newbuf_std(sc, sc->ti_std, m); 1686 continue; 1687 } 1688 } 1689 1690 m->m_pkthdr.len = m->m_len = cur_rx->ti_len; 1691 IFNET_STAT_INC(ifp, ipackets, 1); 1692 m->m_pkthdr.rcvif = ifp; 1693 1694 if (ifp->if_hwassist) { 1695 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED | 1696 CSUM_DATA_VALID; 1697 if ((cur_rx->ti_ip_cksum ^ 0xffff) == 0) 1698 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1699 m->m_pkthdr.csum_data = cur_rx->ti_tcp_udp_cksum; 1700 } 1701 1702 if (have_tag) { 1703 m->m_flags |= M_VLANTAG; 1704 m->m_pkthdr.ether_vlantag = vlan_tag; 1705 } 1706 ifp->if_input(ifp, m, NULL, -1); 1707 } 1708 1709 /* Only necessary on the Tigon 1. */ 1710 if (sc->ti_hwrev == TI_HWREV_TIGON) 1711 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 1712 sc->ti_rx_saved_considx); 1713 1714 TI_UPDATE_STDPROD(sc, sc->ti_std); 1715 TI_UPDATE_MINIPROD(sc, sc->ti_mini); 1716 TI_UPDATE_JUMBOPROD(sc, sc->ti_jumbo); 1717 } 1718 1719 static void 1720 ti_txeof(struct ti_softc *sc) 1721 { 1722 struct ifnet *ifp = &sc->arpcom.ac_if; 1723 struct ti_tx_desc *cur_tx = NULL; 1724 1725 /* 1726 * Go through our tx ring and free mbufs for those 1727 * frames that have been sent. 1728 */ 1729 while (sc->ti_tx_saved_considx != sc->ti_tx_considx.ti_idx) { 1730 uint32_t idx = 0; 1731 1732 idx = sc->ti_tx_saved_considx; 1733 if (sc->ti_hwrev == TI_HWREV_TIGON) { 1734 if (idx > 383) 1735 CSR_WRITE_4(sc, TI_WINBASE, 1736 TI_TX_RING_BASE + 6144); 1737 else if (idx > 255) 1738 CSR_WRITE_4(sc, TI_WINBASE, 1739 TI_TX_RING_BASE + 4096); 1740 else if (idx > 127) 1741 CSR_WRITE_4(sc, TI_WINBASE, 1742 TI_TX_RING_BASE + 2048); 1743 else 1744 CSR_WRITE_4(sc, TI_WINBASE, 1745 TI_TX_RING_BASE); 1746 cur_tx = &sc->ti_rdata->ti_tx_ring_nic[idx % 128]; 1747 } else 1748 cur_tx = &sc->ti_rdata->ti_tx_ring[idx]; 1749 if (cur_tx->ti_flags & TI_BDFLAG_END) 1750 IFNET_STAT_INC(ifp, opackets, 1); 1751 if (sc->ti_cdata.ti_tx_chain[idx] != NULL) { 1752 m_freem(sc->ti_cdata.ti_tx_chain[idx]); 1753 sc->ti_cdata.ti_tx_chain[idx] = NULL; 1754 } 1755 sc->ti_txcnt--; 1756 TI_INC(sc->ti_tx_saved_considx, TI_TX_RING_CNT); 1757 ifp->if_timer = 0; 1758 } 1759 1760 if (cur_tx != NULL) 1761 ifq_clr_oactive(&ifp->if_snd); 1762 } 1763 1764 static void 1765 ti_intr(void *xsc) 1766 { 1767 struct ti_softc *sc = xsc; 1768 struct ifnet *ifp = &sc->arpcom.ac_if; 1769 1770 #ifdef notdef 1771 /* Avoid this for now -- checking this register is expensive. */ 1772 /* Make sure this is really our interrupt. */ 1773 if ((CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_INTSTATE) == 0) 1774 return; 1775 #endif 1776 1777 /* Ack interrupt and stop others from occuring. */ 1778 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 1779 1780 if (ifp->if_flags & IFF_RUNNING) { 1781 /* Check RX return ring producer/consumer */ 1782 ti_rxeof(sc); 1783 1784 /* Check TX ring producer/consumer */ 1785 ti_txeof(sc); 1786 } 1787 1788 ti_handle_events(sc); 1789 1790 /* Re-enable interrupts. */ 1791 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 1792 1793 if ((ifp->if_flags & IFF_RUNNING) && !ifq_is_empty(&ifp->if_snd)) 1794 if_devstart(ifp); 1795 } 1796 1797 static void 1798 ti_stats_update(struct ti_softc *sc) 1799 { 1800 struct ifnet *ifp = &sc->arpcom.ac_if; 1801 1802 IFNET_STAT_SET(ifp, collisions, 1803 (sc->ti_rdata->ti_info.ti_stats.dot3StatsSingleCollisionFrames + 1804 sc->ti_rdata->ti_info.ti_stats.dot3StatsMultipleCollisionFrames + 1805 sc->ti_rdata->ti_info.ti_stats.dot3StatsExcessiveCollisions + 1806 sc->ti_rdata->ti_info.ti_stats.dot3StatsLateCollisions)); 1807 } 1808 1809 /* 1810 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 1811 * pointers to descriptors. 1812 */ 1813 static int 1814 ti_encap(struct ti_softc *sc, struct mbuf *m_head, uint32_t *txidx) 1815 { 1816 struct ti_tx_desc *f = NULL; 1817 struct mbuf *m; 1818 uint32_t cnt = 0, cur, frag; 1819 uint16_t csum_flags = 0, vlan_tag = 0, vlan_flag = 0; 1820 1821 if (m_head->m_flags & M_VLANTAG) { 1822 vlan_tag = m_head->m_pkthdr.ether_vlantag; 1823 vlan_flag = TI_BDFLAG_VLAN_TAG; 1824 } 1825 1826 m = m_head; 1827 cur = frag = *txidx; 1828 1829 if (m_head->m_pkthdr.csum_flags) { 1830 if (m_head->m_pkthdr.csum_flags & CSUM_IP) 1831 csum_flags |= TI_BDFLAG_IP_CKSUM; 1832 if (m_head->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) 1833 csum_flags |= TI_BDFLAG_TCP_UDP_CKSUM; 1834 if (m_head->m_flags & M_LASTFRAG) 1835 csum_flags |= TI_BDFLAG_IP_FRAG_END; 1836 else if (m_head->m_flags & M_FRAG) 1837 csum_flags |= TI_BDFLAG_IP_FRAG; 1838 } 1839 /* 1840 * Start packing the mbufs in this chain into 1841 * the fragment pointers. Stop when we run out 1842 * of fragments or hit the end of the mbuf chain. 1843 */ 1844 for (m = m_head; m != NULL; m = m->m_next) { 1845 if (m->m_len != 0) { 1846 if (sc->ti_hwrev == TI_HWREV_TIGON) { 1847 if (frag > 383) 1848 CSR_WRITE_4(sc, TI_WINBASE, 1849 TI_TX_RING_BASE + 6144); 1850 else if (frag > 255) 1851 CSR_WRITE_4(sc, TI_WINBASE, 1852 TI_TX_RING_BASE + 4096); 1853 else if (frag > 127) 1854 CSR_WRITE_4(sc, TI_WINBASE, 1855 TI_TX_RING_BASE + 2048); 1856 else 1857 CSR_WRITE_4(sc, TI_WINBASE, 1858 TI_TX_RING_BASE); 1859 f = &sc->ti_rdata->ti_tx_ring_nic[frag % 128]; 1860 } else 1861 f = &sc->ti_rdata->ti_tx_ring[frag]; 1862 if (sc->ti_cdata.ti_tx_chain[frag] != NULL) 1863 break; 1864 TI_HOSTADDR(f->ti_addr) = vtophys(mtod(m, vm_offset_t)); 1865 f->ti_len = m->m_len; 1866 f->ti_flags = csum_flags | vlan_flag; 1867 f->ti_vlan_tag = vlan_tag & 0xfff; 1868 1869 /* 1870 * Sanity check: avoid coming within 16 descriptors 1871 * of the end of the ring. 1872 */ 1873 if ((TI_TX_RING_CNT - (sc->ti_txcnt + cnt)) < 16) 1874 return(ENOBUFS); 1875 cur = frag; 1876 TI_INC(frag, TI_TX_RING_CNT); 1877 cnt++; 1878 } 1879 } 1880 1881 if (m != NULL) 1882 return(ENOBUFS); 1883 1884 if (frag == sc->ti_tx_saved_considx) 1885 return(ENOBUFS); 1886 1887 if (sc->ti_hwrev == TI_HWREV_TIGON) 1888 sc->ti_rdata->ti_tx_ring_nic[cur % 128].ti_flags |= 1889 TI_BDFLAG_END; 1890 else 1891 sc->ti_rdata->ti_tx_ring[cur].ti_flags |= TI_BDFLAG_END; 1892 sc->ti_cdata.ti_tx_chain[cur] = m_head; 1893 sc->ti_txcnt += cnt; 1894 1895 *txidx = frag; 1896 1897 return(0); 1898 } 1899 1900 /* 1901 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1902 * to the mbuf data regions directly in the transmit descriptors. 1903 */ 1904 static void 1905 ti_start(struct ifnet *ifp, struct ifaltq_subque *ifsq) 1906 { 1907 struct ti_softc *sc = ifp->if_softc; 1908 struct mbuf *m_head = NULL; 1909 uint32_t prodidx = 0; 1910 int need_trans; 1911 1912 ASSERT_ALTQ_SQ_DEFAULT(ifp, ifsq); 1913 1914 prodidx = CSR_READ_4(sc, TI_MB_SENDPROD_IDX); 1915 1916 need_trans = 0; 1917 while(sc->ti_cdata.ti_tx_chain[prodidx] == NULL) { 1918 m_head = ifq_dequeue(&ifp->if_snd); 1919 if (m_head == NULL) 1920 break; 1921 1922 /* 1923 * XXX 1924 * safety overkill. If this is a fragmented packet chain 1925 * with delayed TCP/UDP checksums, then only encapsulate 1926 * it if we have enough descriptors to handle the entire 1927 * chain at once. 1928 * (paranoia -- may not actually be needed) 1929 */ 1930 if (m_head->m_flags & M_FIRSTFRAG && 1931 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) { 1932 if ((TI_TX_RING_CNT - sc->ti_txcnt) < 1933 m_head->m_pkthdr.csum_data + 16) { 1934 ifq_set_oactive(&ifp->if_snd); 1935 ifq_prepend(&ifp->if_snd, m_head); 1936 break; 1937 } 1938 } 1939 1940 /* 1941 * Pack the data into the transmit ring. If we 1942 * don't have room, set the OACTIVE flag and wait 1943 * for the NIC to drain the ring. 1944 */ 1945 if (ti_encap(sc, m_head, &prodidx)) { 1946 ifq_set_oactive(&ifp->if_snd); 1947 ifq_prepend(&ifp->if_snd, m_head); 1948 break; 1949 } 1950 need_trans = 1; 1951 1952 ETHER_BPF_MTAP(ifp, m_head); 1953 } 1954 1955 if (!need_trans) 1956 return; 1957 1958 /* Transmit */ 1959 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, prodidx); 1960 1961 /* 1962 * Set a timeout in case the chip goes out to lunch. 1963 */ 1964 ifp->if_timer = 5; 1965 } 1966 1967 static void 1968 ti_init(void *xsc) 1969 { 1970 struct ti_softc *sc = xsc; 1971 1972 /* Cancel pending I/O and flush buffers. */ 1973 ti_stop(sc); 1974 1975 /* Init the gen info block, ring control blocks and firmware. */ 1976 if (ti_gibinit(sc)) { 1977 if_printf(&sc->arpcom.ac_if, "initialization failure\n"); 1978 return; 1979 } 1980 } 1981 1982 static void 1983 ti_init2(struct ti_softc *sc) 1984 { 1985 struct ifnet *ifp = &sc->arpcom.ac_if; 1986 struct ti_cmd_desc cmd; 1987 uint16_t *m; 1988 struct ifmedia *ifm; 1989 int tmp; 1990 1991 /* Specify MTU and interface index. */ 1992 CSR_WRITE_4(sc, TI_GCR_IFINDEX, ifp->if_dunit); 1993 CSR_WRITE_4(sc, TI_GCR_IFMTU, ifp->if_mtu + 1994 ETHER_HDR_LEN + ETHER_CRC_LEN); 1995 TI_DO_CMD(TI_CMD_UPDATE_GENCOM, 0, 0); 1996 1997 /* Load our MAC address. */ 1998 m = (uint16_t *)&sc->arpcom.ac_enaddr[0]; 1999 CSR_WRITE_4(sc, TI_GCR_PAR0, htons(m[0])); 2000 CSR_WRITE_4(sc, TI_GCR_PAR1, (htons(m[1]) << 16) | htons(m[2])); 2001 TI_DO_CMD(TI_CMD_SET_MAC_ADDR, 0, 0); 2002 2003 /* Enable or disable promiscuous mode as needed. */ 2004 if (ifp->if_flags & IFF_PROMISC) 2005 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_ENB, 0); 2006 else 2007 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_DIS, 0); 2008 2009 /* Program multicast filter. */ 2010 ti_setmulti(sc); 2011 2012 /* 2013 * If this is a Tigon 1, we should tell the 2014 * firmware to use software packet filtering. 2015 */ 2016 if (sc->ti_hwrev == TI_HWREV_TIGON) 2017 TI_DO_CMD(TI_CMD_FDR_FILTERING, TI_CMD_CODE_FILT_ENB, 0); 2018 2019 /* Init RX ring. */ 2020 ti_init_rx_ring_std(sc); 2021 2022 /* Init jumbo RX ring. */ 2023 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 2024 ti_init_rx_ring_jumbo(sc); 2025 2026 /* 2027 * If this is a Tigon 2, we can also configure the 2028 * mini ring. 2029 */ 2030 if (sc->ti_hwrev == TI_HWREV_TIGON_II) 2031 ti_init_rx_ring_mini(sc); 2032 2033 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 0); 2034 sc->ti_rx_saved_considx = 0; 2035 2036 /* Init TX ring. */ 2037 ti_init_tx_ring(sc); 2038 2039 /* Tell firmware we're alive. */ 2040 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_UP, 0); 2041 2042 /* Enable host interrupts. */ 2043 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 2044 2045 ifp->if_flags |= IFF_RUNNING; 2046 ifq_clr_oactive(&ifp->if_snd); 2047 2048 /* 2049 * Make sure to set media properly. We have to do this 2050 * here since we have to issue commands in order to set 2051 * the link negotiation and we can't issue commands until 2052 * the firmware is running. 2053 */ 2054 ifm = &sc->ifmedia; 2055 tmp = ifm->ifm_media; 2056 ifm->ifm_media = ifm->ifm_cur->ifm_media; 2057 ti_ifmedia_upd(ifp); 2058 ifm->ifm_media = tmp; 2059 } 2060 2061 /* 2062 * Set media options. 2063 */ 2064 static int 2065 ti_ifmedia_upd(struct ifnet *ifp) 2066 { 2067 struct ti_softc *sc = ifp->if_softc; 2068 struct ifmedia *ifm = &sc->ifmedia; 2069 struct ti_cmd_desc cmd; 2070 2071 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 2072 return(EINVAL); 2073 2074 switch(IFM_SUBTYPE(ifm->ifm_media)) { 2075 case IFM_AUTO: 2076 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF | TI_GLNK_1000MB | 2077 TI_GLNK_FULL_DUPLEX | TI_GLNK_RX_FLOWCTL_Y | 2078 TI_GLNK_AUTONEGENB | TI_GLNK_ENB); 2079 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_100MB | TI_LNK_10MB | 2080 TI_LNK_FULL_DUPLEX | TI_LNK_HALF_DUPLEX | 2081 TI_LNK_AUTONEGENB | TI_LNK_ENB); 2082 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 2083 TI_CMD_CODE_NEGOTIATE_BOTH, 0); 2084 break; 2085 case IFM_1000_SX: 2086 case IFM_1000_T: 2087 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB | 2088 TI_GLNK_RX_FLOWCTL_Y | TI_GLNK_ENB); 2089 CSR_WRITE_4(sc, TI_GCR_LINK, 0); 2090 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 2091 TI_SETBIT(sc, TI_GCR_GLINK, TI_GLNK_FULL_DUPLEX); 2092 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 2093 TI_CMD_CODE_NEGOTIATE_GIGABIT, 0); 2094 break; 2095 case IFM_100_FX: 2096 case IFM_10_FL: 2097 case IFM_100_TX: 2098 case IFM_10_T: 2099 CSR_WRITE_4(sc, TI_GCR_GLINK, 0); 2100 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_ENB | TI_LNK_PREF); 2101 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_100_FX || 2102 IFM_SUBTYPE(ifm->ifm_media) == IFM_100_TX) 2103 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_100MB); 2104 else 2105 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_10MB); 2106 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 2107 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_FULL_DUPLEX); 2108 else 2109 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_HALF_DUPLEX); 2110 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 2111 TI_CMD_CODE_NEGOTIATE_10_100, 0); 2112 break; 2113 } 2114 2115 return(0); 2116 } 2117 2118 /* 2119 * Report current media status. 2120 */ 2121 static void 2122 ti_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 2123 { 2124 struct ti_softc *sc = ifp->if_softc; 2125 uint32_t media = 0; 2126 2127 ifmr->ifm_status = IFM_AVALID; 2128 ifmr->ifm_active = IFM_ETHER; 2129 2130 if (sc->ti_linkstat == TI_EV_CODE_LINK_DOWN) 2131 return; 2132 2133 ifmr->ifm_status |= IFM_ACTIVE; 2134 2135 if (sc->ti_linkstat == TI_EV_CODE_GIG_LINK_UP) { 2136 media = CSR_READ_4(sc, TI_GCR_GLINK_STAT); 2137 if (sc->ti_copper) 2138 ifmr->ifm_active |= IFM_1000_T; 2139 else 2140 ifmr->ifm_active |= IFM_1000_SX; 2141 if (media & TI_GLNK_FULL_DUPLEX) 2142 ifmr->ifm_active |= IFM_FDX; 2143 else 2144 ifmr->ifm_active |= IFM_HDX; 2145 } else if (sc->ti_linkstat == TI_EV_CODE_LINK_UP) { 2146 media = CSR_READ_4(sc, TI_GCR_LINK_STAT); 2147 if (sc->ti_copper) { 2148 if (media & TI_LNK_100MB) 2149 ifmr->ifm_active |= IFM_100_TX; 2150 if (media & TI_LNK_10MB) 2151 ifmr->ifm_active |= IFM_10_T; 2152 } else { 2153 if (media & TI_LNK_100MB) 2154 ifmr->ifm_active |= IFM_100_FX; 2155 if (media & TI_LNK_10MB) 2156 ifmr->ifm_active |= IFM_10_FL; 2157 } 2158 if (media & TI_LNK_FULL_DUPLEX) 2159 ifmr->ifm_active |= IFM_FDX; 2160 if (media & TI_LNK_HALF_DUPLEX) 2161 ifmr->ifm_active |= IFM_HDX; 2162 } 2163 } 2164 2165 static int 2166 ti_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr) 2167 { 2168 struct ti_softc *sc = ifp->if_softc; 2169 struct ifreq *ifr = (struct ifreq *) data; 2170 struct ti_cmd_desc cmd; 2171 int error = 0, mask; 2172 2173 switch(command) { 2174 case SIOCSIFMTU: 2175 if (ifr->ifr_mtu > TI_JUMBO_MTU) 2176 error = EINVAL; 2177 else { 2178 ifp->if_mtu = ifr->ifr_mtu; 2179 ti_init(sc); 2180 } 2181 break; 2182 case SIOCSIFFLAGS: 2183 if (ifp->if_flags & IFF_UP) { 2184 /* 2185 * If only the state of the PROMISC flag changed, 2186 * then just use the 'set promisc mode' command 2187 * instead of reinitializing the entire NIC. Doing 2188 * a full re-init means reloading the firmware and 2189 * waiting for it to start up, which may take a 2190 * second or two. 2191 */ 2192 if (ifp->if_flags & IFF_RUNNING && 2193 ifp->if_flags & IFF_PROMISC && 2194 !(sc->ti_if_flags & IFF_PROMISC)) { 2195 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, 2196 TI_CMD_CODE_PROMISC_ENB, 0); 2197 } else if (ifp->if_flags & IFF_RUNNING && 2198 !(ifp->if_flags & IFF_PROMISC) && 2199 sc->ti_if_flags & IFF_PROMISC) { 2200 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, 2201 TI_CMD_CODE_PROMISC_DIS, 0); 2202 } else 2203 ti_init(sc); 2204 } else if (ifp->if_flags & IFF_RUNNING) { 2205 ti_stop(sc); 2206 } 2207 sc->ti_if_flags = ifp->if_flags; 2208 error = 0; 2209 break; 2210 case SIOCADDMULTI: 2211 case SIOCDELMULTI: 2212 if (ifp->if_flags & IFF_RUNNING) { 2213 ti_setmulti(sc); 2214 error = 0; 2215 } 2216 break; 2217 case SIOCSIFMEDIA: 2218 case SIOCGIFMEDIA: 2219 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command); 2220 break; 2221 case SIOCSIFCAP: 2222 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 2223 if (mask & IFCAP_HWCSUM) { 2224 if (IFCAP_HWCSUM & ifp->if_capenable) 2225 ifp->if_capenable &= ~IFCAP_HWCSUM; 2226 else 2227 ifp->if_capenable |= IFCAP_HWCSUM; 2228 if (ifp->if_flags & IFF_RUNNING) 2229 ti_init(sc); 2230 } 2231 error = 0; 2232 break; 2233 default: 2234 error = ether_ioctl(ifp, command, data); 2235 break; 2236 } 2237 return(error); 2238 } 2239 2240 static void 2241 ti_watchdog(struct ifnet *ifp) 2242 { 2243 struct ti_softc *sc = ifp->if_softc; 2244 2245 if_printf(ifp, "watchdog timeout -- resetting\n"); 2246 ti_stop(sc); 2247 ti_init(sc); 2248 2249 IFNET_STAT_INC(ifp, oerrors, 1); 2250 2251 if (!ifq_is_empty(&ifp->if_snd)) 2252 if_devstart(ifp); 2253 } 2254 2255 /* 2256 * Stop the adapter and free any mbufs allocated to the 2257 * RX and TX lists. 2258 */ 2259 static void 2260 ti_stop(struct ti_softc *sc) 2261 { 2262 struct ifnet *ifp = &sc->arpcom.ac_if; 2263 struct ti_cmd_desc cmd; 2264 2265 /* Disable host interrupts. */ 2266 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 2267 /* 2268 * Tell firmware we're shutting down. 2269 */ 2270 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_DOWN, 0); 2271 2272 /* Halt and reinitialize. */ 2273 ti_chipinit(sc); 2274 ti_mem(sc, 0x2000, 0x100000 - 0x2000, NULL); 2275 ti_chipinit(sc); 2276 2277 /* Free the RX lists. */ 2278 ti_free_rx_ring_std(sc); 2279 2280 /* Free jumbo RX list. */ 2281 ti_free_rx_ring_jumbo(sc); 2282 2283 /* Free mini RX list. */ 2284 ti_free_rx_ring_mini(sc); 2285 2286 /* Free TX buffers. */ 2287 ti_free_tx_ring(sc); 2288 2289 sc->ti_ev_prodidx.ti_idx = 0; 2290 sc->ti_return_prodidx.ti_idx = 0; 2291 sc->ti_tx_considx.ti_idx = 0; 2292 sc->ti_tx_saved_considx = TI_TXCONS_UNSET; 2293 2294 ifp->if_flags &= ~IFF_RUNNING; 2295 ifq_clr_oactive(&ifp->if_snd); 2296 } 2297 2298 /* 2299 * Stop all chip I/O so that the kernel's probe routines don't 2300 * get confused by errant DMAs when rebooting. 2301 */ 2302 static void 2303 ti_shutdown(device_t dev) 2304 { 2305 struct ti_softc *sc = device_get_softc(dev); 2306 2307 ti_chipinit(sc); 2308 } 2309