1 /* 2 * Copyright (c) 1997, 1998 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: src/sys/pci/if_tl.c,v 1.51.2.5 2001/12/16 15:46:08 luigi Exp $ 33 * $DragonFly: src/sys/dev/netif/tl/if_tl.c,v 1.16 2005/02/21 18:40:37 joerg Exp $ 34 */ 35 36 /* 37 * Texas Instruments ThunderLAN driver for FreeBSD 2.2.6 and 3.x. 38 * Supports many Compaq PCI NICs based on the ThunderLAN ethernet controller, 39 * the National Semiconductor DP83840A physical interface and the 40 * Microchip Technology 24Cxx series serial EEPROM. 41 * 42 * Written using the following four documents: 43 * 44 * Texas Instruments ThunderLAN Programmer's Guide (www.ti.com) 45 * National Semiconductor DP83840A data sheet (www.national.com) 46 * Microchip Technology 24C02C data sheet (www.microchip.com) 47 * Micro Linear ML6692 100BaseTX only PHY data sheet (www.microlinear.com) 48 * 49 * Written by Bill Paul <wpaul@ctr.columbia.edu> 50 * Electrical Engineering Department 51 * Columbia University, New York City 52 */ 53 54 /* 55 * Some notes about the ThunderLAN: 56 * 57 * The ThunderLAN controller is a single chip containing PCI controller 58 * logic, approximately 3K of on-board SRAM, a LAN controller, and media 59 * independent interface (MII) bus. The MII allows the ThunderLAN chip to 60 * control up to 32 different physical interfaces (PHYs). The ThunderLAN 61 * also has a built-in 10baseT PHY, allowing a single ThunderLAN controller 62 * to act as a complete ethernet interface. 63 * 64 * Other PHYs may be attached to the ThunderLAN; the Compaq 10/100 cards 65 * use a National Semiconductor DP83840A PHY that supports 10 or 100Mb/sec 66 * in full or half duplex. Some of the Compaq Deskpro machines use a 67 * Level 1 LXT970 PHY with the same capabilities. Certain Olicom adapters 68 * use a Micro Linear ML6692 100BaseTX only PHY, which can be used in 69 * concert with the ThunderLAN's internal PHY to provide full 10/100 70 * support. This is cheaper than using a standalone external PHY for both 71 * 10/100 modes and letting the ThunderLAN's internal PHY go to waste. 72 * A serial EEPROM is also attached to the ThunderLAN chip to provide 73 * power-up default register settings and for storing the adapter's 74 * station address. Although not supported by this driver, the ThunderLAN 75 * chip can also be connected to token ring PHYs. 76 * 77 * The ThunderLAN has a set of registers which can be used to issue 78 * commands, acknowledge interrupts, and to manipulate other internal 79 * registers on its DIO bus. The primary registers can be accessed 80 * using either programmed I/O (inb/outb) or via PCI memory mapping, 81 * depending on how the card is configured during the PCI probing 82 * phase. It is even possible to have both PIO and memory mapped 83 * access turned on at the same time. 84 * 85 * Frame reception and transmission with the ThunderLAN chip is done 86 * using frame 'lists.' A list structure looks more or less like this: 87 * 88 * struct tl_frag { 89 * u_int32_t fragment_address; 90 * u_int32_t fragment_size; 91 * }; 92 * struct tl_list { 93 * u_int32_t forward_pointer; 94 * u_int16_t cstat; 95 * u_int16_t frame_size; 96 * struct tl_frag fragments[10]; 97 * }; 98 * 99 * The forward pointer in the list header can be either a 0 or the address 100 * of another list, which allows several lists to be linked together. Each 101 * list contains up to 10 fragment descriptors. This means the chip allows 102 * ethernet frames to be broken up into up to 10 chunks for transfer to 103 * and from the SRAM. Note that the forward pointer and fragment buffer 104 * addresses are physical memory addresses, not virtual. Note also that 105 * a single ethernet frame can not span lists: if the host wants to 106 * transmit a frame and the frame data is split up over more than 10 107 * buffers, the frame has to collapsed before it can be transmitted. 108 * 109 * To receive frames, the driver sets up a number of lists and populates 110 * the fragment descriptors, then it sends an RX GO command to the chip. 111 * When a frame is received, the chip will DMA it into the memory regions 112 * specified by the fragment descriptors and then trigger an RX 'end of 113 * frame interrupt' when done. The driver may choose to use only one 114 * fragment per list; this may result is slighltly less efficient use 115 * of memory in exchange for improving performance. 116 * 117 * To transmit frames, the driver again sets up lists and fragment 118 * descriptors, only this time the buffers contain frame data that 119 * is to be DMA'ed into the chip instead of out of it. Once the chip 120 * has transfered the data into its on-board SRAM, it will trigger a 121 * TX 'end of frame' interrupt. It will also generate an 'end of channel' 122 * interrupt when it reaches the end of the list. 123 */ 124 125 /* 126 * Some notes about this driver: 127 * 128 * The ThunderLAN chip provides a couple of different ways to organize 129 * reception, transmission and interrupt handling. The simplest approach 130 * is to use one list each for transmission and reception. In this mode, 131 * the ThunderLAN will generate two interrupts for every received frame 132 * (one RX EOF and one RX EOC) and two for each transmitted frame (one 133 * TX EOF and one TX EOC). This may make the driver simpler but it hurts 134 * performance to have to handle so many interrupts. 135 * 136 * Initially I wanted to create a circular list of receive buffers so 137 * that the ThunderLAN chip would think there was an infinitely long 138 * receive channel and never deliver an RXEOC interrupt. However this 139 * doesn't work correctly under heavy load: while the manual says the 140 * chip will trigger an RXEOF interrupt each time a frame is copied into 141 * memory, you can't count on the chip waiting around for you to acknowledge 142 * the interrupt before it starts trying to DMA the next frame. The result 143 * is that the chip might traverse the entire circular list and then wrap 144 * around before you have a chance to do anything about it. Consequently, 145 * the receive list is terminated (with a 0 in the forward pointer in the 146 * last element). Each time an RXEOF interrupt arrives, the used list 147 * is shifted to the end of the list. This gives the appearance of an 148 * infinitely large RX chain so long as the driver doesn't fall behind 149 * the chip and allow all of the lists to be filled up. 150 * 151 * If all the lists are filled, the adapter will deliver an RX 'end of 152 * channel' interrupt when it hits the 0 forward pointer at the end of 153 * the chain. The RXEOC handler then cleans out the RX chain and resets 154 * the list head pointer in the ch_parm register and restarts the receiver. 155 * 156 * For frame transmission, it is possible to program the ThunderLAN's 157 * transmit interrupt threshold so that the chip can acknowledge multiple 158 * lists with only a single TX EOF interrupt. This allows the driver to 159 * queue several frames in one shot, and only have to handle a total 160 * two interrupts (one TX EOF and one TX EOC) no matter how many frames 161 * are transmitted. Frame transmission is done directly out of the 162 * mbufs passed to the tl_start() routine via the interface send queue. 163 * The driver simply sets up the fragment descriptors in the transmit 164 * lists to point to the mbuf data regions and sends a TX GO command. 165 * 166 * Note that since the RX and TX lists themselves are always used 167 * only by the driver, the are malloc()ed once at driver initialization 168 * time and never free()ed. 169 * 170 * Also, in order to remain as platform independent as possible, this 171 * driver uses memory mapped register access to manipulate the card 172 * as opposed to programmed I/O. This avoids the use of the inb/outb 173 * (and related) instructions which are specific to the i386 platform. 174 * 175 * Using these techniques, this driver achieves very high performance 176 * by minimizing the amount of interrupts generated during large 177 * transfers and by completely avoiding buffer copies. Frame transfer 178 * to and from the ThunderLAN chip is performed entirely by the chip 179 * itself thereby reducing the load on the host CPU. 180 */ 181 182 #include <sys/param.h> 183 #include <sys/systm.h> 184 #include <sys/sockio.h> 185 #include <sys/mbuf.h> 186 #include <sys/malloc.h> 187 #include <sys/kernel.h> 188 #include <sys/socket.h> 189 190 #include <net/if.h> 191 #include <net/ifq_var.h> 192 #include <net/if_arp.h> 193 #include <net/ethernet.h> 194 #include <net/if_dl.h> 195 #include <net/if_media.h> 196 197 #include <net/bpf.h> 198 199 #include <vm/vm.h> /* for vtophys */ 200 #include <vm/pmap.h> /* for vtophys */ 201 #include <machine/clock.h> /* for DELAY */ 202 #include <machine/bus_memio.h> 203 #include <machine/bus_pio.h> 204 #include <machine/bus.h> 205 #include <machine/resource.h> 206 #include <sys/bus.h> 207 #include <sys/rman.h> 208 209 #include "../mii_layer/mii.h" 210 #include "../mii_layer/miivar.h" 211 212 #include <bus/pci/pcireg.h> 213 #include <bus/pci/pcivar.h> 214 215 /* 216 * Default to using PIO register access mode to pacify certain 217 * laptop docking stations with built-in ThunderLAN chips that 218 * don't seem to handle memory mapped mode properly. 219 */ 220 #define TL_USEIOSPACE 221 222 #include "if_tlreg.h" 223 224 /* "controller miibus0" required. See GENERIC if you get errors here. */ 225 #include "miibus_if.h" 226 227 /* 228 * Various supported device vendors/types and their names. 229 */ 230 231 static struct tl_type tl_devs[] = { 232 { TI_VENDORID, TI_DEVICEID_THUNDERLAN, 233 "Texas Instruments ThunderLAN" }, 234 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10, 235 "Compaq Netelligent 10" }, 236 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100, 237 "Compaq Netelligent 10/100" }, 238 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100_PROLIANT, 239 "Compaq Netelligent 10/100 Proliant" }, 240 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100_DUAL, 241 "Compaq Netelligent 10/100 Dual Port" }, 242 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETFLEX_3P_INTEGRATED, 243 "Compaq NetFlex-3/P Integrated" }, 244 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETFLEX_3P, 245 "Compaq NetFlex-3/P" }, 246 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETFLEX_3P_BNC, 247 "Compaq NetFlex 3/P w/ BNC" }, 248 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100_EMBEDDED, 249 "Compaq Netelligent 10/100 TX Embedded UTP" }, 250 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_T2_UTP_COAX, 251 "Compaq Netelligent 10 T/2 PCI UTP/Coax" }, 252 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100_TX_UTP, 253 "Compaq Netelligent 10/100 TX UTP" }, 254 { OLICOM_VENDORID, OLICOM_DEVICEID_OC2183, 255 "Olicom OC-2183/2185" }, 256 { OLICOM_VENDORID, OLICOM_DEVICEID_OC2325, 257 "Olicom OC-2325" }, 258 { OLICOM_VENDORID, OLICOM_DEVICEID_OC2326, 259 "Olicom OC-2326 10/100 TX UTP" }, 260 { 0, 0, NULL } 261 }; 262 263 static int tl_probe (device_t); 264 static int tl_attach (device_t); 265 static int tl_detach (device_t); 266 static int tl_intvec_rxeoc (void *, u_int32_t); 267 static int tl_intvec_txeoc (void *, u_int32_t); 268 static int tl_intvec_txeof (void *, u_int32_t); 269 static int tl_intvec_rxeof (void *, u_int32_t); 270 static int tl_intvec_adchk (void *, u_int32_t); 271 static int tl_intvec_netsts (void *, u_int32_t); 272 273 static int tl_newbuf (struct tl_softc *, 274 struct tl_chain_onefrag *); 275 static void tl_stats_update (void *); 276 static int tl_encap (struct tl_softc *, struct tl_chain *, 277 struct mbuf *); 278 279 static void tl_intr (void *); 280 static void tl_start (struct ifnet *); 281 static int tl_ioctl (struct ifnet *, u_long, caddr_t, 282 struct ucred *); 283 static void tl_init (void *); 284 static void tl_stop (struct tl_softc *); 285 static void tl_watchdog (struct ifnet *); 286 static void tl_shutdown (device_t); 287 static int tl_ifmedia_upd (struct ifnet *); 288 static void tl_ifmedia_sts (struct ifnet *, struct ifmediareq *); 289 290 static u_int8_t tl_eeprom_putbyte (struct tl_softc *, int); 291 static u_int8_t tl_eeprom_getbyte (struct tl_softc *, 292 int, u_int8_t *); 293 static int tl_read_eeprom (struct tl_softc *, caddr_t, int, int); 294 295 static void tl_mii_sync (struct tl_softc *); 296 static void tl_mii_send (struct tl_softc *, u_int32_t, int); 297 static int tl_mii_readreg (struct tl_softc *, struct tl_mii_frame *); 298 static int tl_mii_writereg (struct tl_softc *, struct tl_mii_frame *); 299 static int tl_miibus_readreg (device_t, int, int); 300 static int tl_miibus_writereg (device_t, int, int, int); 301 static void tl_miibus_statchg (device_t); 302 303 static void tl_setmode (struct tl_softc *, int); 304 static int tl_calchash (caddr_t); 305 static void tl_setmulti (struct tl_softc *); 306 static void tl_setfilt (struct tl_softc *, caddr_t, int); 307 static void tl_softreset (struct tl_softc *, int); 308 static void tl_hardreset (device_t); 309 static int tl_list_rx_init (struct tl_softc *); 310 static int tl_list_tx_init (struct tl_softc *); 311 312 static u_int8_t tl_dio_read8 (struct tl_softc *, int); 313 static u_int16_t tl_dio_read16 (struct tl_softc *, int); 314 static u_int32_t tl_dio_read32 (struct tl_softc *, int); 315 static void tl_dio_write8 (struct tl_softc *, int, int); 316 static void tl_dio_write16 (struct tl_softc *, int, int); 317 static void tl_dio_write32 (struct tl_softc *, int, int); 318 static void tl_dio_setbit (struct tl_softc *, int, int); 319 static void tl_dio_clrbit (struct tl_softc *, int, int); 320 static void tl_dio_setbit16 (struct tl_softc *, int, int); 321 static void tl_dio_clrbit16 (struct tl_softc *, int, int); 322 323 #ifdef TL_USEIOSPACE 324 #define TL_RES SYS_RES_IOPORT 325 #define TL_RID TL_PCI_LOIO 326 #else 327 #define TL_RES SYS_RES_MEMORY 328 #define TL_RID TL_PCI_LOMEM 329 #endif 330 331 static device_method_t tl_methods[] = { 332 /* Device interface */ 333 DEVMETHOD(device_probe, tl_probe), 334 DEVMETHOD(device_attach, tl_attach), 335 DEVMETHOD(device_detach, tl_detach), 336 DEVMETHOD(device_shutdown, tl_shutdown), 337 338 /* bus interface */ 339 DEVMETHOD(bus_print_child, bus_generic_print_child), 340 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 341 342 /* MII interface */ 343 DEVMETHOD(miibus_readreg, tl_miibus_readreg), 344 DEVMETHOD(miibus_writereg, tl_miibus_writereg), 345 DEVMETHOD(miibus_statchg, tl_miibus_statchg), 346 347 { 0, 0 } 348 }; 349 350 static driver_t tl_driver = { 351 "tl", 352 tl_methods, 353 sizeof(struct tl_softc) 354 }; 355 356 static devclass_t tl_devclass; 357 358 DECLARE_DUMMY_MODULE(if_tl); 359 DRIVER_MODULE(if_tl, pci, tl_driver, tl_devclass, 0, 0); 360 DRIVER_MODULE(miibus, tl, miibus_driver, miibus_devclass, 0, 0); 361 362 static u_int8_t tl_dio_read8(sc, reg) 363 struct tl_softc *sc; 364 int reg; 365 { 366 CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 367 return(CSR_READ_1(sc, TL_DIO_DATA + (reg & 3))); 368 } 369 370 static u_int16_t tl_dio_read16(sc, reg) 371 struct tl_softc *sc; 372 int reg; 373 { 374 CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 375 return(CSR_READ_2(sc, TL_DIO_DATA + (reg & 3))); 376 } 377 378 static u_int32_t tl_dio_read32(sc, reg) 379 struct tl_softc *sc; 380 int reg; 381 { 382 CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 383 return(CSR_READ_4(sc, TL_DIO_DATA + (reg & 3))); 384 } 385 386 static void tl_dio_write8(sc, reg, val) 387 struct tl_softc *sc; 388 int reg; 389 int val; 390 { 391 CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 392 CSR_WRITE_1(sc, TL_DIO_DATA + (reg & 3), val); 393 return; 394 } 395 396 static void tl_dio_write16(sc, reg, val) 397 struct tl_softc *sc; 398 int reg; 399 int val; 400 { 401 CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 402 CSR_WRITE_2(sc, TL_DIO_DATA + (reg & 3), val); 403 return; 404 } 405 406 static void tl_dio_write32(sc, reg, val) 407 struct tl_softc *sc; 408 int reg; 409 int val; 410 { 411 CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 412 CSR_WRITE_4(sc, TL_DIO_DATA + (reg & 3), val); 413 return; 414 } 415 416 static void tl_dio_setbit(sc, reg, bit) 417 struct tl_softc *sc; 418 int reg; 419 int bit; 420 { 421 u_int8_t f; 422 423 CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 424 f = CSR_READ_1(sc, TL_DIO_DATA + (reg & 3)); 425 f |= bit; 426 CSR_WRITE_1(sc, TL_DIO_DATA + (reg & 3), f); 427 428 return; 429 } 430 431 static void tl_dio_clrbit(sc, reg, bit) 432 struct tl_softc *sc; 433 int reg; 434 int bit; 435 { 436 u_int8_t f; 437 438 CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 439 f = CSR_READ_1(sc, TL_DIO_DATA + (reg & 3)); 440 f &= ~bit; 441 CSR_WRITE_1(sc, TL_DIO_DATA + (reg & 3), f); 442 443 return; 444 } 445 446 static void tl_dio_setbit16(sc, reg, bit) 447 struct tl_softc *sc; 448 int reg; 449 int bit; 450 { 451 u_int16_t f; 452 453 CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 454 f = CSR_READ_2(sc, TL_DIO_DATA + (reg & 3)); 455 f |= bit; 456 CSR_WRITE_2(sc, TL_DIO_DATA + (reg & 3), f); 457 458 return; 459 } 460 461 static void tl_dio_clrbit16(sc, reg, bit) 462 struct tl_softc *sc; 463 int reg; 464 int bit; 465 { 466 u_int16_t f; 467 468 CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 469 f = CSR_READ_2(sc, TL_DIO_DATA + (reg & 3)); 470 f &= ~bit; 471 CSR_WRITE_2(sc, TL_DIO_DATA + (reg & 3), f); 472 473 return; 474 } 475 476 /* 477 * Send an instruction or address to the EEPROM, check for ACK. 478 */ 479 static u_int8_t tl_eeprom_putbyte(sc, byte) 480 struct tl_softc *sc; 481 int byte; 482 { 483 int i, ack = 0; 484 485 /* 486 * Make sure we're in TX mode. 487 */ 488 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ETXEN); 489 490 /* 491 * Feed in each bit and stobe the clock. 492 */ 493 for (i = 0x80; i; i >>= 1) { 494 if (byte & i) { 495 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_EDATA); 496 } else { 497 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_EDATA); 498 } 499 DELAY(1); 500 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ECLOK); 501 DELAY(1); 502 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ECLOK); 503 } 504 505 /* 506 * Turn off TX mode. 507 */ 508 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ETXEN); 509 510 /* 511 * Check for ack. 512 */ 513 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ECLOK); 514 ack = tl_dio_read8(sc, TL_NETSIO) & TL_SIO_EDATA; 515 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ECLOK); 516 517 return(ack); 518 } 519 520 /* 521 * Read a byte of data stored in the EEPROM at address 'addr.' 522 */ 523 static u_int8_t tl_eeprom_getbyte(sc, addr, dest) 524 struct tl_softc *sc; 525 int addr; 526 u_int8_t *dest; 527 { 528 int i; 529 u_int8_t byte = 0; 530 531 tl_dio_write8(sc, TL_NETSIO, 0); 532 533 EEPROM_START; 534 535 /* 536 * Send write control code to EEPROM. 537 */ 538 if (tl_eeprom_putbyte(sc, EEPROM_CTL_WRITE)) { 539 printf("tl%d: failed to send write command, status: %x\n", 540 sc->tl_unit, tl_dio_read8(sc, TL_NETSIO)); 541 return(1); 542 } 543 544 /* 545 * Send address of byte we want to read. 546 */ 547 if (tl_eeprom_putbyte(sc, addr)) { 548 printf("tl%d: failed to send address, status: %x\n", 549 sc->tl_unit, tl_dio_read8(sc, TL_NETSIO)); 550 return(1); 551 } 552 553 EEPROM_STOP; 554 EEPROM_START; 555 /* 556 * Send read control code to EEPROM. 557 */ 558 if (tl_eeprom_putbyte(sc, EEPROM_CTL_READ)) { 559 printf("tl%d: failed to send write command, status: %x\n", 560 sc->tl_unit, tl_dio_read8(sc, TL_NETSIO)); 561 return(1); 562 } 563 564 /* 565 * Start reading bits from EEPROM. 566 */ 567 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ETXEN); 568 for (i = 0x80; i; i >>= 1) { 569 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ECLOK); 570 DELAY(1); 571 if (tl_dio_read8(sc, TL_NETSIO) & TL_SIO_EDATA) 572 byte |= i; 573 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ECLOK); 574 DELAY(1); 575 } 576 577 EEPROM_STOP; 578 579 /* 580 * No ACK generated for read, so just return byte. 581 */ 582 583 *dest = byte; 584 585 return(0); 586 } 587 588 /* 589 * Read a sequence of bytes from the EEPROM. 590 */ 591 static int tl_read_eeprom(sc, dest, off, cnt) 592 struct tl_softc *sc; 593 caddr_t dest; 594 int off; 595 int cnt; 596 { 597 int err = 0, i; 598 u_int8_t byte = 0; 599 600 for (i = 0; i < cnt; i++) { 601 err = tl_eeprom_getbyte(sc, off + i, &byte); 602 if (err) 603 break; 604 *(dest + i) = byte; 605 } 606 607 return(err ? 1 : 0); 608 } 609 610 static void tl_mii_sync(sc) 611 struct tl_softc *sc; 612 { 613 int i; 614 615 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MTXEN); 616 617 for (i = 0; i < 32; i++) { 618 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK); 619 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK); 620 } 621 622 return; 623 } 624 625 static void tl_mii_send(sc, bits, cnt) 626 struct tl_softc *sc; 627 u_int32_t bits; 628 int cnt; 629 { 630 int i; 631 632 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 633 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK); 634 if (bits & i) { 635 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MDATA); 636 } else { 637 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MDATA); 638 } 639 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK); 640 } 641 } 642 643 static int tl_mii_readreg(sc, frame) 644 struct tl_softc *sc; 645 struct tl_mii_frame *frame; 646 647 { 648 int i, ack, s; 649 int minten = 0; 650 651 s = splimp(); 652 653 tl_mii_sync(sc); 654 655 /* 656 * Set up frame for RX. 657 */ 658 frame->mii_stdelim = TL_MII_STARTDELIM; 659 frame->mii_opcode = TL_MII_READOP; 660 frame->mii_turnaround = 0; 661 frame->mii_data = 0; 662 663 /* 664 * Turn off MII interrupt by forcing MINTEN low. 665 */ 666 minten = tl_dio_read8(sc, TL_NETSIO) & TL_SIO_MINTEN; 667 if (minten) { 668 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MINTEN); 669 } 670 671 /* 672 * Turn on data xmit. 673 */ 674 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MTXEN); 675 676 /* 677 * Send command/address info. 678 */ 679 tl_mii_send(sc, frame->mii_stdelim, 2); 680 tl_mii_send(sc, frame->mii_opcode, 2); 681 tl_mii_send(sc, frame->mii_phyaddr, 5); 682 tl_mii_send(sc, frame->mii_regaddr, 5); 683 684 /* 685 * Turn off xmit. 686 */ 687 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MTXEN); 688 689 /* Idle bit */ 690 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK); 691 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK); 692 693 /* Check for ack */ 694 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK); 695 ack = tl_dio_read8(sc, TL_NETSIO) & TL_SIO_MDATA; 696 697 /* Complete the cycle */ 698 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK); 699 700 /* 701 * Now try reading data bits. If the ack failed, we still 702 * need to clock through 16 cycles to keep the PHYs in sync. 703 */ 704 if (ack) { 705 for(i = 0; i < 16; i++) { 706 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK); 707 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK); 708 } 709 goto fail; 710 } 711 712 for (i = 0x8000; i; i >>= 1) { 713 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK); 714 if (!ack) { 715 if (tl_dio_read8(sc, TL_NETSIO) & TL_SIO_MDATA) 716 frame->mii_data |= i; 717 } 718 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK); 719 } 720 721 fail: 722 723 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK); 724 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK); 725 726 /* Reenable interrupts */ 727 if (minten) { 728 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MINTEN); 729 } 730 731 splx(s); 732 733 if (ack) 734 return(1); 735 return(0); 736 } 737 738 static int tl_mii_writereg(sc, frame) 739 struct tl_softc *sc; 740 struct tl_mii_frame *frame; 741 742 { 743 int s; 744 int minten; 745 746 tl_mii_sync(sc); 747 748 s = splimp(); 749 /* 750 * Set up frame for TX. 751 */ 752 753 frame->mii_stdelim = TL_MII_STARTDELIM; 754 frame->mii_opcode = TL_MII_WRITEOP; 755 frame->mii_turnaround = TL_MII_TURNAROUND; 756 757 /* 758 * Turn off MII interrupt by forcing MINTEN low. 759 */ 760 minten = tl_dio_read8(sc, TL_NETSIO) & TL_SIO_MINTEN; 761 if (minten) { 762 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MINTEN); 763 } 764 765 /* 766 * Turn on data output. 767 */ 768 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MTXEN); 769 770 tl_mii_send(sc, frame->mii_stdelim, 2); 771 tl_mii_send(sc, frame->mii_opcode, 2); 772 tl_mii_send(sc, frame->mii_phyaddr, 5); 773 tl_mii_send(sc, frame->mii_regaddr, 5); 774 tl_mii_send(sc, frame->mii_turnaround, 2); 775 tl_mii_send(sc, frame->mii_data, 16); 776 777 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK); 778 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK); 779 780 /* 781 * Turn off xmit. 782 */ 783 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MTXEN); 784 785 /* Reenable interrupts */ 786 if (minten) 787 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MINTEN); 788 789 splx(s); 790 791 return(0); 792 } 793 794 static int tl_miibus_readreg(dev, phy, reg) 795 device_t dev; 796 int phy, reg; 797 { 798 struct tl_softc *sc; 799 struct tl_mii_frame frame; 800 801 sc = device_get_softc(dev); 802 bzero((char *)&frame, sizeof(frame)); 803 804 frame.mii_phyaddr = phy; 805 frame.mii_regaddr = reg; 806 tl_mii_readreg(sc, &frame); 807 808 return(frame.mii_data); 809 } 810 811 static int tl_miibus_writereg(dev, phy, reg, data) 812 device_t dev; 813 int phy, reg, data; 814 { 815 struct tl_softc *sc; 816 struct tl_mii_frame frame; 817 818 sc = device_get_softc(dev); 819 bzero((char *)&frame, sizeof(frame)); 820 821 frame.mii_phyaddr = phy; 822 frame.mii_regaddr = reg; 823 frame.mii_data = data; 824 825 tl_mii_writereg(sc, &frame); 826 827 return(0); 828 } 829 830 static void tl_miibus_statchg(dev) 831 device_t dev; 832 { 833 struct tl_softc *sc; 834 struct mii_data *mii; 835 836 sc = device_get_softc(dev); 837 mii = device_get_softc(sc->tl_miibus); 838 839 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 840 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_DUPLEX); 841 } else { 842 tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_DUPLEX); 843 } 844 845 return; 846 } 847 848 /* 849 * Set modes for bitrate devices. 850 */ 851 static void tl_setmode(sc, media) 852 struct tl_softc *sc; 853 int media; 854 { 855 if (IFM_SUBTYPE(media) == IFM_10_5) 856 tl_dio_setbit(sc, TL_ACOMMIT, TL_AC_MTXD1); 857 if (IFM_SUBTYPE(media) == IFM_10_T) { 858 tl_dio_clrbit(sc, TL_ACOMMIT, TL_AC_MTXD1); 859 if ((media & IFM_GMASK) == IFM_FDX) { 860 tl_dio_clrbit(sc, TL_ACOMMIT, TL_AC_MTXD3); 861 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_DUPLEX); 862 } else { 863 tl_dio_setbit(sc, TL_ACOMMIT, TL_AC_MTXD3); 864 tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_DUPLEX); 865 } 866 } 867 868 return; 869 } 870 871 /* 872 * Calculate the hash of a MAC address for programming the multicast hash 873 * table. This hash is simply the address split into 6-bit chunks 874 * XOR'd, e.g. 875 * byte: 000000|00 1111|1111 22|222222|333333|33 4444|4444 55|555555 876 * bit: 765432|10 7654|3210 76|543210|765432|10 7654|3210 76|543210 877 * Bytes 0-2 and 3-5 are symmetrical, so are folded together. Then 878 * the folded 24-bit value is split into 6-bit portions and XOR'd. 879 */ 880 static int tl_calchash(addr) 881 caddr_t addr; 882 { 883 int t; 884 885 t = (addr[0] ^ addr[3]) << 16 | (addr[1] ^ addr[4]) << 8 | 886 (addr[2] ^ addr[5]); 887 return ((t >> 18) ^ (t >> 12) ^ (t >> 6) ^ t) & 0x3f; 888 } 889 890 /* 891 * The ThunderLAN has a perfect MAC address filter in addition to 892 * the multicast hash filter. The perfect filter can be programmed 893 * with up to four MAC addresses. The first one is always used to 894 * hold the station address, which leaves us free to use the other 895 * three for multicast addresses. 896 */ 897 static void tl_setfilt(sc, addr, slot) 898 struct tl_softc *sc; 899 caddr_t addr; 900 int slot; 901 { 902 int i; 903 u_int16_t regaddr; 904 905 regaddr = TL_AREG0_B5 + (slot * ETHER_ADDR_LEN); 906 907 for (i = 0; i < ETHER_ADDR_LEN; i++) 908 tl_dio_write8(sc, regaddr + i, *(addr + i)); 909 910 return; 911 } 912 913 /* 914 * XXX In FreeBSD 3.0, multicast addresses are managed using a doubly 915 * linked list. This is fine, except addresses are added from the head 916 * end of the list. We want to arrange for 224.0.0.1 (the "all hosts") 917 * group to always be in the perfect filter, but as more groups are added, 918 * the 224.0.0.1 entry (which is always added first) gets pushed down 919 * the list and ends up at the tail. So after 3 or 4 multicast groups 920 * are added, the all-hosts entry gets pushed out of the perfect filter 921 * and into the hash table. 922 * 923 * Because the multicast list is a doubly-linked list as opposed to a 924 * circular queue, we don't have the ability to just grab the tail of 925 * the list and traverse it backwards. Instead, we have to traverse 926 * the list once to find the tail, then traverse it again backwards to 927 * update the multicast filter. 928 */ 929 static void tl_setmulti(sc) 930 struct tl_softc *sc; 931 { 932 struct ifnet *ifp; 933 u_int32_t hashes[2] = { 0, 0 }; 934 int h, i; 935 struct ifmultiaddr *ifma; 936 u_int8_t dummy[] = { 0, 0, 0, 0, 0 ,0 }; 937 ifp = &sc->arpcom.ac_if; 938 939 /* First, zot all the existing filters. */ 940 for (i = 1; i < 4; i++) 941 tl_setfilt(sc, (caddr_t)&dummy, i); 942 tl_dio_write32(sc, TL_HASH1, 0); 943 tl_dio_write32(sc, TL_HASH2, 0); 944 945 /* Now program new ones. */ 946 if (ifp->if_flags & IFF_ALLMULTI) { 947 hashes[0] = 0xFFFFFFFF; 948 hashes[1] = 0xFFFFFFFF; 949 } else { 950 i = 1; 951 /* First find the tail of the list. */ 952 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 953 ifma = ifma->ifma_link.le_next) { 954 if (ifma->ifma_link.le_next == NULL) 955 break; 956 } 957 /* Now traverse the list backwards. */ 958 for (; ifma != NULL && ifma != (void *)&ifp->if_multiaddrs; 959 ifma = (struct ifmultiaddr *)ifma->ifma_link.le_prev) { 960 if (ifma->ifma_addr->sa_family != AF_LINK) 961 continue; 962 /* 963 * Program the first three multicast groups 964 * into the perfect filter. For all others, 965 * use the hash table. 966 */ 967 if (i < 4) { 968 tl_setfilt(sc, 969 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), i); 970 i++; 971 continue; 972 } 973 974 h = tl_calchash( 975 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 976 if (h < 32) 977 hashes[0] |= (1 << h); 978 else 979 hashes[1] |= (1 << (h - 32)); 980 } 981 } 982 983 tl_dio_write32(sc, TL_HASH1, hashes[0]); 984 tl_dio_write32(sc, TL_HASH2, hashes[1]); 985 986 return; 987 } 988 989 /* 990 * This routine is recommended by the ThunderLAN manual to insure that 991 * the internal PHY is powered up correctly. It also recommends a one 992 * second pause at the end to 'wait for the clocks to start' but in my 993 * experience this isn't necessary. 994 */ 995 static void tl_hardreset(dev) 996 device_t dev; 997 { 998 struct tl_softc *sc; 999 int i; 1000 u_int16_t flags; 1001 1002 sc = device_get_softc(dev); 1003 1004 tl_mii_sync(sc); 1005 1006 flags = BMCR_LOOP|BMCR_ISO|BMCR_PDOWN; 1007 1008 for (i = 0; i < MII_NPHY; i++) 1009 tl_miibus_writereg(dev, i, MII_BMCR, flags); 1010 1011 tl_miibus_writereg(dev, 31, MII_BMCR, BMCR_ISO); 1012 DELAY(50000); 1013 tl_miibus_writereg(dev, 31, MII_BMCR, BMCR_LOOP|BMCR_ISO); 1014 tl_mii_sync(sc); 1015 while(tl_miibus_readreg(dev, 31, MII_BMCR) & BMCR_RESET); 1016 1017 DELAY(50000); 1018 return; 1019 } 1020 1021 static void tl_softreset(sc, internal) 1022 struct tl_softc *sc; 1023 int internal; 1024 { 1025 u_int32_t cmd, dummy, i; 1026 1027 /* Assert the adapter reset bit. */ 1028 CMD_SET(sc, TL_CMD_ADRST); 1029 1030 /* Turn off interrupts */ 1031 CMD_SET(sc, TL_CMD_INTSOFF); 1032 1033 /* First, clear the stats registers. */ 1034 for (i = 0; i < 5; i++) 1035 dummy = tl_dio_read32(sc, TL_TXGOODFRAMES); 1036 1037 /* Clear Areg and Hash registers */ 1038 for (i = 0; i < 8; i++) 1039 tl_dio_write32(sc, TL_AREG0_B5, 0x00000000); 1040 1041 /* 1042 * Set up Netconfig register. Enable one channel and 1043 * one fragment mode. 1044 */ 1045 tl_dio_setbit16(sc, TL_NETCONFIG, TL_CFG_ONECHAN|TL_CFG_ONEFRAG); 1046 if (internal && !sc->tl_bitrate) { 1047 tl_dio_setbit16(sc, TL_NETCONFIG, TL_CFG_PHYEN); 1048 } else { 1049 tl_dio_clrbit16(sc, TL_NETCONFIG, TL_CFG_PHYEN); 1050 } 1051 1052 /* Handle cards with bitrate devices. */ 1053 if (sc->tl_bitrate) 1054 tl_dio_setbit16(sc, TL_NETCONFIG, TL_CFG_BITRATE); 1055 1056 /* 1057 * Load adapter irq pacing timer and tx threshold. 1058 * We make the transmit threshold 1 initially but we may 1059 * change that later. 1060 */ 1061 cmd = CSR_READ_4(sc, TL_HOSTCMD); 1062 cmd |= TL_CMD_NES; 1063 cmd &= ~(TL_CMD_RT|TL_CMD_EOC|TL_CMD_ACK_MASK|TL_CMD_CHSEL_MASK); 1064 CMD_PUT(sc, cmd | (TL_CMD_LDTHR | TX_THR)); 1065 CMD_PUT(sc, cmd | (TL_CMD_LDTMR | 0x00000003)); 1066 1067 /* Unreset the MII */ 1068 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_NMRST); 1069 1070 /* Take the adapter out of reset */ 1071 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_NRESET|TL_CMD_NWRAP); 1072 1073 /* Wait for things to settle down a little. */ 1074 DELAY(500); 1075 1076 return; 1077 } 1078 1079 /* 1080 * Probe for a ThunderLAN chip. Check the PCI vendor and device IDs 1081 * against our list and return its name if we find a match. 1082 */ 1083 static int tl_probe(dev) 1084 device_t dev; 1085 { 1086 struct tl_type *t; 1087 1088 t = tl_devs; 1089 1090 while(t->tl_name != NULL) { 1091 if ((pci_get_vendor(dev) == t->tl_vid) && 1092 (pci_get_device(dev) == t->tl_did)) { 1093 device_set_desc(dev, t->tl_name); 1094 return(0); 1095 } 1096 t++; 1097 } 1098 1099 return(ENXIO); 1100 } 1101 1102 static int tl_attach(dev) 1103 device_t dev; 1104 { 1105 int s, i; 1106 u_int32_t command; 1107 u_int16_t did, vid; 1108 struct tl_type *t; 1109 struct ifnet *ifp; 1110 struct tl_softc *sc; 1111 int unit, error = 0, rid; 1112 1113 s = splimp(); 1114 1115 vid = pci_get_vendor(dev); 1116 did = pci_get_device(dev); 1117 sc = device_get_softc(dev); 1118 unit = device_get_unit(dev); 1119 bzero(sc, sizeof(struct tl_softc)); 1120 1121 t = tl_devs; 1122 while(t->tl_name != NULL) { 1123 if (vid == t->tl_vid && did == t->tl_did) 1124 break; 1125 t++; 1126 } 1127 1128 if (t->tl_name == NULL) { 1129 printf("tl%d: unknown device!?\n", unit); 1130 goto fail; 1131 } 1132 1133 /* 1134 * Map control/status registers. 1135 */ 1136 command = pci_read_config(dev, PCIR_COMMAND, 4); 1137 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 1138 pci_write_config(dev, PCIR_COMMAND, command, 4); 1139 command = pci_read_config(dev, PCIR_COMMAND, 4); 1140 1141 #ifdef TL_USEIOSPACE 1142 if (!(command & PCIM_CMD_PORTEN)) { 1143 printf("tl%d: failed to enable I/O ports!\n", unit); 1144 error = ENXIO; 1145 goto fail; 1146 } 1147 1148 rid = TL_PCI_LOIO; 1149 sc->tl_res = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid, 1150 0, ~0, 1, RF_ACTIVE); 1151 1152 /* 1153 * Some cards have the I/O and memory mapped address registers 1154 * reversed. Try both combinations before giving up. 1155 */ 1156 if (sc->tl_res == NULL) { 1157 rid = TL_PCI_LOMEM; 1158 sc->tl_res = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid, 1159 0, ~0, 1, RF_ACTIVE); 1160 } 1161 #else 1162 if (!(command & PCIM_CMD_MEMEN)) { 1163 printf("tl%d: failed to enable memory mapping!\n", unit); 1164 error = ENXIO; 1165 goto fail; 1166 } 1167 1168 rid = TL_PCI_LOMEM; 1169 sc->tl_res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 1170 0, ~0, 1, RF_ACTIVE); 1171 if (sc->tl_res == NULL) { 1172 rid = TL_PCI_LOIO; 1173 sc->tl_res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 1174 0, ~0, 1, RF_ACTIVE); 1175 } 1176 #endif 1177 1178 if (sc->tl_res == NULL) { 1179 printf("tl%d: couldn't map ports/memory\n", unit); 1180 error = ENXIO; 1181 goto fail; 1182 } 1183 1184 sc->tl_btag = rman_get_bustag(sc->tl_res); 1185 sc->tl_bhandle = rman_get_bushandle(sc->tl_res); 1186 1187 #ifdef notdef 1188 /* 1189 * The ThunderLAN manual suggests jacking the PCI latency 1190 * timer all the way up to its maximum value. I'm not sure 1191 * if this is really necessary, but what the manual wants, 1192 * the manual gets. 1193 */ 1194 command = pci_read_config(dev, TL_PCI_LATENCY_TIMER, 4); 1195 command |= 0x0000FF00; 1196 pci_write_config(dev, TL_PCI_LATENCY_TIMER, command, 4); 1197 #endif 1198 1199 /* Allocate interrupt */ 1200 rid = 0; 1201 sc->tl_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 1202 RF_SHAREABLE | RF_ACTIVE); 1203 1204 if (sc->tl_irq == NULL) { 1205 bus_release_resource(dev, TL_RES, TL_RID, sc->tl_res); 1206 printf("tl%d: couldn't map interrupt\n", unit); 1207 error = ENXIO; 1208 goto fail; 1209 } 1210 1211 error = bus_setup_intr(dev, sc->tl_irq, INTR_TYPE_NET, 1212 tl_intr, sc, &sc->tl_intrhand); 1213 1214 if (error) { 1215 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->tl_irq); 1216 bus_release_resource(dev, TL_RES, TL_RID, sc->tl_res); 1217 printf("tl%d: couldn't set up irq\n", unit); 1218 goto fail; 1219 } 1220 1221 /* 1222 * Now allocate memory for the TX and RX lists. 1223 */ 1224 sc->tl_ldata = contigmalloc(sizeof(struct tl_list_data), M_DEVBUF, 1225 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 1226 1227 if (sc->tl_ldata == NULL) { 1228 bus_teardown_intr(dev, sc->tl_irq, sc->tl_intrhand); 1229 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->tl_irq); 1230 bus_release_resource(dev, TL_RES, TL_RID, sc->tl_res); 1231 printf("tl%d: no memory for list buffers!\n", unit); 1232 error = ENXIO; 1233 goto fail; 1234 } 1235 1236 bzero(sc->tl_ldata, sizeof(struct tl_list_data)); 1237 1238 sc->tl_unit = unit; 1239 sc->tl_dinfo = t; 1240 if (t->tl_vid == COMPAQ_VENDORID || t->tl_vid == TI_VENDORID) 1241 sc->tl_eeaddr = TL_EEPROM_EADDR; 1242 if (t->tl_vid == OLICOM_VENDORID) 1243 sc->tl_eeaddr = TL_EEPROM_EADDR_OC; 1244 1245 /* Reset the adapter. */ 1246 tl_softreset(sc, 1); 1247 tl_hardreset(dev); 1248 tl_softreset(sc, 1); 1249 1250 /* 1251 * Get station address from the EEPROM. 1252 */ 1253 if (tl_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr, 1254 sc->tl_eeaddr, ETHER_ADDR_LEN)) { 1255 bus_teardown_intr(dev, sc->tl_irq, sc->tl_intrhand); 1256 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->tl_irq); 1257 bus_release_resource(dev, TL_RES, TL_RID, sc->tl_res); 1258 contigfree(sc->tl_ldata, 1259 sizeof(struct tl_list_data), M_DEVBUF); 1260 printf("tl%d: failed to read station address\n", unit); 1261 error = ENXIO; 1262 goto fail; 1263 } 1264 1265 /* 1266 * XXX Olicom, in its desire to be different from the 1267 * rest of the world, has done strange things with the 1268 * encoding of the station address in the EEPROM. First 1269 * of all, they store the address at offset 0xF8 rather 1270 * than at 0x83 like the ThunderLAN manual suggests. 1271 * Second, they store the address in three 16-bit words in 1272 * network byte order, as opposed to storing it sequentially 1273 * like all the other ThunderLAN cards. In order to get 1274 * the station address in a form that matches what the Olicom 1275 * diagnostic utility specifies, we have to byte-swap each 1276 * word. To make things even more confusing, neither 00:00:28 1277 * nor 00:00:24 appear in the IEEE OUI database. 1278 */ 1279 if (sc->tl_dinfo->tl_vid == OLICOM_VENDORID) { 1280 for (i = 0; i < ETHER_ADDR_LEN; i += 2) { 1281 u_int16_t *p; 1282 p = (u_int16_t *)&sc->arpcom.ac_enaddr[i]; 1283 *p = ntohs(*p); 1284 } 1285 } 1286 1287 ifp = &sc->arpcom.ac_if; 1288 ifp->if_softc = sc; 1289 if_initname(ifp, "tl", sc->tl_unit); 1290 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1291 ifp->if_ioctl = tl_ioctl; 1292 ifp->if_start = tl_start; 1293 ifp->if_watchdog = tl_watchdog; 1294 ifp->if_init = tl_init; 1295 ifp->if_mtu = ETHERMTU; 1296 ifq_set_maxlen(&ifp->if_snd, TL_TX_LIST_CNT - 1); 1297 ifq_set_ready(&ifp->if_snd); 1298 callout_init(&sc->tl_stat_timer); 1299 1300 /* Reset the adapter again. */ 1301 tl_softreset(sc, 1); 1302 tl_hardreset(dev); 1303 tl_softreset(sc, 1); 1304 1305 /* 1306 * Do MII setup. If no PHYs are found, then this is a 1307 * bitrate ThunderLAN chip that only supports 10baseT 1308 * and AUI/BNC. 1309 */ 1310 if (mii_phy_probe(dev, &sc->tl_miibus, 1311 tl_ifmedia_upd, tl_ifmedia_sts)) { 1312 struct ifmedia *ifm; 1313 sc->tl_bitrate = 1; 1314 ifmedia_init(&sc->ifmedia, 0, tl_ifmedia_upd, tl_ifmedia_sts); 1315 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL); 1316 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T|IFM_HDX, 0, NULL); 1317 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL); 1318 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_5, 0, NULL); 1319 ifmedia_set(&sc->ifmedia, IFM_ETHER|IFM_10_T); 1320 /* Reset again, this time setting bitrate mode. */ 1321 tl_softreset(sc, 1); 1322 ifm = &sc->ifmedia; 1323 ifm->ifm_media = ifm->ifm_cur->ifm_media; 1324 tl_ifmedia_upd(ifp); 1325 } 1326 1327 /* 1328 * Call MI attach routine. 1329 */ 1330 ether_ifattach(ifp, sc->arpcom.ac_enaddr); 1331 1332 fail: 1333 splx(s); 1334 return(error); 1335 } 1336 1337 static int tl_detach(dev) 1338 device_t dev; 1339 { 1340 struct tl_softc *sc; 1341 struct ifnet *ifp; 1342 int s; 1343 1344 s = splimp(); 1345 1346 sc = device_get_softc(dev); 1347 ifp = &sc->arpcom.ac_if; 1348 1349 tl_stop(sc); 1350 ether_ifdetach(ifp); 1351 1352 bus_generic_detach(dev); 1353 device_delete_child(dev, sc->tl_miibus); 1354 1355 contigfree(sc->tl_ldata, sizeof(struct tl_list_data), M_DEVBUF); 1356 if (sc->tl_bitrate) 1357 ifmedia_removeall(&sc->ifmedia); 1358 1359 bus_teardown_intr(dev, sc->tl_irq, sc->tl_intrhand); 1360 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->tl_irq); 1361 bus_release_resource(dev, TL_RES, TL_RID, sc->tl_res); 1362 1363 splx(s); 1364 1365 return(0); 1366 } 1367 1368 /* 1369 * Initialize the transmit lists. 1370 */ 1371 static int tl_list_tx_init(sc) 1372 struct tl_softc *sc; 1373 { 1374 struct tl_chain_data *cd; 1375 struct tl_list_data *ld; 1376 int i; 1377 1378 cd = &sc->tl_cdata; 1379 ld = sc->tl_ldata; 1380 for (i = 0; i < TL_TX_LIST_CNT; i++) { 1381 cd->tl_tx_chain[i].tl_ptr = &ld->tl_tx_list[i]; 1382 if (i == (TL_TX_LIST_CNT - 1)) 1383 cd->tl_tx_chain[i].tl_next = NULL; 1384 else 1385 cd->tl_tx_chain[i].tl_next = &cd->tl_tx_chain[i + 1]; 1386 } 1387 1388 cd->tl_tx_free = &cd->tl_tx_chain[0]; 1389 cd->tl_tx_tail = cd->tl_tx_head = NULL; 1390 sc->tl_txeoc = 1; 1391 1392 return(0); 1393 } 1394 1395 /* 1396 * Initialize the RX lists and allocate mbufs for them. 1397 */ 1398 static int tl_list_rx_init(sc) 1399 struct tl_softc *sc; 1400 { 1401 struct tl_chain_data *cd; 1402 struct tl_list_data *ld; 1403 int i; 1404 1405 cd = &sc->tl_cdata; 1406 ld = sc->tl_ldata; 1407 1408 for (i = 0; i < TL_RX_LIST_CNT; i++) { 1409 cd->tl_rx_chain[i].tl_ptr = 1410 (struct tl_list_onefrag *)&ld->tl_rx_list[i]; 1411 if (tl_newbuf(sc, &cd->tl_rx_chain[i]) == ENOBUFS) 1412 return(ENOBUFS); 1413 if (i == (TL_RX_LIST_CNT - 1)) { 1414 cd->tl_rx_chain[i].tl_next = NULL; 1415 ld->tl_rx_list[i].tlist_fptr = 0; 1416 } else { 1417 cd->tl_rx_chain[i].tl_next = &cd->tl_rx_chain[i + 1]; 1418 ld->tl_rx_list[i].tlist_fptr = 1419 vtophys(&ld->tl_rx_list[i + 1]); 1420 } 1421 } 1422 1423 cd->tl_rx_head = &cd->tl_rx_chain[0]; 1424 cd->tl_rx_tail = &cd->tl_rx_chain[TL_RX_LIST_CNT - 1]; 1425 1426 return(0); 1427 } 1428 1429 static int tl_newbuf(sc, c) 1430 struct tl_softc *sc; 1431 struct tl_chain_onefrag *c; 1432 { 1433 struct mbuf *m_new = NULL; 1434 1435 MGETHDR(m_new, MB_DONTWAIT, MT_DATA); 1436 if (m_new == NULL) 1437 return(ENOBUFS); 1438 1439 MCLGET(m_new, MB_DONTWAIT); 1440 if (!(m_new->m_flags & M_EXT)) { 1441 m_freem(m_new); 1442 return(ENOBUFS); 1443 } 1444 1445 #ifdef __alpha__ 1446 m_new->m_data += 2; 1447 #endif 1448 1449 c->tl_mbuf = m_new; 1450 c->tl_next = NULL; 1451 c->tl_ptr->tlist_frsize = MCLBYTES; 1452 c->tl_ptr->tlist_fptr = 0; 1453 c->tl_ptr->tl_frag.tlist_dadr = vtophys(mtod(m_new, caddr_t)); 1454 c->tl_ptr->tl_frag.tlist_dcnt = MCLBYTES; 1455 c->tl_ptr->tlist_cstat = TL_CSTAT_READY; 1456 1457 return(0); 1458 } 1459 /* 1460 * Interrupt handler for RX 'end of frame' condition (EOF). This 1461 * tells us that a full ethernet frame has been captured and we need 1462 * to handle it. 1463 * 1464 * Reception is done using 'lists' which consist of a header and a 1465 * series of 10 data count/data address pairs that point to buffers. 1466 * Initially you're supposed to create a list, populate it with pointers 1467 * to buffers, then load the physical address of the list into the 1468 * ch_parm register. The adapter is then supposed to DMA the received 1469 * frame into the buffers for you. 1470 * 1471 * To make things as fast as possible, we have the chip DMA directly 1472 * into mbufs. This saves us from having to do a buffer copy: we can 1473 * just hand the mbufs directly to ether_input(). Once the frame has 1474 * been sent on its way, the 'list' structure is assigned a new buffer 1475 * and moved to the end of the RX chain. As long we we stay ahead of 1476 * the chip, it will always think it has an endless receive channel. 1477 * 1478 * If we happen to fall behind and the chip manages to fill up all of 1479 * the buffers, it will generate an end of channel interrupt and wait 1480 * for us to empty the chain and restart the receiver. 1481 */ 1482 static int tl_intvec_rxeof(xsc, type) 1483 void *xsc; 1484 u_int32_t type; 1485 { 1486 struct tl_softc *sc; 1487 int r = 0, total_len = 0; 1488 struct ether_header *eh; 1489 struct mbuf *m; 1490 struct ifnet *ifp; 1491 struct tl_chain_onefrag *cur_rx; 1492 1493 sc = xsc; 1494 ifp = &sc->arpcom.ac_if; 1495 1496 while(sc->tl_cdata.tl_rx_head != NULL) { 1497 cur_rx = sc->tl_cdata.tl_rx_head; 1498 if (!(cur_rx->tl_ptr->tlist_cstat & TL_CSTAT_FRAMECMP)) 1499 break; 1500 r++; 1501 sc->tl_cdata.tl_rx_head = cur_rx->tl_next; 1502 m = cur_rx->tl_mbuf; 1503 total_len = cur_rx->tl_ptr->tlist_frsize; 1504 1505 if (tl_newbuf(sc, cur_rx) == ENOBUFS) { 1506 ifp->if_ierrors++; 1507 cur_rx->tl_ptr->tlist_frsize = MCLBYTES; 1508 cur_rx->tl_ptr->tlist_cstat = TL_CSTAT_READY; 1509 cur_rx->tl_ptr->tl_frag.tlist_dcnt = MCLBYTES; 1510 continue; 1511 } 1512 1513 sc->tl_cdata.tl_rx_tail->tl_ptr->tlist_fptr = 1514 vtophys(cur_rx->tl_ptr); 1515 sc->tl_cdata.tl_rx_tail->tl_next = cur_rx; 1516 sc->tl_cdata.tl_rx_tail = cur_rx; 1517 1518 eh = mtod(m, struct ether_header *); 1519 m->m_pkthdr.rcvif = ifp; 1520 1521 /* 1522 * Note: when the ThunderLAN chip is in 'capture all 1523 * frames' mode, it will receive its own transmissions. 1524 * We drop don't need to process our own transmissions, 1525 * so we drop them here and continue. 1526 */ 1527 /*if (ifp->if_flags & IFF_PROMISC && */ 1528 if (!bcmp(eh->ether_shost, sc->arpcom.ac_enaddr, 1529 ETHER_ADDR_LEN)) { 1530 m_freem(m); 1531 continue; 1532 } 1533 1534 (*ifp->if_input)(ifp, m); 1535 } 1536 1537 return(r); 1538 } 1539 1540 /* 1541 * The RX-EOC condition hits when the ch_parm address hasn't been 1542 * initialized or the adapter reached a list with a forward pointer 1543 * of 0 (which indicates the end of the chain). In our case, this means 1544 * the card has hit the end of the receive buffer chain and we need to 1545 * empty out the buffers and shift the pointer back to the beginning again. 1546 */ 1547 static int tl_intvec_rxeoc(xsc, type) 1548 void *xsc; 1549 u_int32_t type; 1550 { 1551 struct tl_softc *sc; 1552 int r; 1553 struct tl_chain_data *cd; 1554 1555 1556 sc = xsc; 1557 cd = &sc->tl_cdata; 1558 1559 /* Flush out the receive queue and ack RXEOF interrupts. */ 1560 r = tl_intvec_rxeof(xsc, type); 1561 CMD_PUT(sc, TL_CMD_ACK | r | (type & ~(0x00100000))); 1562 r = 1; 1563 cd->tl_rx_head = &cd->tl_rx_chain[0]; 1564 cd->tl_rx_tail = &cd->tl_rx_chain[TL_RX_LIST_CNT - 1]; 1565 CSR_WRITE_4(sc, TL_CH_PARM, vtophys(sc->tl_cdata.tl_rx_head->tl_ptr)); 1566 r |= (TL_CMD_GO|TL_CMD_RT); 1567 return(r); 1568 } 1569 1570 static int tl_intvec_txeof(xsc, type) 1571 void *xsc; 1572 u_int32_t type; 1573 { 1574 struct tl_softc *sc; 1575 int r = 0; 1576 struct tl_chain *cur_tx; 1577 1578 sc = xsc; 1579 1580 /* 1581 * Go through our tx list and free mbufs for those 1582 * frames that have been sent. 1583 */ 1584 while (sc->tl_cdata.tl_tx_head != NULL) { 1585 cur_tx = sc->tl_cdata.tl_tx_head; 1586 if (!(cur_tx->tl_ptr->tlist_cstat & TL_CSTAT_FRAMECMP)) 1587 break; 1588 sc->tl_cdata.tl_tx_head = cur_tx->tl_next; 1589 1590 r++; 1591 m_freem(cur_tx->tl_mbuf); 1592 cur_tx->tl_mbuf = NULL; 1593 1594 cur_tx->tl_next = sc->tl_cdata.tl_tx_free; 1595 sc->tl_cdata.tl_tx_free = cur_tx; 1596 if (!cur_tx->tl_ptr->tlist_fptr) 1597 break; 1598 } 1599 1600 return(r); 1601 } 1602 1603 /* 1604 * The transmit end of channel interrupt. The adapter triggers this 1605 * interrupt to tell us it hit the end of the current transmit list. 1606 * 1607 * A note about this: it's possible for a condition to arise where 1608 * tl_start() may try to send frames between TXEOF and TXEOC interrupts. 1609 * You have to avoid this since the chip expects things to go in a 1610 * particular order: transmit, acknowledge TXEOF, acknowledge TXEOC. 1611 * When the TXEOF handler is called, it will free all of the transmitted 1612 * frames and reset the tx_head pointer to NULL. However, a TXEOC 1613 * interrupt should be received and acknowledged before any more frames 1614 * are queued for transmission. If tl_statrt() is called after TXEOF 1615 * resets the tx_head pointer but _before_ the TXEOC interrupt arrives, 1616 * it could attempt to issue a transmit command prematurely. 1617 * 1618 * To guard against this, tl_start() will only issue transmit commands 1619 * if the tl_txeoc flag is set, and only the TXEOC interrupt handler 1620 * can set this flag once tl_start() has cleared it. 1621 */ 1622 static int tl_intvec_txeoc(xsc, type) 1623 void *xsc; 1624 u_int32_t type; 1625 { 1626 struct tl_softc *sc; 1627 struct ifnet *ifp; 1628 u_int32_t cmd; 1629 1630 sc = xsc; 1631 ifp = &sc->arpcom.ac_if; 1632 1633 /* Clear the timeout timer. */ 1634 ifp->if_timer = 0; 1635 1636 if (sc->tl_cdata.tl_tx_head == NULL) { 1637 ifp->if_flags &= ~IFF_OACTIVE; 1638 sc->tl_cdata.tl_tx_tail = NULL; 1639 sc->tl_txeoc = 1; 1640 } else { 1641 sc->tl_txeoc = 0; 1642 /* First we have to ack the EOC interrupt. */ 1643 CMD_PUT(sc, TL_CMD_ACK | 0x00000001 | type); 1644 /* Then load the address of the next TX list. */ 1645 CSR_WRITE_4(sc, TL_CH_PARM, 1646 vtophys(sc->tl_cdata.tl_tx_head->tl_ptr)); 1647 /* Restart TX channel. */ 1648 cmd = CSR_READ_4(sc, TL_HOSTCMD); 1649 cmd &= ~TL_CMD_RT; 1650 cmd |= TL_CMD_GO|TL_CMD_INTSON; 1651 CMD_PUT(sc, cmd); 1652 return(0); 1653 } 1654 1655 return(1); 1656 } 1657 1658 static int tl_intvec_adchk(xsc, type) 1659 void *xsc; 1660 u_int32_t type; 1661 { 1662 struct tl_softc *sc; 1663 1664 sc = xsc; 1665 1666 if (type) 1667 printf("tl%d: adapter check: %x\n", sc->tl_unit, 1668 (unsigned int)CSR_READ_4(sc, TL_CH_PARM)); 1669 1670 tl_softreset(sc, 1); 1671 tl_stop(sc); 1672 tl_init(sc); 1673 CMD_SET(sc, TL_CMD_INTSON); 1674 1675 return(0); 1676 } 1677 1678 static int tl_intvec_netsts(xsc, type) 1679 void *xsc; 1680 u_int32_t type; 1681 { 1682 struct tl_softc *sc; 1683 u_int16_t netsts; 1684 1685 sc = xsc; 1686 1687 netsts = tl_dio_read16(sc, TL_NETSTS); 1688 tl_dio_write16(sc, TL_NETSTS, netsts); 1689 1690 printf("tl%d: network status: %x\n", sc->tl_unit, netsts); 1691 1692 return(1); 1693 } 1694 1695 static void tl_intr(xsc) 1696 void *xsc; 1697 { 1698 struct tl_softc *sc; 1699 struct ifnet *ifp; 1700 int r = 0; 1701 u_int32_t type = 0; 1702 u_int16_t ints = 0; 1703 u_int8_t ivec = 0; 1704 1705 sc = xsc; 1706 1707 /* Disable interrupts */ 1708 ints = CSR_READ_2(sc, TL_HOST_INT); 1709 CSR_WRITE_2(sc, TL_HOST_INT, ints); 1710 type = (ints << 16) & 0xFFFF0000; 1711 ivec = (ints & TL_VEC_MASK) >> 5; 1712 ints = (ints & TL_INT_MASK) >> 2; 1713 1714 ifp = &sc->arpcom.ac_if; 1715 1716 switch(ints) { 1717 case (TL_INTR_INVALID): 1718 #ifdef DIAGNOSTIC 1719 printf("tl%d: got an invalid interrupt!\n", sc->tl_unit); 1720 #endif 1721 /* Re-enable interrupts but don't ack this one. */ 1722 CMD_PUT(sc, type); 1723 r = 0; 1724 break; 1725 case (TL_INTR_TXEOF): 1726 r = tl_intvec_txeof((void *)sc, type); 1727 break; 1728 case (TL_INTR_TXEOC): 1729 r = tl_intvec_txeoc((void *)sc, type); 1730 break; 1731 case (TL_INTR_STATOFLOW): 1732 tl_stats_update(sc); 1733 r = 1; 1734 break; 1735 case (TL_INTR_RXEOF): 1736 r = tl_intvec_rxeof((void *)sc, type); 1737 break; 1738 case (TL_INTR_DUMMY): 1739 printf("tl%d: got a dummy interrupt\n", sc->tl_unit); 1740 r = 1; 1741 break; 1742 case (TL_INTR_ADCHK): 1743 if (ivec) 1744 r = tl_intvec_adchk((void *)sc, type); 1745 else 1746 r = tl_intvec_netsts((void *)sc, type); 1747 break; 1748 case (TL_INTR_RXEOC): 1749 r = tl_intvec_rxeoc((void *)sc, type); 1750 break; 1751 default: 1752 printf("%s: bogus interrupt type\n", ifp->if_xname); 1753 break; 1754 } 1755 1756 /* Re-enable interrupts */ 1757 if (r) { 1758 CMD_PUT(sc, TL_CMD_ACK | r | type); 1759 } 1760 1761 if (!ifq_is_empty(&ifp->if_snd)) 1762 tl_start(ifp); 1763 1764 return; 1765 } 1766 1767 static void tl_stats_update(xsc) 1768 void *xsc; 1769 { 1770 struct tl_softc *sc; 1771 struct ifnet *ifp; 1772 struct tl_stats tl_stats; 1773 struct mii_data *mii; 1774 u_int32_t *p; 1775 int s; 1776 1777 s = splimp(); 1778 1779 bzero((char *)&tl_stats, sizeof(struct tl_stats)); 1780 1781 sc = xsc; 1782 ifp = &sc->arpcom.ac_if; 1783 1784 p = (u_int32_t *)&tl_stats; 1785 1786 CSR_WRITE_2(sc, TL_DIO_ADDR, TL_TXGOODFRAMES|TL_DIO_ADDR_INC); 1787 *p++ = CSR_READ_4(sc, TL_DIO_DATA); 1788 *p++ = CSR_READ_4(sc, TL_DIO_DATA); 1789 *p++ = CSR_READ_4(sc, TL_DIO_DATA); 1790 *p++ = CSR_READ_4(sc, TL_DIO_DATA); 1791 *p++ = CSR_READ_4(sc, TL_DIO_DATA); 1792 1793 ifp->if_opackets += tl_tx_goodframes(tl_stats); 1794 ifp->if_collisions += tl_stats.tl_tx_single_collision + 1795 tl_stats.tl_tx_multi_collision; 1796 ifp->if_ipackets += tl_rx_goodframes(tl_stats); 1797 ifp->if_ierrors += tl_stats.tl_crc_errors + tl_stats.tl_code_errors + 1798 tl_rx_overrun(tl_stats); 1799 ifp->if_oerrors += tl_tx_underrun(tl_stats); 1800 1801 if (tl_tx_underrun(tl_stats)) { 1802 u_int8_t tx_thresh; 1803 tx_thresh = tl_dio_read8(sc, TL_ACOMMIT) & TL_AC_TXTHRESH; 1804 if (tx_thresh != TL_AC_TXTHRESH_WHOLEPKT) { 1805 tx_thresh >>= 4; 1806 tx_thresh++; 1807 printf("tl%d: tx underrun -- increasing " 1808 "tx threshold to %d bytes\n", sc->tl_unit, 1809 (64 * (tx_thresh * 4))); 1810 tl_dio_clrbit(sc, TL_ACOMMIT, TL_AC_TXTHRESH); 1811 tl_dio_setbit(sc, TL_ACOMMIT, tx_thresh << 4); 1812 } 1813 } 1814 1815 callout_reset(&sc->tl_stat_timer, hz, tl_stats_update, sc); 1816 1817 if (!sc->tl_bitrate) { 1818 mii = device_get_softc(sc->tl_miibus); 1819 mii_tick(mii); 1820 } 1821 1822 splx(s); 1823 1824 return; 1825 } 1826 1827 /* 1828 * Encapsulate an mbuf chain in a list by coupling the mbuf data 1829 * pointers to the fragment pointers. 1830 */ 1831 static int tl_encap(sc, c, m_head) 1832 struct tl_softc *sc; 1833 struct tl_chain *c; 1834 struct mbuf *m_head; 1835 { 1836 int frag = 0; 1837 struct tl_frag *f = NULL; 1838 int total_len; 1839 struct mbuf *m; 1840 1841 /* 1842 * Start packing the mbufs in this chain into 1843 * the fragment pointers. Stop when we run out 1844 * of fragments or hit the end of the mbuf chain. 1845 */ 1846 m = m_head; 1847 total_len = 0; 1848 1849 for (m = m_head, frag = 0; m != NULL; m = m->m_next) { 1850 if (m->m_len != 0) { 1851 if (frag == TL_MAXFRAGS) 1852 break; 1853 total_len+= m->m_len; 1854 c->tl_ptr->tl_frag[frag].tlist_dadr = 1855 vtophys(mtod(m, vm_offset_t)); 1856 c->tl_ptr->tl_frag[frag].tlist_dcnt = m->m_len; 1857 frag++; 1858 } 1859 } 1860 1861 /* 1862 * Handle special cases. 1863 * Special case #1: we used up all 10 fragments, but 1864 * we have more mbufs left in the chain. Copy the 1865 * data into an mbuf cluster. Note that we don't 1866 * bother clearing the values in the other fragment 1867 * pointers/counters; it wouldn't gain us anything, 1868 * and would waste cycles. 1869 */ 1870 if (m != NULL) { 1871 struct mbuf *m_new = NULL; 1872 1873 MGETHDR(m_new, MB_DONTWAIT, MT_DATA); 1874 if (m_new == NULL) { 1875 printf("tl%d: no memory for tx list\n", sc->tl_unit); 1876 return(1); 1877 } 1878 if (m_head->m_pkthdr.len > MHLEN) { 1879 MCLGET(m_new, MB_DONTWAIT); 1880 if (!(m_new->m_flags & M_EXT)) { 1881 m_freem(m_new); 1882 printf("tl%d: no memory for tx list\n", 1883 sc->tl_unit); 1884 return(1); 1885 } 1886 } 1887 m_copydata(m_head, 0, m_head->m_pkthdr.len, 1888 mtod(m_new, caddr_t)); 1889 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 1890 m_freem(m_head); 1891 m_head = m_new; 1892 f = &c->tl_ptr->tl_frag[0]; 1893 f->tlist_dadr = vtophys(mtod(m_new, caddr_t)); 1894 f->tlist_dcnt = total_len = m_new->m_len; 1895 frag = 1; 1896 } 1897 1898 /* 1899 * Special case #2: the frame is smaller than the minimum 1900 * frame size. We have to pad it to make the chip happy. 1901 */ 1902 if (total_len < TL_MIN_FRAMELEN) { 1903 if (frag == TL_MAXFRAGS) 1904 printf("tl%d: all frags filled but " 1905 "frame still to small!\n", sc->tl_unit); 1906 f = &c->tl_ptr->tl_frag[frag]; 1907 f->tlist_dcnt = TL_MIN_FRAMELEN - total_len; 1908 f->tlist_dadr = vtophys(&sc->tl_ldata->tl_pad); 1909 total_len += f->tlist_dcnt; 1910 frag++; 1911 } 1912 1913 c->tl_mbuf = m_head; 1914 c->tl_ptr->tl_frag[frag - 1].tlist_dcnt |= TL_LAST_FRAG; 1915 c->tl_ptr->tlist_frsize = total_len; 1916 c->tl_ptr->tlist_cstat = TL_CSTAT_READY; 1917 c->tl_ptr->tlist_fptr = 0; 1918 1919 return(0); 1920 } 1921 1922 /* 1923 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1924 * to the mbuf data regions directly in the transmit lists. We also save a 1925 * copy of the pointers since the transmit list fragment pointers are 1926 * physical addresses. 1927 */ 1928 static void tl_start(ifp) 1929 struct ifnet *ifp; 1930 { 1931 struct tl_softc *sc; 1932 struct mbuf *m_head = NULL; 1933 u_int32_t cmd; 1934 struct tl_chain *prev = NULL, *cur_tx = NULL, *start_tx; 1935 1936 sc = ifp->if_softc; 1937 1938 /* 1939 * Check for an available queue slot. If there are none, 1940 * punt. 1941 */ 1942 if (sc->tl_cdata.tl_tx_free == NULL) { 1943 ifp->if_flags |= IFF_OACTIVE; 1944 return; 1945 } 1946 1947 start_tx = sc->tl_cdata.tl_tx_free; 1948 1949 while(sc->tl_cdata.tl_tx_free != NULL) { 1950 m_head = ifq_dequeue(&ifp->if_snd); 1951 if (m_head == NULL) 1952 break; 1953 1954 /* Pick a chain member off the free list. */ 1955 cur_tx = sc->tl_cdata.tl_tx_free; 1956 sc->tl_cdata.tl_tx_free = cur_tx->tl_next; 1957 1958 cur_tx->tl_next = NULL; 1959 1960 /* Pack the data into the list. */ 1961 tl_encap(sc, cur_tx, m_head); 1962 1963 /* Chain it together */ 1964 if (prev != NULL) { 1965 prev->tl_next = cur_tx; 1966 prev->tl_ptr->tlist_fptr = vtophys(cur_tx->tl_ptr); 1967 } 1968 prev = cur_tx; 1969 1970 BPF_MTAP(ifp, cur_tx->tl_mbuf); 1971 } 1972 1973 /* 1974 * If there are no packets queued, bail. 1975 */ 1976 if (cur_tx == NULL) 1977 return; 1978 1979 /* 1980 * That's all we can stands, we can't stands no more. 1981 * If there are no other transfers pending, then issue the 1982 * TX GO command to the adapter to start things moving. 1983 * Otherwise, just leave the data in the queue and let 1984 * the EOF/EOC interrupt handler send. 1985 */ 1986 if (sc->tl_cdata.tl_tx_head == NULL) { 1987 sc->tl_cdata.tl_tx_head = start_tx; 1988 sc->tl_cdata.tl_tx_tail = cur_tx; 1989 1990 if (sc->tl_txeoc) { 1991 sc->tl_txeoc = 0; 1992 CSR_WRITE_4(sc, TL_CH_PARM, vtophys(start_tx->tl_ptr)); 1993 cmd = CSR_READ_4(sc, TL_HOSTCMD); 1994 cmd &= ~TL_CMD_RT; 1995 cmd |= TL_CMD_GO|TL_CMD_INTSON; 1996 CMD_PUT(sc, cmd); 1997 } 1998 } else { 1999 sc->tl_cdata.tl_tx_tail->tl_next = start_tx; 2000 sc->tl_cdata.tl_tx_tail = cur_tx; 2001 } 2002 2003 /* 2004 * Set a timeout in case the chip goes out to lunch. 2005 */ 2006 ifp->if_timer = 5; 2007 2008 return; 2009 } 2010 2011 static void tl_init(xsc) 2012 void *xsc; 2013 { 2014 struct tl_softc *sc = xsc; 2015 struct ifnet *ifp = &sc->arpcom.ac_if; 2016 int s; 2017 struct mii_data *mii; 2018 2019 s = splimp(); 2020 2021 ifp = &sc->arpcom.ac_if; 2022 2023 /* 2024 * Cancel pending I/O. 2025 */ 2026 tl_stop(sc); 2027 2028 /* Initialize TX FIFO threshold */ 2029 tl_dio_clrbit(sc, TL_ACOMMIT, TL_AC_TXTHRESH); 2030 tl_dio_setbit(sc, TL_ACOMMIT, TL_AC_TXTHRESH_16LONG); 2031 2032 /* Set PCI burst size */ 2033 tl_dio_write8(sc, TL_BSIZEREG, TL_RXBURST_16LONG|TL_TXBURST_16LONG); 2034 2035 /* 2036 * Set 'capture all frames' bit for promiscuous mode. 2037 */ 2038 if (ifp->if_flags & IFF_PROMISC) 2039 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_CAF); 2040 else 2041 tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_CAF); 2042 2043 /* 2044 * Set capture broadcast bit to capture broadcast frames. 2045 */ 2046 if (ifp->if_flags & IFF_BROADCAST) 2047 tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_NOBRX); 2048 else 2049 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_NOBRX); 2050 2051 tl_dio_write16(sc, TL_MAXRX, MCLBYTES); 2052 2053 /* Init our MAC address */ 2054 tl_setfilt(sc, (caddr_t)&sc->arpcom.ac_enaddr, 0); 2055 2056 /* Init multicast filter, if needed. */ 2057 tl_setmulti(sc); 2058 2059 /* Init circular RX list. */ 2060 if (tl_list_rx_init(sc) == ENOBUFS) { 2061 printf("tl%d: initialization failed: no " 2062 "memory for rx buffers\n", sc->tl_unit); 2063 tl_stop(sc); 2064 return; 2065 } 2066 2067 /* Init TX pointers. */ 2068 tl_list_tx_init(sc); 2069 2070 /* Enable PCI interrupts. */ 2071 CMD_SET(sc, TL_CMD_INTSON); 2072 2073 /* Load the address of the rx list */ 2074 CMD_SET(sc, TL_CMD_RT); 2075 CSR_WRITE_4(sc, TL_CH_PARM, vtophys(&sc->tl_ldata->tl_rx_list[0])); 2076 2077 if (!sc->tl_bitrate) { 2078 if (sc->tl_miibus != NULL) { 2079 mii = device_get_softc(sc->tl_miibus); 2080 mii_mediachg(mii); 2081 } 2082 } 2083 2084 /* Send the RX go command */ 2085 CMD_SET(sc, TL_CMD_GO|TL_CMD_NES|TL_CMD_RT); 2086 2087 ifp->if_flags |= IFF_RUNNING; 2088 ifp->if_flags &= ~IFF_OACTIVE; 2089 2090 (void)splx(s); 2091 2092 /* Start the stats update counter */ 2093 callout_reset(&sc->tl_stat_timer, hz, tl_stats_update, sc); 2094 } 2095 2096 /* 2097 * Set media options. 2098 */ 2099 static int tl_ifmedia_upd(ifp) 2100 struct ifnet *ifp; 2101 { 2102 struct tl_softc *sc; 2103 struct mii_data *mii = NULL; 2104 2105 sc = ifp->if_softc; 2106 2107 if (sc->tl_bitrate) 2108 tl_setmode(sc, sc->ifmedia.ifm_media); 2109 else { 2110 mii = device_get_softc(sc->tl_miibus); 2111 mii_mediachg(mii); 2112 } 2113 2114 return(0); 2115 } 2116 2117 /* 2118 * Report current media status. 2119 */ 2120 static void tl_ifmedia_sts(ifp, ifmr) 2121 struct ifnet *ifp; 2122 struct ifmediareq *ifmr; 2123 { 2124 struct tl_softc *sc; 2125 struct mii_data *mii; 2126 2127 sc = ifp->if_softc; 2128 2129 ifmr->ifm_active = IFM_ETHER; 2130 2131 if (sc->tl_bitrate) { 2132 if (tl_dio_read8(sc, TL_ACOMMIT) & TL_AC_MTXD1) 2133 ifmr->ifm_active = IFM_ETHER|IFM_10_5; 2134 else 2135 ifmr->ifm_active = IFM_ETHER|IFM_10_T; 2136 if (tl_dio_read8(sc, TL_ACOMMIT) & TL_AC_MTXD3) 2137 ifmr->ifm_active |= IFM_HDX; 2138 else 2139 ifmr->ifm_active |= IFM_FDX; 2140 return; 2141 } else { 2142 mii = device_get_softc(sc->tl_miibus); 2143 mii_pollstat(mii); 2144 ifmr->ifm_active = mii->mii_media_active; 2145 ifmr->ifm_status = mii->mii_media_status; 2146 } 2147 2148 return; 2149 } 2150 2151 static int tl_ioctl(ifp, command, data, cr) 2152 struct ifnet *ifp; 2153 u_long command; 2154 caddr_t data; 2155 struct ucred *cr; 2156 { 2157 struct tl_softc *sc = ifp->if_softc; 2158 struct ifreq *ifr = (struct ifreq *) data; 2159 int s, error = 0; 2160 2161 s = splimp(); 2162 2163 switch(command) { 2164 case SIOCSIFADDR: 2165 case SIOCGIFADDR: 2166 case SIOCSIFMTU: 2167 error = ether_ioctl(ifp, command, data); 2168 break; 2169 case SIOCSIFFLAGS: 2170 if (ifp->if_flags & IFF_UP) { 2171 if (ifp->if_flags & IFF_RUNNING && 2172 ifp->if_flags & IFF_PROMISC && 2173 !(sc->tl_if_flags & IFF_PROMISC)) { 2174 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_CAF); 2175 tl_setmulti(sc); 2176 } else if (ifp->if_flags & IFF_RUNNING && 2177 !(ifp->if_flags & IFF_PROMISC) && 2178 sc->tl_if_flags & IFF_PROMISC) { 2179 tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_CAF); 2180 tl_setmulti(sc); 2181 } else 2182 tl_init(sc); 2183 } else { 2184 if (ifp->if_flags & IFF_RUNNING) { 2185 tl_stop(sc); 2186 } 2187 } 2188 sc->tl_if_flags = ifp->if_flags; 2189 error = 0; 2190 break; 2191 case SIOCADDMULTI: 2192 case SIOCDELMULTI: 2193 tl_setmulti(sc); 2194 error = 0; 2195 break; 2196 case SIOCSIFMEDIA: 2197 case SIOCGIFMEDIA: 2198 if (sc->tl_bitrate) 2199 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command); 2200 else { 2201 struct mii_data *mii; 2202 mii = device_get_softc(sc->tl_miibus); 2203 error = ifmedia_ioctl(ifp, ifr, 2204 &mii->mii_media, command); 2205 } 2206 break; 2207 default: 2208 error = EINVAL; 2209 break; 2210 } 2211 2212 (void)splx(s); 2213 2214 return(error); 2215 } 2216 2217 static void tl_watchdog(ifp) 2218 struct ifnet *ifp; 2219 { 2220 struct tl_softc *sc; 2221 2222 sc = ifp->if_softc; 2223 2224 printf("tl%d: device timeout\n", sc->tl_unit); 2225 2226 ifp->if_oerrors++; 2227 2228 tl_softreset(sc, 1); 2229 tl_init(sc); 2230 2231 return; 2232 } 2233 2234 /* 2235 * Stop the adapter and free any mbufs allocated to the 2236 * RX and TX lists. 2237 */ 2238 static void tl_stop(sc) 2239 struct tl_softc *sc; 2240 { 2241 int i; 2242 struct ifnet *ifp; 2243 2244 ifp = &sc->arpcom.ac_if; 2245 2246 /* Stop the stats updater. */ 2247 callout_stop(&sc->tl_stat_timer); 2248 2249 /* Stop the transmitter */ 2250 CMD_CLR(sc, TL_CMD_RT); 2251 CMD_SET(sc, TL_CMD_STOP); 2252 CSR_WRITE_4(sc, TL_CH_PARM, 0); 2253 2254 /* Stop the receiver */ 2255 CMD_SET(sc, TL_CMD_RT); 2256 CMD_SET(sc, TL_CMD_STOP); 2257 CSR_WRITE_4(sc, TL_CH_PARM, 0); 2258 2259 /* 2260 * Disable host interrupts. 2261 */ 2262 CMD_SET(sc, TL_CMD_INTSOFF); 2263 2264 /* 2265 * Clear list pointer. 2266 */ 2267 CSR_WRITE_4(sc, TL_CH_PARM, 0); 2268 2269 /* 2270 * Free the RX lists. 2271 */ 2272 for (i = 0; i < TL_RX_LIST_CNT; i++) { 2273 if (sc->tl_cdata.tl_rx_chain[i].tl_mbuf != NULL) { 2274 m_freem(sc->tl_cdata.tl_rx_chain[i].tl_mbuf); 2275 sc->tl_cdata.tl_rx_chain[i].tl_mbuf = NULL; 2276 } 2277 } 2278 bzero((char *)&sc->tl_ldata->tl_rx_list, 2279 sizeof(sc->tl_ldata->tl_rx_list)); 2280 2281 /* 2282 * Free the TX list buffers. 2283 */ 2284 for (i = 0; i < TL_TX_LIST_CNT; i++) { 2285 if (sc->tl_cdata.tl_tx_chain[i].tl_mbuf != NULL) { 2286 m_freem(sc->tl_cdata.tl_tx_chain[i].tl_mbuf); 2287 sc->tl_cdata.tl_tx_chain[i].tl_mbuf = NULL; 2288 } 2289 } 2290 bzero((char *)&sc->tl_ldata->tl_tx_list, 2291 sizeof(sc->tl_ldata->tl_tx_list)); 2292 2293 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2294 2295 return; 2296 } 2297 2298 /* 2299 * Stop all chip I/O so that the kernel's probe routines don't 2300 * get confused by errant DMAs when rebooting. 2301 */ 2302 static void tl_shutdown(dev) 2303 device_t dev; 2304 { 2305 struct tl_softc *sc; 2306 2307 sc = device_get_softc(dev); 2308 2309 tl_stop(sc); 2310 2311 return; 2312 } 2313