1 /* 2 * Copyright (c) 1997, 1998 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: src/sys/pci/if_tl.c,v 1.51.2.5 2001/12/16 15:46:08 luigi Exp $ 33 */ 34 35 /* 36 * Texas Instruments ThunderLAN driver for FreeBSD 2.2.6 and 3.x. 37 * Supports many Compaq PCI NICs based on the ThunderLAN ethernet controller, 38 * the National Semiconductor DP83840A physical interface and the 39 * Microchip Technology 24Cxx series serial EEPROM. 40 * 41 * Written using the following four documents: 42 * 43 * Texas Instruments ThunderLAN Programmer's Guide (www.ti.com) 44 * National Semiconductor DP83840A data sheet (www.national.com) 45 * Microchip Technology 24C02C data sheet (www.microchip.com) 46 * Micro Linear ML6692 100BaseTX only PHY data sheet (www.microlinear.com) 47 * 48 * Written by Bill Paul <wpaul@ctr.columbia.edu> 49 * Electrical Engineering Department 50 * Columbia University, New York City 51 */ 52 53 /* 54 * Some notes about the ThunderLAN: 55 * 56 * The ThunderLAN controller is a single chip containing PCI controller 57 * logic, approximately 3K of on-board SRAM, a LAN controller, and media 58 * independent interface (MII) bus. The MII allows the ThunderLAN chip to 59 * control up to 32 different physical interfaces (PHYs). The ThunderLAN 60 * also has a built-in 10baseT PHY, allowing a single ThunderLAN controller 61 * to act as a complete ethernet interface. 62 * 63 * Other PHYs may be attached to the ThunderLAN; the Compaq 10/100 cards 64 * use a National Semiconductor DP83840A PHY that supports 10 or 100Mb/sec 65 * in full or half duplex. Some of the Compaq Deskpro machines use a 66 * Level 1 LXT970 PHY with the same capabilities. Certain Olicom adapters 67 * use a Micro Linear ML6692 100BaseTX only PHY, which can be used in 68 * concert with the ThunderLAN's internal PHY to provide full 10/100 69 * support. This is cheaper than using a standalone external PHY for both 70 * 10/100 modes and letting the ThunderLAN's internal PHY go to waste. 71 * A serial EEPROM is also attached to the ThunderLAN chip to provide 72 * power-up default register settings and for storing the adapter's 73 * station address. Although not supported by this driver, the ThunderLAN 74 * chip can also be connected to token ring PHYs. 75 * 76 * The ThunderLAN has a set of registers which can be used to issue 77 * commands, acknowledge interrupts, and to manipulate other internal 78 * registers on its DIO bus. The primary registers can be accessed 79 * using either programmed I/O (inb/outb) or via PCI memory mapping, 80 * depending on how the card is configured during the PCI probing 81 * phase. It is even possible to have both PIO and memory mapped 82 * access turned on at the same time. 83 * 84 * Frame reception and transmission with the ThunderLAN chip is done 85 * using frame 'lists.' A list structure looks more or less like this: 86 * 87 * struct tl_frag { 88 * u_int32_t fragment_address; 89 * u_int32_t fragment_size; 90 * }; 91 * struct tl_list { 92 * u_int32_t forward_pointer; 93 * u_int16_t cstat; 94 * u_int16_t frame_size; 95 * struct tl_frag fragments[10]; 96 * }; 97 * 98 * The forward pointer in the list header can be either a 0 or the address 99 * of another list, which allows several lists to be linked together. Each 100 * list contains up to 10 fragment descriptors. This means the chip allows 101 * ethernet frames to be broken up into up to 10 chunks for transfer to 102 * and from the SRAM. Note that the forward pointer and fragment buffer 103 * addresses are physical memory addresses, not virtual. Note also that 104 * a single ethernet frame can not span lists: if the host wants to 105 * transmit a frame and the frame data is split up over more than 10 106 * buffers, the frame has to collapsed before it can be transmitted. 107 * 108 * To receive frames, the driver sets up a number of lists and populates 109 * the fragment descriptors, then it sends an RX GO command to the chip. 110 * When a frame is received, the chip will DMA it into the memory regions 111 * specified by the fragment descriptors and then trigger an RX 'end of 112 * frame interrupt' when done. The driver may choose to use only one 113 * fragment per list; this may result is slighltly less efficient use 114 * of memory in exchange for improving performance. 115 * 116 * To transmit frames, the driver again sets up lists and fragment 117 * descriptors, only this time the buffers contain frame data that 118 * is to be DMA'ed into the chip instead of out of it. Once the chip 119 * has transfered the data into its on-board SRAM, it will trigger a 120 * TX 'end of frame' interrupt. It will also generate an 'end of channel' 121 * interrupt when it reaches the end of the list. 122 */ 123 124 /* 125 * Some notes about this driver: 126 * 127 * The ThunderLAN chip provides a couple of different ways to organize 128 * reception, transmission and interrupt handling. The simplest approach 129 * is to use one list each for transmission and reception. In this mode, 130 * the ThunderLAN will generate two interrupts for every received frame 131 * (one RX EOF and one RX EOC) and two for each transmitted frame (one 132 * TX EOF and one TX EOC). This may make the driver simpler but it hurts 133 * performance to have to handle so many interrupts. 134 * 135 * Initially I wanted to create a circular list of receive buffers so 136 * that the ThunderLAN chip would think there was an infinitely long 137 * receive channel and never deliver an RXEOC interrupt. However this 138 * doesn't work correctly under heavy load: while the manual says the 139 * chip will trigger an RXEOF interrupt each time a frame is copied into 140 * memory, you can't count on the chip waiting around for you to acknowledge 141 * the interrupt before it starts trying to DMA the next frame. The result 142 * is that the chip might traverse the entire circular list and then wrap 143 * around before you have a chance to do anything about it. Consequently, 144 * the receive list is terminated (with a 0 in the forward pointer in the 145 * last element). Each time an RXEOF interrupt arrives, the used list 146 * is shifted to the end of the list. This gives the appearance of an 147 * infinitely large RX chain so long as the driver doesn't fall behind 148 * the chip and allow all of the lists to be filled up. 149 * 150 * If all the lists are filled, the adapter will deliver an RX 'end of 151 * channel' interrupt when it hits the 0 forward pointer at the end of 152 * the chain. The RXEOC handler then cleans out the RX chain and resets 153 * the list head pointer in the ch_parm register and restarts the receiver. 154 * 155 * For frame transmission, it is possible to program the ThunderLAN's 156 * transmit interrupt threshold so that the chip can acknowledge multiple 157 * lists with only a single TX EOF interrupt. This allows the driver to 158 * queue several frames in one shot, and only have to handle a total 159 * two interrupts (one TX EOF and one TX EOC) no matter how many frames 160 * are transmitted. Frame transmission is done directly out of the 161 * mbufs passed to the tl_start() routine via the interface send queue. 162 * The driver simply sets up the fragment descriptors in the transmit 163 * lists to point to the mbuf data regions and sends a TX GO command. 164 * 165 * Note that since the RX and TX lists themselves are always used 166 * only by the driver, the are malloc()ed once at driver initialization 167 * time and never free()ed. 168 * 169 * Also, in order to remain as platform independent as possible, this 170 * driver uses memory mapped register access to manipulate the card 171 * as opposed to programmed I/O. This avoids the use of the inb/outb 172 * (and related) instructions which are specific to the i386 platform. 173 * 174 * Using these techniques, this driver achieves very high performance 175 * by minimizing the amount of interrupts generated during large 176 * transfers and by completely avoiding buffer copies. Frame transfer 177 * to and from the ThunderLAN chip is performed entirely by the chip 178 * itself thereby reducing the load on the host CPU. 179 */ 180 181 #include <sys/param.h> 182 #include <sys/systm.h> 183 #include <sys/sockio.h> 184 #include <sys/mbuf.h> 185 #include <sys/malloc.h> 186 #include <sys/kernel.h> 187 #include <sys/socket.h> 188 #include <sys/serialize.h> 189 #include <sys/bus.h> 190 #include <sys/rman.h> 191 #include <sys/thread2.h> 192 #include <sys/interrupt.h> 193 194 #include <net/if.h> 195 #include <net/ifq_var.h> 196 #include <net/if_arp.h> 197 #include <net/ethernet.h> 198 #include <net/if_dl.h> 199 #include <net/if_media.h> 200 201 #include <net/bpf.h> 202 203 #include <vm/vm.h> /* for vtophys */ 204 #include <vm/pmap.h> /* for vtophys */ 205 206 #include "../mii_layer/mii.h" 207 #include "../mii_layer/miivar.h" 208 209 #include <bus/pci/pcireg.h> 210 #include <bus/pci/pcivar.h> 211 212 /* 213 * Default to using PIO register access mode to pacify certain 214 * laptop docking stations with built-in ThunderLAN chips that 215 * don't seem to handle memory mapped mode properly. 216 */ 217 #define TL_USEIOSPACE 218 219 #include "if_tlreg.h" 220 221 /* "controller miibus0" required. See GENERIC if you get errors here. */ 222 #include "miibus_if.h" 223 224 /* 225 * Various supported device vendors/types and their names. 226 */ 227 228 static struct tl_type tl_devs[] = { 229 { TI_VENDORID, TI_DEVICEID_THUNDERLAN, 230 "Texas Instruments ThunderLAN" }, 231 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10, 232 "Compaq Netelligent 10" }, 233 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100, 234 "Compaq Netelligent 10/100" }, 235 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100_PROLIANT, 236 "Compaq Netelligent 10/100 Proliant" }, 237 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100_DUAL, 238 "Compaq Netelligent 10/100 Dual Port" }, 239 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETFLEX_3P_INTEGRATED, 240 "Compaq NetFlex-3/P Integrated" }, 241 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETFLEX_3P, 242 "Compaq NetFlex-3/P" }, 243 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETFLEX_3P_BNC, 244 "Compaq NetFlex 3/P w/ BNC" }, 245 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100_EMBEDDED, 246 "Compaq Netelligent 10/100 TX Embedded UTP" }, 247 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_T2_UTP_COAX, 248 "Compaq Netelligent 10 T/2 PCI UTP/Coax" }, 249 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100_TX_UTP, 250 "Compaq Netelligent 10/100 TX UTP" }, 251 { OLICOM_VENDORID, OLICOM_DEVICEID_OC2183, 252 "Olicom OC-2183/2185" }, 253 { OLICOM_VENDORID, OLICOM_DEVICEID_OC2325, 254 "Olicom OC-2325" }, 255 { OLICOM_VENDORID, OLICOM_DEVICEID_OC2326, 256 "Olicom OC-2326 10/100 TX UTP" }, 257 { 0, 0, NULL } 258 }; 259 260 static int tl_probe (device_t); 261 static int tl_attach (device_t); 262 static int tl_detach (device_t); 263 static int tl_intvec_rxeoc (void *, u_int32_t); 264 static int tl_intvec_txeoc (void *, u_int32_t); 265 static int tl_intvec_txeof (void *, u_int32_t); 266 static int tl_intvec_rxeof (void *, u_int32_t); 267 static int tl_intvec_adchk (void *, u_int32_t); 268 static int tl_intvec_netsts (void *, u_int32_t); 269 270 static int tl_newbuf (struct tl_softc *, 271 struct tl_chain_onefrag *); 272 static void tl_stats_update (void *); 273 static void tl_stats_update_serialized(void *); 274 static int tl_encap (struct tl_softc *, struct tl_chain *, 275 struct mbuf *); 276 277 static void tl_intr (void *); 278 static void tl_start (struct ifnet *, struct ifaltq_subque *); 279 static int tl_ioctl (struct ifnet *, u_long, caddr_t, 280 struct ucred *); 281 static void tl_init (void *); 282 static void tl_stop (struct tl_softc *); 283 static void tl_watchdog (struct ifnet *); 284 static void tl_shutdown (device_t); 285 static int tl_ifmedia_upd (struct ifnet *); 286 static void tl_ifmedia_sts (struct ifnet *, struct ifmediareq *); 287 288 static u_int8_t tl_eeprom_putbyte (struct tl_softc *, int); 289 static u_int8_t tl_eeprom_getbyte (struct tl_softc *, 290 int, u_int8_t *); 291 static int tl_read_eeprom (struct tl_softc *, caddr_t, int, int); 292 293 static void tl_mii_sync (struct tl_softc *); 294 static void tl_mii_send (struct tl_softc *, u_int32_t, int); 295 static int tl_mii_readreg (struct tl_softc *, struct tl_mii_frame *); 296 static int tl_mii_writereg (struct tl_softc *, struct tl_mii_frame *); 297 static int tl_miibus_readreg (device_t, int, int); 298 static int tl_miibus_writereg (device_t, int, int, int); 299 static void tl_miibus_statchg (device_t); 300 301 static void tl_setmode (struct tl_softc *, int); 302 static int tl_calchash (caddr_t); 303 static void tl_setmulti (struct tl_softc *); 304 static void tl_setfilt (struct tl_softc *, caddr_t, int); 305 static void tl_softreset (struct tl_softc *, int); 306 static void tl_hardreset (device_t); 307 static int tl_list_rx_init (struct tl_softc *); 308 static int tl_list_tx_init (struct tl_softc *); 309 310 static u_int8_t tl_dio_read8 (struct tl_softc *, int); 311 static u_int16_t tl_dio_read16 (struct tl_softc *, int); 312 static u_int32_t tl_dio_read32 (struct tl_softc *, int); 313 static void tl_dio_write8 (struct tl_softc *, int, int); 314 static void tl_dio_write16 (struct tl_softc *, int, int); 315 static void tl_dio_write32 (struct tl_softc *, int, int); 316 static void tl_dio_setbit (struct tl_softc *, int, int); 317 static void tl_dio_clrbit (struct tl_softc *, int, int); 318 static void tl_dio_setbit16 (struct tl_softc *, int, int); 319 static void tl_dio_clrbit16 (struct tl_softc *, int, int); 320 321 #ifdef TL_USEIOSPACE 322 #define TL_RES SYS_RES_IOPORT 323 #define TL_RID TL_PCI_LOIO 324 #else 325 #define TL_RES SYS_RES_MEMORY 326 #define TL_RID TL_PCI_LOMEM 327 #endif 328 329 static device_method_t tl_methods[] = { 330 /* Device interface */ 331 DEVMETHOD(device_probe, tl_probe), 332 DEVMETHOD(device_attach, tl_attach), 333 DEVMETHOD(device_detach, tl_detach), 334 DEVMETHOD(device_shutdown, tl_shutdown), 335 336 /* bus interface */ 337 DEVMETHOD(bus_print_child, bus_generic_print_child), 338 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 339 340 /* MII interface */ 341 DEVMETHOD(miibus_readreg, tl_miibus_readreg), 342 DEVMETHOD(miibus_writereg, tl_miibus_writereg), 343 DEVMETHOD(miibus_statchg, tl_miibus_statchg), 344 345 DEVMETHOD_END 346 }; 347 348 static driver_t tl_driver = { 349 "tl", 350 tl_methods, 351 sizeof(struct tl_softc) 352 }; 353 354 static devclass_t tl_devclass; 355 356 DECLARE_DUMMY_MODULE(if_tl); 357 DRIVER_MODULE(if_tl, pci, tl_driver, tl_devclass, NULL, NULL); 358 DRIVER_MODULE(miibus, tl, miibus_driver, miibus_devclass, NULL, NULL); 359 360 static u_int8_t 361 tl_dio_read8(struct tl_softc *sc, int reg) 362 { 363 CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 364 return(CSR_READ_1(sc, TL_DIO_DATA + (reg & 3))); 365 } 366 367 static u_int16_t 368 tl_dio_read16(struct tl_softc *sc, int reg) 369 { 370 CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 371 return(CSR_READ_2(sc, TL_DIO_DATA + (reg & 3))); 372 } 373 374 static u_int32_t 375 tl_dio_read32(struct tl_softc *sc, int reg) 376 { 377 CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 378 return(CSR_READ_4(sc, TL_DIO_DATA + (reg & 3))); 379 } 380 381 static void 382 tl_dio_write8(struct tl_softc *sc, int reg, int val) 383 { 384 CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 385 CSR_WRITE_1(sc, TL_DIO_DATA + (reg & 3), val); 386 return; 387 } 388 389 static void 390 tl_dio_write16(struct tl_softc *sc, int reg, int val) 391 { 392 CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 393 CSR_WRITE_2(sc, TL_DIO_DATA + (reg & 3), val); 394 return; 395 } 396 397 static void 398 tl_dio_write32(struct tl_softc *sc, int reg, int val) 399 { 400 CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 401 CSR_WRITE_4(sc, TL_DIO_DATA + (reg & 3), val); 402 return; 403 } 404 405 static void 406 tl_dio_setbit(struct tl_softc *sc, int reg, int bit) 407 { 408 u_int8_t f; 409 410 CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 411 f = CSR_READ_1(sc, TL_DIO_DATA + (reg & 3)); 412 f |= bit; 413 CSR_WRITE_1(sc, TL_DIO_DATA + (reg & 3), f); 414 415 return; 416 } 417 418 static void 419 tl_dio_clrbit(struct tl_softc *sc, int reg, int bit) 420 { 421 u_int8_t f; 422 423 CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 424 f = CSR_READ_1(sc, TL_DIO_DATA + (reg & 3)); 425 f &= ~bit; 426 CSR_WRITE_1(sc, TL_DIO_DATA + (reg & 3), f); 427 428 return; 429 } 430 431 static void 432 tl_dio_setbit16(struct tl_softc *sc, int reg, int bit) 433 { 434 u_int16_t f; 435 436 CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 437 f = CSR_READ_2(sc, TL_DIO_DATA + (reg & 3)); 438 f |= bit; 439 CSR_WRITE_2(sc, TL_DIO_DATA + (reg & 3), f); 440 441 return; 442 } 443 444 static void 445 tl_dio_clrbit16(struct tl_softc *sc, int reg, int bit) 446 { 447 u_int16_t f; 448 449 CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 450 f = CSR_READ_2(sc, TL_DIO_DATA + (reg & 3)); 451 f &= ~bit; 452 CSR_WRITE_2(sc, TL_DIO_DATA + (reg & 3), f); 453 454 return; 455 } 456 457 /* 458 * Send an instruction or address to the EEPROM, check for ACK. 459 */ 460 static u_int8_t 461 tl_eeprom_putbyte(struct tl_softc *sc, int byte) 462 { 463 int i, ack = 0; 464 465 /* 466 * Make sure we're in TX mode. 467 */ 468 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ETXEN); 469 470 /* 471 * Feed in each bit and stobe the clock. 472 */ 473 for (i = 0x80; i; i >>= 1) { 474 if (byte & i) { 475 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_EDATA); 476 } else { 477 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_EDATA); 478 } 479 DELAY(1); 480 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ECLOK); 481 DELAY(1); 482 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ECLOK); 483 } 484 485 /* 486 * Turn off TX mode. 487 */ 488 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ETXEN); 489 490 /* 491 * Check for ack. 492 */ 493 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ECLOK); 494 ack = tl_dio_read8(sc, TL_NETSIO) & TL_SIO_EDATA; 495 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ECLOK); 496 497 return(ack); 498 } 499 500 /* 501 * Read a byte of data stored in the EEPROM at address 'addr.' 502 */ 503 static u_int8_t 504 tl_eeprom_getbyte(struct tl_softc *sc, int addr, u_int8_t *dest) 505 { 506 int i; 507 u_int8_t byte = 0; 508 509 tl_dio_write8(sc, TL_NETSIO, 0); 510 511 EEPROM_START; 512 513 /* 514 * Send write control code to EEPROM. 515 */ 516 if (tl_eeprom_putbyte(sc, EEPROM_CTL_WRITE)) { 517 if_printf(&sc->arpcom.ac_if, "failed to send write command, " 518 "status: %x\n", tl_dio_read8(sc, TL_NETSIO)); 519 return(1); 520 } 521 522 /* 523 * Send address of byte we want to read. 524 */ 525 if (tl_eeprom_putbyte(sc, addr)) { 526 if_printf(&sc->arpcom.ac_if, "failed to send address, " 527 "status: %x\n", tl_dio_read8(sc, TL_NETSIO)); 528 return(1); 529 } 530 531 EEPROM_STOP; 532 EEPROM_START; 533 /* 534 * Send read control code to EEPROM. 535 */ 536 if (tl_eeprom_putbyte(sc, EEPROM_CTL_READ)) { 537 if_printf(&sc->arpcom.ac_if, "failed to send write command, " 538 "status: %x\n", tl_dio_read8(sc, TL_NETSIO)); 539 return(1); 540 } 541 542 /* 543 * Start reading bits from EEPROM. 544 */ 545 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ETXEN); 546 for (i = 0x80; i; i >>= 1) { 547 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ECLOK); 548 DELAY(1); 549 if (tl_dio_read8(sc, TL_NETSIO) & TL_SIO_EDATA) 550 byte |= i; 551 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ECLOK); 552 DELAY(1); 553 } 554 555 EEPROM_STOP; 556 557 /* 558 * No ACK generated for read, so just return byte. 559 */ 560 561 *dest = byte; 562 563 return(0); 564 } 565 566 /* 567 * Read a sequence of bytes from the EEPROM. 568 */ 569 static int 570 tl_read_eeprom(struct tl_softc *sc, caddr_t dest, int off, int cnt) 571 { 572 int err = 0, i; 573 u_int8_t byte = 0; 574 575 for (i = 0; i < cnt; i++) { 576 err = tl_eeprom_getbyte(sc, off + i, &byte); 577 if (err) 578 break; 579 *(dest + i) = byte; 580 } 581 582 return(err ? 1 : 0); 583 } 584 585 static void 586 tl_mii_sync(struct tl_softc *sc) 587 { 588 int i; 589 590 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MTXEN); 591 592 for (i = 0; i < 32; i++) { 593 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK); 594 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK); 595 } 596 597 return; 598 } 599 600 static void 601 tl_mii_send(struct tl_softc *sc, u_int32_t bits, int cnt) 602 { 603 int i; 604 605 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 606 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK); 607 if (bits & i) { 608 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MDATA); 609 } else { 610 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MDATA); 611 } 612 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK); 613 } 614 } 615 616 static int 617 tl_mii_readreg(struct tl_softc *sc, struct tl_mii_frame *frame) 618 { 619 int i, ack; 620 int minten = 0; 621 622 tl_mii_sync(sc); 623 624 /* 625 * Set up frame for RX. 626 */ 627 frame->mii_stdelim = TL_MII_STARTDELIM; 628 frame->mii_opcode = TL_MII_READOP; 629 frame->mii_turnaround = 0; 630 frame->mii_data = 0; 631 632 /* 633 * Turn off MII interrupt by forcing MINTEN low. 634 */ 635 minten = tl_dio_read8(sc, TL_NETSIO) & TL_SIO_MINTEN; 636 if (minten) { 637 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MINTEN); 638 } 639 640 /* 641 * Turn on data xmit. 642 */ 643 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MTXEN); 644 645 /* 646 * Send command/address info. 647 */ 648 tl_mii_send(sc, frame->mii_stdelim, 2); 649 tl_mii_send(sc, frame->mii_opcode, 2); 650 tl_mii_send(sc, frame->mii_phyaddr, 5); 651 tl_mii_send(sc, frame->mii_regaddr, 5); 652 653 /* 654 * Turn off xmit. 655 */ 656 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MTXEN); 657 658 /* Idle bit */ 659 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK); 660 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK); 661 662 /* Check for ack */ 663 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK); 664 ack = tl_dio_read8(sc, TL_NETSIO) & TL_SIO_MDATA; 665 666 /* Complete the cycle */ 667 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK); 668 669 /* 670 * Now try reading data bits. If the ack failed, we still 671 * need to clock through 16 cycles to keep the PHYs in sync. 672 */ 673 if (ack) { 674 for(i = 0; i < 16; i++) { 675 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK); 676 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK); 677 } 678 goto fail; 679 } 680 681 for (i = 0x8000; i; i >>= 1) { 682 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK); 683 if (!ack) { 684 if (tl_dio_read8(sc, TL_NETSIO) & TL_SIO_MDATA) 685 frame->mii_data |= i; 686 } 687 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK); 688 } 689 690 fail: 691 692 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK); 693 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK); 694 695 /* Reenable interrupts */ 696 if (minten) { 697 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MINTEN); 698 } 699 700 if (ack) 701 return(1); 702 return(0); 703 } 704 705 static int 706 tl_mii_writereg(struct tl_softc *sc, struct tl_mii_frame *frame) 707 { 708 int minten; 709 710 tl_mii_sync(sc); 711 712 /* 713 * Set up frame for TX. 714 */ 715 716 frame->mii_stdelim = TL_MII_STARTDELIM; 717 frame->mii_opcode = TL_MII_WRITEOP; 718 frame->mii_turnaround = TL_MII_TURNAROUND; 719 720 /* 721 * Turn off MII interrupt by forcing MINTEN low. 722 */ 723 minten = tl_dio_read8(sc, TL_NETSIO) & TL_SIO_MINTEN; 724 if (minten) { 725 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MINTEN); 726 } 727 728 /* 729 * Turn on data output. 730 */ 731 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MTXEN); 732 733 tl_mii_send(sc, frame->mii_stdelim, 2); 734 tl_mii_send(sc, frame->mii_opcode, 2); 735 tl_mii_send(sc, frame->mii_phyaddr, 5); 736 tl_mii_send(sc, frame->mii_regaddr, 5); 737 tl_mii_send(sc, frame->mii_turnaround, 2); 738 tl_mii_send(sc, frame->mii_data, 16); 739 740 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK); 741 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK); 742 743 /* 744 * Turn off xmit. 745 */ 746 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MTXEN); 747 748 /* Reenable interrupts */ 749 if (minten) 750 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MINTEN); 751 752 return(0); 753 } 754 755 static int 756 tl_miibus_readreg(device_t dev, int phy, int reg) 757 { 758 struct tl_softc *sc; 759 struct tl_mii_frame frame; 760 761 sc = device_get_softc(dev); 762 bzero((char *)&frame, sizeof(frame)); 763 764 frame.mii_phyaddr = phy; 765 frame.mii_regaddr = reg; 766 tl_mii_readreg(sc, &frame); 767 768 return(frame.mii_data); 769 } 770 771 static int 772 tl_miibus_writereg(device_t dev, int phy, int reg, int data) 773 { 774 struct tl_softc *sc; 775 struct tl_mii_frame frame; 776 777 sc = device_get_softc(dev); 778 bzero((char *)&frame, sizeof(frame)); 779 780 frame.mii_phyaddr = phy; 781 frame.mii_regaddr = reg; 782 frame.mii_data = data; 783 784 tl_mii_writereg(sc, &frame); 785 786 return(0); 787 } 788 789 static void 790 tl_miibus_statchg(device_t dev) 791 { 792 struct tl_softc *sc; 793 struct mii_data *mii; 794 795 sc = device_get_softc(dev); 796 mii = device_get_softc(sc->tl_miibus); 797 798 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 799 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_DUPLEX); 800 } else { 801 tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_DUPLEX); 802 } 803 804 return; 805 } 806 807 /* 808 * Set modes for bitrate devices. 809 */ 810 static void 811 tl_setmode(struct tl_softc *sc, int media) 812 { 813 if (IFM_SUBTYPE(media) == IFM_10_5) 814 tl_dio_setbit(sc, TL_ACOMMIT, TL_AC_MTXD1); 815 if (IFM_SUBTYPE(media) == IFM_10_T) { 816 tl_dio_clrbit(sc, TL_ACOMMIT, TL_AC_MTXD1); 817 if ((media & IFM_GMASK) == IFM_FDX) { 818 tl_dio_clrbit(sc, TL_ACOMMIT, TL_AC_MTXD3); 819 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_DUPLEX); 820 } else { 821 tl_dio_setbit(sc, TL_ACOMMIT, TL_AC_MTXD3); 822 tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_DUPLEX); 823 } 824 } 825 826 return; 827 } 828 829 /* 830 * Calculate the hash of a MAC address for programming the multicast hash 831 * table. This hash is simply the address split into 6-bit chunks 832 * XOR'd, e.g. 833 * byte: 000000|00 1111|1111 22|222222|333333|33 4444|4444 55|555555 834 * bit: 765432|10 7654|3210 76|543210|765432|10 7654|3210 76|543210 835 * Bytes 0-2 and 3-5 are symmetrical, so are folded together. Then 836 * the folded 24-bit value is split into 6-bit portions and XOR'd. 837 */ 838 static int 839 tl_calchash(caddr_t addr) 840 { 841 int t; 842 843 t = (addr[0] ^ addr[3]) << 16 | (addr[1] ^ addr[4]) << 8 | 844 (addr[2] ^ addr[5]); 845 return ((t >> 18) ^ (t >> 12) ^ (t >> 6) ^ t) & 0x3f; 846 } 847 848 /* 849 * The ThunderLAN has a perfect MAC address filter in addition to 850 * the multicast hash filter. The perfect filter can be programmed 851 * with up to four MAC addresses. The first one is always used to 852 * hold the station address, which leaves us free to use the other 853 * three for multicast addresses. 854 */ 855 static void 856 tl_setfilt(struct tl_softc *sc, caddr_t addr, int slot) 857 { 858 int i; 859 u_int16_t regaddr; 860 861 regaddr = TL_AREG0_B5 + (slot * ETHER_ADDR_LEN); 862 863 for (i = 0; i < ETHER_ADDR_LEN; i++) 864 tl_dio_write8(sc, regaddr + i, *(addr + i)); 865 866 return; 867 } 868 869 /* 870 * XXX In FreeBSD 3.0, multicast addresses are managed using a doubly 871 * linked list. This is fine, except addresses are added from the head 872 * end of the list. We want to arrange for 224.0.0.1 (the "all hosts") 873 * group to always be in the perfect filter, but as more groups are added, 874 * the 224.0.0.1 entry (which is always added first) gets pushed down 875 * the list and ends up at the tail. So after 3 or 4 multicast groups 876 * are added, the all-hosts entry gets pushed out of the perfect filter 877 * and into the hash table. 878 * 879 * Because the multicast list is a doubly-linked list as opposed to a 880 * circular queue, we don't have the ability to just grab the tail of 881 * the list and traverse it backwards. Instead, we have to traverse 882 * the list once to find the tail, then traverse it again backwards to 883 * update the multicast filter. 884 */ 885 static void 886 tl_setmulti(struct tl_softc *sc) 887 { 888 struct ifnet *ifp; 889 u_int32_t hashes[2] = { 0, 0 }; 890 int h, i; 891 struct ifmultiaddr *ifma; 892 u_int8_t dummy[] = { 0, 0, 0, 0, 0 ,0 }; 893 ifp = &sc->arpcom.ac_if; 894 895 /* First, zot all the existing filters. */ 896 for (i = 1; i < 4; i++) 897 tl_setfilt(sc, (caddr_t)&dummy, i); 898 tl_dio_write32(sc, TL_HASH1, 0); 899 tl_dio_write32(sc, TL_HASH2, 0); 900 901 /* Now program new ones. */ 902 if (ifp->if_flags & IFF_ALLMULTI) { 903 hashes[0] = 0xFFFFFFFF; 904 hashes[1] = 0xFFFFFFFF; 905 } else { 906 i = 1; 907 TAILQ_FOREACH_REVERSE(ifma, &ifp->if_multiaddrs, ifmultihead, ifma_link) { 908 if (ifma->ifma_addr->sa_family != AF_LINK) 909 continue; 910 /* 911 * Program the first three multicast groups 912 * into the perfect filter. For all others, 913 * use the hash table. 914 */ 915 if (i < 4) { 916 tl_setfilt(sc, 917 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), i); 918 i++; 919 continue; 920 } 921 922 h = tl_calchash( 923 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 924 if (h < 32) 925 hashes[0] |= (1 << h); 926 else 927 hashes[1] |= (1 << (h - 32)); 928 } 929 } 930 931 tl_dio_write32(sc, TL_HASH1, hashes[0]); 932 tl_dio_write32(sc, TL_HASH2, hashes[1]); 933 934 return; 935 } 936 937 /* 938 * This routine is recommended by the ThunderLAN manual to insure that 939 * the internal PHY is powered up correctly. It also recommends a one 940 * second pause at the end to 'wait for the clocks to start' but in my 941 * experience this isn't necessary. 942 */ 943 static void 944 tl_hardreset(device_t dev) 945 { 946 struct tl_softc *sc; 947 int i; 948 u_int16_t flags; 949 950 sc = device_get_softc(dev); 951 952 tl_mii_sync(sc); 953 954 flags = BMCR_LOOP|BMCR_ISO|BMCR_PDOWN; 955 956 for (i = 0; i < MII_NPHY; i++) 957 tl_miibus_writereg(dev, i, MII_BMCR, flags); 958 959 tl_miibus_writereg(dev, 31, MII_BMCR, BMCR_ISO); 960 DELAY(50000); 961 tl_miibus_writereg(dev, 31, MII_BMCR, BMCR_LOOP|BMCR_ISO); 962 tl_mii_sync(sc); 963 while(tl_miibus_readreg(dev, 31, MII_BMCR) & BMCR_RESET); 964 965 DELAY(50000); 966 return; 967 } 968 969 static void 970 tl_softreset(struct tl_softc *sc, int internal) 971 { 972 u_int32_t cmd, i; 973 974 /* Assert the adapter reset bit. */ 975 CMD_SET(sc, TL_CMD_ADRST); 976 977 /* Turn off interrupts */ 978 CMD_SET(sc, TL_CMD_INTSOFF); 979 980 /* First, clear the stats registers. */ 981 for (i = 0; i < 5; i++) 982 tl_dio_read32(sc, TL_TXGOODFRAMES); 983 984 /* Clear Areg and Hash registers */ 985 for (i = 0; i < 8; i++) 986 tl_dio_write32(sc, TL_AREG0_B5, 0x00000000); 987 988 /* 989 * Set up Netconfig register. Enable one channel and 990 * one fragment mode. 991 */ 992 tl_dio_setbit16(sc, TL_NETCONFIG, TL_CFG_ONECHAN|TL_CFG_ONEFRAG); 993 if (internal && !sc->tl_bitrate) { 994 tl_dio_setbit16(sc, TL_NETCONFIG, TL_CFG_PHYEN); 995 } else { 996 tl_dio_clrbit16(sc, TL_NETCONFIG, TL_CFG_PHYEN); 997 } 998 999 /* Handle cards with bitrate devices. */ 1000 if (sc->tl_bitrate) 1001 tl_dio_setbit16(sc, TL_NETCONFIG, TL_CFG_BITRATE); 1002 1003 /* 1004 * Load adapter irq pacing timer and tx threshold. 1005 * We make the transmit threshold 1 initially but we may 1006 * change that later. 1007 */ 1008 cmd = CSR_READ_4(sc, TL_HOSTCMD); 1009 cmd |= TL_CMD_NES; 1010 cmd &= ~(TL_CMD_RT|TL_CMD_EOC|TL_CMD_ACK_MASK|TL_CMD_CHSEL_MASK); 1011 CMD_PUT(sc, cmd | (TL_CMD_LDTHR | TX_THR)); 1012 CMD_PUT(sc, cmd | (TL_CMD_LDTMR | 0x00000003)); 1013 1014 /* Unreset the MII */ 1015 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_NMRST); 1016 1017 /* Take the adapter out of reset */ 1018 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_NRESET|TL_CMD_NWRAP); 1019 1020 /* Wait for things to settle down a little. */ 1021 DELAY(500); 1022 1023 return; 1024 } 1025 1026 /* 1027 * Probe for a ThunderLAN chip. Check the PCI vendor and device IDs 1028 * against our list and return its name if we find a match. 1029 */ 1030 static int 1031 tl_probe(device_t dev) 1032 { 1033 struct tl_type *t; 1034 1035 t = tl_devs; 1036 1037 while(t->tl_name != NULL) { 1038 if ((pci_get_vendor(dev) == t->tl_vid) && 1039 (pci_get_device(dev) == t->tl_did)) { 1040 device_set_desc(dev, t->tl_name); 1041 return(0); 1042 } 1043 t++; 1044 } 1045 1046 return(ENXIO); 1047 } 1048 1049 static int 1050 tl_attach(device_t dev) 1051 { 1052 int i; 1053 u_int16_t did, vid; 1054 struct tl_type *t; 1055 struct ifnet *ifp; 1056 struct tl_softc *sc; 1057 int error = 0, rid; 1058 uint8_t eaddr[ETHER_ADDR_LEN]; 1059 1060 vid = pci_get_vendor(dev); 1061 did = pci_get_device(dev); 1062 sc = device_get_softc(dev); 1063 1064 t = tl_devs; 1065 while(t->tl_name != NULL) { 1066 if (vid == t->tl_vid && did == t->tl_did) 1067 break; 1068 t++; 1069 } 1070 1071 KKASSERT(t->tl_name != NULL); 1072 1073 pci_enable_busmaster(dev); 1074 1075 #ifdef TL_USEIOSPACE 1076 rid = TL_PCI_LOIO; 1077 sc->tl_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid, 1078 RF_ACTIVE); 1079 1080 /* 1081 * Some cards have the I/O and memory mapped address registers 1082 * reversed. Try both combinations before giving up. 1083 */ 1084 if (sc->tl_res == NULL) { 1085 rid = TL_PCI_LOMEM; 1086 sc->tl_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid, 1087 RF_ACTIVE); 1088 } 1089 #else 1090 rid = TL_PCI_LOMEM; 1091 sc->tl_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 1092 RF_ACTIVE); 1093 if (sc->tl_res == NULL) { 1094 rid = TL_PCI_LOIO; 1095 sc->tl_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 1096 RF_ACTIVE); 1097 } 1098 #endif 1099 1100 if (sc->tl_res == NULL) { 1101 device_printf(dev, "couldn't map ports/memory\n"); 1102 error = ENXIO; 1103 return(error); 1104 } 1105 1106 sc->tl_btag = rman_get_bustag(sc->tl_res); 1107 sc->tl_bhandle = rman_get_bushandle(sc->tl_res); 1108 1109 #ifdef notdef 1110 /* 1111 * The ThunderLAN manual suggests jacking the PCI latency 1112 * timer all the way up to its maximum value. I'm not sure 1113 * if this is really necessary, but what the manual wants, 1114 * the manual gets. 1115 */ 1116 command = pci_read_config(dev, TL_PCI_LATENCY_TIMER, 4); 1117 command |= 0x0000FF00; 1118 pci_write_config(dev, TL_PCI_LATENCY_TIMER, command, 4); 1119 #endif 1120 1121 /* Allocate interrupt */ 1122 rid = 0; 1123 sc->tl_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1124 RF_SHAREABLE | RF_ACTIVE); 1125 1126 if (sc->tl_irq == NULL) { 1127 device_printf(dev, "couldn't map interrupt\n"); 1128 error = ENXIO; 1129 goto fail; 1130 } 1131 1132 /* 1133 * Now allocate memory for the TX and RX lists. 1134 */ 1135 sc->tl_ldata = contigmalloc(sizeof(struct tl_list_data), M_DEVBUF, 1136 M_WAITOK | M_ZERO, 0, 0xffffffff, PAGE_SIZE, 0); 1137 1138 if (sc->tl_ldata == NULL) { 1139 device_printf(dev, "no memory for list buffers!\n"); 1140 error = ENXIO; 1141 goto fail; 1142 } 1143 1144 sc->tl_dinfo = t; 1145 if (t->tl_vid == COMPAQ_VENDORID || t->tl_vid == TI_VENDORID) 1146 sc->tl_eeaddr = TL_EEPROM_EADDR; 1147 if (t->tl_vid == OLICOM_VENDORID) 1148 sc->tl_eeaddr = TL_EEPROM_EADDR_OC; 1149 1150 /* Reset the adapter. */ 1151 tl_softreset(sc, 1); 1152 tl_hardreset(dev); 1153 tl_softreset(sc, 1); 1154 1155 ifp = &sc->arpcom.ac_if; 1156 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1157 1158 /* 1159 * Get station address from the EEPROM. 1160 */ 1161 if (tl_read_eeprom(sc, eaddr, sc->tl_eeaddr, ETHER_ADDR_LEN)) { 1162 device_printf(dev, "failed to read station address\n"); 1163 error = ENXIO; 1164 goto fail; 1165 } 1166 1167 /* 1168 * XXX Olicom, in its desire to be different from the 1169 * rest of the world, has done strange things with the 1170 * encoding of the station address in the EEPROM. First 1171 * of all, they store the address at offset 0xF8 rather 1172 * than at 0x83 like the ThunderLAN manual suggests. 1173 * Second, they store the address in three 16-bit words in 1174 * network byte order, as opposed to storing it sequentially 1175 * like all the other ThunderLAN cards. In order to get 1176 * the station address in a form that matches what the Olicom 1177 * diagnostic utility specifies, we have to byte-swap each 1178 * word. To make things even more confusing, neither 00:00:28 1179 * nor 00:00:24 appear in the IEEE OUI database. 1180 */ 1181 if (sc->tl_dinfo->tl_vid == OLICOM_VENDORID) { 1182 for (i = 0; i < ETHER_ADDR_LEN; i += 2) { 1183 u_int16_t *p; 1184 p = (u_int16_t *)&eaddr[i]; 1185 *p = ntohs(*p); 1186 } 1187 } 1188 1189 ifp->if_softc = sc; 1190 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1191 ifp->if_ioctl = tl_ioctl; 1192 ifp->if_start = tl_start; 1193 ifp->if_watchdog = tl_watchdog; 1194 ifp->if_init = tl_init; 1195 ifp->if_mtu = ETHERMTU; 1196 ifq_set_maxlen(&ifp->if_snd, TL_TX_LIST_CNT - 1); 1197 ifq_set_ready(&ifp->if_snd); 1198 callout_init(&sc->tl_stat_timer); 1199 1200 /* Reset the adapter again. */ 1201 tl_softreset(sc, 1); 1202 tl_hardreset(dev); 1203 tl_softreset(sc, 1); 1204 1205 /* 1206 * Do MII setup. If no PHYs are found, then this is a 1207 * bitrate ThunderLAN chip that only supports 10baseT 1208 * and AUI/BNC. 1209 */ 1210 if (mii_phy_probe(dev, &sc->tl_miibus, 1211 tl_ifmedia_upd, tl_ifmedia_sts)) { 1212 struct ifmedia *ifm; 1213 sc->tl_bitrate = 1; 1214 ifmedia_init(&sc->ifmedia, 0, tl_ifmedia_upd, tl_ifmedia_sts); 1215 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL); 1216 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T|IFM_HDX, 0, NULL); 1217 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL); 1218 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_5, 0, NULL); 1219 ifmedia_set(&sc->ifmedia, IFM_ETHER|IFM_10_T); 1220 /* Reset again, this time setting bitrate mode. */ 1221 tl_softreset(sc, 1); 1222 ifm = &sc->ifmedia; 1223 ifm->ifm_media = ifm->ifm_cur->ifm_media; 1224 tl_ifmedia_upd(ifp); 1225 } 1226 1227 /* 1228 * Call MI attach routine. 1229 */ 1230 ether_ifattach(ifp, eaddr, NULL); 1231 1232 ifq_set_cpuid(&ifp->if_snd, rman_get_cpuid(sc->tl_irq)); 1233 1234 error = bus_setup_intr(dev, sc->tl_irq, INTR_MPSAFE, 1235 tl_intr, sc, &sc->tl_intrhand, 1236 ifp->if_serializer); 1237 1238 if (error) { 1239 ether_ifdetach(ifp); 1240 device_printf(dev, "couldn't set up irq\n"); 1241 goto fail; 1242 } 1243 1244 return(0); 1245 1246 fail: 1247 tl_detach(dev); 1248 return(error); 1249 } 1250 1251 static int 1252 tl_detach(device_t dev) 1253 { 1254 struct tl_softc *sc = device_get_softc(dev); 1255 struct ifnet *ifp = &sc->arpcom.ac_if; 1256 1257 if (device_is_attached(dev)) { 1258 lwkt_serialize_enter(ifp->if_serializer); 1259 tl_stop(sc); 1260 bus_teardown_intr(dev, sc->tl_irq, sc->tl_intrhand); 1261 lwkt_serialize_exit(ifp->if_serializer); 1262 1263 ether_ifdetach(ifp); 1264 } 1265 1266 if (sc->tl_miibus) 1267 device_delete_child(dev, sc->tl_miibus); 1268 bus_generic_detach(dev); 1269 1270 if (sc->tl_ldata) 1271 contigfree(sc->tl_ldata, sizeof(struct tl_list_data), M_DEVBUF); 1272 if (sc->tl_bitrate) 1273 ifmedia_removeall(&sc->ifmedia); 1274 if (sc->tl_irq) 1275 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->tl_irq); 1276 if (sc->tl_res) 1277 bus_release_resource(dev, TL_RES, TL_RID, sc->tl_res); 1278 1279 return(0); 1280 } 1281 1282 /* 1283 * Initialize the transmit lists. 1284 */ 1285 static int 1286 tl_list_tx_init(struct tl_softc *sc) 1287 { 1288 struct tl_chain_data *cd; 1289 struct tl_list_data *ld; 1290 int i; 1291 1292 cd = &sc->tl_cdata; 1293 ld = sc->tl_ldata; 1294 for (i = 0; i < TL_TX_LIST_CNT; i++) { 1295 cd->tl_tx_chain[i].tl_ptr = &ld->tl_tx_list[i]; 1296 if (i == (TL_TX_LIST_CNT - 1)) 1297 cd->tl_tx_chain[i].tl_next = NULL; 1298 else 1299 cd->tl_tx_chain[i].tl_next = &cd->tl_tx_chain[i + 1]; 1300 } 1301 1302 cd->tl_tx_free = &cd->tl_tx_chain[0]; 1303 cd->tl_tx_tail = cd->tl_tx_head = NULL; 1304 sc->tl_txeoc = 1; 1305 1306 return(0); 1307 } 1308 1309 /* 1310 * Initialize the RX lists and allocate mbufs for them. 1311 */ 1312 static int 1313 tl_list_rx_init(struct tl_softc *sc) 1314 { 1315 struct tl_chain_data *cd; 1316 struct tl_list_data *ld; 1317 int i; 1318 1319 cd = &sc->tl_cdata; 1320 ld = sc->tl_ldata; 1321 1322 for (i = 0; i < TL_RX_LIST_CNT; i++) { 1323 cd->tl_rx_chain[i].tl_ptr = 1324 (struct tl_list_onefrag *)&ld->tl_rx_list[i]; 1325 if (tl_newbuf(sc, &cd->tl_rx_chain[i]) == ENOBUFS) 1326 return(ENOBUFS); 1327 if (i == (TL_RX_LIST_CNT - 1)) { 1328 cd->tl_rx_chain[i].tl_next = NULL; 1329 ld->tl_rx_list[i].tlist_fptr = 0; 1330 } else { 1331 cd->tl_rx_chain[i].tl_next = &cd->tl_rx_chain[i + 1]; 1332 ld->tl_rx_list[i].tlist_fptr = 1333 vtophys(&ld->tl_rx_list[i + 1]); 1334 } 1335 } 1336 1337 cd->tl_rx_head = &cd->tl_rx_chain[0]; 1338 cd->tl_rx_tail = &cd->tl_rx_chain[TL_RX_LIST_CNT - 1]; 1339 1340 return(0); 1341 } 1342 1343 static int 1344 tl_newbuf(struct tl_softc *sc, struct tl_chain_onefrag *c) 1345 { 1346 struct mbuf *m_new; 1347 1348 m_new = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR); 1349 if (m_new == NULL) 1350 return (ENOBUFS); 1351 1352 c->tl_mbuf = m_new; 1353 c->tl_next = NULL; 1354 c->tl_ptr->tlist_frsize = MCLBYTES; 1355 c->tl_ptr->tlist_fptr = 0; 1356 c->tl_ptr->tl_frag.tlist_dadr = vtophys(mtod(m_new, caddr_t)); 1357 c->tl_ptr->tl_frag.tlist_dcnt = MCLBYTES; 1358 c->tl_ptr->tlist_cstat = TL_CSTAT_READY; 1359 1360 return(0); 1361 } 1362 1363 /* 1364 * Interrupt handler for RX 'end of frame' condition (EOF). This 1365 * tells us that a full ethernet frame has been captured and we need 1366 * to handle it. 1367 * 1368 * Reception is done using 'lists' which consist of a header and a 1369 * series of 10 data count/data address pairs that point to buffers. 1370 * Initially you're supposed to create a list, populate it with pointers 1371 * to buffers, then load the physical address of the list into the 1372 * ch_parm register. The adapter is then supposed to DMA the received 1373 * frame into the buffers for you. 1374 * 1375 * To make things as fast as possible, we have the chip DMA directly 1376 * into mbufs. This saves us from having to do a buffer copy: we can 1377 * just hand the mbufs directly to ether_input(). Once the frame has 1378 * been sent on its way, the 'list' structure is assigned a new buffer 1379 * and moved to the end of the RX chain. As long we we stay ahead of 1380 * the chip, it will always think it has an endless receive channel. 1381 * 1382 * If we happen to fall behind and the chip manages to fill up all of 1383 * the buffers, it will generate an end of channel interrupt and wait 1384 * for us to empty the chain and restart the receiver. 1385 */ 1386 static int 1387 tl_intvec_rxeof(void *xsc, u_int32_t type) 1388 { 1389 struct tl_softc *sc; 1390 int r = 0, total_len = 0; 1391 struct ether_header *eh; 1392 struct mbuf *m; 1393 struct ifnet *ifp; 1394 struct tl_chain_onefrag *cur_rx; 1395 1396 sc = xsc; 1397 ifp = &sc->arpcom.ac_if; 1398 1399 while(sc->tl_cdata.tl_rx_head != NULL) { 1400 cur_rx = sc->tl_cdata.tl_rx_head; 1401 if (!(cur_rx->tl_ptr->tlist_cstat & TL_CSTAT_FRAMECMP)) 1402 break; 1403 r++; 1404 sc->tl_cdata.tl_rx_head = cur_rx->tl_next; 1405 m = cur_rx->tl_mbuf; 1406 total_len = cur_rx->tl_ptr->tlist_frsize; 1407 1408 if (tl_newbuf(sc, cur_rx) == ENOBUFS) { 1409 IFNET_STAT_INC(ifp, ierrors, 1); 1410 cur_rx->tl_ptr->tlist_frsize = MCLBYTES; 1411 cur_rx->tl_ptr->tlist_cstat = TL_CSTAT_READY; 1412 cur_rx->tl_ptr->tl_frag.tlist_dcnt = MCLBYTES; 1413 continue; 1414 } 1415 1416 sc->tl_cdata.tl_rx_tail->tl_ptr->tlist_fptr = 1417 vtophys(cur_rx->tl_ptr); 1418 sc->tl_cdata.tl_rx_tail->tl_next = cur_rx; 1419 sc->tl_cdata.tl_rx_tail = cur_rx; 1420 1421 eh = mtod(m, struct ether_header *); 1422 m->m_pkthdr.rcvif = ifp; 1423 m->m_pkthdr.len = m->m_len = total_len; 1424 1425 /* 1426 * Note: when the ThunderLAN chip is in 'capture all 1427 * frames' mode, it will receive its own transmissions. 1428 * We drop don't need to process our own transmissions, 1429 * so we drop them here and continue. 1430 */ 1431 /*if (ifp->if_flags & IFF_PROMISC && */ 1432 if (!bcmp(eh->ether_shost, sc->arpcom.ac_enaddr, 1433 ETHER_ADDR_LEN)) { 1434 m_freem(m); 1435 continue; 1436 } 1437 1438 ifp->if_input(ifp, m); 1439 } 1440 1441 return(r); 1442 } 1443 1444 /* 1445 * The RX-EOC condition hits when the ch_parm address hasn't been 1446 * initialized or the adapter reached a list with a forward pointer 1447 * of 0 (which indicates the end of the chain). In our case, this means 1448 * the card has hit the end of the receive buffer chain and we need to 1449 * empty out the buffers and shift the pointer back to the beginning again. 1450 */ 1451 static int 1452 tl_intvec_rxeoc(void *xsc, u_int32_t type) 1453 { 1454 struct tl_softc *sc; 1455 int r; 1456 struct tl_chain_data *cd; 1457 1458 1459 sc = xsc; 1460 cd = &sc->tl_cdata; 1461 1462 /* Flush out the receive queue and ack RXEOF interrupts. */ 1463 r = tl_intvec_rxeof(xsc, type); 1464 CMD_PUT(sc, TL_CMD_ACK | r | (type & ~(0x00100000))); 1465 r = 1; 1466 cd->tl_rx_head = &cd->tl_rx_chain[0]; 1467 cd->tl_rx_tail = &cd->tl_rx_chain[TL_RX_LIST_CNT - 1]; 1468 CSR_WRITE_4(sc, TL_CH_PARM, vtophys(sc->tl_cdata.tl_rx_head->tl_ptr)); 1469 r |= (TL_CMD_GO|TL_CMD_RT); 1470 return(r); 1471 } 1472 1473 static int 1474 tl_intvec_txeof(void *xsc, u_int32_t type) 1475 { 1476 struct tl_softc *sc; 1477 int r = 0; 1478 struct tl_chain *cur_tx; 1479 1480 sc = xsc; 1481 1482 /* 1483 * Go through our tx list and free mbufs for those 1484 * frames that have been sent. 1485 */ 1486 while (sc->tl_cdata.tl_tx_head != NULL) { 1487 cur_tx = sc->tl_cdata.tl_tx_head; 1488 if (!(cur_tx->tl_ptr->tlist_cstat & TL_CSTAT_FRAMECMP)) 1489 break; 1490 sc->tl_cdata.tl_tx_head = cur_tx->tl_next; 1491 1492 r++; 1493 m_freem(cur_tx->tl_mbuf); 1494 cur_tx->tl_mbuf = NULL; 1495 1496 cur_tx->tl_next = sc->tl_cdata.tl_tx_free; 1497 sc->tl_cdata.tl_tx_free = cur_tx; 1498 if (!cur_tx->tl_ptr->tlist_fptr) 1499 break; 1500 } 1501 1502 return(r); 1503 } 1504 1505 /* 1506 * The transmit end of channel interrupt. The adapter triggers this 1507 * interrupt to tell us it hit the end of the current transmit list. 1508 * 1509 * A note about this: it's possible for a condition to arise where 1510 * tl_start() may try to send frames between TXEOF and TXEOC interrupts. 1511 * You have to avoid this since the chip expects things to go in a 1512 * particular order: transmit, acknowledge TXEOF, acknowledge TXEOC. 1513 * When the TXEOF handler is called, it will free all of the transmitted 1514 * frames and reset the tx_head pointer to NULL. However, a TXEOC 1515 * interrupt should be received and acknowledged before any more frames 1516 * are queued for transmission. If tl_statrt() is called after TXEOF 1517 * resets the tx_head pointer but _before_ the TXEOC interrupt arrives, 1518 * it could attempt to issue a transmit command prematurely. 1519 * 1520 * To guard against this, tl_start() will only issue transmit commands 1521 * if the tl_txeoc flag is set, and only the TXEOC interrupt handler 1522 * can set this flag once tl_start() has cleared it. 1523 */ 1524 static int 1525 tl_intvec_txeoc(void *xsc, u_int32_t type) 1526 { 1527 struct tl_softc *sc; 1528 struct ifnet *ifp; 1529 u_int32_t cmd; 1530 1531 sc = xsc; 1532 ifp = &sc->arpcom.ac_if; 1533 1534 /* Clear the timeout timer. */ 1535 ifp->if_timer = 0; 1536 1537 if (sc->tl_cdata.tl_tx_head == NULL) { 1538 ifq_clr_oactive(&ifp->if_snd); 1539 sc->tl_cdata.tl_tx_tail = NULL; 1540 sc->tl_txeoc = 1; 1541 } else { 1542 sc->tl_txeoc = 0; 1543 /* First we have to ack the EOC interrupt. */ 1544 CMD_PUT(sc, TL_CMD_ACK | 0x00000001 | type); 1545 /* Then load the address of the next TX list. */ 1546 CSR_WRITE_4(sc, TL_CH_PARM, 1547 vtophys(sc->tl_cdata.tl_tx_head->tl_ptr)); 1548 /* Restart TX channel. */ 1549 cmd = CSR_READ_4(sc, TL_HOSTCMD); 1550 cmd &= ~TL_CMD_RT; 1551 cmd |= TL_CMD_GO|TL_CMD_INTSON; 1552 CMD_PUT(sc, cmd); 1553 return(0); 1554 } 1555 1556 return(1); 1557 } 1558 1559 static int 1560 tl_intvec_adchk(void *xsc, u_int32_t type) 1561 { 1562 struct tl_softc *sc; 1563 1564 sc = xsc; 1565 1566 if (type) { 1567 if_printf(&sc->arpcom.ac_if, "adapter check: %x\n", 1568 (unsigned int)CSR_READ_4(sc, TL_CH_PARM)); 1569 } 1570 1571 tl_softreset(sc, 1); 1572 tl_stop(sc); 1573 tl_init(sc); 1574 CMD_SET(sc, TL_CMD_INTSON); 1575 1576 return(0); 1577 } 1578 1579 static int 1580 tl_intvec_netsts(void *xsc, u_int32_t type) 1581 { 1582 struct tl_softc *sc; 1583 u_int16_t netsts; 1584 1585 sc = xsc; 1586 1587 netsts = tl_dio_read16(sc, TL_NETSTS); 1588 tl_dio_write16(sc, TL_NETSTS, netsts); 1589 1590 if_printf(&sc->arpcom.ac_if, "network status: %x\n", netsts); 1591 1592 return(1); 1593 } 1594 1595 static void 1596 tl_intr(void *xsc) 1597 { 1598 struct tl_softc *sc; 1599 struct ifnet *ifp; 1600 int r = 0; 1601 u_int32_t type = 0; 1602 u_int16_t ints = 0; 1603 u_int8_t ivec = 0; 1604 1605 sc = xsc; 1606 1607 /* Disable interrupts */ 1608 ints = CSR_READ_2(sc, TL_HOST_INT); 1609 CSR_WRITE_2(sc, TL_HOST_INT, ints); 1610 type = (ints << 16) & 0xFFFF0000; 1611 ivec = (ints & TL_VEC_MASK) >> 5; 1612 ints = (ints & TL_INT_MASK) >> 2; 1613 1614 ifp = &sc->arpcom.ac_if; 1615 1616 switch(ints) { 1617 case (TL_INTR_INVALID): 1618 #ifdef DIAGNOSTIC 1619 if_printf(ifp, "got an invalid interrupt!\n"); 1620 #endif 1621 /* Re-enable interrupts but don't ack this one. */ 1622 CMD_PUT(sc, type); 1623 r = 0; 1624 break; 1625 case (TL_INTR_TXEOF): 1626 r = tl_intvec_txeof(sc, type); 1627 break; 1628 case (TL_INTR_TXEOC): 1629 r = tl_intvec_txeoc(sc, type); 1630 break; 1631 case (TL_INTR_STATOFLOW): 1632 tl_stats_update_serialized(sc); 1633 r = 1; 1634 break; 1635 case (TL_INTR_RXEOF): 1636 r = tl_intvec_rxeof(sc, type); 1637 break; 1638 case (TL_INTR_DUMMY): 1639 if_printf(ifp, "got a dummy interrupt\n"); 1640 r = 1; 1641 break; 1642 case (TL_INTR_ADCHK): 1643 if (ivec) 1644 r = tl_intvec_adchk(sc, type); 1645 else 1646 r = tl_intvec_netsts(sc, type); 1647 break; 1648 case (TL_INTR_RXEOC): 1649 r = tl_intvec_rxeoc(sc, type); 1650 break; 1651 default: 1652 if_printf(ifp, "bogus interrupt type\n"); 1653 break; 1654 } 1655 1656 /* Re-enable interrupts */ 1657 if (r) { 1658 CMD_PUT(sc, TL_CMD_ACK | r | type); 1659 } 1660 1661 if (!ifq_is_empty(&ifp->if_snd)) 1662 if_devstart(ifp); 1663 } 1664 1665 static 1666 void 1667 tl_stats_update(void *xsc) 1668 { 1669 struct tl_softc *sc = xsc; 1670 struct ifnet *ifp = &sc->arpcom.ac_if; 1671 1672 lwkt_serialize_enter(ifp->if_serializer); 1673 tl_stats_update_serialized(xsc); 1674 lwkt_serialize_exit(ifp->if_serializer); 1675 } 1676 1677 static 1678 void 1679 tl_stats_update_serialized(void *xsc) 1680 { 1681 struct tl_softc *sc; 1682 struct ifnet *ifp; 1683 struct tl_stats tl_stats; 1684 struct mii_data *mii; 1685 u_int32_t *p; 1686 1687 bzero((char *)&tl_stats, sizeof(struct tl_stats)); 1688 1689 sc = xsc; 1690 ifp = &sc->arpcom.ac_if; 1691 1692 p = (u_int32_t *)&tl_stats; 1693 1694 CSR_WRITE_2(sc, TL_DIO_ADDR, TL_TXGOODFRAMES|TL_DIO_ADDR_INC); 1695 *p++ = CSR_READ_4(sc, TL_DIO_DATA); 1696 *p++ = CSR_READ_4(sc, TL_DIO_DATA); 1697 *p++ = CSR_READ_4(sc, TL_DIO_DATA); 1698 *p++ = CSR_READ_4(sc, TL_DIO_DATA); 1699 *p++ = CSR_READ_4(sc, TL_DIO_DATA); 1700 1701 IFNET_STAT_INC(ifp, opackets, tl_tx_goodframes(tl_stats)); 1702 IFNET_STAT_INC(ifp, collisions, tl_stats.tl_tx_single_collision + 1703 tl_stats.tl_tx_multi_collision); 1704 IFNET_STAT_INC(ifp, ipackets, tl_rx_goodframes(tl_stats)); 1705 IFNET_STAT_INC(ifp, ierrors, tl_stats.tl_crc_errors + 1706 tl_stats.tl_code_errors + tl_rx_overrun(tl_stats)); 1707 IFNET_STAT_INC(ifp, oerrors, tl_tx_underrun(tl_stats)); 1708 1709 if (tl_tx_underrun(tl_stats)) { 1710 u_int8_t tx_thresh; 1711 tx_thresh = tl_dio_read8(sc, TL_ACOMMIT) & TL_AC_TXTHRESH; 1712 if (tx_thresh != TL_AC_TXTHRESH_WHOLEPKT) { 1713 tx_thresh >>= 4; 1714 tx_thresh++; 1715 if_printf(ifp, "tx underrun -- increasing " 1716 "tx threshold to %d bytes\n", 1717 (64 * (tx_thresh * 4))); 1718 tl_dio_clrbit(sc, TL_ACOMMIT, TL_AC_TXTHRESH); 1719 tl_dio_setbit(sc, TL_ACOMMIT, tx_thresh << 4); 1720 } 1721 } 1722 1723 callout_reset(&sc->tl_stat_timer, hz, tl_stats_update, sc); 1724 1725 if (!sc->tl_bitrate) { 1726 mii = device_get_softc(sc->tl_miibus); 1727 mii_tick(mii); 1728 } 1729 } 1730 1731 /* 1732 * Encapsulate an mbuf chain in a list by coupling the mbuf data 1733 * pointers to the fragment pointers. 1734 */ 1735 static int 1736 tl_encap(struct tl_softc *sc, struct tl_chain *c, struct mbuf *m_head) 1737 { 1738 int frag = 0; 1739 struct tl_frag *f = NULL; 1740 int total_len; 1741 struct mbuf *m; 1742 1743 /* 1744 * Start packing the mbufs in this chain into 1745 * the fragment pointers. Stop when we run out 1746 * of fragments or hit the end of the mbuf chain. 1747 */ 1748 total_len = 0; 1749 1750 for (m = m_head, frag = 0; m != NULL; m = m->m_next) { 1751 if (m->m_len != 0) { 1752 if (frag == TL_MAXFRAGS) 1753 break; 1754 total_len+= m->m_len; 1755 c->tl_ptr->tl_frag[frag].tlist_dadr = 1756 vtophys(mtod(m, vm_offset_t)); 1757 c->tl_ptr->tl_frag[frag].tlist_dcnt = m->m_len; 1758 frag++; 1759 } 1760 } 1761 1762 /* 1763 * Handle special cases. 1764 * Special case #1: we used up all 10 fragments, but 1765 * we have more mbufs left in the chain. Copy the 1766 * data into an mbuf cluster. Note that we don't 1767 * bother clearing the values in the other fragment 1768 * pointers/counters; it wouldn't gain us anything, 1769 * and would waste cycles. 1770 */ 1771 if (m != NULL) { 1772 struct mbuf *m_new; 1773 1774 m_new = m_getl(m_head->m_pkthdr.len, MB_DONTWAIT, MT_DATA, 1775 M_PKTHDR, NULL); 1776 if (m_new == NULL) { 1777 if_printf(&sc->arpcom.ac_if, "no memory for tx list\n"); 1778 return (1); 1779 } 1780 m_copydata(m_head, 0, m_head->m_pkthdr.len, 1781 mtod(m_new, caddr_t)); 1782 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 1783 m_freem(m_head); 1784 m_head = m_new; 1785 f = &c->tl_ptr->tl_frag[0]; 1786 f->tlist_dadr = vtophys(mtod(m_new, caddr_t)); 1787 f->tlist_dcnt = total_len = m_new->m_len; 1788 frag = 1; 1789 } 1790 1791 /* 1792 * Special case #2: the frame is smaller than the minimum 1793 * frame size. We have to pad it to make the chip happy. 1794 */ 1795 if (total_len < TL_MIN_FRAMELEN) { 1796 if (frag == TL_MAXFRAGS) { 1797 if_printf(&sc->arpcom.ac_if, "all frags filled but " 1798 "frame still to small!\n"); 1799 } 1800 f = &c->tl_ptr->tl_frag[frag]; 1801 f->tlist_dcnt = TL_MIN_FRAMELEN - total_len; 1802 f->tlist_dadr = vtophys(&sc->tl_ldata->tl_pad); 1803 total_len += f->tlist_dcnt; 1804 frag++; 1805 } 1806 1807 c->tl_mbuf = m_head; 1808 c->tl_ptr->tl_frag[frag - 1].tlist_dcnt |= TL_LAST_FRAG; 1809 c->tl_ptr->tlist_frsize = total_len; 1810 c->tl_ptr->tlist_cstat = TL_CSTAT_READY; 1811 c->tl_ptr->tlist_fptr = 0; 1812 1813 return(0); 1814 } 1815 1816 /* 1817 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1818 * to the mbuf data regions directly in the transmit lists. We also save a 1819 * copy of the pointers since the transmit list fragment pointers are 1820 * physical addresses. 1821 */ 1822 static void 1823 tl_start(struct ifnet *ifp, struct ifaltq_subque *ifsq) 1824 { 1825 struct tl_softc *sc; 1826 struct mbuf *m_head = NULL; 1827 u_int32_t cmd; 1828 struct tl_chain *prev = NULL, *cur_tx = NULL, *start_tx; 1829 1830 ASSERT_ALTQ_SQ_DEFAULT(ifp, ifsq); 1831 1832 sc = ifp->if_softc; 1833 1834 /* 1835 * Check for an available queue slot. If there are none, 1836 * punt. 1837 */ 1838 if (sc->tl_cdata.tl_tx_free == NULL) { 1839 ifq_set_oactive(&ifp->if_snd); 1840 return; 1841 } 1842 1843 start_tx = sc->tl_cdata.tl_tx_free; 1844 1845 while(sc->tl_cdata.tl_tx_free != NULL) { 1846 m_head = ifq_dequeue(&ifp->if_snd); 1847 if (m_head == NULL) 1848 break; 1849 1850 /* Pick a chain member off the free list. */ 1851 cur_tx = sc->tl_cdata.tl_tx_free; 1852 sc->tl_cdata.tl_tx_free = cur_tx->tl_next; 1853 1854 cur_tx->tl_next = NULL; 1855 1856 /* Pack the data into the list. */ 1857 tl_encap(sc, cur_tx, m_head); 1858 1859 /* Chain it together */ 1860 if (prev != NULL) { 1861 prev->tl_next = cur_tx; 1862 prev->tl_ptr->tlist_fptr = vtophys(cur_tx->tl_ptr); 1863 } 1864 prev = cur_tx; 1865 1866 BPF_MTAP(ifp, cur_tx->tl_mbuf); 1867 } 1868 1869 /* 1870 * If there are no packets queued, bail. 1871 */ 1872 if (cur_tx == NULL) 1873 return; 1874 1875 /* 1876 * That's all we can stands, we can't stands no more. 1877 * If there are no other transfers pending, then issue the 1878 * TX GO command to the adapter to start things moving. 1879 * Otherwise, just leave the data in the queue and let 1880 * the EOF/EOC interrupt handler send. 1881 */ 1882 if (sc->tl_cdata.tl_tx_head == NULL) { 1883 sc->tl_cdata.tl_tx_head = start_tx; 1884 sc->tl_cdata.tl_tx_tail = cur_tx; 1885 1886 if (sc->tl_txeoc) { 1887 sc->tl_txeoc = 0; 1888 CSR_WRITE_4(sc, TL_CH_PARM, vtophys(start_tx->tl_ptr)); 1889 cmd = CSR_READ_4(sc, TL_HOSTCMD); 1890 cmd &= ~TL_CMD_RT; 1891 cmd |= TL_CMD_GO|TL_CMD_INTSON; 1892 CMD_PUT(sc, cmd); 1893 } 1894 } else { 1895 sc->tl_cdata.tl_tx_tail->tl_next = start_tx; 1896 sc->tl_cdata.tl_tx_tail = cur_tx; 1897 } 1898 1899 /* 1900 * Set a timeout in case the chip goes out to lunch. 1901 */ 1902 ifp->if_timer = 5; 1903 1904 return; 1905 } 1906 1907 static void 1908 tl_init(void *xsc) 1909 { 1910 struct tl_softc *sc = xsc; 1911 struct ifnet *ifp = &sc->arpcom.ac_if; 1912 struct mii_data *mii; 1913 1914 /* 1915 * Cancel pending I/O. 1916 */ 1917 tl_stop(sc); 1918 1919 /* Initialize TX FIFO threshold */ 1920 tl_dio_clrbit(sc, TL_ACOMMIT, TL_AC_TXTHRESH); 1921 tl_dio_setbit(sc, TL_ACOMMIT, TL_AC_TXTHRESH_16LONG); 1922 1923 /* Set PCI burst size */ 1924 tl_dio_write8(sc, TL_BSIZEREG, TL_RXBURST_16LONG|TL_TXBURST_16LONG); 1925 1926 /* 1927 * Set 'capture all frames' bit for promiscuous mode. 1928 */ 1929 if (ifp->if_flags & IFF_PROMISC) 1930 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_CAF); 1931 else 1932 tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_CAF); 1933 1934 /* 1935 * Set capture broadcast bit to capture broadcast frames. 1936 */ 1937 if (ifp->if_flags & IFF_BROADCAST) 1938 tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_NOBRX); 1939 else 1940 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_NOBRX); 1941 1942 tl_dio_write16(sc, TL_MAXRX, MCLBYTES); 1943 1944 /* Init our MAC address */ 1945 tl_setfilt(sc, (caddr_t)&sc->arpcom.ac_enaddr, 0); 1946 1947 /* Init multicast filter, if needed. */ 1948 tl_setmulti(sc); 1949 1950 /* Init circular RX list. */ 1951 if (tl_list_rx_init(sc) == ENOBUFS) { 1952 if_printf(ifp, "initialization failed: no " 1953 "memory for rx buffers\n"); 1954 tl_stop(sc); 1955 return; 1956 } 1957 1958 /* Init TX pointers. */ 1959 tl_list_tx_init(sc); 1960 1961 /* Enable PCI interrupts. */ 1962 CMD_SET(sc, TL_CMD_INTSON); 1963 1964 /* Load the address of the rx list */ 1965 CMD_SET(sc, TL_CMD_RT); 1966 CSR_WRITE_4(sc, TL_CH_PARM, vtophys(&sc->tl_ldata->tl_rx_list[0])); 1967 1968 if (!sc->tl_bitrate) { 1969 if (sc->tl_miibus != NULL) { 1970 mii = device_get_softc(sc->tl_miibus); 1971 mii_mediachg(mii); 1972 } 1973 } 1974 1975 /* Send the RX go command */ 1976 CMD_SET(sc, TL_CMD_GO|TL_CMD_NES|TL_CMD_RT); 1977 1978 ifp->if_flags |= IFF_RUNNING; 1979 ifq_clr_oactive(&ifp->if_snd); 1980 1981 /* Start the stats update counter */ 1982 callout_reset(&sc->tl_stat_timer, hz, tl_stats_update, sc); 1983 } 1984 1985 /* 1986 * Set media options. 1987 */ 1988 static int 1989 tl_ifmedia_upd(struct ifnet *ifp) 1990 { 1991 struct tl_softc *sc; 1992 struct mii_data *mii = NULL; 1993 1994 sc = ifp->if_softc; 1995 1996 if (sc->tl_bitrate) 1997 tl_setmode(sc, sc->ifmedia.ifm_media); 1998 else { 1999 mii = device_get_softc(sc->tl_miibus); 2000 mii_mediachg(mii); 2001 } 2002 2003 return(0); 2004 } 2005 2006 /* 2007 * Report current media status. 2008 */ 2009 static void 2010 tl_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 2011 { 2012 struct tl_softc *sc; 2013 struct mii_data *mii; 2014 2015 sc = ifp->if_softc; 2016 2017 ifmr->ifm_active = IFM_ETHER; 2018 2019 if (sc->tl_bitrate) { 2020 if (tl_dio_read8(sc, TL_ACOMMIT) & TL_AC_MTXD1) 2021 ifmr->ifm_active = IFM_ETHER|IFM_10_5; 2022 else 2023 ifmr->ifm_active = IFM_ETHER|IFM_10_T; 2024 if (tl_dio_read8(sc, TL_ACOMMIT) & TL_AC_MTXD3) 2025 ifmr->ifm_active |= IFM_HDX; 2026 else 2027 ifmr->ifm_active |= IFM_FDX; 2028 return; 2029 } else { 2030 mii = device_get_softc(sc->tl_miibus); 2031 mii_pollstat(mii); 2032 ifmr->ifm_active = mii->mii_media_active; 2033 ifmr->ifm_status = mii->mii_media_status; 2034 } 2035 2036 return; 2037 } 2038 2039 static int 2040 tl_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr) 2041 { 2042 struct tl_softc *sc = ifp->if_softc; 2043 struct ifreq *ifr = (struct ifreq *) data; 2044 int error = 0; 2045 2046 switch(command) { 2047 case SIOCSIFFLAGS: 2048 if (ifp->if_flags & IFF_UP) { 2049 if (ifp->if_flags & IFF_RUNNING && 2050 ifp->if_flags & IFF_PROMISC && 2051 !(sc->tl_if_flags & IFF_PROMISC)) { 2052 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_CAF); 2053 tl_setmulti(sc); 2054 } else if (ifp->if_flags & IFF_RUNNING && 2055 !(ifp->if_flags & IFF_PROMISC) && 2056 sc->tl_if_flags & IFF_PROMISC) { 2057 tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_CAF); 2058 tl_setmulti(sc); 2059 } else 2060 tl_init(sc); 2061 } else { 2062 if (ifp->if_flags & IFF_RUNNING) { 2063 tl_stop(sc); 2064 } 2065 } 2066 sc->tl_if_flags = ifp->if_flags; 2067 error = 0; 2068 break; 2069 case SIOCADDMULTI: 2070 case SIOCDELMULTI: 2071 tl_setmulti(sc); 2072 error = 0; 2073 break; 2074 case SIOCSIFMEDIA: 2075 case SIOCGIFMEDIA: 2076 if (sc->tl_bitrate) 2077 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command); 2078 else { 2079 struct mii_data *mii; 2080 mii = device_get_softc(sc->tl_miibus); 2081 error = ifmedia_ioctl(ifp, ifr, 2082 &mii->mii_media, command); 2083 } 2084 break; 2085 default: 2086 error = ether_ioctl(ifp, command, data); 2087 break; 2088 } 2089 return(error); 2090 } 2091 2092 static void 2093 tl_watchdog(struct ifnet *ifp) 2094 { 2095 struct tl_softc *sc; 2096 2097 sc = ifp->if_softc; 2098 2099 if_printf(ifp, "device timeout\n"); 2100 2101 IFNET_STAT_INC(ifp, oerrors, 1); 2102 2103 tl_softreset(sc, 1); 2104 tl_init(sc); 2105 2106 return; 2107 } 2108 2109 /* 2110 * Stop the adapter and free any mbufs allocated to the 2111 * RX and TX lists. 2112 */ 2113 static void 2114 tl_stop(struct tl_softc *sc) 2115 { 2116 int i; 2117 struct ifnet *ifp; 2118 2119 ifp = &sc->arpcom.ac_if; 2120 2121 /* Stop the stats updater. */ 2122 callout_stop(&sc->tl_stat_timer); 2123 2124 /* Stop the transmitter */ 2125 CMD_CLR(sc, TL_CMD_RT); 2126 CMD_SET(sc, TL_CMD_STOP); 2127 CSR_WRITE_4(sc, TL_CH_PARM, 0); 2128 2129 /* Stop the receiver */ 2130 CMD_SET(sc, TL_CMD_RT); 2131 CMD_SET(sc, TL_CMD_STOP); 2132 CSR_WRITE_4(sc, TL_CH_PARM, 0); 2133 2134 /* 2135 * Disable host interrupts. 2136 */ 2137 CMD_SET(sc, TL_CMD_INTSOFF); 2138 2139 /* 2140 * Clear list pointer. 2141 */ 2142 CSR_WRITE_4(sc, TL_CH_PARM, 0); 2143 2144 /* 2145 * Free the RX lists. 2146 */ 2147 for (i = 0; i < TL_RX_LIST_CNT; i++) { 2148 if (sc->tl_cdata.tl_rx_chain[i].tl_mbuf != NULL) { 2149 m_freem(sc->tl_cdata.tl_rx_chain[i].tl_mbuf); 2150 sc->tl_cdata.tl_rx_chain[i].tl_mbuf = NULL; 2151 } 2152 } 2153 bzero((char *)&sc->tl_ldata->tl_rx_list, 2154 sizeof(sc->tl_ldata->tl_rx_list)); 2155 2156 /* 2157 * Free the TX list buffers. 2158 */ 2159 for (i = 0; i < TL_TX_LIST_CNT; i++) { 2160 if (sc->tl_cdata.tl_tx_chain[i].tl_mbuf != NULL) { 2161 m_freem(sc->tl_cdata.tl_tx_chain[i].tl_mbuf); 2162 sc->tl_cdata.tl_tx_chain[i].tl_mbuf = NULL; 2163 } 2164 } 2165 bzero((char *)&sc->tl_ldata->tl_tx_list, 2166 sizeof(sc->tl_ldata->tl_tx_list)); 2167 2168 ifp->if_flags &= ~IFF_RUNNING; 2169 ifq_clr_oactive(&ifp->if_snd); 2170 2171 return; 2172 } 2173 2174 /* 2175 * Stop all chip I/O so that the kernel's probe routines don't 2176 * get confused by errant DMAs when rebooting. 2177 */ 2178 static void 2179 tl_shutdown(device_t dev) 2180 { 2181 struct tl_softc *sc; 2182 2183 sc = device_get_softc(dev); 2184 2185 tl_stop(sc); 2186 2187 return; 2188 } 2189