1 /* 2 * Copyright (c) 1997, 1998 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: src/sys/pci/if_tl.c,v 1.51.2.5 2001/12/16 15:46:08 luigi Exp $ 33 * $DragonFly: src/sys/dev/netif/tl/if_tl.c,v 1.35 2005/12/31 14:08:00 sephe Exp $ 34 */ 35 36 /* 37 * Texas Instruments ThunderLAN driver for FreeBSD 2.2.6 and 3.x. 38 * Supports many Compaq PCI NICs based on the ThunderLAN ethernet controller, 39 * the National Semiconductor DP83840A physical interface and the 40 * Microchip Technology 24Cxx series serial EEPROM. 41 * 42 * Written using the following four documents: 43 * 44 * Texas Instruments ThunderLAN Programmer's Guide (www.ti.com) 45 * National Semiconductor DP83840A data sheet (www.national.com) 46 * Microchip Technology 24C02C data sheet (www.microchip.com) 47 * Micro Linear ML6692 100BaseTX only PHY data sheet (www.microlinear.com) 48 * 49 * Written by Bill Paul <wpaul@ctr.columbia.edu> 50 * Electrical Engineering Department 51 * Columbia University, New York City 52 */ 53 54 /* 55 * Some notes about the ThunderLAN: 56 * 57 * The ThunderLAN controller is a single chip containing PCI controller 58 * logic, approximately 3K of on-board SRAM, a LAN controller, and media 59 * independent interface (MII) bus. The MII allows the ThunderLAN chip to 60 * control up to 32 different physical interfaces (PHYs). The ThunderLAN 61 * also has a built-in 10baseT PHY, allowing a single ThunderLAN controller 62 * to act as a complete ethernet interface. 63 * 64 * Other PHYs may be attached to the ThunderLAN; the Compaq 10/100 cards 65 * use a National Semiconductor DP83840A PHY that supports 10 or 100Mb/sec 66 * in full or half duplex. Some of the Compaq Deskpro machines use a 67 * Level 1 LXT970 PHY with the same capabilities. Certain Olicom adapters 68 * use a Micro Linear ML6692 100BaseTX only PHY, which can be used in 69 * concert with the ThunderLAN's internal PHY to provide full 10/100 70 * support. This is cheaper than using a standalone external PHY for both 71 * 10/100 modes and letting the ThunderLAN's internal PHY go to waste. 72 * A serial EEPROM is also attached to the ThunderLAN chip to provide 73 * power-up default register settings and for storing the adapter's 74 * station address. Although not supported by this driver, the ThunderLAN 75 * chip can also be connected to token ring PHYs. 76 * 77 * The ThunderLAN has a set of registers which can be used to issue 78 * commands, acknowledge interrupts, and to manipulate other internal 79 * registers on its DIO bus. The primary registers can be accessed 80 * using either programmed I/O (inb/outb) or via PCI memory mapping, 81 * depending on how the card is configured during the PCI probing 82 * phase. It is even possible to have both PIO and memory mapped 83 * access turned on at the same time. 84 * 85 * Frame reception and transmission with the ThunderLAN chip is done 86 * using frame 'lists.' A list structure looks more or less like this: 87 * 88 * struct tl_frag { 89 * u_int32_t fragment_address; 90 * u_int32_t fragment_size; 91 * }; 92 * struct tl_list { 93 * u_int32_t forward_pointer; 94 * u_int16_t cstat; 95 * u_int16_t frame_size; 96 * struct tl_frag fragments[10]; 97 * }; 98 * 99 * The forward pointer in the list header can be either a 0 or the address 100 * of another list, which allows several lists to be linked together. Each 101 * list contains up to 10 fragment descriptors. This means the chip allows 102 * ethernet frames to be broken up into up to 10 chunks for transfer to 103 * and from the SRAM. Note that the forward pointer and fragment buffer 104 * addresses are physical memory addresses, not virtual. Note also that 105 * a single ethernet frame can not span lists: if the host wants to 106 * transmit a frame and the frame data is split up over more than 10 107 * buffers, the frame has to collapsed before it can be transmitted. 108 * 109 * To receive frames, the driver sets up a number of lists and populates 110 * the fragment descriptors, then it sends an RX GO command to the chip. 111 * When a frame is received, the chip will DMA it into the memory regions 112 * specified by the fragment descriptors and then trigger an RX 'end of 113 * frame interrupt' when done. The driver may choose to use only one 114 * fragment per list; this may result is slighltly less efficient use 115 * of memory in exchange for improving performance. 116 * 117 * To transmit frames, the driver again sets up lists and fragment 118 * descriptors, only this time the buffers contain frame data that 119 * is to be DMA'ed into the chip instead of out of it. Once the chip 120 * has transfered the data into its on-board SRAM, it will trigger a 121 * TX 'end of frame' interrupt. It will also generate an 'end of channel' 122 * interrupt when it reaches the end of the list. 123 */ 124 125 /* 126 * Some notes about this driver: 127 * 128 * The ThunderLAN chip provides a couple of different ways to organize 129 * reception, transmission and interrupt handling. The simplest approach 130 * is to use one list each for transmission and reception. In this mode, 131 * the ThunderLAN will generate two interrupts for every received frame 132 * (one RX EOF and one RX EOC) and two for each transmitted frame (one 133 * TX EOF and one TX EOC). This may make the driver simpler but it hurts 134 * performance to have to handle so many interrupts. 135 * 136 * Initially I wanted to create a circular list of receive buffers so 137 * that the ThunderLAN chip would think there was an infinitely long 138 * receive channel and never deliver an RXEOC interrupt. However this 139 * doesn't work correctly under heavy load: while the manual says the 140 * chip will trigger an RXEOF interrupt each time a frame is copied into 141 * memory, you can't count on the chip waiting around for you to acknowledge 142 * the interrupt before it starts trying to DMA the next frame. The result 143 * is that the chip might traverse the entire circular list and then wrap 144 * around before you have a chance to do anything about it. Consequently, 145 * the receive list is terminated (with a 0 in the forward pointer in the 146 * last element). Each time an RXEOF interrupt arrives, the used list 147 * is shifted to the end of the list. This gives the appearance of an 148 * infinitely large RX chain so long as the driver doesn't fall behind 149 * the chip and allow all of the lists to be filled up. 150 * 151 * If all the lists are filled, the adapter will deliver an RX 'end of 152 * channel' interrupt when it hits the 0 forward pointer at the end of 153 * the chain. The RXEOC handler then cleans out the RX chain and resets 154 * the list head pointer in the ch_parm register and restarts the receiver. 155 * 156 * For frame transmission, it is possible to program the ThunderLAN's 157 * transmit interrupt threshold so that the chip can acknowledge multiple 158 * lists with only a single TX EOF interrupt. This allows the driver to 159 * queue several frames in one shot, and only have to handle a total 160 * two interrupts (one TX EOF and one TX EOC) no matter how many frames 161 * are transmitted. Frame transmission is done directly out of the 162 * mbufs passed to the tl_start() routine via the interface send queue. 163 * The driver simply sets up the fragment descriptors in the transmit 164 * lists to point to the mbuf data regions and sends a TX GO command. 165 * 166 * Note that since the RX and TX lists themselves are always used 167 * only by the driver, the are malloc()ed once at driver initialization 168 * time and never free()ed. 169 * 170 * Also, in order to remain as platform independent as possible, this 171 * driver uses memory mapped register access to manipulate the card 172 * as opposed to programmed I/O. This avoids the use of the inb/outb 173 * (and related) instructions which are specific to the i386 platform. 174 * 175 * Using these techniques, this driver achieves very high performance 176 * by minimizing the amount of interrupts generated during large 177 * transfers and by completely avoiding buffer copies. Frame transfer 178 * to and from the ThunderLAN chip is performed entirely by the chip 179 * itself thereby reducing the load on the host CPU. 180 */ 181 182 #include <sys/param.h> 183 #include <sys/systm.h> 184 #include <sys/sockio.h> 185 #include <sys/mbuf.h> 186 #include <sys/malloc.h> 187 #include <sys/kernel.h> 188 #include <sys/socket.h> 189 #include <sys/serialize.h> 190 #include <sys/thread2.h> 191 192 #include <net/if.h> 193 #include <net/ifq_var.h> 194 #include <net/if_arp.h> 195 #include <net/ethernet.h> 196 #include <net/if_dl.h> 197 #include <net/if_media.h> 198 199 #include <net/bpf.h> 200 201 #include <vm/vm.h> /* for vtophys */ 202 #include <vm/pmap.h> /* for vtophys */ 203 #include <machine/bus_memio.h> 204 #include <machine/bus_pio.h> 205 #include <machine/bus.h> 206 #include <machine/resource.h> 207 #include <sys/bus.h> 208 #include <sys/rman.h> 209 210 #include "../mii_layer/mii.h" 211 #include "../mii_layer/miivar.h" 212 213 #include <bus/pci/pcireg.h> 214 #include <bus/pci/pcivar.h> 215 216 /* 217 * Default to using PIO register access mode to pacify certain 218 * laptop docking stations with built-in ThunderLAN chips that 219 * don't seem to handle memory mapped mode properly. 220 */ 221 #define TL_USEIOSPACE 222 223 #include "if_tlreg.h" 224 225 /* "controller miibus0" required. See GENERIC if you get errors here. */ 226 #include "miibus_if.h" 227 228 /* 229 * Various supported device vendors/types and their names. 230 */ 231 232 static struct tl_type tl_devs[] = { 233 { TI_VENDORID, TI_DEVICEID_THUNDERLAN, 234 "Texas Instruments ThunderLAN" }, 235 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10, 236 "Compaq Netelligent 10" }, 237 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100, 238 "Compaq Netelligent 10/100" }, 239 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100_PROLIANT, 240 "Compaq Netelligent 10/100 Proliant" }, 241 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100_DUAL, 242 "Compaq Netelligent 10/100 Dual Port" }, 243 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETFLEX_3P_INTEGRATED, 244 "Compaq NetFlex-3/P Integrated" }, 245 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETFLEX_3P, 246 "Compaq NetFlex-3/P" }, 247 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETFLEX_3P_BNC, 248 "Compaq NetFlex 3/P w/ BNC" }, 249 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100_EMBEDDED, 250 "Compaq Netelligent 10/100 TX Embedded UTP" }, 251 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_T2_UTP_COAX, 252 "Compaq Netelligent 10 T/2 PCI UTP/Coax" }, 253 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100_TX_UTP, 254 "Compaq Netelligent 10/100 TX UTP" }, 255 { OLICOM_VENDORID, OLICOM_DEVICEID_OC2183, 256 "Olicom OC-2183/2185" }, 257 { OLICOM_VENDORID, OLICOM_DEVICEID_OC2325, 258 "Olicom OC-2325" }, 259 { OLICOM_VENDORID, OLICOM_DEVICEID_OC2326, 260 "Olicom OC-2326 10/100 TX UTP" }, 261 { 0, 0, NULL } 262 }; 263 264 static int tl_probe (device_t); 265 static int tl_attach (device_t); 266 static int tl_detach (device_t); 267 static int tl_intvec_rxeoc (void *, u_int32_t); 268 static int tl_intvec_txeoc (void *, u_int32_t); 269 static int tl_intvec_txeof (void *, u_int32_t); 270 static int tl_intvec_rxeof (void *, u_int32_t); 271 static int tl_intvec_adchk (void *, u_int32_t); 272 static int tl_intvec_netsts (void *, u_int32_t); 273 274 static int tl_newbuf (struct tl_softc *, 275 struct tl_chain_onefrag *); 276 static void tl_stats_update (void *); 277 static void tl_stats_update_serialized(void *); 278 static int tl_encap (struct tl_softc *, struct tl_chain *, 279 struct mbuf *); 280 281 static void tl_intr (void *); 282 static void tl_start (struct ifnet *); 283 static int tl_ioctl (struct ifnet *, u_long, caddr_t, 284 struct ucred *); 285 static void tl_init (void *); 286 static void tl_stop (struct tl_softc *); 287 static void tl_watchdog (struct ifnet *); 288 static void tl_shutdown (device_t); 289 static int tl_ifmedia_upd (struct ifnet *); 290 static void tl_ifmedia_sts (struct ifnet *, struct ifmediareq *); 291 292 static u_int8_t tl_eeprom_putbyte (struct tl_softc *, int); 293 static u_int8_t tl_eeprom_getbyte (struct tl_softc *, 294 int, u_int8_t *); 295 static int tl_read_eeprom (struct tl_softc *, caddr_t, int, int); 296 297 static void tl_mii_sync (struct tl_softc *); 298 static void tl_mii_send (struct tl_softc *, u_int32_t, int); 299 static int tl_mii_readreg (struct tl_softc *, struct tl_mii_frame *); 300 static int tl_mii_writereg (struct tl_softc *, struct tl_mii_frame *); 301 static int tl_miibus_readreg (device_t, int, int); 302 static int tl_miibus_writereg (device_t, int, int, int); 303 static void tl_miibus_statchg (device_t); 304 305 static void tl_setmode (struct tl_softc *, int); 306 static int tl_calchash (caddr_t); 307 static void tl_setmulti (struct tl_softc *); 308 static void tl_setfilt (struct tl_softc *, caddr_t, int); 309 static void tl_softreset (struct tl_softc *, int); 310 static void tl_hardreset (device_t); 311 static int tl_list_rx_init (struct tl_softc *); 312 static int tl_list_tx_init (struct tl_softc *); 313 314 static u_int8_t tl_dio_read8 (struct tl_softc *, int); 315 static u_int16_t tl_dio_read16 (struct tl_softc *, int); 316 static u_int32_t tl_dio_read32 (struct tl_softc *, int); 317 static void tl_dio_write8 (struct tl_softc *, int, int); 318 static void tl_dio_write16 (struct tl_softc *, int, int); 319 static void tl_dio_write32 (struct tl_softc *, int, int); 320 static void tl_dio_setbit (struct tl_softc *, int, int); 321 static void tl_dio_clrbit (struct tl_softc *, int, int); 322 static void tl_dio_setbit16 (struct tl_softc *, int, int); 323 static void tl_dio_clrbit16 (struct tl_softc *, int, int); 324 325 #ifdef TL_USEIOSPACE 326 #define TL_RES SYS_RES_IOPORT 327 #define TL_RID TL_PCI_LOIO 328 #else 329 #define TL_RES SYS_RES_MEMORY 330 #define TL_RID TL_PCI_LOMEM 331 #endif 332 333 static device_method_t tl_methods[] = { 334 /* Device interface */ 335 DEVMETHOD(device_probe, tl_probe), 336 DEVMETHOD(device_attach, tl_attach), 337 DEVMETHOD(device_detach, tl_detach), 338 DEVMETHOD(device_shutdown, tl_shutdown), 339 340 /* bus interface */ 341 DEVMETHOD(bus_print_child, bus_generic_print_child), 342 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 343 344 /* MII interface */ 345 DEVMETHOD(miibus_readreg, tl_miibus_readreg), 346 DEVMETHOD(miibus_writereg, tl_miibus_writereg), 347 DEVMETHOD(miibus_statchg, tl_miibus_statchg), 348 349 { 0, 0 } 350 }; 351 352 static driver_t tl_driver = { 353 "tl", 354 tl_methods, 355 sizeof(struct tl_softc) 356 }; 357 358 static devclass_t tl_devclass; 359 360 DECLARE_DUMMY_MODULE(if_tl); 361 DRIVER_MODULE(if_tl, pci, tl_driver, tl_devclass, 0, 0); 362 DRIVER_MODULE(miibus, tl, miibus_driver, miibus_devclass, 0, 0); 363 364 static u_int8_t 365 tl_dio_read8(struct tl_softc *sc, int reg) 366 { 367 CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 368 return(CSR_READ_1(sc, TL_DIO_DATA + (reg & 3))); 369 } 370 371 static u_int16_t 372 tl_dio_read16(struct tl_softc *sc, int reg) 373 { 374 CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 375 return(CSR_READ_2(sc, TL_DIO_DATA + (reg & 3))); 376 } 377 378 static u_int32_t 379 tl_dio_read32(struct tl_softc *sc, int reg) 380 { 381 CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 382 return(CSR_READ_4(sc, TL_DIO_DATA + (reg & 3))); 383 } 384 385 static void 386 tl_dio_write8(struct tl_softc *sc, int reg, int val) 387 { 388 CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 389 CSR_WRITE_1(sc, TL_DIO_DATA + (reg & 3), val); 390 return; 391 } 392 393 static void 394 tl_dio_write16(struct tl_softc *sc, int reg, int val) 395 { 396 CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 397 CSR_WRITE_2(sc, TL_DIO_DATA + (reg & 3), val); 398 return; 399 } 400 401 static void 402 tl_dio_write32(struct tl_softc *sc, int reg, int val) 403 { 404 CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 405 CSR_WRITE_4(sc, TL_DIO_DATA + (reg & 3), val); 406 return; 407 } 408 409 static void 410 tl_dio_setbit(struct tl_softc *sc, int reg, int bit) 411 { 412 u_int8_t f; 413 414 CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 415 f = CSR_READ_1(sc, TL_DIO_DATA + (reg & 3)); 416 f |= bit; 417 CSR_WRITE_1(sc, TL_DIO_DATA + (reg & 3), f); 418 419 return; 420 } 421 422 static void 423 tl_dio_clrbit(struct tl_softc *sc, int reg, int bit) 424 { 425 u_int8_t f; 426 427 CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 428 f = CSR_READ_1(sc, TL_DIO_DATA + (reg & 3)); 429 f &= ~bit; 430 CSR_WRITE_1(sc, TL_DIO_DATA + (reg & 3), f); 431 432 return; 433 } 434 435 static void 436 tl_dio_setbit16(struct tl_softc *sc, int reg, int bit) 437 { 438 u_int16_t f; 439 440 CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 441 f = CSR_READ_2(sc, TL_DIO_DATA + (reg & 3)); 442 f |= bit; 443 CSR_WRITE_2(sc, TL_DIO_DATA + (reg & 3), f); 444 445 return; 446 } 447 448 static void 449 tl_dio_clrbit16(struct tl_softc *sc, int reg, int bit) 450 { 451 u_int16_t f; 452 453 CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 454 f = CSR_READ_2(sc, TL_DIO_DATA + (reg & 3)); 455 f &= ~bit; 456 CSR_WRITE_2(sc, TL_DIO_DATA + (reg & 3), f); 457 458 return; 459 } 460 461 /* 462 * Send an instruction or address to the EEPROM, check for ACK. 463 */ 464 static u_int8_t 465 tl_eeprom_putbyte(struct tl_softc *sc, int byte) 466 { 467 int i, ack = 0; 468 469 /* 470 * Make sure we're in TX mode. 471 */ 472 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ETXEN); 473 474 /* 475 * Feed in each bit and stobe the clock. 476 */ 477 for (i = 0x80; i; i >>= 1) { 478 if (byte & i) { 479 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_EDATA); 480 } else { 481 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_EDATA); 482 } 483 DELAY(1); 484 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ECLOK); 485 DELAY(1); 486 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ECLOK); 487 } 488 489 /* 490 * Turn off TX mode. 491 */ 492 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ETXEN); 493 494 /* 495 * Check for ack. 496 */ 497 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ECLOK); 498 ack = tl_dio_read8(sc, TL_NETSIO) & TL_SIO_EDATA; 499 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ECLOK); 500 501 return(ack); 502 } 503 504 /* 505 * Read a byte of data stored in the EEPROM at address 'addr.' 506 */ 507 static u_int8_t 508 tl_eeprom_getbyte(struct tl_softc *sc, int addr, u_int8_t *dest) 509 { 510 int i; 511 u_int8_t byte = 0; 512 513 tl_dio_write8(sc, TL_NETSIO, 0); 514 515 EEPROM_START; 516 517 /* 518 * Send write control code to EEPROM. 519 */ 520 if (tl_eeprom_putbyte(sc, EEPROM_CTL_WRITE)) { 521 if_printf(&sc->arpcom.ac_if, "failed to send write command, " 522 "status: %x\n", tl_dio_read8(sc, TL_NETSIO)); 523 return(1); 524 } 525 526 /* 527 * Send address of byte we want to read. 528 */ 529 if (tl_eeprom_putbyte(sc, addr)) { 530 if_printf(&sc->arpcom.ac_if, "failed to send address, " 531 "status: %x\n", tl_dio_read8(sc, TL_NETSIO)); 532 return(1); 533 } 534 535 EEPROM_STOP; 536 EEPROM_START; 537 /* 538 * Send read control code to EEPROM. 539 */ 540 if (tl_eeprom_putbyte(sc, EEPROM_CTL_READ)) { 541 if_printf(&sc->arpcom.ac_if, "failed to send write command, " 542 "status: %x\n", tl_dio_read8(sc, TL_NETSIO)); 543 return(1); 544 } 545 546 /* 547 * Start reading bits from EEPROM. 548 */ 549 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ETXEN); 550 for (i = 0x80; i; i >>= 1) { 551 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ECLOK); 552 DELAY(1); 553 if (tl_dio_read8(sc, TL_NETSIO) & TL_SIO_EDATA) 554 byte |= i; 555 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ECLOK); 556 DELAY(1); 557 } 558 559 EEPROM_STOP; 560 561 /* 562 * No ACK generated for read, so just return byte. 563 */ 564 565 *dest = byte; 566 567 return(0); 568 } 569 570 /* 571 * Read a sequence of bytes from the EEPROM. 572 */ 573 static int 574 tl_read_eeprom(struct tl_softc *sc, caddr_t dest, int off, int cnt) 575 { 576 int err = 0, i; 577 u_int8_t byte = 0; 578 579 for (i = 0; i < cnt; i++) { 580 err = tl_eeprom_getbyte(sc, off + i, &byte); 581 if (err) 582 break; 583 *(dest + i) = byte; 584 } 585 586 return(err ? 1 : 0); 587 } 588 589 static void 590 tl_mii_sync(struct tl_softc *sc) 591 { 592 int i; 593 594 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MTXEN); 595 596 for (i = 0; i < 32; i++) { 597 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK); 598 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK); 599 } 600 601 return; 602 } 603 604 static void 605 tl_mii_send(struct tl_softc *sc, u_int32_t bits, int cnt) 606 { 607 int i; 608 609 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 610 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK); 611 if (bits & i) { 612 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MDATA); 613 } else { 614 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MDATA); 615 } 616 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK); 617 } 618 } 619 620 static int 621 tl_mii_readreg(struct tl_softc *sc, struct tl_mii_frame *frame) 622 { 623 int i, ack; 624 int minten = 0; 625 626 tl_mii_sync(sc); 627 628 /* 629 * Set up frame for RX. 630 */ 631 frame->mii_stdelim = TL_MII_STARTDELIM; 632 frame->mii_opcode = TL_MII_READOP; 633 frame->mii_turnaround = 0; 634 frame->mii_data = 0; 635 636 /* 637 * Turn off MII interrupt by forcing MINTEN low. 638 */ 639 minten = tl_dio_read8(sc, TL_NETSIO) & TL_SIO_MINTEN; 640 if (minten) { 641 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MINTEN); 642 } 643 644 /* 645 * Turn on data xmit. 646 */ 647 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MTXEN); 648 649 /* 650 * Send command/address info. 651 */ 652 tl_mii_send(sc, frame->mii_stdelim, 2); 653 tl_mii_send(sc, frame->mii_opcode, 2); 654 tl_mii_send(sc, frame->mii_phyaddr, 5); 655 tl_mii_send(sc, frame->mii_regaddr, 5); 656 657 /* 658 * Turn off xmit. 659 */ 660 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MTXEN); 661 662 /* Idle bit */ 663 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK); 664 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK); 665 666 /* Check for ack */ 667 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK); 668 ack = tl_dio_read8(sc, TL_NETSIO) & TL_SIO_MDATA; 669 670 /* Complete the cycle */ 671 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK); 672 673 /* 674 * Now try reading data bits. If the ack failed, we still 675 * need to clock through 16 cycles to keep the PHYs in sync. 676 */ 677 if (ack) { 678 for(i = 0; i < 16; i++) { 679 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK); 680 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK); 681 } 682 goto fail; 683 } 684 685 for (i = 0x8000; i; i >>= 1) { 686 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK); 687 if (!ack) { 688 if (tl_dio_read8(sc, TL_NETSIO) & TL_SIO_MDATA) 689 frame->mii_data |= i; 690 } 691 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK); 692 } 693 694 fail: 695 696 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK); 697 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK); 698 699 /* Reenable interrupts */ 700 if (minten) { 701 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MINTEN); 702 } 703 704 if (ack) 705 return(1); 706 return(0); 707 } 708 709 static int 710 tl_mii_writereg(struct tl_softc *sc, struct tl_mii_frame *frame) 711 { 712 int minten; 713 714 tl_mii_sync(sc); 715 716 /* 717 * Set up frame for TX. 718 */ 719 720 frame->mii_stdelim = TL_MII_STARTDELIM; 721 frame->mii_opcode = TL_MII_WRITEOP; 722 frame->mii_turnaround = TL_MII_TURNAROUND; 723 724 /* 725 * Turn off MII interrupt by forcing MINTEN low. 726 */ 727 minten = tl_dio_read8(sc, TL_NETSIO) & TL_SIO_MINTEN; 728 if (minten) { 729 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MINTEN); 730 } 731 732 /* 733 * Turn on data output. 734 */ 735 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MTXEN); 736 737 tl_mii_send(sc, frame->mii_stdelim, 2); 738 tl_mii_send(sc, frame->mii_opcode, 2); 739 tl_mii_send(sc, frame->mii_phyaddr, 5); 740 tl_mii_send(sc, frame->mii_regaddr, 5); 741 tl_mii_send(sc, frame->mii_turnaround, 2); 742 tl_mii_send(sc, frame->mii_data, 16); 743 744 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK); 745 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK); 746 747 /* 748 * Turn off xmit. 749 */ 750 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MTXEN); 751 752 /* Reenable interrupts */ 753 if (minten) 754 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MINTEN); 755 756 return(0); 757 } 758 759 static int 760 tl_miibus_readreg(device_t dev, int phy, int reg) 761 { 762 struct tl_softc *sc; 763 struct tl_mii_frame frame; 764 765 sc = device_get_softc(dev); 766 bzero((char *)&frame, sizeof(frame)); 767 768 frame.mii_phyaddr = phy; 769 frame.mii_regaddr = reg; 770 tl_mii_readreg(sc, &frame); 771 772 return(frame.mii_data); 773 } 774 775 static int 776 tl_miibus_writereg(device_t dev, int phy, int reg, int data) 777 { 778 struct tl_softc *sc; 779 struct tl_mii_frame frame; 780 781 sc = device_get_softc(dev); 782 bzero((char *)&frame, sizeof(frame)); 783 784 frame.mii_phyaddr = phy; 785 frame.mii_regaddr = reg; 786 frame.mii_data = data; 787 788 tl_mii_writereg(sc, &frame); 789 790 return(0); 791 } 792 793 static void 794 tl_miibus_statchg(device_t dev) 795 { 796 struct tl_softc *sc; 797 struct mii_data *mii; 798 799 sc = device_get_softc(dev); 800 mii = device_get_softc(sc->tl_miibus); 801 802 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 803 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_DUPLEX); 804 } else { 805 tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_DUPLEX); 806 } 807 808 return; 809 } 810 811 /* 812 * Set modes for bitrate devices. 813 */ 814 static void 815 tl_setmode(struct tl_softc *sc, int media) 816 { 817 if (IFM_SUBTYPE(media) == IFM_10_5) 818 tl_dio_setbit(sc, TL_ACOMMIT, TL_AC_MTXD1); 819 if (IFM_SUBTYPE(media) == IFM_10_T) { 820 tl_dio_clrbit(sc, TL_ACOMMIT, TL_AC_MTXD1); 821 if ((media & IFM_GMASK) == IFM_FDX) { 822 tl_dio_clrbit(sc, TL_ACOMMIT, TL_AC_MTXD3); 823 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_DUPLEX); 824 } else { 825 tl_dio_setbit(sc, TL_ACOMMIT, TL_AC_MTXD3); 826 tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_DUPLEX); 827 } 828 } 829 830 return; 831 } 832 833 /* 834 * Calculate the hash of a MAC address for programming the multicast hash 835 * table. This hash is simply the address split into 6-bit chunks 836 * XOR'd, e.g. 837 * byte: 000000|00 1111|1111 22|222222|333333|33 4444|4444 55|555555 838 * bit: 765432|10 7654|3210 76|543210|765432|10 7654|3210 76|543210 839 * Bytes 0-2 and 3-5 are symmetrical, so are folded together. Then 840 * the folded 24-bit value is split into 6-bit portions and XOR'd. 841 */ 842 static int 843 tl_calchash(caddr_t addr) 844 { 845 int t; 846 847 t = (addr[0] ^ addr[3]) << 16 | (addr[1] ^ addr[4]) << 8 | 848 (addr[2] ^ addr[5]); 849 return ((t >> 18) ^ (t >> 12) ^ (t >> 6) ^ t) & 0x3f; 850 } 851 852 /* 853 * The ThunderLAN has a perfect MAC address filter in addition to 854 * the multicast hash filter. The perfect filter can be programmed 855 * with up to four MAC addresses. The first one is always used to 856 * hold the station address, which leaves us free to use the other 857 * three for multicast addresses. 858 */ 859 static void 860 tl_setfilt(struct tl_softc *sc, caddr_t addr, int slot) 861 { 862 int i; 863 u_int16_t regaddr; 864 865 regaddr = TL_AREG0_B5 + (slot * ETHER_ADDR_LEN); 866 867 for (i = 0; i < ETHER_ADDR_LEN; i++) 868 tl_dio_write8(sc, regaddr + i, *(addr + i)); 869 870 return; 871 } 872 873 /* 874 * XXX In FreeBSD 3.0, multicast addresses are managed using a doubly 875 * linked list. This is fine, except addresses are added from the head 876 * end of the list. We want to arrange for 224.0.0.1 (the "all hosts") 877 * group to always be in the perfect filter, but as more groups are added, 878 * the 224.0.0.1 entry (which is always added first) gets pushed down 879 * the list and ends up at the tail. So after 3 or 4 multicast groups 880 * are added, the all-hosts entry gets pushed out of the perfect filter 881 * and into the hash table. 882 * 883 * Because the multicast list is a doubly-linked list as opposed to a 884 * circular queue, we don't have the ability to just grab the tail of 885 * the list and traverse it backwards. Instead, we have to traverse 886 * the list once to find the tail, then traverse it again backwards to 887 * update the multicast filter. 888 */ 889 static void 890 tl_setmulti(struct tl_softc *sc) 891 { 892 struct ifnet *ifp; 893 u_int32_t hashes[2] = { 0, 0 }; 894 int h, i; 895 struct ifmultiaddr *ifma; 896 u_int8_t dummy[] = { 0, 0, 0, 0, 0 ,0 }; 897 ifp = &sc->arpcom.ac_if; 898 899 /* First, zot all the existing filters. */ 900 for (i = 1; i < 4; i++) 901 tl_setfilt(sc, (caddr_t)&dummy, i); 902 tl_dio_write32(sc, TL_HASH1, 0); 903 tl_dio_write32(sc, TL_HASH2, 0); 904 905 /* Now program new ones. */ 906 if (ifp->if_flags & IFF_ALLMULTI) { 907 hashes[0] = 0xFFFFFFFF; 908 hashes[1] = 0xFFFFFFFF; 909 } else { 910 i = 1; 911 /* First find the tail of the list. */ 912 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 913 ifma = ifma->ifma_link.le_next) { 914 if (ifma->ifma_link.le_next == NULL) 915 break; 916 } 917 /* Now traverse the list backwards. */ 918 for (; ifma != NULL && ifma != (void *)&ifp->if_multiaddrs; 919 ifma = (struct ifmultiaddr *)ifma->ifma_link.le_prev) { 920 if (ifma->ifma_addr->sa_family != AF_LINK) 921 continue; 922 /* 923 * Program the first three multicast groups 924 * into the perfect filter. For all others, 925 * use the hash table. 926 */ 927 if (i < 4) { 928 tl_setfilt(sc, 929 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), i); 930 i++; 931 continue; 932 } 933 934 h = tl_calchash( 935 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 936 if (h < 32) 937 hashes[0] |= (1 << h); 938 else 939 hashes[1] |= (1 << (h - 32)); 940 } 941 } 942 943 tl_dio_write32(sc, TL_HASH1, hashes[0]); 944 tl_dio_write32(sc, TL_HASH2, hashes[1]); 945 946 return; 947 } 948 949 /* 950 * This routine is recommended by the ThunderLAN manual to insure that 951 * the internal PHY is powered up correctly. It also recommends a one 952 * second pause at the end to 'wait for the clocks to start' but in my 953 * experience this isn't necessary. 954 */ 955 static void 956 tl_hardreset(device_t dev) 957 { 958 struct tl_softc *sc; 959 int i; 960 u_int16_t flags; 961 962 sc = device_get_softc(dev); 963 964 tl_mii_sync(sc); 965 966 flags = BMCR_LOOP|BMCR_ISO|BMCR_PDOWN; 967 968 for (i = 0; i < MII_NPHY; i++) 969 tl_miibus_writereg(dev, i, MII_BMCR, flags); 970 971 tl_miibus_writereg(dev, 31, MII_BMCR, BMCR_ISO); 972 DELAY(50000); 973 tl_miibus_writereg(dev, 31, MII_BMCR, BMCR_LOOP|BMCR_ISO); 974 tl_mii_sync(sc); 975 while(tl_miibus_readreg(dev, 31, MII_BMCR) & BMCR_RESET); 976 977 DELAY(50000); 978 return; 979 } 980 981 static void 982 tl_softreset(struct tl_softc *sc, int internal) 983 { 984 u_int32_t cmd, dummy, i; 985 986 /* Assert the adapter reset bit. */ 987 CMD_SET(sc, TL_CMD_ADRST); 988 989 /* Turn off interrupts */ 990 CMD_SET(sc, TL_CMD_INTSOFF); 991 992 /* First, clear the stats registers. */ 993 for (i = 0; i < 5; i++) 994 dummy = tl_dio_read32(sc, TL_TXGOODFRAMES); 995 996 /* Clear Areg and Hash registers */ 997 for (i = 0; i < 8; i++) 998 tl_dio_write32(sc, TL_AREG0_B5, 0x00000000); 999 1000 /* 1001 * Set up Netconfig register. Enable one channel and 1002 * one fragment mode. 1003 */ 1004 tl_dio_setbit16(sc, TL_NETCONFIG, TL_CFG_ONECHAN|TL_CFG_ONEFRAG); 1005 if (internal && !sc->tl_bitrate) { 1006 tl_dio_setbit16(sc, TL_NETCONFIG, TL_CFG_PHYEN); 1007 } else { 1008 tl_dio_clrbit16(sc, TL_NETCONFIG, TL_CFG_PHYEN); 1009 } 1010 1011 /* Handle cards with bitrate devices. */ 1012 if (sc->tl_bitrate) 1013 tl_dio_setbit16(sc, TL_NETCONFIG, TL_CFG_BITRATE); 1014 1015 /* 1016 * Load adapter irq pacing timer and tx threshold. 1017 * We make the transmit threshold 1 initially but we may 1018 * change that later. 1019 */ 1020 cmd = CSR_READ_4(sc, TL_HOSTCMD); 1021 cmd |= TL_CMD_NES; 1022 cmd &= ~(TL_CMD_RT|TL_CMD_EOC|TL_CMD_ACK_MASK|TL_CMD_CHSEL_MASK); 1023 CMD_PUT(sc, cmd | (TL_CMD_LDTHR | TX_THR)); 1024 CMD_PUT(sc, cmd | (TL_CMD_LDTMR | 0x00000003)); 1025 1026 /* Unreset the MII */ 1027 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_NMRST); 1028 1029 /* Take the adapter out of reset */ 1030 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_NRESET|TL_CMD_NWRAP); 1031 1032 /* Wait for things to settle down a little. */ 1033 DELAY(500); 1034 1035 return; 1036 } 1037 1038 /* 1039 * Probe for a ThunderLAN chip. Check the PCI vendor and device IDs 1040 * against our list and return its name if we find a match. 1041 */ 1042 static int 1043 tl_probe(device_t dev) 1044 { 1045 struct tl_type *t; 1046 1047 t = tl_devs; 1048 1049 while(t->tl_name != NULL) { 1050 if ((pci_get_vendor(dev) == t->tl_vid) && 1051 (pci_get_device(dev) == t->tl_did)) { 1052 device_set_desc(dev, t->tl_name); 1053 return(0); 1054 } 1055 t++; 1056 } 1057 1058 return(ENXIO); 1059 } 1060 1061 static int 1062 tl_attach(device_t dev) 1063 { 1064 int i; 1065 u_int16_t did, vid; 1066 struct tl_type *t; 1067 struct ifnet *ifp; 1068 struct tl_softc *sc; 1069 int error = 0, rid; 1070 uint8_t eaddr[ETHER_ADDR_LEN]; 1071 1072 vid = pci_get_vendor(dev); 1073 did = pci_get_device(dev); 1074 sc = device_get_softc(dev); 1075 1076 t = tl_devs; 1077 while(t->tl_name != NULL) { 1078 if (vid == t->tl_vid && did == t->tl_did) 1079 break; 1080 t++; 1081 } 1082 1083 KKASSERT(t->tl_name != NULL); 1084 1085 pci_enable_busmaster(dev); 1086 1087 #ifdef TL_USEIOSPACE 1088 rid = TL_PCI_LOIO; 1089 sc->tl_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid, 1090 RF_ACTIVE); 1091 1092 /* 1093 * Some cards have the I/O and memory mapped address registers 1094 * reversed. Try both combinations before giving up. 1095 */ 1096 if (sc->tl_res == NULL) { 1097 rid = TL_PCI_LOMEM; 1098 sc->tl_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid, 1099 RF_ACTIVE); 1100 } 1101 #else 1102 rid = TL_PCI_LOMEM; 1103 sc->tl_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 1104 RF_ACTIVE); 1105 if (sc->tl_res == NULL) { 1106 rid = TL_PCI_LOIO; 1107 sc->tl_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 1108 RF_ACTIVE); 1109 } 1110 #endif 1111 1112 if (sc->tl_res == NULL) { 1113 device_printf(dev, "couldn't map ports/memory\n"); 1114 error = ENXIO; 1115 return(error); 1116 } 1117 1118 sc->tl_btag = rman_get_bustag(sc->tl_res); 1119 sc->tl_bhandle = rman_get_bushandle(sc->tl_res); 1120 1121 #ifdef notdef 1122 /* 1123 * The ThunderLAN manual suggests jacking the PCI latency 1124 * timer all the way up to its maximum value. I'm not sure 1125 * if this is really necessary, but what the manual wants, 1126 * the manual gets. 1127 */ 1128 command = pci_read_config(dev, TL_PCI_LATENCY_TIMER, 4); 1129 command |= 0x0000FF00; 1130 pci_write_config(dev, TL_PCI_LATENCY_TIMER, command, 4); 1131 #endif 1132 1133 /* Allocate interrupt */ 1134 rid = 0; 1135 sc->tl_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1136 RF_SHAREABLE | RF_ACTIVE); 1137 1138 if (sc->tl_irq == NULL) { 1139 device_printf(dev, "couldn't map interrupt\n"); 1140 error = ENXIO; 1141 goto fail; 1142 } 1143 1144 /* 1145 * Now allocate memory for the TX and RX lists. 1146 */ 1147 sc->tl_ldata = contigmalloc(sizeof(struct tl_list_data), M_DEVBUF, 1148 M_WAITOK, 0, 0xffffffff, PAGE_SIZE, 0); 1149 1150 if (sc->tl_ldata == NULL) { 1151 device_printf(dev, "no memory for list buffers!\n"); 1152 error = ENXIO; 1153 goto fail; 1154 } 1155 1156 bzero(sc->tl_ldata, sizeof(struct tl_list_data)); 1157 1158 sc->tl_dinfo = t; 1159 if (t->tl_vid == COMPAQ_VENDORID || t->tl_vid == TI_VENDORID) 1160 sc->tl_eeaddr = TL_EEPROM_EADDR; 1161 if (t->tl_vid == OLICOM_VENDORID) 1162 sc->tl_eeaddr = TL_EEPROM_EADDR_OC; 1163 1164 /* Reset the adapter. */ 1165 tl_softreset(sc, 1); 1166 tl_hardreset(dev); 1167 tl_softreset(sc, 1); 1168 1169 ifp = &sc->arpcom.ac_if; 1170 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1171 1172 /* 1173 * Get station address from the EEPROM. 1174 */ 1175 if (tl_read_eeprom(sc, eaddr, sc->tl_eeaddr, ETHER_ADDR_LEN)) { 1176 device_printf(dev, "failed to read station address\n"); 1177 error = ENXIO; 1178 goto fail; 1179 } 1180 1181 /* 1182 * XXX Olicom, in its desire to be different from the 1183 * rest of the world, has done strange things with the 1184 * encoding of the station address in the EEPROM. First 1185 * of all, they store the address at offset 0xF8 rather 1186 * than at 0x83 like the ThunderLAN manual suggests. 1187 * Second, they store the address in three 16-bit words in 1188 * network byte order, as opposed to storing it sequentially 1189 * like all the other ThunderLAN cards. In order to get 1190 * the station address in a form that matches what the Olicom 1191 * diagnostic utility specifies, we have to byte-swap each 1192 * word. To make things even more confusing, neither 00:00:28 1193 * nor 00:00:24 appear in the IEEE OUI database. 1194 */ 1195 if (sc->tl_dinfo->tl_vid == OLICOM_VENDORID) { 1196 for (i = 0; i < ETHER_ADDR_LEN; i += 2) { 1197 u_int16_t *p; 1198 p = (u_int16_t *)&eaddr[i]; 1199 *p = ntohs(*p); 1200 } 1201 } 1202 1203 ifp->if_softc = sc; 1204 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1205 ifp->if_ioctl = tl_ioctl; 1206 ifp->if_start = tl_start; 1207 ifp->if_watchdog = tl_watchdog; 1208 ifp->if_init = tl_init; 1209 ifp->if_mtu = ETHERMTU; 1210 ifq_set_maxlen(&ifp->if_snd, TL_TX_LIST_CNT - 1); 1211 ifq_set_ready(&ifp->if_snd); 1212 callout_init(&sc->tl_stat_timer); 1213 1214 /* Reset the adapter again. */ 1215 tl_softreset(sc, 1); 1216 tl_hardreset(dev); 1217 tl_softreset(sc, 1); 1218 1219 /* 1220 * Do MII setup. If no PHYs are found, then this is a 1221 * bitrate ThunderLAN chip that only supports 10baseT 1222 * and AUI/BNC. 1223 */ 1224 if (mii_phy_probe(dev, &sc->tl_miibus, 1225 tl_ifmedia_upd, tl_ifmedia_sts)) { 1226 struct ifmedia *ifm; 1227 sc->tl_bitrate = 1; 1228 ifmedia_init(&sc->ifmedia, 0, tl_ifmedia_upd, tl_ifmedia_sts); 1229 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL); 1230 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T|IFM_HDX, 0, NULL); 1231 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL); 1232 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_5, 0, NULL); 1233 ifmedia_set(&sc->ifmedia, IFM_ETHER|IFM_10_T); 1234 /* Reset again, this time setting bitrate mode. */ 1235 tl_softreset(sc, 1); 1236 ifm = &sc->ifmedia; 1237 ifm->ifm_media = ifm->ifm_cur->ifm_media; 1238 tl_ifmedia_upd(ifp); 1239 } 1240 1241 /* 1242 * Call MI attach routine. 1243 */ 1244 ether_ifattach(ifp, eaddr, NULL); 1245 1246 error = bus_setup_intr(dev, sc->tl_irq, INTR_NETSAFE, 1247 tl_intr, sc, &sc->tl_intrhand, 1248 ifp->if_serializer); 1249 1250 if (error) { 1251 ether_ifdetach(ifp); 1252 device_printf(dev, "couldn't set up irq\n"); 1253 goto fail; 1254 } 1255 1256 return(0); 1257 1258 fail: 1259 tl_detach(dev); 1260 return(error); 1261 } 1262 1263 static int 1264 tl_detach(device_t dev) 1265 { 1266 struct tl_softc *sc = device_get_softc(dev); 1267 struct ifnet *ifp = &sc->arpcom.ac_if; 1268 1269 if (device_is_attached(dev)) { 1270 lwkt_serialize_enter(ifp->if_serializer); 1271 tl_stop(sc); 1272 bus_teardown_intr(dev, sc->tl_irq, sc->tl_intrhand); 1273 lwkt_serialize_exit(ifp->if_serializer); 1274 1275 ether_ifdetach(ifp); 1276 } 1277 1278 if (sc->tl_miibus) 1279 device_delete_child(dev, sc->tl_miibus); 1280 bus_generic_detach(dev); 1281 1282 if (sc->tl_ldata) 1283 contigfree(sc->tl_ldata, sizeof(struct tl_list_data), M_DEVBUF); 1284 if (sc->tl_bitrate) 1285 ifmedia_removeall(&sc->ifmedia); 1286 if (sc->tl_irq) 1287 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->tl_irq); 1288 if (sc->tl_res) 1289 bus_release_resource(dev, TL_RES, TL_RID, sc->tl_res); 1290 1291 return(0); 1292 } 1293 1294 /* 1295 * Initialize the transmit lists. 1296 */ 1297 static int 1298 tl_list_tx_init(struct tl_softc *sc) 1299 { 1300 struct tl_chain_data *cd; 1301 struct tl_list_data *ld; 1302 int i; 1303 1304 cd = &sc->tl_cdata; 1305 ld = sc->tl_ldata; 1306 for (i = 0; i < TL_TX_LIST_CNT; i++) { 1307 cd->tl_tx_chain[i].tl_ptr = &ld->tl_tx_list[i]; 1308 if (i == (TL_TX_LIST_CNT - 1)) 1309 cd->tl_tx_chain[i].tl_next = NULL; 1310 else 1311 cd->tl_tx_chain[i].tl_next = &cd->tl_tx_chain[i + 1]; 1312 } 1313 1314 cd->tl_tx_free = &cd->tl_tx_chain[0]; 1315 cd->tl_tx_tail = cd->tl_tx_head = NULL; 1316 sc->tl_txeoc = 1; 1317 1318 return(0); 1319 } 1320 1321 /* 1322 * Initialize the RX lists and allocate mbufs for them. 1323 */ 1324 static int 1325 tl_list_rx_init(struct tl_softc *sc) 1326 { 1327 struct tl_chain_data *cd; 1328 struct tl_list_data *ld; 1329 int i; 1330 1331 cd = &sc->tl_cdata; 1332 ld = sc->tl_ldata; 1333 1334 for (i = 0; i < TL_RX_LIST_CNT; i++) { 1335 cd->tl_rx_chain[i].tl_ptr = 1336 (struct tl_list_onefrag *)&ld->tl_rx_list[i]; 1337 if (tl_newbuf(sc, &cd->tl_rx_chain[i]) == ENOBUFS) 1338 return(ENOBUFS); 1339 if (i == (TL_RX_LIST_CNT - 1)) { 1340 cd->tl_rx_chain[i].tl_next = NULL; 1341 ld->tl_rx_list[i].tlist_fptr = 0; 1342 } else { 1343 cd->tl_rx_chain[i].tl_next = &cd->tl_rx_chain[i + 1]; 1344 ld->tl_rx_list[i].tlist_fptr = 1345 vtophys(&ld->tl_rx_list[i + 1]); 1346 } 1347 } 1348 1349 cd->tl_rx_head = &cd->tl_rx_chain[0]; 1350 cd->tl_rx_tail = &cd->tl_rx_chain[TL_RX_LIST_CNT - 1]; 1351 1352 return(0); 1353 } 1354 1355 static int 1356 tl_newbuf(struct tl_softc *sc, struct tl_chain_onefrag *c) 1357 { 1358 struct mbuf *m_new; 1359 1360 m_new = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR); 1361 if (m_new == NULL) 1362 return (ENOBUFS); 1363 1364 c->tl_mbuf = m_new; 1365 c->tl_next = NULL; 1366 c->tl_ptr->tlist_frsize = MCLBYTES; 1367 c->tl_ptr->tlist_fptr = 0; 1368 c->tl_ptr->tl_frag.tlist_dadr = vtophys(mtod(m_new, caddr_t)); 1369 c->tl_ptr->tl_frag.tlist_dcnt = MCLBYTES; 1370 c->tl_ptr->tlist_cstat = TL_CSTAT_READY; 1371 1372 return(0); 1373 } 1374 1375 /* 1376 * Interrupt handler for RX 'end of frame' condition (EOF). This 1377 * tells us that a full ethernet frame has been captured and we need 1378 * to handle it. 1379 * 1380 * Reception is done using 'lists' which consist of a header and a 1381 * series of 10 data count/data address pairs that point to buffers. 1382 * Initially you're supposed to create a list, populate it with pointers 1383 * to buffers, then load the physical address of the list into the 1384 * ch_parm register. The adapter is then supposed to DMA the received 1385 * frame into the buffers for you. 1386 * 1387 * To make things as fast as possible, we have the chip DMA directly 1388 * into mbufs. This saves us from having to do a buffer copy: we can 1389 * just hand the mbufs directly to ether_input(). Once the frame has 1390 * been sent on its way, the 'list' structure is assigned a new buffer 1391 * and moved to the end of the RX chain. As long we we stay ahead of 1392 * the chip, it will always think it has an endless receive channel. 1393 * 1394 * If we happen to fall behind and the chip manages to fill up all of 1395 * the buffers, it will generate an end of channel interrupt and wait 1396 * for us to empty the chain and restart the receiver. 1397 */ 1398 static int 1399 tl_intvec_rxeof(void *xsc, u_int32_t type) 1400 { 1401 struct tl_softc *sc; 1402 int r = 0, total_len = 0; 1403 struct ether_header *eh; 1404 struct mbuf *m; 1405 struct ifnet *ifp; 1406 struct tl_chain_onefrag *cur_rx; 1407 1408 sc = xsc; 1409 ifp = &sc->arpcom.ac_if; 1410 1411 while(sc->tl_cdata.tl_rx_head != NULL) { 1412 cur_rx = sc->tl_cdata.tl_rx_head; 1413 if (!(cur_rx->tl_ptr->tlist_cstat & TL_CSTAT_FRAMECMP)) 1414 break; 1415 r++; 1416 sc->tl_cdata.tl_rx_head = cur_rx->tl_next; 1417 m = cur_rx->tl_mbuf; 1418 total_len = cur_rx->tl_ptr->tlist_frsize; 1419 1420 if (tl_newbuf(sc, cur_rx) == ENOBUFS) { 1421 ifp->if_ierrors++; 1422 cur_rx->tl_ptr->tlist_frsize = MCLBYTES; 1423 cur_rx->tl_ptr->tlist_cstat = TL_CSTAT_READY; 1424 cur_rx->tl_ptr->tl_frag.tlist_dcnt = MCLBYTES; 1425 continue; 1426 } 1427 1428 sc->tl_cdata.tl_rx_tail->tl_ptr->tlist_fptr = 1429 vtophys(cur_rx->tl_ptr); 1430 sc->tl_cdata.tl_rx_tail->tl_next = cur_rx; 1431 sc->tl_cdata.tl_rx_tail = cur_rx; 1432 1433 eh = mtod(m, struct ether_header *); 1434 m->m_pkthdr.rcvif = ifp; 1435 1436 /* 1437 * Note: when the ThunderLAN chip is in 'capture all 1438 * frames' mode, it will receive its own transmissions. 1439 * We drop don't need to process our own transmissions, 1440 * so we drop them here and continue. 1441 */ 1442 /*if (ifp->if_flags & IFF_PROMISC && */ 1443 if (!bcmp(eh->ether_shost, sc->arpcom.ac_enaddr, 1444 ETHER_ADDR_LEN)) { 1445 m_freem(m); 1446 continue; 1447 } 1448 1449 ifp->if_input(ifp, m); 1450 } 1451 1452 return(r); 1453 } 1454 1455 /* 1456 * The RX-EOC condition hits when the ch_parm address hasn't been 1457 * initialized or the adapter reached a list with a forward pointer 1458 * of 0 (which indicates the end of the chain). In our case, this means 1459 * the card has hit the end of the receive buffer chain and we need to 1460 * empty out the buffers and shift the pointer back to the beginning again. 1461 */ 1462 static int 1463 tl_intvec_rxeoc(void *xsc, u_int32_t type) 1464 { 1465 struct tl_softc *sc; 1466 int r; 1467 struct tl_chain_data *cd; 1468 1469 1470 sc = xsc; 1471 cd = &sc->tl_cdata; 1472 1473 /* Flush out the receive queue and ack RXEOF interrupts. */ 1474 r = tl_intvec_rxeof(xsc, type); 1475 CMD_PUT(sc, TL_CMD_ACK | r | (type & ~(0x00100000))); 1476 r = 1; 1477 cd->tl_rx_head = &cd->tl_rx_chain[0]; 1478 cd->tl_rx_tail = &cd->tl_rx_chain[TL_RX_LIST_CNT - 1]; 1479 CSR_WRITE_4(sc, TL_CH_PARM, vtophys(sc->tl_cdata.tl_rx_head->tl_ptr)); 1480 r |= (TL_CMD_GO|TL_CMD_RT); 1481 return(r); 1482 } 1483 1484 static int 1485 tl_intvec_txeof(void *xsc, u_int32_t type) 1486 { 1487 struct tl_softc *sc; 1488 int r = 0; 1489 struct tl_chain *cur_tx; 1490 1491 sc = xsc; 1492 1493 /* 1494 * Go through our tx list and free mbufs for those 1495 * frames that have been sent. 1496 */ 1497 while (sc->tl_cdata.tl_tx_head != NULL) { 1498 cur_tx = sc->tl_cdata.tl_tx_head; 1499 if (!(cur_tx->tl_ptr->tlist_cstat & TL_CSTAT_FRAMECMP)) 1500 break; 1501 sc->tl_cdata.tl_tx_head = cur_tx->tl_next; 1502 1503 r++; 1504 m_freem(cur_tx->tl_mbuf); 1505 cur_tx->tl_mbuf = NULL; 1506 1507 cur_tx->tl_next = sc->tl_cdata.tl_tx_free; 1508 sc->tl_cdata.tl_tx_free = cur_tx; 1509 if (!cur_tx->tl_ptr->tlist_fptr) 1510 break; 1511 } 1512 1513 return(r); 1514 } 1515 1516 /* 1517 * The transmit end of channel interrupt. The adapter triggers this 1518 * interrupt to tell us it hit the end of the current transmit list. 1519 * 1520 * A note about this: it's possible for a condition to arise where 1521 * tl_start() may try to send frames between TXEOF and TXEOC interrupts. 1522 * You have to avoid this since the chip expects things to go in a 1523 * particular order: transmit, acknowledge TXEOF, acknowledge TXEOC. 1524 * When the TXEOF handler is called, it will free all of the transmitted 1525 * frames and reset the tx_head pointer to NULL. However, a TXEOC 1526 * interrupt should be received and acknowledged before any more frames 1527 * are queued for transmission. If tl_statrt() is called after TXEOF 1528 * resets the tx_head pointer but _before_ the TXEOC interrupt arrives, 1529 * it could attempt to issue a transmit command prematurely. 1530 * 1531 * To guard against this, tl_start() will only issue transmit commands 1532 * if the tl_txeoc flag is set, and only the TXEOC interrupt handler 1533 * can set this flag once tl_start() has cleared it. 1534 */ 1535 static int 1536 tl_intvec_txeoc(void *xsc, u_int32_t type) 1537 { 1538 struct tl_softc *sc; 1539 struct ifnet *ifp; 1540 u_int32_t cmd; 1541 1542 sc = xsc; 1543 ifp = &sc->arpcom.ac_if; 1544 1545 /* Clear the timeout timer. */ 1546 ifp->if_timer = 0; 1547 1548 if (sc->tl_cdata.tl_tx_head == NULL) { 1549 ifp->if_flags &= ~IFF_OACTIVE; 1550 sc->tl_cdata.tl_tx_tail = NULL; 1551 sc->tl_txeoc = 1; 1552 } else { 1553 sc->tl_txeoc = 0; 1554 /* First we have to ack the EOC interrupt. */ 1555 CMD_PUT(sc, TL_CMD_ACK | 0x00000001 | type); 1556 /* Then load the address of the next TX list. */ 1557 CSR_WRITE_4(sc, TL_CH_PARM, 1558 vtophys(sc->tl_cdata.tl_tx_head->tl_ptr)); 1559 /* Restart TX channel. */ 1560 cmd = CSR_READ_4(sc, TL_HOSTCMD); 1561 cmd &= ~TL_CMD_RT; 1562 cmd |= TL_CMD_GO|TL_CMD_INTSON; 1563 CMD_PUT(sc, cmd); 1564 return(0); 1565 } 1566 1567 return(1); 1568 } 1569 1570 static int 1571 tl_intvec_adchk(void *xsc, u_int32_t type) 1572 { 1573 struct tl_softc *sc; 1574 1575 sc = xsc; 1576 1577 if (type) { 1578 if_printf(&sc->arpcom.ac_if, "adapter check: %x\n", 1579 (unsigned int)CSR_READ_4(sc, TL_CH_PARM)); 1580 } 1581 1582 tl_softreset(sc, 1); 1583 tl_stop(sc); 1584 tl_init(sc); 1585 CMD_SET(sc, TL_CMD_INTSON); 1586 1587 return(0); 1588 } 1589 1590 static int 1591 tl_intvec_netsts(void *xsc, u_int32_t type) 1592 { 1593 struct tl_softc *sc; 1594 u_int16_t netsts; 1595 1596 sc = xsc; 1597 1598 netsts = tl_dio_read16(sc, TL_NETSTS); 1599 tl_dio_write16(sc, TL_NETSTS, netsts); 1600 1601 if_printf(&sc->arpcom.ac_if, "network status: %x\n", netsts); 1602 1603 return(1); 1604 } 1605 1606 static void 1607 tl_intr(void *xsc) 1608 { 1609 struct tl_softc *sc; 1610 struct ifnet *ifp; 1611 int r = 0; 1612 u_int32_t type = 0; 1613 u_int16_t ints = 0; 1614 u_int8_t ivec = 0; 1615 1616 sc = xsc; 1617 1618 /* Disable interrupts */ 1619 ints = CSR_READ_2(sc, TL_HOST_INT); 1620 CSR_WRITE_2(sc, TL_HOST_INT, ints); 1621 type = (ints << 16) & 0xFFFF0000; 1622 ivec = (ints & TL_VEC_MASK) >> 5; 1623 ints = (ints & TL_INT_MASK) >> 2; 1624 1625 ifp = &sc->arpcom.ac_if; 1626 1627 switch(ints) { 1628 case (TL_INTR_INVALID): 1629 #ifdef DIAGNOSTIC 1630 if_printf(ifp, "got an invalid interrupt!\n"); 1631 #endif 1632 /* Re-enable interrupts but don't ack this one. */ 1633 CMD_PUT(sc, type); 1634 r = 0; 1635 break; 1636 case (TL_INTR_TXEOF): 1637 r = tl_intvec_txeof((void *)sc, type); 1638 break; 1639 case (TL_INTR_TXEOC): 1640 r = tl_intvec_txeoc((void *)sc, type); 1641 break; 1642 case (TL_INTR_STATOFLOW): 1643 tl_stats_update_serialized(sc); 1644 r = 1; 1645 break; 1646 case (TL_INTR_RXEOF): 1647 r = tl_intvec_rxeof((void *)sc, type); 1648 break; 1649 case (TL_INTR_DUMMY): 1650 if_printf(ifp, "got a dummy interrupt\n"); 1651 r = 1; 1652 break; 1653 case (TL_INTR_ADCHK): 1654 if (ivec) 1655 r = tl_intvec_adchk((void *)sc, type); 1656 else 1657 r = tl_intvec_netsts((void *)sc, type); 1658 break; 1659 case (TL_INTR_RXEOC): 1660 r = tl_intvec_rxeoc((void *)sc, type); 1661 break; 1662 default: 1663 if_printf(ifp, "bogus interrupt type\n"); 1664 break; 1665 } 1666 1667 /* Re-enable interrupts */ 1668 if (r) { 1669 CMD_PUT(sc, TL_CMD_ACK | r | type); 1670 } 1671 1672 if (!ifq_is_empty(&ifp->if_snd)) 1673 tl_start(ifp); 1674 1675 return; 1676 } 1677 1678 static 1679 void 1680 tl_stats_update(void *xsc) 1681 { 1682 struct tl_softc *sc = xsc; 1683 struct ifnet *ifp = &sc->arpcom.ac_if; 1684 1685 lwkt_serialize_enter(ifp->if_serializer); 1686 tl_stats_update_serialized(xsc); 1687 lwkt_serialize_exit(ifp->if_serializer); 1688 } 1689 1690 static 1691 void 1692 tl_stats_update_serialized(void *xsc) 1693 { 1694 struct tl_softc *sc; 1695 struct ifnet *ifp; 1696 struct tl_stats tl_stats; 1697 struct mii_data *mii; 1698 u_int32_t *p; 1699 1700 bzero((char *)&tl_stats, sizeof(struct tl_stats)); 1701 1702 sc = xsc; 1703 ifp = &sc->arpcom.ac_if; 1704 1705 p = (u_int32_t *)&tl_stats; 1706 1707 CSR_WRITE_2(sc, TL_DIO_ADDR, TL_TXGOODFRAMES|TL_DIO_ADDR_INC); 1708 *p++ = CSR_READ_4(sc, TL_DIO_DATA); 1709 *p++ = CSR_READ_4(sc, TL_DIO_DATA); 1710 *p++ = CSR_READ_4(sc, TL_DIO_DATA); 1711 *p++ = CSR_READ_4(sc, TL_DIO_DATA); 1712 *p++ = CSR_READ_4(sc, TL_DIO_DATA); 1713 1714 ifp->if_opackets += tl_tx_goodframes(tl_stats); 1715 ifp->if_collisions += tl_stats.tl_tx_single_collision + 1716 tl_stats.tl_tx_multi_collision; 1717 ifp->if_ipackets += tl_rx_goodframes(tl_stats); 1718 ifp->if_ierrors += tl_stats.tl_crc_errors + tl_stats.tl_code_errors + 1719 tl_rx_overrun(tl_stats); 1720 ifp->if_oerrors += tl_tx_underrun(tl_stats); 1721 1722 if (tl_tx_underrun(tl_stats)) { 1723 u_int8_t tx_thresh; 1724 tx_thresh = tl_dio_read8(sc, TL_ACOMMIT) & TL_AC_TXTHRESH; 1725 if (tx_thresh != TL_AC_TXTHRESH_WHOLEPKT) { 1726 tx_thresh >>= 4; 1727 tx_thresh++; 1728 if_printf(ifp, "tx underrun -- increasing " 1729 "tx threshold to %d bytes\n", 1730 (64 * (tx_thresh * 4))); 1731 tl_dio_clrbit(sc, TL_ACOMMIT, TL_AC_TXTHRESH); 1732 tl_dio_setbit(sc, TL_ACOMMIT, tx_thresh << 4); 1733 } 1734 } 1735 1736 callout_reset(&sc->tl_stat_timer, hz, tl_stats_update, sc); 1737 1738 if (!sc->tl_bitrate) { 1739 mii = device_get_softc(sc->tl_miibus); 1740 mii_tick(mii); 1741 } 1742 } 1743 1744 /* 1745 * Encapsulate an mbuf chain in a list by coupling the mbuf data 1746 * pointers to the fragment pointers. 1747 */ 1748 static int 1749 tl_encap(struct tl_softc *sc, struct tl_chain *c, struct mbuf *m_head) 1750 { 1751 int frag = 0; 1752 struct tl_frag *f = NULL; 1753 int total_len; 1754 struct mbuf *m; 1755 1756 /* 1757 * Start packing the mbufs in this chain into 1758 * the fragment pointers. Stop when we run out 1759 * of fragments or hit the end of the mbuf chain. 1760 */ 1761 m = m_head; 1762 total_len = 0; 1763 1764 for (m = m_head, frag = 0; m != NULL; m = m->m_next) { 1765 if (m->m_len != 0) { 1766 if (frag == TL_MAXFRAGS) 1767 break; 1768 total_len+= m->m_len; 1769 c->tl_ptr->tl_frag[frag].tlist_dadr = 1770 vtophys(mtod(m, vm_offset_t)); 1771 c->tl_ptr->tl_frag[frag].tlist_dcnt = m->m_len; 1772 frag++; 1773 } 1774 } 1775 1776 /* 1777 * Handle special cases. 1778 * Special case #1: we used up all 10 fragments, but 1779 * we have more mbufs left in the chain. Copy the 1780 * data into an mbuf cluster. Note that we don't 1781 * bother clearing the values in the other fragment 1782 * pointers/counters; it wouldn't gain us anything, 1783 * and would waste cycles. 1784 */ 1785 if (m != NULL) { 1786 struct mbuf *m_new; 1787 1788 m_new = m_getl(m_head->m_pkthdr.len, MB_DONTWAIT, MT_DATA, 1789 M_PKTHDR, NULL); 1790 if (m_new == NULL) { 1791 if_printf(&sc->arpcom.ac_if, "no memory for tx list\n"); 1792 return (1); 1793 } 1794 m_copydata(m_head, 0, m_head->m_pkthdr.len, 1795 mtod(m_new, caddr_t)); 1796 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 1797 m_freem(m_head); 1798 m_head = m_new; 1799 f = &c->tl_ptr->tl_frag[0]; 1800 f->tlist_dadr = vtophys(mtod(m_new, caddr_t)); 1801 f->tlist_dcnt = total_len = m_new->m_len; 1802 frag = 1; 1803 } 1804 1805 /* 1806 * Special case #2: the frame is smaller than the minimum 1807 * frame size. We have to pad it to make the chip happy. 1808 */ 1809 if (total_len < TL_MIN_FRAMELEN) { 1810 if (frag == TL_MAXFRAGS) { 1811 if_printf(&sc->arpcom.ac_if, "all frags filled but " 1812 "frame still to small!\n"); 1813 } 1814 f = &c->tl_ptr->tl_frag[frag]; 1815 f->tlist_dcnt = TL_MIN_FRAMELEN - total_len; 1816 f->tlist_dadr = vtophys(&sc->tl_ldata->tl_pad); 1817 total_len += f->tlist_dcnt; 1818 frag++; 1819 } 1820 1821 c->tl_mbuf = m_head; 1822 c->tl_ptr->tl_frag[frag - 1].tlist_dcnt |= TL_LAST_FRAG; 1823 c->tl_ptr->tlist_frsize = total_len; 1824 c->tl_ptr->tlist_cstat = TL_CSTAT_READY; 1825 c->tl_ptr->tlist_fptr = 0; 1826 1827 return(0); 1828 } 1829 1830 /* 1831 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1832 * to the mbuf data regions directly in the transmit lists. We also save a 1833 * copy of the pointers since the transmit list fragment pointers are 1834 * physical addresses. 1835 */ 1836 static void 1837 tl_start(struct ifnet *ifp) 1838 { 1839 struct tl_softc *sc; 1840 struct mbuf *m_head = NULL; 1841 u_int32_t cmd; 1842 struct tl_chain *prev = NULL, *cur_tx = NULL, *start_tx; 1843 1844 sc = ifp->if_softc; 1845 1846 /* 1847 * Check for an available queue slot. If there are none, 1848 * punt. 1849 */ 1850 if (sc->tl_cdata.tl_tx_free == NULL) { 1851 ifp->if_flags |= IFF_OACTIVE; 1852 return; 1853 } 1854 1855 start_tx = sc->tl_cdata.tl_tx_free; 1856 1857 while(sc->tl_cdata.tl_tx_free != NULL) { 1858 m_head = ifq_dequeue(&ifp->if_snd, NULL); 1859 if (m_head == NULL) 1860 break; 1861 1862 /* Pick a chain member off the free list. */ 1863 cur_tx = sc->tl_cdata.tl_tx_free; 1864 sc->tl_cdata.tl_tx_free = cur_tx->tl_next; 1865 1866 cur_tx->tl_next = NULL; 1867 1868 /* Pack the data into the list. */ 1869 tl_encap(sc, cur_tx, m_head); 1870 1871 /* Chain it together */ 1872 if (prev != NULL) { 1873 prev->tl_next = cur_tx; 1874 prev->tl_ptr->tlist_fptr = vtophys(cur_tx->tl_ptr); 1875 } 1876 prev = cur_tx; 1877 1878 BPF_MTAP(ifp, cur_tx->tl_mbuf); 1879 } 1880 1881 /* 1882 * If there are no packets queued, bail. 1883 */ 1884 if (cur_tx == NULL) 1885 return; 1886 1887 /* 1888 * That's all we can stands, we can't stands no more. 1889 * If there are no other transfers pending, then issue the 1890 * TX GO command to the adapter to start things moving. 1891 * Otherwise, just leave the data in the queue and let 1892 * the EOF/EOC interrupt handler send. 1893 */ 1894 if (sc->tl_cdata.tl_tx_head == NULL) { 1895 sc->tl_cdata.tl_tx_head = start_tx; 1896 sc->tl_cdata.tl_tx_tail = cur_tx; 1897 1898 if (sc->tl_txeoc) { 1899 sc->tl_txeoc = 0; 1900 CSR_WRITE_4(sc, TL_CH_PARM, vtophys(start_tx->tl_ptr)); 1901 cmd = CSR_READ_4(sc, TL_HOSTCMD); 1902 cmd &= ~TL_CMD_RT; 1903 cmd |= TL_CMD_GO|TL_CMD_INTSON; 1904 CMD_PUT(sc, cmd); 1905 } 1906 } else { 1907 sc->tl_cdata.tl_tx_tail->tl_next = start_tx; 1908 sc->tl_cdata.tl_tx_tail = cur_tx; 1909 } 1910 1911 /* 1912 * Set a timeout in case the chip goes out to lunch. 1913 */ 1914 ifp->if_timer = 5; 1915 1916 return; 1917 } 1918 1919 static void 1920 tl_init(void *xsc) 1921 { 1922 struct tl_softc *sc = xsc; 1923 struct ifnet *ifp = &sc->arpcom.ac_if; 1924 struct mii_data *mii; 1925 1926 /* 1927 * Cancel pending I/O. 1928 */ 1929 tl_stop(sc); 1930 1931 /* Initialize TX FIFO threshold */ 1932 tl_dio_clrbit(sc, TL_ACOMMIT, TL_AC_TXTHRESH); 1933 tl_dio_setbit(sc, TL_ACOMMIT, TL_AC_TXTHRESH_16LONG); 1934 1935 /* Set PCI burst size */ 1936 tl_dio_write8(sc, TL_BSIZEREG, TL_RXBURST_16LONG|TL_TXBURST_16LONG); 1937 1938 /* 1939 * Set 'capture all frames' bit for promiscuous mode. 1940 */ 1941 if (ifp->if_flags & IFF_PROMISC) 1942 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_CAF); 1943 else 1944 tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_CAF); 1945 1946 /* 1947 * Set capture broadcast bit to capture broadcast frames. 1948 */ 1949 if (ifp->if_flags & IFF_BROADCAST) 1950 tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_NOBRX); 1951 else 1952 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_NOBRX); 1953 1954 tl_dio_write16(sc, TL_MAXRX, MCLBYTES); 1955 1956 /* Init our MAC address */ 1957 tl_setfilt(sc, (caddr_t)&sc->arpcom.ac_enaddr, 0); 1958 1959 /* Init multicast filter, if needed. */ 1960 tl_setmulti(sc); 1961 1962 /* Init circular RX list. */ 1963 if (tl_list_rx_init(sc) == ENOBUFS) { 1964 if_printf(ifp, "initialization failed: no " 1965 "memory for rx buffers\n"); 1966 tl_stop(sc); 1967 return; 1968 } 1969 1970 /* Init TX pointers. */ 1971 tl_list_tx_init(sc); 1972 1973 /* Enable PCI interrupts. */ 1974 CMD_SET(sc, TL_CMD_INTSON); 1975 1976 /* Load the address of the rx list */ 1977 CMD_SET(sc, TL_CMD_RT); 1978 CSR_WRITE_4(sc, TL_CH_PARM, vtophys(&sc->tl_ldata->tl_rx_list[0])); 1979 1980 if (!sc->tl_bitrate) { 1981 if (sc->tl_miibus != NULL) { 1982 mii = device_get_softc(sc->tl_miibus); 1983 mii_mediachg(mii); 1984 } 1985 } 1986 1987 /* Send the RX go command */ 1988 CMD_SET(sc, TL_CMD_GO|TL_CMD_NES|TL_CMD_RT); 1989 1990 ifp->if_flags |= IFF_RUNNING; 1991 ifp->if_flags &= ~IFF_OACTIVE; 1992 1993 /* Start the stats update counter */ 1994 callout_reset(&sc->tl_stat_timer, hz, tl_stats_update, sc); 1995 } 1996 1997 /* 1998 * Set media options. 1999 */ 2000 static int 2001 tl_ifmedia_upd(struct ifnet *ifp) 2002 { 2003 struct tl_softc *sc; 2004 struct mii_data *mii = NULL; 2005 2006 sc = ifp->if_softc; 2007 2008 if (sc->tl_bitrate) 2009 tl_setmode(sc, sc->ifmedia.ifm_media); 2010 else { 2011 mii = device_get_softc(sc->tl_miibus); 2012 mii_mediachg(mii); 2013 } 2014 2015 return(0); 2016 } 2017 2018 /* 2019 * Report current media status. 2020 */ 2021 static void 2022 tl_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 2023 { 2024 struct tl_softc *sc; 2025 struct mii_data *mii; 2026 2027 sc = ifp->if_softc; 2028 2029 ifmr->ifm_active = IFM_ETHER; 2030 2031 if (sc->tl_bitrate) { 2032 if (tl_dio_read8(sc, TL_ACOMMIT) & TL_AC_MTXD1) 2033 ifmr->ifm_active = IFM_ETHER|IFM_10_5; 2034 else 2035 ifmr->ifm_active = IFM_ETHER|IFM_10_T; 2036 if (tl_dio_read8(sc, TL_ACOMMIT) & TL_AC_MTXD3) 2037 ifmr->ifm_active |= IFM_HDX; 2038 else 2039 ifmr->ifm_active |= IFM_FDX; 2040 return; 2041 } else { 2042 mii = device_get_softc(sc->tl_miibus); 2043 mii_pollstat(mii); 2044 ifmr->ifm_active = mii->mii_media_active; 2045 ifmr->ifm_status = mii->mii_media_status; 2046 } 2047 2048 return; 2049 } 2050 2051 static int 2052 tl_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr) 2053 { 2054 struct tl_softc *sc = ifp->if_softc; 2055 struct ifreq *ifr = (struct ifreq *) data; 2056 int error = 0; 2057 2058 switch(command) { 2059 case SIOCSIFFLAGS: 2060 if (ifp->if_flags & IFF_UP) { 2061 if (ifp->if_flags & IFF_RUNNING && 2062 ifp->if_flags & IFF_PROMISC && 2063 !(sc->tl_if_flags & IFF_PROMISC)) { 2064 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_CAF); 2065 tl_setmulti(sc); 2066 } else if (ifp->if_flags & IFF_RUNNING && 2067 !(ifp->if_flags & IFF_PROMISC) && 2068 sc->tl_if_flags & IFF_PROMISC) { 2069 tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_CAF); 2070 tl_setmulti(sc); 2071 } else 2072 tl_init(sc); 2073 } else { 2074 if (ifp->if_flags & IFF_RUNNING) { 2075 tl_stop(sc); 2076 } 2077 } 2078 sc->tl_if_flags = ifp->if_flags; 2079 error = 0; 2080 break; 2081 case SIOCADDMULTI: 2082 case SIOCDELMULTI: 2083 tl_setmulti(sc); 2084 error = 0; 2085 break; 2086 case SIOCSIFMEDIA: 2087 case SIOCGIFMEDIA: 2088 if (sc->tl_bitrate) 2089 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command); 2090 else { 2091 struct mii_data *mii; 2092 mii = device_get_softc(sc->tl_miibus); 2093 error = ifmedia_ioctl(ifp, ifr, 2094 &mii->mii_media, command); 2095 } 2096 break; 2097 default: 2098 error = ether_ioctl(ifp, command, data); 2099 break; 2100 } 2101 return(error); 2102 } 2103 2104 static void 2105 tl_watchdog(struct ifnet *ifp) 2106 { 2107 struct tl_softc *sc; 2108 2109 sc = ifp->if_softc; 2110 2111 if_printf(ifp, "device timeout\n"); 2112 2113 ifp->if_oerrors++; 2114 2115 tl_softreset(sc, 1); 2116 tl_init(sc); 2117 2118 return; 2119 } 2120 2121 /* 2122 * Stop the adapter and free any mbufs allocated to the 2123 * RX and TX lists. 2124 */ 2125 static void 2126 tl_stop(struct tl_softc *sc) 2127 { 2128 int i; 2129 struct ifnet *ifp; 2130 2131 ifp = &sc->arpcom.ac_if; 2132 2133 /* Stop the stats updater. */ 2134 callout_stop(&sc->tl_stat_timer); 2135 2136 /* Stop the transmitter */ 2137 CMD_CLR(sc, TL_CMD_RT); 2138 CMD_SET(sc, TL_CMD_STOP); 2139 CSR_WRITE_4(sc, TL_CH_PARM, 0); 2140 2141 /* Stop the receiver */ 2142 CMD_SET(sc, TL_CMD_RT); 2143 CMD_SET(sc, TL_CMD_STOP); 2144 CSR_WRITE_4(sc, TL_CH_PARM, 0); 2145 2146 /* 2147 * Disable host interrupts. 2148 */ 2149 CMD_SET(sc, TL_CMD_INTSOFF); 2150 2151 /* 2152 * Clear list pointer. 2153 */ 2154 CSR_WRITE_4(sc, TL_CH_PARM, 0); 2155 2156 /* 2157 * Free the RX lists. 2158 */ 2159 for (i = 0; i < TL_RX_LIST_CNT; i++) { 2160 if (sc->tl_cdata.tl_rx_chain[i].tl_mbuf != NULL) { 2161 m_freem(sc->tl_cdata.tl_rx_chain[i].tl_mbuf); 2162 sc->tl_cdata.tl_rx_chain[i].tl_mbuf = NULL; 2163 } 2164 } 2165 bzero((char *)&sc->tl_ldata->tl_rx_list, 2166 sizeof(sc->tl_ldata->tl_rx_list)); 2167 2168 /* 2169 * Free the TX list buffers. 2170 */ 2171 for (i = 0; i < TL_TX_LIST_CNT; i++) { 2172 if (sc->tl_cdata.tl_tx_chain[i].tl_mbuf != NULL) { 2173 m_freem(sc->tl_cdata.tl_tx_chain[i].tl_mbuf); 2174 sc->tl_cdata.tl_tx_chain[i].tl_mbuf = NULL; 2175 } 2176 } 2177 bzero((char *)&sc->tl_ldata->tl_tx_list, 2178 sizeof(sc->tl_ldata->tl_tx_list)); 2179 2180 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2181 2182 return; 2183 } 2184 2185 /* 2186 * Stop all chip I/O so that the kernel's probe routines don't 2187 * get confused by errant DMAs when rebooting. 2188 */ 2189 static void 2190 tl_shutdown(device_t dev) 2191 { 2192 struct tl_softc *sc; 2193 2194 sc = device_get_softc(dev); 2195 2196 tl_stop(sc); 2197 2198 return; 2199 } 2200