1*86d7f5d3SJohn Marino /* 2*86d7f5d3SJohn Marino * Copyright (c) 1997, 1998 3*86d7f5d3SJohn Marino * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4*86d7f5d3SJohn Marino * 5*86d7f5d3SJohn Marino * Redistribution and use in source and binary forms, with or without 6*86d7f5d3SJohn Marino * modification, are permitted provided that the following conditions 7*86d7f5d3SJohn Marino * are met: 8*86d7f5d3SJohn Marino * 1. Redistributions of source code must retain the above copyright 9*86d7f5d3SJohn Marino * notice, this list of conditions and the following disclaimer. 10*86d7f5d3SJohn Marino * 2. Redistributions in binary form must reproduce the above copyright 11*86d7f5d3SJohn Marino * notice, this list of conditions and the following disclaimer in the 12*86d7f5d3SJohn Marino * documentation and/or other materials provided with the distribution. 13*86d7f5d3SJohn Marino * 3. All advertising materials mentioning features or use of this software 14*86d7f5d3SJohn Marino * must display the following acknowledgement: 15*86d7f5d3SJohn Marino * This product includes software developed by Bill Paul. 16*86d7f5d3SJohn Marino * 4. Neither the name of the author nor the names of any co-contributors 17*86d7f5d3SJohn Marino * may be used to endorse or promote products derived from this software 18*86d7f5d3SJohn Marino * without specific prior written permission. 19*86d7f5d3SJohn Marino * 20*86d7f5d3SJohn Marino * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21*86d7f5d3SJohn Marino * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22*86d7f5d3SJohn Marino * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23*86d7f5d3SJohn Marino * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24*86d7f5d3SJohn Marino * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25*86d7f5d3SJohn Marino * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26*86d7f5d3SJohn Marino * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27*86d7f5d3SJohn Marino * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28*86d7f5d3SJohn Marino * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29*86d7f5d3SJohn Marino * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30*86d7f5d3SJohn Marino * THE POSSIBILITY OF SUCH DAMAGE. 31*86d7f5d3SJohn Marino * 32*86d7f5d3SJohn Marino * $FreeBSD: src/sys/pci/if_tlreg.h,v 1.15 1999/09/19 22:39:24 wpaul Exp $ 33*86d7f5d3SJohn Marino * $DragonFly: src/sys/dev/netif/tl/if_tlreg.h,v 1.5 2005/06/14 12:38:04 joerg Exp $ 34*86d7f5d3SJohn Marino */ 35*86d7f5d3SJohn Marino 36*86d7f5d3SJohn Marino 37*86d7f5d3SJohn Marino struct tl_type { 38*86d7f5d3SJohn Marino u_int16_t tl_vid; 39*86d7f5d3SJohn Marino u_int16_t tl_did; 40*86d7f5d3SJohn Marino char *tl_name; 41*86d7f5d3SJohn Marino }; 42*86d7f5d3SJohn Marino 43*86d7f5d3SJohn Marino /* 44*86d7f5d3SJohn Marino * ThunderLAN TX/RX list format. The TX and RX lists are pretty much 45*86d7f5d3SJohn Marino * identical: the list begins with a 32-bit forward pointer which points 46*86d7f5d3SJohn Marino * at the next list in the chain, followed by 16 bits for the total 47*86d7f5d3SJohn Marino * frame size, and a 16 bit status field. This is followed by a series 48*86d7f5d3SJohn Marino * of 10 32-bit data count/data address pairs that point to the fragments 49*86d7f5d3SJohn Marino * that make up the complete frame. 50*86d7f5d3SJohn Marino */ 51*86d7f5d3SJohn Marino 52*86d7f5d3SJohn Marino #define TL_MAXFRAGS 10 53*86d7f5d3SJohn Marino #define TL_RX_LIST_CNT 64 54*86d7f5d3SJohn Marino #define TL_TX_LIST_CNT 128 55*86d7f5d3SJohn Marino #define TL_MIN_FRAMELEN 64 56*86d7f5d3SJohn Marino 57*86d7f5d3SJohn Marino struct tl_frag { 58*86d7f5d3SJohn Marino u_int32_t tlist_dcnt; 59*86d7f5d3SJohn Marino u_int32_t tlist_dadr; 60*86d7f5d3SJohn Marino }; 61*86d7f5d3SJohn Marino 62*86d7f5d3SJohn Marino struct tl_list { 63*86d7f5d3SJohn Marino u_int32_t tlist_fptr; /* phys address of next list */ 64*86d7f5d3SJohn Marino u_int16_t tlist_cstat; /* status word */ 65*86d7f5d3SJohn Marino u_int16_t tlist_frsize; /* size of data in frame */ 66*86d7f5d3SJohn Marino struct tl_frag tl_frag[TL_MAXFRAGS]; 67*86d7f5d3SJohn Marino }; 68*86d7f5d3SJohn Marino 69*86d7f5d3SJohn Marino /* 70*86d7f5d3SJohn Marino * This is a special case of an RX list. By setting the One_Frag 71*86d7f5d3SJohn Marino * bit in the NETCONFIG register, the driver can force the ThunderLAN 72*86d7f5d3SJohn Marino * chip to use only one fragment when DMAing RX frames. 73*86d7f5d3SJohn Marino */ 74*86d7f5d3SJohn Marino 75*86d7f5d3SJohn Marino struct tl_list_onefrag { 76*86d7f5d3SJohn Marino u_int32_t tlist_fptr; 77*86d7f5d3SJohn Marino u_int16_t tlist_cstat; 78*86d7f5d3SJohn Marino u_int16_t tlist_frsize; 79*86d7f5d3SJohn Marino struct tl_frag tl_frag; 80*86d7f5d3SJohn Marino }; 81*86d7f5d3SJohn Marino 82*86d7f5d3SJohn Marino struct tl_list_data { 83*86d7f5d3SJohn Marino struct tl_list_onefrag tl_rx_list[TL_RX_LIST_CNT]; 84*86d7f5d3SJohn Marino struct tl_list tl_tx_list[TL_TX_LIST_CNT]; 85*86d7f5d3SJohn Marino unsigned char tl_pad[TL_MIN_FRAMELEN]; 86*86d7f5d3SJohn Marino }; 87*86d7f5d3SJohn Marino 88*86d7f5d3SJohn Marino struct tl_chain { 89*86d7f5d3SJohn Marino struct tl_list *tl_ptr; 90*86d7f5d3SJohn Marino struct mbuf *tl_mbuf; 91*86d7f5d3SJohn Marino struct tl_chain *tl_next; 92*86d7f5d3SJohn Marino }; 93*86d7f5d3SJohn Marino 94*86d7f5d3SJohn Marino struct tl_chain_onefrag { 95*86d7f5d3SJohn Marino struct tl_list_onefrag *tl_ptr; 96*86d7f5d3SJohn Marino struct mbuf *tl_mbuf; 97*86d7f5d3SJohn Marino struct tl_chain_onefrag *tl_next; 98*86d7f5d3SJohn Marino }; 99*86d7f5d3SJohn Marino 100*86d7f5d3SJohn Marino struct tl_chain_data { 101*86d7f5d3SJohn Marino struct tl_chain_onefrag tl_rx_chain[TL_RX_LIST_CNT]; 102*86d7f5d3SJohn Marino struct tl_chain tl_tx_chain[TL_TX_LIST_CNT]; 103*86d7f5d3SJohn Marino 104*86d7f5d3SJohn Marino struct tl_chain_onefrag *tl_rx_head; 105*86d7f5d3SJohn Marino struct tl_chain_onefrag *tl_rx_tail; 106*86d7f5d3SJohn Marino 107*86d7f5d3SJohn Marino struct tl_chain *tl_tx_head; 108*86d7f5d3SJohn Marino struct tl_chain *tl_tx_tail; 109*86d7f5d3SJohn Marino struct tl_chain *tl_tx_free; 110*86d7f5d3SJohn Marino }; 111*86d7f5d3SJohn Marino 112*86d7f5d3SJohn Marino struct tl_softc { 113*86d7f5d3SJohn Marino struct arpcom arpcom; /* interface info */ 114*86d7f5d3SJohn Marino struct ifmedia ifmedia; /* media info */ 115*86d7f5d3SJohn Marino bus_space_handle_t tl_bhandle; 116*86d7f5d3SJohn Marino bus_space_tag_t tl_btag; 117*86d7f5d3SJohn Marino void *tl_intrhand; 118*86d7f5d3SJohn Marino struct resource *tl_irq; 119*86d7f5d3SJohn Marino struct resource *tl_res; 120*86d7f5d3SJohn Marino device_t tl_miibus; 121*86d7f5d3SJohn Marino struct tl_type *tl_dinfo; /* ThunderLAN adapter info */ 122*86d7f5d3SJohn Marino u_int8_t tl_eeaddr; 123*86d7f5d3SJohn Marino struct tl_list_data *tl_ldata; /* TX/RX lists and mbufs */ 124*86d7f5d3SJohn Marino struct tl_chain_data tl_cdata; 125*86d7f5d3SJohn Marino u_int8_t tl_txeoc; 126*86d7f5d3SJohn Marino u_int8_t tl_bitrate; 127*86d7f5d3SJohn Marino int tl_if_flags; 128*86d7f5d3SJohn Marino struct callout tl_stat_timer; 129*86d7f5d3SJohn Marino }; 130*86d7f5d3SJohn Marino 131*86d7f5d3SJohn Marino /* 132*86d7f5d3SJohn Marino * Transmit interrupt threshold. 133*86d7f5d3SJohn Marino */ 134*86d7f5d3SJohn Marino #define TX_THR 0x00000004 135*86d7f5d3SJohn Marino 136*86d7f5d3SJohn Marino /* 137*86d7f5d3SJohn Marino * General constants that are fun to know. 138*86d7f5d3SJohn Marino * 139*86d7f5d3SJohn Marino * The ThunderLAN controller is made by Texas Instruments. The 140*86d7f5d3SJohn Marino * manual indicates that if the EEPROM checksum fails, the PCI 141*86d7f5d3SJohn Marino * vendor and device ID registers will be loaded with TI-specific 142*86d7f5d3SJohn Marino * values. 143*86d7f5d3SJohn Marino */ 144*86d7f5d3SJohn Marino #define TI_VENDORID 0x104C 145*86d7f5d3SJohn Marino #define TI_DEVICEID_THUNDERLAN 0x0500 146*86d7f5d3SJohn Marino 147*86d7f5d3SJohn Marino /* 148*86d7f5d3SJohn Marino * These are the PCI vendor and device IDs for Compaq ethernet 149*86d7f5d3SJohn Marino * adapters based on the ThunderLAN controller. 150*86d7f5d3SJohn Marino */ 151*86d7f5d3SJohn Marino #define COMPAQ_VENDORID 0x0E11 152*86d7f5d3SJohn Marino #define COMPAQ_DEVICEID_NETEL_10_100 0xAE32 153*86d7f5d3SJohn Marino #define COMPAQ_DEVICEID_NETEL_UNKNOWN 0xAE33 154*86d7f5d3SJohn Marino #define COMPAQ_DEVICEID_NETEL_10 0xAE34 155*86d7f5d3SJohn Marino #define COMPAQ_DEVICEID_NETFLEX_3P_INTEGRATED 0xAE35 156*86d7f5d3SJohn Marino #define COMPAQ_DEVICEID_NETEL_10_100_DUAL 0xAE40 157*86d7f5d3SJohn Marino #define COMPAQ_DEVICEID_NETEL_10_100_PROLIANT 0xAE43 158*86d7f5d3SJohn Marino #define COMPAQ_DEVICEID_NETEL_10_100_EMBEDDED 0xB011 159*86d7f5d3SJohn Marino #define COMPAQ_DEVICEID_NETEL_10_T2_UTP_COAX 0xB012 160*86d7f5d3SJohn Marino #define COMPAQ_DEVICEID_NETEL_10_100_TX_UTP 0xB030 161*86d7f5d3SJohn Marino #define COMPAQ_DEVICEID_NETFLEX_3P 0xF130 162*86d7f5d3SJohn Marino #define COMPAQ_DEVICEID_NETFLEX_3P_BNC 0xF150 163*86d7f5d3SJohn Marino 164*86d7f5d3SJohn Marino /* 165*86d7f5d3SJohn Marino * These are the PCI vendor and device IDs for Olicom 166*86d7f5d3SJohn Marino * adapters based on the ThunderLAN controller. 167*86d7f5d3SJohn Marino */ 168*86d7f5d3SJohn Marino #define OLICOM_VENDORID 0x108D 169*86d7f5d3SJohn Marino #define OLICOM_DEVICEID_OC2183 0x0013 170*86d7f5d3SJohn Marino #define OLICOM_DEVICEID_OC2325 0x0012 171*86d7f5d3SJohn Marino #define OLICOM_DEVICEID_OC2326 0x0014 172*86d7f5d3SJohn Marino 173*86d7f5d3SJohn Marino /* 174*86d7f5d3SJohn Marino * PCI low memory base and low I/O base 175*86d7f5d3SJohn Marino */ 176*86d7f5d3SJohn Marino #define TL_PCI_LOIO 0x10 177*86d7f5d3SJohn Marino #define TL_PCI_LOMEM 0x14 178*86d7f5d3SJohn Marino 179*86d7f5d3SJohn Marino /* 180*86d7f5d3SJohn Marino * PCI latency timer (it's actually 0x0D, but we want a value 181*86d7f5d3SJohn Marino * that's longword aligned). 182*86d7f5d3SJohn Marino */ 183*86d7f5d3SJohn Marino #define TL_PCI_LATENCY_TIMER 0x0C 184*86d7f5d3SJohn Marino 185*86d7f5d3SJohn Marino #define TL_DIO_ADDR_INC 0x8000 /* Increment addr on each read */ 186*86d7f5d3SJohn Marino #define TL_DIO_RAM_SEL 0x4000 /* RAM address select */ 187*86d7f5d3SJohn Marino #define TL_DIO_ADDR_MASK 0x3FFF /* address bits mask */ 188*86d7f5d3SJohn Marino 189*86d7f5d3SJohn Marino /* 190*86d7f5d3SJohn Marino * Interrupt types 191*86d7f5d3SJohn Marino */ 192*86d7f5d3SJohn Marino #define TL_INTR_INVALID 0x0 193*86d7f5d3SJohn Marino #define TL_INTR_TXEOF 0x1 194*86d7f5d3SJohn Marino #define TL_INTR_STATOFLOW 0x2 195*86d7f5d3SJohn Marino #define TL_INTR_RXEOF 0x3 196*86d7f5d3SJohn Marino #define TL_INTR_DUMMY 0x4 197*86d7f5d3SJohn Marino #define TL_INTR_TXEOC 0x5 198*86d7f5d3SJohn Marino #define TL_INTR_ADCHK 0x6 199*86d7f5d3SJohn Marino #define TL_INTR_RXEOC 0x7 200*86d7f5d3SJohn Marino 201*86d7f5d3SJohn Marino #define TL_INT_MASK 0x001C 202*86d7f5d3SJohn Marino #define TL_VEC_MASK 0x1FE0 203*86d7f5d3SJohn Marino /* 204*86d7f5d3SJohn Marino * Host command register bits 205*86d7f5d3SJohn Marino */ 206*86d7f5d3SJohn Marino #define TL_CMD_GO 0x80000000 207*86d7f5d3SJohn Marino #define TL_CMD_STOP 0x40000000 208*86d7f5d3SJohn Marino #define TL_CMD_ACK 0x20000000 209*86d7f5d3SJohn Marino #define TL_CMD_CHSEL7 0x10000000 210*86d7f5d3SJohn Marino #define TL_CMD_CHSEL6 0x08000000 211*86d7f5d3SJohn Marino #define TL_CMD_CHSEL5 0x04000000 212*86d7f5d3SJohn Marino #define TL_CMD_CHSEL4 0x02000000 213*86d7f5d3SJohn Marino #define TL_CMD_CHSEL3 0x01000000 214*86d7f5d3SJohn Marino #define TL_CMD_CHSEL2 0x00800000 215*86d7f5d3SJohn Marino #define TL_CMD_CHSEL1 0x00400000 216*86d7f5d3SJohn Marino #define TL_CMD_CHSEL0 0x00200000 217*86d7f5d3SJohn Marino #define TL_CMD_EOC 0x00100000 218*86d7f5d3SJohn Marino #define TL_CMD_RT 0x00080000 219*86d7f5d3SJohn Marino #define TL_CMD_NES 0x00040000 220*86d7f5d3SJohn Marino #define TL_CMD_ZERO0 0x00020000 221*86d7f5d3SJohn Marino #define TL_CMD_ZERO1 0x00010000 222*86d7f5d3SJohn Marino #define TL_CMD_ADRST 0x00008000 223*86d7f5d3SJohn Marino #define TL_CMD_LDTMR 0x00004000 224*86d7f5d3SJohn Marino #define TL_CMD_LDTHR 0x00002000 225*86d7f5d3SJohn Marino #define TL_CMD_REQINT 0x00001000 226*86d7f5d3SJohn Marino #define TL_CMD_INTSOFF 0x00000800 227*86d7f5d3SJohn Marino #define TL_CMD_INTSON 0x00000400 228*86d7f5d3SJohn Marino #define TL_CMD_RSVD0 0x00000200 229*86d7f5d3SJohn Marino #define TL_CMD_RSVD1 0x00000100 230*86d7f5d3SJohn Marino #define TL_CMD_ACK7 0x00000080 231*86d7f5d3SJohn Marino #define TL_CMD_ACK6 0x00000040 232*86d7f5d3SJohn Marino #define TL_CMD_ACK5 0x00000020 233*86d7f5d3SJohn Marino #define TL_CMD_ACK4 0x00000010 234*86d7f5d3SJohn Marino #define TL_CMD_ACK3 0x00000008 235*86d7f5d3SJohn Marino #define TL_CMD_ACK2 0x00000004 236*86d7f5d3SJohn Marino #define TL_CMD_ACK1 0x00000002 237*86d7f5d3SJohn Marino #define TL_CMD_ACK0 0x00000001 238*86d7f5d3SJohn Marino 239*86d7f5d3SJohn Marino #define TL_CMD_CHSEL_MASK 0x01FE0000 240*86d7f5d3SJohn Marino #define TL_CMD_ACK_MASK 0xFF 241*86d7f5d3SJohn Marino 242*86d7f5d3SJohn Marino /* 243*86d7f5d3SJohn Marino * EEPROM address where station address resides. 244*86d7f5d3SJohn Marino */ 245*86d7f5d3SJohn Marino #define TL_EEPROM_EADDR 0x83 246*86d7f5d3SJohn Marino #define TL_EEPROM_EADDR2 0x99 247*86d7f5d3SJohn Marino #define TL_EEPROM_EADDR3 0xAF 248*86d7f5d3SJohn Marino #define TL_EEPROM_EADDR_OC 0xF8 /* Olicom cards use a different 249*86d7f5d3SJohn Marino address than Compaqs. */ 250*86d7f5d3SJohn Marino /* 251*86d7f5d3SJohn Marino * ThunderLAN host command register offsets. 252*86d7f5d3SJohn Marino * (Can be accessed either by IO ports or memory map.) 253*86d7f5d3SJohn Marino */ 254*86d7f5d3SJohn Marino #define TL_HOSTCMD 0x00 255*86d7f5d3SJohn Marino #define TL_CH_PARM 0x04 256*86d7f5d3SJohn Marino #define TL_DIO_ADDR 0x08 257*86d7f5d3SJohn Marino #define TL_HOST_INT 0x0A 258*86d7f5d3SJohn Marino #define TL_DIO_DATA 0x0C 259*86d7f5d3SJohn Marino 260*86d7f5d3SJohn Marino /* 261*86d7f5d3SJohn Marino * ThunderLAN internal registers 262*86d7f5d3SJohn Marino */ 263*86d7f5d3SJohn Marino #define TL_NETCMD 0x00 264*86d7f5d3SJohn Marino #define TL_NETSIO 0x01 265*86d7f5d3SJohn Marino #define TL_NETSTS 0x02 266*86d7f5d3SJohn Marino #define TL_NETMASK 0x03 267*86d7f5d3SJohn Marino 268*86d7f5d3SJohn Marino #define TL_NETCONFIG 0x04 269*86d7f5d3SJohn Marino #define TL_MANTEST 0x06 270*86d7f5d3SJohn Marino 271*86d7f5d3SJohn Marino #define TL_VENID_LSB 0x08 272*86d7f5d3SJohn Marino #define TL_VENID_MSB 0x09 273*86d7f5d3SJohn Marino #define TL_DEVID_LSB 0x0A 274*86d7f5d3SJohn Marino #define TL_DEVID_MSB 0x0B 275*86d7f5d3SJohn Marino 276*86d7f5d3SJohn Marino #define TL_REVISION 0x0C 277*86d7f5d3SJohn Marino #define TL_SUBCLASS 0x0D 278*86d7f5d3SJohn Marino #define TL_MINLAT 0x0E 279*86d7f5d3SJohn Marino #define TL_MAXLAT 0x0F 280*86d7f5d3SJohn Marino 281*86d7f5d3SJohn Marino #define TL_AREG0_B5 0x10 282*86d7f5d3SJohn Marino #define TL_AREG0_B4 0x11 283*86d7f5d3SJohn Marino #define TL_AREG0_B3 0x12 284*86d7f5d3SJohn Marino #define TL_AREG0_B2 0x13 285*86d7f5d3SJohn Marino 286*86d7f5d3SJohn Marino #define TL_AREG0_B1 0x14 287*86d7f5d3SJohn Marino #define TL_AREG0_B0 0x15 288*86d7f5d3SJohn Marino #define TL_AREG1_B5 0x16 289*86d7f5d3SJohn Marino #define TL_AREG1_B4 0x17 290*86d7f5d3SJohn Marino 291*86d7f5d3SJohn Marino #define TL_AREG1_B3 0x18 292*86d7f5d3SJohn Marino #define TL_AREG1_B2 0x19 293*86d7f5d3SJohn Marino #define TL_AREG1_B1 0x1A 294*86d7f5d3SJohn Marino #define TL_AREG1_B0 0x1B 295*86d7f5d3SJohn Marino 296*86d7f5d3SJohn Marino #define TL_AREG2_B5 0x1C 297*86d7f5d3SJohn Marino #define TL_AREG2_B4 0x1D 298*86d7f5d3SJohn Marino #define TL_AREG2_B3 0x1E 299*86d7f5d3SJohn Marino #define TL_AREG2_B2 0x1F 300*86d7f5d3SJohn Marino 301*86d7f5d3SJohn Marino #define TL_AREG2_B1 0x20 302*86d7f5d3SJohn Marino #define TL_AREG2_B0 0x21 303*86d7f5d3SJohn Marino #define TL_AREG3_B5 0x22 304*86d7f5d3SJohn Marino #define TL_AREG3_B4 0x23 305*86d7f5d3SJohn Marino 306*86d7f5d3SJohn Marino #define TL_AREG3_B3 0x24 307*86d7f5d3SJohn Marino #define TL_AREG3_B2 0x25 308*86d7f5d3SJohn Marino #define TL_AREG3_B1 0x26 309*86d7f5d3SJohn Marino #define TL_AREG3_B0 0x27 310*86d7f5d3SJohn Marino 311*86d7f5d3SJohn Marino #define TL_HASH1 0x28 312*86d7f5d3SJohn Marino #define TL_HASH2 0x2C 313*86d7f5d3SJohn Marino #define TL_TXGOODFRAMES 0x30 314*86d7f5d3SJohn Marino #define TL_TXUNDERRUN 0x33 315*86d7f5d3SJohn Marino #define TL_RXGOODFRAMES 0x34 316*86d7f5d3SJohn Marino #define TL_RXOVERRUN 0x37 317*86d7f5d3SJohn Marino #define TL_DEFEREDTX 0x38 318*86d7f5d3SJohn Marino #define TL_CRCERROR 0x3A 319*86d7f5d3SJohn Marino #define TL_CODEERROR 0x3B 320*86d7f5d3SJohn Marino #define TL_MULTICOLTX 0x3C 321*86d7f5d3SJohn Marino #define TL_SINGLECOLTX 0x3E 322*86d7f5d3SJohn Marino #define TL_EXCESSIVECOL 0x40 323*86d7f5d3SJohn Marino #define TL_LATECOL 0x41 324*86d7f5d3SJohn Marino #define TL_CARRIERLOSS 0x42 325*86d7f5d3SJohn Marino #define TL_ACOMMIT 0x43 326*86d7f5d3SJohn Marino #define TL_LDREG 0x44 327*86d7f5d3SJohn Marino #define TL_BSIZEREG 0x45 328*86d7f5d3SJohn Marino #define TL_MAXRX 0x46 329*86d7f5d3SJohn Marino 330*86d7f5d3SJohn Marino /* 331*86d7f5d3SJohn Marino * ThunderLAN SIO register bits 332*86d7f5d3SJohn Marino */ 333*86d7f5d3SJohn Marino #define TL_SIO_MINTEN 0x80 334*86d7f5d3SJohn Marino #define TL_SIO_ECLOK 0x40 335*86d7f5d3SJohn Marino #define TL_SIO_ETXEN 0x20 336*86d7f5d3SJohn Marino #define TL_SIO_EDATA 0x10 337*86d7f5d3SJohn Marino #define TL_SIO_NMRST 0x08 338*86d7f5d3SJohn Marino #define TL_SIO_MCLK 0x04 339*86d7f5d3SJohn Marino #define TL_SIO_MTXEN 0x02 340*86d7f5d3SJohn Marino #define TL_SIO_MDATA 0x01 341*86d7f5d3SJohn Marino 342*86d7f5d3SJohn Marino /* 343*86d7f5d3SJohn Marino * Thunderlan NETCONFIG bits 344*86d7f5d3SJohn Marino */ 345*86d7f5d3SJohn Marino #define TL_CFG_RCLKTEST 0x8000 346*86d7f5d3SJohn Marino #define TL_CFG_TCLKTEST 0x4000 347*86d7f5d3SJohn Marino #define TL_CFG_BITRATE 0x2000 348*86d7f5d3SJohn Marino #define TL_CFG_RXCRC 0x1000 349*86d7f5d3SJohn Marino #define TL_CFG_PEF 0x0800 350*86d7f5d3SJohn Marino #define TL_CFG_ONEFRAG 0x0400 351*86d7f5d3SJohn Marino #define TL_CFG_ONECHAN 0x0200 352*86d7f5d3SJohn Marino #define TL_CFG_MTEST 0x0100 353*86d7f5d3SJohn Marino #define TL_CFG_PHYEN 0x0080 354*86d7f5d3SJohn Marino #define TL_CFG_MACSEL6 0x0040 355*86d7f5d3SJohn Marino #define TL_CFG_MACSEL5 0x0020 356*86d7f5d3SJohn Marino #define TL_CFG_MACSEL4 0x0010 357*86d7f5d3SJohn Marino #define TL_CFG_MACSEL3 0x0008 358*86d7f5d3SJohn Marino #define TL_CFG_MACSEL2 0x0004 359*86d7f5d3SJohn Marino #define TL_CFG_MACSEL1 0x0002 360*86d7f5d3SJohn Marino #define TL_CFG_MACSEL0 0x0001 361*86d7f5d3SJohn Marino 362*86d7f5d3SJohn Marino /* 363*86d7f5d3SJohn Marino * ThunderLAN NETSTS bits 364*86d7f5d3SJohn Marino */ 365*86d7f5d3SJohn Marino #define TL_STS_MIRQ 0x80 366*86d7f5d3SJohn Marino #define TL_STS_HBEAT 0x40 367*86d7f5d3SJohn Marino #define TL_STS_TXSTOP 0x20 368*86d7f5d3SJohn Marino #define TL_STS_RXSTOP 0x10 369*86d7f5d3SJohn Marino 370*86d7f5d3SJohn Marino /* 371*86d7f5d3SJohn Marino * ThunderLAN NETCMD bits 372*86d7f5d3SJohn Marino */ 373*86d7f5d3SJohn Marino #define TL_CMD_NRESET 0x80 374*86d7f5d3SJohn Marino #define TL_CMD_NWRAP 0x40 375*86d7f5d3SJohn Marino #define TL_CMD_CSF 0x20 376*86d7f5d3SJohn Marino #define TL_CMD_CAF 0x10 377*86d7f5d3SJohn Marino #define TL_CMD_NOBRX 0x08 378*86d7f5d3SJohn Marino #define TL_CMD_DUPLEX 0x04 379*86d7f5d3SJohn Marino #define TL_CMD_TRFRAM 0x02 380*86d7f5d3SJohn Marino #define TL_CMD_TXPACE 0x01 381*86d7f5d3SJohn Marino 382*86d7f5d3SJohn Marino /* 383*86d7f5d3SJohn Marino * ThunderLAN NETMASK bits 384*86d7f5d3SJohn Marino */ 385*86d7f5d3SJohn Marino #define TL_MASK_MASK7 0x80 386*86d7f5d3SJohn Marino #define TL_MASK_MASK6 0x40 387*86d7f5d3SJohn Marino #define TL_MASK_MASK5 0x20 388*86d7f5d3SJohn Marino #define TL_MASK_MASK4 0x10 389*86d7f5d3SJohn Marino 390*86d7f5d3SJohn Marino /* 391*86d7f5d3SJohn Marino * MII frame format 392*86d7f5d3SJohn Marino */ 393*86d7f5d3SJohn Marino #ifdef ANSI_DOESNT_ALLOW_BITFIELDS 394*86d7f5d3SJohn Marino struct tl_mii_frame { 395*86d7f5d3SJohn Marino u_int16_t mii_stdelim:2, 396*86d7f5d3SJohn Marino mii_opcode:2, 397*86d7f5d3SJohn Marino mii_phyaddr:5, 398*86d7f5d3SJohn Marino mii_regaddr:5, 399*86d7f5d3SJohn Marino mii_turnaround:2; 400*86d7f5d3SJohn Marino u_int16_t mii_data; 401*86d7f5d3SJohn Marino }; 402*86d7f5d3SJohn Marino #else 403*86d7f5d3SJohn Marino struct tl_mii_frame { 404*86d7f5d3SJohn Marino u_int8_t mii_stdelim; 405*86d7f5d3SJohn Marino u_int8_t mii_opcode; 406*86d7f5d3SJohn Marino u_int8_t mii_phyaddr; 407*86d7f5d3SJohn Marino u_int8_t mii_regaddr; 408*86d7f5d3SJohn Marino u_int8_t mii_turnaround; 409*86d7f5d3SJohn Marino u_int16_t mii_data; 410*86d7f5d3SJohn Marino }; 411*86d7f5d3SJohn Marino #endif 412*86d7f5d3SJohn Marino /* 413*86d7f5d3SJohn Marino * MII constants 414*86d7f5d3SJohn Marino */ 415*86d7f5d3SJohn Marino #define TL_MII_STARTDELIM 0x01 416*86d7f5d3SJohn Marino #define TL_MII_READOP 0x02 417*86d7f5d3SJohn Marino #define TL_MII_WRITEOP 0x01 418*86d7f5d3SJohn Marino #define TL_MII_TURNAROUND 0x02 419*86d7f5d3SJohn Marino 420*86d7f5d3SJohn Marino #define TL_LAST_FRAG 0x80000000 421*86d7f5d3SJohn Marino #define TL_CSTAT_UNUSED 0x8000 422*86d7f5d3SJohn Marino #define TL_CSTAT_FRAMECMP 0x4000 423*86d7f5d3SJohn Marino #define TL_CSTAT_READY 0x3000 424*86d7f5d3SJohn Marino #define TL_CSTAT_UNUSED13 0x2000 425*86d7f5d3SJohn Marino #define TL_CSTAT_UNUSED12 0x1000 426*86d7f5d3SJohn Marino #define TL_CSTAT_EOC 0x0800 427*86d7f5d3SJohn Marino #define TL_CSTAT_RXERROR 0x0400 428*86d7f5d3SJohn Marino #define TL_CSTAT_PASSCRC 0x0200 429*86d7f5d3SJohn Marino #define TL_CSTAT_DPRIO 0x0100 430*86d7f5d3SJohn Marino 431*86d7f5d3SJohn Marino #define TL_FRAME_MASK 0x00FFFFFF 432*86d7f5d3SJohn Marino #define tl_tx_goodframes(x) (x.tl_txstat & TL_FRAME_MASK) 433*86d7f5d3SJohn Marino #define tl_tx_underrun(x) ((x.tl_txstat & ~TL_FRAME_MASK) >> 24) 434*86d7f5d3SJohn Marino #define tl_rx_goodframes(x) (x.tl_rxstat & TL_FRAME_MASK) 435*86d7f5d3SJohn Marino #define tl_rx_overrun(x) ((x.tl_rxstat & ~TL_FRAME_MASK) >> 24) 436*86d7f5d3SJohn Marino 437*86d7f5d3SJohn Marino struct tl_stats { 438*86d7f5d3SJohn Marino u_int32_t tl_txstat; 439*86d7f5d3SJohn Marino u_int32_t tl_rxstat; 440*86d7f5d3SJohn Marino u_int16_t tl_deferred; 441*86d7f5d3SJohn Marino u_int8_t tl_crc_errors; 442*86d7f5d3SJohn Marino u_int8_t tl_code_errors; 443*86d7f5d3SJohn Marino u_int16_t tl_tx_multi_collision; 444*86d7f5d3SJohn Marino u_int16_t tl_tx_single_collision; 445*86d7f5d3SJohn Marino u_int8_t tl_excessive_collision; 446*86d7f5d3SJohn Marino u_int8_t tl_late_collision; 447*86d7f5d3SJohn Marino u_int8_t tl_carrier_loss; 448*86d7f5d3SJohn Marino u_int8_t acommit; 449*86d7f5d3SJohn Marino }; 450*86d7f5d3SJohn Marino 451*86d7f5d3SJohn Marino /* 452*86d7f5d3SJohn Marino * ACOMMIT register bits. These are used only when a bitrate 453*86d7f5d3SJohn Marino * PHY is selected ('bitrate' bit in netconfig register is set). 454*86d7f5d3SJohn Marino */ 455*86d7f5d3SJohn Marino #define TL_AC_MTXER 0x01 /* reserved */ 456*86d7f5d3SJohn Marino #define TL_AC_MTXD1 0x02 /* 0 == 10baseT 1 == AUI */ 457*86d7f5d3SJohn Marino #define TL_AC_MTXD2 0x04 /* loopback disable */ 458*86d7f5d3SJohn Marino #define TL_AC_MTXD3 0x08 /* full duplex disable */ 459*86d7f5d3SJohn Marino 460*86d7f5d3SJohn Marino #define TL_AC_TXTHRESH 0xF0 461*86d7f5d3SJohn Marino #define TL_AC_TXTHRESH_16LONG 0x00 462*86d7f5d3SJohn Marino #define TL_AC_TXTHRESH_32LONG 0x10 463*86d7f5d3SJohn Marino #define TL_AC_TXTHRESH_64LONG 0x20 464*86d7f5d3SJohn Marino #define TL_AC_TXTHRESH_128LONG 0x30 465*86d7f5d3SJohn Marino #define TL_AC_TXTHRESH_256LONG 0x40 466*86d7f5d3SJohn Marino #define TL_AC_TXTHRESH_WHOLEPKT 0x50 467*86d7f5d3SJohn Marino 468*86d7f5d3SJohn Marino /* 469*86d7f5d3SJohn Marino * PCI burst size register (TL_BSIZEREG). 470*86d7f5d3SJohn Marino */ 471*86d7f5d3SJohn Marino #define TL_RXBURST 0x0F 472*86d7f5d3SJohn Marino #define TL_TXBURST 0xF0 473*86d7f5d3SJohn Marino 474*86d7f5d3SJohn Marino #define TL_RXBURST_4LONG 0x00 475*86d7f5d3SJohn Marino #define TL_RXBURST_8LONG 0x01 476*86d7f5d3SJohn Marino #define TL_RXBURST_16LONG 0x02 477*86d7f5d3SJohn Marino #define TL_RXBURST_32LONG 0x03 478*86d7f5d3SJohn Marino #define TL_RXBURST_64LONG 0x04 479*86d7f5d3SJohn Marino #define TL_RXBURST_128LONG 0x05 480*86d7f5d3SJohn Marino 481*86d7f5d3SJohn Marino #define TL_TXBURST_4LONG 0x00 482*86d7f5d3SJohn Marino #define TL_TXBURST_8LONG 0x10 483*86d7f5d3SJohn Marino #define TL_TXBURST_16LONG 0x20 484*86d7f5d3SJohn Marino #define TL_TXBURST_32LONG 0x30 485*86d7f5d3SJohn Marino #define TL_TXBURST_64LONG 0x40 486*86d7f5d3SJohn Marino #define TL_TXBURST_128LONG 0x50 487*86d7f5d3SJohn Marino 488*86d7f5d3SJohn Marino /* 489*86d7f5d3SJohn Marino * register space access macros 490*86d7f5d3SJohn Marino */ 491*86d7f5d3SJohn Marino #define CSR_WRITE_4(sc, reg, val) \ 492*86d7f5d3SJohn Marino bus_space_write_4(sc->tl_btag, sc->tl_bhandle, reg, val) 493*86d7f5d3SJohn Marino #define CSR_WRITE_2(sc, reg, val) \ 494*86d7f5d3SJohn Marino bus_space_write_2(sc->tl_btag, sc->tl_bhandle, reg, val) 495*86d7f5d3SJohn Marino #define CSR_WRITE_1(sc, reg, val) \ 496*86d7f5d3SJohn Marino bus_space_write_1(sc->tl_btag, sc->tl_bhandle, reg, val) 497*86d7f5d3SJohn Marino 498*86d7f5d3SJohn Marino #define CSR_READ_4(sc, reg) \ 499*86d7f5d3SJohn Marino bus_space_read_4(sc->tl_btag, sc->tl_bhandle, reg) 500*86d7f5d3SJohn Marino #define CSR_READ_2(sc, reg) \ 501*86d7f5d3SJohn Marino bus_space_read_2(sc->tl_btag, sc->tl_bhandle, reg) 502*86d7f5d3SJohn Marino #define CSR_READ_1(sc, reg) \ 503*86d7f5d3SJohn Marino bus_space_read_1(sc->tl_btag, sc->tl_bhandle, reg) 504*86d7f5d3SJohn Marino 505*86d7f5d3SJohn Marino #define CMD_PUT(sc, x) CSR_WRITE_4(sc, TL_HOSTCMD, x) 506*86d7f5d3SJohn Marino #define CMD_SET(sc, x) \ 507*86d7f5d3SJohn Marino CSR_WRITE_4(sc, TL_HOSTCMD, CSR_READ_4(sc, TL_HOSTCMD) | (x)) 508*86d7f5d3SJohn Marino #define CMD_CLR(sc, x) \ 509*86d7f5d3SJohn Marino CSR_WRITE_4(sc, TL_HOSTCMD, CSR_READ_4(sc, TL_HOSTCMD) & ~(x)) 510*86d7f5d3SJohn Marino 511*86d7f5d3SJohn Marino /* 512*86d7f5d3SJohn Marino * ThunderLAN adapters typically have a serial EEPROM containing 513*86d7f5d3SJohn Marino * configuration information. The main reason we're interested in 514*86d7f5d3SJohn Marino * it is because it also contains the adapters's station address. 515*86d7f5d3SJohn Marino * 516*86d7f5d3SJohn Marino * Access to the EEPROM is a bit goofy since it is a serial device: 517*86d7f5d3SJohn Marino * you have to do reads and writes one bit at a time. The state of 518*86d7f5d3SJohn Marino * the DATA bit can only change while the CLOCK line is held low. 519*86d7f5d3SJohn Marino * Transactions work basically like this: 520*86d7f5d3SJohn Marino * 521*86d7f5d3SJohn Marino * 1) Send the EEPROM_START sequence to prepare the EEPROM for 522*86d7f5d3SJohn Marino * accepting commands. This pulls the clock high, sets 523*86d7f5d3SJohn Marino * the data bit to 0, enables transmission to the EEPROM, 524*86d7f5d3SJohn Marino * pulls the data bit up to 1, then pulls the clock low. 525*86d7f5d3SJohn Marino * The idea is to do a 0 to 1 transition of the data bit 526*86d7f5d3SJohn Marino * while the clock pin is held high. 527*86d7f5d3SJohn Marino * 528*86d7f5d3SJohn Marino * 2) To write a bit to the EEPROM, set the TXENABLE bit, then 529*86d7f5d3SJohn Marino * set the EDATA bit to send a 1 or clear it to send a 0. 530*86d7f5d3SJohn Marino * Finally, set and then clear ECLOK. Strobing the clock 531*86d7f5d3SJohn Marino * transmits the bit. After 8 bits have been written, the 532*86d7f5d3SJohn Marino * EEPROM should respond with an ACK, which should be read. 533*86d7f5d3SJohn Marino * 534*86d7f5d3SJohn Marino * 3) To read a bit from the EEPROM, clear the TXENABLE bit, 535*86d7f5d3SJohn Marino * then set ECLOK. The bit can then be read by reading EDATA. 536*86d7f5d3SJohn Marino * ECLOCK should then be cleared again. This can be repeated 537*86d7f5d3SJohn Marino * 8 times to read a whole byte, after which the 538*86d7f5d3SJohn Marino * 539*86d7f5d3SJohn Marino * 4) We need to send the address byte to the EEPROM. For this 540*86d7f5d3SJohn Marino * we have to send the write control byte to the EEPROM to 541*86d7f5d3SJohn Marino * tell it to accept data. The byte is 0xA0. The EEPROM should 542*86d7f5d3SJohn Marino * ack this. The address byte can be send after that. 543*86d7f5d3SJohn Marino * 544*86d7f5d3SJohn Marino * 5) Now we have to tell the EEPROM to send us data. For that we 545*86d7f5d3SJohn Marino * have to transmit the read control byte, which is 0xA1. This 546*86d7f5d3SJohn Marino * byte should also be acked. We can then read the data bits 547*86d7f5d3SJohn Marino * from the EEPROM. 548*86d7f5d3SJohn Marino * 549*86d7f5d3SJohn Marino * 6) When we're all finished, send the EEPROM_STOP sequence. 550*86d7f5d3SJohn Marino * 551*86d7f5d3SJohn Marino * Note that we use the ThunderLAN's NetSio register to access the 552*86d7f5d3SJohn Marino * EEPROM, however there is an alternate method. There is a PCI NVRAM 553*86d7f5d3SJohn Marino * register at PCI offset 0xB4 which can also be used with minor changes. 554*86d7f5d3SJohn Marino * The difference is that access to PCI registers via pci_conf_read() 555*86d7f5d3SJohn Marino * and pci_conf_write() is done using programmed I/O, which we want to 556*86d7f5d3SJohn Marino * avoid. 557*86d7f5d3SJohn Marino */ 558*86d7f5d3SJohn Marino 559*86d7f5d3SJohn Marino /* 560*86d7f5d3SJohn Marino * Note that EEPROM_START leaves transmission enabled. 561*86d7f5d3SJohn Marino */ 562*86d7f5d3SJohn Marino #define EEPROM_START \ 563*86d7f5d3SJohn Marino tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ECLOK); /* Pull clock pin high */\ 564*86d7f5d3SJohn Marino tl_dio_setbit(sc, TL_NETSIO, TL_SIO_EDATA); /* Set DATA bit to 1 */ \ 565*86d7f5d3SJohn Marino tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ETXEN); /* Enable xmit to write bit */\ 566*86d7f5d3SJohn Marino tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_EDATA); /* Pull DATA bit to 0 again */\ 567*86d7f5d3SJohn Marino tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ECLOK); /* Pull clock low again */ 568*86d7f5d3SJohn Marino 569*86d7f5d3SJohn Marino /* 570*86d7f5d3SJohn Marino * EEPROM_STOP ends access to the EEPROM and clears the ETXEN bit so 571*86d7f5d3SJohn Marino * that no further data can be written to the EEPROM I/O pin. 572*86d7f5d3SJohn Marino */ 573*86d7f5d3SJohn Marino #define EEPROM_STOP \ 574*86d7f5d3SJohn Marino tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ETXEN); /* Disable xmit */ \ 575*86d7f5d3SJohn Marino tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_EDATA); /* Pull DATA to 0 */ \ 576*86d7f5d3SJohn Marino tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ECLOK); /* Pull clock high */ \ 577*86d7f5d3SJohn Marino tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ETXEN); /* Enable xmit */ \ 578*86d7f5d3SJohn Marino tl_dio_setbit(sc, TL_NETSIO, TL_SIO_EDATA); /* Toggle DATA to 1 */ \ 579*86d7f5d3SJohn Marino tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ETXEN); /* Disable xmit. */ \ 580*86d7f5d3SJohn Marino tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ECLOK); /* Pull clock low again */ 581*86d7f5d3SJohn Marino 582*86d7f5d3SJohn Marino 583*86d7f5d3SJohn Marino /* 584*86d7f5d3SJohn Marino * Microchip Technology 24Cxx EEPROM control bytes 585*86d7f5d3SJohn Marino */ 586*86d7f5d3SJohn Marino #define EEPROM_CTL_READ 0xA1 /* 0101 0001 */ 587*86d7f5d3SJohn Marino #define EEPROM_CTL_WRITE 0xA0 /* 0101 0000 */ 588