1 /*- 2 * Copyright (c) 1997 Semen Ustimenko (semenu@FreeBSD.org) 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD: src/sys/dev/tx/if_tx.c,v 1.61.2.1 2002/10/29 01:43:49 semenu Exp $ 27 */ 28 29 /* 30 * EtherPower II 10/100 Fast Ethernet (SMC 9432 serie) 31 * 32 * These cards are based on SMC83c17x (EPIC) chip and one of the various 33 * PHYs (QS6612, AC101 and LXT970 were seen). The media support depends on 34 * card model. All cards support 10baseT/UTP and 100baseTX half- and full- 35 * duplex (SMB9432TX). SMC9432BTX also supports 10baseT/BNC. SMC9432FTX also 36 * supports fibre optics. 37 * 38 * Thanks are going to Steve Bauer and Jason Wright. 39 */ 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/sockio.h> 44 #include <sys/mbuf.h> 45 #include <sys/malloc.h> 46 #include <sys/kernel.h> 47 #include <sys/socket.h> 48 #include <sys/queue.h> 49 #include <sys/serialize.h> 50 #include <sys/bus.h> 51 #include <sys/rman.h> 52 #include <sys/thread2.h> 53 #include <sys/interrupt.h> 54 55 #include <net/if.h> 56 #include <net/ifq_var.h> 57 #include <net/if_arp.h> 58 #include <net/ethernet.h> 59 #include <net/if_dl.h> 60 #include <net/if_media.h> 61 62 #include <net/bpf.h> 63 64 #include <net/vlan/if_vlan_var.h> 65 66 #include <vm/vm.h> /* for vtophys */ 67 #include <vm/pmap.h> /* for vtophys */ 68 69 #include <bus/pci/pcireg.h> 70 #include <bus/pci/pcivar.h> 71 #include <bus/pci/pcidevs.h> 72 73 #include <dev/netif/mii_layer/mii.h> 74 #include <dev/netif/mii_layer/miivar.h> 75 #include <dev/netif/mii_layer/miidevs.h> 76 #include <dev/netif/mii_layer/lxtphyreg.h> 77 78 #include "miibus_if.h" 79 80 #include <dev/netif/tx/if_txreg.h> 81 #include <dev/netif/tx/if_txvar.h> 82 83 static int epic_ifioctl(struct ifnet *, u_long, caddr_t, struct ucred *); 84 static void epic_intr(void *); 85 static void epic_tx_underrun(epic_softc_t *); 86 static int epic_common_attach(epic_softc_t *); 87 static void epic_ifstart(struct ifnet *); 88 static void epic_ifwatchdog(struct ifnet *); 89 static void epic_stats_update(void *); 90 static int epic_init(epic_softc_t *); 91 static void epic_stop(epic_softc_t *); 92 static void epic_rx_done(epic_softc_t *); 93 static void epic_tx_done(epic_softc_t *); 94 static int epic_init_rings(epic_softc_t *); 95 static void epic_free_rings(epic_softc_t *); 96 static void epic_stop_activity(epic_softc_t *); 97 static int epic_queue_last_packet(epic_softc_t *); 98 static void epic_start_activity(epic_softc_t *); 99 static void epic_set_rx_mode(epic_softc_t *); 100 static void epic_set_tx_mode(epic_softc_t *); 101 static void epic_set_mc_table(epic_softc_t *); 102 static int epic_read_eeprom(epic_softc_t *,u_int16_t); 103 static void epic_output_eepromw(epic_softc_t *, u_int16_t); 104 static u_int16_t epic_input_eepromw(epic_softc_t *); 105 static u_int8_t epic_eeprom_clock(epic_softc_t *,u_int8_t); 106 static void epic_write_eepromreg(epic_softc_t *,u_int8_t); 107 static u_int8_t epic_read_eepromreg(epic_softc_t *); 108 109 static int epic_read_phy_reg(epic_softc_t *, int, int); 110 static void epic_write_phy_reg(epic_softc_t *, int, int, int); 111 112 static int epic_miibus_readreg(device_t, int, int); 113 static int epic_miibus_writereg(device_t, int, int, int); 114 static void epic_miibus_statchg(device_t); 115 static void epic_miibus_mediainit(device_t); 116 117 static int epic_ifmedia_upd(struct ifnet *); 118 static void epic_ifmedia_sts(struct ifnet *, struct ifmediareq *); 119 120 static int epic_probe(device_t); 121 static int epic_attach(device_t); 122 static void epic_shutdown(device_t); 123 static int epic_detach(device_t); 124 125 static device_method_t epic_methods[] = { 126 /* Device interface */ 127 DEVMETHOD(device_probe, epic_probe), 128 DEVMETHOD(device_attach, epic_attach), 129 DEVMETHOD(device_detach, epic_detach), 130 DEVMETHOD(device_shutdown, epic_shutdown), 131 132 /* MII interface */ 133 DEVMETHOD(miibus_readreg, epic_miibus_readreg), 134 DEVMETHOD(miibus_writereg, epic_miibus_writereg), 135 DEVMETHOD(miibus_statchg, epic_miibus_statchg), 136 DEVMETHOD(miibus_mediainit, epic_miibus_mediainit), 137 138 { 0, 0 } 139 }; 140 141 static driver_t epic_driver = { 142 "tx", 143 epic_methods, 144 sizeof(epic_softc_t) 145 }; 146 147 static devclass_t epic_devclass; 148 149 DECLARE_DUMMY_MODULE(if_tx); 150 MODULE_DEPEND(if_tx, miibus, 1, 1, 1); 151 DRIVER_MODULE(if_tx, pci, epic_driver, epic_devclass, NULL, NULL); 152 DRIVER_MODULE(miibus, tx, miibus_driver, miibus_devclass, NULL, NULL); 153 154 static struct epic_type epic_devs[] = { 155 { PCI_VENDOR_SMC, PCI_PRODUCT_SMC_83C170, 156 "SMC EtherPower II 10/100" }, 157 { 0, 0, NULL } 158 }; 159 160 static int 161 epic_probe(device_t dev) 162 { 163 struct epic_type *t; 164 uint16_t vid, did; 165 166 vid = pci_get_vendor(dev); 167 did = pci_get_device(dev); 168 for (t = epic_devs; t->name != NULL; ++t) { 169 if (vid == t->ven_id && did == t->dev_id) { 170 device_set_desc(dev, t->name); 171 return 0; 172 } 173 } 174 return ENXIO; 175 } 176 177 #if defined(EPIC_USEIOSPACE) 178 #define EPIC_RES SYS_RES_IOPORT 179 #define EPIC_RID PCIR_BAR(0) 180 #else 181 #define EPIC_RES SYS_RES_MEMORY 182 #define EPIC_RID PCIR_BAR(1) 183 #endif 184 185 /* 186 * Attach routine: map registers, allocate softc, rings and descriptors. 187 * Reset to known state. 188 */ 189 static int 190 epic_attach(device_t dev) 191 { 192 struct ifnet *ifp; 193 epic_softc_t *sc; 194 int error; 195 int i, rid, tmp; 196 197 sc = device_get_softc(dev); 198 199 /* Preinitialize softc structure */ 200 sc->dev = dev; 201 callout_init(&sc->tx_stat_timer); 202 203 /* Fill ifnet structure */ 204 ifp = &sc->sc_if; 205 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 206 ifp->if_softc = sc; 207 ifp->if_flags = IFF_BROADCAST|IFF_SIMPLEX|IFF_MULTICAST; 208 ifp->if_ioctl = epic_ifioctl; 209 ifp->if_start = epic_ifstart; 210 ifp->if_watchdog = epic_ifwatchdog; 211 ifp->if_init = (if_init_f_t*)epic_init; 212 ifp->if_timer = 0; 213 ifp->if_baudrate = 10000000; 214 ifq_set_maxlen(&ifp->if_snd, TX_RING_SIZE - 1); 215 ifq_set_ready(&ifp->if_snd); 216 217 pci_enable_busmaster(dev); 218 219 rid = EPIC_RID; 220 sc->res = bus_alloc_resource_any(dev, EPIC_RES, &rid, RF_ACTIVE); 221 222 if (sc->res == NULL) { 223 device_printf(dev, "couldn't map ports/memory\n"); 224 error = ENXIO; 225 goto fail; 226 } 227 228 sc->sc_st = rman_get_bustag(sc->res); 229 sc->sc_sh = rman_get_bushandle(sc->res); 230 231 /* Allocate interrupt */ 232 rid = 0; 233 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 234 RF_SHAREABLE | RF_ACTIVE); 235 236 if (sc->irq == NULL) { 237 device_printf(dev, "couldn't map interrupt\n"); 238 error = ENXIO; 239 goto fail; 240 } 241 242 /* Do OS independent part, including chip wakeup and reset */ 243 error = epic_common_attach(sc); 244 if (error) { 245 error = ENXIO; 246 goto fail; 247 } 248 249 /* Do ifmedia setup */ 250 if (mii_phy_probe(dev, &sc->miibus, 251 epic_ifmedia_upd, epic_ifmedia_sts)) { 252 device_printf(dev, "ERROR! MII without any PHY!?\n"); 253 error = ENXIO; 254 goto fail; 255 } 256 257 /* board type and ... */ 258 kprintf(" type "); 259 for(i=0x2c;i<0x32;i++) { 260 tmp = epic_read_eeprom(sc, i); 261 if (' ' == (u_int8_t)tmp) break; 262 kprintf("%c", (u_int8_t)tmp); 263 tmp >>= 8; 264 if (' ' == (u_int8_t)tmp) break; 265 kprintf("%c", (u_int8_t)tmp); 266 } 267 kprintf("\n"); 268 269 /* Attach to OS's managers */ 270 ether_ifattach(ifp, sc->sc_macaddr, NULL); 271 ifp->if_hdrlen = sizeof(struct ether_vlan_header); 272 273 error = bus_setup_intr(dev, sc->irq, INTR_MPSAFE, 274 epic_intr, sc, &sc->sc_ih, 275 ifp->if_serializer); 276 277 if (error) { 278 device_printf(dev, "couldn't set up irq\n"); 279 ether_ifdetach(ifp); 280 goto fail; 281 } 282 283 ifp->if_cpuid = ithread_cpuid(rman_get_start(sc->irq)); 284 KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus); 285 286 return(0); 287 288 fail: 289 epic_detach(dev); 290 return(error); 291 } 292 293 /* 294 * Detach driver and free resources 295 */ 296 static int 297 epic_detach(device_t dev) 298 { 299 epic_softc_t *sc = device_get_softc(dev); 300 struct ifnet *ifp = &sc->arpcom.ac_if; 301 302 if (device_is_attached(dev)) { 303 lwkt_serialize_enter(ifp->if_serializer); 304 epic_stop(sc); 305 bus_teardown_intr(dev, sc->irq, sc->sc_ih); 306 lwkt_serialize_exit(ifp->if_serializer); 307 308 ether_ifdetach(ifp); 309 } 310 311 if (sc->miibus) 312 device_delete_child(dev, sc->miibus); 313 bus_generic_detach(dev); 314 315 if (sc->irq) 316 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq); 317 if (sc->res) 318 bus_release_resource(dev, EPIC_RES, EPIC_RID, sc->res); 319 320 if (sc->tx_flist) 321 kfree(sc->tx_flist, M_DEVBUF); 322 if (sc->tx_desc) 323 kfree(sc->tx_desc, M_DEVBUF); 324 if (sc->rx_desc) 325 kfree(sc->rx_desc, M_DEVBUF); 326 327 return(0); 328 } 329 330 #undef EPIC_RES 331 #undef EPIC_RID 332 333 /* 334 * Stop all chip I/O so that the kernel's probe routines don't 335 * get confused by errant DMAs when rebooting. 336 */ 337 static void 338 epic_shutdown(device_t dev) 339 { 340 epic_softc_t *sc; 341 struct ifnet *ifp; 342 343 sc = device_get_softc(dev); 344 ifp = &sc->arpcom.ac_if; 345 lwkt_serialize_enter(ifp->if_serializer); 346 epic_stop(sc); 347 lwkt_serialize_exit(ifp->if_serializer); 348 } 349 350 /* 351 * This is if_ioctl handler. 352 */ 353 static int 354 epic_ifioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr) 355 { 356 epic_softc_t *sc = ifp->if_softc; 357 struct mii_data *mii; 358 struct ifreq *ifr = (struct ifreq *) data; 359 int error = 0; 360 361 switch (command) { 362 case SIOCSIFMTU: 363 if (ifp->if_mtu == ifr->ifr_mtu) 364 break; 365 366 /* XXX Though the datasheet doesn't imply any 367 * limitations on RX and TX sizes beside max 64Kb 368 * DMA transfer, seems we can't send more then 1600 369 * data bytes per ethernet packet. (Transmitter hangs 370 * up if more data is sent) 371 */ 372 if (ifr->ifr_mtu + ifp->if_hdrlen <= EPIC_MAX_MTU) { 373 ifp->if_mtu = ifr->ifr_mtu; 374 epic_stop(sc); 375 epic_init(sc); 376 } else 377 error = EINVAL; 378 break; 379 380 case SIOCSIFFLAGS: 381 /* 382 * If the interface is marked up and stopped, then start it. 383 * If it is marked down and running, then stop it. 384 */ 385 if (ifp->if_flags & IFF_UP) { 386 if ((ifp->if_flags & IFF_RUNNING) == 0) { 387 epic_init(sc); 388 break; 389 } 390 } else { 391 if (ifp->if_flags & IFF_RUNNING) { 392 epic_stop(sc); 393 break; 394 } 395 } 396 397 /* Handle IFF_PROMISC and IFF_ALLMULTI flags */ 398 epic_stop_activity(sc); 399 epic_set_mc_table(sc); 400 epic_set_rx_mode(sc); 401 epic_start_activity(sc); 402 break; 403 404 case SIOCADDMULTI: 405 case SIOCDELMULTI: 406 epic_set_mc_table(sc); 407 error = 0; 408 break; 409 410 case SIOCSIFMEDIA: 411 case SIOCGIFMEDIA: 412 mii = device_get_softc(sc->miibus); 413 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 414 break; 415 416 default: 417 error = ether_ioctl(ifp, command, data); 418 break; 419 } 420 return error; 421 } 422 423 /* 424 * OS-independed part of attach process. allocate memory for descriptors 425 * and frag lists, wake up chip, read MAC address and PHY identyfier. 426 * Return -1 on failure. 427 */ 428 static int 429 epic_common_attach(epic_softc_t *sc) 430 { 431 uint16_t sub_vid; 432 int i; 433 434 sc->tx_flist = kmalloc(sizeof(struct epic_frag_list)*TX_RING_SIZE, 435 M_DEVBUF, M_WAITOK | M_ZERO); 436 sc->tx_desc = kmalloc(sizeof(struct epic_tx_desc)*TX_RING_SIZE, 437 M_DEVBUF, M_WAITOK | M_ZERO); 438 sc->rx_desc = kmalloc(sizeof(struct epic_rx_desc)*RX_RING_SIZE, 439 M_DEVBUF, M_WAITOK | M_ZERO); 440 441 /* Bring the chip out of low-power mode. */ 442 CSR_WRITE_4(sc, GENCTL, GENCTL_SOFT_RESET); 443 DELAY(500); 444 445 /* Workaround for Application Note 7-15 */ 446 for (i=0; i<16; i++) CSR_WRITE_4(sc, TEST1, TEST1_CLOCK_TEST); 447 448 /* Read mac address from EEPROM */ 449 for (i = 0; i < ETHER_ADDR_LEN / sizeof(u_int16_t); i++) 450 ((u_int16_t *)sc->sc_macaddr)[i] = epic_read_eeprom(sc,i); 451 452 /* Set Non-Volatile Control Register from EEPROM */ 453 CSR_WRITE_4(sc, NVCTL, epic_read_eeprom(sc, EEPROM_NVCTL) & 0x1F); 454 455 /* Set defaults */ 456 sc->tx_threshold = TRANSMIT_THRESHOLD; 457 sc->txcon = TXCON_DEFAULT; 458 sc->miicfg = MIICFG_SMI_ENABLE; 459 sc->phyid = EPIC_UNKN_PHY; 460 sc->serinst = -1; 461 462 /* Fetch card id */ 463 sub_vid = pci_get_subvendor(sc->dev); 464 sc->cardid = pci_get_subdevice(sc->dev); 465 466 if (sub_vid != PCI_VENDOR_SMC) 467 device_printf(sc->dev, "unknown card vendor %04xh\n", sub_vid); 468 469 return 0; 470 } 471 472 /* 473 * This is if_start handler. It takes mbufs from if_snd queue 474 * and queue them for transmit, one by one, until TX ring become full 475 * or queue become empty. 476 */ 477 static void 478 epic_ifstart(struct ifnet *ifp) 479 { 480 epic_softc_t *sc = ifp->if_softc; 481 struct epic_tx_buffer *buf; 482 struct epic_tx_desc *desc; 483 struct epic_frag_list *flist; 484 struct mbuf *m0; 485 struct mbuf *m; 486 int i; 487 488 while (sc->pending_txs < TX_RING_SIZE) { 489 buf = sc->tx_buffer + sc->cur_tx; 490 desc = sc->tx_desc + sc->cur_tx; 491 flist = sc->tx_flist + sc->cur_tx; 492 493 /* Get next packet to send */ 494 m0 = ifq_dequeue(&ifp->if_snd, NULL); 495 496 /* If nothing to send, return */ 497 if (m0 == NULL) 498 return; 499 500 /* Fill fragments list */ 501 for (m = m0, i = 0; 502 (NULL != m) && (i < EPIC_MAX_FRAGS); 503 m = m->m_next, i++) { 504 flist->frag[i].fraglen = m->m_len; 505 flist->frag[i].fragaddr = vtophys(mtod(m, caddr_t)); 506 } 507 flist->numfrags = i; 508 509 /* If packet was more than EPIC_MAX_FRAGS parts, */ 510 /* recopy packet to new allocated mbuf cluster */ 511 if (NULL != m) { 512 m = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR); 513 if (NULL == m) { 514 m_freem(m0); 515 ifp->if_oerrors++; 516 continue; 517 } 518 519 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 520 flist->frag[0].fraglen = 521 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 522 m->m_pkthdr.rcvif = ifp; 523 524 flist->numfrags = 1; 525 flist->frag[0].fragaddr = vtophys(mtod(m, caddr_t)); 526 m_freem(m0); 527 m0 = m; 528 } 529 530 buf->mbuf = m0; 531 sc->pending_txs++; 532 sc->cur_tx = (sc->cur_tx + 1) & TX_RING_MASK; 533 desc->control = 0x01; 534 desc->txlength = 535 max(m0->m_pkthdr.len,ETHER_MIN_LEN-ETHER_CRC_LEN); 536 desc->status = 0x8000; 537 CSR_WRITE_4(sc, COMMAND, COMMAND_TXQUEUED); 538 539 /* Set watchdog timer */ 540 ifp->if_timer = 8; 541 542 BPF_MTAP(ifp, m0); 543 } 544 545 ifp->if_flags |= IFF_OACTIVE; 546 547 return; 548 549 } 550 551 /* 552 * Synopsis: Finish all received frames. 553 */ 554 static void 555 epic_rx_done(epic_softc_t *sc) 556 { 557 u_int16_t len; 558 struct ifnet *ifp = &sc->sc_if; 559 struct epic_rx_buffer *buf; 560 struct epic_rx_desc *desc; 561 struct mbuf *m; 562 563 while ((sc->rx_desc[sc->cur_rx].status & 0x8000) == 0) { 564 buf = sc->rx_buffer + sc->cur_rx; 565 desc = sc->rx_desc + sc->cur_rx; 566 567 /* Switch to next descriptor */ 568 sc->cur_rx = (sc->cur_rx+1) & RX_RING_MASK; 569 570 /* 571 * Check for RX errors. This should only happen if 572 * SAVE_ERRORED_PACKETS is set. RX errors generate 573 * RXE interrupt usually. 574 */ 575 if ((desc->status & 1) == 0) { 576 sc->sc_if.if_ierrors++; 577 desc->status = 0x8000; 578 continue; 579 } 580 581 /* Save packet length and mbuf contained packet */ 582 len = desc->rxlength - ETHER_CRC_LEN; 583 m = buf->mbuf; 584 585 /* Try to get mbuf cluster */ 586 buf->mbuf = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR); 587 if (NULL == buf->mbuf) { 588 buf->mbuf = m; 589 desc->status = 0x8000; 590 ifp->if_ierrors++; 591 continue; 592 } 593 594 /* Point to new mbuf, and give descriptor to chip */ 595 desc->bufaddr = vtophys(mtod(buf->mbuf, caddr_t)); 596 desc->status = 0x8000; 597 598 /* First mbuf in packet holds the ethernet and packet headers */ 599 m->m_pkthdr.rcvif = ifp; 600 m->m_pkthdr.len = m->m_len = len; 601 602 /* Give mbuf to OS */ 603 ifp->if_input(ifp, m); 604 605 /* Successfuly received frame */ 606 ifp->if_ipackets++; 607 } 608 609 return; 610 } 611 612 /* 613 * Synopsis: Do last phase of transmission. I.e. if desc is 614 * transmitted, decrease pending_txs counter, free mbuf contained 615 * packet, switch to next descriptor and repeat until no packets 616 * are pending or descriptor is not transmitted yet. 617 */ 618 static void 619 epic_tx_done(epic_softc_t *sc) 620 { 621 struct epic_tx_buffer *buf; 622 struct epic_tx_desc *desc; 623 u_int16_t status; 624 625 while (sc->pending_txs > 0) { 626 buf = sc->tx_buffer + sc->dirty_tx; 627 desc = sc->tx_desc + sc->dirty_tx; 628 status = desc->status; 629 630 /* If packet is not transmitted, thou followed */ 631 /* packets are not transmitted too */ 632 if (status & 0x8000) break; 633 634 /* Packet is transmitted. Switch to next and */ 635 /* free mbuf */ 636 sc->pending_txs--; 637 sc->dirty_tx = (sc->dirty_tx + 1) & TX_RING_MASK; 638 m_freem(buf->mbuf); 639 buf->mbuf = NULL; 640 641 /* Check for errors and collisions */ 642 if (status & 0x0001) sc->sc_if.if_opackets++; 643 else sc->sc_if.if_oerrors++; 644 sc->sc_if.if_collisions += (status >> 8) & 0x1F; 645 #if defined(EPIC_DIAG) 646 if ((status & 0x1001) == 0x1001) { 647 if_printf(&sc->sc_if, 648 "Tx ERROR: excessive coll. number\n"); 649 } 650 #endif 651 } 652 653 if (sc->pending_txs < TX_RING_SIZE) 654 sc->sc_if.if_flags &= ~IFF_OACTIVE; 655 } 656 657 /* 658 * Interrupt function 659 */ 660 static void 661 epic_intr(void *arg) 662 { 663 epic_softc_t * sc = (epic_softc_t *) arg; 664 int status, i = 4; 665 666 while (i-- && ((status = CSR_READ_4(sc, INTSTAT)) & INTSTAT_INT_ACTV)) { 667 CSR_WRITE_4(sc, INTSTAT, status); 668 669 if (status & (INTSTAT_RQE|INTSTAT_RCC|INTSTAT_OVW)) { 670 epic_rx_done(sc); 671 if (status & (INTSTAT_RQE|INTSTAT_OVW)) { 672 #if defined(EPIC_DIAG) 673 if (status & INTSTAT_OVW) 674 if_printf(&sc->sc_if, "RX buffer overflow\n"); 675 if (status & INTSTAT_RQE) 676 if_printf(&sc->sc_if, "RX FIFO overflow\n"); 677 #endif 678 if ((CSR_READ_4(sc, COMMAND) & COMMAND_RXQUEUED) == 0) 679 CSR_WRITE_4(sc, COMMAND, COMMAND_RXQUEUED); 680 sc->sc_if.if_ierrors++; 681 } 682 } 683 684 if (status & (INTSTAT_TXC|INTSTAT_TCC|INTSTAT_TQE)) { 685 epic_tx_done(sc); 686 if (!ifq_is_empty(&sc->sc_if.if_snd)) 687 if_devstart(&sc->sc_if); 688 } 689 690 /* Check for rare errors */ 691 if (status & (INTSTAT_FATAL|INTSTAT_PMA|INTSTAT_PTA| 692 INTSTAT_APE|INTSTAT_DPE|INTSTAT_TXU|INTSTAT_RXE)) { 693 if (status & (INTSTAT_FATAL|INTSTAT_PMA|INTSTAT_PTA| 694 INTSTAT_APE|INTSTAT_DPE)) { 695 if_printf(&sc->sc_if, "PCI fatal errors occurred: %s%s%s%s\n", 696 (status&INTSTAT_PMA)?"PMA ":"", 697 (status&INTSTAT_PTA)?"PTA ":"", 698 (status&INTSTAT_APE)?"APE ":"", 699 (status&INTSTAT_DPE)?"DPE":"" 700 ); 701 702 epic_stop(sc); 703 epic_init(sc); 704 705 break; 706 } 707 708 if (status & INTSTAT_RXE) { 709 #if defined(EPIC_DIAG) 710 if_printf(sc->sc_if, "CRC/Alignment error\n"); 711 #endif 712 sc->sc_if.if_ierrors++; 713 } 714 715 if (status & INTSTAT_TXU) { 716 epic_tx_underrun(sc); 717 sc->sc_if.if_oerrors++; 718 } 719 } 720 } 721 722 /* If no packets are pending, then no timeouts */ 723 if (sc->pending_txs == 0) sc->sc_if.if_timer = 0; 724 725 return; 726 } 727 728 /* 729 * Handle the TX underrun error: increase the TX threshold 730 * and restart the transmitter. 731 */ 732 static void 733 epic_tx_underrun(epic_softc_t *sc) 734 { 735 if (sc->tx_threshold > TRANSMIT_THRESHOLD_MAX) { 736 sc->txcon &= ~TXCON_EARLY_TRANSMIT_ENABLE; 737 #if defined(EPIC_DIAG) 738 if_printf(&sc->sc_if, "Tx UNDERRUN: early TX disabled\n"); 739 #endif 740 } else { 741 sc->tx_threshold += 0x40; 742 #if defined(EPIC_DIAG) 743 if_printf(&sc->sc_if, "Tx UNDERRUN: " 744 "TX threshold increased to %d\n", sc->tx_threshold); 745 #endif 746 } 747 748 /* We must set TXUGO to reset the stuck transmitter */ 749 CSR_WRITE_4(sc, COMMAND, COMMAND_TXUGO); 750 751 /* Update the TX threshold */ 752 epic_stop_activity(sc); 753 epic_set_tx_mode(sc); 754 epic_start_activity(sc); 755 756 return; 757 } 758 759 /* 760 * Synopsis: This one is called if packets wasn't transmitted 761 * during timeout. Try to deallocate transmitted packets, and 762 * if success continue to work. 763 */ 764 static void 765 epic_ifwatchdog(struct ifnet *ifp) 766 { 767 epic_softc_t *sc = ifp->if_softc; 768 769 if_printf(ifp, "device timeout %d packets\n", sc->pending_txs); 770 771 /* Try to finish queued packets */ 772 epic_tx_done(sc); 773 774 /* If not successful */ 775 if (sc->pending_txs > 0) { 776 777 ifp->if_oerrors+=sc->pending_txs; 778 779 /* Reinitialize board */ 780 if_printf(ifp, "reinitialization\n"); 781 epic_stop(sc); 782 epic_init(sc); 783 784 } else 785 if_printf(ifp, "seems we can continue normally\n"); 786 787 /* Start output */ 788 if (!ifq_is_empty(&ifp->if_snd)) 789 if_devstart(ifp); 790 } 791 792 /* 793 * Despite the name of this function, it doesn't update statistics, it only 794 * helps in autonegotiation process. 795 */ 796 static void 797 epic_stats_update(void *xsc) 798 { 799 epic_softc_t *sc = xsc; 800 struct ifnet *ifp = &sc->sc_if; 801 struct mii_data * mii; 802 803 lwkt_serialize_enter(ifp->if_serializer); 804 805 mii = device_get_softc(sc->miibus); 806 mii_tick(mii); 807 808 callout_reset(&sc->tx_stat_timer, hz, epic_stats_update, sc); 809 810 lwkt_serialize_exit(ifp->if_serializer); 811 } 812 813 /* 814 * Set media options. 815 */ 816 static int 817 epic_ifmedia_upd(struct ifnet *ifp) 818 { 819 epic_softc_t *sc; 820 struct mii_data *mii; 821 struct ifmedia *ifm; 822 struct mii_softc *miisc; 823 int cfg, media; 824 825 sc = ifp->if_softc; 826 mii = device_get_softc(sc->miibus); 827 ifm = &mii->mii_media; 828 media = ifm->ifm_cur->ifm_media; 829 830 /* Do not do anything if interface is not up */ 831 if ((ifp->if_flags & IFF_UP) == 0) 832 return (0); 833 834 /* 835 * Lookup current selected PHY 836 */ 837 if (IFM_INST(media) == sc->serinst) { 838 sc->phyid = EPIC_SERIAL; 839 sc->physc = NULL; 840 } else { 841 /* If we're not selecting serial interface, select MII mode */ 842 sc->miicfg &= ~MIICFG_SERIAL_ENABLE; 843 CSR_WRITE_4(sc, MIICFG, sc->miicfg); 844 845 /* Default to unknown PHY */ 846 sc->phyid = EPIC_UNKN_PHY; 847 848 /* Lookup selected PHY */ 849 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 850 miisc = LIST_NEXT(miisc, mii_list)) { 851 if (IFM_INST(media) == miisc->mii_inst) { 852 sc->physc = miisc; 853 break; 854 } 855 } 856 857 /* Identify selected PHY */ 858 if (sc->physc) { 859 int id1, id2, model, oui; 860 861 id1 = PHY_READ(sc->physc, MII_PHYIDR1); 862 id2 = PHY_READ(sc->physc, MII_PHYIDR2); 863 864 oui = MII_OUI(id1, id2); 865 model = MII_MODEL(id2); 866 switch (oui) { 867 case MII_OUI_QUALSEMI: 868 if (model == MII_MODEL_QUALSEMI_QS6612) 869 sc->phyid = EPIC_QS6612_PHY; 870 break; 871 case MII_OUI_xxALTIMA: 872 if (model == MII_MODEL_xxALTIMA_AC101) 873 sc->phyid = EPIC_AC101_PHY; 874 break; 875 case MII_OUI_xxLEVEL1: 876 if (model == MII_MODEL_xxLEVEL1_LXT970) 877 sc->phyid = EPIC_LXT970_PHY; 878 break; 879 } 880 } 881 } 882 883 /* 884 * Do PHY specific card setup 885 */ 886 887 /* Call this, to isolate all not selected PHYs and 888 * set up selected 889 */ 890 mii_mediachg(mii); 891 892 /* Do our own setup */ 893 switch (sc->phyid) { 894 case EPIC_QS6612_PHY: 895 break; 896 case EPIC_AC101_PHY: 897 /* We have to powerup fiber tranceivers */ 898 if (IFM_SUBTYPE(media) == IFM_100_FX) 899 sc->miicfg |= MIICFG_694_ENABLE; 900 else 901 sc->miicfg &= ~MIICFG_694_ENABLE; 902 CSR_WRITE_4(sc, MIICFG, sc->miicfg); 903 904 break; 905 case EPIC_LXT970_PHY: 906 /* We have to powerup fiber tranceivers */ 907 cfg = PHY_READ(sc->physc, MII_LXTPHY_CONFIG); 908 if (IFM_SUBTYPE(media) == IFM_100_FX) 909 cfg |= CONFIG_LEDC1 | CONFIG_LEDC0; 910 else 911 cfg &= ~(CONFIG_LEDC1 | CONFIG_LEDC0); 912 PHY_WRITE(sc->physc, MII_LXTPHY_CONFIG, cfg); 913 914 break; 915 case EPIC_SERIAL: 916 /* Select serial PHY, (10base2/BNC usually) */ 917 sc->miicfg |= MIICFG_694_ENABLE | MIICFG_SERIAL_ENABLE; 918 CSR_WRITE_4(sc, MIICFG, sc->miicfg); 919 920 /* There is no driver to fill this */ 921 mii->mii_media_active = media; 922 mii->mii_media_status = 0; 923 924 /* We need to call this manualy as i wasn't called 925 * in mii_mediachg() 926 */ 927 epic_miibus_statchg(sc->dev); 928 929 break; 930 default: 931 if_printf(ifp, "ERROR! Unknown PHY selected\n"); 932 return (EINVAL); 933 } 934 935 return(0); 936 } 937 938 /* 939 * Report current media status. 940 */ 941 static void 942 epic_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 943 { 944 epic_softc_t *sc; 945 struct mii_data *mii; 946 struct ifmedia *ifm; 947 948 sc = ifp->if_softc; 949 mii = device_get_softc(sc->miibus); 950 ifm = &mii->mii_media; 951 952 /* Nothing should be selected if interface is down */ 953 if ((ifp->if_flags & IFF_UP) == 0) { 954 ifmr->ifm_active = IFM_NONE; 955 ifmr->ifm_status = 0; 956 957 return; 958 } 959 960 /* Call underlying pollstat, if not serial PHY */ 961 if (sc->phyid != EPIC_SERIAL) 962 mii_pollstat(mii); 963 964 /* Simply copy media info */ 965 ifmr->ifm_active = mii->mii_media_active; 966 ifmr->ifm_status = mii->mii_media_status; 967 968 return; 969 } 970 971 /* 972 * Callback routine, called on media change. 973 */ 974 static void 975 epic_miibus_statchg(device_t dev) 976 { 977 epic_softc_t *sc; 978 struct mii_data *mii; 979 int media; 980 981 sc = device_get_softc(dev); 982 mii = device_get_softc(sc->miibus); 983 media = mii->mii_media_active; 984 985 sc->txcon &= ~(TXCON_LOOPBACK_MODE | TXCON_FULL_DUPLEX); 986 987 /* If we are in full-duplex mode or loopback operation, 988 * we need to decouple receiver and transmitter. 989 */ 990 if (IFM_OPTIONS(media) & (IFM_FDX | IFM_LOOP)) 991 sc->txcon |= TXCON_FULL_DUPLEX; 992 993 /* On some cards we need manualy set fullduplex led */ 994 if (sc->cardid == SMC9432FTX || 995 sc->cardid == SMC9432FTX_SC) { 996 if (IFM_OPTIONS(media) & IFM_FDX) 997 sc->miicfg |= MIICFG_694_ENABLE; 998 else 999 sc->miicfg &= ~MIICFG_694_ENABLE; 1000 1001 CSR_WRITE_4(sc, MIICFG, sc->miicfg); 1002 } 1003 1004 /* Update baudrate */ 1005 if (IFM_SUBTYPE(media) == IFM_100_TX || 1006 IFM_SUBTYPE(media) == IFM_100_FX) 1007 sc->sc_if.if_baudrate = 100000000; 1008 else 1009 sc->sc_if.if_baudrate = 10000000; 1010 1011 epic_stop_activity(sc); 1012 epic_set_tx_mode(sc); 1013 epic_start_activity(sc); 1014 1015 return; 1016 } 1017 1018 static void 1019 epic_miibus_mediainit(device_t dev) 1020 { 1021 epic_softc_t *sc; 1022 struct mii_data *mii; 1023 struct ifmedia *ifm; 1024 int media; 1025 1026 sc = device_get_softc(dev); 1027 mii = device_get_softc(sc->miibus); 1028 ifm = &mii->mii_media; 1029 1030 /* Add Serial Media Interface if present, this applies to 1031 * SMC9432BTX serie 1032 */ 1033 if (CSR_READ_4(sc, MIICFG) & MIICFG_PHY_PRESENT) { 1034 /* Store its instance */ 1035 sc->serinst = mii->mii_instance++; 1036 1037 /* Add as 10base2/BNC media */ 1038 media = IFM_MAKEWORD(IFM_ETHER, IFM_10_2, 0, sc->serinst); 1039 ifmedia_add(ifm, media, 0, NULL); 1040 1041 /* Report to user */ 1042 if_printf(&sc->sc_if, "serial PHY detected (10Base2/BNC)\n"); 1043 } 1044 1045 return; 1046 } 1047 1048 /* 1049 * Reset chip, allocate rings, and update media. 1050 */ 1051 static int 1052 epic_init(epic_softc_t *sc) 1053 { 1054 struct ifnet *ifp = &sc->sc_if; 1055 int i; 1056 1057 /* If interface is already running, then we need not do anything */ 1058 if (ifp->if_flags & IFF_RUNNING) { 1059 return 0; 1060 } 1061 1062 /* Soft reset the chip (we have to power up card before) */ 1063 CSR_WRITE_4(sc, GENCTL, 0); 1064 CSR_WRITE_4(sc, GENCTL, GENCTL_SOFT_RESET); 1065 1066 /* 1067 * Reset takes 15 pci ticks which depends on PCI bus speed. 1068 * Assuming it >= 33000000 hz, we have wait at least 495e-6 sec. 1069 */ 1070 DELAY(500); 1071 1072 /* Wake up */ 1073 CSR_WRITE_4(sc, GENCTL, 0); 1074 1075 /* Workaround for Application Note 7-15 */ 1076 for (i=0; i<16; i++) CSR_WRITE_4(sc, TEST1, TEST1_CLOCK_TEST); 1077 1078 /* Initialize rings */ 1079 if (epic_init_rings(sc)) { 1080 if_printf(ifp, "failed to init rings\n"); 1081 return -1; 1082 } 1083 1084 /* Give rings to EPIC */ 1085 CSR_WRITE_4(sc, PRCDAR, vtophys(sc->rx_desc)); 1086 CSR_WRITE_4(sc, PTCDAR, vtophys(sc->tx_desc)); 1087 1088 /* Put node address to EPIC */ 1089 CSR_WRITE_4(sc, LAN0, ((u_int16_t *)sc->sc_macaddr)[0]); 1090 CSR_WRITE_4(sc, LAN1, ((u_int16_t *)sc->sc_macaddr)[1]); 1091 CSR_WRITE_4(sc, LAN2, ((u_int16_t *)sc->sc_macaddr)[2]); 1092 1093 /* Set tx mode, includeing transmit threshold */ 1094 epic_set_tx_mode(sc); 1095 1096 /* Compute and set RXCON. */ 1097 epic_set_rx_mode(sc); 1098 1099 /* Set multicast table */ 1100 epic_set_mc_table(sc); 1101 1102 /* Enable interrupts by setting the interrupt mask. */ 1103 CSR_WRITE_4(sc, INTMASK, 1104 INTSTAT_RCC | /* INTSTAT_RQE | INTSTAT_OVW | INTSTAT_RXE | */ 1105 /* INTSTAT_TXC | */ INTSTAT_TCC | INTSTAT_TQE | INTSTAT_TXU | 1106 INTSTAT_FATAL); 1107 1108 /* Acknowledge all pending interrupts */ 1109 CSR_WRITE_4(sc, INTSTAT, CSR_READ_4(sc, INTSTAT)); 1110 1111 /* Enable interrupts, set for PCI read multiple and etc */ 1112 CSR_WRITE_4(sc, GENCTL, 1113 GENCTL_ENABLE_INTERRUPT | GENCTL_MEMORY_READ_MULTIPLE | 1114 GENCTL_ONECOPY | GENCTL_RECEIVE_FIFO_THRESHOLD64); 1115 1116 /* Mark interface running ... */ 1117 if (ifp->if_flags & IFF_UP) ifp->if_flags |= IFF_RUNNING; 1118 else ifp->if_flags &= ~IFF_RUNNING; 1119 1120 /* ... and free */ 1121 ifp->if_flags &= ~IFF_OACTIVE; 1122 1123 /* Start Rx process */ 1124 epic_start_activity(sc); 1125 1126 /* Set appropriate media */ 1127 epic_ifmedia_upd(ifp); 1128 1129 callout_reset(&sc->tx_stat_timer, hz, epic_stats_update, sc); 1130 1131 return 0; 1132 } 1133 1134 /* 1135 * Synopsis: calculate and set Rx mode. Chip must be in idle state to 1136 * access RXCON. 1137 */ 1138 static void 1139 epic_set_rx_mode(epic_softc_t *sc) 1140 { 1141 u_int32_t flags = sc->sc_if.if_flags; 1142 u_int32_t rxcon = RXCON_DEFAULT; 1143 1144 #if defined(EPIC_EARLY_RX) 1145 rxcon |= RXCON_EARLY_RX; 1146 #endif 1147 1148 rxcon |= (flags & IFF_PROMISC) ? RXCON_PROMISCUOUS_MODE : 0; 1149 1150 CSR_WRITE_4(sc, RXCON, rxcon); 1151 1152 return; 1153 } 1154 1155 /* 1156 * Synopsis: Set transmit control register. Chip must be in idle state to 1157 * access TXCON. 1158 */ 1159 static void 1160 epic_set_tx_mode(epic_softc_t *sc) 1161 { 1162 if (sc->txcon & TXCON_EARLY_TRANSMIT_ENABLE) 1163 CSR_WRITE_4(sc, ETXTHR, sc->tx_threshold); 1164 1165 CSR_WRITE_4(sc, TXCON, sc->txcon); 1166 } 1167 1168 /* 1169 * Synopsis: Program multicast filter honoring IFF_ALLMULTI and IFF_PROMISC 1170 * flags. (Note, that setting PROMISC bit in EPIC's RXCON will only touch 1171 * individual frames, multicast filter must be manually programmed) 1172 * 1173 * Note: EPIC must be in idle state. 1174 */ 1175 static void 1176 epic_set_mc_table(epic_softc_t *sc) 1177 { 1178 struct ifnet *ifp = &sc->sc_if; 1179 struct ifmultiaddr *ifma; 1180 u_int16_t filter[4]; 1181 u_int8_t h; 1182 1183 if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) { 1184 CSR_WRITE_4(sc, MC0, 0xFFFF); 1185 CSR_WRITE_4(sc, MC1, 0xFFFF); 1186 CSR_WRITE_4(sc, MC2, 0xFFFF); 1187 CSR_WRITE_4(sc, MC3, 0xFFFF); 1188 1189 return; 1190 } 1191 1192 filter[0] = 0; 1193 filter[1] = 0; 1194 filter[2] = 0; 1195 filter[3] = 0; 1196 1197 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1198 if (ifma->ifma_addr->sa_family != AF_LINK) 1199 continue; 1200 h = (ether_crc32_be( 1201 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 1202 ETHER_ADDR_LEN) >> 26) & 0x3f; 1203 filter[h >> 4] |= 1 << (h & 0xF); 1204 } 1205 1206 CSR_WRITE_4(sc, MC0, filter[0]); 1207 CSR_WRITE_4(sc, MC1, filter[1]); 1208 CSR_WRITE_4(sc, MC2, filter[2]); 1209 CSR_WRITE_4(sc, MC3, filter[3]); 1210 1211 return; 1212 } 1213 1214 /* 1215 * Synopsis: Start receive process and transmit one, if they need. 1216 */ 1217 static void 1218 epic_start_activity(epic_softc_t *sc) 1219 { 1220 /* Start rx process */ 1221 CSR_WRITE_4(sc, COMMAND, 1222 COMMAND_RXQUEUED | COMMAND_START_RX | 1223 (sc->pending_txs?COMMAND_TXQUEUED:0)); 1224 } 1225 1226 /* 1227 * Synopsis: Completely stop Rx and Tx processes. If TQE is set additional 1228 * packet needs to be queued to stop Tx DMA. 1229 */ 1230 static void 1231 epic_stop_activity(epic_softc_t *sc) 1232 { 1233 int status, i; 1234 1235 /* Stop Tx and Rx DMA */ 1236 CSR_WRITE_4(sc, COMMAND, 1237 COMMAND_STOP_RX | COMMAND_STOP_RDMA | COMMAND_STOP_TDMA); 1238 1239 /* Wait Rx and Tx DMA to stop (why 1 ms ??? XXX) */ 1240 for (i=0; i<0x1000; i++) { 1241 status = CSR_READ_4(sc, INTSTAT) & (INTSTAT_TXIDLE | INTSTAT_RXIDLE); 1242 if (status == (INTSTAT_TXIDLE | INTSTAT_RXIDLE)) 1243 break; 1244 DELAY(1); 1245 } 1246 1247 /* Catch all finished packets */ 1248 epic_rx_done(sc); 1249 epic_tx_done(sc); 1250 1251 status = CSR_READ_4(sc, INTSTAT); 1252 1253 if ((status & INTSTAT_RXIDLE) == 0) 1254 if_printf(&sc->sc_if, "ERROR! Can't stop Rx DMA\n"); 1255 1256 if ((status & INTSTAT_TXIDLE) == 0) 1257 if_printf(&sc->sc_if, "ERROR! Can't stop Tx DMA\n"); 1258 1259 /* 1260 * May need to queue one more packet if TQE, this is rare 1261 * but existing case. 1262 */ 1263 if ((status & INTSTAT_TQE) && !(status & INTSTAT_TXIDLE)) 1264 epic_queue_last_packet(sc); 1265 1266 } 1267 1268 /* 1269 * The EPIC transmitter may stuck in TQE state. It will not go IDLE until 1270 * a packet from current descriptor will be copied to internal RAM. We 1271 * compose a dummy packet here and queue it for transmission. 1272 * 1273 * XXX the packet will then be actually sent over network... 1274 */ 1275 static int 1276 epic_queue_last_packet(epic_softc_t *sc) 1277 { 1278 struct epic_tx_desc *desc; 1279 struct epic_frag_list *flist; 1280 struct epic_tx_buffer *buf; 1281 struct mbuf *m0; 1282 int i; 1283 1284 if_printf(&sc->sc_if, "queue last packet\n"); 1285 1286 desc = sc->tx_desc + sc->cur_tx; 1287 flist = sc->tx_flist + sc->cur_tx; 1288 buf = sc->tx_buffer + sc->cur_tx; 1289 1290 if ((desc->status & 0x8000) || (buf->mbuf != NULL)) 1291 return (EBUSY); 1292 1293 MGETHDR(m0, MB_DONTWAIT, MT_DATA); 1294 if (NULL == m0) 1295 return (ENOBUFS); 1296 1297 /* Prepare mbuf */ 1298 m0->m_len = min(MHLEN, ETHER_MIN_LEN-ETHER_CRC_LEN); 1299 flist->frag[0].fraglen = m0->m_len; 1300 m0->m_pkthdr.len = m0->m_len; 1301 m0->m_pkthdr.rcvif = &sc->sc_if; 1302 bzero(mtod(m0,caddr_t), m0->m_len); 1303 1304 /* Fill fragments list */ 1305 flist->frag[0].fraglen = m0->m_len; 1306 flist->frag[0].fragaddr = vtophys(mtod(m0, caddr_t)); 1307 flist->numfrags = 1; 1308 1309 /* Fill in descriptor */ 1310 buf->mbuf = m0; 1311 sc->pending_txs++; 1312 sc->cur_tx = (sc->cur_tx + 1) & TX_RING_MASK; 1313 desc->control = 0x01; 1314 desc->txlength = max(m0->m_pkthdr.len,ETHER_MIN_LEN-ETHER_CRC_LEN); 1315 desc->status = 0x8000; 1316 1317 /* Launch transmition */ 1318 CSR_WRITE_4(sc, COMMAND, COMMAND_STOP_TDMA | COMMAND_TXQUEUED); 1319 1320 /* Wait Tx DMA to stop (for how long??? XXX) */ 1321 for (i=0; i<1000; i++) { 1322 if (CSR_READ_4(sc, INTSTAT) & INTSTAT_TXIDLE) 1323 break; 1324 DELAY(1); 1325 } 1326 1327 if ((CSR_READ_4(sc, INTSTAT) & INTSTAT_TXIDLE) == 0) 1328 if_printf(&sc->sc_if, "ERROR! can't stop Tx DMA (2)\n"); 1329 else 1330 epic_tx_done(sc); 1331 1332 return 0; 1333 } 1334 1335 /* 1336 * Synopsis: Shut down board and deallocates rings. 1337 */ 1338 static void 1339 epic_stop(epic_softc_t *sc) 1340 { 1341 sc->sc_if.if_timer = 0; 1342 1343 callout_stop(&sc->tx_stat_timer); 1344 1345 /* Disable interrupts */ 1346 CSR_WRITE_4(sc, INTMASK, 0); 1347 CSR_WRITE_4(sc, GENCTL, 0); 1348 1349 /* Try to stop Rx and TX processes */ 1350 epic_stop_activity(sc); 1351 1352 /* Reset chip */ 1353 CSR_WRITE_4(sc, GENCTL, GENCTL_SOFT_RESET); 1354 DELAY(1000); 1355 1356 /* Make chip go to bed */ 1357 CSR_WRITE_4(sc, GENCTL, GENCTL_POWER_DOWN); 1358 1359 /* Free memory allocated for rings */ 1360 epic_free_rings(sc); 1361 1362 /* Mark as stoped */ 1363 sc->sc_if.if_flags &= ~IFF_RUNNING; 1364 } 1365 1366 /* 1367 * Synopsis: This function should free all memory allocated for rings. 1368 */ 1369 static void 1370 epic_free_rings(epic_softc_t *sc) 1371 { 1372 int i; 1373 1374 for (i=0; i<RX_RING_SIZE; i++) { 1375 struct epic_rx_buffer *buf = sc->rx_buffer + i; 1376 struct epic_rx_desc *desc = sc->rx_desc + i; 1377 1378 desc->status = 0; 1379 desc->buflength = 0; 1380 desc->bufaddr = 0; 1381 1382 if (buf->mbuf) m_freem(buf->mbuf); 1383 buf->mbuf = NULL; 1384 } 1385 1386 for (i=0; i<TX_RING_SIZE; i++) { 1387 struct epic_tx_buffer *buf = sc->tx_buffer + i; 1388 struct epic_tx_desc *desc = sc->tx_desc + i; 1389 1390 desc->status = 0; 1391 desc->buflength = 0; 1392 desc->bufaddr = 0; 1393 1394 if (buf->mbuf) m_freem(buf->mbuf); 1395 buf->mbuf = NULL; 1396 } 1397 } 1398 1399 /* 1400 * Synopsis: Allocates mbufs for Rx ring and point Rx descs to them. 1401 * Point Tx descs to fragment lists. Check that all descs and fraglists 1402 * are bounded and aligned properly. 1403 */ 1404 static int 1405 epic_init_rings(epic_softc_t *sc) 1406 { 1407 int i; 1408 1409 sc->cur_rx = sc->cur_tx = sc->dirty_tx = sc->pending_txs = 0; 1410 1411 for (i = 0; i < RX_RING_SIZE; i++) { 1412 struct epic_rx_buffer *buf = sc->rx_buffer + i; 1413 struct epic_rx_desc *desc = sc->rx_desc + i; 1414 1415 desc->status = 0; /* Owned by driver */ 1416 desc->next = vtophys(sc->rx_desc + ((i+1) & RX_RING_MASK)); 1417 1418 if ((desc->next & 3) || 1419 ((desc->next & PAGE_MASK) + sizeof *desc) > PAGE_SIZE) { 1420 epic_free_rings(sc); 1421 return EFAULT; 1422 } 1423 1424 buf->mbuf = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR); 1425 if (NULL == buf->mbuf) { 1426 epic_free_rings(sc); 1427 return ENOBUFS; 1428 } 1429 desc->bufaddr = vtophys(mtod(buf->mbuf, caddr_t)); 1430 1431 desc->buflength = MCLBYTES; /* Max RX buffer length */ 1432 desc->status = 0x8000; /* Set owner bit to NIC */ 1433 } 1434 1435 for (i = 0; i < TX_RING_SIZE; i++) { 1436 struct epic_tx_buffer *buf = sc->tx_buffer + i; 1437 struct epic_tx_desc *desc = sc->tx_desc + i; 1438 1439 desc->status = 0; 1440 desc->next = vtophys(sc->tx_desc + ((i+1) & TX_RING_MASK)); 1441 1442 if ((desc->next & 3) || 1443 ((desc->next & PAGE_MASK) + sizeof *desc) > PAGE_SIZE) { 1444 epic_free_rings(sc); 1445 return EFAULT; 1446 } 1447 1448 buf->mbuf = NULL; 1449 desc->bufaddr = vtophys(sc->tx_flist + i); 1450 1451 if ((desc->bufaddr & 3) || 1452 ((desc->bufaddr & PAGE_MASK) + sizeof(struct epic_frag_list)) > PAGE_SIZE) { 1453 epic_free_rings(sc); 1454 return EFAULT; 1455 } 1456 } 1457 1458 return 0; 1459 } 1460 1461 /* 1462 * EEPROM operation functions 1463 */ 1464 static void 1465 epic_write_eepromreg(epic_softc_t *sc, u_int8_t val) 1466 { 1467 u_int16_t i; 1468 1469 CSR_WRITE_1(sc, EECTL, val); 1470 1471 for (i=0; i<0xFF; i++) 1472 if ((CSR_READ_1(sc, EECTL) & 0x20) == 0) break; 1473 1474 return; 1475 } 1476 1477 static u_int8_t 1478 epic_read_eepromreg(epic_softc_t *sc) 1479 { 1480 return CSR_READ_1(sc, EECTL); 1481 } 1482 1483 static u_int8_t 1484 epic_eeprom_clock(epic_softc_t *sc, u_int8_t val) 1485 { 1486 epic_write_eepromreg(sc, val); 1487 epic_write_eepromreg(sc, (val | 0x4)); 1488 epic_write_eepromreg(sc, val); 1489 1490 return epic_read_eepromreg(sc); 1491 } 1492 1493 static void 1494 epic_output_eepromw(epic_softc_t *sc, u_int16_t val) 1495 { 1496 int i; 1497 1498 for (i = 0xF; i >= 0; i--) { 1499 if (val & (1 << i)) 1500 epic_eeprom_clock(sc, 0x0B); 1501 else 1502 epic_eeprom_clock(sc, 0x03); 1503 } 1504 } 1505 1506 static u_int16_t 1507 epic_input_eepromw(epic_softc_t *sc) 1508 { 1509 u_int16_t retval = 0; 1510 int i; 1511 1512 for (i = 0xF; i >= 0; i--) { 1513 if (epic_eeprom_clock(sc, 0x3) & 0x10) 1514 retval |= (1 << i); 1515 } 1516 1517 return retval; 1518 } 1519 1520 static int 1521 epic_read_eeprom(epic_softc_t *sc, u_int16_t loc) 1522 { 1523 u_int16_t dataval; 1524 u_int16_t read_cmd; 1525 1526 epic_write_eepromreg(sc, 3); 1527 1528 if (epic_read_eepromreg(sc) & 0x40) 1529 read_cmd = (loc & 0x3F) | 0x180; 1530 else 1531 read_cmd = (loc & 0xFF) | 0x600; 1532 1533 epic_output_eepromw(sc, read_cmd); 1534 1535 dataval = epic_input_eepromw(sc); 1536 1537 epic_write_eepromreg(sc, 1); 1538 1539 return dataval; 1540 } 1541 1542 /* 1543 * Here goes MII read/write routines 1544 */ 1545 static int 1546 epic_read_phy_reg(epic_softc_t *sc, int phy, int reg) 1547 { 1548 int i; 1549 1550 CSR_WRITE_4(sc, MIICTL, ((reg << 4) | (phy << 9) | 0x01)); 1551 1552 for (i = 0; i < 0x100; i++) { 1553 if ((CSR_READ_4(sc, MIICTL) & 0x01) == 0) break; 1554 DELAY(1); 1555 } 1556 1557 return (CSR_READ_4(sc, MIIDATA)); 1558 } 1559 1560 static void 1561 epic_write_phy_reg(epic_softc_t *sc, int phy, int reg, int val) 1562 { 1563 int i; 1564 1565 CSR_WRITE_4(sc, MIIDATA, val); 1566 CSR_WRITE_4(sc, MIICTL, ((reg << 4) | (phy << 9) | 0x02)); 1567 1568 for(i=0;i<0x100;i++) { 1569 if ((CSR_READ_4(sc, MIICTL) & 0x02) == 0) break; 1570 DELAY(1); 1571 } 1572 1573 return; 1574 } 1575 1576 static int 1577 epic_miibus_readreg(device_t dev, int phy, int reg) 1578 { 1579 epic_softc_t *sc; 1580 1581 sc = device_get_softc(dev); 1582 1583 return (PHY_READ_2(sc, phy, reg)); 1584 } 1585 1586 static int 1587 epic_miibus_writereg(device_t dev, int phy, int reg, int data) 1588 { 1589 epic_softc_t *sc; 1590 1591 sc = device_get_softc(dev); 1592 1593 PHY_WRITE_2(sc, phy, reg, data); 1594 1595 return (0); 1596 } 1597