1 /*- 2 * Copyright (c) 1997 Semen Ustimenko (semenu@FreeBSD.org) 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD: src/sys/dev/tx/if_tx.c,v 1.61.2.1 2002/10/29 01:43:49 semenu Exp $ 27 * $DragonFly: src/sys/dev/netif/tx/if_tx.c,v 1.39 2006/12/22 23:26:22 swildner Exp $ 28 */ 29 30 /* 31 * EtherPower II 10/100 Fast Ethernet (SMC 9432 serie) 32 * 33 * These cards are based on SMC83c17x (EPIC) chip and one of the various 34 * PHYs (QS6612, AC101 and LXT970 were seen). The media support depends on 35 * card model. All cards support 10baseT/UTP and 100baseTX half- and full- 36 * duplex (SMB9432TX). SMC9432BTX also supports 10baseT/BNC. SMC9432FTX also 37 * supports fibre optics. 38 * 39 * Thanks are going to Steve Bauer and Jason Wright. 40 */ 41 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 #include <sys/sockio.h> 45 #include <sys/mbuf.h> 46 #include <sys/malloc.h> 47 #include <sys/kernel.h> 48 #include <sys/socket.h> 49 #include <sys/queue.h> 50 #include <sys/serialize.h> 51 #include <sys/bus.h> 52 #include <sys/rman.h> 53 #include <sys/thread2.h> 54 55 #include <net/if.h> 56 #include <net/ifq_var.h> 57 #include <net/if_arp.h> 58 #include <net/ethernet.h> 59 #include <net/if_dl.h> 60 #include <net/if_media.h> 61 62 #include <net/bpf.h> 63 64 #include <net/vlan/if_vlan_var.h> 65 66 #include <vm/vm.h> /* for vtophys */ 67 #include <vm/pmap.h> /* for vtophys */ 68 69 #include <bus/pci/pcireg.h> 70 #include <bus/pci/pcivar.h> 71 #include <bus/pci/pcidevs.h> 72 73 #include <dev/netif/mii_layer/mii.h> 74 #include <dev/netif/mii_layer/miivar.h> 75 #include <dev/netif/mii_layer/miidevs.h> 76 #include <dev/netif/mii_layer/lxtphyreg.h> 77 78 #include "miibus_if.h" 79 80 #include <dev/netif/tx/if_txreg.h> 81 #include <dev/netif/tx/if_txvar.h> 82 83 static int epic_ifioctl(struct ifnet *, u_long, caddr_t, struct ucred *); 84 static void epic_intr(void *); 85 static void epic_tx_underrun(epic_softc_t *); 86 static int epic_common_attach(epic_softc_t *); 87 static void epic_ifstart(struct ifnet *); 88 static void epic_ifwatchdog(struct ifnet *); 89 static void epic_stats_update(void *); 90 static int epic_init(epic_softc_t *); 91 static void epic_stop(epic_softc_t *); 92 static void epic_rx_done(epic_softc_t *); 93 static void epic_tx_done(epic_softc_t *); 94 static int epic_init_rings(epic_softc_t *); 95 static void epic_free_rings(epic_softc_t *); 96 static void epic_stop_activity(epic_softc_t *); 97 static int epic_queue_last_packet(epic_softc_t *); 98 static void epic_start_activity(epic_softc_t *); 99 static void epic_set_rx_mode(epic_softc_t *); 100 static void epic_set_tx_mode(epic_softc_t *); 101 static void epic_set_mc_table(epic_softc_t *); 102 static int epic_read_eeprom(epic_softc_t *,u_int16_t); 103 static void epic_output_eepromw(epic_softc_t *, u_int16_t); 104 static u_int16_t epic_input_eepromw(epic_softc_t *); 105 static u_int8_t epic_eeprom_clock(epic_softc_t *,u_int8_t); 106 static void epic_write_eepromreg(epic_softc_t *,u_int8_t); 107 static u_int8_t epic_read_eepromreg(epic_softc_t *); 108 109 static int epic_read_phy_reg(epic_softc_t *, int, int); 110 static void epic_write_phy_reg(epic_softc_t *, int, int, int); 111 112 static int epic_miibus_readreg(device_t, int, int); 113 static int epic_miibus_writereg(device_t, int, int, int); 114 static void epic_miibus_statchg(device_t); 115 static void epic_miibus_mediainit(device_t); 116 117 static int epic_ifmedia_upd(struct ifnet *); 118 static void epic_ifmedia_sts(struct ifnet *, struct ifmediareq *); 119 120 static int epic_probe(device_t); 121 static int epic_attach(device_t); 122 static void epic_shutdown(device_t); 123 static int epic_detach(device_t); 124 125 static device_method_t epic_methods[] = { 126 /* Device interface */ 127 DEVMETHOD(device_probe, epic_probe), 128 DEVMETHOD(device_attach, epic_attach), 129 DEVMETHOD(device_detach, epic_detach), 130 DEVMETHOD(device_shutdown, epic_shutdown), 131 132 /* MII interface */ 133 DEVMETHOD(miibus_readreg, epic_miibus_readreg), 134 DEVMETHOD(miibus_writereg, epic_miibus_writereg), 135 DEVMETHOD(miibus_statchg, epic_miibus_statchg), 136 DEVMETHOD(miibus_mediainit, epic_miibus_mediainit), 137 138 { 0, 0 } 139 }; 140 141 static driver_t epic_driver = { 142 "tx", 143 epic_methods, 144 sizeof(epic_softc_t) 145 }; 146 147 static devclass_t epic_devclass; 148 149 DECLARE_DUMMY_MODULE(if_tx); 150 MODULE_DEPEND(if_tx, miibus, 1, 1, 1); 151 DRIVER_MODULE(if_tx, pci, epic_driver, epic_devclass, 0, 0); 152 DRIVER_MODULE(miibus, tx, miibus_driver, miibus_devclass, 0, 0); 153 154 static struct epic_type epic_devs[] = { 155 { PCI_VENDOR_SMC, PCI_PRODUCT_SMC_83C170, 156 "SMC EtherPower II 10/100" }, 157 { 0, 0, NULL } 158 }; 159 160 static int 161 epic_probe(device_t dev) 162 { 163 struct epic_type *t; 164 uint16_t vid, did; 165 166 vid = pci_get_vendor(dev); 167 did = pci_get_device(dev); 168 for (t = epic_devs; t->name != NULL; ++t) { 169 if (vid == t->ven_id && did == t->dev_id) { 170 device_set_desc(dev, t->name); 171 return 0; 172 } 173 } 174 return ENXIO; 175 } 176 177 #if defined(EPIC_USEIOSPACE) 178 #define EPIC_RES SYS_RES_IOPORT 179 #define EPIC_RID PCIR_BAR(0) 180 #else 181 #define EPIC_RES SYS_RES_MEMORY 182 #define EPIC_RID PCIR_BAR(1) 183 #endif 184 185 /* 186 * Attach routine: map registers, allocate softc, rings and descriptors. 187 * Reset to known state. 188 */ 189 static int 190 epic_attach(device_t dev) 191 { 192 struct ifnet *ifp; 193 epic_softc_t *sc; 194 int error; 195 int i, rid, tmp; 196 197 sc = device_get_softc(dev); 198 199 /* Preinitialize softc structure */ 200 sc->dev = dev; 201 callout_init(&sc->tx_stat_timer); 202 203 /* Fill ifnet structure */ 204 ifp = &sc->sc_if; 205 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 206 ifp->if_softc = sc; 207 ifp->if_flags = IFF_BROADCAST|IFF_SIMPLEX|IFF_MULTICAST; 208 ifp->if_ioctl = epic_ifioctl; 209 ifp->if_start = epic_ifstart; 210 ifp->if_watchdog = epic_ifwatchdog; 211 ifp->if_init = (if_init_f_t*)epic_init; 212 ifp->if_timer = 0; 213 ifp->if_baudrate = 10000000; 214 ifq_set_maxlen(&ifp->if_snd, TX_RING_SIZE - 1); 215 ifq_set_ready(&ifp->if_snd); 216 217 pci_enable_busmaster(dev); 218 219 rid = EPIC_RID; 220 sc->res = bus_alloc_resource_any(dev, EPIC_RES, &rid, RF_ACTIVE); 221 222 if (sc->res == NULL) { 223 device_printf(dev, "couldn't map ports/memory\n"); 224 error = ENXIO; 225 goto fail; 226 } 227 228 sc->sc_st = rman_get_bustag(sc->res); 229 sc->sc_sh = rman_get_bushandle(sc->res); 230 231 /* Allocate interrupt */ 232 rid = 0; 233 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 234 RF_SHAREABLE | RF_ACTIVE); 235 236 if (sc->irq == NULL) { 237 device_printf(dev, "couldn't map interrupt\n"); 238 error = ENXIO; 239 goto fail; 240 } 241 242 /* Do OS independent part, including chip wakeup and reset */ 243 error = epic_common_attach(sc); 244 if (error) { 245 error = ENXIO; 246 goto fail; 247 } 248 249 /* Do ifmedia setup */ 250 if (mii_phy_probe(dev, &sc->miibus, 251 epic_ifmedia_upd, epic_ifmedia_sts)) { 252 device_printf(dev, "ERROR! MII without any PHY!?\n"); 253 error = ENXIO; 254 goto fail; 255 } 256 257 /* board type and ... */ 258 kprintf(" type "); 259 for(i=0x2c;i<0x32;i++) { 260 tmp = epic_read_eeprom(sc, i); 261 if (' ' == (u_int8_t)tmp) break; 262 kprintf("%c", (u_int8_t)tmp); 263 tmp >>= 8; 264 if (' ' == (u_int8_t)tmp) break; 265 kprintf("%c", (u_int8_t)tmp); 266 } 267 kprintf("\n"); 268 269 /* Attach to OS's managers */ 270 ether_ifattach(ifp, sc->sc_macaddr, NULL); 271 ifp->if_hdrlen = sizeof(struct ether_vlan_header); 272 273 error = bus_setup_intr(dev, sc->irq, INTR_NETSAFE, 274 epic_intr, sc, &sc->sc_ih, 275 ifp->if_serializer); 276 277 if (error) { 278 device_printf(dev, "couldn't set up irq\n"); 279 ether_ifdetach(ifp); 280 goto fail; 281 } 282 283 return(0); 284 285 fail: 286 epic_detach(dev); 287 return(error); 288 } 289 290 /* 291 * Detach driver and free resources 292 */ 293 static int 294 epic_detach(device_t dev) 295 { 296 epic_softc_t *sc = device_get_softc(dev); 297 struct ifnet *ifp = &sc->arpcom.ac_if; 298 299 if (device_is_attached(dev)) { 300 lwkt_serialize_enter(ifp->if_serializer); 301 epic_stop(sc); 302 bus_teardown_intr(dev, sc->irq, sc->sc_ih); 303 lwkt_serialize_exit(ifp->if_serializer); 304 305 ether_ifdetach(ifp); 306 } 307 308 if (sc->miibus) 309 device_delete_child(dev, sc->miibus); 310 bus_generic_detach(dev); 311 312 if (sc->irq) 313 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq); 314 if (sc->res) 315 bus_release_resource(dev, EPIC_RES, EPIC_RID, sc->res); 316 317 if (sc->tx_flist) 318 kfree(sc->tx_flist, M_DEVBUF); 319 if (sc->tx_desc) 320 kfree(sc->tx_desc, M_DEVBUF); 321 if (sc->rx_desc) 322 kfree(sc->rx_desc, M_DEVBUF); 323 324 return(0); 325 } 326 327 #undef EPIC_RES 328 #undef EPIC_RID 329 330 /* 331 * Stop all chip I/O so that the kernel's probe routines don't 332 * get confused by errant DMAs when rebooting. 333 */ 334 static void 335 epic_shutdown(device_t dev) 336 { 337 epic_softc_t *sc; 338 struct ifnet *ifp; 339 340 sc = device_get_softc(dev); 341 ifp = &sc->arpcom.ac_if; 342 lwkt_serialize_enter(ifp->if_serializer); 343 epic_stop(sc); 344 lwkt_serialize_exit(ifp->if_serializer); 345 } 346 347 /* 348 * This is if_ioctl handler. 349 */ 350 static int 351 epic_ifioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr) 352 { 353 epic_softc_t *sc = ifp->if_softc; 354 struct mii_data *mii; 355 struct ifreq *ifr = (struct ifreq *) data; 356 int error = 0; 357 358 switch (command) { 359 case SIOCSIFMTU: 360 if (ifp->if_mtu == ifr->ifr_mtu) 361 break; 362 363 /* XXX Though the datasheet doesn't imply any 364 * limitations on RX and TX sizes beside max 64Kb 365 * DMA transfer, seems we can't send more then 1600 366 * data bytes per ethernet packet. (Transmitter hangs 367 * up if more data is sent) 368 */ 369 if (ifr->ifr_mtu + ifp->if_hdrlen <= EPIC_MAX_MTU) { 370 ifp->if_mtu = ifr->ifr_mtu; 371 epic_stop(sc); 372 epic_init(sc); 373 } else 374 error = EINVAL; 375 break; 376 377 case SIOCSIFFLAGS: 378 /* 379 * If the interface is marked up and stopped, then start it. 380 * If it is marked down and running, then stop it. 381 */ 382 if (ifp->if_flags & IFF_UP) { 383 if ((ifp->if_flags & IFF_RUNNING) == 0) { 384 epic_init(sc); 385 break; 386 } 387 } else { 388 if (ifp->if_flags & IFF_RUNNING) { 389 epic_stop(sc); 390 break; 391 } 392 } 393 394 /* Handle IFF_PROMISC and IFF_ALLMULTI flags */ 395 epic_stop_activity(sc); 396 epic_set_mc_table(sc); 397 epic_set_rx_mode(sc); 398 epic_start_activity(sc); 399 break; 400 401 case SIOCADDMULTI: 402 case SIOCDELMULTI: 403 epic_set_mc_table(sc); 404 error = 0; 405 break; 406 407 case SIOCSIFMEDIA: 408 case SIOCGIFMEDIA: 409 mii = device_get_softc(sc->miibus); 410 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 411 break; 412 413 default: 414 error = ether_ioctl(ifp, command, data); 415 break; 416 } 417 return error; 418 } 419 420 /* 421 * OS-independed part of attach process. allocate memory for descriptors 422 * and frag lists, wake up chip, read MAC address and PHY identyfier. 423 * Return -1 on failure. 424 */ 425 static int 426 epic_common_attach(epic_softc_t *sc) 427 { 428 uint16_t sub_vid; 429 int i; 430 431 sc->tx_flist = kmalloc(sizeof(struct epic_frag_list)*TX_RING_SIZE, 432 M_DEVBUF, M_WAITOK | M_ZERO); 433 sc->tx_desc = kmalloc(sizeof(struct epic_tx_desc)*TX_RING_SIZE, 434 M_DEVBUF, M_WAITOK | M_ZERO); 435 sc->rx_desc = kmalloc(sizeof(struct epic_rx_desc)*RX_RING_SIZE, 436 M_DEVBUF, M_WAITOK | M_ZERO); 437 438 /* Bring the chip out of low-power mode. */ 439 CSR_WRITE_4(sc, GENCTL, GENCTL_SOFT_RESET); 440 DELAY(500); 441 442 /* Workaround for Application Note 7-15 */ 443 for (i=0; i<16; i++) CSR_WRITE_4(sc, TEST1, TEST1_CLOCK_TEST); 444 445 /* Read mac address from EEPROM */ 446 for (i = 0; i < ETHER_ADDR_LEN / sizeof(u_int16_t); i++) 447 ((u_int16_t *)sc->sc_macaddr)[i] = epic_read_eeprom(sc,i); 448 449 /* Set Non-Volatile Control Register from EEPROM */ 450 CSR_WRITE_4(sc, NVCTL, epic_read_eeprom(sc, EEPROM_NVCTL) & 0x1F); 451 452 /* Set defaults */ 453 sc->tx_threshold = TRANSMIT_THRESHOLD; 454 sc->txcon = TXCON_DEFAULT; 455 sc->miicfg = MIICFG_SMI_ENABLE; 456 sc->phyid = EPIC_UNKN_PHY; 457 sc->serinst = -1; 458 459 /* Fetch card id */ 460 sub_vid = pci_get_subvendor(sc->dev); 461 sc->cardid = pci_get_subdevice(sc->dev); 462 463 if (sub_vid != PCI_VENDOR_SMC) 464 device_printf(sc->dev, "unknown card vendor %04xh\n", sub_vid); 465 466 return 0; 467 } 468 469 /* 470 * This is if_start handler. It takes mbufs from if_snd queue 471 * and queue them for transmit, one by one, until TX ring become full 472 * or queue become empty. 473 */ 474 static void 475 epic_ifstart(struct ifnet *ifp) 476 { 477 epic_softc_t *sc = ifp->if_softc; 478 struct epic_tx_buffer *buf; 479 struct epic_tx_desc *desc; 480 struct epic_frag_list *flist; 481 struct mbuf *m0; 482 struct mbuf *m; 483 int i; 484 485 while (sc->pending_txs < TX_RING_SIZE) { 486 buf = sc->tx_buffer + sc->cur_tx; 487 desc = sc->tx_desc + sc->cur_tx; 488 flist = sc->tx_flist + sc->cur_tx; 489 490 /* Get next packet to send */ 491 m0 = ifq_dequeue(&ifp->if_snd, NULL); 492 493 /* If nothing to send, return */ 494 if (m0 == NULL) 495 return; 496 497 /* Fill fragments list */ 498 for (m = m0, i = 0; 499 (NULL != m) && (i < EPIC_MAX_FRAGS); 500 m = m->m_next, i++) { 501 flist->frag[i].fraglen = m->m_len; 502 flist->frag[i].fragaddr = vtophys(mtod(m, caddr_t)); 503 } 504 flist->numfrags = i; 505 506 /* If packet was more than EPIC_MAX_FRAGS parts, */ 507 /* recopy packet to new allocated mbuf cluster */ 508 if (NULL != m) { 509 m = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR); 510 if (NULL == m) { 511 m_freem(m0); 512 ifp->if_oerrors++; 513 continue; 514 } 515 516 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 517 flist->frag[0].fraglen = 518 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 519 m->m_pkthdr.rcvif = ifp; 520 521 flist->numfrags = 1; 522 flist->frag[0].fragaddr = vtophys(mtod(m, caddr_t)); 523 m_freem(m0); 524 m0 = m; 525 } 526 527 buf->mbuf = m0; 528 sc->pending_txs++; 529 sc->cur_tx = (sc->cur_tx + 1) & TX_RING_MASK; 530 desc->control = 0x01; 531 desc->txlength = 532 max(m0->m_pkthdr.len,ETHER_MIN_LEN-ETHER_CRC_LEN); 533 desc->status = 0x8000; 534 CSR_WRITE_4(sc, COMMAND, COMMAND_TXQUEUED); 535 536 /* Set watchdog timer */ 537 ifp->if_timer = 8; 538 539 BPF_MTAP(ifp, m0); 540 } 541 542 ifp->if_flags |= IFF_OACTIVE; 543 544 return; 545 546 } 547 548 /* 549 * Synopsis: Finish all received frames. 550 */ 551 static void 552 epic_rx_done(epic_softc_t *sc) 553 { 554 u_int16_t len; 555 struct ifnet *ifp = &sc->sc_if; 556 struct epic_rx_buffer *buf; 557 struct epic_rx_desc *desc; 558 struct mbuf *m; 559 560 while ((sc->rx_desc[sc->cur_rx].status & 0x8000) == 0) { 561 buf = sc->rx_buffer + sc->cur_rx; 562 desc = sc->rx_desc + sc->cur_rx; 563 564 /* Switch to next descriptor */ 565 sc->cur_rx = (sc->cur_rx+1) & RX_RING_MASK; 566 567 /* 568 * Check for RX errors. This should only happen if 569 * SAVE_ERRORED_PACKETS is set. RX errors generate 570 * RXE interrupt usually. 571 */ 572 if ((desc->status & 1) == 0) { 573 sc->sc_if.if_ierrors++; 574 desc->status = 0x8000; 575 continue; 576 } 577 578 /* Save packet length and mbuf contained packet */ 579 len = desc->rxlength - ETHER_CRC_LEN; 580 m = buf->mbuf; 581 582 /* Try to get mbuf cluster */ 583 buf->mbuf = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR); 584 if (NULL == buf->mbuf) { 585 buf->mbuf = m; 586 desc->status = 0x8000; 587 ifp->if_ierrors++; 588 continue; 589 } 590 591 /* Point to new mbuf, and give descriptor to chip */ 592 desc->bufaddr = vtophys(mtod(buf->mbuf, caddr_t)); 593 desc->status = 0x8000; 594 595 /* First mbuf in packet holds the ethernet and packet headers */ 596 m->m_pkthdr.rcvif = ifp; 597 m->m_pkthdr.len = m->m_len = len; 598 599 /* Give mbuf to OS */ 600 ifp->if_input(ifp, m); 601 602 /* Successfuly received frame */ 603 ifp->if_ipackets++; 604 } 605 606 return; 607 } 608 609 /* 610 * Synopsis: Do last phase of transmission. I.e. if desc is 611 * transmitted, decrease pending_txs counter, free mbuf contained 612 * packet, switch to next descriptor and repeat until no packets 613 * are pending or descriptor is not transmitted yet. 614 */ 615 static void 616 epic_tx_done(epic_softc_t *sc) 617 { 618 struct epic_tx_buffer *buf; 619 struct epic_tx_desc *desc; 620 u_int16_t status; 621 622 while (sc->pending_txs > 0) { 623 buf = sc->tx_buffer + sc->dirty_tx; 624 desc = sc->tx_desc + sc->dirty_tx; 625 status = desc->status; 626 627 /* If packet is not transmitted, thou followed */ 628 /* packets are not transmitted too */ 629 if (status & 0x8000) break; 630 631 /* Packet is transmitted. Switch to next and */ 632 /* free mbuf */ 633 sc->pending_txs--; 634 sc->dirty_tx = (sc->dirty_tx + 1) & TX_RING_MASK; 635 m_freem(buf->mbuf); 636 buf->mbuf = NULL; 637 638 /* Check for errors and collisions */ 639 if (status & 0x0001) sc->sc_if.if_opackets++; 640 else sc->sc_if.if_oerrors++; 641 sc->sc_if.if_collisions += (status >> 8) & 0x1F; 642 #if defined(EPIC_DIAG) 643 if ((status & 0x1001) == 0x1001) { 644 if_printf(&sc->sc_if, 645 "Tx ERROR: excessive coll. number\n"); 646 } 647 #endif 648 } 649 650 if (sc->pending_txs < TX_RING_SIZE) 651 sc->sc_if.if_flags &= ~IFF_OACTIVE; 652 } 653 654 /* 655 * Interrupt function 656 */ 657 static void 658 epic_intr(void *arg) 659 { 660 epic_softc_t * sc = (epic_softc_t *) arg; 661 int status, i = 4; 662 663 while (i-- && ((status = CSR_READ_4(sc, INTSTAT)) & INTSTAT_INT_ACTV)) { 664 CSR_WRITE_4(sc, INTSTAT, status); 665 666 if (status & (INTSTAT_RQE|INTSTAT_RCC|INTSTAT_OVW)) { 667 epic_rx_done(sc); 668 if (status & (INTSTAT_RQE|INTSTAT_OVW)) { 669 #if defined(EPIC_DIAG) 670 if (status & INTSTAT_OVW) 671 if_printf(&sc->sc_if, "RX buffer overflow\n"); 672 if (status & INTSTAT_RQE) 673 if_printf(&sc->sc_if, "RX FIFO overflow\n"); 674 #endif 675 if ((CSR_READ_4(sc, COMMAND) & COMMAND_RXQUEUED) == 0) 676 CSR_WRITE_4(sc, COMMAND, COMMAND_RXQUEUED); 677 sc->sc_if.if_ierrors++; 678 } 679 } 680 681 if (status & (INTSTAT_TXC|INTSTAT_TCC|INTSTAT_TQE)) { 682 epic_tx_done(sc); 683 if (!ifq_is_empty(&sc->sc_if.if_snd)) 684 epic_ifstart(&sc->sc_if); 685 } 686 687 /* Check for rare errors */ 688 if (status & (INTSTAT_FATAL|INTSTAT_PMA|INTSTAT_PTA| 689 INTSTAT_APE|INTSTAT_DPE|INTSTAT_TXU|INTSTAT_RXE)) { 690 if (status & (INTSTAT_FATAL|INTSTAT_PMA|INTSTAT_PTA| 691 INTSTAT_APE|INTSTAT_DPE)) { 692 if_printf(&sc->sc_if, "PCI fatal errors occured: %s%s%s%s\n", 693 (status&INTSTAT_PMA)?"PMA ":"", 694 (status&INTSTAT_PTA)?"PTA ":"", 695 (status&INTSTAT_APE)?"APE ":"", 696 (status&INTSTAT_DPE)?"DPE":"" 697 ); 698 699 epic_stop(sc); 700 epic_init(sc); 701 702 break; 703 } 704 705 if (status & INTSTAT_RXE) { 706 #if defined(EPIC_DIAG) 707 if_printf(sc->sc_if, "CRC/Alignment error\n"); 708 #endif 709 sc->sc_if.if_ierrors++; 710 } 711 712 if (status & INTSTAT_TXU) { 713 epic_tx_underrun(sc); 714 sc->sc_if.if_oerrors++; 715 } 716 } 717 } 718 719 /* If no packets are pending, then no timeouts */ 720 if (sc->pending_txs == 0) sc->sc_if.if_timer = 0; 721 722 return; 723 } 724 725 /* 726 * Handle the TX underrun error: increase the TX threshold 727 * and restart the transmitter. 728 */ 729 static void 730 epic_tx_underrun(epic_softc_t *sc) 731 { 732 if (sc->tx_threshold > TRANSMIT_THRESHOLD_MAX) { 733 sc->txcon &= ~TXCON_EARLY_TRANSMIT_ENABLE; 734 #if defined(EPIC_DIAG) 735 if_printf(&sc->sc_if, "Tx UNDERRUN: early TX disabled\n"); 736 #endif 737 } else { 738 sc->tx_threshold += 0x40; 739 #if defined(EPIC_DIAG) 740 if_printf(&sc->sc_if, "Tx UNDERRUN: " 741 "TX threshold increased to %d\n", sc->tx_threshold); 742 #endif 743 } 744 745 /* We must set TXUGO to reset the stuck transmitter */ 746 CSR_WRITE_4(sc, COMMAND, COMMAND_TXUGO); 747 748 /* Update the TX threshold */ 749 epic_stop_activity(sc); 750 epic_set_tx_mode(sc); 751 epic_start_activity(sc); 752 753 return; 754 } 755 756 /* 757 * Synopsis: This one is called if packets wasn't transmitted 758 * during timeout. Try to deallocate transmitted packets, and 759 * if success continue to work. 760 */ 761 static void 762 epic_ifwatchdog(struct ifnet *ifp) 763 { 764 epic_softc_t *sc = ifp->if_softc; 765 766 if_printf(ifp, "device timeout %d packets\n", sc->pending_txs); 767 768 /* Try to finish queued packets */ 769 epic_tx_done(sc); 770 771 /* If not successful */ 772 if (sc->pending_txs > 0) { 773 774 ifp->if_oerrors+=sc->pending_txs; 775 776 /* Reinitialize board */ 777 if_printf(ifp, "reinitialization\n"); 778 epic_stop(sc); 779 epic_init(sc); 780 781 } else 782 if_printf(ifp, "seems we can continue normaly\n"); 783 784 /* Start output */ 785 if (!ifq_is_empty(&ifp->if_snd)) 786 epic_ifstart(ifp); 787 } 788 789 /* 790 * Despite the name of this function, it doesn't update statistics, it only 791 * helps in autonegotiation process. 792 */ 793 static void 794 epic_stats_update(void *xsc) 795 { 796 epic_softc_t *sc = xsc; 797 struct ifnet *ifp = &sc->sc_if; 798 struct mii_data * mii; 799 800 lwkt_serialize_enter(ifp->if_serializer); 801 802 mii = device_get_softc(sc->miibus); 803 mii_tick(mii); 804 805 callout_reset(&sc->tx_stat_timer, hz, epic_stats_update, sc); 806 807 lwkt_serialize_exit(ifp->if_serializer); 808 } 809 810 /* 811 * Set media options. 812 */ 813 static int 814 epic_ifmedia_upd(struct ifnet *ifp) 815 { 816 epic_softc_t *sc; 817 struct mii_data *mii; 818 struct ifmedia *ifm; 819 struct mii_softc *miisc; 820 int cfg, media; 821 822 sc = ifp->if_softc; 823 mii = device_get_softc(sc->miibus); 824 ifm = &mii->mii_media; 825 media = ifm->ifm_cur->ifm_media; 826 827 /* Do not do anything if interface is not up */ 828 if ((ifp->if_flags & IFF_UP) == 0) 829 return (0); 830 831 /* 832 * Lookup current selected PHY 833 */ 834 if (IFM_INST(media) == sc->serinst) { 835 sc->phyid = EPIC_SERIAL; 836 sc->physc = NULL; 837 } else { 838 /* If we're not selecting serial interface, select MII mode */ 839 sc->miicfg &= ~MIICFG_SERIAL_ENABLE; 840 CSR_WRITE_4(sc, MIICFG, sc->miicfg); 841 842 /* Default to unknown PHY */ 843 sc->phyid = EPIC_UNKN_PHY; 844 845 /* Lookup selected PHY */ 846 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 847 miisc = LIST_NEXT(miisc, mii_list)) { 848 if (IFM_INST(media) == miisc->mii_inst) { 849 sc->physc = miisc; 850 break; 851 } 852 } 853 854 /* Identify selected PHY */ 855 if (sc->physc) { 856 int id1, id2, model, oui; 857 858 id1 = PHY_READ(sc->physc, MII_PHYIDR1); 859 id2 = PHY_READ(sc->physc, MII_PHYIDR2); 860 861 oui = MII_OUI(id1, id2); 862 model = MII_MODEL(id2); 863 switch (oui) { 864 case MII_OUI_QUALSEMI: 865 if (model == MII_MODEL_QUALSEMI_QS6612) 866 sc->phyid = EPIC_QS6612_PHY; 867 break; 868 case MII_OUI_xxALTIMA: 869 if (model == MII_MODEL_xxALTIMA_AC101) 870 sc->phyid = EPIC_AC101_PHY; 871 break; 872 case MII_OUI_xxLEVEL1: 873 if (model == MII_MODEL_xxLEVEL1_LXT970) 874 sc->phyid = EPIC_LXT970_PHY; 875 break; 876 } 877 } 878 } 879 880 /* 881 * Do PHY specific card setup 882 */ 883 884 /* Call this, to isolate all not selected PHYs and 885 * set up selected 886 */ 887 mii_mediachg(mii); 888 889 /* Do our own setup */ 890 switch (sc->phyid) { 891 case EPIC_QS6612_PHY: 892 break; 893 case EPIC_AC101_PHY: 894 /* We have to powerup fiber tranceivers */ 895 if (IFM_SUBTYPE(media) == IFM_100_FX) 896 sc->miicfg |= MIICFG_694_ENABLE; 897 else 898 sc->miicfg &= ~MIICFG_694_ENABLE; 899 CSR_WRITE_4(sc, MIICFG, sc->miicfg); 900 901 break; 902 case EPIC_LXT970_PHY: 903 /* We have to powerup fiber tranceivers */ 904 cfg = PHY_READ(sc->physc, MII_LXTPHY_CONFIG); 905 if (IFM_SUBTYPE(media) == IFM_100_FX) 906 cfg |= CONFIG_LEDC1 | CONFIG_LEDC0; 907 else 908 cfg &= ~(CONFIG_LEDC1 | CONFIG_LEDC0); 909 PHY_WRITE(sc->physc, MII_LXTPHY_CONFIG, cfg); 910 911 break; 912 case EPIC_SERIAL: 913 /* Select serial PHY, (10base2/BNC usually) */ 914 sc->miicfg |= MIICFG_694_ENABLE | MIICFG_SERIAL_ENABLE; 915 CSR_WRITE_4(sc, MIICFG, sc->miicfg); 916 917 /* There is no driver to fill this */ 918 mii->mii_media_active = media; 919 mii->mii_media_status = 0; 920 921 /* We need to call this manualy as i wasn't called 922 * in mii_mediachg() 923 */ 924 epic_miibus_statchg(sc->dev); 925 926 break; 927 default: 928 if_printf(ifp, "ERROR! Unknown PHY selected\n"); 929 return (EINVAL); 930 } 931 932 return(0); 933 } 934 935 /* 936 * Report current media status. 937 */ 938 static void 939 epic_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 940 { 941 epic_softc_t *sc; 942 struct mii_data *mii; 943 struct ifmedia *ifm; 944 945 sc = ifp->if_softc; 946 mii = device_get_softc(sc->miibus); 947 ifm = &mii->mii_media; 948 949 /* Nothing should be selected if interface is down */ 950 if ((ifp->if_flags & IFF_UP) == 0) { 951 ifmr->ifm_active = IFM_NONE; 952 ifmr->ifm_status = 0; 953 954 return; 955 } 956 957 /* Call underlying pollstat, if not serial PHY */ 958 if (sc->phyid != EPIC_SERIAL) 959 mii_pollstat(mii); 960 961 /* Simply copy media info */ 962 ifmr->ifm_active = mii->mii_media_active; 963 ifmr->ifm_status = mii->mii_media_status; 964 965 return; 966 } 967 968 /* 969 * Callback routine, called on media change. 970 */ 971 static void 972 epic_miibus_statchg(device_t dev) 973 { 974 epic_softc_t *sc; 975 struct mii_data *mii; 976 int media; 977 978 sc = device_get_softc(dev); 979 mii = device_get_softc(sc->miibus); 980 media = mii->mii_media_active; 981 982 sc->txcon &= ~(TXCON_LOOPBACK_MODE | TXCON_FULL_DUPLEX); 983 984 /* If we are in full-duplex mode or loopback operation, 985 * we need to decouple receiver and transmitter. 986 */ 987 if (IFM_OPTIONS(media) & (IFM_FDX | IFM_LOOP)) 988 sc->txcon |= TXCON_FULL_DUPLEX; 989 990 /* On some cards we need manualy set fullduplex led */ 991 if (sc->cardid == SMC9432FTX || 992 sc->cardid == SMC9432FTX_SC) { 993 if (IFM_OPTIONS(media) & IFM_FDX) 994 sc->miicfg |= MIICFG_694_ENABLE; 995 else 996 sc->miicfg &= ~MIICFG_694_ENABLE; 997 998 CSR_WRITE_4(sc, MIICFG, sc->miicfg); 999 } 1000 1001 /* Update baudrate */ 1002 if (IFM_SUBTYPE(media) == IFM_100_TX || 1003 IFM_SUBTYPE(media) == IFM_100_FX) 1004 sc->sc_if.if_baudrate = 100000000; 1005 else 1006 sc->sc_if.if_baudrate = 10000000; 1007 1008 epic_stop_activity(sc); 1009 epic_set_tx_mode(sc); 1010 epic_start_activity(sc); 1011 1012 return; 1013 } 1014 1015 static void 1016 epic_miibus_mediainit(device_t dev) 1017 { 1018 epic_softc_t *sc; 1019 struct mii_data *mii; 1020 struct ifmedia *ifm; 1021 int media; 1022 1023 sc = device_get_softc(dev); 1024 mii = device_get_softc(sc->miibus); 1025 ifm = &mii->mii_media; 1026 1027 /* Add Serial Media Interface if present, this applies to 1028 * SMC9432BTX serie 1029 */ 1030 if (CSR_READ_4(sc, MIICFG) & MIICFG_PHY_PRESENT) { 1031 /* Store its instance */ 1032 sc->serinst = mii->mii_instance++; 1033 1034 /* Add as 10base2/BNC media */ 1035 media = IFM_MAKEWORD(IFM_ETHER, IFM_10_2, 0, sc->serinst); 1036 ifmedia_add(ifm, media, 0, NULL); 1037 1038 /* Report to user */ 1039 if_printf(&sc->sc_if, "serial PHY detected (10Base2/BNC)\n"); 1040 } 1041 1042 return; 1043 } 1044 1045 /* 1046 * Reset chip, allocate rings, and update media. 1047 */ 1048 static int 1049 epic_init(epic_softc_t *sc) 1050 { 1051 struct ifnet *ifp = &sc->sc_if; 1052 int i; 1053 1054 /* If interface is already running, then we need not do anything */ 1055 if (ifp->if_flags & IFF_RUNNING) { 1056 return 0; 1057 } 1058 1059 /* Soft reset the chip (we have to power up card before) */ 1060 CSR_WRITE_4(sc, GENCTL, 0); 1061 CSR_WRITE_4(sc, GENCTL, GENCTL_SOFT_RESET); 1062 1063 /* 1064 * Reset takes 15 pci ticks which depends on PCI bus speed. 1065 * Assuming it >= 33000000 hz, we have wait at least 495e-6 sec. 1066 */ 1067 DELAY(500); 1068 1069 /* Wake up */ 1070 CSR_WRITE_4(sc, GENCTL, 0); 1071 1072 /* Workaround for Application Note 7-15 */ 1073 for (i=0; i<16; i++) CSR_WRITE_4(sc, TEST1, TEST1_CLOCK_TEST); 1074 1075 /* Initialize rings */ 1076 if (epic_init_rings(sc)) { 1077 if_printf(ifp, "failed to init rings\n"); 1078 return -1; 1079 } 1080 1081 /* Give rings to EPIC */ 1082 CSR_WRITE_4(sc, PRCDAR, vtophys(sc->rx_desc)); 1083 CSR_WRITE_4(sc, PTCDAR, vtophys(sc->tx_desc)); 1084 1085 /* Put node address to EPIC */ 1086 CSR_WRITE_4(sc, LAN0, ((u_int16_t *)sc->sc_macaddr)[0]); 1087 CSR_WRITE_4(sc, LAN1, ((u_int16_t *)sc->sc_macaddr)[1]); 1088 CSR_WRITE_4(sc, LAN2, ((u_int16_t *)sc->sc_macaddr)[2]); 1089 1090 /* Set tx mode, includeing transmit threshold */ 1091 epic_set_tx_mode(sc); 1092 1093 /* Compute and set RXCON. */ 1094 epic_set_rx_mode(sc); 1095 1096 /* Set multicast table */ 1097 epic_set_mc_table(sc); 1098 1099 /* Enable interrupts by setting the interrupt mask. */ 1100 CSR_WRITE_4(sc, INTMASK, 1101 INTSTAT_RCC | /* INTSTAT_RQE | INTSTAT_OVW | INTSTAT_RXE | */ 1102 /* INTSTAT_TXC | */ INTSTAT_TCC | INTSTAT_TQE | INTSTAT_TXU | 1103 INTSTAT_FATAL); 1104 1105 /* Acknowledge all pending interrupts */ 1106 CSR_WRITE_4(sc, INTSTAT, CSR_READ_4(sc, INTSTAT)); 1107 1108 /* Enable interrupts, set for PCI read multiple and etc */ 1109 CSR_WRITE_4(sc, GENCTL, 1110 GENCTL_ENABLE_INTERRUPT | GENCTL_MEMORY_READ_MULTIPLE | 1111 GENCTL_ONECOPY | GENCTL_RECEIVE_FIFO_THRESHOLD64); 1112 1113 /* Mark interface running ... */ 1114 if (ifp->if_flags & IFF_UP) ifp->if_flags |= IFF_RUNNING; 1115 else ifp->if_flags &= ~IFF_RUNNING; 1116 1117 /* ... and free */ 1118 ifp->if_flags &= ~IFF_OACTIVE; 1119 1120 /* Start Rx process */ 1121 epic_start_activity(sc); 1122 1123 /* Set appropriate media */ 1124 epic_ifmedia_upd(ifp); 1125 1126 callout_reset(&sc->tx_stat_timer, hz, epic_stats_update, sc); 1127 1128 return 0; 1129 } 1130 1131 /* 1132 * Synopsis: calculate and set Rx mode. Chip must be in idle state to 1133 * access RXCON. 1134 */ 1135 static void 1136 epic_set_rx_mode(epic_softc_t *sc) 1137 { 1138 u_int32_t flags = sc->sc_if.if_flags; 1139 u_int32_t rxcon = RXCON_DEFAULT; 1140 1141 #if defined(EPIC_EARLY_RX) 1142 rxcon |= RXCON_EARLY_RX; 1143 #endif 1144 1145 rxcon |= (flags & IFF_PROMISC) ? RXCON_PROMISCUOUS_MODE : 0; 1146 1147 CSR_WRITE_4(sc, RXCON, rxcon); 1148 1149 return; 1150 } 1151 1152 /* 1153 * Synopsis: Set transmit control register. Chip must be in idle state to 1154 * access TXCON. 1155 */ 1156 static void 1157 epic_set_tx_mode(epic_softc_t *sc) 1158 { 1159 if (sc->txcon & TXCON_EARLY_TRANSMIT_ENABLE) 1160 CSR_WRITE_4(sc, ETXTHR, sc->tx_threshold); 1161 1162 CSR_WRITE_4(sc, TXCON, sc->txcon); 1163 } 1164 1165 /* 1166 * Synopsis: Program multicast filter honoring IFF_ALLMULTI and IFF_PROMISC 1167 * flags. (Note, that setting PROMISC bit in EPIC's RXCON will only touch 1168 * individual frames, multicast filter must be manually programmed) 1169 * 1170 * Note: EPIC must be in idle state. 1171 */ 1172 static void 1173 epic_set_mc_table(epic_softc_t *sc) 1174 { 1175 struct ifnet *ifp = &sc->sc_if; 1176 struct ifmultiaddr *ifma; 1177 u_int16_t filter[4]; 1178 u_int8_t h; 1179 1180 if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) { 1181 CSR_WRITE_4(sc, MC0, 0xFFFF); 1182 CSR_WRITE_4(sc, MC1, 0xFFFF); 1183 CSR_WRITE_4(sc, MC2, 0xFFFF); 1184 CSR_WRITE_4(sc, MC3, 0xFFFF); 1185 1186 return; 1187 } 1188 1189 filter[0] = 0; 1190 filter[1] = 0; 1191 filter[2] = 0; 1192 filter[3] = 0; 1193 1194 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1195 if (ifma->ifma_addr->sa_family != AF_LINK) 1196 continue; 1197 h = (ether_crc32_be( 1198 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 1199 ETHER_ADDR_LEN) >> 26) & 0x3f; 1200 filter[h >> 4] |= 1 << (h & 0xF); 1201 } 1202 1203 CSR_WRITE_4(sc, MC0, filter[0]); 1204 CSR_WRITE_4(sc, MC1, filter[1]); 1205 CSR_WRITE_4(sc, MC2, filter[2]); 1206 CSR_WRITE_4(sc, MC3, filter[3]); 1207 1208 return; 1209 } 1210 1211 /* 1212 * Synopsis: Start receive process and transmit one, if they need. 1213 */ 1214 static void 1215 epic_start_activity(epic_softc_t *sc) 1216 { 1217 /* Start rx process */ 1218 CSR_WRITE_4(sc, COMMAND, 1219 COMMAND_RXQUEUED | COMMAND_START_RX | 1220 (sc->pending_txs?COMMAND_TXQUEUED:0)); 1221 } 1222 1223 /* 1224 * Synopsis: Completely stop Rx and Tx processes. If TQE is set additional 1225 * packet needs to be queued to stop Tx DMA. 1226 */ 1227 static void 1228 epic_stop_activity(epic_softc_t *sc) 1229 { 1230 int status, i; 1231 1232 /* Stop Tx and Rx DMA */ 1233 CSR_WRITE_4(sc, COMMAND, 1234 COMMAND_STOP_RX | COMMAND_STOP_RDMA | COMMAND_STOP_TDMA); 1235 1236 /* Wait Rx and Tx DMA to stop (why 1 ms ??? XXX) */ 1237 for (i=0; i<0x1000; i++) { 1238 status = CSR_READ_4(sc, INTSTAT) & (INTSTAT_TXIDLE | INTSTAT_RXIDLE); 1239 if (status == (INTSTAT_TXIDLE | INTSTAT_RXIDLE)) 1240 break; 1241 DELAY(1); 1242 } 1243 1244 /* Catch all finished packets */ 1245 epic_rx_done(sc); 1246 epic_tx_done(sc); 1247 1248 status = CSR_READ_4(sc, INTSTAT); 1249 1250 if ((status & INTSTAT_RXIDLE) == 0) 1251 if_printf(&sc->sc_if, "ERROR! Can't stop Rx DMA\n"); 1252 1253 if ((status & INTSTAT_TXIDLE) == 0) 1254 if_printf(&sc->sc_if, "ERROR! Can't stop Tx DMA\n"); 1255 1256 /* 1257 * May need to queue one more packet if TQE, this is rare 1258 * but existing case. 1259 */ 1260 if ((status & INTSTAT_TQE) && !(status & INTSTAT_TXIDLE)) 1261 epic_queue_last_packet(sc); 1262 1263 } 1264 1265 /* 1266 * The EPIC transmitter may stuck in TQE state. It will not go IDLE until 1267 * a packet from current descriptor will be copied to internal RAM. We 1268 * compose a dummy packet here and queue it for transmission. 1269 * 1270 * XXX the packet will then be actually sent over network... 1271 */ 1272 static int 1273 epic_queue_last_packet(epic_softc_t *sc) 1274 { 1275 struct epic_tx_desc *desc; 1276 struct epic_frag_list *flist; 1277 struct epic_tx_buffer *buf; 1278 struct mbuf *m0; 1279 int i; 1280 1281 if_printf(&sc->sc_if, "queue last packet\n"); 1282 1283 desc = sc->tx_desc + sc->cur_tx; 1284 flist = sc->tx_flist + sc->cur_tx; 1285 buf = sc->tx_buffer + sc->cur_tx; 1286 1287 if ((desc->status & 0x8000) || (buf->mbuf != NULL)) 1288 return (EBUSY); 1289 1290 MGETHDR(m0, MB_DONTWAIT, MT_DATA); 1291 if (NULL == m0) 1292 return (ENOBUFS); 1293 1294 /* Prepare mbuf */ 1295 m0->m_len = min(MHLEN, ETHER_MIN_LEN-ETHER_CRC_LEN); 1296 flist->frag[0].fraglen = m0->m_len; 1297 m0->m_pkthdr.len = m0->m_len; 1298 m0->m_pkthdr.rcvif = &sc->sc_if; 1299 bzero(mtod(m0,caddr_t), m0->m_len); 1300 1301 /* Fill fragments list */ 1302 flist->frag[0].fraglen = m0->m_len; 1303 flist->frag[0].fragaddr = vtophys(mtod(m0, caddr_t)); 1304 flist->numfrags = 1; 1305 1306 /* Fill in descriptor */ 1307 buf->mbuf = m0; 1308 sc->pending_txs++; 1309 sc->cur_tx = (sc->cur_tx + 1) & TX_RING_MASK; 1310 desc->control = 0x01; 1311 desc->txlength = max(m0->m_pkthdr.len,ETHER_MIN_LEN-ETHER_CRC_LEN); 1312 desc->status = 0x8000; 1313 1314 /* Launch transmition */ 1315 CSR_WRITE_4(sc, COMMAND, COMMAND_STOP_TDMA | COMMAND_TXQUEUED); 1316 1317 /* Wait Tx DMA to stop (for how long??? XXX) */ 1318 for (i=0; i<1000; i++) { 1319 if (CSR_READ_4(sc, INTSTAT) & INTSTAT_TXIDLE) 1320 break; 1321 DELAY(1); 1322 } 1323 1324 if ((CSR_READ_4(sc, INTSTAT) & INTSTAT_TXIDLE) == 0) 1325 if_printf(&sc->sc_if, "ERROR! can't stop Tx DMA (2)\n"); 1326 else 1327 epic_tx_done(sc); 1328 1329 return 0; 1330 } 1331 1332 /* 1333 * Synopsis: Shut down board and deallocates rings. 1334 */ 1335 static void 1336 epic_stop(epic_softc_t *sc) 1337 { 1338 sc->sc_if.if_timer = 0; 1339 1340 callout_stop(&sc->tx_stat_timer); 1341 1342 /* Disable interrupts */ 1343 CSR_WRITE_4(sc, INTMASK, 0); 1344 CSR_WRITE_4(sc, GENCTL, 0); 1345 1346 /* Try to stop Rx and TX processes */ 1347 epic_stop_activity(sc); 1348 1349 /* Reset chip */ 1350 CSR_WRITE_4(sc, GENCTL, GENCTL_SOFT_RESET); 1351 DELAY(1000); 1352 1353 /* Make chip go to bed */ 1354 CSR_WRITE_4(sc, GENCTL, GENCTL_POWER_DOWN); 1355 1356 /* Free memory allocated for rings */ 1357 epic_free_rings(sc); 1358 1359 /* Mark as stoped */ 1360 sc->sc_if.if_flags &= ~IFF_RUNNING; 1361 } 1362 1363 /* 1364 * Synopsis: This function should free all memory allocated for rings. 1365 */ 1366 static void 1367 epic_free_rings(epic_softc_t *sc) 1368 { 1369 int i; 1370 1371 for (i=0; i<RX_RING_SIZE; i++) { 1372 struct epic_rx_buffer *buf = sc->rx_buffer + i; 1373 struct epic_rx_desc *desc = sc->rx_desc + i; 1374 1375 desc->status = 0; 1376 desc->buflength = 0; 1377 desc->bufaddr = 0; 1378 1379 if (buf->mbuf) m_freem(buf->mbuf); 1380 buf->mbuf = NULL; 1381 } 1382 1383 for (i=0; i<TX_RING_SIZE; i++) { 1384 struct epic_tx_buffer *buf = sc->tx_buffer + i; 1385 struct epic_tx_desc *desc = sc->tx_desc + i; 1386 1387 desc->status = 0; 1388 desc->buflength = 0; 1389 desc->bufaddr = 0; 1390 1391 if (buf->mbuf) m_freem(buf->mbuf); 1392 buf->mbuf = NULL; 1393 } 1394 } 1395 1396 /* 1397 * Synopsis: Allocates mbufs for Rx ring and point Rx descs to them. 1398 * Point Tx descs to fragment lists. Check that all descs and fraglists 1399 * are bounded and aligned properly. 1400 */ 1401 static int 1402 epic_init_rings(epic_softc_t *sc) 1403 { 1404 int i; 1405 1406 sc->cur_rx = sc->cur_tx = sc->dirty_tx = sc->pending_txs = 0; 1407 1408 for (i = 0; i < RX_RING_SIZE; i++) { 1409 struct epic_rx_buffer *buf = sc->rx_buffer + i; 1410 struct epic_rx_desc *desc = sc->rx_desc + i; 1411 1412 desc->status = 0; /* Owned by driver */ 1413 desc->next = vtophys(sc->rx_desc + ((i+1) & RX_RING_MASK)); 1414 1415 if ((desc->next & 3) || 1416 ((desc->next & PAGE_MASK) + sizeof *desc) > PAGE_SIZE) { 1417 epic_free_rings(sc); 1418 return EFAULT; 1419 } 1420 1421 buf->mbuf = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR); 1422 if (NULL == buf->mbuf) { 1423 epic_free_rings(sc); 1424 return ENOBUFS; 1425 } 1426 desc->bufaddr = vtophys(mtod(buf->mbuf, caddr_t)); 1427 1428 desc->buflength = MCLBYTES; /* Max RX buffer length */ 1429 desc->status = 0x8000; /* Set owner bit to NIC */ 1430 } 1431 1432 for (i = 0; i < TX_RING_SIZE; i++) { 1433 struct epic_tx_buffer *buf = sc->tx_buffer + i; 1434 struct epic_tx_desc *desc = sc->tx_desc + i; 1435 1436 desc->status = 0; 1437 desc->next = vtophys(sc->tx_desc + ((i+1) & TX_RING_MASK)); 1438 1439 if ((desc->next & 3) || 1440 ((desc->next & PAGE_MASK) + sizeof *desc) > PAGE_SIZE) { 1441 epic_free_rings(sc); 1442 return EFAULT; 1443 } 1444 1445 buf->mbuf = NULL; 1446 desc->bufaddr = vtophys(sc->tx_flist + i); 1447 1448 if ((desc->bufaddr & 3) || 1449 ((desc->bufaddr & PAGE_MASK) + sizeof(struct epic_frag_list)) > PAGE_SIZE) { 1450 epic_free_rings(sc); 1451 return EFAULT; 1452 } 1453 } 1454 1455 return 0; 1456 } 1457 1458 /* 1459 * EEPROM operation functions 1460 */ 1461 static void 1462 epic_write_eepromreg(epic_softc_t *sc, u_int8_t val) 1463 { 1464 u_int16_t i; 1465 1466 CSR_WRITE_1(sc, EECTL, val); 1467 1468 for (i=0; i<0xFF; i++) 1469 if ((CSR_READ_1(sc, EECTL) & 0x20) == 0) break; 1470 1471 return; 1472 } 1473 1474 static u_int8_t 1475 epic_read_eepromreg(epic_softc_t *sc) 1476 { 1477 return CSR_READ_1(sc, EECTL); 1478 } 1479 1480 static u_int8_t 1481 epic_eeprom_clock(epic_softc_t *sc, u_int8_t val) 1482 { 1483 epic_write_eepromreg(sc, val); 1484 epic_write_eepromreg(sc, (val | 0x4)); 1485 epic_write_eepromreg(sc, val); 1486 1487 return epic_read_eepromreg(sc); 1488 } 1489 1490 static void 1491 epic_output_eepromw(epic_softc_t *sc, u_int16_t val) 1492 { 1493 int i; 1494 1495 for (i = 0xF; i >= 0; i--) { 1496 if (val & (1 << i)) 1497 epic_eeprom_clock(sc, 0x0B); 1498 else 1499 epic_eeprom_clock(sc, 0x03); 1500 } 1501 } 1502 1503 static u_int16_t 1504 epic_input_eepromw(epic_softc_t *sc) 1505 { 1506 u_int16_t retval = 0; 1507 int i; 1508 1509 for (i = 0xF; i >= 0; i--) { 1510 if (epic_eeprom_clock(sc, 0x3) & 0x10) 1511 retval |= (1 << i); 1512 } 1513 1514 return retval; 1515 } 1516 1517 static int 1518 epic_read_eeprom(epic_softc_t *sc, u_int16_t loc) 1519 { 1520 u_int16_t dataval; 1521 u_int16_t read_cmd; 1522 1523 epic_write_eepromreg(sc, 3); 1524 1525 if (epic_read_eepromreg(sc) & 0x40) 1526 read_cmd = (loc & 0x3F) | 0x180; 1527 else 1528 read_cmd = (loc & 0xFF) | 0x600; 1529 1530 epic_output_eepromw(sc, read_cmd); 1531 1532 dataval = epic_input_eepromw(sc); 1533 1534 epic_write_eepromreg(sc, 1); 1535 1536 return dataval; 1537 } 1538 1539 /* 1540 * Here goes MII read/write routines 1541 */ 1542 static int 1543 epic_read_phy_reg(epic_softc_t *sc, int phy, int reg) 1544 { 1545 int i; 1546 1547 CSR_WRITE_4(sc, MIICTL, ((reg << 4) | (phy << 9) | 0x01)); 1548 1549 for (i = 0; i < 0x100; i++) { 1550 if ((CSR_READ_4(sc, MIICTL) & 0x01) == 0) break; 1551 DELAY(1); 1552 } 1553 1554 return (CSR_READ_4(sc, MIIDATA)); 1555 } 1556 1557 static void 1558 epic_write_phy_reg(epic_softc_t *sc, int phy, int reg, int val) 1559 { 1560 int i; 1561 1562 CSR_WRITE_4(sc, MIIDATA, val); 1563 CSR_WRITE_4(sc, MIICTL, ((reg << 4) | (phy << 9) | 0x02)); 1564 1565 for(i=0;i<0x100;i++) { 1566 if ((CSR_READ_4(sc, MIICTL) & 0x02) == 0) break; 1567 DELAY(1); 1568 } 1569 1570 return; 1571 } 1572 1573 static int 1574 epic_miibus_readreg(device_t dev, int phy, int reg) 1575 { 1576 epic_softc_t *sc; 1577 1578 sc = device_get_softc(dev); 1579 1580 return (PHY_READ_2(sc, phy, reg)); 1581 } 1582 1583 static int 1584 epic_miibus_writereg(device_t dev, int phy, int reg, int data) 1585 { 1586 epic_softc_t *sc; 1587 1588 sc = device_get_softc(dev); 1589 1590 PHY_WRITE_2(sc, phy, reg, data); 1591 1592 return (0); 1593 } 1594