1 /* $OpenBSD: if_txp.c,v 1.48 2001/06/27 06:34:50 kjc Exp $ */ 2 /* $FreeBSD: src/sys/dev/txp/if_txp.c,v 1.4.2.4 2001/12/14 19:50:43 jlemon Exp $ */ 3 /* $DragonFly: src/sys/dev/netif/txp/if_txp.c,v 1.37 2006/08/03 16:40:47 swildner Exp $ */ 4 5 /* 6 * Copyright (c) 2001 7 * Jason L. Wright <jason@thought.net>, Theo de Raadt, and 8 * Aaron Campbell <aaron@monkey.org>. All rights reserved. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by Jason L. Wright, 21 * Theo de Raadt and Aaron Campbell. 22 * 4. Neither the name of the author nor the names of any co-contributors 23 * may be used to endorse or promote products derived from this software 24 * without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR 27 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 28 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 29 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 36 * THE POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Driver for 3c990 (Typhoon) Ethernet ASIC 41 */ 42 43 #include <sys/param.h> 44 #include <sys/systm.h> 45 #include <sys/sockio.h> 46 #include <sys/mbuf.h> 47 #include <sys/malloc.h> 48 #include <sys/kernel.h> 49 #include <sys/socket.h> 50 #include <sys/serialize.h> 51 #include <sys/thread2.h> 52 53 #include <net/if.h> 54 #include <net/ifq_var.h> 55 #include <net/if_arp.h> 56 #include <net/ethernet.h> 57 #include <net/if_dl.h> 58 #include <net/if_types.h> 59 #include <net/vlan/if_vlan_var.h> 60 61 #include <netinet/in.h> 62 #include <netinet/in_systm.h> 63 #include <netinet/in_var.h> 64 #include <netinet/ip.h> 65 #include <netinet/if_ether.h> 66 #include <sys/in_cksum.h> 67 68 #include <net/if_media.h> 69 70 #include <net/bpf.h> 71 72 #include <vm/vm.h> /* for vtophys */ 73 #include <vm/pmap.h> /* for vtophys */ 74 #include <machine/bus_pio.h> 75 #include <machine/bus_memio.h> 76 #include <machine/bus.h> 77 #include <machine/resource.h> 78 #include <sys/bus.h> 79 #include <sys/rman.h> 80 81 #include "../mii_layer/mii.h" 82 #include "../mii_layer/miivar.h" 83 84 #include <bus/pci/pcidevs.h> 85 #include <bus/pci/pcireg.h> 86 #include <bus/pci/pcivar.h> 87 88 #define TXP_USEIOSPACE 89 #define __STRICT_ALIGNMENT 90 91 #include "if_txpreg.h" 92 #include "3c990img.h" 93 94 /* 95 * Various supported device vendors/types and their names. 96 */ 97 static struct txp_type txp_devs[] = { 98 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990TX95, 99 "3Com 3cR990-TX-95 Etherlink with 3XP Processor" }, 100 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990TX97, 101 "3Com 3cR990-TX-97 Etherlink with 3XP Processor" }, 102 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C990B, 103 "3Com 3cR990B-TXM Etherlink with 3XP Processor" }, 104 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990SVR95, 105 "3Com 3cR990-SRV-95 Etherlink Server with 3XP Processor" }, 106 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990SVR97, 107 "3Com 3cR990-SRV-97 Etherlink Server with 3XP Processor" }, 108 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C990BSVR, 109 "3Com 3cR990B-SRV Etherlink Server with 3XP Processor" }, 110 { 0, 0, NULL } 111 }; 112 113 static int txp_probe (device_t); 114 static int txp_attach (device_t); 115 static int txp_detach (device_t); 116 static void txp_intr (void *); 117 static void txp_tick (void *); 118 static int txp_shutdown (device_t); 119 static int txp_ioctl (struct ifnet *, u_long, caddr_t, struct ucred *); 120 static void txp_start (struct ifnet *); 121 static void txp_stop (struct txp_softc *); 122 static void txp_init (void *); 123 static void txp_watchdog (struct ifnet *); 124 125 static void txp_release_resources (device_t); 126 static int txp_chip_init (struct txp_softc *); 127 static int txp_reset_adapter (struct txp_softc *); 128 static int txp_download_fw (struct txp_softc *); 129 static int txp_download_fw_wait (struct txp_softc *); 130 static int txp_download_fw_section (struct txp_softc *, 131 struct txp_fw_section_header *, int); 132 static int txp_alloc_rings (struct txp_softc *); 133 static int txp_rxring_fill (struct txp_softc *); 134 static void txp_rxring_empty (struct txp_softc *); 135 static void txp_set_filter (struct txp_softc *); 136 137 static int txp_cmd_desc_numfree (struct txp_softc *); 138 static int txp_command (struct txp_softc *, u_int16_t, u_int16_t, u_int32_t, 139 u_int32_t, u_int16_t *, u_int32_t *, u_int32_t *, int); 140 static int txp_command2 (struct txp_softc *, u_int16_t, u_int16_t, 141 u_int32_t, u_int32_t, struct txp_ext_desc *, u_int8_t, 142 struct txp_rsp_desc **, int); 143 static int txp_response (struct txp_softc *, u_int32_t, u_int16_t, u_int16_t, 144 struct txp_rsp_desc **); 145 static void txp_rsp_fixup (struct txp_softc *, struct txp_rsp_desc *, 146 struct txp_rsp_desc *); 147 static void txp_capabilities (struct txp_softc *); 148 149 static void txp_ifmedia_sts (struct ifnet *, struct ifmediareq *); 150 static int txp_ifmedia_upd (struct ifnet *); 151 #ifdef TXP_DEBUG 152 static void txp_show_descriptor (void *); 153 #endif 154 static void txp_tx_reclaim (struct txp_softc *, struct txp_tx_ring *); 155 static void txp_rxbuf_reclaim (struct txp_softc *); 156 static void txp_rx_reclaim (struct txp_softc *, struct txp_rx_ring *); 157 158 #ifdef TXP_USEIOSPACE 159 #define TXP_RES SYS_RES_IOPORT 160 #define TXP_RID TXP_PCI_LOIO 161 #else 162 #define TXP_RES SYS_RES_MEMORY 163 #define TXP_RID TXP_PCI_LOMEM 164 #endif 165 166 static device_method_t txp_methods[] = { 167 /* Device interface */ 168 DEVMETHOD(device_probe, txp_probe), 169 DEVMETHOD(device_attach, txp_attach), 170 DEVMETHOD(device_detach, txp_detach), 171 DEVMETHOD(device_shutdown, txp_shutdown), 172 { 0, 0 } 173 }; 174 175 static driver_t txp_driver = { 176 "txp", 177 txp_methods, 178 sizeof(struct txp_softc) 179 }; 180 181 static devclass_t txp_devclass; 182 183 DECLARE_DUMMY_MODULE(if_txp); 184 DRIVER_MODULE(if_txp, pci, txp_driver, txp_devclass, 0, 0); 185 186 static int 187 txp_probe(device_t dev) 188 { 189 struct txp_type *t; 190 uint16_t vid, did; 191 192 vid = pci_get_vendor(dev); 193 did = pci_get_device(dev); 194 195 for (t = txp_devs; t->txp_name != NULL; ++t) { 196 if ((vid == t->txp_vid) && (did == t->txp_did)) { 197 device_set_desc(dev, t->txp_name); 198 return(0); 199 } 200 } 201 202 return(ENXIO); 203 } 204 205 static int 206 txp_attach(device_t dev) 207 { 208 struct txp_softc *sc; 209 struct ifnet *ifp; 210 uint16_t p1; 211 uint32_t p2; 212 uint8_t enaddr[ETHER_ADDR_LEN]; 213 int error = 0, rid; 214 215 sc = device_get_softc(dev); 216 callout_init(&sc->txp_stat_timer); 217 218 ifp = &sc->sc_arpcom.ac_if; 219 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 220 221 pci_enable_busmaster(dev); 222 223 rid = TXP_RID; 224 sc->sc_res = bus_alloc_resource_any(dev, TXP_RES, &rid, RF_ACTIVE); 225 226 if (sc->sc_res == NULL) { 227 device_printf(dev, "couldn't map ports/memory\n"); 228 return(ENXIO); 229 } 230 231 sc->sc_bt = rman_get_bustag(sc->sc_res); 232 sc->sc_bh = rman_get_bushandle(sc->sc_res); 233 234 /* Allocate interrupt */ 235 rid = 0; 236 sc->sc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 237 RF_SHAREABLE | RF_ACTIVE); 238 239 if (sc->sc_irq == NULL) { 240 device_printf(dev, "couldn't map interrupt\n"); 241 error = ENXIO; 242 goto fail; 243 } 244 245 if (txp_chip_init(sc)) { 246 error = ENXIO; 247 goto fail; 248 } 249 250 sc->sc_fwbuf = contigmalloc(32768, M_DEVBUF, 251 M_WAITOK, 0, 0xffffffff, PAGE_SIZE, 0); 252 error = txp_download_fw(sc); 253 contigfree(sc->sc_fwbuf, 32768, M_DEVBUF); 254 sc->sc_fwbuf = NULL; 255 256 if (error) 257 goto fail; 258 259 sc->sc_ldata = contigmalloc(sizeof(struct txp_ldata), M_DEVBUF, 260 M_WAITOK, 0, 0xffffffff, PAGE_SIZE, 0); 261 bzero(sc->sc_ldata, sizeof(struct txp_ldata)); 262 263 if (txp_alloc_rings(sc)) { 264 error = ENXIO; 265 goto fail; 266 } 267 268 if (txp_command(sc, TXP_CMD_MAX_PKT_SIZE_WRITE, TXP_MAX_PKTLEN, 0, 0, 269 NULL, NULL, NULL, 1)) { 270 error = ENXIO; 271 goto fail; 272 } 273 274 if (txp_command(sc, TXP_CMD_STATION_ADDRESS_READ, 0, 0, 0, 275 &p1, &p2, NULL, 1)) { 276 error = ENXIO; 277 goto fail; 278 } 279 280 txp_set_filter(sc); 281 282 enaddr[0] = ((uint8_t *)&p1)[1]; 283 enaddr[1] = ((uint8_t *)&p1)[0]; 284 enaddr[2] = ((uint8_t *)&p2)[3]; 285 enaddr[3] = ((uint8_t *)&p2)[2]; 286 enaddr[4] = ((uint8_t *)&p2)[1]; 287 enaddr[5] = ((uint8_t *)&p2)[0]; 288 289 ifmedia_init(&sc->sc_ifmedia, 0, txp_ifmedia_upd, txp_ifmedia_sts); 290 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_10_T, 0, NULL); 291 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_10_T|IFM_HDX, 0, NULL); 292 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL); 293 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_100_TX, 0, NULL); 294 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_100_TX|IFM_HDX, 0, NULL); 295 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_100_TX|IFM_FDX, 0, NULL); 296 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 297 298 sc->sc_xcvr = TXP_XCVR_AUTO; 299 txp_command(sc, TXP_CMD_XCVR_SELECT, TXP_XCVR_AUTO, 0, 0, 300 NULL, NULL, NULL, 0); 301 ifmedia_set(&sc->sc_ifmedia, IFM_ETHER|IFM_AUTO); 302 303 ifp->if_softc = sc; 304 ifp->if_mtu = ETHERMTU; 305 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 306 ifp->if_ioctl = txp_ioctl; 307 ifp->if_start = txp_start; 308 ifp->if_watchdog = txp_watchdog; 309 ifp->if_init = txp_init; 310 ifp->if_baudrate = 100000000; 311 ifq_set_maxlen(&ifp->if_snd, TX_ENTRIES); 312 ifq_set_ready(&ifp->if_snd); 313 ifp->if_hwassist = 0; 314 txp_capabilities(sc); 315 316 ether_ifattach(ifp, enaddr, NULL); 317 318 error = bus_setup_intr(dev, sc->sc_irq, INTR_NETSAFE, 319 txp_intr, sc, &sc->sc_intrhand, 320 ifp->if_serializer); 321 if (error) { 322 device_printf(dev, "couldn't set up irq\n"); 323 ether_ifdetach(ifp); 324 goto fail; 325 } 326 327 return(0); 328 329 fail: 330 txp_release_resources(dev); 331 return(error); 332 } 333 334 static int 335 txp_detach(device_t dev) 336 { 337 struct txp_softc *sc = device_get_softc(dev); 338 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 339 int i; 340 341 lwkt_serialize_enter(ifp->if_serializer); 342 343 txp_stop(sc); 344 txp_shutdown(dev); 345 bus_teardown_intr(dev, sc->sc_irq, sc->sc_intrhand); 346 347 lwkt_serialize_exit(ifp->if_serializer); 348 349 ifmedia_removeall(&sc->sc_ifmedia); 350 ether_ifdetach(ifp); 351 352 for (i = 0; i < RXBUF_ENTRIES; i++) 353 free(sc->sc_rxbufs[i].rb_sd, M_DEVBUF); 354 355 txp_release_resources(dev); 356 357 return(0); 358 } 359 360 static void 361 txp_release_resources(device_t dev) 362 { 363 struct txp_softc *sc; 364 365 sc = device_get_softc(dev); 366 367 if (sc->sc_irq != NULL) 368 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq); 369 370 if (sc->sc_res != NULL) 371 bus_release_resource(dev, TXP_RES, TXP_RID, sc->sc_res); 372 373 if (sc->sc_ldata != NULL) 374 contigfree(sc->sc_ldata, sizeof(struct txp_ldata), M_DEVBUF); 375 376 return; 377 } 378 379 static int 380 txp_chip_init(struct txp_softc *sc) 381 { 382 /* disable interrupts */ 383 WRITE_REG(sc, TXP_IER, 0); 384 WRITE_REG(sc, TXP_IMR, 385 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 386 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 387 TXP_INT_LATCH); 388 389 /* ack all interrupts */ 390 WRITE_REG(sc, TXP_ISR, TXP_INT_RESERVED | TXP_INT_LATCH | 391 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 | 392 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 393 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 394 TXP_INT_A2H_3 | TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0); 395 396 if (txp_reset_adapter(sc)) 397 return (-1); 398 399 /* disable interrupts */ 400 WRITE_REG(sc, TXP_IER, 0); 401 WRITE_REG(sc, TXP_IMR, 402 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 403 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 404 TXP_INT_LATCH); 405 406 /* ack all interrupts */ 407 WRITE_REG(sc, TXP_ISR, TXP_INT_RESERVED | TXP_INT_LATCH | 408 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 | 409 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 410 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 411 TXP_INT_A2H_3 | TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0); 412 413 return (0); 414 } 415 416 static int 417 txp_reset_adapter(struct txp_softc *sc) 418 { 419 u_int32_t r; 420 int i; 421 422 WRITE_REG(sc, TXP_SRR, TXP_SRR_ALL); 423 DELAY(1000); 424 WRITE_REG(sc, TXP_SRR, 0); 425 426 /* Should wait max 6 seconds */ 427 for (i = 0; i < 6000; i++) { 428 r = READ_REG(sc, TXP_A2H_0); 429 if (r == STAT_WAITING_FOR_HOST_REQUEST) 430 break; 431 DELAY(1000); 432 } 433 434 if (r != STAT_WAITING_FOR_HOST_REQUEST) { 435 if_printf(&sc->sc_arpcom.ac_if, "reset hung\n"); 436 return (-1); 437 } 438 439 return (0); 440 } 441 442 static int 443 txp_download_fw(struct txp_softc *sc) 444 { 445 struct txp_fw_file_header *fileheader; 446 struct txp_fw_section_header *secthead; 447 int sect; 448 u_int32_t r, i, ier, imr; 449 450 ier = READ_REG(sc, TXP_IER); 451 WRITE_REG(sc, TXP_IER, ier | TXP_INT_A2H_0); 452 453 imr = READ_REG(sc, TXP_IMR); 454 WRITE_REG(sc, TXP_IMR, imr | TXP_INT_A2H_0); 455 456 for (i = 0; i < 10000; i++) { 457 r = READ_REG(sc, TXP_A2H_0); 458 if (r == STAT_WAITING_FOR_HOST_REQUEST) 459 break; 460 DELAY(50); 461 } 462 if (r != STAT_WAITING_FOR_HOST_REQUEST) { 463 if_printf(&sc->sc_arpcom.ac_if, 464 "not waiting for host request\n"); 465 return (-1); 466 } 467 468 /* Ack the status */ 469 WRITE_REG(sc, TXP_ISR, TXP_INT_A2H_0); 470 471 fileheader = (struct txp_fw_file_header *)tc990image; 472 if (bcmp("TYPHOON", fileheader->magicid, sizeof(fileheader->magicid))) { 473 if_printf(&sc->sc_arpcom.ac_if, "fw invalid magic\n"); 474 return (-1); 475 } 476 477 /* Tell boot firmware to get ready for image */ 478 WRITE_REG(sc, TXP_H2A_1, fileheader->addr); 479 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_RUNTIME_IMAGE); 480 481 if (txp_download_fw_wait(sc)) { 482 if_printf(&sc->sc_arpcom.ac_if, "fw wait failed, initial\n"); 483 return (-1); 484 } 485 486 secthead = (struct txp_fw_section_header *)(((u_int8_t *)tc990image) + 487 sizeof(struct txp_fw_file_header)); 488 489 for (sect = 0; sect < fileheader->nsections; sect++) { 490 if (txp_download_fw_section(sc, secthead, sect)) 491 return (-1); 492 secthead = (struct txp_fw_section_header *) 493 (((u_int8_t *)secthead) + secthead->nbytes + 494 sizeof(*secthead)); 495 } 496 497 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_DOWNLOAD_COMPLETE); 498 499 for (i = 0; i < 10000; i++) { 500 r = READ_REG(sc, TXP_A2H_0); 501 if (r == STAT_WAITING_FOR_BOOT) 502 break; 503 DELAY(50); 504 } 505 if (r != STAT_WAITING_FOR_BOOT) { 506 if_printf(&sc->sc_arpcom.ac_if, "not waiting for boot\n"); 507 return (-1); 508 } 509 510 WRITE_REG(sc, TXP_IER, ier); 511 WRITE_REG(sc, TXP_IMR, imr); 512 513 return (0); 514 } 515 516 static int 517 txp_download_fw_wait(struct txp_softc *sc) 518 { 519 u_int32_t i, r; 520 521 for (i = 0; i < 10000; i++) { 522 r = READ_REG(sc, TXP_ISR); 523 if (r & TXP_INT_A2H_0) 524 break; 525 DELAY(50); 526 } 527 528 if (!(r & TXP_INT_A2H_0)) { 529 if_printf(&sc->sc_arpcom.ac_if, "fw wait failed comm0\n"); 530 return (-1); 531 } 532 533 WRITE_REG(sc, TXP_ISR, TXP_INT_A2H_0); 534 535 r = READ_REG(sc, TXP_A2H_0); 536 if (r != STAT_WAITING_FOR_SEGMENT) { 537 if_printf(&sc->sc_arpcom.ac_if, "fw not waiting for segment\n"); 538 return (-1); 539 } 540 return (0); 541 } 542 543 static int 544 txp_download_fw_section(struct txp_softc *sc, 545 struct txp_fw_section_header *sect, int sectnum) 546 { 547 vm_offset_t dma; 548 int rseg, err = 0; 549 struct mbuf m; 550 u_int16_t csum; 551 552 /* Skip zero length sections */ 553 if (sect->nbytes == 0) 554 return (0); 555 556 /* Make sure we aren't past the end of the image */ 557 rseg = ((u_int8_t *)sect) - ((u_int8_t *)tc990image); 558 if (rseg >= sizeof(tc990image)) { 559 if_printf(&sc->sc_arpcom.ac_if, "fw invalid section address, " 560 "section %d\n", sectnum); 561 return (-1); 562 } 563 564 /* Make sure this section doesn't go past the end */ 565 rseg += sect->nbytes; 566 if (rseg >= sizeof(tc990image)) { 567 if_printf(&sc->sc_arpcom.ac_if, "fw truncated section %d\n", 568 sectnum); 569 return (-1); 570 } 571 572 bcopy(((u_int8_t *)sect) + sizeof(*sect), sc->sc_fwbuf, sect->nbytes); 573 dma = vtophys(sc->sc_fwbuf); 574 575 /* 576 * dummy up mbuf and verify section checksum 577 */ 578 m.m_type = MT_DATA; 579 m.m_next = m.m_nextpkt = NULL; 580 m.m_len = sect->nbytes; 581 m.m_data = sc->sc_fwbuf; 582 m.m_flags = 0; 583 csum = in_cksum(&m, sect->nbytes); 584 if (csum != sect->cksum) { 585 if_printf(&sc->sc_arpcom.ac_if, "fw section %d, bad " 586 "cksum (expected 0x%x got 0x%x)\n", 587 sectnum, sect->cksum, csum); 588 err = -1; 589 goto bail; 590 } 591 592 WRITE_REG(sc, TXP_H2A_1, sect->nbytes); 593 WRITE_REG(sc, TXP_H2A_2, sect->cksum); 594 WRITE_REG(sc, TXP_H2A_3, sect->addr); 595 WRITE_REG(sc, TXP_H2A_4, 0); 596 WRITE_REG(sc, TXP_H2A_5, dma & 0xffffffff); 597 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_SEGMENT_AVAILABLE); 598 599 if (txp_download_fw_wait(sc)) { 600 if_printf(&sc->sc_arpcom.ac_if, "fw wait failed, " 601 "section %d\n", sectnum); 602 err = -1; 603 } 604 605 bail: 606 return (err); 607 } 608 609 static void 610 txp_intr(void *vsc) 611 { 612 struct txp_softc *sc = vsc; 613 struct txp_hostvar *hv = sc->sc_hostvar; 614 u_int32_t isr; 615 616 /* mask all interrupts */ 617 WRITE_REG(sc, TXP_IMR, TXP_INT_RESERVED | TXP_INT_SELF | 618 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 | 619 TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0 | 620 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 621 TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | TXP_INT_LATCH); 622 623 isr = READ_REG(sc, TXP_ISR); 624 while (isr) { 625 WRITE_REG(sc, TXP_ISR, isr); 626 627 if ((*sc->sc_rxhir.r_roff) != (*sc->sc_rxhir.r_woff)) 628 txp_rx_reclaim(sc, &sc->sc_rxhir); 629 if ((*sc->sc_rxlor.r_roff) != (*sc->sc_rxlor.r_woff)) 630 txp_rx_reclaim(sc, &sc->sc_rxlor); 631 632 if (hv->hv_rx_buf_write_idx == hv->hv_rx_buf_read_idx) 633 txp_rxbuf_reclaim(sc); 634 635 if (sc->sc_txhir.r_cnt && (sc->sc_txhir.r_cons != 636 TXP_OFFSET2IDX(*(sc->sc_txhir.r_off)))) 637 txp_tx_reclaim(sc, &sc->sc_txhir); 638 639 if (sc->sc_txlor.r_cnt && (sc->sc_txlor.r_cons != 640 TXP_OFFSET2IDX(*(sc->sc_txlor.r_off)))) 641 txp_tx_reclaim(sc, &sc->sc_txlor); 642 643 isr = READ_REG(sc, TXP_ISR); 644 } 645 646 /* unmask all interrupts */ 647 WRITE_REG(sc, TXP_IMR, TXP_INT_A2H_3); 648 649 txp_start(&sc->sc_arpcom.ac_if); 650 651 return; 652 } 653 654 static void 655 txp_rx_reclaim(struct txp_softc *sc, struct txp_rx_ring *r) 656 { 657 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 658 struct txp_rx_desc *rxd; 659 struct mbuf *m; 660 struct txp_swdesc *sd = NULL; 661 u_int32_t roff, woff; 662 663 roff = *r->r_roff; 664 woff = *r->r_woff; 665 rxd = r->r_desc + (roff / sizeof(struct txp_rx_desc)); 666 667 while (roff != woff) { 668 669 if (rxd->rx_flags & RX_FLAGS_ERROR) { 670 if_printf(ifp, "error 0x%x\n", rxd->rx_stat); 671 ifp->if_ierrors++; 672 goto next; 673 } 674 675 /* retrieve stashed pointer */ 676 sd = rxd->rx_sd; 677 678 m = sd->sd_mbuf; 679 sd->sd_mbuf = NULL; 680 681 m->m_pkthdr.len = m->m_len = rxd->rx_len; 682 683 #ifdef __STRICT_ALIGNMENT 684 { 685 /* 686 * XXX Nice chip, except it won't accept "off by 2" 687 * buffers, so we're force to copy. Supposedly 688 * this will be fixed in a newer firmware rev 689 * and this will be temporary. 690 */ 691 struct mbuf *mnew; 692 693 MGETHDR(mnew, MB_DONTWAIT, MT_DATA); 694 if (mnew == NULL) { 695 m_freem(m); 696 goto next; 697 } 698 if (m->m_len > (MHLEN - 2)) { 699 MCLGET(mnew, MB_DONTWAIT); 700 if (!(mnew->m_flags & M_EXT)) { 701 m_freem(mnew); 702 m_freem(m); 703 goto next; 704 } 705 } 706 mnew->m_pkthdr.rcvif = ifp; 707 m_adj(mnew, 2); 708 mnew->m_pkthdr.len = mnew->m_len = m->m_len; 709 m_copydata(m, 0, m->m_pkthdr.len, mtod(mnew, caddr_t)); 710 m_freem(m); 711 m = mnew; 712 } 713 #endif 714 715 if (rxd->rx_stat & RX_STAT_IPCKSUMBAD) 716 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 717 else if (rxd->rx_stat & RX_STAT_IPCKSUMGOOD) 718 m->m_pkthdr.csum_flags |= 719 CSUM_IP_CHECKED|CSUM_IP_VALID; 720 721 if ((rxd->rx_stat & RX_STAT_TCPCKSUMGOOD) || 722 (rxd->rx_stat & RX_STAT_UDPCKSUMGOOD)) { 723 m->m_pkthdr.csum_flags |= 724 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 725 m->m_pkthdr.csum_data = 0xffff; 726 } 727 728 lwkt_serialize_enter(ifp->if_serializer); 729 if (rxd->rx_stat & RX_STAT_VLAN) 730 VLAN_INPUT_TAG(m, htons(rxd->rx_vlan >> 16)); 731 else 732 ifp->if_input(ifp, m); 733 lwkt_serialize_exit(ifp->if_serializer); 734 735 next: 736 737 roff += sizeof(struct txp_rx_desc); 738 if (roff == (RX_ENTRIES * sizeof(struct txp_rx_desc))) { 739 roff = 0; 740 rxd = r->r_desc; 741 } else 742 rxd++; 743 woff = *r->r_woff; 744 } 745 746 *r->r_roff = woff; 747 748 return; 749 } 750 751 static void 752 txp_rxbuf_reclaim(struct txp_softc *sc) 753 { 754 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 755 struct txp_hostvar *hv = sc->sc_hostvar; 756 struct txp_rxbuf_desc *rbd; 757 struct txp_swdesc *sd; 758 u_int32_t i; 759 760 if (!(ifp->if_flags & IFF_RUNNING)) 761 return; 762 763 i = sc->sc_rxbufprod; 764 rbd = sc->sc_rxbufs + i; 765 766 while (1) { 767 sd = rbd->rb_sd; 768 if (sd->sd_mbuf != NULL) 769 break; 770 771 MGETHDR(sd->sd_mbuf, MB_DONTWAIT, MT_DATA); 772 if (sd->sd_mbuf == NULL) 773 goto err_sd; 774 775 MCLGET(sd->sd_mbuf, MB_DONTWAIT); 776 if ((sd->sd_mbuf->m_flags & M_EXT) == 0) 777 goto err_mbuf; 778 sd->sd_mbuf->m_pkthdr.rcvif = ifp; 779 sd->sd_mbuf->m_pkthdr.len = sd->sd_mbuf->m_len = MCLBYTES; 780 781 rbd->rb_paddrlo = vtophys(mtod(sd->sd_mbuf, vm_offset_t)) 782 & 0xffffffff; 783 rbd->rb_paddrhi = 0; 784 785 hv->hv_rx_buf_write_idx = TXP_IDX2OFFSET(i); 786 787 if (++i == RXBUF_ENTRIES) { 788 i = 0; 789 rbd = sc->sc_rxbufs; 790 } else 791 rbd++; 792 } 793 794 sc->sc_rxbufprod = i; 795 796 return; 797 798 err_mbuf: 799 m_freem(sd->sd_mbuf); 800 err_sd: 801 free(sd, M_DEVBUF); 802 } 803 804 /* 805 * Reclaim mbufs and entries from a transmit ring. 806 */ 807 static void 808 txp_tx_reclaim(struct txp_softc *sc, struct txp_tx_ring *r) 809 { 810 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 811 u_int32_t idx = TXP_OFFSET2IDX(*(r->r_off)); 812 u_int32_t cons = r->r_cons, cnt = r->r_cnt; 813 struct txp_tx_desc *txd = r->r_desc + cons; 814 struct txp_swdesc *sd = sc->sc_txd + cons; 815 struct mbuf *m; 816 817 while (cons != idx) { 818 if (cnt == 0) 819 break; 820 821 if ((txd->tx_flags & TX_FLAGS_TYPE_M) == 822 TX_FLAGS_TYPE_DATA) { 823 m = sd->sd_mbuf; 824 if (m != NULL) { 825 m_freem(m); 826 txd->tx_addrlo = 0; 827 txd->tx_addrhi = 0; 828 ifp->if_opackets++; 829 } 830 } 831 ifp->if_flags &= ~IFF_OACTIVE; 832 833 if (++cons == TX_ENTRIES) { 834 txd = r->r_desc; 835 cons = 0; 836 sd = sc->sc_txd; 837 } else { 838 txd++; 839 sd++; 840 } 841 842 cnt--; 843 } 844 845 r->r_cons = cons; 846 r->r_cnt = cnt; 847 if (cnt == 0) 848 ifp->if_timer = 0; 849 } 850 851 static int 852 txp_shutdown(device_t dev) 853 { 854 struct txp_softc *sc; 855 struct ifnet *ifp; 856 857 sc = device_get_softc(dev); 858 ifp = &sc->sc_arpcom.ac_if; 859 lwkt_serialize_enter(ifp->if_serializer); 860 861 /* mask all interrupts */ 862 WRITE_REG(sc, TXP_IMR, 863 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 864 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 865 TXP_INT_LATCH); 866 867 txp_command(sc, TXP_CMD_TX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 0); 868 txp_command(sc, TXP_CMD_RX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 0); 869 txp_command(sc, TXP_CMD_HALT, 0, 0, 0, NULL, NULL, NULL, 0); 870 871 lwkt_serialize_exit(ifp->if_serializer); 872 return(0); 873 } 874 875 static int 876 txp_alloc_rings(struct txp_softc *sc) 877 { 878 struct txp_boot_record *boot; 879 struct txp_ldata *ld; 880 u_int32_t r; 881 int i; 882 883 ld = sc->sc_ldata; 884 boot = &ld->txp_boot; 885 886 /* boot record */ 887 sc->sc_boot = boot; 888 889 /* host variables */ 890 bzero(&ld->txp_hostvar, sizeof(struct txp_hostvar)); 891 boot->br_hostvar_lo = vtophys(&ld->txp_hostvar); 892 boot->br_hostvar_hi = 0; 893 sc->sc_hostvar = (struct txp_hostvar *)&ld->txp_hostvar; 894 895 /* hi priority tx ring */ 896 boot->br_txhipri_lo = vtophys(&ld->txp_txhiring); 897 boot->br_txhipri_hi = 0; 898 boot->br_txhipri_siz = TX_ENTRIES * sizeof(struct txp_tx_desc); 899 sc->sc_txhir.r_reg = TXP_H2A_1; 900 sc->sc_txhir.r_desc = (struct txp_tx_desc *)&ld->txp_txhiring; 901 sc->sc_txhir.r_cons = sc->sc_txhir.r_prod = sc->sc_txhir.r_cnt = 0; 902 sc->sc_txhir.r_off = &sc->sc_hostvar->hv_tx_hi_desc_read_idx; 903 904 /* lo priority tx ring */ 905 boot->br_txlopri_lo = vtophys(&ld->txp_txloring); 906 boot->br_txlopri_hi = 0; 907 boot->br_txlopri_siz = TX_ENTRIES * sizeof(struct txp_tx_desc); 908 sc->sc_txlor.r_reg = TXP_H2A_3; 909 sc->sc_txlor.r_desc = (struct txp_tx_desc *)&ld->txp_txloring; 910 sc->sc_txlor.r_cons = sc->sc_txlor.r_prod = sc->sc_txlor.r_cnt = 0; 911 sc->sc_txlor.r_off = &sc->sc_hostvar->hv_tx_lo_desc_read_idx; 912 913 /* high priority rx ring */ 914 boot->br_rxhipri_lo = vtophys(&ld->txp_rxhiring); 915 boot->br_rxhipri_hi = 0; 916 boot->br_rxhipri_siz = RX_ENTRIES * sizeof(struct txp_rx_desc); 917 sc->sc_rxhir.r_desc = (struct txp_rx_desc *)&ld->txp_rxhiring; 918 sc->sc_rxhir.r_roff = &sc->sc_hostvar->hv_rx_hi_read_idx; 919 sc->sc_rxhir.r_woff = &sc->sc_hostvar->hv_rx_hi_write_idx; 920 921 /* low priority rx ring */ 922 boot->br_rxlopri_lo = vtophys(&ld->txp_rxloring); 923 boot->br_rxlopri_hi = 0; 924 boot->br_rxlopri_siz = RX_ENTRIES * sizeof(struct txp_rx_desc); 925 sc->sc_rxlor.r_desc = (struct txp_rx_desc *)&ld->txp_rxloring; 926 sc->sc_rxlor.r_roff = &sc->sc_hostvar->hv_rx_lo_read_idx; 927 sc->sc_rxlor.r_woff = &sc->sc_hostvar->hv_rx_lo_write_idx; 928 929 /* command ring */ 930 bzero(&ld->txp_cmdring, sizeof(struct txp_cmd_desc) * CMD_ENTRIES); 931 boot->br_cmd_lo = vtophys(&ld->txp_cmdring); 932 boot->br_cmd_hi = 0; 933 boot->br_cmd_siz = CMD_ENTRIES * sizeof(struct txp_cmd_desc); 934 sc->sc_cmdring.base = (struct txp_cmd_desc *)&ld->txp_cmdring; 935 sc->sc_cmdring.size = CMD_ENTRIES * sizeof(struct txp_cmd_desc); 936 sc->sc_cmdring.lastwrite = 0; 937 938 /* response ring */ 939 bzero(&ld->txp_rspring, sizeof(struct txp_rsp_desc) * RSP_ENTRIES); 940 boot->br_resp_lo = vtophys(&ld->txp_rspring); 941 boot->br_resp_hi = 0; 942 boot->br_resp_siz = CMD_ENTRIES * sizeof(struct txp_rsp_desc); 943 sc->sc_rspring.base = (struct txp_rsp_desc *)&ld->txp_rspring; 944 sc->sc_rspring.size = RSP_ENTRIES * sizeof(struct txp_rsp_desc); 945 sc->sc_rspring.lastwrite = 0; 946 947 /* receive buffer ring */ 948 boot->br_rxbuf_lo = vtophys(&ld->txp_rxbufs); 949 boot->br_rxbuf_hi = 0; 950 boot->br_rxbuf_siz = RXBUF_ENTRIES * sizeof(struct txp_rxbuf_desc); 951 sc->sc_rxbufs = (struct txp_rxbuf_desc *)&ld->txp_rxbufs; 952 953 for (i = 0; i < RXBUF_ENTRIES; i++) { 954 struct txp_swdesc *sd; 955 if (sc->sc_rxbufs[i].rb_sd != NULL) 956 continue; 957 sc->sc_rxbufs[i].rb_sd = malloc(sizeof(struct txp_swdesc), 958 M_DEVBUF, M_WAITOK); 959 if (sc->sc_rxbufs[i].rb_sd == NULL) 960 return(ENOBUFS); 961 sd = sc->sc_rxbufs[i].rb_sd; 962 sd->sd_mbuf = NULL; 963 } 964 sc->sc_rxbufprod = 0; 965 966 /* zero dma */ 967 bzero(&ld->txp_zero, sizeof(u_int32_t)); 968 boot->br_zero_lo = vtophys(&ld->txp_zero); 969 boot->br_zero_hi = 0; 970 971 /* See if it's waiting for boot, and try to boot it */ 972 for (i = 0; i < 10000; i++) { 973 r = READ_REG(sc, TXP_A2H_0); 974 if (r == STAT_WAITING_FOR_BOOT) 975 break; 976 DELAY(50); 977 } 978 979 if (r != STAT_WAITING_FOR_BOOT) { 980 if_printf(&sc->sc_arpcom.ac_if, "not waiting for boot\n"); 981 return(ENXIO); 982 } 983 984 WRITE_REG(sc, TXP_H2A_2, 0); 985 WRITE_REG(sc, TXP_H2A_1, vtophys(sc->sc_boot)); 986 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_REGISTER_BOOT_RECORD); 987 988 /* See if it booted */ 989 for (i = 0; i < 10000; i++) { 990 r = READ_REG(sc, TXP_A2H_0); 991 if (r == STAT_RUNNING) 992 break; 993 DELAY(50); 994 } 995 if (r != STAT_RUNNING) { 996 if_printf(&sc->sc_arpcom.ac_if, "fw not running\n"); 997 return(ENXIO); 998 } 999 1000 /* Clear TX and CMD ring write registers */ 1001 WRITE_REG(sc, TXP_H2A_1, TXP_BOOTCMD_NULL); 1002 WRITE_REG(sc, TXP_H2A_2, TXP_BOOTCMD_NULL); 1003 WRITE_REG(sc, TXP_H2A_3, TXP_BOOTCMD_NULL); 1004 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_NULL); 1005 1006 return (0); 1007 } 1008 1009 static int 1010 txp_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr) 1011 { 1012 struct txp_softc *sc = ifp->if_softc; 1013 struct ifreq *ifr = (struct ifreq *)data; 1014 int error = 0; 1015 1016 switch(command) { 1017 case SIOCSIFFLAGS: 1018 if (ifp->if_flags & IFF_UP) { 1019 txp_init(sc); 1020 } else { 1021 if (ifp->if_flags & IFF_RUNNING) 1022 txp_stop(sc); 1023 } 1024 break; 1025 case SIOCADDMULTI: 1026 case SIOCDELMULTI: 1027 /* 1028 * Multicast list has changed; set the hardware 1029 * filter accordingly. 1030 */ 1031 txp_set_filter(sc); 1032 error = 0; 1033 break; 1034 case SIOCGIFMEDIA: 1035 case SIOCSIFMEDIA: 1036 error = ifmedia_ioctl(ifp, ifr, &sc->sc_ifmedia, command); 1037 break; 1038 default: 1039 error = ether_ioctl(ifp, command, data); 1040 break; 1041 } 1042 return(error); 1043 } 1044 1045 static int 1046 txp_rxring_fill(struct txp_softc *sc) 1047 { 1048 int i; 1049 struct ifnet *ifp; 1050 struct txp_swdesc *sd; 1051 1052 ifp = &sc->sc_arpcom.ac_if; 1053 1054 for (i = 0; i < RXBUF_ENTRIES; i++) { 1055 sd = sc->sc_rxbufs[i].rb_sd; 1056 MGETHDR(sd->sd_mbuf, MB_DONTWAIT, MT_DATA); 1057 if (sd->sd_mbuf == NULL) 1058 return(ENOBUFS); 1059 1060 MCLGET(sd->sd_mbuf, MB_DONTWAIT); 1061 if ((sd->sd_mbuf->m_flags & M_EXT) == 0) { 1062 m_freem(sd->sd_mbuf); 1063 return(ENOBUFS); 1064 } 1065 sd->sd_mbuf->m_pkthdr.len = sd->sd_mbuf->m_len = MCLBYTES; 1066 sd->sd_mbuf->m_pkthdr.rcvif = ifp; 1067 1068 sc->sc_rxbufs[i].rb_paddrlo = 1069 vtophys(mtod(sd->sd_mbuf, vm_offset_t)); 1070 sc->sc_rxbufs[i].rb_paddrhi = 0; 1071 } 1072 1073 sc->sc_hostvar->hv_rx_buf_write_idx = (RXBUF_ENTRIES - 1) * 1074 sizeof(struct txp_rxbuf_desc); 1075 1076 return(0); 1077 } 1078 1079 static void 1080 txp_rxring_empty(struct txp_softc *sc) 1081 { 1082 int i; 1083 struct txp_swdesc *sd; 1084 1085 if (sc->sc_rxbufs == NULL) 1086 return; 1087 1088 for (i = 0; i < RXBUF_ENTRIES; i++) { 1089 if (&sc->sc_rxbufs[i] == NULL) 1090 continue; 1091 sd = sc->sc_rxbufs[i].rb_sd; 1092 if (sd == NULL) 1093 continue; 1094 if (sd->sd_mbuf != NULL) { 1095 m_freem(sd->sd_mbuf); 1096 sd->sd_mbuf = NULL; 1097 } 1098 } 1099 1100 return; 1101 } 1102 1103 static void 1104 txp_init(void *xsc) 1105 { 1106 struct txp_softc *sc; 1107 struct ifnet *ifp; 1108 u_int16_t p1; 1109 u_int32_t p2; 1110 1111 sc = xsc; 1112 ifp = &sc->sc_arpcom.ac_if; 1113 1114 if (ifp->if_flags & IFF_RUNNING) 1115 return; 1116 1117 txp_stop(sc); 1118 1119 txp_command(sc, TXP_CMD_MAX_PKT_SIZE_WRITE, TXP_MAX_PKTLEN, 0, 0, 1120 NULL, NULL, NULL, 1); 1121 1122 /* Set station address. */ 1123 ((u_int8_t *)&p1)[1] = sc->sc_arpcom.ac_enaddr[0]; 1124 ((u_int8_t *)&p1)[0] = sc->sc_arpcom.ac_enaddr[1]; 1125 ((u_int8_t *)&p2)[3] = sc->sc_arpcom.ac_enaddr[2]; 1126 ((u_int8_t *)&p2)[2] = sc->sc_arpcom.ac_enaddr[3]; 1127 ((u_int8_t *)&p2)[1] = sc->sc_arpcom.ac_enaddr[4]; 1128 ((u_int8_t *)&p2)[0] = sc->sc_arpcom.ac_enaddr[5]; 1129 txp_command(sc, TXP_CMD_STATION_ADDRESS_WRITE, p1, p2, 0, 1130 NULL, NULL, NULL, 1); 1131 1132 txp_set_filter(sc); 1133 1134 txp_rxring_fill(sc); 1135 1136 txp_command(sc, TXP_CMD_TX_ENABLE, 0, 0, 0, NULL, NULL, NULL, 1); 1137 txp_command(sc, TXP_CMD_RX_ENABLE, 0, 0, 0, NULL, NULL, NULL, 1); 1138 1139 WRITE_REG(sc, TXP_IER, TXP_INT_RESERVED | TXP_INT_SELF | 1140 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 | 1141 TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0 | 1142 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 1143 TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | TXP_INT_LATCH); 1144 WRITE_REG(sc, TXP_IMR, TXP_INT_A2H_3); 1145 1146 ifp->if_flags |= IFF_RUNNING; 1147 ifp->if_flags &= ~IFF_OACTIVE; 1148 ifp->if_timer = 0; 1149 1150 callout_reset(&sc->txp_stat_timer, hz, txp_tick, sc); 1151 } 1152 1153 static void 1154 txp_tick(void *vsc) 1155 { 1156 struct txp_softc *sc = vsc; 1157 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1158 struct txp_rsp_desc *rsp = NULL; 1159 struct txp_ext_desc *ext; 1160 1161 lwkt_serialize_enter(ifp->if_serializer); 1162 txp_rxbuf_reclaim(sc); 1163 1164 if (txp_command2(sc, TXP_CMD_READ_STATISTICS, 0, 0, 0, NULL, 0, 1165 &rsp, 1)) 1166 goto out; 1167 if (rsp->rsp_numdesc != 6) 1168 goto out; 1169 if (txp_command(sc, TXP_CMD_CLEAR_STATISTICS, 0, 0, 0, 1170 NULL, NULL, NULL, 1)) 1171 goto out; 1172 ext = (struct txp_ext_desc *)(rsp + 1); 1173 1174 ifp->if_ierrors += ext[3].ext_2 + ext[3].ext_3 + ext[3].ext_4 + 1175 ext[4].ext_1 + ext[4].ext_4; 1176 ifp->if_oerrors += ext[0].ext_1 + ext[1].ext_1 + ext[1].ext_4 + 1177 ext[2].ext_1; 1178 ifp->if_collisions += ext[0].ext_2 + ext[0].ext_3 + ext[1].ext_2 + 1179 ext[1].ext_3; 1180 ifp->if_opackets += rsp->rsp_par2; 1181 ifp->if_ipackets += ext[2].ext_3; 1182 1183 out: 1184 if (rsp != NULL) 1185 free(rsp, M_DEVBUF); 1186 1187 callout_reset(&sc->txp_stat_timer, hz, txp_tick, sc); 1188 lwkt_serialize_exit(ifp->if_serializer); 1189 } 1190 1191 static void 1192 txp_start(struct ifnet *ifp) 1193 { 1194 struct txp_softc *sc = ifp->if_softc; 1195 struct txp_tx_ring *r = &sc->sc_txhir; 1196 struct txp_tx_desc *txd; 1197 struct txp_frag_desc *fxd; 1198 struct mbuf *m, *m0; 1199 struct txp_swdesc *sd; 1200 u_int32_t firstprod, firstcnt, prod, cnt; 1201 struct ifvlan *ifv; 1202 1203 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1204 return; 1205 1206 prod = r->r_prod; 1207 cnt = r->r_cnt; 1208 1209 while (1) { 1210 m = ifq_poll(&ifp->if_snd); 1211 if (m == NULL) 1212 break; 1213 1214 firstprod = prod; 1215 firstcnt = cnt; 1216 1217 sd = sc->sc_txd + prod; 1218 sd->sd_mbuf = m; 1219 1220 if ((TX_ENTRIES - cnt) < 4) 1221 goto oactive; 1222 1223 txd = r->r_desc + prod; 1224 1225 txd->tx_flags = TX_FLAGS_TYPE_DATA; 1226 txd->tx_numdesc = 0; 1227 txd->tx_addrlo = 0; 1228 txd->tx_addrhi = 0; 1229 txd->tx_totlen = 0; 1230 txd->tx_pflags = 0; 1231 1232 if (++prod == TX_ENTRIES) 1233 prod = 0; 1234 1235 if (++cnt >= (TX_ENTRIES - 4)) 1236 goto oactive; 1237 1238 if ((m->m_flags & (M_PROTO1|M_PKTHDR)) == (M_PROTO1|M_PKTHDR) && 1239 m->m_pkthdr.rcvif != NULL) { 1240 ifv = m->m_pkthdr.rcvif->if_softc; 1241 txd->tx_pflags = TX_PFLAGS_VLAN | 1242 (htons(ifv->ifv_tag) << TX_PFLAGS_VLANTAG_S); 1243 } 1244 1245 if (m->m_pkthdr.csum_flags & CSUM_IP) 1246 txd->tx_pflags |= TX_PFLAGS_IPCKSUM; 1247 1248 #if 0 1249 if (m->m_pkthdr.csum_flags & CSUM_TCP) 1250 txd->tx_pflags |= TX_PFLAGS_TCPCKSUM; 1251 if (m->m_pkthdr.csum_flags & CSUM_UDP) 1252 txd->tx_pflags |= TX_PFLAGS_UDPCKSUM; 1253 #endif 1254 1255 fxd = (struct txp_frag_desc *)(r->r_desc + prod); 1256 for (m0 = m; m0 != NULL; m0 = m0->m_next) { 1257 if (m0->m_len == 0) 1258 continue; 1259 if (++cnt >= (TX_ENTRIES - 4)) 1260 goto oactive; 1261 1262 txd->tx_numdesc++; 1263 1264 fxd->frag_flags = FRAG_FLAGS_TYPE_FRAG; 1265 fxd->frag_rsvd1 = 0; 1266 fxd->frag_len = m0->m_len; 1267 fxd->frag_addrlo = vtophys(mtod(m0, vm_offset_t)); 1268 fxd->frag_addrhi = 0; 1269 fxd->frag_rsvd2 = 0; 1270 1271 if (++prod == TX_ENTRIES) { 1272 fxd = (struct txp_frag_desc *)r->r_desc; 1273 prod = 0; 1274 } else 1275 fxd++; 1276 1277 } 1278 1279 ifp->if_timer = 5; 1280 1281 ifq_dequeue(&ifp->if_snd, m); 1282 BPF_MTAP(ifp, m); 1283 WRITE_REG(sc, r->r_reg, TXP_IDX2OFFSET(prod)); 1284 } 1285 1286 r->r_prod = prod; 1287 r->r_cnt = cnt; 1288 return; 1289 1290 oactive: 1291 ifp->if_flags |= IFF_OACTIVE; 1292 r->r_prod = firstprod; 1293 r->r_cnt = firstcnt; 1294 return; 1295 } 1296 1297 /* 1298 * Handle simple commands sent to the typhoon 1299 */ 1300 static int 1301 txp_command(struct txp_softc *sc, u_int16_t id, u_int16_t in1, u_int32_t in2, 1302 u_int32_t in3, u_int16_t *out1, u_int32_t *out2, u_int32_t *out3, 1303 int wait) 1304 { 1305 struct txp_rsp_desc *rsp = NULL; 1306 1307 if (txp_command2(sc, id, in1, in2, in3, NULL, 0, &rsp, wait)) 1308 return (-1); 1309 1310 if (!wait) 1311 return (0); 1312 1313 if (out1 != NULL) 1314 *out1 = rsp->rsp_par1; 1315 if (out2 != NULL) 1316 *out2 = rsp->rsp_par2; 1317 if (out3 != NULL) 1318 *out3 = rsp->rsp_par3; 1319 free(rsp, M_DEVBUF); 1320 return (0); 1321 } 1322 1323 static int 1324 txp_command2(struct txp_softc *sc, u_int16_t id, u_int16_t in1, u_int32_t in2, 1325 u_int32_t in3, struct txp_ext_desc *in_extp, u_int8_t in_extn, 1326 struct txp_rsp_desc **rspp, int wait) 1327 { 1328 struct txp_hostvar *hv = sc->sc_hostvar; 1329 struct txp_cmd_desc *cmd; 1330 struct txp_ext_desc *ext; 1331 u_int32_t idx, i; 1332 u_int16_t seq; 1333 1334 if (txp_cmd_desc_numfree(sc) < (in_extn + 1)) { 1335 if_printf(&sc->sc_arpcom.ac_if, "no free cmd descriptors\n"); 1336 return (-1); 1337 } 1338 1339 idx = sc->sc_cmdring.lastwrite; 1340 cmd = (struct txp_cmd_desc *)(((u_int8_t *)sc->sc_cmdring.base) + idx); 1341 bzero(cmd, sizeof(*cmd)); 1342 1343 cmd->cmd_numdesc = in_extn; 1344 cmd->cmd_seq = seq = sc->sc_seq++; 1345 cmd->cmd_id = id; 1346 cmd->cmd_par1 = in1; 1347 cmd->cmd_par2 = in2; 1348 cmd->cmd_par3 = in3; 1349 cmd->cmd_flags = CMD_FLAGS_TYPE_CMD | 1350 (wait ? CMD_FLAGS_RESP : 0) | CMD_FLAGS_VALID; 1351 1352 idx += sizeof(struct txp_cmd_desc); 1353 if (idx == sc->sc_cmdring.size) 1354 idx = 0; 1355 1356 for (i = 0; i < in_extn; i++) { 1357 ext = (struct txp_ext_desc *)(((u_int8_t *)sc->sc_cmdring.base) + idx); 1358 bcopy(in_extp, ext, sizeof(struct txp_ext_desc)); 1359 in_extp++; 1360 idx += sizeof(struct txp_cmd_desc); 1361 if (idx == sc->sc_cmdring.size) 1362 idx = 0; 1363 } 1364 1365 sc->sc_cmdring.lastwrite = idx; 1366 1367 WRITE_REG(sc, TXP_H2A_2, sc->sc_cmdring.lastwrite); 1368 1369 if (!wait) 1370 return (0); 1371 1372 for (i = 0; i < 10000; i++) { 1373 idx = hv->hv_resp_read_idx; 1374 if (idx != hv->hv_resp_write_idx) { 1375 *rspp = NULL; 1376 if (txp_response(sc, idx, id, seq, rspp)) 1377 return (-1); 1378 if (*rspp != NULL) 1379 break; 1380 } 1381 DELAY(50); 1382 } 1383 if (i == 1000 || (*rspp) == NULL) { 1384 if_printf(&sc->sc_arpcom.ac_if, "0x%x command failed\n", id); 1385 return (-1); 1386 } 1387 1388 return (0); 1389 } 1390 1391 static int 1392 txp_response(struct txp_softc *sc, u_int32_t ridx, u_int16_t id, u_int16_t seq, 1393 struct txp_rsp_desc **rspp) 1394 { 1395 struct txp_hostvar *hv = sc->sc_hostvar; 1396 struct txp_rsp_desc *rsp; 1397 1398 while (ridx != hv->hv_resp_write_idx) { 1399 rsp = (struct txp_rsp_desc *)(((u_int8_t *)sc->sc_rspring.base) + ridx); 1400 1401 if (id == rsp->rsp_id && rsp->rsp_seq == seq) { 1402 *rspp = (struct txp_rsp_desc *)malloc( 1403 sizeof(struct txp_rsp_desc) * (rsp->rsp_numdesc + 1), 1404 M_DEVBUF, M_INTWAIT); 1405 if ((*rspp) == NULL) 1406 return (-1); 1407 txp_rsp_fixup(sc, rsp, *rspp); 1408 return (0); 1409 } 1410 1411 if (rsp->rsp_flags & RSP_FLAGS_ERROR) { 1412 if_printf(&sc->sc_arpcom.ac_if, "response error!\n"); 1413 txp_rsp_fixup(sc, rsp, NULL); 1414 ridx = hv->hv_resp_read_idx; 1415 continue; 1416 } 1417 1418 switch (rsp->rsp_id) { 1419 case TXP_CMD_CYCLE_STATISTICS: 1420 case TXP_CMD_MEDIA_STATUS_READ: 1421 break; 1422 case TXP_CMD_HELLO_RESPONSE: 1423 if_printf(&sc->sc_arpcom.ac_if, "hello\n"); 1424 break; 1425 default: 1426 if_printf(&sc->sc_arpcom.ac_if, "unknown id(0x%x)\n", 1427 rsp->rsp_id); 1428 } 1429 1430 txp_rsp_fixup(sc, rsp, NULL); 1431 ridx = hv->hv_resp_read_idx; 1432 hv->hv_resp_read_idx = ridx; 1433 } 1434 1435 return (0); 1436 } 1437 1438 static void 1439 txp_rsp_fixup(struct txp_softc *sc, struct txp_rsp_desc *rsp, 1440 struct txp_rsp_desc *dst) 1441 { 1442 struct txp_rsp_desc *src = rsp; 1443 struct txp_hostvar *hv = sc->sc_hostvar; 1444 u_int32_t i, ridx; 1445 1446 ridx = hv->hv_resp_read_idx; 1447 1448 for (i = 0; i < rsp->rsp_numdesc + 1; i++) { 1449 if (dst != NULL) 1450 bcopy(src, dst++, sizeof(struct txp_rsp_desc)); 1451 ridx += sizeof(struct txp_rsp_desc); 1452 if (ridx == sc->sc_rspring.size) { 1453 src = sc->sc_rspring.base; 1454 ridx = 0; 1455 } else 1456 src++; 1457 sc->sc_rspring.lastwrite = hv->hv_resp_read_idx = ridx; 1458 } 1459 1460 hv->hv_resp_read_idx = ridx; 1461 } 1462 1463 static int 1464 txp_cmd_desc_numfree(struct txp_softc *sc) 1465 { 1466 struct txp_hostvar *hv = sc->sc_hostvar; 1467 struct txp_boot_record *br = sc->sc_boot; 1468 u_int32_t widx, ridx, nfree; 1469 1470 widx = sc->sc_cmdring.lastwrite; 1471 ridx = hv->hv_cmd_read_idx; 1472 1473 if (widx == ridx) { 1474 /* Ring is completely free */ 1475 nfree = br->br_cmd_siz - sizeof(struct txp_cmd_desc); 1476 } else { 1477 if (widx > ridx) 1478 nfree = br->br_cmd_siz - 1479 (widx - ridx + sizeof(struct txp_cmd_desc)); 1480 else 1481 nfree = ridx - widx - sizeof(struct txp_cmd_desc); 1482 } 1483 1484 return (nfree / sizeof(struct txp_cmd_desc)); 1485 } 1486 1487 static void 1488 txp_stop(struct txp_softc *sc) 1489 { 1490 struct ifnet *ifp; 1491 1492 ifp = &sc->sc_arpcom.ac_if; 1493 1494 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1495 1496 callout_stop(&sc->txp_stat_timer); 1497 1498 txp_command(sc, TXP_CMD_TX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 1); 1499 txp_command(sc, TXP_CMD_RX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 1); 1500 1501 txp_rxring_empty(sc); 1502 1503 return; 1504 } 1505 1506 static void 1507 txp_watchdog(struct ifnet *ifp) 1508 { 1509 return; 1510 } 1511 1512 static int 1513 txp_ifmedia_upd(struct ifnet *ifp) 1514 { 1515 struct txp_softc *sc = ifp->if_softc; 1516 struct ifmedia *ifm = &sc->sc_ifmedia; 1517 u_int16_t new_xcvr; 1518 1519 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 1520 return (EINVAL); 1521 1522 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_10_T) { 1523 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1524 new_xcvr = TXP_XCVR_10_FDX; 1525 else 1526 new_xcvr = TXP_XCVR_10_HDX; 1527 } else if (IFM_SUBTYPE(ifm->ifm_media) == IFM_100_TX) { 1528 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1529 new_xcvr = TXP_XCVR_100_FDX; 1530 else 1531 new_xcvr = TXP_XCVR_100_HDX; 1532 } else if (IFM_SUBTYPE(ifm->ifm_media) == IFM_AUTO) { 1533 new_xcvr = TXP_XCVR_AUTO; 1534 } else 1535 return (EINVAL); 1536 1537 /* nothing to do */ 1538 if (sc->sc_xcvr == new_xcvr) 1539 return (0); 1540 1541 txp_command(sc, TXP_CMD_XCVR_SELECT, new_xcvr, 0, 0, 1542 NULL, NULL, NULL, 0); 1543 sc->sc_xcvr = new_xcvr; 1544 1545 return (0); 1546 } 1547 1548 static void 1549 txp_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1550 { 1551 struct txp_softc *sc = ifp->if_softc; 1552 struct ifmedia *ifm = &sc->sc_ifmedia; 1553 u_int16_t bmsr, bmcr, anlpar; 1554 1555 ifmr->ifm_status = IFM_AVALID; 1556 ifmr->ifm_active = IFM_ETHER; 1557 1558 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_BMSR, 0, 1559 &bmsr, NULL, NULL, 1)) 1560 goto bail; 1561 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_BMSR, 0, 1562 &bmsr, NULL, NULL, 1)) 1563 goto bail; 1564 1565 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_BMCR, 0, 1566 &bmcr, NULL, NULL, 1)) 1567 goto bail; 1568 1569 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_ANLPAR, 0, 1570 &anlpar, NULL, NULL, 1)) 1571 goto bail; 1572 1573 if (bmsr & BMSR_LINK) 1574 ifmr->ifm_status |= IFM_ACTIVE; 1575 1576 if (bmcr & BMCR_ISO) { 1577 ifmr->ifm_active |= IFM_NONE; 1578 ifmr->ifm_status = 0; 1579 return; 1580 } 1581 1582 if (bmcr & BMCR_LOOP) 1583 ifmr->ifm_active |= IFM_LOOP; 1584 1585 if (bmcr & BMCR_AUTOEN) { 1586 if ((bmsr & BMSR_ACOMP) == 0) { 1587 ifmr->ifm_active |= IFM_NONE; 1588 return; 1589 } 1590 1591 if (anlpar & ANLPAR_T4) 1592 ifmr->ifm_active |= IFM_100_T4; 1593 else if (anlpar & ANLPAR_TX_FD) 1594 ifmr->ifm_active |= IFM_100_TX|IFM_FDX; 1595 else if (anlpar & ANLPAR_TX) 1596 ifmr->ifm_active |= IFM_100_TX; 1597 else if (anlpar & ANLPAR_10_FD) 1598 ifmr->ifm_active |= IFM_10_T|IFM_FDX; 1599 else if (anlpar & ANLPAR_10) 1600 ifmr->ifm_active |= IFM_10_T; 1601 else 1602 ifmr->ifm_active |= IFM_NONE; 1603 } else 1604 ifmr->ifm_active = ifm->ifm_cur->ifm_media; 1605 return; 1606 1607 bail: 1608 ifmr->ifm_active |= IFM_NONE; 1609 ifmr->ifm_status &= ~IFM_AVALID; 1610 } 1611 1612 #ifdef TXP_DEBUG 1613 static void 1614 txp_show_descriptor(void *d) 1615 { 1616 struct txp_cmd_desc *cmd = d; 1617 struct txp_rsp_desc *rsp = d; 1618 struct txp_tx_desc *txd = d; 1619 struct txp_frag_desc *frgd = d; 1620 1621 switch (cmd->cmd_flags & CMD_FLAGS_TYPE_M) { 1622 case CMD_FLAGS_TYPE_CMD: 1623 /* command descriptor */ 1624 printf("[cmd flags 0x%x num %d id %d seq %d par1 0x%x par2 0x%x par3 0x%x]\n", 1625 cmd->cmd_flags, cmd->cmd_numdesc, cmd->cmd_id, cmd->cmd_seq, 1626 cmd->cmd_par1, cmd->cmd_par2, cmd->cmd_par3); 1627 break; 1628 case CMD_FLAGS_TYPE_RESP: 1629 /* response descriptor */ 1630 printf("[rsp flags 0x%x num %d id %d seq %d par1 0x%x par2 0x%x par3 0x%x]\n", 1631 rsp->rsp_flags, rsp->rsp_numdesc, rsp->rsp_id, rsp->rsp_seq, 1632 rsp->rsp_par1, rsp->rsp_par2, rsp->rsp_par3); 1633 break; 1634 case CMD_FLAGS_TYPE_DATA: 1635 /* data header (assuming tx for now) */ 1636 printf("[data flags 0x%x num %d totlen %d addr 0x%x/0x%x pflags 0x%x]", 1637 txd->tx_flags, txd->tx_numdesc, txd->tx_totlen, 1638 txd->tx_addrlo, txd->tx_addrhi, txd->tx_pflags); 1639 break; 1640 case CMD_FLAGS_TYPE_FRAG: 1641 /* fragment descriptor */ 1642 printf("[frag flags 0x%x rsvd1 0x%x len %d addr 0x%x/0x%x rsvd2 0x%x]", 1643 frgd->frag_flags, frgd->frag_rsvd1, frgd->frag_len, 1644 frgd->frag_addrlo, frgd->frag_addrhi, frgd->frag_rsvd2); 1645 break; 1646 default: 1647 printf("[unknown(%x) flags 0x%x num %d id %d seq %d par1 0x%x par2 0x%x par3 0x%x]\n", 1648 cmd->cmd_flags & CMD_FLAGS_TYPE_M, 1649 cmd->cmd_flags, cmd->cmd_numdesc, cmd->cmd_id, cmd->cmd_seq, 1650 cmd->cmd_par1, cmd->cmd_par2, cmd->cmd_par3); 1651 break; 1652 } 1653 } 1654 #endif 1655 1656 static void 1657 txp_set_filter(struct txp_softc *sc) 1658 { 1659 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1660 uint16_t filter; 1661 struct ifmultiaddr *ifma; 1662 1663 if (ifp->if_flags & IFF_PROMISC) { 1664 filter = TXP_RXFILT_PROMISC; 1665 goto setit; 1666 } 1667 1668 filter = TXP_RXFILT_DIRECT; 1669 1670 if (ifp->if_flags & IFF_BROADCAST) 1671 filter |= TXP_RXFILT_BROADCAST; 1672 1673 if (ifp->if_flags & IFF_ALLMULTI) { 1674 filter |= TXP_RXFILT_ALLMULTI; 1675 } else { 1676 uint32_t hashbit, hash[2]; 1677 int mcnt = 0; 1678 1679 hash[0] = hash[1] = 0; 1680 1681 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1682 if (ifma->ifma_addr->sa_family != AF_LINK) 1683 continue; 1684 1685 mcnt++; 1686 hashbit = (uint16_t)(ether_crc32_be( 1687 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 1688 ETHER_ADDR_LEN) & (64 - 1)); 1689 hash[hashbit / 32] |= (1 << hashbit % 32); 1690 } 1691 1692 if (mcnt > 0) { 1693 filter |= TXP_RXFILT_HASHMULTI; 1694 txp_command(sc, TXP_CMD_MCAST_HASH_MASK_WRITE, 1695 2, hash[0], hash[1], NULL, NULL, NULL, 0); 1696 } 1697 } 1698 1699 setit: 1700 txp_command(sc, TXP_CMD_RX_FILTER_WRITE, filter, 0, 0, 1701 NULL, NULL, NULL, 1); 1702 } 1703 1704 static void 1705 txp_capabilities(struct txp_softc *sc) 1706 { 1707 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1708 struct txp_rsp_desc *rsp = NULL; 1709 struct txp_ext_desc *ext; 1710 1711 if (txp_command2(sc, TXP_CMD_OFFLOAD_READ, 0, 0, 0, NULL, 0, &rsp, 1)) 1712 goto out; 1713 1714 if (rsp->rsp_numdesc != 1) 1715 goto out; 1716 ext = (struct txp_ext_desc *)(rsp + 1); 1717 1718 sc->sc_tx_capability = ext->ext_1 & OFFLOAD_MASK; 1719 sc->sc_rx_capability = ext->ext_2 & OFFLOAD_MASK; 1720 ifp->if_capabilities = 0; 1721 1722 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_VLAN) { 1723 sc->sc_tx_capability |= OFFLOAD_VLAN; 1724 sc->sc_rx_capability |= OFFLOAD_VLAN; 1725 } 1726 1727 #if 0 1728 /* not ready yet */ 1729 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_IPSEC) { 1730 sc->sc_tx_capability |= OFFLOAD_IPSEC; 1731 sc->sc_rx_capability |= OFFLOAD_IPSEC; 1732 ifp->if_capabilities |= IFCAP_IPSEC; 1733 } 1734 #endif 1735 1736 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_IPCKSUM) { 1737 sc->sc_tx_capability |= OFFLOAD_IPCKSUM; 1738 sc->sc_rx_capability |= OFFLOAD_IPCKSUM; 1739 ifp->if_capabilities |= IFCAP_HWCSUM; 1740 ifp->if_hwassist |= CSUM_IP; 1741 } 1742 1743 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_TCPCKSUM) { 1744 #if 0 1745 sc->sc_tx_capability |= OFFLOAD_TCPCKSUM; 1746 #endif 1747 sc->sc_rx_capability |= OFFLOAD_TCPCKSUM; 1748 ifp->if_capabilities |= IFCAP_HWCSUM; 1749 } 1750 1751 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_UDPCKSUM) { 1752 #if 0 1753 sc->sc_tx_capability |= OFFLOAD_UDPCKSUM; 1754 #endif 1755 sc->sc_rx_capability |= OFFLOAD_UDPCKSUM; 1756 ifp->if_capabilities |= IFCAP_HWCSUM; 1757 } 1758 ifp->if_capenable = ifp->if_capabilities; 1759 1760 if (txp_command(sc, TXP_CMD_OFFLOAD_WRITE, 0, 1761 sc->sc_tx_capability, sc->sc_rx_capability, NULL, NULL, NULL, 1)) 1762 goto out; 1763 1764 out: 1765 if (rsp != NULL) 1766 free(rsp, M_DEVBUF); 1767 1768 return; 1769 } 1770