1 /* $OpenBSD: if_txp.c,v 1.48 2001/06/27 06:34:50 kjc Exp $ */ 2 /* $FreeBSD: src/sys/dev/txp/if_txp.c,v 1.4.2.4 2001/12/14 19:50:43 jlemon Exp $ */ 3 /* $DragonFly: src/sys/dev/netif/txp/if_txp.c,v 1.5 2003/11/20 22:07:31 dillon Exp $ */ 4 5 /* 6 * Copyright (c) 2001 7 * Jason L. Wright <jason@thought.net>, Theo de Raadt, and 8 * Aaron Campbell <aaron@monkey.org>. All rights reserved. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by Jason L. Wright, 21 * Theo de Raadt and Aaron Campbell. 22 * 4. Neither the name of the author nor the names of any co-contributors 23 * may be used to endorse or promote products derived from this software 24 * without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR 27 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 28 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 29 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 36 * THE POSSIBILITY OF SUCH DAMAGE. 37 * 38 * $FreeBSD: src/sys/dev/txp/if_txp.c,v 1.4.2.4 2001/12/14 19:50:43 jlemon Exp $ 39 */ 40 41 /* 42 * Driver for 3c990 (Typhoon) Ethernet ASIC 43 */ 44 45 #include <sys/param.h> 46 #include <sys/systm.h> 47 #include <sys/sockio.h> 48 #include <sys/mbuf.h> 49 #include <sys/malloc.h> 50 #include <sys/kernel.h> 51 #include <sys/socket.h> 52 53 #include <net/if.h> 54 #include <net/if_arp.h> 55 #include <net/ethernet.h> 56 #include <net/if_dl.h> 57 #include <net/if_types.h> 58 #include <net/vlan/if_vlan_var.h> 59 60 #include <netinet/in.h> 61 #include <netinet/in_systm.h> 62 #include <netinet/in_var.h> 63 #include <netinet/ip.h> 64 #include <netinet/if_ether.h> 65 #include <machine/in_cksum.h> 66 67 #include <net/if_media.h> 68 69 #include <net/bpf.h> 70 71 #include <vm/vm.h> /* for vtophys */ 72 #include <vm/pmap.h> /* for vtophys */ 73 #include <machine/clock.h> /* for DELAY */ 74 #include <machine/bus_pio.h> 75 #include <machine/bus_memio.h> 76 #include <machine/bus.h> 77 #include <machine/resource.h> 78 #include <sys/bus.h> 79 #include <sys/rman.h> 80 81 #include "../mii_layer/mii.h" 82 #include "../mii_layer/miivar.h" 83 #include <bus/pci/pcireg.h> 84 #include <bus/pci/pcivar.h> 85 86 #define TXP_USEIOSPACE 87 #define __STRICT_ALIGNMENT 88 89 #include "if_txpreg.h" 90 #include "3c990img.h" 91 92 /* 93 * Various supported device vendors/types and their names. 94 */ 95 static struct txp_type txp_devs[] = { 96 { TXP_VENDORID_3COM, TXP_DEVICEID_3CR990_TX_95, 97 "3Com 3cR990-TX-95 Etherlink with 3XP Processor" }, 98 { TXP_VENDORID_3COM, TXP_DEVICEID_3CR990_TX_97, 99 "3Com 3cR990-TX-97 Etherlink with 3XP Processor" }, 100 { TXP_VENDORID_3COM, TXP_DEVICEID_3CR990B_TXM, 101 "3Com 3cR990B-TXM Etherlink with 3XP Processor" }, 102 { TXP_VENDORID_3COM, TXP_DEVICEID_3CR990_SRV_95, 103 "3Com 3cR990-SRV-95 Etherlink Server with 3XP Processor" }, 104 { TXP_VENDORID_3COM, TXP_DEVICEID_3CR990_SRV_97, 105 "3Com 3cR990-SRV-97 Etherlink Server with 3XP Processor" }, 106 { TXP_VENDORID_3COM, TXP_DEVICEID_3CR990B_SRV, 107 "3Com 3cR990B-SRV Etherlink Server with 3XP Processor" }, 108 { 0, 0, NULL } 109 }; 110 111 static int txp_probe (device_t); 112 static int txp_attach (device_t); 113 static int txp_detach (device_t); 114 static void txp_intr (void *); 115 static void txp_tick (void *); 116 static int txp_shutdown (device_t); 117 static int txp_ioctl (struct ifnet *, u_long, caddr_t); 118 static void txp_start (struct ifnet *); 119 static void txp_stop (struct txp_softc *); 120 static void txp_init (void *); 121 static void txp_watchdog (struct ifnet *); 122 123 static void txp_release_resources (struct txp_softc *); 124 static int txp_chip_init (struct txp_softc *); 125 static int txp_reset_adapter (struct txp_softc *); 126 static int txp_download_fw (struct txp_softc *); 127 static int txp_download_fw_wait (struct txp_softc *); 128 static int txp_download_fw_section (struct txp_softc *, 129 struct txp_fw_section_header *, int); 130 static int txp_alloc_rings (struct txp_softc *); 131 static int txp_rxring_fill (struct txp_softc *); 132 static void txp_rxring_empty (struct txp_softc *); 133 static void txp_set_filter (struct txp_softc *); 134 135 static int txp_cmd_desc_numfree (struct txp_softc *); 136 static int txp_command (struct txp_softc *, u_int16_t, u_int16_t, u_int32_t, 137 u_int32_t, u_int16_t *, u_int32_t *, u_int32_t *, int); 138 static int txp_command2 (struct txp_softc *, u_int16_t, u_int16_t, 139 u_int32_t, u_int32_t, struct txp_ext_desc *, u_int8_t, 140 struct txp_rsp_desc **, int); 141 static int txp_response (struct txp_softc *, u_int32_t, u_int16_t, u_int16_t, 142 struct txp_rsp_desc **); 143 static void txp_rsp_fixup (struct txp_softc *, struct txp_rsp_desc *, 144 struct txp_rsp_desc *); 145 static void txp_capabilities (struct txp_softc *); 146 147 static void txp_ifmedia_sts (struct ifnet *, struct ifmediareq *); 148 static int txp_ifmedia_upd (struct ifnet *); 149 #ifdef TXP_DEBUG 150 static void txp_show_descriptor (void *); 151 #endif 152 static void txp_tx_reclaim (struct txp_softc *, struct txp_tx_ring *); 153 static void txp_rxbuf_reclaim (struct txp_softc *); 154 static void txp_rx_reclaim (struct txp_softc *, struct txp_rx_ring *); 155 156 #ifdef TXP_USEIOSPACE 157 #define TXP_RES SYS_RES_IOPORT 158 #define TXP_RID TXP_PCI_LOIO 159 #else 160 #define TXP_RES SYS_RES_MEMORY 161 #define TXP_RID TXP_PCI_LOMEM 162 #endif 163 164 static device_method_t txp_methods[] = { 165 /* Device interface */ 166 DEVMETHOD(device_probe, txp_probe), 167 DEVMETHOD(device_attach, txp_attach), 168 DEVMETHOD(device_detach, txp_detach), 169 DEVMETHOD(device_shutdown, txp_shutdown), 170 { 0, 0 } 171 }; 172 173 static driver_t txp_driver = { 174 "txp", 175 txp_methods, 176 sizeof(struct txp_softc) 177 }; 178 179 static devclass_t txp_devclass; 180 181 DECLARE_DUMMY_MODULE(if_txp); 182 DRIVER_MODULE(if_txp, pci, txp_driver, txp_devclass, 0, 0); 183 184 static int 185 txp_probe(dev) 186 device_t dev; 187 { 188 struct txp_type *t; 189 190 t = txp_devs; 191 192 while(t->txp_name != NULL) { 193 if ((pci_get_vendor(dev) == t->txp_vid) && 194 (pci_get_device(dev) == t->txp_did)) { 195 device_set_desc(dev, t->txp_name); 196 return(0); 197 } 198 t++; 199 } 200 201 return(ENXIO); 202 } 203 204 static int 205 txp_attach(dev) 206 device_t dev; 207 { 208 struct txp_softc *sc; 209 struct ifnet *ifp; 210 u_int32_t command; 211 u_int16_t p1; 212 u_int32_t p2; 213 int unit, error = 0, rid; 214 215 sc = device_get_softc(dev); 216 unit = device_get_unit(dev); 217 sc->sc_dev = dev; 218 sc->sc_cold = 1; 219 220 /* 221 * Map control/status registers. 222 */ 223 command = pci_read_config(dev, PCIR_COMMAND, 4); 224 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 225 pci_write_config(dev, PCIR_COMMAND, command, 4); 226 command = pci_read_config(dev, PCIR_COMMAND, 4); 227 228 #ifdef TXP_USEIOSPACE 229 if (!(command & PCIM_CMD_PORTEN)) { 230 device_printf(dev, "failed to enable I/O ports!\n"); 231 error = ENXIO;; 232 goto fail; 233 } 234 #else 235 if (!(command & PCIM_CMD_MEMEN)) { 236 device_printf(dev, "failed to enable memory mapping!\n"); 237 error = ENXIO;; 238 goto fail; 239 } 240 #endif 241 242 rid = TXP_RID; 243 sc->sc_res = bus_alloc_resource(dev, TXP_RES, &rid, 244 0, ~0, 1, RF_ACTIVE); 245 246 if (sc->sc_res == NULL) { 247 device_printf(dev, "couldn't map ports/memory\n"); 248 error = ENXIO; 249 goto fail; 250 } 251 252 sc->sc_bt = rman_get_bustag(sc->sc_res); 253 sc->sc_bh = rman_get_bushandle(sc->sc_res); 254 255 /* Allocate interrupt */ 256 rid = 0; 257 sc->sc_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 258 RF_SHAREABLE | RF_ACTIVE); 259 260 if (sc->sc_irq == NULL) { 261 device_printf(dev, "couldn't map interrupt\n"); 262 txp_release_resources(sc); 263 error = ENXIO; 264 goto fail; 265 } 266 267 error = bus_setup_intr(dev, sc->sc_irq, INTR_TYPE_NET, 268 txp_intr, sc, &sc->sc_intrhand); 269 270 if (error) { 271 txp_release_resources(sc); 272 device_printf(dev, "couldn't set up irq\n"); 273 goto fail; 274 } 275 276 if (txp_chip_init(sc)) { 277 txp_release_resources(sc); 278 goto fail; 279 } 280 281 sc->sc_fwbuf = contigmalloc(32768, M_DEVBUF, 282 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 283 error = txp_download_fw(sc); 284 contigfree(sc->sc_fwbuf, 32768, M_DEVBUF); 285 sc->sc_fwbuf = NULL; 286 287 if (error) { 288 txp_release_resources(sc); 289 goto fail; 290 } 291 292 sc->sc_ldata = contigmalloc(sizeof(struct txp_ldata), M_DEVBUF, 293 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 294 bzero(sc->sc_ldata, sizeof(struct txp_ldata)); 295 296 if (txp_alloc_rings(sc)) { 297 txp_release_resources(sc); 298 goto fail; 299 } 300 301 if (txp_command(sc, TXP_CMD_MAX_PKT_SIZE_WRITE, TXP_MAX_PKTLEN, 0, 0, 302 NULL, NULL, NULL, 1)) { 303 txp_release_resources(sc); 304 goto fail; 305 } 306 307 if (txp_command(sc, TXP_CMD_STATION_ADDRESS_READ, 0, 0, 0, 308 &p1, &p2, NULL, 1)) { 309 txp_release_resources(sc); 310 goto fail; 311 } 312 313 txp_set_filter(sc); 314 315 sc->sc_arpcom.ac_enaddr[0] = ((u_int8_t *)&p1)[1]; 316 sc->sc_arpcom.ac_enaddr[1] = ((u_int8_t *)&p1)[0]; 317 sc->sc_arpcom.ac_enaddr[2] = ((u_int8_t *)&p2)[3]; 318 sc->sc_arpcom.ac_enaddr[3] = ((u_int8_t *)&p2)[2]; 319 sc->sc_arpcom.ac_enaddr[4] = ((u_int8_t *)&p2)[1]; 320 sc->sc_arpcom.ac_enaddr[5] = ((u_int8_t *)&p2)[0]; 321 322 printf("txp%d: Ethernet address %6D\n", unit, 323 sc->sc_arpcom.ac_enaddr, ":"); 324 325 sc->sc_cold = 0; 326 327 ifmedia_init(&sc->sc_ifmedia, 0, txp_ifmedia_upd, txp_ifmedia_sts); 328 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_10_T, 0, NULL); 329 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_10_T|IFM_HDX, 0, NULL); 330 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL); 331 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_100_TX, 0, NULL); 332 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_100_TX|IFM_HDX, 0, NULL); 333 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_100_TX|IFM_FDX, 0, NULL); 334 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 335 336 sc->sc_xcvr = TXP_XCVR_AUTO; 337 txp_command(sc, TXP_CMD_XCVR_SELECT, TXP_XCVR_AUTO, 0, 0, 338 NULL, NULL, NULL, 0); 339 ifmedia_set(&sc->sc_ifmedia, IFM_ETHER|IFM_AUTO); 340 341 ifp = &sc->sc_arpcom.ac_if; 342 ifp->if_softc = sc; 343 ifp->if_unit = unit; 344 ifp->if_name = "txp"; 345 ifp->if_mtu = ETHERMTU; 346 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 347 ifp->if_ioctl = txp_ioctl; 348 ifp->if_output = ether_output; 349 ifp->if_start = txp_start; 350 ifp->if_watchdog = txp_watchdog; 351 ifp->if_init = txp_init; 352 ifp->if_baudrate = 100000000; 353 ifp->if_snd.ifq_maxlen = TX_ENTRIES; 354 ifp->if_hwassist = 0; 355 txp_capabilities(sc); 356 357 /* 358 * Attach us everywhere 359 */ 360 ether_ifattach(ifp, ETHER_BPF_SUPPORTED); 361 callout_handle_init(&sc->sc_tick); 362 return(0); 363 364 fail: 365 txp_release_resources(sc); 366 return(error); 367 } 368 369 static int 370 txp_detach(dev) 371 device_t dev; 372 { 373 struct txp_softc *sc; 374 struct ifnet *ifp; 375 int i; 376 377 sc = device_get_softc(dev); 378 ifp = &sc->sc_arpcom.ac_if; 379 380 txp_stop(sc); 381 txp_shutdown(dev); 382 383 ifmedia_removeall(&sc->sc_ifmedia); 384 ether_ifdetach(ifp, ETHER_BPF_SUPPORTED); 385 386 for (i = 0; i < RXBUF_ENTRIES; i++) 387 free(sc->sc_rxbufs[i].rb_sd, M_DEVBUF); 388 389 txp_release_resources(sc); 390 391 return(0); 392 } 393 394 static void 395 txp_release_resources(sc) 396 struct txp_softc *sc; 397 { 398 device_t dev; 399 400 dev = sc->sc_dev; 401 402 if (sc->sc_intrhand != NULL) 403 bus_teardown_intr(dev, sc->sc_irq, sc->sc_intrhand); 404 405 if (sc->sc_irq != NULL) 406 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq); 407 408 if (sc->sc_res != NULL) 409 bus_release_resource(dev, TXP_RES, TXP_RID, sc->sc_res); 410 411 if (sc->sc_ldata != NULL) 412 contigfree(sc->sc_ldata, sizeof(struct txp_ldata), M_DEVBUF); 413 414 return; 415 } 416 417 static int 418 txp_chip_init(sc) 419 struct txp_softc *sc; 420 { 421 /* disable interrupts */ 422 WRITE_REG(sc, TXP_IER, 0); 423 WRITE_REG(sc, TXP_IMR, 424 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 425 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 426 TXP_INT_LATCH); 427 428 /* ack all interrupts */ 429 WRITE_REG(sc, TXP_ISR, TXP_INT_RESERVED | TXP_INT_LATCH | 430 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 | 431 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 432 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 433 TXP_INT_A2H_3 | TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0); 434 435 if (txp_reset_adapter(sc)) 436 return (-1); 437 438 /* disable interrupts */ 439 WRITE_REG(sc, TXP_IER, 0); 440 WRITE_REG(sc, TXP_IMR, 441 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 442 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 443 TXP_INT_LATCH); 444 445 /* ack all interrupts */ 446 WRITE_REG(sc, TXP_ISR, TXP_INT_RESERVED | TXP_INT_LATCH | 447 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 | 448 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 449 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 450 TXP_INT_A2H_3 | TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0); 451 452 return (0); 453 } 454 455 static int 456 txp_reset_adapter(sc) 457 struct txp_softc *sc; 458 { 459 u_int32_t r; 460 int i; 461 462 WRITE_REG(sc, TXP_SRR, TXP_SRR_ALL); 463 DELAY(1000); 464 WRITE_REG(sc, TXP_SRR, 0); 465 466 /* Should wait max 6 seconds */ 467 for (i = 0; i < 6000; i++) { 468 r = READ_REG(sc, TXP_A2H_0); 469 if (r == STAT_WAITING_FOR_HOST_REQUEST) 470 break; 471 DELAY(1000); 472 } 473 474 if (r != STAT_WAITING_FOR_HOST_REQUEST) { 475 device_printf(sc->sc_dev, "reset hung\n"); 476 return (-1); 477 } 478 479 return (0); 480 } 481 482 static int 483 txp_download_fw(sc) 484 struct txp_softc *sc; 485 { 486 struct txp_fw_file_header *fileheader; 487 struct txp_fw_section_header *secthead; 488 int sect; 489 u_int32_t r, i, ier, imr; 490 491 ier = READ_REG(sc, TXP_IER); 492 WRITE_REG(sc, TXP_IER, ier | TXP_INT_A2H_0); 493 494 imr = READ_REG(sc, TXP_IMR); 495 WRITE_REG(sc, TXP_IMR, imr | TXP_INT_A2H_0); 496 497 for (i = 0; i < 10000; i++) { 498 r = READ_REG(sc, TXP_A2H_0); 499 if (r == STAT_WAITING_FOR_HOST_REQUEST) 500 break; 501 DELAY(50); 502 } 503 if (r != STAT_WAITING_FOR_HOST_REQUEST) { 504 device_printf(sc->sc_dev, "not waiting for host request\n"); 505 return (-1); 506 } 507 508 /* Ack the status */ 509 WRITE_REG(sc, TXP_ISR, TXP_INT_A2H_0); 510 511 fileheader = (struct txp_fw_file_header *)tc990image; 512 if (bcmp("TYPHOON", fileheader->magicid, sizeof(fileheader->magicid))) { 513 device_printf(sc->sc_dev, "fw invalid magic\n"); 514 return (-1); 515 } 516 517 /* Tell boot firmware to get ready for image */ 518 WRITE_REG(sc, TXP_H2A_1, fileheader->addr); 519 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_RUNTIME_IMAGE); 520 521 if (txp_download_fw_wait(sc)) { 522 device_printf(sc->sc_dev, "fw wait failed, initial\n"); 523 return (-1); 524 } 525 526 secthead = (struct txp_fw_section_header *)(((u_int8_t *)tc990image) + 527 sizeof(struct txp_fw_file_header)); 528 529 for (sect = 0; sect < fileheader->nsections; sect++) { 530 if (txp_download_fw_section(sc, secthead, sect)) 531 return (-1); 532 secthead = (struct txp_fw_section_header *) 533 (((u_int8_t *)secthead) + secthead->nbytes + 534 sizeof(*secthead)); 535 } 536 537 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_DOWNLOAD_COMPLETE); 538 539 for (i = 0; i < 10000; i++) { 540 r = READ_REG(sc, TXP_A2H_0); 541 if (r == STAT_WAITING_FOR_BOOT) 542 break; 543 DELAY(50); 544 } 545 if (r != STAT_WAITING_FOR_BOOT) { 546 device_printf(sc->sc_dev, "not waiting for boot\n"); 547 return (-1); 548 } 549 550 WRITE_REG(sc, TXP_IER, ier); 551 WRITE_REG(sc, TXP_IMR, imr); 552 553 return (0); 554 } 555 556 static int 557 txp_download_fw_wait(sc) 558 struct txp_softc *sc; 559 { 560 u_int32_t i, r; 561 562 for (i = 0; i < 10000; i++) { 563 r = READ_REG(sc, TXP_ISR); 564 if (r & TXP_INT_A2H_0) 565 break; 566 DELAY(50); 567 } 568 569 if (!(r & TXP_INT_A2H_0)) { 570 device_printf(sc->sc_dev, "fw wait failed comm0\n"); 571 return (-1); 572 } 573 574 WRITE_REG(sc, TXP_ISR, TXP_INT_A2H_0); 575 576 r = READ_REG(sc, TXP_A2H_0); 577 if (r != STAT_WAITING_FOR_SEGMENT) { 578 device_printf(sc->sc_dev, "fw not waiting for segment\n"); 579 return (-1); 580 } 581 return (0); 582 } 583 584 static int 585 txp_download_fw_section(sc, sect, sectnum) 586 struct txp_softc *sc; 587 struct txp_fw_section_header *sect; 588 int sectnum; 589 { 590 vm_offset_t dma; 591 int rseg, err = 0; 592 struct mbuf m; 593 u_int16_t csum; 594 595 /* Skip zero length sections */ 596 if (sect->nbytes == 0) 597 return (0); 598 599 /* Make sure we aren't past the end of the image */ 600 rseg = ((u_int8_t *)sect) - ((u_int8_t *)tc990image); 601 if (rseg >= sizeof(tc990image)) { 602 device_printf(sc->sc_dev, "fw invalid section address, " 603 "section %d\n", sectnum); 604 return (-1); 605 } 606 607 /* Make sure this section doesn't go past the end */ 608 rseg += sect->nbytes; 609 if (rseg >= sizeof(tc990image)) { 610 device_printf(sc->sc_dev, "fw truncated section %d\n", 611 sectnum); 612 return (-1); 613 } 614 615 bcopy(((u_int8_t *)sect) + sizeof(*sect), sc->sc_fwbuf, sect->nbytes); 616 dma = vtophys(sc->sc_fwbuf); 617 618 /* 619 * dummy up mbuf and verify section checksum 620 */ 621 m.m_type = MT_DATA; 622 m.m_next = m.m_nextpkt = NULL; 623 m.m_len = sect->nbytes; 624 m.m_data = sc->sc_fwbuf; 625 m.m_flags = 0; 626 csum = in_cksum(&m, sect->nbytes); 627 if (csum != sect->cksum) { 628 device_printf(sc->sc_dev, "fw section %d, bad " 629 "cksum (expected 0x%x got 0x%x)\n", 630 sectnum, sect->cksum, csum); 631 err = -1; 632 goto bail; 633 } 634 635 WRITE_REG(sc, TXP_H2A_1, sect->nbytes); 636 WRITE_REG(sc, TXP_H2A_2, sect->cksum); 637 WRITE_REG(sc, TXP_H2A_3, sect->addr); 638 WRITE_REG(sc, TXP_H2A_4, 0); 639 WRITE_REG(sc, TXP_H2A_5, dma & 0xffffffff); 640 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_SEGMENT_AVAILABLE); 641 642 if (txp_download_fw_wait(sc)) { 643 device_printf(sc->sc_dev, "fw wait failed, " 644 "section %d\n", sectnum); 645 err = -1; 646 } 647 648 bail: 649 return (err); 650 } 651 652 static void 653 txp_intr(vsc) 654 void *vsc; 655 { 656 struct txp_softc *sc = vsc; 657 struct txp_hostvar *hv = sc->sc_hostvar; 658 u_int32_t isr; 659 660 /* mask all interrupts */ 661 WRITE_REG(sc, TXP_IMR, TXP_INT_RESERVED | TXP_INT_SELF | 662 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 | 663 TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0 | 664 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 665 TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | TXP_INT_LATCH); 666 667 isr = READ_REG(sc, TXP_ISR); 668 while (isr) { 669 WRITE_REG(sc, TXP_ISR, isr); 670 671 if ((*sc->sc_rxhir.r_roff) != (*sc->sc_rxhir.r_woff)) 672 txp_rx_reclaim(sc, &sc->sc_rxhir); 673 if ((*sc->sc_rxlor.r_roff) != (*sc->sc_rxlor.r_woff)) 674 txp_rx_reclaim(sc, &sc->sc_rxlor); 675 676 if (hv->hv_rx_buf_write_idx == hv->hv_rx_buf_read_idx) 677 txp_rxbuf_reclaim(sc); 678 679 if (sc->sc_txhir.r_cnt && (sc->sc_txhir.r_cons != 680 TXP_OFFSET2IDX(*(sc->sc_txhir.r_off)))) 681 txp_tx_reclaim(sc, &sc->sc_txhir); 682 683 if (sc->sc_txlor.r_cnt && (sc->sc_txlor.r_cons != 684 TXP_OFFSET2IDX(*(sc->sc_txlor.r_off)))) 685 txp_tx_reclaim(sc, &sc->sc_txlor); 686 687 isr = READ_REG(sc, TXP_ISR); 688 } 689 690 /* unmask all interrupts */ 691 WRITE_REG(sc, TXP_IMR, TXP_INT_A2H_3); 692 693 txp_start(&sc->sc_arpcom.ac_if); 694 695 return; 696 } 697 698 static void 699 txp_rx_reclaim(sc, r) 700 struct txp_softc *sc; 701 struct txp_rx_ring *r; 702 { 703 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 704 struct txp_rx_desc *rxd; 705 struct mbuf *m; 706 struct txp_swdesc *sd = NULL; 707 u_int32_t roff, woff; 708 struct ether_header *eh = NULL; 709 710 roff = *r->r_roff; 711 woff = *r->r_woff; 712 rxd = r->r_desc + (roff / sizeof(struct txp_rx_desc)); 713 714 while (roff != woff) { 715 716 if (rxd->rx_flags & RX_FLAGS_ERROR) { 717 device_printf(sc->sc_dev, "error 0x%x\n", 718 rxd->rx_stat); 719 ifp->if_ierrors++; 720 goto next; 721 } 722 723 /* retrieve stashed pointer */ 724 sd = rxd->rx_sd; 725 726 m = sd->sd_mbuf; 727 sd->sd_mbuf = NULL; 728 729 m->m_pkthdr.len = m->m_len = rxd->rx_len; 730 731 #ifdef __STRICT_ALIGNMENT 732 { 733 /* 734 * XXX Nice chip, except it won't accept "off by 2" 735 * buffers, so we're force to copy. Supposedly 736 * this will be fixed in a newer firmware rev 737 * and this will be temporary. 738 */ 739 struct mbuf *mnew; 740 741 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 742 if (mnew == NULL) { 743 m_freem(m); 744 goto next; 745 } 746 if (m->m_len > (MHLEN - 2)) { 747 MCLGET(mnew, M_DONTWAIT); 748 if (!(mnew->m_flags & M_EXT)) { 749 m_freem(mnew); 750 m_freem(m); 751 goto next; 752 } 753 } 754 mnew->m_pkthdr.rcvif = ifp; 755 m_adj(mnew, 2); 756 mnew->m_pkthdr.len = mnew->m_len = m->m_len; 757 m_copydata(m, 0, m->m_pkthdr.len, mtod(mnew, caddr_t)); 758 m_freem(m); 759 m = mnew; 760 } 761 #endif 762 763 if (rxd->rx_stat & RX_STAT_IPCKSUMBAD) 764 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 765 else if (rxd->rx_stat & RX_STAT_IPCKSUMGOOD) 766 m->m_pkthdr.csum_flags |= 767 CSUM_IP_CHECKED|CSUM_IP_VALID; 768 769 if ((rxd->rx_stat & RX_STAT_TCPCKSUMGOOD) || 770 (rxd->rx_stat & RX_STAT_UDPCKSUMGOOD)) { 771 m->m_pkthdr.csum_flags |= 772 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 773 m->m_pkthdr.csum_data = 0xffff; 774 } 775 776 eh = mtod(m, struct ether_header *); 777 /* Remove header from mbuf and pass it on. */ 778 m_adj(m, sizeof(struct ether_header)); 779 780 if (rxd->rx_stat & RX_STAT_VLAN) { 781 VLAN_INPUT_TAG(eh, m, htons(rxd->rx_vlan >> 16)); 782 goto next; 783 } 784 785 ether_input(ifp, eh, m); 786 787 next: 788 789 roff += sizeof(struct txp_rx_desc); 790 if (roff == (RX_ENTRIES * sizeof(struct txp_rx_desc))) { 791 roff = 0; 792 rxd = r->r_desc; 793 } else 794 rxd++; 795 woff = *r->r_woff; 796 } 797 798 *r->r_roff = woff; 799 800 return; 801 } 802 803 static void 804 txp_rxbuf_reclaim(sc) 805 struct txp_softc *sc; 806 { 807 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 808 struct txp_hostvar *hv = sc->sc_hostvar; 809 struct txp_rxbuf_desc *rbd; 810 struct txp_swdesc *sd; 811 u_int32_t i; 812 813 if (!(ifp->if_flags & IFF_RUNNING)) 814 return; 815 816 i = sc->sc_rxbufprod; 817 rbd = sc->sc_rxbufs + i; 818 819 while (1) { 820 sd = rbd->rb_sd; 821 if (sd->sd_mbuf != NULL) 822 break; 823 824 MGETHDR(sd->sd_mbuf, M_DONTWAIT, MT_DATA); 825 if (sd->sd_mbuf == NULL) 826 goto err_sd; 827 828 MCLGET(sd->sd_mbuf, M_DONTWAIT); 829 if ((sd->sd_mbuf->m_flags & M_EXT) == 0) 830 goto err_mbuf; 831 sd->sd_mbuf->m_pkthdr.rcvif = ifp; 832 sd->sd_mbuf->m_pkthdr.len = sd->sd_mbuf->m_len = MCLBYTES; 833 834 rbd->rb_paddrlo = vtophys(mtod(sd->sd_mbuf, vm_offset_t)) 835 & 0xffffffff; 836 rbd->rb_paddrhi = 0; 837 838 hv->hv_rx_buf_write_idx = TXP_IDX2OFFSET(i); 839 840 if (++i == RXBUF_ENTRIES) { 841 i = 0; 842 rbd = sc->sc_rxbufs; 843 } else 844 rbd++; 845 } 846 847 sc->sc_rxbufprod = i; 848 849 return; 850 851 err_mbuf: 852 m_freem(sd->sd_mbuf); 853 err_sd: 854 free(sd, M_DEVBUF); 855 } 856 857 /* 858 * Reclaim mbufs and entries from a transmit ring. 859 */ 860 static void 861 txp_tx_reclaim(sc, r) 862 struct txp_softc *sc; 863 struct txp_tx_ring *r; 864 { 865 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 866 u_int32_t idx = TXP_OFFSET2IDX(*(r->r_off)); 867 u_int32_t cons = r->r_cons, cnt = r->r_cnt; 868 struct txp_tx_desc *txd = r->r_desc + cons; 869 struct txp_swdesc *sd = sc->sc_txd + cons; 870 struct mbuf *m; 871 872 while (cons != idx) { 873 if (cnt == 0) 874 break; 875 876 if ((txd->tx_flags & TX_FLAGS_TYPE_M) == 877 TX_FLAGS_TYPE_DATA) { 878 m = sd->sd_mbuf; 879 if (m != NULL) { 880 m_freem(m); 881 txd->tx_addrlo = 0; 882 txd->tx_addrhi = 0; 883 ifp->if_opackets++; 884 } 885 } 886 ifp->if_flags &= ~IFF_OACTIVE; 887 888 if (++cons == TX_ENTRIES) { 889 txd = r->r_desc; 890 cons = 0; 891 sd = sc->sc_txd; 892 } else { 893 txd++; 894 sd++; 895 } 896 897 cnt--; 898 } 899 900 r->r_cons = cons; 901 r->r_cnt = cnt; 902 if (cnt == 0) 903 ifp->if_timer = 0; 904 } 905 906 static int 907 txp_shutdown(dev) 908 device_t dev; 909 { 910 struct txp_softc *sc; 911 912 sc = device_get_softc(dev); 913 914 /* mask all interrupts */ 915 WRITE_REG(sc, TXP_IMR, 916 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 917 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 918 TXP_INT_LATCH); 919 920 txp_command(sc, TXP_CMD_TX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 0); 921 txp_command(sc, TXP_CMD_RX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 0); 922 txp_command(sc, TXP_CMD_HALT, 0, 0, 0, NULL, NULL, NULL, 0); 923 924 return(0); 925 } 926 927 static int 928 txp_alloc_rings(sc) 929 struct txp_softc *sc; 930 { 931 struct txp_boot_record *boot; 932 struct txp_ldata *ld; 933 u_int32_t r; 934 int i; 935 936 ld = sc->sc_ldata; 937 boot = &ld->txp_boot; 938 939 /* boot record */ 940 sc->sc_boot = boot; 941 942 /* host variables */ 943 bzero(&ld->txp_hostvar, sizeof(struct txp_hostvar)); 944 boot->br_hostvar_lo = vtophys(&ld->txp_hostvar); 945 boot->br_hostvar_hi = 0; 946 sc->sc_hostvar = (struct txp_hostvar *)&ld->txp_hostvar; 947 948 /* hi priority tx ring */ 949 boot->br_txhipri_lo = vtophys(&ld->txp_txhiring);; 950 boot->br_txhipri_hi = 0; 951 boot->br_txhipri_siz = TX_ENTRIES * sizeof(struct txp_tx_desc); 952 sc->sc_txhir.r_reg = TXP_H2A_1; 953 sc->sc_txhir.r_desc = (struct txp_tx_desc *)&ld->txp_txhiring; 954 sc->sc_txhir.r_cons = sc->sc_txhir.r_prod = sc->sc_txhir.r_cnt = 0; 955 sc->sc_txhir.r_off = &sc->sc_hostvar->hv_tx_hi_desc_read_idx; 956 957 /* lo priority tx ring */ 958 boot->br_txlopri_lo = vtophys(&ld->txp_txloring); 959 boot->br_txlopri_hi = 0; 960 boot->br_txlopri_siz = TX_ENTRIES * sizeof(struct txp_tx_desc); 961 sc->sc_txlor.r_reg = TXP_H2A_3; 962 sc->sc_txlor.r_desc = (struct txp_tx_desc *)&ld->txp_txloring; 963 sc->sc_txlor.r_cons = sc->sc_txlor.r_prod = sc->sc_txlor.r_cnt = 0; 964 sc->sc_txlor.r_off = &sc->sc_hostvar->hv_tx_lo_desc_read_idx; 965 966 /* high priority rx ring */ 967 boot->br_rxhipri_lo = vtophys(&ld->txp_rxhiring); 968 boot->br_rxhipri_hi = 0; 969 boot->br_rxhipri_siz = RX_ENTRIES * sizeof(struct txp_rx_desc); 970 sc->sc_rxhir.r_desc = (struct txp_rx_desc *)&ld->txp_rxhiring; 971 sc->sc_rxhir.r_roff = &sc->sc_hostvar->hv_rx_hi_read_idx; 972 sc->sc_rxhir.r_woff = &sc->sc_hostvar->hv_rx_hi_write_idx; 973 974 /* low priority rx ring */ 975 boot->br_rxlopri_lo = vtophys(&ld->txp_rxloring); 976 boot->br_rxlopri_hi = 0; 977 boot->br_rxlopri_siz = RX_ENTRIES * sizeof(struct txp_rx_desc); 978 sc->sc_rxlor.r_desc = (struct txp_rx_desc *)&ld->txp_rxloring; 979 sc->sc_rxlor.r_roff = &sc->sc_hostvar->hv_rx_lo_read_idx; 980 sc->sc_rxlor.r_woff = &sc->sc_hostvar->hv_rx_lo_write_idx; 981 982 /* command ring */ 983 bzero(&ld->txp_cmdring, sizeof(struct txp_cmd_desc) * CMD_ENTRIES); 984 boot->br_cmd_lo = vtophys(&ld->txp_cmdring); 985 boot->br_cmd_hi = 0; 986 boot->br_cmd_siz = CMD_ENTRIES * sizeof(struct txp_cmd_desc); 987 sc->sc_cmdring.base = (struct txp_cmd_desc *)&ld->txp_cmdring; 988 sc->sc_cmdring.size = CMD_ENTRIES * sizeof(struct txp_cmd_desc); 989 sc->sc_cmdring.lastwrite = 0; 990 991 /* response ring */ 992 bzero(&ld->txp_rspring, sizeof(struct txp_rsp_desc) * RSP_ENTRIES); 993 boot->br_resp_lo = vtophys(&ld->txp_rspring); 994 boot->br_resp_hi = 0; 995 boot->br_resp_siz = CMD_ENTRIES * sizeof(struct txp_rsp_desc); 996 sc->sc_rspring.base = (struct txp_rsp_desc *)&ld->txp_rspring; 997 sc->sc_rspring.size = RSP_ENTRIES * sizeof(struct txp_rsp_desc); 998 sc->sc_rspring.lastwrite = 0; 999 1000 /* receive buffer ring */ 1001 boot->br_rxbuf_lo = vtophys(&ld->txp_rxbufs); 1002 boot->br_rxbuf_hi = 0; 1003 boot->br_rxbuf_siz = RXBUF_ENTRIES * sizeof(struct txp_rxbuf_desc); 1004 sc->sc_rxbufs = (struct txp_rxbuf_desc *)&ld->txp_rxbufs; 1005 1006 for (i = 0; i < RXBUF_ENTRIES; i++) { 1007 struct txp_swdesc *sd; 1008 if (sc->sc_rxbufs[i].rb_sd != NULL) 1009 continue; 1010 sc->sc_rxbufs[i].rb_sd = malloc(sizeof(struct txp_swdesc), 1011 M_DEVBUF, M_NOWAIT); 1012 if (sc->sc_rxbufs[i].rb_sd == NULL) 1013 return(ENOBUFS); 1014 sd = sc->sc_rxbufs[i].rb_sd; 1015 sd->sd_mbuf = NULL; 1016 } 1017 sc->sc_rxbufprod = 0; 1018 1019 /* zero dma */ 1020 bzero(&ld->txp_zero, sizeof(u_int32_t)); 1021 boot->br_zero_lo = vtophys(&ld->txp_zero); 1022 boot->br_zero_hi = 0; 1023 1024 /* See if it's waiting for boot, and try to boot it */ 1025 for (i = 0; i < 10000; i++) { 1026 r = READ_REG(sc, TXP_A2H_0); 1027 if (r == STAT_WAITING_FOR_BOOT) 1028 break; 1029 DELAY(50); 1030 } 1031 1032 if (r != STAT_WAITING_FOR_BOOT) { 1033 device_printf(sc->sc_dev, "not waiting for boot\n"); 1034 return(ENXIO); 1035 } 1036 1037 WRITE_REG(sc, TXP_H2A_2, 0); 1038 WRITE_REG(sc, TXP_H2A_1, vtophys(sc->sc_boot)); 1039 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_REGISTER_BOOT_RECORD); 1040 1041 /* See if it booted */ 1042 for (i = 0; i < 10000; i++) { 1043 r = READ_REG(sc, TXP_A2H_0); 1044 if (r == STAT_RUNNING) 1045 break; 1046 DELAY(50); 1047 } 1048 if (r != STAT_RUNNING) { 1049 device_printf(sc->sc_dev, "fw not running\n"); 1050 return(ENXIO); 1051 } 1052 1053 /* Clear TX and CMD ring write registers */ 1054 WRITE_REG(sc, TXP_H2A_1, TXP_BOOTCMD_NULL); 1055 WRITE_REG(sc, TXP_H2A_2, TXP_BOOTCMD_NULL); 1056 WRITE_REG(sc, TXP_H2A_3, TXP_BOOTCMD_NULL); 1057 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_NULL); 1058 1059 return (0); 1060 } 1061 1062 static int 1063 txp_ioctl(ifp, command, data) 1064 struct ifnet *ifp; 1065 u_long command; 1066 caddr_t data; 1067 { 1068 struct txp_softc *sc = ifp->if_softc; 1069 struct ifreq *ifr = (struct ifreq *)data; 1070 int s, error = 0; 1071 1072 s = splnet(); 1073 1074 if ((error = ether_ioctl(ifp, command, data)) > 0) { 1075 splx(s); 1076 return error; 1077 } 1078 1079 switch(command) { 1080 case SIOCSIFADDR: 1081 case SIOCGIFADDR: 1082 case SIOCSIFMTU: 1083 error = ether_ioctl(ifp, command, data); 1084 break; 1085 case SIOCSIFFLAGS: 1086 if (ifp->if_flags & IFF_UP) { 1087 txp_init(sc); 1088 } else { 1089 if (ifp->if_flags & IFF_RUNNING) 1090 txp_stop(sc); 1091 } 1092 break; 1093 case SIOCADDMULTI: 1094 case SIOCDELMULTI: 1095 /* 1096 * Multicast list has changed; set the hardware 1097 * filter accordingly. 1098 */ 1099 txp_set_filter(sc); 1100 error = 0; 1101 break; 1102 case SIOCGIFMEDIA: 1103 case SIOCSIFMEDIA: 1104 error = ifmedia_ioctl(ifp, ifr, &sc->sc_ifmedia, command); 1105 break; 1106 default: 1107 error = EINVAL; 1108 break; 1109 } 1110 1111 (void)splx(s); 1112 1113 return(error); 1114 } 1115 1116 static int 1117 txp_rxring_fill(sc) 1118 struct txp_softc *sc; 1119 { 1120 int i; 1121 struct ifnet *ifp; 1122 struct txp_swdesc *sd; 1123 1124 ifp = &sc->sc_arpcom.ac_if; 1125 1126 for (i = 0; i < RXBUF_ENTRIES; i++) { 1127 sd = sc->sc_rxbufs[i].rb_sd; 1128 MGETHDR(sd->sd_mbuf, M_DONTWAIT, MT_DATA); 1129 if (sd->sd_mbuf == NULL) 1130 return(ENOBUFS); 1131 1132 MCLGET(sd->sd_mbuf, M_DONTWAIT); 1133 if ((sd->sd_mbuf->m_flags & M_EXT) == 0) { 1134 m_freem(sd->sd_mbuf); 1135 return(ENOBUFS); 1136 } 1137 sd->sd_mbuf->m_pkthdr.len = sd->sd_mbuf->m_len = MCLBYTES; 1138 sd->sd_mbuf->m_pkthdr.rcvif = ifp; 1139 1140 sc->sc_rxbufs[i].rb_paddrlo = 1141 vtophys(mtod(sd->sd_mbuf, vm_offset_t)); 1142 sc->sc_rxbufs[i].rb_paddrhi = 0; 1143 } 1144 1145 sc->sc_hostvar->hv_rx_buf_write_idx = (RXBUF_ENTRIES - 1) * 1146 sizeof(struct txp_rxbuf_desc); 1147 1148 return(0); 1149 } 1150 1151 static void 1152 txp_rxring_empty(sc) 1153 struct txp_softc *sc; 1154 { 1155 int i; 1156 struct txp_swdesc *sd; 1157 1158 if (sc->sc_rxbufs == NULL) 1159 return; 1160 1161 for (i = 0; i < RXBUF_ENTRIES; i++) { 1162 if (&sc->sc_rxbufs[i] == NULL) 1163 continue; 1164 sd = sc->sc_rxbufs[i].rb_sd; 1165 if (sd == NULL) 1166 continue; 1167 if (sd->sd_mbuf != NULL) { 1168 m_freem(sd->sd_mbuf); 1169 sd->sd_mbuf = NULL; 1170 } 1171 } 1172 1173 return; 1174 } 1175 1176 static void 1177 txp_init(xsc) 1178 void *xsc; 1179 { 1180 struct txp_softc *sc; 1181 struct ifnet *ifp; 1182 u_int16_t p1; 1183 u_int32_t p2; 1184 int s; 1185 1186 sc = xsc; 1187 ifp = &sc->sc_arpcom.ac_if; 1188 1189 if (ifp->if_flags & IFF_RUNNING) 1190 return; 1191 1192 txp_stop(sc); 1193 1194 s = splnet(); 1195 1196 txp_command(sc, TXP_CMD_MAX_PKT_SIZE_WRITE, TXP_MAX_PKTLEN, 0, 0, 1197 NULL, NULL, NULL, 1); 1198 1199 /* Set station address. */ 1200 ((u_int8_t *)&p1)[1] = sc->sc_arpcom.ac_enaddr[0]; 1201 ((u_int8_t *)&p1)[0] = sc->sc_arpcom.ac_enaddr[1]; 1202 ((u_int8_t *)&p2)[3] = sc->sc_arpcom.ac_enaddr[2]; 1203 ((u_int8_t *)&p2)[2] = sc->sc_arpcom.ac_enaddr[3]; 1204 ((u_int8_t *)&p2)[1] = sc->sc_arpcom.ac_enaddr[4]; 1205 ((u_int8_t *)&p2)[0] = sc->sc_arpcom.ac_enaddr[5]; 1206 txp_command(sc, TXP_CMD_STATION_ADDRESS_WRITE, p1, p2, 0, 1207 NULL, NULL, NULL, 1); 1208 1209 txp_set_filter(sc); 1210 1211 txp_rxring_fill(sc); 1212 1213 txp_command(sc, TXP_CMD_TX_ENABLE, 0, 0, 0, NULL, NULL, NULL, 1); 1214 txp_command(sc, TXP_CMD_RX_ENABLE, 0, 0, 0, NULL, NULL, NULL, 1); 1215 1216 WRITE_REG(sc, TXP_IER, TXP_INT_RESERVED | TXP_INT_SELF | 1217 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 | 1218 TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0 | 1219 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 1220 TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | TXP_INT_LATCH); 1221 WRITE_REG(sc, TXP_IMR, TXP_INT_A2H_3); 1222 1223 ifp->if_flags |= IFF_RUNNING; 1224 ifp->if_flags &= ~IFF_OACTIVE; 1225 ifp->if_timer = 0; 1226 1227 sc->sc_tick = timeout(txp_tick, sc, hz); 1228 1229 splx(s); 1230 } 1231 1232 static void 1233 txp_tick(vsc) 1234 void *vsc; 1235 { 1236 struct txp_softc *sc = vsc; 1237 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1238 struct txp_rsp_desc *rsp = NULL; 1239 struct txp_ext_desc *ext; 1240 int s; 1241 1242 s = splnet(); 1243 txp_rxbuf_reclaim(sc); 1244 1245 if (txp_command2(sc, TXP_CMD_READ_STATISTICS, 0, 0, 0, NULL, 0, 1246 &rsp, 1)) 1247 goto out; 1248 if (rsp->rsp_numdesc != 6) 1249 goto out; 1250 if (txp_command(sc, TXP_CMD_CLEAR_STATISTICS, 0, 0, 0, 1251 NULL, NULL, NULL, 1)) 1252 goto out; 1253 ext = (struct txp_ext_desc *)(rsp + 1); 1254 1255 ifp->if_ierrors += ext[3].ext_2 + ext[3].ext_3 + ext[3].ext_4 + 1256 ext[4].ext_1 + ext[4].ext_4; 1257 ifp->if_oerrors += ext[0].ext_1 + ext[1].ext_1 + ext[1].ext_4 + 1258 ext[2].ext_1; 1259 ifp->if_collisions += ext[0].ext_2 + ext[0].ext_3 + ext[1].ext_2 + 1260 ext[1].ext_3; 1261 ifp->if_opackets += rsp->rsp_par2; 1262 ifp->if_ipackets += ext[2].ext_3; 1263 1264 out: 1265 if (rsp != NULL) 1266 free(rsp, M_DEVBUF); 1267 1268 splx(s); 1269 sc->sc_tick = timeout(txp_tick, sc, hz); 1270 1271 return; 1272 } 1273 1274 static void 1275 txp_start(ifp) 1276 struct ifnet *ifp; 1277 { 1278 struct txp_softc *sc = ifp->if_softc; 1279 struct txp_tx_ring *r = &sc->sc_txhir; 1280 struct txp_tx_desc *txd; 1281 struct txp_frag_desc *fxd; 1282 struct mbuf *m, *m0; 1283 struct txp_swdesc *sd; 1284 u_int32_t firstprod, firstcnt, prod, cnt; 1285 struct ifvlan *ifv; 1286 1287 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1288 return; 1289 1290 prod = r->r_prod; 1291 cnt = r->r_cnt; 1292 1293 while (1) { 1294 IF_DEQUEUE(&ifp->if_snd, m); 1295 if (m == NULL) 1296 break; 1297 1298 firstprod = prod; 1299 firstcnt = cnt; 1300 1301 sd = sc->sc_txd + prod; 1302 sd->sd_mbuf = m; 1303 1304 if ((TX_ENTRIES - cnt) < 4) 1305 goto oactive; 1306 1307 txd = r->r_desc + prod; 1308 1309 txd->tx_flags = TX_FLAGS_TYPE_DATA; 1310 txd->tx_numdesc = 0; 1311 txd->tx_addrlo = 0; 1312 txd->tx_addrhi = 0; 1313 txd->tx_totlen = 0; 1314 txd->tx_pflags = 0; 1315 1316 if (++prod == TX_ENTRIES) 1317 prod = 0; 1318 1319 if (++cnt >= (TX_ENTRIES - 4)) 1320 goto oactive; 1321 1322 if ((m->m_flags & (M_PROTO1|M_PKTHDR)) == (M_PROTO1|M_PKTHDR) && 1323 m->m_pkthdr.rcvif != NULL) { 1324 ifv = m->m_pkthdr.rcvif->if_softc; 1325 txd->tx_pflags = TX_PFLAGS_VLAN | 1326 (htons(ifv->ifv_tag) << TX_PFLAGS_VLANTAG_S); 1327 } 1328 1329 if (m->m_pkthdr.csum_flags & CSUM_IP) 1330 txd->tx_pflags |= TX_PFLAGS_IPCKSUM; 1331 1332 #if 0 1333 if (m->m_pkthdr.csum_flags & CSUM_TCP) 1334 txd->tx_pflags |= TX_PFLAGS_TCPCKSUM; 1335 if (m->m_pkthdr.csum_flags & CSUM_UDP) 1336 txd->tx_pflags |= TX_PFLAGS_UDPCKSUM; 1337 #endif 1338 1339 fxd = (struct txp_frag_desc *)(r->r_desc + prod); 1340 for (m0 = m; m0 != NULL; m0 = m0->m_next) { 1341 if (m0->m_len == 0) 1342 continue; 1343 if (++cnt >= (TX_ENTRIES - 4)) 1344 goto oactive; 1345 1346 txd->tx_numdesc++; 1347 1348 fxd->frag_flags = FRAG_FLAGS_TYPE_FRAG; 1349 fxd->frag_rsvd1 = 0; 1350 fxd->frag_len = m0->m_len; 1351 fxd->frag_addrlo = vtophys(mtod(m0, vm_offset_t)); 1352 fxd->frag_addrhi = 0; 1353 fxd->frag_rsvd2 = 0; 1354 1355 if (++prod == TX_ENTRIES) { 1356 fxd = (struct txp_frag_desc *)r->r_desc; 1357 prod = 0; 1358 } else 1359 fxd++; 1360 1361 } 1362 1363 ifp->if_timer = 5; 1364 1365 if (ifp->if_bpf) 1366 bpf_mtap(ifp, m); 1367 WRITE_REG(sc, r->r_reg, TXP_IDX2OFFSET(prod)); 1368 } 1369 1370 r->r_prod = prod; 1371 r->r_cnt = cnt; 1372 return; 1373 1374 oactive: 1375 ifp->if_flags |= IFF_OACTIVE; 1376 r->r_prod = firstprod; 1377 r->r_cnt = firstcnt; 1378 IF_PREPEND(&ifp->if_snd, m); 1379 return; 1380 } 1381 1382 /* 1383 * Handle simple commands sent to the typhoon 1384 */ 1385 static int 1386 txp_command(sc, id, in1, in2, in3, out1, out2, out3, wait) 1387 struct txp_softc *sc; 1388 u_int16_t id, in1, *out1; 1389 u_int32_t in2, in3, *out2, *out3; 1390 int wait; 1391 { 1392 struct txp_rsp_desc *rsp = NULL; 1393 1394 if (txp_command2(sc, id, in1, in2, in3, NULL, 0, &rsp, wait)) 1395 return (-1); 1396 1397 if (!wait) 1398 return (0); 1399 1400 if (out1 != NULL) 1401 *out1 = rsp->rsp_par1; 1402 if (out2 != NULL) 1403 *out2 = rsp->rsp_par2; 1404 if (out3 != NULL) 1405 *out3 = rsp->rsp_par3; 1406 free(rsp, M_DEVBUF); 1407 return (0); 1408 } 1409 1410 static int 1411 txp_command2(sc, id, in1, in2, in3, in_extp, in_extn, rspp, wait) 1412 struct txp_softc *sc; 1413 u_int16_t id, in1; 1414 u_int32_t in2, in3; 1415 struct txp_ext_desc *in_extp; 1416 u_int8_t in_extn; 1417 struct txp_rsp_desc **rspp; 1418 int wait; 1419 { 1420 struct txp_hostvar *hv = sc->sc_hostvar; 1421 struct txp_cmd_desc *cmd; 1422 struct txp_ext_desc *ext; 1423 u_int32_t idx, i; 1424 u_int16_t seq; 1425 1426 if (txp_cmd_desc_numfree(sc) < (in_extn + 1)) { 1427 device_printf(sc->sc_dev, "no free cmd descriptors\n"); 1428 return (-1); 1429 } 1430 1431 idx = sc->sc_cmdring.lastwrite; 1432 cmd = (struct txp_cmd_desc *)(((u_int8_t *)sc->sc_cmdring.base) + idx); 1433 bzero(cmd, sizeof(*cmd)); 1434 1435 cmd->cmd_numdesc = in_extn; 1436 cmd->cmd_seq = seq = sc->sc_seq++; 1437 cmd->cmd_id = id; 1438 cmd->cmd_par1 = in1; 1439 cmd->cmd_par2 = in2; 1440 cmd->cmd_par3 = in3; 1441 cmd->cmd_flags = CMD_FLAGS_TYPE_CMD | 1442 (wait ? CMD_FLAGS_RESP : 0) | CMD_FLAGS_VALID; 1443 1444 idx += sizeof(struct txp_cmd_desc); 1445 if (idx == sc->sc_cmdring.size) 1446 idx = 0; 1447 1448 for (i = 0; i < in_extn; i++) { 1449 ext = (struct txp_ext_desc *)(((u_int8_t *)sc->sc_cmdring.base) + idx); 1450 bcopy(in_extp, ext, sizeof(struct txp_ext_desc)); 1451 in_extp++; 1452 idx += sizeof(struct txp_cmd_desc); 1453 if (idx == sc->sc_cmdring.size) 1454 idx = 0; 1455 } 1456 1457 sc->sc_cmdring.lastwrite = idx; 1458 1459 WRITE_REG(sc, TXP_H2A_2, sc->sc_cmdring.lastwrite); 1460 1461 if (!wait) 1462 return (0); 1463 1464 for (i = 0; i < 10000; i++) { 1465 idx = hv->hv_resp_read_idx; 1466 if (idx != hv->hv_resp_write_idx) { 1467 *rspp = NULL; 1468 if (txp_response(sc, idx, id, seq, rspp)) 1469 return (-1); 1470 if (*rspp != NULL) 1471 break; 1472 } 1473 DELAY(50); 1474 } 1475 if (i == 1000 || (*rspp) == NULL) { 1476 device_printf(sc->sc_dev, "0x%x command failed\n", id); 1477 return (-1); 1478 } 1479 1480 return (0); 1481 } 1482 1483 static int 1484 txp_response(sc, ridx, id, seq, rspp) 1485 struct txp_softc *sc; 1486 u_int32_t ridx; 1487 u_int16_t id; 1488 u_int16_t seq; 1489 struct txp_rsp_desc **rspp; 1490 { 1491 struct txp_hostvar *hv = sc->sc_hostvar; 1492 struct txp_rsp_desc *rsp; 1493 1494 while (ridx != hv->hv_resp_write_idx) { 1495 rsp = (struct txp_rsp_desc *)(((u_int8_t *)sc->sc_rspring.base) + ridx); 1496 1497 if (id == rsp->rsp_id && rsp->rsp_seq == seq) { 1498 *rspp = (struct txp_rsp_desc *)malloc( 1499 sizeof(struct txp_rsp_desc) * (rsp->rsp_numdesc + 1), 1500 M_DEVBUF, M_NOWAIT); 1501 if ((*rspp) == NULL) 1502 return (-1); 1503 txp_rsp_fixup(sc, rsp, *rspp); 1504 return (0); 1505 } 1506 1507 if (rsp->rsp_flags & RSP_FLAGS_ERROR) { 1508 device_printf(sc->sc_dev, "response error!\n"); 1509 txp_rsp_fixup(sc, rsp, NULL); 1510 ridx = hv->hv_resp_read_idx; 1511 continue; 1512 } 1513 1514 switch (rsp->rsp_id) { 1515 case TXP_CMD_CYCLE_STATISTICS: 1516 case TXP_CMD_MEDIA_STATUS_READ: 1517 break; 1518 case TXP_CMD_HELLO_RESPONSE: 1519 device_printf(sc->sc_dev, "hello\n"); 1520 break; 1521 default: 1522 device_printf(sc->sc_dev, "unknown id(0x%x)\n", 1523 rsp->rsp_id); 1524 } 1525 1526 txp_rsp_fixup(sc, rsp, NULL); 1527 ridx = hv->hv_resp_read_idx; 1528 hv->hv_resp_read_idx = ridx; 1529 } 1530 1531 return (0); 1532 } 1533 1534 static void 1535 txp_rsp_fixup(sc, rsp, dst) 1536 struct txp_softc *sc; 1537 struct txp_rsp_desc *rsp, *dst; 1538 { 1539 struct txp_rsp_desc *src = rsp; 1540 struct txp_hostvar *hv = sc->sc_hostvar; 1541 u_int32_t i, ridx; 1542 1543 ridx = hv->hv_resp_read_idx; 1544 1545 for (i = 0; i < rsp->rsp_numdesc + 1; i++) { 1546 if (dst != NULL) 1547 bcopy(src, dst++, sizeof(struct txp_rsp_desc)); 1548 ridx += sizeof(struct txp_rsp_desc); 1549 if (ridx == sc->sc_rspring.size) { 1550 src = sc->sc_rspring.base; 1551 ridx = 0; 1552 } else 1553 src++; 1554 sc->sc_rspring.lastwrite = hv->hv_resp_read_idx = ridx; 1555 } 1556 1557 hv->hv_resp_read_idx = ridx; 1558 } 1559 1560 static int 1561 txp_cmd_desc_numfree(sc) 1562 struct txp_softc *sc; 1563 { 1564 struct txp_hostvar *hv = sc->sc_hostvar; 1565 struct txp_boot_record *br = sc->sc_boot; 1566 u_int32_t widx, ridx, nfree; 1567 1568 widx = sc->sc_cmdring.lastwrite; 1569 ridx = hv->hv_cmd_read_idx; 1570 1571 if (widx == ridx) { 1572 /* Ring is completely free */ 1573 nfree = br->br_cmd_siz - sizeof(struct txp_cmd_desc); 1574 } else { 1575 if (widx > ridx) 1576 nfree = br->br_cmd_siz - 1577 (widx - ridx + sizeof(struct txp_cmd_desc)); 1578 else 1579 nfree = ridx - widx - sizeof(struct txp_cmd_desc); 1580 } 1581 1582 return (nfree / sizeof(struct txp_cmd_desc)); 1583 } 1584 1585 static void 1586 txp_stop(sc) 1587 struct txp_softc *sc; 1588 { 1589 struct ifnet *ifp; 1590 1591 ifp = &sc->sc_arpcom.ac_if; 1592 1593 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1594 1595 untimeout(txp_tick, sc, sc->sc_tick); 1596 1597 txp_command(sc, TXP_CMD_TX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 1); 1598 txp_command(sc, TXP_CMD_RX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 1); 1599 1600 txp_rxring_empty(sc); 1601 1602 return; 1603 } 1604 1605 static void 1606 txp_watchdog(ifp) 1607 struct ifnet *ifp; 1608 { 1609 return; 1610 } 1611 1612 static int 1613 txp_ifmedia_upd(ifp) 1614 struct ifnet *ifp; 1615 { 1616 struct txp_softc *sc = ifp->if_softc; 1617 struct ifmedia *ifm = &sc->sc_ifmedia; 1618 u_int16_t new_xcvr; 1619 1620 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 1621 return (EINVAL); 1622 1623 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_10_T) { 1624 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1625 new_xcvr = TXP_XCVR_10_FDX; 1626 else 1627 new_xcvr = TXP_XCVR_10_HDX; 1628 } else if (IFM_SUBTYPE(ifm->ifm_media) == IFM_100_TX) { 1629 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1630 new_xcvr = TXP_XCVR_100_FDX; 1631 else 1632 new_xcvr = TXP_XCVR_100_HDX; 1633 } else if (IFM_SUBTYPE(ifm->ifm_media) == IFM_AUTO) { 1634 new_xcvr = TXP_XCVR_AUTO; 1635 } else 1636 return (EINVAL); 1637 1638 /* nothing to do */ 1639 if (sc->sc_xcvr == new_xcvr) 1640 return (0); 1641 1642 txp_command(sc, TXP_CMD_XCVR_SELECT, new_xcvr, 0, 0, 1643 NULL, NULL, NULL, 0); 1644 sc->sc_xcvr = new_xcvr; 1645 1646 return (0); 1647 } 1648 1649 static void 1650 txp_ifmedia_sts(ifp, ifmr) 1651 struct ifnet *ifp; 1652 struct ifmediareq *ifmr; 1653 { 1654 struct txp_softc *sc = ifp->if_softc; 1655 struct ifmedia *ifm = &sc->sc_ifmedia; 1656 u_int16_t bmsr, bmcr, anlpar; 1657 1658 ifmr->ifm_status = IFM_AVALID; 1659 ifmr->ifm_active = IFM_ETHER; 1660 1661 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_BMSR, 0, 1662 &bmsr, NULL, NULL, 1)) 1663 goto bail; 1664 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_BMSR, 0, 1665 &bmsr, NULL, NULL, 1)) 1666 goto bail; 1667 1668 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_BMCR, 0, 1669 &bmcr, NULL, NULL, 1)) 1670 goto bail; 1671 1672 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_ANLPAR, 0, 1673 &anlpar, NULL, NULL, 1)) 1674 goto bail; 1675 1676 if (bmsr & BMSR_LINK) 1677 ifmr->ifm_status |= IFM_ACTIVE; 1678 1679 if (bmcr & BMCR_ISO) { 1680 ifmr->ifm_active |= IFM_NONE; 1681 ifmr->ifm_status = 0; 1682 return; 1683 } 1684 1685 if (bmcr & BMCR_LOOP) 1686 ifmr->ifm_active |= IFM_LOOP; 1687 1688 if (bmcr & BMCR_AUTOEN) { 1689 if ((bmsr & BMSR_ACOMP) == 0) { 1690 ifmr->ifm_active |= IFM_NONE; 1691 return; 1692 } 1693 1694 if (anlpar & ANLPAR_T4) 1695 ifmr->ifm_active |= IFM_100_T4; 1696 else if (anlpar & ANLPAR_TX_FD) 1697 ifmr->ifm_active |= IFM_100_TX|IFM_FDX; 1698 else if (anlpar & ANLPAR_TX) 1699 ifmr->ifm_active |= IFM_100_TX; 1700 else if (anlpar & ANLPAR_10_FD) 1701 ifmr->ifm_active |= IFM_10_T|IFM_FDX; 1702 else if (anlpar & ANLPAR_10) 1703 ifmr->ifm_active |= IFM_10_T; 1704 else 1705 ifmr->ifm_active |= IFM_NONE; 1706 } else 1707 ifmr->ifm_active = ifm->ifm_cur->ifm_media; 1708 return; 1709 1710 bail: 1711 ifmr->ifm_active |= IFM_NONE; 1712 ifmr->ifm_status &= ~IFM_AVALID; 1713 } 1714 1715 #ifdef TXP_DEBUG 1716 static void 1717 txp_show_descriptor(d) 1718 void *d; 1719 { 1720 struct txp_cmd_desc *cmd = d; 1721 struct txp_rsp_desc *rsp = d; 1722 struct txp_tx_desc *txd = d; 1723 struct txp_frag_desc *frgd = d; 1724 1725 switch (cmd->cmd_flags & CMD_FLAGS_TYPE_M) { 1726 case CMD_FLAGS_TYPE_CMD: 1727 /* command descriptor */ 1728 printf("[cmd flags 0x%x num %d id %d seq %d par1 0x%x par2 0x%x par3 0x%x]\n", 1729 cmd->cmd_flags, cmd->cmd_numdesc, cmd->cmd_id, cmd->cmd_seq, 1730 cmd->cmd_par1, cmd->cmd_par2, cmd->cmd_par3); 1731 break; 1732 case CMD_FLAGS_TYPE_RESP: 1733 /* response descriptor */ 1734 printf("[rsp flags 0x%x num %d id %d seq %d par1 0x%x par2 0x%x par3 0x%x]\n", 1735 rsp->rsp_flags, rsp->rsp_numdesc, rsp->rsp_id, rsp->rsp_seq, 1736 rsp->rsp_par1, rsp->rsp_par2, rsp->rsp_par3); 1737 break; 1738 case CMD_FLAGS_TYPE_DATA: 1739 /* data header (assuming tx for now) */ 1740 printf("[data flags 0x%x num %d totlen %d addr 0x%x/0x%x pflags 0x%x]", 1741 txd->tx_flags, txd->tx_numdesc, txd->tx_totlen, 1742 txd->tx_addrlo, txd->tx_addrhi, txd->tx_pflags); 1743 break; 1744 case CMD_FLAGS_TYPE_FRAG: 1745 /* fragment descriptor */ 1746 printf("[frag flags 0x%x rsvd1 0x%x len %d addr 0x%x/0x%x rsvd2 0x%x]", 1747 frgd->frag_flags, frgd->frag_rsvd1, frgd->frag_len, 1748 frgd->frag_addrlo, frgd->frag_addrhi, frgd->frag_rsvd2); 1749 break; 1750 default: 1751 printf("[unknown(%x) flags 0x%x num %d id %d seq %d par1 0x%x par2 0x%x par3 0x%x]\n", 1752 cmd->cmd_flags & CMD_FLAGS_TYPE_M, 1753 cmd->cmd_flags, cmd->cmd_numdesc, cmd->cmd_id, cmd->cmd_seq, 1754 cmd->cmd_par1, cmd->cmd_par2, cmd->cmd_par3); 1755 break; 1756 } 1757 } 1758 #endif 1759 1760 static void 1761 txp_set_filter(sc) 1762 struct txp_softc *sc; 1763 { 1764 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1765 u_int32_t crc, carry, hashbit, hash[2]; 1766 u_int16_t filter; 1767 u_int8_t octet; 1768 int i, j, mcnt = 0; 1769 struct ifmultiaddr *ifma; 1770 char *enm; 1771 1772 if (ifp->if_flags & IFF_PROMISC) { 1773 filter = TXP_RXFILT_PROMISC; 1774 goto setit; 1775 } 1776 1777 filter = TXP_RXFILT_DIRECT; 1778 1779 if (ifp->if_flags & IFF_BROADCAST) 1780 filter |= TXP_RXFILT_BROADCAST; 1781 1782 if (ifp->if_flags & IFF_ALLMULTI) 1783 filter |= TXP_RXFILT_ALLMULTI; 1784 else { 1785 hash[0] = hash[1] = 0; 1786 1787 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 1788 ifma = ifma->ifma_link.le_next) { 1789 if (ifma->ifma_addr->sa_family != AF_LINK) 1790 continue; 1791 1792 enm = LLADDR((struct sockaddr_dl *)ifma->ifma_addr); 1793 mcnt++; 1794 crc = 0xffffffff; 1795 1796 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1797 octet = enm[i]; 1798 for (j = 0; j < 8; j++) { 1799 carry = ((crc & 0x80000000) ? 1 : 0) ^ 1800 (octet & 1); 1801 crc <<= 1; 1802 octet >>= 1; 1803 if (carry) 1804 crc = (crc ^ TXP_POLYNOMIAL) | 1805 carry; 1806 } 1807 } 1808 hashbit = (u_int16_t)(crc & (64 - 1)); 1809 hash[hashbit / 32] |= (1 << hashbit % 32); 1810 } 1811 1812 if (mcnt > 0) { 1813 filter |= TXP_RXFILT_HASHMULTI; 1814 txp_command(sc, TXP_CMD_MCAST_HASH_MASK_WRITE, 1815 2, hash[0], hash[1], NULL, NULL, NULL, 0); 1816 } 1817 } 1818 1819 setit: 1820 1821 txp_command(sc, TXP_CMD_RX_FILTER_WRITE, filter, 0, 0, 1822 NULL, NULL, NULL, 1); 1823 1824 return; 1825 } 1826 1827 static void 1828 txp_capabilities(sc) 1829 struct txp_softc *sc; 1830 { 1831 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1832 struct txp_rsp_desc *rsp = NULL; 1833 struct txp_ext_desc *ext; 1834 1835 if (txp_command2(sc, TXP_CMD_OFFLOAD_READ, 0, 0, 0, NULL, 0, &rsp, 1)) 1836 goto out; 1837 1838 if (rsp->rsp_numdesc != 1) 1839 goto out; 1840 ext = (struct txp_ext_desc *)(rsp + 1); 1841 1842 sc->sc_tx_capability = ext->ext_1 & OFFLOAD_MASK; 1843 sc->sc_rx_capability = ext->ext_2 & OFFLOAD_MASK; 1844 ifp->if_capabilities = 0; 1845 1846 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_VLAN) { 1847 sc->sc_tx_capability |= OFFLOAD_VLAN; 1848 sc->sc_rx_capability |= OFFLOAD_VLAN; 1849 } 1850 1851 #if 0 1852 /* not ready yet */ 1853 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_IPSEC) { 1854 sc->sc_tx_capability |= OFFLOAD_IPSEC; 1855 sc->sc_rx_capability |= OFFLOAD_IPSEC; 1856 ifp->if_capabilities |= IFCAP_IPSEC; 1857 } 1858 #endif 1859 1860 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_IPCKSUM) { 1861 sc->sc_tx_capability |= OFFLOAD_IPCKSUM; 1862 sc->sc_rx_capability |= OFFLOAD_IPCKSUM; 1863 ifp->if_capabilities |= IFCAP_HWCSUM; 1864 ifp->if_hwassist |= CSUM_IP; 1865 } 1866 1867 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_TCPCKSUM) { 1868 #if 0 1869 sc->sc_tx_capability |= OFFLOAD_TCPCKSUM; 1870 #endif 1871 sc->sc_rx_capability |= OFFLOAD_TCPCKSUM; 1872 ifp->if_capabilities |= IFCAP_HWCSUM; 1873 } 1874 1875 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_UDPCKSUM) { 1876 #if 0 1877 sc->sc_tx_capability |= OFFLOAD_UDPCKSUM; 1878 #endif 1879 sc->sc_rx_capability |= OFFLOAD_UDPCKSUM; 1880 ifp->if_capabilities |= IFCAP_HWCSUM; 1881 } 1882 ifp->if_capenable = ifp->if_capabilities; 1883 1884 if (txp_command(sc, TXP_CMD_OFFLOAD_WRITE, 0, 1885 sc->sc_tx_capability, sc->sc_rx_capability, NULL, NULL, NULL, 1)) 1886 goto out; 1887 1888 out: 1889 if (rsp != NULL) 1890 free(rsp, M_DEVBUF); 1891 1892 return; 1893 } 1894