1 /* $OpenBSD: if_txp.c,v 1.48 2001/06/27 06:34:50 kjc Exp $ */ 2 /* $FreeBSD: src/sys/dev/txp/if_txp.c,v 1.4.2.4 2001/12/14 19:50:43 jlemon Exp $ */ 3 4 /* 5 * Copyright (c) 2001 6 * Jason L. Wright <jason@thought.net>, Theo de Raadt, and 7 * Aaron Campbell <aaron@monkey.org>. All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by Jason L. Wright, 20 * Theo de Raadt and Aaron Campbell. 21 * 4. Neither the name of the author nor the names of any co-contributors 22 * may be used to endorse or promote products derived from this software 23 * without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR 26 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 27 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 28 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 35 * THE POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Driver for 3c990 (Typhoon) Ethernet ASIC 40 */ 41 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 #include <sys/sockio.h> 45 #include <sys/mbuf.h> 46 #include <sys/malloc.h> 47 #include <sys/kernel.h> 48 #include <sys/socket.h> 49 #include <sys/serialize.h> 50 #include <sys/bus.h> 51 #include <sys/rman.h> 52 #include <sys/thread2.h> 53 #include <sys/interrupt.h> 54 55 #include <net/if.h> 56 #include <net/ifq_var.h> 57 #include <net/if_arp.h> 58 #include <net/ethernet.h> 59 #include <net/if_dl.h> 60 #include <net/if_types.h> 61 #include <net/vlan/if_vlan_var.h> 62 #include <net/vlan/if_vlan_ether.h> 63 64 #include <netinet/in.h> 65 #include <netinet/in_systm.h> 66 #include <netinet/in_var.h> 67 #include <netinet/ip.h> 68 #include <netinet/if_ether.h> 69 #include <sys/in_cksum.h> 70 71 #include <net/if_media.h> 72 73 #include <net/bpf.h> 74 75 #include <vm/vm.h> /* for vtophys */ 76 #include <vm/pmap.h> /* for vtophys */ 77 78 #include "../mii_layer/mii.h" 79 #include "../mii_layer/miivar.h" 80 81 #include <bus/pci/pcidevs.h> 82 #include <bus/pci/pcireg.h> 83 #include <bus/pci/pcivar.h> 84 85 #define TXP_USEIOSPACE 86 #define __STRICT_ALIGNMENT 87 88 #include "if_txpreg.h" 89 #include "3c990img.h" 90 91 /* 92 * Various supported device vendors/types and their names. 93 */ 94 static struct txp_type txp_devs[] = { 95 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990TX95, 96 "3Com 3cR990-TX-95 Etherlink with 3XP Processor" }, 97 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990TX97, 98 "3Com 3cR990-TX-97 Etherlink with 3XP Processor" }, 99 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C990B, 100 "3Com 3cR990B-TXM Etherlink with 3XP Processor" }, 101 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990SVR95, 102 "3Com 3cR990-SRV-95 Etherlink Server with 3XP Processor" }, 103 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990SVR97, 104 "3Com 3cR990-SRV-97 Etherlink Server with 3XP Processor" }, 105 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C990BSVR, 106 "3Com 3cR990B-SRV Etherlink Server with 3XP Processor" }, 107 { 0, 0, NULL } 108 }; 109 110 static int txp_probe (device_t); 111 static int txp_attach (device_t); 112 static int txp_detach (device_t); 113 static void txp_intr (void *); 114 static void txp_tick (void *); 115 static int txp_shutdown (device_t); 116 static int txp_ioctl (struct ifnet *, u_long, caddr_t, struct ucred *); 117 static void txp_start (struct ifnet *); 118 static void txp_stop (struct txp_softc *); 119 static void txp_init (void *); 120 static void txp_watchdog (struct ifnet *); 121 122 static void txp_release_resources (device_t); 123 static int txp_chip_init (struct txp_softc *); 124 static int txp_reset_adapter (struct txp_softc *); 125 static int txp_download_fw (struct txp_softc *); 126 static int txp_download_fw_wait (struct txp_softc *); 127 static int txp_download_fw_section (struct txp_softc *, 128 struct txp_fw_section_header *, int); 129 static int txp_alloc_rings (struct txp_softc *); 130 static int txp_rxring_fill (struct txp_softc *); 131 static void txp_rxring_empty (struct txp_softc *); 132 static void txp_set_filter (struct txp_softc *); 133 134 static int txp_cmd_desc_numfree (struct txp_softc *); 135 static int txp_command (struct txp_softc *, u_int16_t, u_int16_t, u_int32_t, 136 u_int32_t, u_int16_t *, u_int32_t *, u_int32_t *, int); 137 static int txp_command2 (struct txp_softc *, u_int16_t, u_int16_t, 138 u_int32_t, u_int32_t, struct txp_ext_desc *, u_int8_t, 139 struct txp_rsp_desc **, int); 140 static int txp_response (struct txp_softc *, u_int32_t, u_int16_t, u_int16_t, 141 struct txp_rsp_desc **); 142 static void txp_rsp_fixup (struct txp_softc *, struct txp_rsp_desc *, 143 struct txp_rsp_desc *); 144 static void txp_capabilities (struct txp_softc *); 145 146 static void txp_ifmedia_sts (struct ifnet *, struct ifmediareq *); 147 static int txp_ifmedia_upd (struct ifnet *); 148 #ifdef TXP_DEBUG 149 static void txp_show_descriptor (void *); 150 #endif 151 static void txp_tx_reclaim (struct txp_softc *, struct txp_tx_ring *); 152 static void txp_rxbuf_reclaim (struct txp_softc *); 153 static void txp_rx_reclaim (struct txp_softc *, struct txp_rx_ring *); 154 155 #ifdef TXP_USEIOSPACE 156 #define TXP_RES SYS_RES_IOPORT 157 #define TXP_RID TXP_PCI_LOIO 158 #else 159 #define TXP_RES SYS_RES_MEMORY 160 #define TXP_RID TXP_PCI_LOMEM 161 #endif 162 163 static device_method_t txp_methods[] = { 164 /* Device interface */ 165 DEVMETHOD(device_probe, txp_probe), 166 DEVMETHOD(device_attach, txp_attach), 167 DEVMETHOD(device_detach, txp_detach), 168 DEVMETHOD(device_shutdown, txp_shutdown), 169 { 0, 0 } 170 }; 171 172 static driver_t txp_driver = { 173 "txp", 174 txp_methods, 175 sizeof(struct txp_softc) 176 }; 177 178 static devclass_t txp_devclass; 179 180 DECLARE_DUMMY_MODULE(if_txp); 181 DRIVER_MODULE(if_txp, pci, txp_driver, txp_devclass, NULL, NULL); 182 183 static int 184 txp_probe(device_t dev) 185 { 186 struct txp_type *t; 187 uint16_t vid, did; 188 189 vid = pci_get_vendor(dev); 190 did = pci_get_device(dev); 191 192 for (t = txp_devs; t->txp_name != NULL; ++t) { 193 if ((vid == t->txp_vid) && (did == t->txp_did)) { 194 device_set_desc(dev, t->txp_name); 195 return(0); 196 } 197 } 198 199 return(ENXIO); 200 } 201 202 static int 203 txp_attach(device_t dev) 204 { 205 struct txp_softc *sc; 206 struct ifnet *ifp; 207 uint16_t p1; 208 uint32_t p2; 209 uint8_t enaddr[ETHER_ADDR_LEN]; 210 int error = 0, rid; 211 212 sc = device_get_softc(dev); 213 callout_init(&sc->txp_stat_timer); 214 215 ifp = &sc->sc_arpcom.ac_if; 216 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 217 218 pci_enable_busmaster(dev); 219 220 rid = TXP_RID; 221 sc->sc_res = bus_alloc_resource_any(dev, TXP_RES, &rid, RF_ACTIVE); 222 223 if (sc->sc_res == NULL) { 224 device_printf(dev, "couldn't map ports/memory\n"); 225 return(ENXIO); 226 } 227 228 sc->sc_bt = rman_get_bustag(sc->sc_res); 229 sc->sc_bh = rman_get_bushandle(sc->sc_res); 230 231 /* Allocate interrupt */ 232 rid = 0; 233 sc->sc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 234 RF_SHAREABLE | RF_ACTIVE); 235 236 if (sc->sc_irq == NULL) { 237 device_printf(dev, "couldn't map interrupt\n"); 238 error = ENXIO; 239 goto fail; 240 } 241 242 if (txp_chip_init(sc)) { 243 error = ENXIO; 244 goto fail; 245 } 246 247 sc->sc_fwbuf = contigmalloc(32768, M_DEVBUF, 248 M_WAITOK, 0, 0xffffffff, PAGE_SIZE, 0); 249 error = txp_download_fw(sc); 250 contigfree(sc->sc_fwbuf, 32768, M_DEVBUF); 251 sc->sc_fwbuf = NULL; 252 253 if (error) 254 goto fail; 255 256 sc->sc_ldata = contigmalloc(sizeof(struct txp_ldata), M_DEVBUF, 257 M_WAITOK | M_ZERO, 0, 0xffffffff, PAGE_SIZE, 0); 258 259 if (txp_alloc_rings(sc)) { 260 error = ENXIO; 261 goto fail; 262 } 263 264 if (txp_command(sc, TXP_CMD_MAX_PKT_SIZE_WRITE, TXP_MAX_PKTLEN, 0, 0, 265 NULL, NULL, NULL, 1)) { 266 error = ENXIO; 267 goto fail; 268 } 269 270 if (txp_command(sc, TXP_CMD_STATION_ADDRESS_READ, 0, 0, 0, 271 &p1, &p2, NULL, 1)) { 272 error = ENXIO; 273 goto fail; 274 } 275 276 txp_set_filter(sc); 277 278 enaddr[0] = ((uint8_t *)&p1)[1]; 279 enaddr[1] = ((uint8_t *)&p1)[0]; 280 enaddr[2] = ((uint8_t *)&p2)[3]; 281 enaddr[3] = ((uint8_t *)&p2)[2]; 282 enaddr[4] = ((uint8_t *)&p2)[1]; 283 enaddr[5] = ((uint8_t *)&p2)[0]; 284 285 ifmedia_init(&sc->sc_ifmedia, 0, txp_ifmedia_upd, txp_ifmedia_sts); 286 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_10_T, 0, NULL); 287 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_10_T|IFM_HDX, 0, NULL); 288 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL); 289 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_100_TX, 0, NULL); 290 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_100_TX|IFM_HDX, 0, NULL); 291 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_100_TX|IFM_FDX, 0, NULL); 292 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 293 294 sc->sc_xcvr = TXP_XCVR_AUTO; 295 txp_command(sc, TXP_CMD_XCVR_SELECT, TXP_XCVR_AUTO, 0, 0, 296 NULL, NULL, NULL, 0); 297 ifmedia_set(&sc->sc_ifmedia, IFM_ETHER|IFM_AUTO); 298 299 ifp->if_softc = sc; 300 ifp->if_mtu = ETHERMTU; 301 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 302 ifp->if_ioctl = txp_ioctl; 303 ifp->if_start = txp_start; 304 ifp->if_watchdog = txp_watchdog; 305 ifp->if_init = txp_init; 306 ifp->if_baudrate = 100000000; 307 ifq_set_maxlen(&ifp->if_snd, TX_ENTRIES); 308 ifq_set_ready(&ifp->if_snd); 309 ifp->if_hwassist = 0; 310 txp_capabilities(sc); 311 312 ether_ifattach(ifp, enaddr, NULL); 313 314 error = bus_setup_intr(dev, sc->sc_irq, INTR_MPSAFE, 315 txp_intr, sc, &sc->sc_intrhand, 316 ifp->if_serializer); 317 if (error) { 318 device_printf(dev, "couldn't set up irq\n"); 319 ether_ifdetach(ifp); 320 goto fail; 321 } 322 323 ifp->if_cpuid = rman_get_cpuid(sc->sc_irq); 324 KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus); 325 326 return(0); 327 328 fail: 329 txp_release_resources(dev); 330 return(error); 331 } 332 333 static int 334 txp_detach(device_t dev) 335 { 336 struct txp_softc *sc = device_get_softc(dev); 337 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 338 int i; 339 340 lwkt_serialize_enter(ifp->if_serializer); 341 342 txp_stop(sc); 343 txp_shutdown(dev); 344 bus_teardown_intr(dev, sc->sc_irq, sc->sc_intrhand); 345 346 lwkt_serialize_exit(ifp->if_serializer); 347 348 ifmedia_removeall(&sc->sc_ifmedia); 349 ether_ifdetach(ifp); 350 351 for (i = 0; i < RXBUF_ENTRIES; i++) 352 kfree(sc->sc_rxbufs[i].rb_sd, M_DEVBUF); 353 354 txp_release_resources(dev); 355 356 return(0); 357 } 358 359 static void 360 txp_release_resources(device_t dev) 361 { 362 struct txp_softc *sc; 363 364 sc = device_get_softc(dev); 365 366 if (sc->sc_irq != NULL) 367 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq); 368 369 if (sc->sc_res != NULL) 370 bus_release_resource(dev, TXP_RES, TXP_RID, sc->sc_res); 371 372 if (sc->sc_ldata != NULL) 373 contigfree(sc->sc_ldata, sizeof(struct txp_ldata), M_DEVBUF); 374 375 return; 376 } 377 378 static int 379 txp_chip_init(struct txp_softc *sc) 380 { 381 /* disable interrupts */ 382 WRITE_REG(sc, TXP_IER, 0); 383 WRITE_REG(sc, TXP_IMR, 384 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 385 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 386 TXP_INT_LATCH); 387 388 /* ack all interrupts */ 389 WRITE_REG(sc, TXP_ISR, TXP_INT_RESERVED | TXP_INT_LATCH | 390 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 | 391 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 392 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 393 TXP_INT_A2H_3 | TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0); 394 395 if (txp_reset_adapter(sc)) 396 return (-1); 397 398 /* disable interrupts */ 399 WRITE_REG(sc, TXP_IER, 0); 400 WRITE_REG(sc, TXP_IMR, 401 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 402 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 403 TXP_INT_LATCH); 404 405 /* ack all interrupts */ 406 WRITE_REG(sc, TXP_ISR, TXP_INT_RESERVED | TXP_INT_LATCH | 407 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 | 408 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 409 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 410 TXP_INT_A2H_3 | TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0); 411 412 return (0); 413 } 414 415 static int 416 txp_reset_adapter(struct txp_softc *sc) 417 { 418 u_int32_t r; 419 int i; 420 421 WRITE_REG(sc, TXP_SRR, TXP_SRR_ALL); 422 DELAY(1000); 423 WRITE_REG(sc, TXP_SRR, 0); 424 425 /* Should wait max 6 seconds */ 426 for (i = 0; i < 6000; i++) { 427 r = READ_REG(sc, TXP_A2H_0); 428 if (r == STAT_WAITING_FOR_HOST_REQUEST) 429 break; 430 DELAY(1000); 431 } 432 433 if (r != STAT_WAITING_FOR_HOST_REQUEST) { 434 if_printf(&sc->sc_arpcom.ac_if, "reset hung\n"); 435 return (-1); 436 } 437 438 return (0); 439 } 440 441 static int 442 txp_download_fw(struct txp_softc *sc) 443 { 444 struct txp_fw_file_header *fileheader; 445 struct txp_fw_section_header *secthead; 446 int sect; 447 u_int32_t r, i, ier, imr; 448 449 ier = READ_REG(sc, TXP_IER); 450 WRITE_REG(sc, TXP_IER, ier | TXP_INT_A2H_0); 451 452 imr = READ_REG(sc, TXP_IMR); 453 WRITE_REG(sc, TXP_IMR, imr | TXP_INT_A2H_0); 454 455 for (i = 0; i < 10000; i++) { 456 r = READ_REG(sc, TXP_A2H_0); 457 if (r == STAT_WAITING_FOR_HOST_REQUEST) 458 break; 459 DELAY(50); 460 } 461 if (r != STAT_WAITING_FOR_HOST_REQUEST) { 462 if_printf(&sc->sc_arpcom.ac_if, 463 "not waiting for host request\n"); 464 return (-1); 465 } 466 467 /* Ack the status */ 468 WRITE_REG(sc, TXP_ISR, TXP_INT_A2H_0); 469 470 fileheader = (struct txp_fw_file_header *)tc990image; 471 if (bcmp("TYPHOON", fileheader->magicid, sizeof(fileheader->magicid))) { 472 if_printf(&sc->sc_arpcom.ac_if, "fw invalid magic\n"); 473 return (-1); 474 } 475 476 /* Tell boot firmware to get ready for image */ 477 WRITE_REG(sc, TXP_H2A_1, fileheader->addr); 478 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_RUNTIME_IMAGE); 479 480 if (txp_download_fw_wait(sc)) { 481 if_printf(&sc->sc_arpcom.ac_if, "fw wait failed, initial\n"); 482 return (-1); 483 } 484 485 secthead = (struct txp_fw_section_header *)(((u_int8_t *)tc990image) + 486 sizeof(struct txp_fw_file_header)); 487 488 for (sect = 0; sect < fileheader->nsections; sect++) { 489 if (txp_download_fw_section(sc, secthead, sect)) 490 return (-1); 491 secthead = (struct txp_fw_section_header *) 492 (((u_int8_t *)secthead) + secthead->nbytes + 493 sizeof(*secthead)); 494 } 495 496 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_DOWNLOAD_COMPLETE); 497 498 for (i = 0; i < 10000; i++) { 499 r = READ_REG(sc, TXP_A2H_0); 500 if (r == STAT_WAITING_FOR_BOOT) 501 break; 502 DELAY(50); 503 } 504 if (r != STAT_WAITING_FOR_BOOT) { 505 if_printf(&sc->sc_arpcom.ac_if, "not waiting for boot\n"); 506 return (-1); 507 } 508 509 WRITE_REG(sc, TXP_IER, ier); 510 WRITE_REG(sc, TXP_IMR, imr); 511 512 return (0); 513 } 514 515 static int 516 txp_download_fw_wait(struct txp_softc *sc) 517 { 518 u_int32_t i, r; 519 520 for (i = 0; i < 10000; i++) { 521 r = READ_REG(sc, TXP_ISR); 522 if (r & TXP_INT_A2H_0) 523 break; 524 DELAY(50); 525 } 526 527 if (!(r & TXP_INT_A2H_0)) { 528 if_printf(&sc->sc_arpcom.ac_if, "fw wait failed comm0\n"); 529 return (-1); 530 } 531 532 WRITE_REG(sc, TXP_ISR, TXP_INT_A2H_0); 533 534 r = READ_REG(sc, TXP_A2H_0); 535 if (r != STAT_WAITING_FOR_SEGMENT) { 536 if_printf(&sc->sc_arpcom.ac_if, "fw not waiting for segment\n"); 537 return (-1); 538 } 539 return (0); 540 } 541 542 static int 543 txp_download_fw_section(struct txp_softc *sc, 544 struct txp_fw_section_header *sect, int sectnum) 545 { 546 vm_offset_t dma; 547 int rseg, err = 0; 548 struct mbuf m; 549 u_int16_t csum; 550 551 /* Skip zero length sections */ 552 if (sect->nbytes == 0) 553 return (0); 554 555 /* Make sure we aren't past the end of the image */ 556 rseg = ((u_int8_t *)sect) - ((u_int8_t *)tc990image); 557 if (rseg >= sizeof(tc990image)) { 558 if_printf(&sc->sc_arpcom.ac_if, "fw invalid section address, " 559 "section %d\n", sectnum); 560 return (-1); 561 } 562 563 /* Make sure this section doesn't go past the end */ 564 rseg += sect->nbytes; 565 if (rseg >= sizeof(tc990image)) { 566 if_printf(&sc->sc_arpcom.ac_if, "fw truncated section %d\n", 567 sectnum); 568 return (-1); 569 } 570 571 bcopy(((u_int8_t *)sect) + sizeof(*sect), sc->sc_fwbuf, sect->nbytes); 572 dma = vtophys(sc->sc_fwbuf); 573 574 /* 575 * dummy up mbuf and verify section checksum 576 */ 577 m.m_type = MT_DATA; 578 m.m_next = m.m_nextpkt = NULL; 579 m.m_len = sect->nbytes; 580 m.m_data = sc->sc_fwbuf; 581 m.m_flags = 0; 582 csum = in_cksum(&m, sect->nbytes); 583 if (csum != sect->cksum) { 584 if_printf(&sc->sc_arpcom.ac_if, "fw section %d, bad " 585 "cksum (expected 0x%x got 0x%x)\n", 586 sectnum, sect->cksum, csum); 587 err = -1; 588 goto bail; 589 } 590 591 WRITE_REG(sc, TXP_H2A_1, sect->nbytes); 592 WRITE_REG(sc, TXP_H2A_2, sect->cksum); 593 WRITE_REG(sc, TXP_H2A_3, sect->addr); 594 WRITE_REG(sc, TXP_H2A_4, 0); 595 WRITE_REG(sc, TXP_H2A_5, dma & 0xffffffff); 596 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_SEGMENT_AVAILABLE); 597 598 if (txp_download_fw_wait(sc)) { 599 if_printf(&sc->sc_arpcom.ac_if, "fw wait failed, " 600 "section %d\n", sectnum); 601 err = -1; 602 } 603 604 bail: 605 return (err); 606 } 607 608 static void 609 txp_intr(void *vsc) 610 { 611 struct txp_softc *sc = vsc; 612 struct txp_hostvar *hv = sc->sc_hostvar; 613 u_int32_t isr; 614 615 /* mask all interrupts */ 616 WRITE_REG(sc, TXP_IMR, TXP_INT_RESERVED | TXP_INT_SELF | 617 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 | 618 TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0 | 619 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 620 TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | TXP_INT_LATCH); 621 622 isr = READ_REG(sc, TXP_ISR); 623 while (isr) { 624 WRITE_REG(sc, TXP_ISR, isr); 625 626 if ((*sc->sc_rxhir.r_roff) != (*sc->sc_rxhir.r_woff)) 627 txp_rx_reclaim(sc, &sc->sc_rxhir); 628 if ((*sc->sc_rxlor.r_roff) != (*sc->sc_rxlor.r_woff)) 629 txp_rx_reclaim(sc, &sc->sc_rxlor); 630 631 if (hv->hv_rx_buf_write_idx == hv->hv_rx_buf_read_idx) 632 txp_rxbuf_reclaim(sc); 633 634 if (sc->sc_txhir.r_cnt && (sc->sc_txhir.r_cons != 635 TXP_OFFSET2IDX(*(sc->sc_txhir.r_off)))) 636 txp_tx_reclaim(sc, &sc->sc_txhir); 637 638 if (sc->sc_txlor.r_cnt && (sc->sc_txlor.r_cons != 639 TXP_OFFSET2IDX(*(sc->sc_txlor.r_off)))) 640 txp_tx_reclaim(sc, &sc->sc_txlor); 641 642 isr = READ_REG(sc, TXP_ISR); 643 } 644 645 /* unmask all interrupts */ 646 WRITE_REG(sc, TXP_IMR, TXP_INT_A2H_3); 647 648 if_devstart(&sc->sc_arpcom.ac_if); 649 } 650 651 static void 652 txp_rx_reclaim(struct txp_softc *sc, struct txp_rx_ring *r) 653 { 654 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 655 struct txp_rx_desc *rxd; 656 struct mbuf *m; 657 struct txp_swdesc *sd = NULL; 658 u_int32_t roff, woff; 659 660 roff = *r->r_roff; 661 woff = *r->r_woff; 662 rxd = r->r_desc + (roff / sizeof(struct txp_rx_desc)); 663 664 while (roff != woff) { 665 666 if (rxd->rx_flags & RX_FLAGS_ERROR) { 667 if_printf(ifp, "error 0x%x\n", rxd->rx_stat); 668 ifp->if_ierrors++; 669 goto next; 670 } 671 672 /* retrieve stashed pointer */ 673 sd = rxd->rx_sd; 674 675 m = sd->sd_mbuf; 676 sd->sd_mbuf = NULL; 677 678 m->m_pkthdr.len = m->m_len = rxd->rx_len; 679 680 #ifdef __STRICT_ALIGNMENT 681 { 682 /* 683 * XXX Nice chip, except it won't accept "off by 2" 684 * buffers, so we're force to copy. Supposedly 685 * this will be fixed in a newer firmware rev 686 * and this will be temporary. 687 */ 688 struct mbuf *mnew; 689 690 MGETHDR(mnew, MB_DONTWAIT, MT_DATA); 691 if (mnew == NULL) { 692 m_freem(m); 693 goto next; 694 } 695 if (m->m_len > (MHLEN - 2)) { 696 MCLGET(mnew, MB_DONTWAIT); 697 if (!(mnew->m_flags & M_EXT)) { 698 m_freem(mnew); 699 m_freem(m); 700 goto next; 701 } 702 } 703 mnew->m_pkthdr.rcvif = ifp; 704 m_adj(mnew, 2); 705 mnew->m_pkthdr.len = mnew->m_len = m->m_len; 706 m_copydata(m, 0, m->m_pkthdr.len, mtod(mnew, caddr_t)); 707 m_freem(m); 708 m = mnew; 709 } 710 #endif 711 712 if (rxd->rx_stat & RX_STAT_IPCKSUMBAD) 713 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 714 else if (rxd->rx_stat & RX_STAT_IPCKSUMGOOD) 715 m->m_pkthdr.csum_flags |= 716 CSUM_IP_CHECKED|CSUM_IP_VALID; 717 718 if ((rxd->rx_stat & RX_STAT_TCPCKSUMGOOD) || 719 (rxd->rx_stat & RX_STAT_UDPCKSUMGOOD)) { 720 m->m_pkthdr.csum_flags |= 721 CSUM_DATA_VALID|CSUM_PSEUDO_HDR| 722 CSUM_FRAG_NOT_CHECKED; 723 m->m_pkthdr.csum_data = 0xffff; 724 } 725 726 if (rxd->rx_stat & RX_STAT_VLAN) { 727 m->m_flags |= M_VLANTAG; 728 m->m_pkthdr.ether_vlantag = htons(rxd->rx_vlan >> 16); 729 } 730 ifp->if_input(ifp, m); 731 732 next: 733 734 roff += sizeof(struct txp_rx_desc); 735 if (roff == (RX_ENTRIES * sizeof(struct txp_rx_desc))) { 736 roff = 0; 737 rxd = r->r_desc; 738 } else 739 rxd++; 740 woff = *r->r_woff; 741 } 742 743 *r->r_roff = woff; 744 745 return; 746 } 747 748 static void 749 txp_rxbuf_reclaim(struct txp_softc *sc) 750 { 751 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 752 struct txp_hostvar *hv = sc->sc_hostvar; 753 struct txp_rxbuf_desc *rbd; 754 struct txp_swdesc *sd; 755 u_int32_t i; 756 757 if (!(ifp->if_flags & IFF_RUNNING)) 758 return; 759 760 i = sc->sc_rxbufprod; 761 rbd = sc->sc_rxbufs + i; 762 763 while (1) { 764 sd = rbd->rb_sd; 765 if (sd->sd_mbuf != NULL) 766 break; 767 768 MGETHDR(sd->sd_mbuf, MB_DONTWAIT, MT_DATA); 769 if (sd->sd_mbuf == NULL) 770 goto err_sd; 771 772 MCLGET(sd->sd_mbuf, MB_DONTWAIT); 773 if ((sd->sd_mbuf->m_flags & M_EXT) == 0) 774 goto err_mbuf; 775 sd->sd_mbuf->m_pkthdr.rcvif = ifp; 776 sd->sd_mbuf->m_pkthdr.len = sd->sd_mbuf->m_len = MCLBYTES; 777 778 rbd->rb_paddrlo = vtophys(mtod(sd->sd_mbuf, vm_offset_t)) 779 & 0xffffffff; 780 rbd->rb_paddrhi = 0; 781 782 hv->hv_rx_buf_write_idx = TXP_IDX2OFFSET(i); 783 784 if (++i == RXBUF_ENTRIES) { 785 i = 0; 786 rbd = sc->sc_rxbufs; 787 } else 788 rbd++; 789 } 790 791 sc->sc_rxbufprod = i; 792 793 return; 794 795 err_mbuf: 796 m_freem(sd->sd_mbuf); 797 err_sd: 798 kfree(sd, M_DEVBUF); 799 } 800 801 /* 802 * Reclaim mbufs and entries from a transmit ring. 803 */ 804 static void 805 txp_tx_reclaim(struct txp_softc *sc, struct txp_tx_ring *r) 806 { 807 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 808 u_int32_t idx = TXP_OFFSET2IDX(*(r->r_off)); 809 u_int32_t cons = r->r_cons, cnt = r->r_cnt; 810 struct txp_tx_desc *txd = r->r_desc + cons; 811 struct txp_swdesc *sd = sc->sc_txd + cons; 812 struct mbuf *m; 813 814 while (cons != idx) { 815 if (cnt == 0) 816 break; 817 818 if ((txd->tx_flags & TX_FLAGS_TYPE_M) == 819 TX_FLAGS_TYPE_DATA) { 820 m = sd->sd_mbuf; 821 if (m != NULL) { 822 m_freem(m); 823 txd->tx_addrlo = 0; 824 txd->tx_addrhi = 0; 825 ifp->if_opackets++; 826 } 827 } 828 ifp->if_flags &= ~IFF_OACTIVE; 829 830 if (++cons == TX_ENTRIES) { 831 txd = r->r_desc; 832 cons = 0; 833 sd = sc->sc_txd; 834 } else { 835 txd++; 836 sd++; 837 } 838 839 cnt--; 840 } 841 842 r->r_cons = cons; 843 r->r_cnt = cnt; 844 if (cnt == 0) 845 ifp->if_timer = 0; 846 } 847 848 static int 849 txp_shutdown(device_t dev) 850 { 851 struct txp_softc *sc; 852 struct ifnet *ifp; 853 854 sc = device_get_softc(dev); 855 ifp = &sc->sc_arpcom.ac_if; 856 lwkt_serialize_enter(ifp->if_serializer); 857 858 /* mask all interrupts */ 859 WRITE_REG(sc, TXP_IMR, 860 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 861 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 862 TXP_INT_LATCH); 863 864 txp_command(sc, TXP_CMD_TX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 0); 865 txp_command(sc, TXP_CMD_RX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 0); 866 txp_command(sc, TXP_CMD_HALT, 0, 0, 0, NULL, NULL, NULL, 0); 867 868 lwkt_serialize_exit(ifp->if_serializer); 869 return(0); 870 } 871 872 static int 873 txp_alloc_rings(struct txp_softc *sc) 874 { 875 struct txp_boot_record *boot; 876 struct txp_ldata *ld; 877 u_int32_t r; 878 int i; 879 880 ld = sc->sc_ldata; 881 boot = &ld->txp_boot; 882 883 /* boot record */ 884 sc->sc_boot = boot; 885 886 /* host variables */ 887 bzero(&ld->txp_hostvar, sizeof(struct txp_hostvar)); 888 boot->br_hostvar_lo = vtophys(&ld->txp_hostvar); 889 boot->br_hostvar_hi = 0; 890 sc->sc_hostvar = (struct txp_hostvar *)&ld->txp_hostvar; 891 892 /* hi priority tx ring */ 893 boot->br_txhipri_lo = vtophys(&ld->txp_txhiring); 894 boot->br_txhipri_hi = 0; 895 boot->br_txhipri_siz = TX_ENTRIES * sizeof(struct txp_tx_desc); 896 sc->sc_txhir.r_reg = TXP_H2A_1; 897 sc->sc_txhir.r_desc = (struct txp_tx_desc *)&ld->txp_txhiring; 898 sc->sc_txhir.r_cons = sc->sc_txhir.r_prod = sc->sc_txhir.r_cnt = 0; 899 sc->sc_txhir.r_off = &sc->sc_hostvar->hv_tx_hi_desc_read_idx; 900 901 /* lo priority tx ring */ 902 boot->br_txlopri_lo = vtophys(&ld->txp_txloring); 903 boot->br_txlopri_hi = 0; 904 boot->br_txlopri_siz = TX_ENTRIES * sizeof(struct txp_tx_desc); 905 sc->sc_txlor.r_reg = TXP_H2A_3; 906 sc->sc_txlor.r_desc = (struct txp_tx_desc *)&ld->txp_txloring; 907 sc->sc_txlor.r_cons = sc->sc_txlor.r_prod = sc->sc_txlor.r_cnt = 0; 908 sc->sc_txlor.r_off = &sc->sc_hostvar->hv_tx_lo_desc_read_idx; 909 910 /* high priority rx ring */ 911 boot->br_rxhipri_lo = vtophys(&ld->txp_rxhiring); 912 boot->br_rxhipri_hi = 0; 913 boot->br_rxhipri_siz = RX_ENTRIES * sizeof(struct txp_rx_desc); 914 sc->sc_rxhir.r_desc = (struct txp_rx_desc *)&ld->txp_rxhiring; 915 sc->sc_rxhir.r_roff = &sc->sc_hostvar->hv_rx_hi_read_idx; 916 sc->sc_rxhir.r_woff = &sc->sc_hostvar->hv_rx_hi_write_idx; 917 918 /* low priority rx ring */ 919 boot->br_rxlopri_lo = vtophys(&ld->txp_rxloring); 920 boot->br_rxlopri_hi = 0; 921 boot->br_rxlopri_siz = RX_ENTRIES * sizeof(struct txp_rx_desc); 922 sc->sc_rxlor.r_desc = (struct txp_rx_desc *)&ld->txp_rxloring; 923 sc->sc_rxlor.r_roff = &sc->sc_hostvar->hv_rx_lo_read_idx; 924 sc->sc_rxlor.r_woff = &sc->sc_hostvar->hv_rx_lo_write_idx; 925 926 /* command ring */ 927 bzero(&ld->txp_cmdring, sizeof(struct txp_cmd_desc) * CMD_ENTRIES); 928 boot->br_cmd_lo = vtophys(&ld->txp_cmdring); 929 boot->br_cmd_hi = 0; 930 boot->br_cmd_siz = CMD_ENTRIES * sizeof(struct txp_cmd_desc); 931 sc->sc_cmdring.base = (struct txp_cmd_desc *)&ld->txp_cmdring; 932 sc->sc_cmdring.size = CMD_ENTRIES * sizeof(struct txp_cmd_desc); 933 sc->sc_cmdring.lastwrite = 0; 934 935 /* response ring */ 936 bzero(&ld->txp_rspring, sizeof(struct txp_rsp_desc) * RSP_ENTRIES); 937 boot->br_resp_lo = vtophys(&ld->txp_rspring); 938 boot->br_resp_hi = 0; 939 boot->br_resp_siz = CMD_ENTRIES * sizeof(struct txp_rsp_desc); 940 sc->sc_rspring.base = (struct txp_rsp_desc *)&ld->txp_rspring; 941 sc->sc_rspring.size = RSP_ENTRIES * sizeof(struct txp_rsp_desc); 942 sc->sc_rspring.lastwrite = 0; 943 944 /* receive buffer ring */ 945 boot->br_rxbuf_lo = vtophys(&ld->txp_rxbufs); 946 boot->br_rxbuf_hi = 0; 947 boot->br_rxbuf_siz = RXBUF_ENTRIES * sizeof(struct txp_rxbuf_desc); 948 sc->sc_rxbufs = (struct txp_rxbuf_desc *)&ld->txp_rxbufs; 949 950 for (i = 0; i < RXBUF_ENTRIES; i++) { 951 struct txp_swdesc *sd; 952 if (sc->sc_rxbufs[i].rb_sd != NULL) 953 continue; 954 sc->sc_rxbufs[i].rb_sd = kmalloc(sizeof(struct txp_swdesc), 955 M_DEVBUF, M_WAITOK); 956 sd = sc->sc_rxbufs[i].rb_sd; 957 sd->sd_mbuf = NULL; 958 } 959 sc->sc_rxbufprod = 0; 960 961 /* zero dma */ 962 bzero(&ld->txp_zero, sizeof(u_int32_t)); 963 boot->br_zero_lo = vtophys(&ld->txp_zero); 964 boot->br_zero_hi = 0; 965 966 /* See if it's waiting for boot, and try to boot it */ 967 for (i = 0; i < 10000; i++) { 968 r = READ_REG(sc, TXP_A2H_0); 969 if (r == STAT_WAITING_FOR_BOOT) 970 break; 971 DELAY(50); 972 } 973 974 if (r != STAT_WAITING_FOR_BOOT) { 975 if_printf(&sc->sc_arpcom.ac_if, "not waiting for boot\n"); 976 return(ENXIO); 977 } 978 979 WRITE_REG(sc, TXP_H2A_2, 0); 980 WRITE_REG(sc, TXP_H2A_1, vtophys(sc->sc_boot)); 981 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_REGISTER_BOOT_RECORD); 982 983 /* See if it booted */ 984 for (i = 0; i < 10000; i++) { 985 r = READ_REG(sc, TXP_A2H_0); 986 if (r == STAT_RUNNING) 987 break; 988 DELAY(50); 989 } 990 if (r != STAT_RUNNING) { 991 if_printf(&sc->sc_arpcom.ac_if, "fw not running\n"); 992 return(ENXIO); 993 } 994 995 /* Clear TX and CMD ring write registers */ 996 WRITE_REG(sc, TXP_H2A_1, TXP_BOOTCMD_NULL); 997 WRITE_REG(sc, TXP_H2A_2, TXP_BOOTCMD_NULL); 998 WRITE_REG(sc, TXP_H2A_3, TXP_BOOTCMD_NULL); 999 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_NULL); 1000 1001 return (0); 1002 } 1003 1004 static int 1005 txp_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr) 1006 { 1007 struct txp_softc *sc = ifp->if_softc; 1008 struct ifreq *ifr = (struct ifreq *)data; 1009 int error = 0; 1010 1011 switch(command) { 1012 case SIOCSIFFLAGS: 1013 if (ifp->if_flags & IFF_UP) { 1014 txp_init(sc); 1015 } else { 1016 if (ifp->if_flags & IFF_RUNNING) 1017 txp_stop(sc); 1018 } 1019 break; 1020 case SIOCADDMULTI: 1021 case SIOCDELMULTI: 1022 /* 1023 * Multicast list has changed; set the hardware 1024 * filter accordingly. 1025 */ 1026 txp_set_filter(sc); 1027 error = 0; 1028 break; 1029 case SIOCGIFMEDIA: 1030 case SIOCSIFMEDIA: 1031 error = ifmedia_ioctl(ifp, ifr, &sc->sc_ifmedia, command); 1032 break; 1033 default: 1034 error = ether_ioctl(ifp, command, data); 1035 break; 1036 } 1037 return(error); 1038 } 1039 1040 static int 1041 txp_rxring_fill(struct txp_softc *sc) 1042 { 1043 int i; 1044 struct ifnet *ifp; 1045 struct txp_swdesc *sd; 1046 1047 ifp = &sc->sc_arpcom.ac_if; 1048 1049 for (i = 0; i < RXBUF_ENTRIES; i++) { 1050 sd = sc->sc_rxbufs[i].rb_sd; 1051 MGETHDR(sd->sd_mbuf, MB_DONTWAIT, MT_DATA); 1052 if (sd->sd_mbuf == NULL) 1053 return(ENOBUFS); 1054 1055 MCLGET(sd->sd_mbuf, MB_DONTWAIT); 1056 if ((sd->sd_mbuf->m_flags & M_EXT) == 0) { 1057 m_freem(sd->sd_mbuf); 1058 return(ENOBUFS); 1059 } 1060 sd->sd_mbuf->m_pkthdr.len = sd->sd_mbuf->m_len = MCLBYTES; 1061 sd->sd_mbuf->m_pkthdr.rcvif = ifp; 1062 1063 sc->sc_rxbufs[i].rb_paddrlo = 1064 vtophys(mtod(sd->sd_mbuf, vm_offset_t)); 1065 sc->sc_rxbufs[i].rb_paddrhi = 0; 1066 } 1067 1068 sc->sc_hostvar->hv_rx_buf_write_idx = (RXBUF_ENTRIES - 1) * 1069 sizeof(struct txp_rxbuf_desc); 1070 1071 return(0); 1072 } 1073 1074 static void 1075 txp_rxring_empty(struct txp_softc *sc) 1076 { 1077 int i; 1078 struct txp_swdesc *sd; 1079 1080 if (sc->sc_rxbufs == NULL) 1081 return; 1082 1083 for (i = 0; i < RXBUF_ENTRIES; i++) { 1084 if (&sc->sc_rxbufs[i] == NULL) 1085 continue; 1086 sd = sc->sc_rxbufs[i].rb_sd; 1087 if (sd == NULL) 1088 continue; 1089 if (sd->sd_mbuf != NULL) { 1090 m_freem(sd->sd_mbuf); 1091 sd->sd_mbuf = NULL; 1092 } 1093 } 1094 1095 return; 1096 } 1097 1098 static void 1099 txp_init(void *xsc) 1100 { 1101 struct txp_softc *sc; 1102 struct ifnet *ifp; 1103 u_int16_t p1; 1104 u_int32_t p2; 1105 1106 sc = xsc; 1107 ifp = &sc->sc_arpcom.ac_if; 1108 1109 if (ifp->if_flags & IFF_RUNNING) 1110 return; 1111 1112 txp_stop(sc); 1113 1114 txp_command(sc, TXP_CMD_MAX_PKT_SIZE_WRITE, TXP_MAX_PKTLEN, 0, 0, 1115 NULL, NULL, NULL, 1); 1116 1117 /* Set station address. */ 1118 ((u_int8_t *)&p1)[1] = sc->sc_arpcom.ac_enaddr[0]; 1119 ((u_int8_t *)&p1)[0] = sc->sc_arpcom.ac_enaddr[1]; 1120 ((u_int8_t *)&p2)[3] = sc->sc_arpcom.ac_enaddr[2]; 1121 ((u_int8_t *)&p2)[2] = sc->sc_arpcom.ac_enaddr[3]; 1122 ((u_int8_t *)&p2)[1] = sc->sc_arpcom.ac_enaddr[4]; 1123 ((u_int8_t *)&p2)[0] = sc->sc_arpcom.ac_enaddr[5]; 1124 txp_command(sc, TXP_CMD_STATION_ADDRESS_WRITE, p1, p2, 0, 1125 NULL, NULL, NULL, 1); 1126 1127 txp_set_filter(sc); 1128 1129 txp_rxring_fill(sc); 1130 1131 txp_command(sc, TXP_CMD_TX_ENABLE, 0, 0, 0, NULL, NULL, NULL, 1); 1132 txp_command(sc, TXP_CMD_RX_ENABLE, 0, 0, 0, NULL, NULL, NULL, 1); 1133 1134 WRITE_REG(sc, TXP_IER, TXP_INT_RESERVED | TXP_INT_SELF | 1135 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 | 1136 TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0 | 1137 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 1138 TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | TXP_INT_LATCH); 1139 WRITE_REG(sc, TXP_IMR, TXP_INT_A2H_3); 1140 1141 ifp->if_flags |= IFF_RUNNING; 1142 ifp->if_flags &= ~IFF_OACTIVE; 1143 ifp->if_timer = 0; 1144 1145 callout_reset(&sc->txp_stat_timer, hz, txp_tick, sc); 1146 } 1147 1148 static void 1149 txp_tick(void *vsc) 1150 { 1151 struct txp_softc *sc = vsc; 1152 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1153 struct txp_rsp_desc *rsp = NULL; 1154 struct txp_ext_desc *ext; 1155 1156 lwkt_serialize_enter(ifp->if_serializer); 1157 txp_rxbuf_reclaim(sc); 1158 1159 if (txp_command2(sc, TXP_CMD_READ_STATISTICS, 0, 0, 0, NULL, 0, 1160 &rsp, 1)) 1161 goto out; 1162 if (rsp->rsp_numdesc != 6) 1163 goto out; 1164 if (txp_command(sc, TXP_CMD_CLEAR_STATISTICS, 0, 0, 0, 1165 NULL, NULL, NULL, 1)) 1166 goto out; 1167 ext = (struct txp_ext_desc *)(rsp + 1); 1168 1169 ifp->if_ierrors += ext[3].ext_2 + ext[3].ext_3 + ext[3].ext_4 + 1170 ext[4].ext_1 + ext[4].ext_4; 1171 ifp->if_oerrors += ext[0].ext_1 + ext[1].ext_1 + ext[1].ext_4 + 1172 ext[2].ext_1; 1173 ifp->if_collisions += ext[0].ext_2 + ext[0].ext_3 + ext[1].ext_2 + 1174 ext[1].ext_3; 1175 ifp->if_opackets += rsp->rsp_par2; 1176 ifp->if_ipackets += ext[2].ext_3; 1177 1178 out: 1179 if (rsp != NULL) 1180 kfree(rsp, M_DEVBUF); 1181 1182 callout_reset(&sc->txp_stat_timer, hz, txp_tick, sc); 1183 lwkt_serialize_exit(ifp->if_serializer); 1184 } 1185 1186 static void 1187 txp_start(struct ifnet *ifp) 1188 { 1189 struct txp_softc *sc = ifp->if_softc; 1190 struct txp_tx_ring *r = &sc->sc_txhir; 1191 struct txp_tx_desc *txd; 1192 struct txp_frag_desc *fxd; 1193 struct mbuf *m, *m0, *m_defragged; 1194 struct txp_swdesc *sd; 1195 u_int32_t firstprod, firstcnt, prod, cnt; 1196 1197 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1198 return; 1199 1200 prod = r->r_prod; 1201 cnt = r->r_cnt; 1202 1203 while (1) { 1204 int frag; 1205 1206 firstprod = prod; 1207 firstcnt = cnt; 1208 1209 if ((TX_ENTRIES - cnt) < 4) 1210 goto oactive; 1211 1212 m_defragged = NULL; 1213 m = ifq_dequeue(&ifp->if_snd, NULL); 1214 if (m == NULL) 1215 break; 1216 again: 1217 frag = 1; /* Extra desc */ 1218 for (m0 = m; m0 != NULL; m0 = m0->m_next) 1219 ++frag; 1220 if ((cnt + frag) >= (TX_ENTRIES - 4)) { 1221 if (m_defragged != NULL) { 1222 /* 1223 * Even after defragmentation, there 1224 * are still too many fragments, so 1225 * drop this packet. 1226 */ 1227 m_freem(m); 1228 goto oactive; 1229 } 1230 1231 m_defragged = m_defrag(m, MB_DONTWAIT); 1232 if (m_defragged == NULL) { 1233 m_freem(m); 1234 continue; 1235 } 1236 m = m_defragged; 1237 1238 /* Recount # of fragments */ 1239 goto again; 1240 } 1241 1242 sd = sc->sc_txd + prod; 1243 sd->sd_mbuf = m; 1244 1245 txd = r->r_desc + prod; 1246 txd->tx_flags = TX_FLAGS_TYPE_DATA; 1247 txd->tx_numdesc = 0; 1248 txd->tx_addrlo = 0; 1249 txd->tx_addrhi = 0; 1250 txd->tx_totlen = 0; 1251 txd->tx_pflags = 0; 1252 1253 if (++prod == TX_ENTRIES) 1254 prod = 0; 1255 1256 ++cnt; 1257 KASSERT(cnt < (TX_ENTRIES - 4), ("too many frag\n")); 1258 1259 if (m->m_flags & M_VLANTAG) { 1260 txd->tx_pflags = TX_PFLAGS_VLAN | 1261 (htons(m->m_pkthdr.ether_vlantag) << 1262 TX_PFLAGS_VLANTAG_S); 1263 } 1264 1265 if (m->m_pkthdr.csum_flags & CSUM_IP) 1266 txd->tx_pflags |= TX_PFLAGS_IPCKSUM; 1267 1268 #if 0 1269 if (m->m_pkthdr.csum_flags & CSUM_TCP) 1270 txd->tx_pflags |= TX_PFLAGS_TCPCKSUM; 1271 if (m->m_pkthdr.csum_flags & CSUM_UDP) 1272 txd->tx_pflags |= TX_PFLAGS_UDPCKSUM; 1273 #endif 1274 1275 fxd = (struct txp_frag_desc *)(r->r_desc + prod); 1276 for (m0 = m; m0 != NULL; m0 = m0->m_next) { 1277 if (m0->m_len == 0) 1278 continue; 1279 1280 ++cnt; 1281 KASSERT(cnt < (TX_ENTRIES - 4), ("too many frag\n")); 1282 1283 txd->tx_numdesc++; 1284 1285 fxd->frag_flags = FRAG_FLAGS_TYPE_FRAG; 1286 fxd->frag_rsvd1 = 0; 1287 fxd->frag_len = m0->m_len; 1288 fxd->frag_addrlo = vtophys(mtod(m0, vm_offset_t)); 1289 fxd->frag_addrhi = 0; 1290 fxd->frag_rsvd2 = 0; 1291 1292 if (++prod == TX_ENTRIES) { 1293 fxd = (struct txp_frag_desc *)r->r_desc; 1294 prod = 0; 1295 } else 1296 fxd++; 1297 } 1298 1299 ifp->if_timer = 5; 1300 1301 ETHER_BPF_MTAP(ifp, m); 1302 WRITE_REG(sc, r->r_reg, TXP_IDX2OFFSET(prod)); 1303 } 1304 1305 r->r_prod = prod; 1306 r->r_cnt = cnt; 1307 return; 1308 1309 oactive: 1310 ifp->if_flags |= IFF_OACTIVE; 1311 r->r_prod = firstprod; 1312 r->r_cnt = firstcnt; 1313 return; 1314 } 1315 1316 /* 1317 * Handle simple commands sent to the typhoon 1318 */ 1319 static int 1320 txp_command(struct txp_softc *sc, u_int16_t id, u_int16_t in1, u_int32_t in2, 1321 u_int32_t in3, u_int16_t *out1, u_int32_t *out2, u_int32_t *out3, 1322 int wait) 1323 { 1324 struct txp_rsp_desc *rsp = NULL; 1325 1326 if (txp_command2(sc, id, in1, in2, in3, NULL, 0, &rsp, wait)) 1327 return (-1); 1328 1329 if (!wait) 1330 return (0); 1331 1332 if (out1 != NULL) 1333 *out1 = rsp->rsp_par1; 1334 if (out2 != NULL) 1335 *out2 = rsp->rsp_par2; 1336 if (out3 != NULL) 1337 *out3 = rsp->rsp_par3; 1338 kfree(rsp, M_DEVBUF); 1339 return (0); 1340 } 1341 1342 static int 1343 txp_command2(struct txp_softc *sc, u_int16_t id, u_int16_t in1, u_int32_t in2, 1344 u_int32_t in3, struct txp_ext_desc *in_extp, u_int8_t in_extn, 1345 struct txp_rsp_desc **rspp, int wait) 1346 { 1347 struct txp_hostvar *hv = sc->sc_hostvar; 1348 struct txp_cmd_desc *cmd; 1349 struct txp_ext_desc *ext; 1350 u_int32_t idx, i; 1351 u_int16_t seq; 1352 1353 if (txp_cmd_desc_numfree(sc) < (in_extn + 1)) { 1354 if_printf(&sc->sc_arpcom.ac_if, "no free cmd descriptors\n"); 1355 return (-1); 1356 } 1357 1358 idx = sc->sc_cmdring.lastwrite; 1359 cmd = (struct txp_cmd_desc *)(((u_int8_t *)sc->sc_cmdring.base) + idx); 1360 bzero(cmd, sizeof(*cmd)); 1361 1362 cmd->cmd_numdesc = in_extn; 1363 cmd->cmd_seq = seq = sc->sc_seq++; 1364 cmd->cmd_id = id; 1365 cmd->cmd_par1 = in1; 1366 cmd->cmd_par2 = in2; 1367 cmd->cmd_par3 = in3; 1368 cmd->cmd_flags = CMD_FLAGS_TYPE_CMD | 1369 (wait ? CMD_FLAGS_RESP : 0) | CMD_FLAGS_VALID; 1370 1371 idx += sizeof(struct txp_cmd_desc); 1372 if (idx == sc->sc_cmdring.size) 1373 idx = 0; 1374 1375 for (i = 0; i < in_extn; i++) { 1376 ext = (struct txp_ext_desc *)(((u_int8_t *)sc->sc_cmdring.base) + idx); 1377 bcopy(in_extp, ext, sizeof(struct txp_ext_desc)); 1378 in_extp++; 1379 idx += sizeof(struct txp_cmd_desc); 1380 if (idx == sc->sc_cmdring.size) 1381 idx = 0; 1382 } 1383 1384 sc->sc_cmdring.lastwrite = idx; 1385 1386 WRITE_REG(sc, TXP_H2A_2, sc->sc_cmdring.lastwrite); 1387 1388 if (!wait) 1389 return (0); 1390 1391 for (i = 0; i < 10000; i++) { 1392 idx = hv->hv_resp_read_idx; 1393 if (idx != hv->hv_resp_write_idx) { 1394 *rspp = NULL; 1395 if (txp_response(sc, idx, id, seq, rspp)) 1396 return (-1); 1397 if (*rspp != NULL) 1398 break; 1399 } 1400 DELAY(50); 1401 } 1402 if (i == 1000 || (*rspp) == NULL) { 1403 if_printf(&sc->sc_arpcom.ac_if, "0x%x command failed\n", id); 1404 return (-1); 1405 } 1406 1407 return (0); 1408 } 1409 1410 static int 1411 txp_response(struct txp_softc *sc, u_int32_t ridx, u_int16_t id, u_int16_t seq, 1412 struct txp_rsp_desc **rspp) 1413 { 1414 struct txp_hostvar *hv = sc->sc_hostvar; 1415 struct txp_rsp_desc *rsp; 1416 1417 while (ridx != hv->hv_resp_write_idx) { 1418 rsp = (struct txp_rsp_desc *)(((u_int8_t *)sc->sc_rspring.base) + ridx); 1419 1420 if (id == rsp->rsp_id && rsp->rsp_seq == seq) { 1421 *rspp = (struct txp_rsp_desc *)kmalloc( 1422 sizeof(struct txp_rsp_desc) * (rsp->rsp_numdesc + 1), 1423 M_DEVBUF, M_INTWAIT); 1424 if ((*rspp) == NULL) 1425 return (-1); 1426 txp_rsp_fixup(sc, rsp, *rspp); 1427 return (0); 1428 } 1429 1430 if (rsp->rsp_flags & RSP_FLAGS_ERROR) { 1431 if_printf(&sc->sc_arpcom.ac_if, "response error!\n"); 1432 txp_rsp_fixup(sc, rsp, NULL); 1433 ridx = hv->hv_resp_read_idx; 1434 continue; 1435 } 1436 1437 switch (rsp->rsp_id) { 1438 case TXP_CMD_CYCLE_STATISTICS: 1439 case TXP_CMD_MEDIA_STATUS_READ: 1440 break; 1441 case TXP_CMD_HELLO_RESPONSE: 1442 if_printf(&sc->sc_arpcom.ac_if, "hello\n"); 1443 break; 1444 default: 1445 if_printf(&sc->sc_arpcom.ac_if, "unknown id(0x%x)\n", 1446 rsp->rsp_id); 1447 } 1448 1449 txp_rsp_fixup(sc, rsp, NULL); 1450 ridx = hv->hv_resp_read_idx; 1451 hv->hv_resp_read_idx = ridx; 1452 } 1453 1454 return (0); 1455 } 1456 1457 static void 1458 txp_rsp_fixup(struct txp_softc *sc, struct txp_rsp_desc *rsp, 1459 struct txp_rsp_desc *dst) 1460 { 1461 struct txp_rsp_desc *src = rsp; 1462 struct txp_hostvar *hv = sc->sc_hostvar; 1463 u_int32_t i, ridx; 1464 1465 ridx = hv->hv_resp_read_idx; 1466 1467 for (i = 0; i < rsp->rsp_numdesc + 1; i++) { 1468 if (dst != NULL) 1469 bcopy(src, dst++, sizeof(struct txp_rsp_desc)); 1470 ridx += sizeof(struct txp_rsp_desc); 1471 if (ridx == sc->sc_rspring.size) { 1472 src = sc->sc_rspring.base; 1473 ridx = 0; 1474 } else 1475 src++; 1476 sc->sc_rspring.lastwrite = hv->hv_resp_read_idx = ridx; 1477 } 1478 1479 hv->hv_resp_read_idx = ridx; 1480 } 1481 1482 static int 1483 txp_cmd_desc_numfree(struct txp_softc *sc) 1484 { 1485 struct txp_hostvar *hv = sc->sc_hostvar; 1486 struct txp_boot_record *br = sc->sc_boot; 1487 u_int32_t widx, ridx, nfree; 1488 1489 widx = sc->sc_cmdring.lastwrite; 1490 ridx = hv->hv_cmd_read_idx; 1491 1492 if (widx == ridx) { 1493 /* Ring is completely free */ 1494 nfree = br->br_cmd_siz - sizeof(struct txp_cmd_desc); 1495 } else { 1496 if (widx > ridx) 1497 nfree = br->br_cmd_siz - 1498 (widx - ridx + sizeof(struct txp_cmd_desc)); 1499 else 1500 nfree = ridx - widx - sizeof(struct txp_cmd_desc); 1501 } 1502 1503 return (nfree / sizeof(struct txp_cmd_desc)); 1504 } 1505 1506 static void 1507 txp_stop(struct txp_softc *sc) 1508 { 1509 struct ifnet *ifp; 1510 1511 ifp = &sc->sc_arpcom.ac_if; 1512 1513 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1514 1515 callout_stop(&sc->txp_stat_timer); 1516 1517 txp_command(sc, TXP_CMD_TX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 1); 1518 txp_command(sc, TXP_CMD_RX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 1); 1519 1520 txp_rxring_empty(sc); 1521 1522 return; 1523 } 1524 1525 static void 1526 txp_watchdog(struct ifnet *ifp) 1527 { 1528 return; 1529 } 1530 1531 static int 1532 txp_ifmedia_upd(struct ifnet *ifp) 1533 { 1534 struct txp_softc *sc = ifp->if_softc; 1535 struct ifmedia *ifm = &sc->sc_ifmedia; 1536 u_int16_t new_xcvr; 1537 1538 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 1539 return (EINVAL); 1540 1541 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_10_T) { 1542 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1543 new_xcvr = TXP_XCVR_10_FDX; 1544 else 1545 new_xcvr = TXP_XCVR_10_HDX; 1546 } else if (IFM_SUBTYPE(ifm->ifm_media) == IFM_100_TX) { 1547 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1548 new_xcvr = TXP_XCVR_100_FDX; 1549 else 1550 new_xcvr = TXP_XCVR_100_HDX; 1551 } else if (IFM_SUBTYPE(ifm->ifm_media) == IFM_AUTO) { 1552 new_xcvr = TXP_XCVR_AUTO; 1553 } else 1554 return (EINVAL); 1555 1556 /* nothing to do */ 1557 if (sc->sc_xcvr == new_xcvr) 1558 return (0); 1559 1560 txp_command(sc, TXP_CMD_XCVR_SELECT, new_xcvr, 0, 0, 1561 NULL, NULL, NULL, 0); 1562 sc->sc_xcvr = new_xcvr; 1563 1564 return (0); 1565 } 1566 1567 static void 1568 txp_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1569 { 1570 struct txp_softc *sc = ifp->if_softc; 1571 struct ifmedia *ifm = &sc->sc_ifmedia; 1572 u_int16_t bmsr, bmcr, anlpar; 1573 1574 ifmr->ifm_status = IFM_AVALID; 1575 ifmr->ifm_active = IFM_ETHER; 1576 1577 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_BMSR, 0, 1578 &bmsr, NULL, NULL, 1)) 1579 goto bail; 1580 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_BMSR, 0, 1581 &bmsr, NULL, NULL, 1)) 1582 goto bail; 1583 1584 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_BMCR, 0, 1585 &bmcr, NULL, NULL, 1)) 1586 goto bail; 1587 1588 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_ANLPAR, 0, 1589 &anlpar, NULL, NULL, 1)) 1590 goto bail; 1591 1592 if (bmsr & BMSR_LINK) 1593 ifmr->ifm_status |= IFM_ACTIVE; 1594 1595 if (bmcr & BMCR_ISO) { 1596 ifmr->ifm_active |= IFM_NONE; 1597 ifmr->ifm_status = 0; 1598 return; 1599 } 1600 1601 if (bmcr & BMCR_LOOP) 1602 ifmr->ifm_active |= IFM_LOOP; 1603 1604 if (bmcr & BMCR_AUTOEN) { 1605 if ((bmsr & BMSR_ACOMP) == 0) { 1606 ifmr->ifm_active |= IFM_NONE; 1607 return; 1608 } 1609 1610 if (anlpar & ANLPAR_T4) 1611 ifmr->ifm_active |= IFM_100_T4; 1612 else if (anlpar & ANLPAR_TX_FD) 1613 ifmr->ifm_active |= IFM_100_TX|IFM_FDX; 1614 else if (anlpar & ANLPAR_TX) 1615 ifmr->ifm_active |= IFM_100_TX; 1616 else if (anlpar & ANLPAR_10_FD) 1617 ifmr->ifm_active |= IFM_10_T|IFM_FDX; 1618 else if (anlpar & ANLPAR_10) 1619 ifmr->ifm_active |= IFM_10_T; 1620 else 1621 ifmr->ifm_active |= IFM_NONE; 1622 } else 1623 ifmr->ifm_active = ifm->ifm_cur->ifm_media; 1624 return; 1625 1626 bail: 1627 ifmr->ifm_active |= IFM_NONE; 1628 ifmr->ifm_status &= ~IFM_AVALID; 1629 } 1630 1631 #ifdef TXP_DEBUG 1632 static void 1633 txp_show_descriptor(void *d) 1634 { 1635 struct txp_cmd_desc *cmd = d; 1636 struct txp_rsp_desc *rsp = d; 1637 struct txp_tx_desc *txd = d; 1638 struct txp_frag_desc *frgd = d; 1639 1640 switch (cmd->cmd_flags & CMD_FLAGS_TYPE_M) { 1641 case CMD_FLAGS_TYPE_CMD: 1642 /* command descriptor */ 1643 kprintf("[cmd flags 0x%x num %d id %d seq %d par1 0x%x par2 0x%x par3 0x%x]\n", 1644 cmd->cmd_flags, cmd->cmd_numdesc, cmd->cmd_id, cmd->cmd_seq, 1645 cmd->cmd_par1, cmd->cmd_par2, cmd->cmd_par3); 1646 break; 1647 case CMD_FLAGS_TYPE_RESP: 1648 /* response descriptor */ 1649 kprintf("[rsp flags 0x%x num %d id %d seq %d par1 0x%x par2 0x%x par3 0x%x]\n", 1650 rsp->rsp_flags, rsp->rsp_numdesc, rsp->rsp_id, rsp->rsp_seq, 1651 rsp->rsp_par1, rsp->rsp_par2, rsp->rsp_par3); 1652 break; 1653 case CMD_FLAGS_TYPE_DATA: 1654 /* data header (assuming tx for now) */ 1655 kprintf("[data flags 0x%x num %d totlen %d addr 0x%x/0x%x pflags 0x%x]", 1656 txd->tx_flags, txd->tx_numdesc, txd->tx_totlen, 1657 txd->tx_addrlo, txd->tx_addrhi, txd->tx_pflags); 1658 break; 1659 case CMD_FLAGS_TYPE_FRAG: 1660 /* fragment descriptor */ 1661 kprintf("[frag flags 0x%x rsvd1 0x%x len %d addr 0x%x/0x%x rsvd2 0x%x]", 1662 frgd->frag_flags, frgd->frag_rsvd1, frgd->frag_len, 1663 frgd->frag_addrlo, frgd->frag_addrhi, frgd->frag_rsvd2); 1664 break; 1665 default: 1666 kprintf("[unknown(%x) flags 0x%x num %d id %d seq %d par1 0x%x par2 0x%x par3 0x%x]\n", 1667 cmd->cmd_flags & CMD_FLAGS_TYPE_M, 1668 cmd->cmd_flags, cmd->cmd_numdesc, cmd->cmd_id, cmd->cmd_seq, 1669 cmd->cmd_par1, cmd->cmd_par2, cmd->cmd_par3); 1670 break; 1671 } 1672 } 1673 #endif 1674 1675 static void 1676 txp_set_filter(struct txp_softc *sc) 1677 { 1678 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1679 uint16_t filter; 1680 struct ifmultiaddr *ifma; 1681 1682 if (ifp->if_flags & IFF_PROMISC) { 1683 filter = TXP_RXFILT_PROMISC; 1684 goto setit; 1685 } 1686 1687 filter = TXP_RXFILT_DIRECT; 1688 1689 if (ifp->if_flags & IFF_BROADCAST) 1690 filter |= TXP_RXFILT_BROADCAST; 1691 1692 if (ifp->if_flags & IFF_ALLMULTI) { 1693 filter |= TXP_RXFILT_ALLMULTI; 1694 } else { 1695 uint32_t hashbit, hash[2]; 1696 int mcnt = 0; 1697 1698 hash[0] = hash[1] = 0; 1699 1700 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1701 if (ifma->ifma_addr->sa_family != AF_LINK) 1702 continue; 1703 1704 mcnt++; 1705 hashbit = (uint16_t)(ether_crc32_be( 1706 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 1707 ETHER_ADDR_LEN) & (64 - 1)); 1708 hash[hashbit / 32] |= (1 << hashbit % 32); 1709 } 1710 1711 if (mcnt > 0) { 1712 filter |= TXP_RXFILT_HASHMULTI; 1713 txp_command(sc, TXP_CMD_MCAST_HASH_MASK_WRITE, 1714 2, hash[0], hash[1], NULL, NULL, NULL, 0); 1715 } 1716 } 1717 1718 setit: 1719 txp_command(sc, TXP_CMD_RX_FILTER_WRITE, filter, 0, 0, 1720 NULL, NULL, NULL, 1); 1721 } 1722 1723 static void 1724 txp_capabilities(struct txp_softc *sc) 1725 { 1726 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1727 struct txp_rsp_desc *rsp = NULL; 1728 struct txp_ext_desc *ext; 1729 1730 if (txp_command2(sc, TXP_CMD_OFFLOAD_READ, 0, 0, 0, NULL, 0, &rsp, 1)) 1731 goto out; 1732 1733 if (rsp->rsp_numdesc != 1) 1734 goto out; 1735 ext = (struct txp_ext_desc *)(rsp + 1); 1736 1737 sc->sc_tx_capability = ext->ext_1 & OFFLOAD_MASK; 1738 sc->sc_rx_capability = ext->ext_2 & OFFLOAD_MASK; 1739 ifp->if_capabilities = 0; 1740 1741 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_VLAN) { 1742 sc->sc_tx_capability |= OFFLOAD_VLAN; 1743 sc->sc_rx_capability |= OFFLOAD_VLAN; 1744 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING; 1745 } 1746 1747 #if 0 1748 /* not ready yet */ 1749 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_IPSEC) { 1750 sc->sc_tx_capability |= OFFLOAD_IPSEC; 1751 sc->sc_rx_capability |= OFFLOAD_IPSEC; 1752 ifp->if_capabilities |= IFCAP_IPSEC; 1753 } 1754 #endif 1755 1756 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_IPCKSUM) { 1757 sc->sc_tx_capability |= OFFLOAD_IPCKSUM; 1758 sc->sc_rx_capability |= OFFLOAD_IPCKSUM; 1759 ifp->if_capabilities |= IFCAP_HWCSUM; 1760 ifp->if_hwassist |= CSUM_IP; 1761 } 1762 1763 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_TCPCKSUM) { 1764 #if 0 1765 sc->sc_tx_capability |= OFFLOAD_TCPCKSUM; 1766 #endif 1767 sc->sc_rx_capability |= OFFLOAD_TCPCKSUM; 1768 ifp->if_capabilities |= IFCAP_HWCSUM; 1769 } 1770 1771 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_UDPCKSUM) { 1772 #if 0 1773 sc->sc_tx_capability |= OFFLOAD_UDPCKSUM; 1774 #endif 1775 sc->sc_rx_capability |= OFFLOAD_UDPCKSUM; 1776 ifp->if_capabilities |= IFCAP_HWCSUM; 1777 } 1778 ifp->if_capenable = ifp->if_capabilities; 1779 1780 if (txp_command(sc, TXP_CMD_OFFLOAD_WRITE, 0, 1781 sc->sc_tx_capability, sc->sc_rx_capability, NULL, NULL, NULL, 1)) 1782 goto out; 1783 1784 out: 1785 if (rsp != NULL) 1786 kfree(rsp, M_DEVBUF); 1787 1788 return; 1789 } 1790