1 /* 2 * Copyright (c) 1997, 1998 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: src/sys/pci/if_vr.c,v 1.26.2.13 2003/02/06 04:46:20 silby Exp $ 33 * $DragonFly: src/sys/dev/netif/vr/if_vr.c,v 1.14 2004/07/23 07:16:29 joerg Exp $ 34 * 35 * $FreeBSD: src/sys/pci/if_vr.c,v 1.26.2.13 2003/02/06 04:46:20 silby Exp $ 36 */ 37 38 /* 39 * VIA Rhine fast ethernet PCI NIC driver 40 * 41 * Supports various network adapters based on the VIA Rhine 42 * and Rhine II PCI controllers, including the D-Link DFE530TX. 43 * Datasheets are available at http://www.via.com.tw. 44 * 45 * Written by Bill Paul <wpaul@ctr.columbia.edu> 46 * Electrical Engineering Department 47 * Columbia University, New York City 48 */ 49 50 /* 51 * The VIA Rhine controllers are similar in some respects to the 52 * the DEC tulip chips, except less complicated. The controller 53 * uses an MII bus and an external physical layer interface. The 54 * receiver has a one entry perfect filter and a 64-bit hash table 55 * multicast filter. Transmit and receive descriptors are similar 56 * to the tulip. 57 * 58 * The Rhine has a serious flaw in its transmit DMA mechanism: 59 * transmit buffers must be longword aligned. Unfortunately, 60 * FreeBSD doesn't guarantee that mbufs will be filled in starting 61 * at longword boundaries, so we have to do a buffer copy before 62 * transmission. 63 */ 64 65 #include <sys/param.h> 66 #include <sys/systm.h> 67 #include <sys/sockio.h> 68 #include <sys/mbuf.h> 69 #include <sys/malloc.h> 70 #include <sys/kernel.h> 71 #include <sys/socket.h> 72 73 #include <net/if.h> 74 #include <net/if_arp.h> 75 #include <net/ethernet.h> 76 #include <net/if_dl.h> 77 #include <net/if_media.h> 78 79 #include <net/bpf.h> 80 81 #include <vm/vm.h> /* for vtophys */ 82 #include <vm/pmap.h> /* for vtophys */ 83 #include <machine/clock.h> /* for DELAY */ 84 #include <machine/bus_pio.h> 85 #include <machine/bus_memio.h> 86 #include <machine/bus.h> 87 #include <machine/resource.h> 88 #include <sys/bus.h> 89 #include <sys/rman.h> 90 91 #include "../mii_layer/mii.h" 92 #include "../mii_layer/miivar.h" 93 94 #include <bus/pci/pcireg.h> 95 #include <bus/pci/pcivar.h> 96 97 #define VR_USEIOSPACE 98 99 #include "if_vrreg.h" 100 101 /* "controller miibus0" required. See GENERIC if you get errors here. */ 102 #include "miibus_if.h" 103 104 #undef VR_USESWSHIFT 105 106 /* 107 * Various supported device vendors/types and their names. 108 */ 109 static struct vr_type vr_devs[] = { 110 { VIA_VENDORID, VIA_DEVICEID_RHINE, 111 "VIA VT3043 Rhine I 10/100BaseTX" }, 112 { VIA_VENDORID, VIA_DEVICEID_RHINE_II, 113 "VIA VT86C100A Rhine II 10/100BaseTX" }, 114 { VIA_VENDORID, VIA_DEVICEID_RHINE_II_2, 115 "VIA VT6102 Rhine II 10/100BaseTX" }, 116 { VIA_VENDORID, VIA_DEVICEID_RHINE_III, 117 "VIA VT6105 Rhine III 10/100BaseTX" }, 118 { VIA_VENDORID, VIA_DEVICEID_RHINE_III_M, 119 "VIA VT6105M Rhine III 10/100BaseTX" }, 120 { DELTA_VENDORID, DELTA_DEVICEID_RHINE_II, 121 "Delta Electronics Rhine II 10/100BaseTX" }, 122 { ADDTRON_VENDORID, ADDTRON_DEVICEID_RHINE_II, 123 "Addtron Technology Rhine II 10/100BaseTX" }, 124 { 0, 0, NULL } 125 }; 126 127 static int vr_probe (device_t); 128 static int vr_attach (device_t); 129 static int vr_detach (device_t); 130 131 static int vr_newbuf (struct vr_softc *, 132 struct vr_chain_onefrag *, 133 struct mbuf *); 134 static int vr_encap (struct vr_softc *, struct vr_chain *, 135 struct mbuf * ); 136 137 static void vr_rxeof (struct vr_softc *); 138 static void vr_rxeoc (struct vr_softc *); 139 static void vr_txeof (struct vr_softc *); 140 static void vr_txeoc (struct vr_softc *); 141 static void vr_tick (void *); 142 static void vr_intr (void *); 143 static void vr_start (struct ifnet *); 144 static int vr_ioctl (struct ifnet *, u_long, caddr_t, 145 struct ucred *); 146 static void vr_init (void *); 147 static void vr_stop (struct vr_softc *); 148 static void vr_watchdog (struct ifnet *); 149 static void vr_shutdown (device_t); 150 static int vr_ifmedia_upd (struct ifnet *); 151 static void vr_ifmedia_sts (struct ifnet *, struct ifmediareq *); 152 153 #ifdef VR_USESWSHIFT 154 static void vr_mii_sync (struct vr_softc *); 155 static void vr_mii_send (struct vr_softc *, u_int32_t, int); 156 #endif 157 static int vr_mii_readreg (struct vr_softc *, struct vr_mii_frame *); 158 static int vr_mii_writereg (struct vr_softc *, struct vr_mii_frame *); 159 static int vr_miibus_readreg (device_t, int, int); 160 static int vr_miibus_writereg (device_t, int, int, int); 161 static void vr_miibus_statchg (device_t); 162 163 static void vr_setcfg (struct vr_softc *, int); 164 static u_int8_t vr_calchash (u_int8_t *); 165 static void vr_setmulti (struct vr_softc *); 166 static void vr_reset (struct vr_softc *); 167 static int vr_list_rx_init (struct vr_softc *); 168 static int vr_list_tx_init (struct vr_softc *); 169 170 #ifdef VR_USEIOSPACE 171 #define VR_RES SYS_RES_IOPORT 172 #define VR_RID VR_PCI_LOIO 173 #else 174 #define VR_RES SYS_RES_MEMORY 175 #define VR_RID VR_PCI_LOMEM 176 #endif 177 178 static device_method_t vr_methods[] = { 179 /* Device interface */ 180 DEVMETHOD(device_probe, vr_probe), 181 DEVMETHOD(device_attach, vr_attach), 182 DEVMETHOD(device_detach, vr_detach), 183 DEVMETHOD(device_shutdown, vr_shutdown), 184 185 /* bus interface */ 186 DEVMETHOD(bus_print_child, bus_generic_print_child), 187 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 188 189 /* MII interface */ 190 DEVMETHOD(miibus_readreg, vr_miibus_readreg), 191 DEVMETHOD(miibus_writereg, vr_miibus_writereg), 192 DEVMETHOD(miibus_statchg, vr_miibus_statchg), 193 194 { 0, 0 } 195 }; 196 197 static driver_t vr_driver = { 198 "vr", 199 vr_methods, 200 sizeof(struct vr_softc) 201 }; 202 203 static devclass_t vr_devclass; 204 205 DECLARE_DUMMY_MODULE(if_vr); 206 DRIVER_MODULE(if_vr, pci, vr_driver, vr_devclass, 0, 0); 207 DRIVER_MODULE(miibus, vr, miibus_driver, miibus_devclass, 0, 0); 208 209 #define VR_SETBIT(sc, reg, x) \ 210 CSR_WRITE_1(sc, reg, \ 211 CSR_READ_1(sc, reg) | x) 212 213 #define VR_CLRBIT(sc, reg, x) \ 214 CSR_WRITE_1(sc, reg, \ 215 CSR_READ_1(sc, reg) & ~x) 216 217 #define VR_SETBIT16(sc, reg, x) \ 218 CSR_WRITE_2(sc, reg, \ 219 CSR_READ_2(sc, reg) | x) 220 221 #define VR_CLRBIT16(sc, reg, x) \ 222 CSR_WRITE_2(sc, reg, \ 223 CSR_READ_2(sc, reg) & ~x) 224 225 #define VR_SETBIT32(sc, reg, x) \ 226 CSR_WRITE_4(sc, reg, \ 227 CSR_READ_4(sc, reg) | x) 228 229 #define VR_CLRBIT32(sc, reg, x) \ 230 CSR_WRITE_4(sc, reg, \ 231 CSR_READ_4(sc, reg) & ~x) 232 233 #define SIO_SET(x) \ 234 CSR_WRITE_1(sc, VR_MIICMD, \ 235 CSR_READ_1(sc, VR_MIICMD) | x) 236 237 #define SIO_CLR(x) \ 238 CSR_WRITE_1(sc, VR_MIICMD, \ 239 CSR_READ_1(sc, VR_MIICMD) & ~x) 240 241 #ifdef VR_USESWSHIFT 242 /* 243 * Sync the PHYs by setting data bit and strobing the clock 32 times. 244 */ 245 static void vr_mii_sync(sc) 246 struct vr_softc *sc; 247 { 248 int i; 249 250 SIO_SET(VR_MIICMD_DIR|VR_MIICMD_DATAIN); 251 252 for (i = 0; i < 32; i++) { 253 SIO_SET(VR_MIICMD_CLK); 254 DELAY(1); 255 SIO_CLR(VR_MIICMD_CLK); 256 DELAY(1); 257 } 258 259 return; 260 } 261 262 /* 263 * Clock a series of bits through the MII. 264 */ 265 static void vr_mii_send(sc, bits, cnt) 266 struct vr_softc *sc; 267 u_int32_t bits; 268 int cnt; 269 { 270 int i; 271 272 SIO_CLR(VR_MIICMD_CLK); 273 274 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 275 if (bits & i) { 276 SIO_SET(VR_MIICMD_DATAIN); 277 } else { 278 SIO_CLR(VR_MIICMD_DATAIN); 279 } 280 DELAY(1); 281 SIO_CLR(VR_MIICMD_CLK); 282 DELAY(1); 283 SIO_SET(VR_MIICMD_CLK); 284 } 285 } 286 #endif 287 288 /* 289 * Read an PHY register through the MII. 290 */ 291 static int vr_mii_readreg(sc, frame) 292 struct vr_softc *sc; 293 struct vr_mii_frame *frame; 294 295 #ifdef VR_USESWSHIFT 296 { 297 int i, ack, s; 298 299 s = splimp(); 300 301 /* 302 * Set up frame for RX. 303 */ 304 frame->mii_stdelim = VR_MII_STARTDELIM; 305 frame->mii_opcode = VR_MII_READOP; 306 frame->mii_turnaround = 0; 307 frame->mii_data = 0; 308 309 CSR_WRITE_1(sc, VR_MIICMD, 0); 310 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_DIRECTPGM); 311 312 /* 313 * Turn on data xmit. 314 */ 315 SIO_SET(VR_MIICMD_DIR); 316 317 vr_mii_sync(sc); 318 319 /* 320 * Send command/address info. 321 */ 322 vr_mii_send(sc, frame->mii_stdelim, 2); 323 vr_mii_send(sc, frame->mii_opcode, 2); 324 vr_mii_send(sc, frame->mii_phyaddr, 5); 325 vr_mii_send(sc, frame->mii_regaddr, 5); 326 327 /* Idle bit */ 328 SIO_CLR((VR_MIICMD_CLK|VR_MIICMD_DATAIN)); 329 DELAY(1); 330 SIO_SET(VR_MIICMD_CLK); 331 DELAY(1); 332 333 /* Turn off xmit. */ 334 SIO_CLR(VR_MIICMD_DIR); 335 336 /* Check for ack */ 337 SIO_CLR(VR_MIICMD_CLK); 338 DELAY(1); 339 ack = CSR_READ_4(sc, VR_MIICMD) & VR_MIICMD_DATAOUT; 340 SIO_SET(VR_MIICMD_CLK); 341 DELAY(1); 342 343 /* 344 * Now try reading data bits. If the ack failed, we still 345 * need to clock through 16 cycles to keep the PHY(s) in sync. 346 */ 347 if (ack) { 348 for(i = 0; i < 16; i++) { 349 SIO_CLR(VR_MIICMD_CLK); 350 DELAY(1); 351 SIO_SET(VR_MIICMD_CLK); 352 DELAY(1); 353 } 354 goto fail; 355 } 356 357 for (i = 0x8000; i; i >>= 1) { 358 SIO_CLR(VR_MIICMD_CLK); 359 DELAY(1); 360 if (!ack) { 361 if (CSR_READ_4(sc, VR_MIICMD) & VR_MIICMD_DATAOUT) 362 frame->mii_data |= i; 363 DELAY(1); 364 } 365 SIO_SET(VR_MIICMD_CLK); 366 DELAY(1); 367 } 368 369 fail: 370 371 SIO_CLR(VR_MIICMD_CLK); 372 DELAY(1); 373 SIO_SET(VR_MIICMD_CLK); 374 DELAY(1); 375 376 splx(s); 377 378 if (ack) 379 return(1); 380 return(0); 381 } 382 #else 383 { 384 int s, i; 385 386 s = splimp(); 387 388 /* Set the PHY-adress */ 389 CSR_WRITE_1(sc, VR_PHYADDR, (CSR_READ_1(sc, VR_PHYADDR)& 0xe0)| 390 frame->mii_phyaddr); 391 392 /* Set the register-adress */ 393 CSR_WRITE_1(sc, VR_MIIADDR, frame->mii_regaddr); 394 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_READ_ENB); 395 396 for (i = 0; i < 10000; i++) { 397 if ((CSR_READ_1(sc, VR_MIICMD) & VR_MIICMD_READ_ENB) == 0) 398 break; 399 DELAY(1); 400 } 401 402 frame->mii_data = CSR_READ_2(sc, VR_MIIDATA); 403 404 (void)splx(s); 405 406 return(0); 407 } 408 #endif 409 410 411 /* 412 * Write to a PHY register through the MII. 413 */ 414 static int vr_mii_writereg(sc, frame) 415 struct vr_softc *sc; 416 struct vr_mii_frame *frame; 417 418 #ifdef VR_USESWSHIFT 419 { 420 int s; 421 422 s = splimp(); 423 424 CSR_WRITE_1(sc, VR_MIICMD, 0); 425 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_DIRECTPGM); 426 427 /* 428 * Set up frame for TX. 429 */ 430 431 frame->mii_stdelim = VR_MII_STARTDELIM; 432 frame->mii_opcode = VR_MII_WRITEOP; 433 frame->mii_turnaround = VR_MII_TURNAROUND; 434 435 /* 436 * Turn on data output. 437 */ 438 SIO_SET(VR_MIICMD_DIR); 439 440 vr_mii_sync(sc); 441 442 vr_mii_send(sc, frame->mii_stdelim, 2); 443 vr_mii_send(sc, frame->mii_opcode, 2); 444 vr_mii_send(sc, frame->mii_phyaddr, 5); 445 vr_mii_send(sc, frame->mii_regaddr, 5); 446 vr_mii_send(sc, frame->mii_turnaround, 2); 447 vr_mii_send(sc, frame->mii_data, 16); 448 449 /* Idle bit. */ 450 SIO_SET(VR_MIICMD_CLK); 451 DELAY(1); 452 SIO_CLR(VR_MIICMD_CLK); 453 DELAY(1); 454 455 /* 456 * Turn off xmit. 457 */ 458 SIO_CLR(VR_MIICMD_DIR); 459 460 splx(s); 461 462 return(0); 463 } 464 #else 465 { 466 int s, i; 467 468 s = splimp(); 469 470 /* Set the PHY-adress */ 471 CSR_WRITE_1(sc, VR_PHYADDR, (CSR_READ_1(sc, VR_PHYADDR)& 0xe0)| 472 frame->mii_phyaddr); 473 474 /* Set the register-adress and data to write */ 475 CSR_WRITE_1(sc, VR_MIIADDR, frame->mii_regaddr); 476 CSR_WRITE_2(sc, VR_MIIDATA, frame->mii_data); 477 478 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_WRITE_ENB); 479 480 for (i = 0; i < 10000; i++) { 481 if ((CSR_READ_1(sc, VR_MIICMD) & VR_MIICMD_WRITE_ENB) == 0) 482 break; 483 DELAY(1); 484 } 485 486 (void)splx(s); 487 488 return(0); 489 } 490 #endif 491 492 static int vr_miibus_readreg(dev, phy, reg) 493 device_t dev; 494 int phy, reg; 495 { 496 struct vr_softc *sc; 497 struct vr_mii_frame frame; 498 499 sc = device_get_softc(dev); 500 501 switch (sc->vr_revid) { 502 case REV_ID_VT6102_APOLLO: 503 if (phy != 1) 504 return 0; 505 default: 506 break; 507 } 508 509 bzero((char *)&frame, sizeof(frame)); 510 511 frame.mii_phyaddr = phy; 512 frame.mii_regaddr = reg; 513 vr_mii_readreg(sc, &frame); 514 515 return(frame.mii_data); 516 } 517 518 static int vr_miibus_writereg(dev, phy, reg, data) 519 device_t dev; 520 u_int16_t phy, reg, data; 521 { 522 struct vr_softc *sc; 523 struct vr_mii_frame frame; 524 525 sc = device_get_softc(dev); 526 527 switch (sc->vr_revid) { 528 case REV_ID_VT6102_APOLLO: 529 if (phy != 1) 530 return 0; 531 default: 532 break; 533 } 534 535 bzero((char *)&frame, sizeof(frame)); 536 537 frame.mii_phyaddr = phy; 538 frame.mii_regaddr = reg; 539 frame.mii_data = data; 540 541 vr_mii_writereg(sc, &frame); 542 543 return(0); 544 } 545 546 static void vr_miibus_statchg(dev) 547 device_t dev; 548 { 549 struct vr_softc *sc; 550 struct mii_data *mii; 551 552 sc = device_get_softc(dev); 553 mii = device_get_softc(sc->vr_miibus); 554 vr_setcfg(sc, mii->mii_media_active); 555 556 return; 557 } 558 559 /* 560 * Calculate CRC of a multicast group address, return the lower 6 bits. 561 */ 562 static u_int8_t vr_calchash(addr) 563 u_int8_t *addr; 564 { 565 u_int32_t crc, carry; 566 int i, j; 567 u_int8_t c; 568 569 /* Compute CRC for the address value. */ 570 crc = 0xFFFFFFFF; /* initial value */ 571 572 for (i = 0; i < 6; i++) { 573 c = *(addr + i); 574 for (j = 0; j < 8; j++) { 575 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 576 crc <<= 1; 577 c >>= 1; 578 if (carry) 579 crc = (crc ^ 0x04c11db6) | carry; 580 } 581 } 582 583 /* return the filter bit position */ 584 return((crc >> 26) & 0x0000003F); 585 } 586 587 /* 588 * Program the 64-bit multicast hash filter. 589 */ 590 static void vr_setmulti(sc) 591 struct vr_softc *sc; 592 { 593 struct ifnet *ifp; 594 int h = 0; 595 u_int32_t hashes[2] = { 0, 0 }; 596 struct ifmultiaddr *ifma; 597 u_int8_t rxfilt; 598 int mcnt = 0; 599 600 ifp = &sc->arpcom.ac_if; 601 602 rxfilt = CSR_READ_1(sc, VR_RXCFG); 603 604 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 605 rxfilt |= VR_RXCFG_RX_MULTI; 606 CSR_WRITE_1(sc, VR_RXCFG, rxfilt); 607 CSR_WRITE_4(sc, VR_MAR0, 0xFFFFFFFF); 608 CSR_WRITE_4(sc, VR_MAR1, 0xFFFFFFFF); 609 return; 610 } 611 612 /* first, zot all the existing hash bits */ 613 CSR_WRITE_4(sc, VR_MAR0, 0); 614 CSR_WRITE_4(sc, VR_MAR1, 0); 615 616 /* now program new ones */ 617 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 618 ifma = ifma->ifma_link.le_next) { 619 if (ifma->ifma_addr->sa_family != AF_LINK) 620 continue; 621 h = vr_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 622 if (h < 32) 623 hashes[0] |= (1 << h); 624 else 625 hashes[1] |= (1 << (h - 32)); 626 mcnt++; 627 } 628 629 if (mcnt) 630 rxfilt |= VR_RXCFG_RX_MULTI; 631 else 632 rxfilt &= ~VR_RXCFG_RX_MULTI; 633 634 CSR_WRITE_4(sc, VR_MAR0, hashes[0]); 635 CSR_WRITE_4(sc, VR_MAR1, hashes[1]); 636 CSR_WRITE_1(sc, VR_RXCFG, rxfilt); 637 638 return; 639 } 640 641 /* 642 * In order to fiddle with the 643 * 'full-duplex' and '100Mbps' bits in the netconfig register, we 644 * first have to put the transmit and/or receive logic in the idle state. 645 */ 646 static void vr_setcfg(sc, media) 647 struct vr_softc *sc; 648 int media; 649 { 650 int restart = 0; 651 652 if (CSR_READ_2(sc, VR_COMMAND) & (VR_CMD_TX_ON|VR_CMD_RX_ON)) { 653 restart = 1; 654 VR_CLRBIT16(sc, VR_COMMAND, (VR_CMD_TX_ON|VR_CMD_RX_ON)); 655 } 656 657 if ((media & IFM_GMASK) == IFM_FDX) 658 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_FULLDUPLEX); 659 else 660 VR_CLRBIT16(sc, VR_COMMAND, VR_CMD_FULLDUPLEX); 661 662 if (restart) 663 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_ON|VR_CMD_RX_ON); 664 665 return; 666 } 667 668 static void vr_reset(sc) 669 struct vr_softc *sc; 670 { 671 int i; 672 673 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RESET); 674 675 for (i = 0; i < VR_TIMEOUT; i++) { 676 DELAY(10); 677 if (!(CSR_READ_2(sc, VR_COMMAND) & VR_CMD_RESET)) 678 break; 679 } 680 if (i == VR_TIMEOUT) { 681 if (sc->vr_revid < REV_ID_VT3065_A) 682 printf("vr%d: reset never completed!\n", sc->vr_unit); 683 else { 684 /* Use newer force reset command */ 685 printf("vr%d: Using force reset command.\n", sc->vr_unit); 686 VR_SETBIT(sc, VR_MISC_CR1, VR_MISCCR1_FORSRST); 687 } 688 } 689 690 /* Wait a little while for the chip to get its brains in order. */ 691 DELAY(1000); 692 693 return; 694 } 695 696 /* 697 * Probe for a VIA Rhine chip. Check the PCI vendor and device 698 * IDs against our list and return a device name if we find a match. 699 */ 700 static int vr_probe(dev) 701 device_t dev; 702 { 703 struct vr_type *t; 704 705 t = vr_devs; 706 707 while(t->vr_name != NULL) { 708 if ((pci_get_vendor(dev) == t->vr_vid) && 709 (pci_get_device(dev) == t->vr_did)) { 710 device_set_desc(dev, t->vr_name); 711 return(0); 712 } 713 t++; 714 } 715 716 return(ENXIO); 717 } 718 719 /* 720 * Attach the interface. Allocate softc structures, do ifmedia 721 * setup and ethernet/BPF attach. 722 */ 723 static int vr_attach(dev) 724 device_t dev; 725 { 726 int i, s; 727 u_char eaddr[ETHER_ADDR_LEN]; 728 u_int32_t command; 729 struct vr_softc *sc; 730 struct ifnet *ifp; 731 int unit, error = 0, rid; 732 733 s = splimp(); 734 735 sc = device_get_softc(dev); 736 unit = device_get_unit(dev); 737 bzero(sc, sizeof(struct vr_softc *)); 738 739 /* 740 * Handle power management nonsense. 741 */ 742 743 command = pci_read_config(dev, VR_PCI_CAPID, 4) & 0x000000FF; 744 if (command == 0x01) { 745 746 command = pci_read_config(dev, VR_PCI_PWRMGMTCTRL, 4); 747 if (command & VR_PSTATE_MASK) { 748 u_int32_t iobase, membase, irq; 749 750 /* Save important PCI config data. */ 751 iobase = pci_read_config(dev, VR_PCI_LOIO, 4); 752 membase = pci_read_config(dev, VR_PCI_LOMEM, 4); 753 irq = pci_read_config(dev, VR_PCI_INTLINE, 4); 754 755 /* Reset the power state. */ 756 printf("vr%d: chip is in D%d power mode " 757 "-- setting to D0\n", unit, command & VR_PSTATE_MASK); 758 command &= 0xFFFFFFFC; 759 pci_write_config(dev, VR_PCI_PWRMGMTCTRL, command, 4); 760 761 /* Restore PCI config data. */ 762 pci_write_config(dev, VR_PCI_LOIO, iobase, 4); 763 pci_write_config(dev, VR_PCI_LOMEM, membase, 4); 764 pci_write_config(dev, VR_PCI_INTLINE, irq, 4); 765 } 766 } 767 768 /* 769 * Map control/status registers. 770 */ 771 command = pci_read_config(dev, PCIR_COMMAND, 4); 772 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 773 pci_write_config(dev, PCIR_COMMAND, command, 4); 774 command = pci_read_config(dev, PCIR_COMMAND, 4); 775 sc->vr_revid = pci_read_config(dev, VR_PCI_REVID, 4) & 0x000000FF; 776 777 #ifdef VR_USEIOSPACE 778 if (!(command & PCIM_CMD_PORTEN)) { 779 printf("vr%d: failed to enable I/O ports!\n", unit); 780 free(sc, M_DEVBUF); 781 goto fail; 782 } 783 #else 784 if (!(command & PCIM_CMD_MEMEN)) { 785 printf("vr%d: failed to enable memory mapping!\n", unit); 786 goto fail; 787 } 788 #endif 789 790 rid = VR_RID; 791 sc->vr_res = bus_alloc_resource(dev, VR_RES, &rid, 792 0, ~0, 1, RF_ACTIVE); 793 794 if (sc->vr_res == NULL) { 795 printf("vr%d: couldn't map ports/memory\n", unit); 796 error = ENXIO; 797 goto fail; 798 } 799 800 sc->vr_btag = rman_get_bustag(sc->vr_res); 801 sc->vr_bhandle = rman_get_bushandle(sc->vr_res); 802 803 /* Allocate interrupt */ 804 rid = 0; 805 sc->vr_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 806 RF_SHAREABLE | RF_ACTIVE); 807 808 if (sc->vr_irq == NULL) { 809 printf("vr%d: couldn't map interrupt\n", unit); 810 bus_release_resource(dev, VR_RES, VR_RID, sc->vr_res); 811 error = ENXIO; 812 goto fail; 813 } 814 815 error = bus_setup_intr(dev, sc->vr_irq, INTR_TYPE_NET, 816 vr_intr, sc, &sc->vr_intrhand); 817 818 if (error) { 819 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->vr_irq); 820 bus_release_resource(dev, VR_RES, VR_RID, sc->vr_res); 821 printf("vr%d: couldn't set up irq\n", unit); 822 goto fail; 823 } 824 825 /* 826 * Windows may put the chip in suspend mode when it 827 * shuts down. Be sure to kick it in the head to wake it 828 * up again. 829 */ 830 VR_CLRBIT(sc, VR_STICKHW, (VR_STICKHW_DS0|VR_STICKHW_DS1)); 831 832 /* Reset the adapter. */ 833 vr_reset(sc); 834 835 /* 836 * Turn on bit2 (MIION) in PCI configuration register 0x53 during 837 * initialization and disable AUTOPOLL. 838 */ 839 pci_write_config(dev, VR_PCI_MODE, 840 pci_read_config(dev, VR_PCI_MODE, 4) | (VR_MODE3_MIION << 24), 4); 841 VR_CLRBIT(sc, VR_MIICMD, VR_MIICMD_AUTOPOLL); 842 843 /* 844 * Get station address. The way the Rhine chips work, 845 * you're not allowed to directly access the EEPROM once 846 * they've been programmed a special way. Consequently, 847 * we need to read the node address from the PAR0 and PAR1 848 * registers. 849 */ 850 VR_SETBIT(sc, VR_EECSR, VR_EECSR_LOAD); 851 DELAY(200); 852 for (i = 0; i < ETHER_ADDR_LEN; i++) 853 eaddr[i] = CSR_READ_1(sc, VR_PAR0 + i); 854 855 sc->vr_unit = unit; 856 857 sc->vr_ldata = contigmalloc(sizeof(struct vr_list_data), M_DEVBUF, 858 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 859 860 if (sc->vr_ldata == NULL) { 861 printf("vr%d: no memory for list buffers!\n", unit); 862 bus_teardown_intr(dev, sc->vr_irq, sc->vr_intrhand); 863 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->vr_irq); 864 bus_release_resource(dev, VR_RES, VR_RID, sc->vr_res); 865 error = ENXIO; 866 goto fail; 867 } 868 869 bzero(sc->vr_ldata, sizeof(struct vr_list_data)); 870 871 ifp = &sc->arpcom.ac_if; 872 ifp->if_softc = sc; 873 if_initname(ifp, "vr", unit); 874 ifp->if_mtu = ETHERMTU; 875 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 876 ifp->if_ioctl = vr_ioctl; 877 ifp->if_start = vr_start; 878 ifp->if_watchdog = vr_watchdog; 879 ifp->if_init = vr_init; 880 ifp->if_baudrate = 10000000; 881 ifp->if_snd.ifq_maxlen = VR_TX_LIST_CNT - 1; 882 883 /* 884 * Do MII setup. 885 */ 886 if (mii_phy_probe(dev, &sc->vr_miibus, 887 vr_ifmedia_upd, vr_ifmedia_sts)) { 888 printf("vr%d: MII without any phy!\n", sc->vr_unit); 889 bus_teardown_intr(dev, sc->vr_irq, sc->vr_intrhand); 890 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->vr_irq); 891 bus_release_resource(dev, VR_RES, VR_RID, sc->vr_res); 892 contigfree(sc->vr_ldata, 893 sizeof(struct vr_list_data), M_DEVBUF); 894 error = ENXIO; 895 goto fail; 896 } 897 898 callout_handle_init(&sc->vr_stat_ch); 899 900 /* 901 * Call MI attach routine. 902 */ 903 ether_ifattach(ifp, eaddr); 904 905 fail: 906 splx(s); 907 return(error); 908 } 909 910 static int vr_detach(dev) 911 device_t dev; 912 { 913 struct vr_softc *sc; 914 struct ifnet *ifp; 915 int s; 916 917 s = splimp(); 918 919 sc = device_get_softc(dev); 920 ifp = &sc->arpcom.ac_if; 921 922 vr_stop(sc); 923 ether_ifdetach(ifp); 924 925 bus_generic_detach(dev); 926 device_delete_child(dev, sc->vr_miibus); 927 928 bus_teardown_intr(dev, sc->vr_irq, sc->vr_intrhand); 929 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->vr_irq); 930 bus_release_resource(dev, VR_RES, VR_RID, sc->vr_res); 931 932 contigfree(sc->vr_ldata, sizeof(struct vr_list_data), M_DEVBUF); 933 934 splx(s); 935 936 return(0); 937 } 938 939 /* 940 * Initialize the transmit descriptors. 941 */ 942 static int vr_list_tx_init(sc) 943 struct vr_softc *sc; 944 { 945 struct vr_chain_data *cd; 946 struct vr_list_data *ld; 947 int i; 948 949 cd = &sc->vr_cdata; 950 ld = sc->vr_ldata; 951 for (i = 0; i < VR_TX_LIST_CNT; i++) { 952 cd->vr_tx_chain[i].vr_ptr = &ld->vr_tx_list[i]; 953 if (i == (VR_TX_LIST_CNT - 1)) 954 cd->vr_tx_chain[i].vr_nextdesc = 955 &cd->vr_tx_chain[0]; 956 else 957 cd->vr_tx_chain[i].vr_nextdesc = 958 &cd->vr_tx_chain[i + 1]; 959 } 960 961 cd->vr_tx_free = &cd->vr_tx_chain[0]; 962 cd->vr_tx_tail = cd->vr_tx_head = NULL; 963 964 return(0); 965 } 966 967 968 /* 969 * Initialize the RX descriptors and allocate mbufs for them. Note that 970 * we arrange the descriptors in a closed ring, so that the last descriptor 971 * points back to the first. 972 */ 973 static int vr_list_rx_init(sc) 974 struct vr_softc *sc; 975 { 976 struct vr_chain_data *cd; 977 struct vr_list_data *ld; 978 int i; 979 980 cd = &sc->vr_cdata; 981 ld = sc->vr_ldata; 982 983 for (i = 0; i < VR_RX_LIST_CNT; i++) { 984 cd->vr_rx_chain[i].vr_ptr = 985 (struct vr_desc *)&ld->vr_rx_list[i]; 986 if (vr_newbuf(sc, &cd->vr_rx_chain[i], NULL) == ENOBUFS) 987 return(ENOBUFS); 988 if (i == (VR_RX_LIST_CNT - 1)) { 989 cd->vr_rx_chain[i].vr_nextdesc = 990 &cd->vr_rx_chain[0]; 991 ld->vr_rx_list[i].vr_next = 992 vtophys(&ld->vr_rx_list[0]); 993 } else { 994 cd->vr_rx_chain[i].vr_nextdesc = 995 &cd->vr_rx_chain[i + 1]; 996 ld->vr_rx_list[i].vr_next = 997 vtophys(&ld->vr_rx_list[i + 1]); 998 } 999 } 1000 1001 cd->vr_rx_head = &cd->vr_rx_chain[0]; 1002 1003 return(0); 1004 } 1005 1006 /* 1007 * Initialize an RX descriptor and attach an MBUF cluster. 1008 * Note: the length fields are only 11 bits wide, which means the 1009 * largest size we can specify is 2047. This is important because 1010 * MCLBYTES is 2048, so we have to subtract one otherwise we'll 1011 * overflow the field and make a mess. 1012 */ 1013 static int vr_newbuf(sc, c, m) 1014 struct vr_softc *sc; 1015 struct vr_chain_onefrag *c; 1016 struct mbuf *m; 1017 { 1018 struct mbuf *m_new = NULL; 1019 1020 if (m == NULL) { 1021 MGETHDR(m_new, MB_DONTWAIT, MT_DATA); 1022 if (m_new == NULL) 1023 return(ENOBUFS); 1024 1025 MCLGET(m_new, MB_DONTWAIT); 1026 if (!(m_new->m_flags & M_EXT)) { 1027 m_freem(m_new); 1028 return(ENOBUFS); 1029 } 1030 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1031 } else { 1032 m_new = m; 1033 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1034 m_new->m_data = m_new->m_ext.ext_buf; 1035 } 1036 1037 m_adj(m_new, sizeof(u_int64_t)); 1038 1039 c->vr_mbuf = m_new; 1040 c->vr_ptr->vr_status = VR_RXSTAT; 1041 c->vr_ptr->vr_data = vtophys(mtod(m_new, caddr_t)); 1042 c->vr_ptr->vr_ctl = VR_RXCTL | VR_RXLEN; 1043 1044 return(0); 1045 } 1046 1047 /* 1048 * A frame has been uploaded: pass the resulting mbuf chain up to 1049 * the higher level protocols. 1050 */ 1051 static void vr_rxeof(sc) 1052 struct vr_softc *sc; 1053 { 1054 struct mbuf *m; 1055 struct ifnet *ifp; 1056 struct vr_chain_onefrag *cur_rx; 1057 int total_len = 0; 1058 u_int32_t rxstat; 1059 1060 ifp = &sc->arpcom.ac_if; 1061 1062 while(!((rxstat = sc->vr_cdata.vr_rx_head->vr_ptr->vr_status) & 1063 VR_RXSTAT_OWN)) { 1064 struct mbuf *m0 = NULL; 1065 1066 cur_rx = sc->vr_cdata.vr_rx_head; 1067 sc->vr_cdata.vr_rx_head = cur_rx->vr_nextdesc; 1068 m = cur_rx->vr_mbuf; 1069 1070 /* 1071 * If an error occurs, update stats, clear the 1072 * status word and leave the mbuf cluster in place: 1073 * it should simply get re-used next time this descriptor 1074 * comes up in the ring. 1075 */ 1076 if (rxstat & VR_RXSTAT_RXERR) { 1077 ifp->if_ierrors++; 1078 printf("vr%d: rx error (%02x):", 1079 sc->vr_unit, rxstat & 0x000000ff); 1080 if (rxstat & VR_RXSTAT_CRCERR) 1081 printf(" crc error"); 1082 if (rxstat & VR_RXSTAT_FRAMEALIGNERR) 1083 printf(" frame alignment error\n"); 1084 if (rxstat & VR_RXSTAT_FIFOOFLOW) 1085 printf(" FIFO overflow"); 1086 if (rxstat & VR_RXSTAT_GIANT) 1087 printf(" received giant packet"); 1088 if (rxstat & VR_RXSTAT_RUNT) 1089 printf(" received runt packet"); 1090 if (rxstat & VR_RXSTAT_BUSERR) 1091 printf(" system bus error"); 1092 if (rxstat & VR_RXSTAT_BUFFERR) 1093 printf("rx buffer error"); 1094 printf("\n"); 1095 vr_newbuf(sc, cur_rx, m); 1096 continue; 1097 } 1098 1099 /* No errors; receive the packet. */ 1100 total_len = VR_RXBYTES(cur_rx->vr_ptr->vr_status); 1101 1102 /* 1103 * XXX The VIA Rhine chip includes the CRC with every 1104 * received frame, and there's no way to turn this 1105 * behavior off (at least, I can't find anything in 1106 * the manual that explains how to do it) so we have 1107 * to trim off the CRC manually. 1108 */ 1109 total_len -= ETHER_CRC_LEN; 1110 1111 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 1112 total_len + ETHER_ALIGN, 0, ifp, NULL); 1113 vr_newbuf(sc, cur_rx, m); 1114 if (m0 == NULL) { 1115 ifp->if_ierrors++; 1116 continue; 1117 } 1118 m_adj(m0, ETHER_ALIGN); 1119 m = m0; 1120 1121 ifp->if_ipackets++; 1122 (*ifp->if_input)(ifp, m); 1123 } 1124 1125 return; 1126 } 1127 1128 void vr_rxeoc(sc) 1129 struct vr_softc *sc; 1130 { 1131 struct ifnet *ifp; 1132 int i; 1133 1134 ifp = &sc->arpcom.ac_if; 1135 1136 ifp->if_ierrors++; 1137 1138 VR_CLRBIT16(sc, VR_COMMAND, VR_CMD_RX_ON); 1139 DELAY(10000); 1140 1141 for (i = 0x400; 1142 i && (CSR_READ_2(sc, VR_COMMAND) & VR_CMD_RX_ON); 1143 i--) 1144 ; /* Wait for receiver to stop */ 1145 1146 if (!i) { 1147 printf("vr%d: rx shutdown error!\n", sc->vr_unit); 1148 sc->vr_flags |= VR_F_RESTART; 1149 return; 1150 } 1151 1152 vr_rxeof(sc); 1153 1154 CSR_WRITE_4(sc, VR_RXADDR, vtophys(sc->vr_cdata.vr_rx_head->vr_ptr)); 1155 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RX_ON); 1156 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RX_GO); 1157 1158 return; 1159 } 1160 1161 /* 1162 * A frame was downloaded to the chip. It's safe for us to clean up 1163 * the list buffers. 1164 */ 1165 1166 static void vr_txeof(sc) 1167 struct vr_softc *sc; 1168 { 1169 struct vr_chain *cur_tx; 1170 struct ifnet *ifp; 1171 1172 ifp = &sc->arpcom.ac_if; 1173 1174 /* Reset the timeout timer; if_txeoc will clear it. */ 1175 ifp->if_timer = 5; 1176 1177 /* Sanity check. */ 1178 if (sc->vr_cdata.vr_tx_head == NULL) 1179 return; 1180 1181 /* 1182 * Go through our tx list and free mbufs for those 1183 * frames that have been transmitted. 1184 */ 1185 while(sc->vr_cdata.vr_tx_head->vr_mbuf != NULL) { 1186 u_int32_t txstat; 1187 int i; 1188 1189 cur_tx = sc->vr_cdata.vr_tx_head; 1190 txstat = cur_tx->vr_ptr->vr_status; 1191 1192 if ((txstat & VR_TXSTAT_ABRT) || 1193 (txstat & VR_TXSTAT_UDF)) { 1194 for (i = 0x400; 1195 i && (CSR_READ_2(sc, VR_COMMAND) & VR_CMD_TX_ON); 1196 i--) 1197 ; /* Wait for chip to shutdown */ 1198 if (!i) { 1199 printf("vr%d: tx shutdown timeout\n", sc->vr_unit); 1200 sc->vr_flags |= VR_F_RESTART; 1201 break; 1202 } 1203 VR_TXOWN(cur_tx) = VR_TXSTAT_OWN; 1204 CSR_WRITE_4(sc, VR_TXADDR, vtophys(cur_tx->vr_ptr)); 1205 break; 1206 } 1207 1208 if (txstat & VR_TXSTAT_OWN) 1209 break; 1210 1211 if (txstat & VR_TXSTAT_ERRSUM) { 1212 ifp->if_oerrors++; 1213 if (txstat & VR_TXSTAT_DEFER) 1214 ifp->if_collisions++; 1215 if (txstat & VR_TXSTAT_LATECOLL) 1216 ifp->if_collisions++; 1217 } 1218 1219 ifp->if_collisions +=(txstat & VR_TXSTAT_COLLCNT) >> 3; 1220 1221 ifp->if_opackets++; 1222 if (cur_tx->vr_mbuf != NULL) { 1223 m_freem(cur_tx->vr_mbuf); 1224 cur_tx->vr_mbuf = NULL; 1225 } 1226 1227 if (sc->vr_cdata.vr_tx_head == sc->vr_cdata.vr_tx_tail) { 1228 sc->vr_cdata.vr_tx_head = NULL; 1229 sc->vr_cdata.vr_tx_tail = NULL; 1230 break; 1231 } 1232 1233 sc->vr_cdata.vr_tx_head = cur_tx->vr_nextdesc; 1234 } 1235 1236 return; 1237 } 1238 1239 /* 1240 * TX 'end of channel' interrupt handler. 1241 */ 1242 static void vr_txeoc(sc) 1243 struct vr_softc *sc; 1244 { 1245 struct ifnet *ifp; 1246 1247 ifp = &sc->arpcom.ac_if; 1248 1249 if (sc->vr_cdata.vr_tx_head == NULL) { 1250 ifp->if_flags &= ~IFF_OACTIVE; 1251 sc->vr_cdata.vr_tx_tail = NULL; 1252 ifp->if_timer = 0; 1253 } 1254 1255 return; 1256 } 1257 1258 static void vr_tick(xsc) 1259 void *xsc; 1260 { 1261 struct vr_softc *sc; 1262 struct mii_data *mii; 1263 int s; 1264 1265 s = splimp(); 1266 1267 sc = xsc; 1268 if (sc->vr_flags & VR_F_RESTART) { 1269 printf("vr%d: restarting\n", sc->vr_unit); 1270 vr_stop(sc); 1271 vr_reset(sc); 1272 vr_init(sc); 1273 sc->vr_flags &= ~VR_F_RESTART; 1274 } 1275 1276 mii = device_get_softc(sc->vr_miibus); 1277 mii_tick(mii); 1278 1279 sc->vr_stat_ch = timeout(vr_tick, sc, hz); 1280 1281 splx(s); 1282 1283 return; 1284 } 1285 1286 static void vr_intr(arg) 1287 void *arg; 1288 { 1289 struct vr_softc *sc; 1290 struct ifnet *ifp; 1291 u_int16_t status; 1292 1293 sc = arg; 1294 ifp = &sc->arpcom.ac_if; 1295 1296 /* Supress unwanted interrupts. */ 1297 if (!(ifp->if_flags & IFF_UP)) { 1298 vr_stop(sc); 1299 return; 1300 } 1301 1302 /* Disable interrupts. */ 1303 if ((ifp->if_flags & IFF_POLLING) == 0) 1304 CSR_WRITE_2(sc, VR_IMR, 0x0000); 1305 1306 for (;;) { 1307 1308 status = CSR_READ_2(sc, VR_ISR); 1309 if (status) 1310 CSR_WRITE_2(sc, VR_ISR, status); 1311 1312 if ((status & VR_INTRS) == 0) 1313 break; 1314 1315 if (status & VR_ISR_RX_OK) 1316 vr_rxeof(sc); 1317 1318 if (status & VR_ISR_RX_DROPPED) { 1319 printf("vr%d: rx packet lost\n", sc->vr_unit); 1320 ifp->if_ierrors++; 1321 } 1322 1323 if ((status & VR_ISR_RX_ERR) || (status & VR_ISR_RX_NOBUF) || 1324 (status & VR_ISR_RX_NOBUF) || (status & VR_ISR_RX_OFLOW)) { 1325 printf("vr%d: receive error (%04x)", 1326 sc->vr_unit, status); 1327 if (status & VR_ISR_RX_NOBUF) 1328 printf(" no buffers"); 1329 if (status & VR_ISR_RX_OFLOW) 1330 printf(" overflow"); 1331 if (status & VR_ISR_RX_DROPPED) 1332 printf(" packet lost"); 1333 printf("\n"); 1334 vr_rxeoc(sc); 1335 } 1336 1337 if ((status & VR_ISR_BUSERR) || (status & VR_ISR_TX_UNDERRUN)) { 1338 vr_reset(sc); 1339 vr_init(sc); 1340 break; 1341 } 1342 1343 if ((status & VR_ISR_TX_OK) || (status & VR_ISR_TX_ABRT) || 1344 (status & VR_ISR_TX_ABRT2) || (status & VR_ISR_UDFI)) { 1345 vr_txeof(sc); 1346 if ((status & VR_ISR_UDFI) || 1347 (status & VR_ISR_TX_ABRT2) || 1348 (status & VR_ISR_TX_ABRT)) { 1349 ifp->if_oerrors++; 1350 if (sc->vr_cdata.vr_tx_head != NULL) { 1351 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_ON); 1352 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_GO); 1353 } 1354 } else 1355 vr_txeoc(sc); 1356 } 1357 1358 } 1359 1360 /* Re-enable interrupts. */ 1361 if ((ifp->if_flags & IFF_POLLING) == 0) 1362 CSR_WRITE_2(sc, VR_IMR, VR_INTRS); 1363 1364 if (ifp->if_snd.ifq_head != NULL) { 1365 vr_start(ifp); 1366 } 1367 1368 return; 1369 } 1370 1371 /* 1372 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1373 * pointers to the fragment pointers. 1374 */ 1375 static int vr_encap(sc, c, m_head) 1376 struct vr_softc *sc; 1377 struct vr_chain *c; 1378 struct mbuf *m_head; 1379 { 1380 int frag = 0; 1381 struct vr_desc *f = NULL; 1382 int total_len; 1383 struct mbuf *m; 1384 1385 m = m_head; 1386 total_len = 0; 1387 1388 /* 1389 * The VIA Rhine wants packet buffers to be longword 1390 * aligned, but very often our mbufs aren't. Rather than 1391 * waste time trying to decide when to copy and when not 1392 * to copy, just do it all the time. 1393 */ 1394 if (m != NULL) { 1395 struct mbuf *m_new = NULL; 1396 1397 MGETHDR(m_new, MB_DONTWAIT, MT_DATA); 1398 if (m_new == NULL) { 1399 printf("vr%d: no memory for tx list\n", sc->vr_unit); 1400 return(1); 1401 } 1402 if (m_head->m_pkthdr.len > MHLEN) { 1403 MCLGET(m_new, MB_DONTWAIT); 1404 if (!(m_new->m_flags & M_EXT)) { 1405 m_freem(m_new); 1406 printf("vr%d: no memory for tx list\n", 1407 sc->vr_unit); 1408 return(1); 1409 } 1410 } 1411 m_copydata(m_head, 0, m_head->m_pkthdr.len, 1412 mtod(m_new, caddr_t)); 1413 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 1414 m_freem(m_head); 1415 m_head = m_new; 1416 /* 1417 * The Rhine chip doesn't auto-pad, so we have to make 1418 * sure to pad short frames out to the minimum frame length 1419 * ourselves. 1420 */ 1421 if (m_head->m_len < VR_MIN_FRAMELEN) { 1422 m_new->m_pkthdr.len += VR_MIN_FRAMELEN - m_new->m_len; 1423 m_new->m_len = m_new->m_pkthdr.len; 1424 } 1425 f = c->vr_ptr; 1426 f->vr_data = vtophys(mtod(m_new, caddr_t)); 1427 f->vr_ctl = total_len = m_new->m_len; 1428 f->vr_ctl |= VR_TXCTL_TLINK|VR_TXCTL_FIRSTFRAG; 1429 f->vr_status = 0; 1430 frag = 1; 1431 } 1432 1433 c->vr_mbuf = m_head; 1434 c->vr_ptr->vr_ctl |= VR_TXCTL_LASTFRAG|VR_TXCTL_FINT; 1435 c->vr_ptr->vr_next = vtophys(c->vr_nextdesc->vr_ptr); 1436 1437 return(0); 1438 } 1439 1440 /* 1441 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1442 * to the mbuf data regions directly in the transmit lists. We also save a 1443 * copy of the pointers since the transmit list fragment pointers are 1444 * physical addresses. 1445 */ 1446 1447 static void vr_start(ifp) 1448 struct ifnet *ifp; 1449 { 1450 struct vr_softc *sc; 1451 struct mbuf *m_head = NULL; 1452 struct vr_chain *cur_tx = NULL, *start_tx; 1453 1454 sc = ifp->if_softc; 1455 1456 if (ifp->if_flags & IFF_OACTIVE) 1457 return; 1458 1459 /* 1460 * Check for an available queue slot. If there are none, 1461 * punt. 1462 */ 1463 if (sc->vr_cdata.vr_tx_free->vr_mbuf != NULL) { 1464 ifp->if_flags |= IFF_OACTIVE; 1465 return; 1466 } 1467 1468 start_tx = sc->vr_cdata.vr_tx_free; 1469 1470 while(sc->vr_cdata.vr_tx_free->vr_mbuf == NULL) { 1471 IF_DEQUEUE(&ifp->if_snd, m_head); 1472 if (m_head == NULL) 1473 break; 1474 1475 /* Pick a descriptor off the free list. */ 1476 cur_tx = sc->vr_cdata.vr_tx_free; 1477 sc->vr_cdata.vr_tx_free = cur_tx->vr_nextdesc; 1478 1479 /* Pack the data into the descriptor. */ 1480 if (vr_encap(sc, cur_tx, m_head)) { 1481 IF_PREPEND(&ifp->if_snd, m_head); 1482 ifp->if_flags |= IFF_OACTIVE; 1483 cur_tx = NULL; 1484 break; 1485 } 1486 1487 if (cur_tx != start_tx) 1488 VR_TXOWN(cur_tx) = VR_TXSTAT_OWN; 1489 1490 /* 1491 * If there's a BPF listener, bounce a copy of this frame 1492 * to him. 1493 */ 1494 if (ifp->if_bpf) 1495 bpf_mtap(ifp, cur_tx->vr_mbuf); 1496 1497 VR_TXOWN(cur_tx) = VR_TXSTAT_OWN; 1498 VR_SETBIT16(sc, VR_COMMAND, /*VR_CMD_TX_ON|*/VR_CMD_TX_GO); 1499 } 1500 1501 /* 1502 * If there are no frames queued, bail. 1503 */ 1504 if (cur_tx == NULL) 1505 return; 1506 1507 sc->vr_cdata.vr_tx_tail = cur_tx; 1508 1509 if (sc->vr_cdata.vr_tx_head == NULL) 1510 sc->vr_cdata.vr_tx_head = start_tx; 1511 1512 /* 1513 * Set a timeout in case the chip goes out to lunch. 1514 */ 1515 ifp->if_timer = 5; 1516 1517 return; 1518 } 1519 1520 static void vr_init(xsc) 1521 void *xsc; 1522 { 1523 struct vr_softc *sc = xsc; 1524 struct ifnet *ifp = &sc->arpcom.ac_if; 1525 struct mii_data *mii; 1526 int s, i; 1527 1528 s = splimp(); 1529 1530 mii = device_get_softc(sc->vr_miibus); 1531 1532 /* 1533 * Cancel pending I/O and free all RX/TX buffers. 1534 */ 1535 vr_stop(sc); 1536 vr_reset(sc); 1537 1538 /* 1539 * Set our station address. 1540 */ 1541 for (i = 0; i < ETHER_ADDR_LEN; i++) 1542 CSR_WRITE_1(sc, VR_PAR0 + i, sc->arpcom.ac_enaddr[i]); 1543 1544 /* Set DMA size */ 1545 VR_CLRBIT(sc, VR_BCR0, VR_BCR0_DMA_LENGTH); 1546 VR_SETBIT(sc, VR_BCR0, VR_BCR0_DMA_STORENFWD); 1547 1548 /* 1549 * BCR0 and BCR1 can override the RXCFG and TXCFG registers, 1550 * so we must set both. 1551 */ 1552 VR_CLRBIT(sc, VR_BCR0, VR_BCR0_RX_THRESH); 1553 VR_SETBIT(sc, VR_BCR0, VR_BCR0_RXTHRESH128BYTES); 1554 1555 VR_CLRBIT(sc, VR_BCR1, VR_BCR1_TX_THRESH); 1556 VR_SETBIT(sc, VR_BCR1, VR_BCR1_TXTHRESHSTORENFWD); 1557 1558 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_THRESH); 1559 VR_SETBIT(sc, VR_RXCFG, VR_RXTHRESH_128BYTES); 1560 1561 VR_CLRBIT(sc, VR_TXCFG, VR_TXCFG_TX_THRESH); 1562 VR_SETBIT(sc, VR_TXCFG, VR_TXTHRESH_STORENFWD); 1563 1564 /* Init circular RX list. */ 1565 if (vr_list_rx_init(sc) == ENOBUFS) { 1566 printf("vr%d: initialization failed: no " 1567 "memory for rx buffers\n", sc->vr_unit); 1568 vr_stop(sc); 1569 (void)splx(s); 1570 return; 1571 } 1572 1573 /* 1574 * Init tx descriptors. 1575 */ 1576 vr_list_tx_init(sc); 1577 1578 /* If we want promiscuous mode, set the allframes bit. */ 1579 if (ifp->if_flags & IFF_PROMISC) 1580 VR_SETBIT(sc, VR_RXCFG, VR_RXCFG_RX_PROMISC); 1581 else 1582 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_PROMISC); 1583 1584 /* Set capture broadcast bit to capture broadcast frames. */ 1585 if (ifp->if_flags & IFF_BROADCAST) 1586 VR_SETBIT(sc, VR_RXCFG, VR_RXCFG_RX_BROAD); 1587 else 1588 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_BROAD); 1589 1590 /* 1591 * Program the multicast filter, if necessary. 1592 */ 1593 vr_setmulti(sc); 1594 1595 /* 1596 * Load the address of the RX list. 1597 */ 1598 CSR_WRITE_4(sc, VR_RXADDR, vtophys(sc->vr_cdata.vr_rx_head->vr_ptr)); 1599 1600 /* Enable receiver and transmitter. */ 1601 CSR_WRITE_2(sc, VR_COMMAND, VR_CMD_TX_NOPOLL|VR_CMD_START| 1602 VR_CMD_TX_ON|VR_CMD_RX_ON| 1603 VR_CMD_RX_GO); 1604 1605 CSR_WRITE_4(sc, VR_TXADDR, vtophys(&sc->vr_ldata->vr_tx_list[0])); 1606 1607 /* 1608 * Enable interrupts, unless we are polling. 1609 */ 1610 CSR_WRITE_2(sc, VR_ISR, 0xFFFF); 1611 if ((ifp->if_flags & IFF_POLLING) == 0) 1612 CSR_WRITE_2(sc, VR_IMR, VR_INTRS); 1613 1614 mii_mediachg(mii); 1615 1616 ifp->if_flags |= IFF_RUNNING; 1617 ifp->if_flags &= ~IFF_OACTIVE; 1618 1619 (void)splx(s); 1620 1621 sc->vr_stat_ch = timeout(vr_tick, sc, hz); 1622 1623 return; 1624 } 1625 1626 /* 1627 * Set media options. 1628 */ 1629 static int vr_ifmedia_upd(ifp) 1630 struct ifnet *ifp; 1631 { 1632 struct vr_softc *sc; 1633 1634 sc = ifp->if_softc; 1635 1636 if (ifp->if_flags & IFF_UP) 1637 vr_init(sc); 1638 1639 return(0); 1640 } 1641 1642 /* 1643 * Report current media status. 1644 */ 1645 static void vr_ifmedia_sts(ifp, ifmr) 1646 struct ifnet *ifp; 1647 struct ifmediareq *ifmr; 1648 { 1649 struct vr_softc *sc; 1650 struct mii_data *mii; 1651 1652 sc = ifp->if_softc; 1653 mii = device_get_softc(sc->vr_miibus); 1654 mii_pollstat(mii); 1655 ifmr->ifm_active = mii->mii_media_active; 1656 ifmr->ifm_status = mii->mii_media_status; 1657 1658 return; 1659 } 1660 1661 static int vr_ioctl(ifp, command, data, cr) 1662 struct ifnet *ifp; 1663 u_long command; 1664 caddr_t data; 1665 struct ucred *cr; 1666 { 1667 struct vr_softc *sc = ifp->if_softc; 1668 struct ifreq *ifr = (struct ifreq *) data; 1669 struct mii_data *mii; 1670 int s, error = 0; 1671 1672 s = splimp(); 1673 1674 switch(command) { 1675 case SIOCSIFADDR: 1676 case SIOCGIFADDR: 1677 case SIOCSIFMTU: 1678 error = ether_ioctl(ifp, command, data); 1679 break; 1680 case SIOCSIFFLAGS: 1681 if (ifp->if_flags & IFF_UP) { 1682 vr_init(sc); 1683 } else { 1684 if (ifp->if_flags & IFF_RUNNING) 1685 vr_stop(sc); 1686 } 1687 error = 0; 1688 break; 1689 case SIOCADDMULTI: 1690 case SIOCDELMULTI: 1691 vr_setmulti(sc); 1692 error = 0; 1693 break; 1694 case SIOCGIFMEDIA: 1695 case SIOCSIFMEDIA: 1696 mii = device_get_softc(sc->vr_miibus); 1697 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1698 break; 1699 default: 1700 error = EINVAL; 1701 break; 1702 } 1703 1704 (void)splx(s); 1705 1706 return(error); 1707 } 1708 1709 #ifdef DEVICE_POLLING 1710 1711 static 1712 void 1713 vr_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1714 { 1715 struct vr_softc *sc = ifp->if_softc; 1716 1717 if (cmd == POLL_DEREGISTER) { 1718 CSR_WRITE_2(sc, VR_IMR, VR_INTRS); 1719 } else { 1720 vr_intr(sc); 1721 } 1722 } 1723 1724 #endif 1725 1726 static void vr_watchdog(ifp) 1727 struct ifnet *ifp; 1728 { 1729 struct vr_softc *sc; 1730 1731 sc = ifp->if_softc; 1732 1733 ifp->if_oerrors++; 1734 printf("vr%d: watchdog timeout\n", sc->vr_unit); 1735 1736 #ifdef DEVICE_POLLING 1737 if (++sc->vr_wdogerrors == 1 && (ifp->if_flags & IFF_POLLING) == 0) { 1738 printf("vr%d ints don't seem to be working, " 1739 "emergency switch to polling\n", sc->vr_unit); 1740 emergency_poll_enable("if_vr"); 1741 if (ether_poll_register(vr_poll, ifp)) { 1742 CSR_WRITE_2(sc, VR_IMR, 0x0000); 1743 } 1744 } else 1745 #endif 1746 { 1747 vr_stop(sc); 1748 vr_reset(sc); 1749 vr_init(sc); 1750 } 1751 1752 if (ifp->if_snd.ifq_head != NULL) 1753 vr_start(ifp); 1754 } 1755 1756 /* 1757 * Stop the adapter and free any mbufs allocated to the 1758 * RX and TX lists. 1759 */ 1760 static void vr_stop(sc) 1761 struct vr_softc *sc; 1762 { 1763 int i; 1764 struct ifnet *ifp; 1765 1766 ifp = &sc->arpcom.ac_if; 1767 ifp->if_timer = 0; 1768 1769 untimeout(vr_tick, sc, sc->vr_stat_ch); 1770 1771 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_STOP); 1772 VR_CLRBIT16(sc, VR_COMMAND, (VR_CMD_RX_ON|VR_CMD_TX_ON)); 1773 CSR_WRITE_2(sc, VR_IMR, 0x0000); 1774 CSR_WRITE_4(sc, VR_TXADDR, 0x00000000); 1775 CSR_WRITE_4(sc, VR_RXADDR, 0x00000000); 1776 1777 /* 1778 * Free data in the RX lists. 1779 */ 1780 for (i = 0; i < VR_RX_LIST_CNT; i++) { 1781 if (sc->vr_cdata.vr_rx_chain[i].vr_mbuf != NULL) { 1782 m_freem(sc->vr_cdata.vr_rx_chain[i].vr_mbuf); 1783 sc->vr_cdata.vr_rx_chain[i].vr_mbuf = NULL; 1784 } 1785 } 1786 bzero((char *)&sc->vr_ldata->vr_rx_list, 1787 sizeof(sc->vr_ldata->vr_rx_list)); 1788 1789 /* 1790 * Free the TX list buffers. 1791 */ 1792 for (i = 0; i < VR_TX_LIST_CNT; i++) { 1793 if (sc->vr_cdata.vr_tx_chain[i].vr_mbuf != NULL) { 1794 m_freem(sc->vr_cdata.vr_tx_chain[i].vr_mbuf); 1795 sc->vr_cdata.vr_tx_chain[i].vr_mbuf = NULL; 1796 } 1797 } 1798 1799 bzero((char *)&sc->vr_ldata->vr_tx_list, 1800 sizeof(sc->vr_ldata->vr_tx_list)); 1801 1802 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1803 1804 return; 1805 } 1806 1807 /* 1808 * Stop all chip I/O so that the kernel's probe routines don't 1809 * get confused by errant DMAs when rebooting. 1810 */ 1811 static void vr_shutdown(dev) 1812 device_t dev; 1813 { 1814 struct vr_softc *sc; 1815 1816 sc = device_get_softc(dev); 1817 1818 vr_stop(sc); 1819 1820 return; 1821 } 1822