1 /* 2 * Copyright (c) 1997, 1998 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: src/sys/pci/if_vr.c,v 1.26.2.13 2003/02/06 04:46:20 silby Exp $ 33 * $DragonFly: src/sys/dev/netif/vr/if_vr.c,v 1.42 2006/08/01 18:11:20 swildner Exp $ 34 */ 35 36 /* 37 * VIA Rhine fast ethernet PCI NIC driver 38 * 39 * Supports various network adapters based on the VIA Rhine 40 * and Rhine II PCI controllers, including the D-Link DFE530TX. 41 * Datasheets are available at http://www.via.com.tw. 42 * 43 * Written by Bill Paul <wpaul@ctr.columbia.edu> 44 * Electrical Engineering Department 45 * Columbia University, New York City 46 */ 47 48 /* 49 * The VIA Rhine controllers are similar in some respects to the 50 * the DEC tulip chips, except less complicated. The controller 51 * uses an MII bus and an external physical layer interface. The 52 * receiver has a one entry perfect filter and a 64-bit hash table 53 * multicast filter. Transmit and receive descriptors are similar 54 * to the tulip. 55 * 56 * The Rhine has a serious flaw in its transmit DMA mechanism: 57 * transmit buffers must be longword aligned. Unfortunately, 58 * FreeBSD doesn't guarantee that mbufs will be filled in starting 59 * at longword boundaries, so we have to do a buffer copy before 60 * transmission. 61 */ 62 63 #include "opt_polling.h" 64 65 #include <sys/param.h> 66 #include <sys/systm.h> 67 #include <sys/sockio.h> 68 #include <sys/mbuf.h> 69 #include <sys/malloc.h> 70 #include <sys/kernel.h> 71 #include <sys/socket.h> 72 #include <sys/serialize.h> 73 #include <sys/thread2.h> 74 75 #include <net/if.h> 76 #include <net/ifq_var.h> 77 #include <net/if_arp.h> 78 #include <net/ethernet.h> 79 #include <net/if_dl.h> 80 #include <net/if_media.h> 81 82 #include <net/bpf.h> 83 84 #include <vm/vm.h> /* for vtophys */ 85 #include <vm/pmap.h> /* for vtophys */ 86 #include <machine/bus_pio.h> 87 #include <machine/bus_memio.h> 88 #include <machine/bus.h> 89 #include <machine/resource.h> 90 #include <sys/bus.h> 91 #include <sys/rman.h> 92 93 #include <dev/netif/mii_layer/mii.h> 94 #include <dev/netif/mii_layer/miivar.h> 95 96 #include <bus/pci/pcidevs.h> 97 #include <bus/pci/pcireg.h> 98 #include <bus/pci/pcivar.h> 99 100 #define VR_USEIOSPACE 101 102 #include <dev/netif/vr/if_vrreg.h> 103 104 /* "controller miibus0" required. See GENERIC if you get errors here. */ 105 #include "miibus_if.h" 106 107 #undef VR_USESWSHIFT 108 109 /* 110 * Various supported device vendors/types and their names. 111 */ 112 static struct vr_type vr_devs[] = { 113 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT3043, 114 "VIA VT3043 Rhine I 10/100BaseTX" }, 115 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT86C100A, 116 "VIA VT86C100A Rhine II 10/100BaseTX" }, 117 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT6102, 118 "VIA VT6102 Rhine II 10/100BaseTX" }, 119 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT6105, 120 "VIA VT6105 Rhine III 10/100BaseTX" }, 121 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT6105M, 122 "VIA VT6105M Rhine III 10/100BaseTX" }, 123 { PCI_VENDOR_DELTA, PCI_PRODUCT_DELTA_RHINEII, 124 "Delta Electronics Rhine II 10/100BaseTX" }, 125 { PCI_VENDOR_ADDTRON, PCI_PRODUCT_ADDTRON_RHINEII, 126 "Addtron Technology Rhine II 10/100BaseTX" }, 127 { 0, 0, NULL } 128 }; 129 130 static int vr_probe(device_t); 131 static int vr_attach(device_t); 132 static int vr_detach(device_t); 133 134 static int vr_newbuf(struct vr_softc *, struct vr_chain_onefrag *, 135 struct mbuf *); 136 static int vr_encap(struct vr_softc *, int, struct mbuf * ); 137 138 static void vr_rxeof(struct vr_softc *); 139 static void vr_rxeoc(struct vr_softc *); 140 static void vr_txeof(struct vr_softc *); 141 static void vr_txeoc(struct vr_softc *); 142 static void vr_tick(void *); 143 static void vr_intr(void *); 144 static void vr_start(struct ifnet *); 145 static int vr_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *); 146 static void vr_init(void *); 147 static void vr_stop(struct vr_softc *); 148 static void vr_watchdog(struct ifnet *); 149 static void vr_shutdown(device_t); 150 static int vr_ifmedia_upd(struct ifnet *); 151 static void vr_ifmedia_sts(struct ifnet *, struct ifmediareq *); 152 153 #ifdef VR_USESWSHIFT 154 static void vr_mii_sync(struct vr_softc *); 155 static void vr_mii_send(struct vr_softc *, uint32_t, int); 156 #endif 157 static int vr_mii_readreg(struct vr_softc *, struct vr_mii_frame *); 158 static int vr_mii_writereg(struct vr_softc *, struct vr_mii_frame *); 159 static int vr_miibus_readreg(device_t, int, int); 160 static int vr_miibus_writereg(device_t, int, int, int); 161 static void vr_miibus_statchg(device_t); 162 163 static void vr_setcfg(struct vr_softc *, int); 164 static void vr_setmulti(struct vr_softc *); 165 static void vr_reset(struct vr_softc *); 166 static int vr_list_rx_init(struct vr_softc *); 167 static int vr_list_tx_init(struct vr_softc *); 168 #ifdef DEVICE_POLLING 169 static void vr_poll(struct ifnet *ifp, enum poll_cmd cmd, int count); 170 #endif 171 172 #ifdef VR_USEIOSPACE 173 #define VR_RES SYS_RES_IOPORT 174 #define VR_RID VR_PCI_LOIO 175 #else 176 #define VR_RES SYS_RES_MEMORY 177 #define VR_RID VR_PCI_LOMEM 178 #endif 179 180 static device_method_t vr_methods[] = { 181 /* Device interface */ 182 DEVMETHOD(device_probe, vr_probe), 183 DEVMETHOD(device_attach, vr_attach), 184 DEVMETHOD(device_detach, vr_detach), 185 DEVMETHOD(device_shutdown, vr_shutdown), 186 187 /* bus interface */ 188 DEVMETHOD(bus_print_child, bus_generic_print_child), 189 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 190 191 /* MII interface */ 192 DEVMETHOD(miibus_readreg, vr_miibus_readreg), 193 DEVMETHOD(miibus_writereg, vr_miibus_writereg), 194 DEVMETHOD(miibus_statchg, vr_miibus_statchg), 195 196 { 0, 0 } 197 }; 198 199 static driver_t vr_driver = { 200 "vr", 201 vr_methods, 202 sizeof(struct vr_softc) 203 }; 204 205 static devclass_t vr_devclass; 206 207 DECLARE_DUMMY_MODULE(if_vr); 208 DRIVER_MODULE(if_vr, pci, vr_driver, vr_devclass, 0, 0); 209 DRIVER_MODULE(miibus, vr, miibus_driver, miibus_devclass, 0, 0); 210 211 #define VR_SETBIT(sc, reg, x) \ 212 CSR_WRITE_1(sc, reg, \ 213 CSR_READ_1(sc, reg) | (x)) 214 215 #define VR_CLRBIT(sc, reg, x) \ 216 CSR_WRITE_1(sc, reg, \ 217 CSR_READ_1(sc, reg) & ~(x)) 218 219 #define VR_SETBIT16(sc, reg, x) \ 220 CSR_WRITE_2(sc, reg, \ 221 CSR_READ_2(sc, reg) | (x)) 222 223 #define VR_CLRBIT16(sc, reg, x) \ 224 CSR_WRITE_2(sc, reg, \ 225 CSR_READ_2(sc, reg) & ~(x)) 226 227 #define VR_SETBIT32(sc, reg, x) \ 228 CSR_WRITE_4(sc, reg, \ 229 CSR_READ_4(sc, reg) | (x)) 230 231 #define VR_CLRBIT32(sc, reg, x) \ 232 CSR_WRITE_4(sc, reg, \ 233 CSR_READ_4(sc, reg) & ~(x)) 234 235 #define SIO_SET(x) \ 236 CSR_WRITE_1(sc, VR_MIICMD, \ 237 CSR_READ_1(sc, VR_MIICMD) | (x)) 238 239 #define SIO_CLR(x) \ 240 CSR_WRITE_1(sc, VR_MIICMD, \ 241 CSR_READ_1(sc, VR_MIICMD) & ~(x)) 242 243 #ifdef VR_USESWSHIFT 244 /* 245 * Sync the PHYs by setting data bit and strobing the clock 32 times. 246 */ 247 static void 248 vr_mii_sync(struct vr_softc *sc) 249 { 250 int i; 251 252 SIO_SET(VR_MIICMD_DIR|VR_MIICMD_DATAIN); 253 254 for (i = 0; i < 32; i++) { 255 SIO_SET(VR_MIICMD_CLK); 256 DELAY(1); 257 SIO_CLR(VR_MIICMD_CLK); 258 DELAY(1); 259 } 260 } 261 262 /* 263 * Clock a series of bits through the MII. 264 */ 265 static void 266 vr_mii_send(struct vr_softc *sc, uint32_t bits, int cnt) 267 { 268 int i; 269 270 SIO_CLR(VR_MIICMD_CLK); 271 272 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 273 if (bits & i) 274 SIO_SET(VR_MIICMD_DATAIN); 275 else 276 SIO_CLR(VR_MIICMD_DATAIN); 277 DELAY(1); 278 SIO_CLR(VR_MIICMD_CLK); 279 DELAY(1); 280 SIO_SET(VR_MIICMD_CLK); 281 } 282 } 283 #endif 284 285 /* 286 * Read an PHY register through the MII. 287 */ 288 static int 289 vr_mii_readreg(struct vr_softc *sc, struct vr_mii_frame *frame) 290 #ifdef VR_USESWSHIFT 291 { 292 int i, ack; 293 294 /* Set up frame for RX. */ 295 frame->mii_stdelim = VR_MII_STARTDELIM; 296 frame->mii_opcode = VR_MII_READOP; 297 frame->mii_turnaround = 0; 298 frame->mii_data = 0; 299 300 CSR_WRITE_1(sc, VR_MIICMD, 0); 301 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_DIRECTPGM); 302 303 /* Turn on data xmit. */ 304 SIO_SET(VR_MIICMD_DIR); 305 306 vr_mii_sync(sc); 307 308 /* Send command/address info. */ 309 vr_mii_send(sc, frame->mii_stdelim, 2); 310 vr_mii_send(sc, frame->mii_opcode, 2); 311 vr_mii_send(sc, frame->mii_phyaddr, 5); 312 vr_mii_send(sc, frame->mii_regaddr, 5); 313 314 /* Idle bit. */ 315 SIO_CLR((VR_MIICMD_CLK|VR_MIICMD_DATAIN)); 316 DELAY(1); 317 SIO_SET(VR_MIICMD_CLK); 318 DELAY(1); 319 320 /* Turn off xmit. */ 321 SIO_CLR(VR_MIICMD_DIR); 322 323 /* Check for ack */ 324 SIO_CLR(VR_MIICMD_CLK); 325 DELAY(1); 326 ack = CSR_READ_4(sc, VR_MIICMD) & VR_MIICMD_DATAOUT; 327 SIO_SET(VR_MIICMD_CLK); 328 DELAY(1); 329 330 /* 331 * Now try reading data bits. If the ack failed, we still 332 * need to clock through 16 cycles to keep the PHY(s) in sync. 333 */ 334 if (ack) { 335 for(i = 0; i < 16; i++) { 336 SIO_CLR(VR_MIICMD_CLK); 337 DELAY(1); 338 SIO_SET(VR_MIICMD_CLK); 339 DELAY(1); 340 } 341 goto fail; 342 } 343 344 for (i = 0x8000; i; i >>= 1) { 345 SIO_CLR(VR_MIICMD_CLK); 346 DELAY(1); 347 if (!ack) { 348 if (CSR_READ_4(sc, VR_MIICMD) & VR_MIICMD_DATAOUT) 349 frame->mii_data |= i; 350 DELAY(1); 351 } 352 SIO_SET(VR_MIICMD_CLK); 353 DELAY(1); 354 } 355 356 fail: 357 SIO_CLR(VR_MIICMD_CLK); 358 DELAY(1); 359 SIO_SET(VR_MIICMD_CLK); 360 DELAY(1); 361 362 if (ack) 363 return(1); 364 return(0); 365 } 366 #else 367 { 368 int i; 369 370 /* Set the PHY address. */ 371 CSR_WRITE_1(sc, VR_PHYADDR, (CSR_READ_1(sc, VR_PHYADDR)& 0xe0)| 372 frame->mii_phyaddr); 373 374 /* Set the register address. */ 375 CSR_WRITE_1(sc, VR_MIIADDR, frame->mii_regaddr); 376 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_READ_ENB); 377 378 for (i = 0; i < 10000; i++) { 379 if ((CSR_READ_1(sc, VR_MIICMD) & VR_MIICMD_READ_ENB) == 0) 380 break; 381 DELAY(1); 382 } 383 frame->mii_data = CSR_READ_2(sc, VR_MIIDATA); 384 385 return(0); 386 } 387 #endif 388 389 390 /* 391 * Write to a PHY register through the MII. 392 */ 393 static int 394 vr_mii_writereg(struct vr_softc *sc, struct vr_mii_frame *frame) 395 #ifdef VR_USESWSHIFT 396 { 397 CSR_WRITE_1(sc, VR_MIICMD, 0); 398 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_DIRECTPGM); 399 400 /* Set up frame for TX. */ 401 frame->mii_stdelim = VR_MII_STARTDELIM; 402 frame->mii_opcode = VR_MII_WRITEOP; 403 frame->mii_turnaround = VR_MII_TURNAROUND; 404 405 /* Turn on data output. */ 406 SIO_SET(VR_MIICMD_DIR); 407 408 vr_mii_sync(sc); 409 410 vr_mii_send(sc, frame->mii_stdelim, 2); 411 vr_mii_send(sc, frame->mii_opcode, 2); 412 vr_mii_send(sc, frame->mii_phyaddr, 5); 413 vr_mii_send(sc, frame->mii_regaddr, 5); 414 vr_mii_send(sc, frame->mii_turnaround, 2); 415 vr_mii_send(sc, frame->mii_data, 16); 416 417 /* Idle bit. */ 418 SIO_SET(VR_MIICMD_CLK); 419 DELAY(1); 420 SIO_CLR(VR_MIICMD_CLK); 421 DELAY(1); 422 423 /* Turn off xmit. */ 424 SIO_CLR(VR_MIICMD_DIR); 425 426 return(0); 427 } 428 #else 429 { 430 int i; 431 432 /* Set the PHY-adress */ 433 CSR_WRITE_1(sc, VR_PHYADDR, (CSR_READ_1(sc, VR_PHYADDR)& 0xe0)| 434 frame->mii_phyaddr); 435 436 /* Set the register address and data to write. */ 437 CSR_WRITE_1(sc, VR_MIIADDR, frame->mii_regaddr); 438 CSR_WRITE_2(sc, VR_MIIDATA, frame->mii_data); 439 440 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_WRITE_ENB); 441 442 for (i = 0; i < 10000; i++) { 443 if ((CSR_READ_1(sc, VR_MIICMD) & VR_MIICMD_WRITE_ENB) == 0) 444 break; 445 DELAY(1); 446 } 447 return(0); 448 } 449 #endif 450 451 static int 452 vr_miibus_readreg(device_t dev, int phy, int reg) 453 { 454 struct vr_mii_frame frame; 455 struct vr_softc *sc; 456 457 sc = device_get_softc(dev); 458 459 switch (sc->vr_revid) { 460 case REV_ID_VT6102_APOLLO: 461 if (phy != 1) 462 return(0); 463 break; 464 default: 465 break; 466 } 467 468 bzero(&frame, sizeof(frame)); 469 470 frame.mii_phyaddr = phy; 471 frame.mii_regaddr = reg; 472 vr_mii_readreg(sc, &frame); 473 474 return(frame.mii_data); 475 } 476 477 static int 478 vr_miibus_writereg(device_t dev, int phy, int reg, int data) 479 { 480 struct vr_mii_frame frame; 481 struct vr_softc *sc; 482 483 sc = device_get_softc(dev); 484 485 switch (sc->vr_revid) { 486 case REV_ID_VT6102_APOLLO: 487 if (phy != 1) 488 return 0; 489 break; 490 default: 491 break; 492 } 493 494 bzero(&frame, sizeof(frame)); 495 496 frame.mii_phyaddr = phy; 497 frame.mii_regaddr = reg; 498 frame.mii_data = data; 499 500 vr_mii_writereg(sc, &frame); 501 502 return(0); 503 } 504 505 static void 506 vr_miibus_statchg(device_t dev) 507 { 508 struct mii_data *mii; 509 struct vr_softc *sc; 510 511 sc = device_get_softc(dev); 512 mii = device_get_softc(sc->vr_miibus); 513 vr_setcfg(sc, mii->mii_media_active); 514 } 515 516 /* 517 * Program the 64-bit multicast hash filter. 518 */ 519 static void 520 vr_setmulti(struct vr_softc *sc) 521 { 522 struct ifnet *ifp; 523 uint32_t hashes[2] = { 0, 0 }; 524 struct ifmultiaddr *ifma; 525 uint8_t rxfilt; 526 int mcnt = 0; 527 528 ifp = &sc->arpcom.ac_if; 529 530 rxfilt = CSR_READ_1(sc, VR_RXCFG); 531 532 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 533 rxfilt |= VR_RXCFG_RX_MULTI; 534 CSR_WRITE_1(sc, VR_RXCFG, rxfilt); 535 CSR_WRITE_4(sc, VR_MAR0, 0xFFFFFFFF); 536 CSR_WRITE_4(sc, VR_MAR1, 0xFFFFFFFF); 537 return; 538 } 539 540 /* First, zero out all the existing hash bits. */ 541 CSR_WRITE_4(sc, VR_MAR0, 0); 542 CSR_WRITE_4(sc, VR_MAR1, 0); 543 544 /* Now program new ones. */ 545 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 546 int h; 547 548 if (ifma->ifma_addr->sa_family != AF_LINK) 549 continue; 550 551 /* use the lower 6 bits */ 552 h = (ether_crc32_be( 553 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 554 ETHER_ADDR_LEN) >> 26) & 0x0000003F; 555 if (h < 32) 556 hashes[0] |= (1 << h); 557 else 558 hashes[1] |= (1 << (h - 32)); 559 mcnt++; 560 } 561 562 if (mcnt) 563 rxfilt |= VR_RXCFG_RX_MULTI; 564 else 565 rxfilt &= ~VR_RXCFG_RX_MULTI; 566 567 CSR_WRITE_4(sc, VR_MAR0, hashes[0]); 568 CSR_WRITE_4(sc, VR_MAR1, hashes[1]); 569 CSR_WRITE_1(sc, VR_RXCFG, rxfilt); 570 } 571 572 /* 573 * In order to fiddle with the 574 * 'full-duplex' and '100Mbps' bits in the netconfig register, we 575 * first have to put the transmit and/or receive logic in the idle state. 576 */ 577 static void 578 vr_setcfg(struct vr_softc *sc, int media) 579 { 580 int restart = 0; 581 582 if (CSR_READ_2(sc, VR_COMMAND) & (VR_CMD_TX_ON|VR_CMD_RX_ON)) { 583 restart = 1; 584 VR_CLRBIT16(sc, VR_COMMAND, (VR_CMD_TX_ON|VR_CMD_RX_ON)); 585 } 586 587 if ((media & IFM_GMASK) == IFM_FDX) 588 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_FULLDUPLEX); 589 else 590 VR_CLRBIT16(sc, VR_COMMAND, VR_CMD_FULLDUPLEX); 591 592 if (restart) 593 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_ON|VR_CMD_RX_ON); 594 } 595 596 static void 597 vr_reset(struct vr_softc *sc) 598 { 599 int i; 600 601 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RESET); 602 603 for (i = 0; i < VR_TIMEOUT; i++) { 604 DELAY(10); 605 if (!(CSR_READ_2(sc, VR_COMMAND) & VR_CMD_RESET)) 606 break; 607 } 608 if (i == VR_TIMEOUT) { 609 struct ifnet *ifp = &sc->arpcom.ac_if; 610 611 if (sc->vr_revid < REV_ID_VT3065_A) { 612 if_printf(ifp, "reset never completed!\n"); 613 } else { 614 /* Use newer force reset command */ 615 if_printf(ifp, "Using force reset command.\n"); 616 VR_SETBIT(sc, VR_MISC_CR1, VR_MISCCR1_FORSRST); 617 } 618 } 619 620 /* Wait a little while for the chip to get its brains in order. */ 621 DELAY(1000); 622 } 623 624 /* 625 * Probe for a VIA Rhine chip. Check the PCI vendor and device 626 * IDs against our list and return a device name if we find a match. 627 */ 628 static int 629 vr_probe(device_t dev) 630 { 631 struct vr_type *t; 632 uint16_t vid, did; 633 634 vid = pci_get_vendor(dev); 635 did = pci_get_device(dev); 636 637 for (t = vr_devs; t->vr_name != NULL; ++t) { 638 if (vid == t->vr_vid && did == t->vr_did) { 639 device_set_desc(dev, t->vr_name); 640 return(0); 641 } 642 } 643 644 return(ENXIO); 645 } 646 647 /* 648 * Attach the interface. Allocate softc structures, do ifmedia 649 * setup and ethernet/BPF attach. 650 */ 651 static int 652 vr_attach(device_t dev) 653 { 654 int i; 655 uint8_t eaddr[ETHER_ADDR_LEN]; 656 struct vr_softc *sc; 657 struct ifnet *ifp; 658 int error = 0, rid; 659 660 sc = device_get_softc(dev); 661 callout_init(&sc->vr_stat_timer); 662 663 /* 664 * Handle power management nonsense. 665 */ 666 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 667 uint32_t iobase, membase, irq; 668 669 /* Save important PCI config data. */ 670 iobase = pci_read_config(dev, VR_PCI_LOIO, 4); 671 membase = pci_read_config(dev, VR_PCI_LOMEM, 4); 672 irq = pci_read_config(dev, VR_PCI_INTLINE, 4); 673 674 /* Reset the power state. */ 675 device_printf(dev, "chip is in D%d power mode " 676 "-- setting to D0\n", pci_get_powerstate(dev)); 677 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 678 679 /* Restore PCI config data. */ 680 pci_write_config(dev, VR_PCI_LOIO, iobase, 4); 681 pci_write_config(dev, VR_PCI_LOMEM, membase, 4); 682 pci_write_config(dev, VR_PCI_INTLINE, irq, 4); 683 } 684 685 pci_enable_busmaster(dev); 686 687 sc->vr_revid = pci_get_revid(dev); 688 689 rid = VR_RID; 690 sc->vr_res = bus_alloc_resource_any(dev, VR_RES, &rid, RF_ACTIVE); 691 692 if (sc->vr_res == NULL) { 693 device_printf(dev, "couldn't map ports/memory\n"); 694 return ENXIO; 695 } 696 697 sc->vr_btag = rman_get_bustag(sc->vr_res); 698 sc->vr_bhandle = rman_get_bushandle(sc->vr_res); 699 700 /* Allocate interrupt */ 701 rid = 0; 702 sc->vr_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 703 RF_SHAREABLE | RF_ACTIVE); 704 705 if (sc->vr_irq == NULL) { 706 device_printf(dev, "couldn't map interrupt\n"); 707 error = ENXIO; 708 goto fail; 709 } 710 711 /* 712 * Windows may put the chip in suspend mode when it 713 * shuts down. Be sure to kick it in the head to wake it 714 * up again. 715 */ 716 VR_CLRBIT(sc, VR_STICKHW, (VR_STICKHW_DS0|VR_STICKHW_DS1)); 717 718 ifp = &sc->arpcom.ac_if; 719 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 720 721 /* Reset the adapter. */ 722 vr_reset(sc); 723 724 /* 725 * Turn on bit2 (MIION) in PCI configuration register 0x53 during 726 * initialization and disable AUTOPOLL. 727 */ 728 pci_write_config(dev, VR_PCI_MODE, 729 pci_read_config(dev, VR_PCI_MODE, 4) | (VR_MODE3_MIION << 24), 4); 730 VR_CLRBIT(sc, VR_MIICMD, VR_MIICMD_AUTOPOLL); 731 732 /* 733 * Get station address. The way the Rhine chips work, 734 * you're not allowed to directly access the EEPROM once 735 * they've been programmed a special way. Consequently, 736 * we need to read the node address from the PAR0 and PAR1 737 * registers. 738 */ 739 VR_SETBIT(sc, VR_EECSR, VR_EECSR_LOAD); 740 DELAY(200); 741 for (i = 0; i < ETHER_ADDR_LEN; i++) 742 eaddr[i] = CSR_READ_1(sc, VR_PAR0 + i); 743 744 sc->vr_ldata = contigmalloc(sizeof(struct vr_list_data), M_DEVBUF, 745 M_WAITOK | M_ZERO, 0, 0xffffffff, PAGE_SIZE, 0); 746 747 if (sc->vr_ldata == NULL) { 748 device_printf(dev, "no memory for list buffers!\n"); 749 error = ENXIO; 750 goto fail; 751 } 752 753 /* Initialize TX buffer */ 754 sc->vr_cdata.vr_tx_buf = contigmalloc(VR_TX_BUF_SIZE, M_DEVBUF, 755 M_WAITOK, 0, 0xffffffff, PAGE_SIZE, 0); 756 if (sc->vr_cdata.vr_tx_buf == NULL) { 757 device_printf(dev, "can't allocate tx buffer!\n"); 758 error = ENXIO; 759 goto fail; 760 } 761 762 /* Set various TX indexes to invalid value */ 763 sc->vr_cdata.vr_tx_free_idx = -1; 764 sc->vr_cdata.vr_tx_tail_idx = -1; 765 sc->vr_cdata.vr_tx_head_idx = -1; 766 767 768 ifp->if_softc = sc; 769 ifp->if_mtu = ETHERMTU; 770 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 771 ifp->if_ioctl = vr_ioctl; 772 ifp->if_start = vr_start; 773 #ifdef DEVICE_POLLING 774 ifp->if_poll = vr_poll; 775 #endif 776 ifp->if_watchdog = vr_watchdog; 777 ifp->if_init = vr_init; 778 ifp->if_baudrate = 10000000; 779 ifq_set_maxlen(&ifp->if_snd, VR_TX_LIST_CNT - 1); 780 ifq_set_ready(&ifp->if_snd); 781 782 /* 783 * Do MII setup. 784 */ 785 if (mii_phy_probe(dev, &sc->vr_miibus, 786 vr_ifmedia_upd, vr_ifmedia_sts)) { 787 if_printf(ifp, "MII without any phy!\n"); 788 error = ENXIO; 789 goto fail; 790 } 791 792 /* Call MI attach routine. */ 793 ether_ifattach(ifp, eaddr, NULL); 794 795 error = bus_setup_intr(dev, sc->vr_irq, INTR_NETSAFE, 796 vr_intr, sc, &sc->vr_intrhand, 797 ifp->if_serializer); 798 799 if (error) { 800 device_printf(dev, "couldn't set up irq\n"); 801 ether_ifdetach(ifp); 802 goto fail; 803 } 804 return 0; 805 806 fail: 807 vr_detach(dev); 808 return(error); 809 } 810 811 static int 812 vr_detach(device_t dev) 813 { 814 struct vr_softc *sc = device_get_softc(dev); 815 struct ifnet *ifp = &sc->arpcom.ac_if; 816 817 if (device_is_attached(dev)) { 818 lwkt_serialize_enter(ifp->if_serializer); 819 vr_stop(sc); 820 bus_teardown_intr(dev, sc->vr_irq, sc->vr_intrhand); 821 lwkt_serialize_exit(ifp->if_serializer); 822 823 ether_ifdetach(ifp); 824 } 825 if (sc->vr_miibus != NULL) 826 device_delete_child(dev, sc->vr_miibus); 827 bus_generic_detach(dev); 828 829 if (sc->vr_irq != NULL) 830 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->vr_irq); 831 if (sc->vr_res != NULL) 832 bus_release_resource(dev, VR_RES, VR_RID, sc->vr_res); 833 if (sc->vr_ldata != NULL) 834 contigfree(sc->vr_ldata, sizeof(struct vr_list_data), M_DEVBUF); 835 if (sc->vr_cdata.vr_tx_buf != NULL) 836 contigfree(sc->vr_cdata.vr_tx_buf, VR_TX_BUF_SIZE, M_DEVBUF); 837 838 return(0); 839 } 840 841 /* 842 * Initialize the transmit descriptors. 843 */ 844 static int 845 vr_list_tx_init(struct vr_softc *sc) 846 { 847 struct vr_chain_data *cd; 848 struct vr_list_data *ld; 849 struct vr_chain *tx_chain; 850 int i; 851 852 cd = &sc->vr_cdata; 853 ld = sc->vr_ldata; 854 tx_chain = cd->vr_tx_chain; 855 856 for (i = 0; i < VR_TX_LIST_CNT; i++) { 857 tx_chain[i].vr_ptr = &ld->vr_tx_list[i]; 858 if (i == (VR_TX_LIST_CNT - 1)) 859 tx_chain[i].vr_next_idx = 0; 860 else 861 tx_chain[i].vr_next_idx = i + 1; 862 } 863 864 for (i = 0; i < VR_TX_LIST_CNT; ++i) { 865 void *tx_buf; 866 int next_idx; 867 868 tx_buf = VR_TX_BUF(sc, i); 869 next_idx = tx_chain[i].vr_next_idx; 870 871 tx_chain[i].vr_next_desc_paddr = 872 vtophys(tx_chain[next_idx].vr_ptr); 873 tx_chain[i].vr_buf_paddr = vtophys(tx_buf); 874 } 875 876 cd->vr_tx_free_idx = 0; 877 cd->vr_tx_tail_idx = cd->vr_tx_head_idx = -1; 878 879 return 0; 880 } 881 882 883 /* 884 * Initialize the RX descriptors and allocate mbufs for them. Note that 885 * we arrange the descriptors in a closed ring, so that the last descriptor 886 * points back to the first. 887 */ 888 static int 889 vr_list_rx_init(struct vr_softc *sc) 890 { 891 struct vr_chain_data *cd; 892 struct vr_list_data *ld; 893 int i, nexti; 894 895 cd = &sc->vr_cdata; 896 ld = sc->vr_ldata; 897 898 for (i = 0; i < VR_RX_LIST_CNT; i++) { 899 cd->vr_rx_chain[i].vr_ptr = (struct vr_desc *)&ld->vr_rx_list[i]; 900 if (vr_newbuf(sc, &cd->vr_rx_chain[i], NULL) == ENOBUFS) 901 return(ENOBUFS); 902 if (i == (VR_RX_LIST_CNT - 1)) 903 nexti = 0; 904 else 905 nexti = i + 1; 906 cd->vr_rx_chain[i].vr_nextdesc = &cd->vr_rx_chain[nexti]; 907 ld->vr_rx_list[i].vr_next = vtophys(&ld->vr_rx_list[nexti]); 908 } 909 910 cd->vr_rx_head = &cd->vr_rx_chain[0]; 911 912 return(0); 913 } 914 915 /* 916 * Initialize an RX descriptor and attach an MBUF cluster. 917 * Note: the length fields are only 11 bits wide, which means the 918 * largest size we can specify is 2047. This is important because 919 * MCLBYTES is 2048, so we have to subtract one otherwise we'll 920 * overflow the field and make a mess. 921 */ 922 static int 923 vr_newbuf(struct vr_softc *sc, struct vr_chain_onefrag *c, struct mbuf *m) 924 { 925 struct mbuf *m_new = NULL; 926 927 if (m == NULL) { 928 m_new = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR); 929 if (m_new == NULL) 930 return (ENOBUFS); 931 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 932 } else { 933 m_new = m; 934 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 935 m_new->m_data = m_new->m_ext.ext_buf; 936 } 937 938 m_adj(m_new, sizeof(uint64_t)); 939 940 c->vr_mbuf = m_new; 941 c->vr_ptr->vr_status = VR_RXSTAT; 942 c->vr_ptr->vr_data = vtophys(mtod(m_new, caddr_t)); 943 c->vr_ptr->vr_ctl = VR_RXCTL | VR_RXLEN; 944 945 return(0); 946 } 947 948 /* 949 * A frame has been uploaded: pass the resulting mbuf chain up to 950 * the higher level protocols. 951 */ 952 static void 953 vr_rxeof(struct vr_softc *sc) 954 { 955 struct mbuf *m; 956 struct ifnet *ifp; 957 struct vr_chain_onefrag *cur_rx; 958 int total_len = 0; 959 uint32_t rxstat; 960 961 ifp = &sc->arpcom.ac_if; 962 963 while(!((rxstat = sc->vr_cdata.vr_rx_head->vr_ptr->vr_status) & 964 VR_RXSTAT_OWN)) { 965 struct mbuf *m0 = NULL; 966 967 cur_rx = sc->vr_cdata.vr_rx_head; 968 sc->vr_cdata.vr_rx_head = cur_rx->vr_nextdesc; 969 m = cur_rx->vr_mbuf; 970 971 /* 972 * If an error occurs, update stats, clear the 973 * status word and leave the mbuf cluster in place: 974 * it should simply get re-used next time this descriptor 975 * comes up in the ring. 976 */ 977 if (rxstat & VR_RXSTAT_RXERR) { 978 ifp->if_ierrors++; 979 if_printf(ifp, "rx error (%02x):", rxstat & 0x000000ff); 980 if (rxstat & VR_RXSTAT_CRCERR) 981 printf(" crc error"); 982 if (rxstat & VR_RXSTAT_FRAMEALIGNERR) 983 printf(" frame alignment error\n"); 984 if (rxstat & VR_RXSTAT_FIFOOFLOW) 985 printf(" FIFO overflow"); 986 if (rxstat & VR_RXSTAT_GIANT) 987 printf(" received giant packet"); 988 if (rxstat & VR_RXSTAT_RUNT) 989 printf(" received runt packet"); 990 if (rxstat & VR_RXSTAT_BUSERR) 991 printf(" system bus error"); 992 if (rxstat & VR_RXSTAT_BUFFERR) 993 printf("rx buffer error"); 994 printf("\n"); 995 vr_newbuf(sc, cur_rx, m); 996 continue; 997 } 998 999 /* No errors; receive the packet. */ 1000 total_len = VR_RXBYTES(cur_rx->vr_ptr->vr_status); 1001 1002 /* 1003 * XXX The VIA Rhine chip includes the CRC with every 1004 * received frame, and there's no way to turn this 1005 * behavior off (at least, I can't find anything in 1006 * the manual that explains how to do it) so we have 1007 * to trim off the CRC manually. 1008 */ 1009 total_len -= ETHER_CRC_LEN; 1010 1011 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 1012 total_len + ETHER_ALIGN, 0, ifp, NULL); 1013 vr_newbuf(sc, cur_rx, m); 1014 if (m0 == NULL) { 1015 ifp->if_ierrors++; 1016 continue; 1017 } 1018 m_adj(m0, ETHER_ALIGN); 1019 m = m0; 1020 1021 ifp->if_ipackets++; 1022 ifp->if_input(ifp, m); 1023 } 1024 } 1025 1026 static void 1027 vr_rxeoc(struct vr_softc *sc) 1028 { 1029 struct ifnet *ifp; 1030 int i; 1031 1032 ifp = &sc->arpcom.ac_if; 1033 1034 ifp->if_ierrors++; 1035 1036 VR_CLRBIT16(sc, VR_COMMAND, VR_CMD_RX_ON); 1037 DELAY(10000); 1038 1039 /* Wait for receiver to stop */ 1040 for (i = 0x400; 1041 i && (CSR_READ_2(sc, VR_COMMAND) & VR_CMD_RX_ON); 1042 i--) 1043 ; /* Wait for receiver to stop */ 1044 1045 if (i == 0) { 1046 if_printf(ifp, "rx shutdown error!\n"); 1047 sc->vr_flags |= VR_F_RESTART; 1048 return; 1049 } 1050 1051 vr_rxeof(sc); 1052 1053 CSR_WRITE_4(sc, VR_RXADDR, vtophys(sc->vr_cdata.vr_rx_head->vr_ptr)); 1054 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RX_ON); 1055 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RX_GO); 1056 } 1057 1058 /* 1059 * A frame was downloaded to the chip. It's safe for us to clean up 1060 * the list buffers. 1061 */ 1062 static void 1063 vr_txeof(struct vr_softc *sc) 1064 { 1065 struct vr_chain_data *cd; 1066 struct vr_chain *tx_chain; 1067 struct ifnet *ifp; 1068 1069 ifp = &sc->arpcom.ac_if; 1070 cd = &sc->vr_cdata; 1071 1072 /* Reset the timeout timer; if_txeoc will clear it. */ 1073 ifp->if_timer = 5; 1074 1075 /* Sanity check. */ 1076 if (cd->vr_tx_head_idx == -1) 1077 return; 1078 1079 tx_chain = cd->vr_tx_chain; 1080 1081 /* 1082 * Go through our tx list and free mbufs for those 1083 * frames that have been transmitted. 1084 */ 1085 while(tx_chain[cd->vr_tx_head_idx].vr_buf != NULL) { 1086 struct vr_chain *cur_tx; 1087 uint32_t txstat; 1088 int i; 1089 1090 cur_tx = &tx_chain[cd->vr_tx_head_idx]; 1091 txstat = cur_tx->vr_ptr->vr_status; 1092 1093 if ((txstat & VR_TXSTAT_ABRT) || 1094 (txstat & VR_TXSTAT_UDF)) { 1095 for (i = 0x400; 1096 i && (CSR_READ_2(sc, VR_COMMAND) & VR_CMD_TX_ON); 1097 i--) 1098 ; /* Wait for chip to shutdown */ 1099 if (i == 0) { 1100 if_printf(ifp, "tx shutdown timeout\n"); 1101 sc->vr_flags |= VR_F_RESTART; 1102 break; 1103 } 1104 VR_TXOWN(cur_tx) = VR_TXSTAT_OWN; 1105 CSR_WRITE_4(sc, VR_TXADDR, vtophys(cur_tx->vr_ptr)); 1106 break; 1107 } 1108 1109 if (txstat & VR_TXSTAT_OWN) 1110 break; 1111 1112 if (txstat & VR_TXSTAT_ERRSUM) { 1113 ifp->if_oerrors++; 1114 if (txstat & VR_TXSTAT_DEFER) 1115 ifp->if_collisions++; 1116 if (txstat & VR_TXSTAT_LATECOLL) 1117 ifp->if_collisions++; 1118 } 1119 1120 ifp->if_collisions += (txstat & VR_TXSTAT_COLLCNT) >> 3; 1121 1122 ifp->if_opackets++; 1123 cur_tx->vr_buf = NULL; 1124 1125 if (cd->vr_tx_head_idx == cd->vr_tx_tail_idx) { 1126 cd->vr_tx_head_idx = -1; 1127 cd->vr_tx_tail_idx = -1; 1128 break; 1129 } 1130 1131 cd->vr_tx_head_idx = cur_tx->vr_next_idx; 1132 } 1133 } 1134 1135 /* 1136 * TX 'end of channel' interrupt handler. 1137 */ 1138 static void 1139 vr_txeoc(struct vr_softc *sc) 1140 { 1141 struct ifnet *ifp; 1142 1143 ifp = &sc->arpcom.ac_if; 1144 1145 if (sc->vr_cdata.vr_tx_head_idx == -1) { 1146 ifp->if_flags &= ~IFF_OACTIVE; 1147 sc->vr_cdata.vr_tx_tail_idx = -1; 1148 ifp->if_timer = 0; 1149 } 1150 } 1151 1152 static void 1153 vr_tick(void *xsc) 1154 { 1155 struct vr_softc *sc = xsc; 1156 struct ifnet *ifp = &sc->arpcom.ac_if; 1157 struct mii_data *mii; 1158 1159 lwkt_serialize_enter(ifp->if_serializer); 1160 1161 if (sc->vr_flags & VR_F_RESTART) { 1162 if_printf(&sc->arpcom.ac_if, "restarting\n"); 1163 vr_stop(sc); 1164 vr_reset(sc); 1165 vr_init(sc); 1166 sc->vr_flags &= ~VR_F_RESTART; 1167 } 1168 1169 mii = device_get_softc(sc->vr_miibus); 1170 mii_tick(mii); 1171 1172 callout_reset(&sc->vr_stat_timer, hz, vr_tick, sc); 1173 1174 lwkt_serialize_exit(ifp->if_serializer); 1175 } 1176 1177 static void 1178 vr_intr(void *arg) 1179 { 1180 struct vr_softc *sc; 1181 struct ifnet *ifp; 1182 uint16_t status; 1183 1184 sc = arg; 1185 ifp = &sc->arpcom.ac_if; 1186 1187 /* Supress unwanted interrupts. */ 1188 if (!(ifp->if_flags & IFF_UP)) { 1189 vr_stop(sc); 1190 return; 1191 } 1192 1193 /* Disable interrupts. */ 1194 if ((ifp->if_flags & IFF_POLLING) == 0) 1195 CSR_WRITE_2(sc, VR_IMR, 0x0000); 1196 1197 for (;;) { 1198 status = CSR_READ_2(sc, VR_ISR); 1199 if (status) 1200 CSR_WRITE_2(sc, VR_ISR, status); 1201 1202 if ((status & VR_INTRS) == 0) 1203 break; 1204 1205 if (status & VR_ISR_RX_OK) 1206 vr_rxeof(sc); 1207 1208 if (status & VR_ISR_RX_DROPPED) { 1209 if_printf(ifp, "rx packet lost\n"); 1210 ifp->if_ierrors++; 1211 } 1212 1213 if ((status & VR_ISR_RX_ERR) || (status & VR_ISR_RX_NOBUF) || 1214 (status & VR_ISR_RX_NOBUF) || (status & VR_ISR_RX_OFLOW)) { 1215 if_printf(ifp, "receive error (%04x)", status); 1216 if (status & VR_ISR_RX_NOBUF) 1217 printf(" no buffers"); 1218 if (status & VR_ISR_RX_OFLOW) 1219 printf(" overflow"); 1220 if (status & VR_ISR_RX_DROPPED) 1221 printf(" packet lost"); 1222 printf("\n"); 1223 vr_rxeoc(sc); 1224 } 1225 1226 if ((status & VR_ISR_BUSERR) || (status & VR_ISR_TX_UNDERRUN)) { 1227 vr_reset(sc); 1228 vr_init(sc); 1229 break; 1230 } 1231 1232 if ((status & VR_ISR_TX_OK) || (status & VR_ISR_TX_ABRT) || 1233 (status & VR_ISR_TX_ABRT2) || (status & VR_ISR_UDFI)) { 1234 vr_txeof(sc); 1235 if ((status & VR_ISR_UDFI) || 1236 (status & VR_ISR_TX_ABRT2) || 1237 (status & VR_ISR_TX_ABRT)) { 1238 ifp->if_oerrors++; 1239 if (sc->vr_cdata.vr_tx_head_idx != -1) { 1240 VR_SETBIT16(sc, VR_COMMAND, 1241 VR_CMD_TX_ON); 1242 VR_SETBIT16(sc, VR_COMMAND, 1243 VR_CMD_TX_GO); 1244 } 1245 } else { 1246 vr_txeoc(sc); 1247 } 1248 } 1249 1250 } 1251 1252 /* Re-enable interrupts. */ 1253 if ((ifp->if_flags & IFF_POLLING) == 0) 1254 CSR_WRITE_2(sc, VR_IMR, VR_INTRS); 1255 1256 if (!ifq_is_empty(&ifp->if_snd)) 1257 vr_start(ifp); 1258 } 1259 1260 /* 1261 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1262 * pointers to the fragment pointers. 1263 */ 1264 static int 1265 vr_encap(struct vr_softc *sc, int chain_idx, struct mbuf *m_head) 1266 { 1267 struct vr_chain *c; 1268 struct vr_desc *f; 1269 caddr_t tx_buf; 1270 int len; 1271 1272 KASSERT(chain_idx >= 0 && chain_idx < VR_TX_LIST_CNT, 1273 ("%s: chain idx(%d) out of range 0-%d", 1274 sc->arpcom.ac_if.if_xname, chain_idx, VR_TX_LIST_CNT)); 1275 1276 /* 1277 * The VIA Rhine wants packet buffers to be longword 1278 * aligned, but very often our mbufs aren't. Rather than 1279 * waste time trying to decide when to copy and when not 1280 * to copy, just do it all the time. 1281 */ 1282 tx_buf = VR_TX_BUF(sc, chain_idx); 1283 m_copydata(m_head, 0, m_head->m_pkthdr.len, tx_buf); 1284 len = m_head->m_pkthdr.len; 1285 1286 /* 1287 * The Rhine chip doesn't auto-pad, so we have to make 1288 * sure to pad short frames out to the minimum frame length 1289 * ourselves. 1290 */ 1291 if (len < VR_MIN_FRAMELEN) { 1292 bzero(tx_buf + len, VR_MIN_FRAMELEN - len); 1293 len = VR_MIN_FRAMELEN; 1294 } 1295 1296 c = &sc->vr_cdata.vr_tx_chain[chain_idx]; 1297 c->vr_buf = tx_buf; 1298 1299 f = c->vr_ptr; 1300 f->vr_data = c->vr_buf_paddr; 1301 f->vr_ctl = len; 1302 f->vr_ctl |= (VR_TXCTL_TLINK | VR_TXCTL_FIRSTFRAG); 1303 f->vr_ctl |= (VR_TXCTL_LASTFRAG | VR_TXCTL_FINT); 1304 f->vr_status = 0; 1305 f->vr_next = c->vr_next_desc_paddr; 1306 1307 return(0); 1308 } 1309 1310 /* 1311 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1312 * to the mbuf data regions directly in the transmit lists. We also save a 1313 * copy of the pointers since the transmit list fragment pointers are 1314 * physical addresses. 1315 */ 1316 static void 1317 vr_start(struct ifnet *ifp) 1318 { 1319 struct vr_softc *sc; 1320 struct vr_chain_data *cd; 1321 struct vr_chain *tx_chain; 1322 int cur_tx_idx, start_tx_idx, prev_tx_idx; 1323 1324 if (ifp->if_flags & IFF_OACTIVE) 1325 return; 1326 1327 sc = ifp->if_softc; 1328 cd = &sc->vr_cdata; 1329 tx_chain = cd->vr_tx_chain; 1330 1331 start_tx_idx = cd->vr_tx_free_idx; 1332 cur_tx_idx = prev_tx_idx = -1; 1333 1334 /* Check for an available queue slot. If there are none, punt. */ 1335 if (tx_chain[start_tx_idx].vr_buf != NULL) { 1336 ifp->if_flags |= IFF_OACTIVE; 1337 return; 1338 } 1339 1340 while(tx_chain[cd->vr_tx_free_idx].vr_buf == NULL) { 1341 struct mbuf *m_head; 1342 struct vr_chain *cur_tx; 1343 1344 m_head = ifq_poll(&ifp->if_snd); 1345 if (m_head == NULL) 1346 break; 1347 1348 /* Pick a descriptor off the free list. */ 1349 cur_tx_idx = cd->vr_tx_free_idx; 1350 cur_tx = &tx_chain[cur_tx_idx]; 1351 1352 /* Pack the data into the descriptor. */ 1353 if (vr_encap(sc, cur_tx_idx, m_head)) { 1354 ifp->if_flags |= IFF_OACTIVE; 1355 cur_tx_idx = prev_tx_idx; 1356 break; 1357 } 1358 1359 ifq_dequeue(&ifp->if_snd, m_head); 1360 1361 /* XXX */ 1362 if (cur_tx_idx != start_tx_idx) 1363 VR_TXOWN(cur_tx) = VR_TXSTAT_OWN; 1364 1365 BPF_MTAP(ifp, m_head); 1366 m_freem(m_head); 1367 1368 VR_TXOWN(cur_tx) = VR_TXSTAT_OWN; 1369 VR_SETBIT16(sc, VR_COMMAND, /*VR_CMD_TX_ON|*/VR_CMD_TX_GO); 1370 1371 /* Iff everything went OK, we bump up free index. */ 1372 prev_tx_idx = cur_tx_idx; 1373 cd->vr_tx_free_idx = cur_tx->vr_next_idx; 1374 } 1375 1376 /* If there are no frames queued, bail. */ 1377 if (cur_tx_idx == -1) 1378 return; 1379 1380 sc->vr_cdata.vr_tx_tail_idx = cur_tx_idx; 1381 1382 if (sc->vr_cdata.vr_tx_head_idx == -1) 1383 sc->vr_cdata.vr_tx_head_idx = start_tx_idx; 1384 1385 /* 1386 * Set a timeout in case the chip goes out to lunch. 1387 */ 1388 ifp->if_timer = 5; 1389 } 1390 1391 static void 1392 vr_init(void *xsc) 1393 { 1394 struct vr_softc *sc = xsc; 1395 struct ifnet *ifp = &sc->arpcom.ac_if; 1396 struct mii_data *mii; 1397 int i; 1398 1399 mii = device_get_softc(sc->vr_miibus); 1400 1401 /* Cancel pending I/O and free all RX/TX buffers. */ 1402 vr_stop(sc); 1403 vr_reset(sc); 1404 1405 /* Set our station address. */ 1406 for (i = 0; i < ETHER_ADDR_LEN; i++) 1407 CSR_WRITE_1(sc, VR_PAR0 + i, sc->arpcom.ac_enaddr[i]); 1408 1409 /* Set DMA size. */ 1410 VR_CLRBIT(sc, VR_BCR0, VR_BCR0_DMA_LENGTH); 1411 VR_SETBIT(sc, VR_BCR0, VR_BCR0_DMA_STORENFWD); 1412 1413 /* 1414 * BCR0 and BCR1 can override the RXCFG and TXCFG registers, 1415 * so we must set both. 1416 */ 1417 VR_CLRBIT(sc, VR_BCR0, VR_BCR0_RX_THRESH); 1418 VR_SETBIT(sc, VR_BCR0, VR_BCR0_RXTHRESH128BYTES); 1419 1420 VR_CLRBIT(sc, VR_BCR1, VR_BCR1_TX_THRESH); 1421 VR_SETBIT(sc, VR_BCR1, VR_BCR1_TXTHRESHSTORENFWD); 1422 1423 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_THRESH); 1424 VR_SETBIT(sc, VR_RXCFG, VR_RXTHRESH_128BYTES); 1425 1426 VR_CLRBIT(sc, VR_TXCFG, VR_TXCFG_TX_THRESH); 1427 VR_SETBIT(sc, VR_TXCFG, VR_TXTHRESH_STORENFWD); 1428 1429 /* Init circular RX list. */ 1430 if (vr_list_rx_init(sc) == ENOBUFS) { 1431 vr_stop(sc); 1432 if_printf(ifp, "initialization failed: no memory for rx buffers\n"); 1433 return; 1434 } 1435 1436 /* Init tx descriptors. */ 1437 vr_list_tx_init(sc); 1438 1439 /* If we want promiscuous mode, set the allframes bit. */ 1440 if (ifp->if_flags & IFF_PROMISC) 1441 VR_SETBIT(sc, VR_RXCFG, VR_RXCFG_RX_PROMISC); 1442 else 1443 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_PROMISC); 1444 1445 /* Set capture broadcast bit to capture broadcast frames. */ 1446 if (ifp->if_flags & IFF_BROADCAST) 1447 VR_SETBIT(sc, VR_RXCFG, VR_RXCFG_RX_BROAD); 1448 else 1449 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_BROAD); 1450 1451 /* 1452 * Program the multicast filter, if necessary. 1453 */ 1454 vr_setmulti(sc); 1455 1456 /* 1457 * Load the address of the RX list. 1458 */ 1459 CSR_WRITE_4(sc, VR_RXADDR, vtophys(sc->vr_cdata.vr_rx_head->vr_ptr)); 1460 1461 /* Enable receiver and transmitter. */ 1462 CSR_WRITE_2(sc, VR_COMMAND, VR_CMD_TX_NOPOLL|VR_CMD_START| 1463 VR_CMD_TX_ON|VR_CMD_RX_ON| 1464 VR_CMD_RX_GO); 1465 1466 CSR_WRITE_4(sc, VR_TXADDR, vtophys(&sc->vr_ldata->vr_tx_list[0])); 1467 1468 /* 1469 * Enable interrupts, unless we are polling. 1470 */ 1471 CSR_WRITE_2(sc, VR_ISR, 0xFFFF); 1472 if ((ifp->if_flags & IFF_POLLING) == 0) 1473 CSR_WRITE_2(sc, VR_IMR, VR_INTRS); 1474 1475 mii_mediachg(mii); 1476 1477 ifp->if_flags |= IFF_RUNNING; 1478 ifp->if_flags &= ~IFF_OACTIVE; 1479 1480 callout_reset(&sc->vr_stat_timer, hz, vr_tick, sc); 1481 } 1482 1483 /* 1484 * Set media options. 1485 */ 1486 static int 1487 vr_ifmedia_upd(struct ifnet *ifp) 1488 { 1489 struct vr_softc *sc; 1490 1491 sc = ifp->if_softc; 1492 1493 if (ifp->if_flags & IFF_UP) 1494 vr_init(sc); 1495 1496 return(0); 1497 } 1498 1499 /* 1500 * Report current media status. 1501 */ 1502 static void 1503 vr_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1504 { 1505 struct vr_softc *sc; 1506 struct mii_data *mii; 1507 1508 sc = ifp->if_softc; 1509 mii = device_get_softc(sc->vr_miibus); 1510 mii_pollstat(mii); 1511 ifmr->ifm_active = mii->mii_media_active; 1512 ifmr->ifm_status = mii->mii_media_status; 1513 } 1514 1515 static int 1516 vr_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr) 1517 { 1518 struct vr_softc *sc = ifp->if_softc; 1519 struct ifreq *ifr = (struct ifreq *) data; 1520 struct mii_data *mii; 1521 int error = 0; 1522 1523 switch(command) { 1524 case SIOCSIFFLAGS: 1525 if (ifp->if_flags & IFF_UP) { 1526 vr_init(sc); 1527 } else { 1528 if (ifp->if_flags & IFF_RUNNING) 1529 vr_stop(sc); 1530 } 1531 error = 0; 1532 break; 1533 case SIOCADDMULTI: 1534 case SIOCDELMULTI: 1535 vr_setmulti(sc); 1536 error = 0; 1537 break; 1538 case SIOCGIFMEDIA: 1539 case SIOCSIFMEDIA: 1540 mii = device_get_softc(sc->vr_miibus); 1541 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1542 break; 1543 default: 1544 error = ether_ioctl(ifp, command, data); 1545 break; 1546 } 1547 return(error); 1548 } 1549 1550 #ifdef DEVICE_POLLING 1551 1552 static void 1553 vr_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1554 { 1555 struct vr_softc *sc = ifp->if_softc; 1556 1557 switch(cmd) { 1558 case POLL_REGISTER: 1559 /* disable interrupts */ 1560 CSR_WRITE_2(sc, VR_IMR, 0x0000); 1561 break; 1562 case POLL_DEREGISTER: 1563 /* enable interrupts */ 1564 CSR_WRITE_2(sc, VR_IMR, VR_INTRS); 1565 break; 1566 default: 1567 vr_intr(sc); 1568 break; 1569 } 1570 } 1571 #endif 1572 1573 static void 1574 vr_watchdog(struct ifnet *ifp) 1575 { 1576 struct vr_softc *sc; 1577 1578 sc = ifp->if_softc; 1579 1580 ifp->if_oerrors++; 1581 if_printf(ifp, "watchdog timeout\n"); 1582 1583 #ifdef DEVICE_POLLING 1584 if (++sc->vr_wdogerrors == 1 && (ifp->if_flags & IFF_POLLING) == 0) { 1585 if_printf(ifp, "ints don't seem to be working, " 1586 "emergency switch to polling\n"); 1587 emergency_poll_enable("if_vr"); 1588 ether_poll_register(ifp); /* XXX illegal */ 1589 } else 1590 #endif 1591 { 1592 vr_stop(sc); 1593 vr_reset(sc); 1594 vr_init(sc); 1595 } 1596 1597 if (!ifq_is_empty(&ifp->if_snd)) 1598 vr_start(ifp); 1599 } 1600 1601 /* 1602 * Stop the adapter and free any mbufs allocated to the 1603 * RX and TX lists. 1604 */ 1605 static void 1606 vr_stop(struct vr_softc *sc) 1607 { 1608 int i; 1609 struct ifnet *ifp; 1610 1611 ifp = &sc->arpcom.ac_if; 1612 ifp->if_timer = 0; 1613 1614 callout_stop(&sc->vr_stat_timer); 1615 1616 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_STOP); 1617 VR_CLRBIT16(sc, VR_COMMAND, (VR_CMD_RX_ON|VR_CMD_TX_ON)); 1618 CSR_WRITE_2(sc, VR_IMR, 0x0000); 1619 CSR_WRITE_4(sc, VR_TXADDR, 0x00000000); 1620 CSR_WRITE_4(sc, VR_RXADDR, 0x00000000); 1621 1622 /* 1623 * Free data in the RX lists. 1624 */ 1625 for (i = 0; i < VR_RX_LIST_CNT; i++) { 1626 if (sc->vr_cdata.vr_rx_chain[i].vr_mbuf != NULL) { 1627 m_freem(sc->vr_cdata.vr_rx_chain[i].vr_mbuf); 1628 sc->vr_cdata.vr_rx_chain[i].vr_mbuf = NULL; 1629 } 1630 } 1631 bzero(&sc->vr_ldata->vr_rx_list, sizeof(sc->vr_ldata->vr_rx_list)); 1632 1633 /* 1634 * Reset the TX list buffer pointers. 1635 */ 1636 for (i = 0; i < VR_TX_LIST_CNT; i++) 1637 sc->vr_cdata.vr_tx_chain[i].vr_buf = NULL; 1638 1639 bzero(&sc->vr_ldata->vr_tx_list, sizeof(sc->vr_ldata->vr_tx_list)); 1640 1641 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1642 } 1643 1644 /* 1645 * Stop all chip I/O so that the kernel's probe routines don't 1646 * get confused by errant DMAs when rebooting. 1647 */ 1648 static void 1649 vr_shutdown(device_t dev) 1650 { 1651 struct vr_softc *sc; 1652 1653 sc = device_get_softc(dev); 1654 1655 vr_stop(sc); 1656 } 1657