1 /* 2 * Copyright (c) 1997, 1998 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: src/sys/pci/if_vr.c,v 1.26.2.13 2003/02/06 04:46:20 silby Exp $ 33 * $DragonFly: src/sys/dev/netif/vr/if_vr.c,v 1.15 2004/09/15 01:04:59 joerg Exp $ 34 * 35 * $FreeBSD: src/sys/pci/if_vr.c,v 1.26.2.13 2003/02/06 04:46:20 silby Exp $ 36 */ 37 38 /* 39 * VIA Rhine fast ethernet PCI NIC driver 40 * 41 * Supports various network adapters based on the VIA Rhine 42 * and Rhine II PCI controllers, including the D-Link DFE530TX. 43 * Datasheets are available at http://www.via.com.tw. 44 * 45 * Written by Bill Paul <wpaul@ctr.columbia.edu> 46 * Electrical Engineering Department 47 * Columbia University, New York City 48 */ 49 50 /* 51 * The VIA Rhine controllers are similar in some respects to the 52 * the DEC tulip chips, except less complicated. The controller 53 * uses an MII bus and an external physical layer interface. The 54 * receiver has a one entry perfect filter and a 64-bit hash table 55 * multicast filter. Transmit and receive descriptors are similar 56 * to the tulip. 57 * 58 * The Rhine has a serious flaw in its transmit DMA mechanism: 59 * transmit buffers must be longword aligned. Unfortunately, 60 * FreeBSD doesn't guarantee that mbufs will be filled in starting 61 * at longword boundaries, so we have to do a buffer copy before 62 * transmission. 63 */ 64 65 #include <sys/param.h> 66 #include <sys/systm.h> 67 #include <sys/sockio.h> 68 #include <sys/mbuf.h> 69 #include <sys/malloc.h> 70 #include <sys/kernel.h> 71 #include <sys/socket.h> 72 73 #include <net/if.h> 74 #include <net/if_arp.h> 75 #include <net/ethernet.h> 76 #include <net/if_dl.h> 77 #include <net/if_media.h> 78 79 #include <net/bpf.h> 80 81 #include <vm/vm.h> /* for vtophys */ 82 #include <vm/pmap.h> /* for vtophys */ 83 #include <machine/clock.h> /* for DELAY */ 84 #include <machine/bus_pio.h> 85 #include <machine/bus_memio.h> 86 #include <machine/bus.h> 87 #include <machine/resource.h> 88 #include <sys/bus.h> 89 #include <sys/rman.h> 90 91 #include "../mii_layer/mii.h" 92 #include "../mii_layer/miivar.h" 93 94 #include <bus/pci/pcireg.h> 95 #include <bus/pci/pcivar.h> 96 97 #define VR_USEIOSPACE 98 99 #include "if_vrreg.h" 100 101 /* "controller miibus0" required. See GENERIC if you get errors here. */ 102 #include "miibus_if.h" 103 104 #undef VR_USESWSHIFT 105 106 /* 107 * Various supported device vendors/types and their names. 108 */ 109 static struct vr_type vr_devs[] = { 110 { VIA_VENDORID, VIA_DEVICEID_RHINE, 111 "VIA VT3043 Rhine I 10/100BaseTX" }, 112 { VIA_VENDORID, VIA_DEVICEID_RHINE_II, 113 "VIA VT86C100A Rhine II 10/100BaseTX" }, 114 { VIA_VENDORID, VIA_DEVICEID_RHINE_II_2, 115 "VIA VT6102 Rhine II 10/100BaseTX" }, 116 { VIA_VENDORID, VIA_DEVICEID_RHINE_III, 117 "VIA VT6105 Rhine III 10/100BaseTX" }, 118 { VIA_VENDORID, VIA_DEVICEID_RHINE_III_M, 119 "VIA VT6105M Rhine III 10/100BaseTX" }, 120 { DELTA_VENDORID, DELTA_DEVICEID_RHINE_II, 121 "Delta Electronics Rhine II 10/100BaseTX" }, 122 { ADDTRON_VENDORID, ADDTRON_DEVICEID_RHINE_II, 123 "Addtron Technology Rhine II 10/100BaseTX" }, 124 { 0, 0, NULL } 125 }; 126 127 static int vr_probe (device_t); 128 static int vr_attach (device_t); 129 static int vr_detach (device_t); 130 131 static int vr_newbuf (struct vr_softc *, 132 struct vr_chain_onefrag *, 133 struct mbuf *); 134 static int vr_encap (struct vr_softc *, struct vr_chain *, 135 struct mbuf * ); 136 137 static void vr_rxeof (struct vr_softc *); 138 static void vr_rxeoc (struct vr_softc *); 139 static void vr_txeof (struct vr_softc *); 140 static void vr_txeoc (struct vr_softc *); 141 static void vr_tick (void *); 142 static void vr_intr (void *); 143 static void vr_start (struct ifnet *); 144 static int vr_ioctl (struct ifnet *, u_long, caddr_t, 145 struct ucred *); 146 static void vr_init (void *); 147 static void vr_stop (struct vr_softc *); 148 static void vr_watchdog (struct ifnet *); 149 static void vr_shutdown (device_t); 150 static int vr_ifmedia_upd (struct ifnet *); 151 static void vr_ifmedia_sts (struct ifnet *, struct ifmediareq *); 152 153 #ifdef VR_USESWSHIFT 154 static void vr_mii_sync (struct vr_softc *); 155 static void vr_mii_send (struct vr_softc *, u_int32_t, int); 156 #endif 157 static int vr_mii_readreg (struct vr_softc *, struct vr_mii_frame *); 158 static int vr_mii_writereg (struct vr_softc *, struct vr_mii_frame *); 159 static int vr_miibus_readreg (device_t, int, int); 160 static int vr_miibus_writereg (device_t, int, int, int); 161 static void vr_miibus_statchg (device_t); 162 163 static void vr_setcfg (struct vr_softc *, int); 164 static u_int8_t vr_calchash (u_int8_t *); 165 static void vr_setmulti (struct vr_softc *); 166 static void vr_reset (struct vr_softc *); 167 static int vr_list_rx_init (struct vr_softc *); 168 static int vr_list_tx_init (struct vr_softc *); 169 170 #ifdef VR_USEIOSPACE 171 #define VR_RES SYS_RES_IOPORT 172 #define VR_RID VR_PCI_LOIO 173 #else 174 #define VR_RES SYS_RES_MEMORY 175 #define VR_RID VR_PCI_LOMEM 176 #endif 177 178 static device_method_t vr_methods[] = { 179 /* Device interface */ 180 DEVMETHOD(device_probe, vr_probe), 181 DEVMETHOD(device_attach, vr_attach), 182 DEVMETHOD(device_detach, vr_detach), 183 DEVMETHOD(device_shutdown, vr_shutdown), 184 185 /* bus interface */ 186 DEVMETHOD(bus_print_child, bus_generic_print_child), 187 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 188 189 /* MII interface */ 190 DEVMETHOD(miibus_readreg, vr_miibus_readreg), 191 DEVMETHOD(miibus_writereg, vr_miibus_writereg), 192 DEVMETHOD(miibus_statchg, vr_miibus_statchg), 193 194 { 0, 0 } 195 }; 196 197 static driver_t vr_driver = { 198 "vr", 199 vr_methods, 200 sizeof(struct vr_softc) 201 }; 202 203 static devclass_t vr_devclass; 204 205 DECLARE_DUMMY_MODULE(if_vr); 206 DRIVER_MODULE(if_vr, pci, vr_driver, vr_devclass, 0, 0); 207 DRIVER_MODULE(miibus, vr, miibus_driver, miibus_devclass, 0, 0); 208 209 #define VR_SETBIT(sc, reg, x) \ 210 CSR_WRITE_1(sc, reg, \ 211 CSR_READ_1(sc, reg) | x) 212 213 #define VR_CLRBIT(sc, reg, x) \ 214 CSR_WRITE_1(sc, reg, \ 215 CSR_READ_1(sc, reg) & ~x) 216 217 #define VR_SETBIT16(sc, reg, x) \ 218 CSR_WRITE_2(sc, reg, \ 219 CSR_READ_2(sc, reg) | x) 220 221 #define VR_CLRBIT16(sc, reg, x) \ 222 CSR_WRITE_2(sc, reg, \ 223 CSR_READ_2(sc, reg) & ~x) 224 225 #define VR_SETBIT32(sc, reg, x) \ 226 CSR_WRITE_4(sc, reg, \ 227 CSR_READ_4(sc, reg) | x) 228 229 #define VR_CLRBIT32(sc, reg, x) \ 230 CSR_WRITE_4(sc, reg, \ 231 CSR_READ_4(sc, reg) & ~x) 232 233 #define SIO_SET(x) \ 234 CSR_WRITE_1(sc, VR_MIICMD, \ 235 CSR_READ_1(sc, VR_MIICMD) | x) 236 237 #define SIO_CLR(x) \ 238 CSR_WRITE_1(sc, VR_MIICMD, \ 239 CSR_READ_1(sc, VR_MIICMD) & ~x) 240 241 #ifdef VR_USESWSHIFT 242 /* 243 * Sync the PHYs by setting data bit and strobing the clock 32 times. 244 */ 245 static void vr_mii_sync(sc) 246 struct vr_softc *sc; 247 { 248 int i; 249 250 SIO_SET(VR_MIICMD_DIR|VR_MIICMD_DATAIN); 251 252 for (i = 0; i < 32; i++) { 253 SIO_SET(VR_MIICMD_CLK); 254 DELAY(1); 255 SIO_CLR(VR_MIICMD_CLK); 256 DELAY(1); 257 } 258 259 return; 260 } 261 262 /* 263 * Clock a series of bits through the MII. 264 */ 265 static void vr_mii_send(sc, bits, cnt) 266 struct vr_softc *sc; 267 u_int32_t bits; 268 int cnt; 269 { 270 int i; 271 272 SIO_CLR(VR_MIICMD_CLK); 273 274 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 275 if (bits & i) { 276 SIO_SET(VR_MIICMD_DATAIN); 277 } else { 278 SIO_CLR(VR_MIICMD_DATAIN); 279 } 280 DELAY(1); 281 SIO_CLR(VR_MIICMD_CLK); 282 DELAY(1); 283 SIO_SET(VR_MIICMD_CLK); 284 } 285 } 286 #endif 287 288 /* 289 * Read an PHY register through the MII. 290 */ 291 static int vr_mii_readreg(sc, frame) 292 struct vr_softc *sc; 293 struct vr_mii_frame *frame; 294 295 #ifdef VR_USESWSHIFT 296 { 297 int i, ack, s; 298 299 s = splimp(); 300 301 /* 302 * Set up frame for RX. 303 */ 304 frame->mii_stdelim = VR_MII_STARTDELIM; 305 frame->mii_opcode = VR_MII_READOP; 306 frame->mii_turnaround = 0; 307 frame->mii_data = 0; 308 309 CSR_WRITE_1(sc, VR_MIICMD, 0); 310 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_DIRECTPGM); 311 312 /* 313 * Turn on data xmit. 314 */ 315 SIO_SET(VR_MIICMD_DIR); 316 317 vr_mii_sync(sc); 318 319 /* 320 * Send command/address info. 321 */ 322 vr_mii_send(sc, frame->mii_stdelim, 2); 323 vr_mii_send(sc, frame->mii_opcode, 2); 324 vr_mii_send(sc, frame->mii_phyaddr, 5); 325 vr_mii_send(sc, frame->mii_regaddr, 5); 326 327 /* Idle bit */ 328 SIO_CLR((VR_MIICMD_CLK|VR_MIICMD_DATAIN)); 329 DELAY(1); 330 SIO_SET(VR_MIICMD_CLK); 331 DELAY(1); 332 333 /* Turn off xmit. */ 334 SIO_CLR(VR_MIICMD_DIR); 335 336 /* Check for ack */ 337 SIO_CLR(VR_MIICMD_CLK); 338 DELAY(1); 339 ack = CSR_READ_4(sc, VR_MIICMD) & VR_MIICMD_DATAOUT; 340 SIO_SET(VR_MIICMD_CLK); 341 DELAY(1); 342 343 /* 344 * Now try reading data bits. If the ack failed, we still 345 * need to clock through 16 cycles to keep the PHY(s) in sync. 346 */ 347 if (ack) { 348 for(i = 0; i < 16; i++) { 349 SIO_CLR(VR_MIICMD_CLK); 350 DELAY(1); 351 SIO_SET(VR_MIICMD_CLK); 352 DELAY(1); 353 } 354 goto fail; 355 } 356 357 for (i = 0x8000; i; i >>= 1) { 358 SIO_CLR(VR_MIICMD_CLK); 359 DELAY(1); 360 if (!ack) { 361 if (CSR_READ_4(sc, VR_MIICMD) & VR_MIICMD_DATAOUT) 362 frame->mii_data |= i; 363 DELAY(1); 364 } 365 SIO_SET(VR_MIICMD_CLK); 366 DELAY(1); 367 } 368 369 fail: 370 371 SIO_CLR(VR_MIICMD_CLK); 372 DELAY(1); 373 SIO_SET(VR_MIICMD_CLK); 374 DELAY(1); 375 376 splx(s); 377 378 if (ack) 379 return(1); 380 return(0); 381 } 382 #else 383 { 384 int s, i; 385 386 s = splimp(); 387 388 /* Set the PHY-adress */ 389 CSR_WRITE_1(sc, VR_PHYADDR, (CSR_READ_1(sc, VR_PHYADDR)& 0xe0)| 390 frame->mii_phyaddr); 391 392 /* Set the register-adress */ 393 CSR_WRITE_1(sc, VR_MIIADDR, frame->mii_regaddr); 394 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_READ_ENB); 395 396 for (i = 0; i < 10000; i++) { 397 if ((CSR_READ_1(sc, VR_MIICMD) & VR_MIICMD_READ_ENB) == 0) 398 break; 399 DELAY(1); 400 } 401 402 frame->mii_data = CSR_READ_2(sc, VR_MIIDATA); 403 404 (void)splx(s); 405 406 return(0); 407 } 408 #endif 409 410 411 /* 412 * Write to a PHY register through the MII. 413 */ 414 static int vr_mii_writereg(sc, frame) 415 struct vr_softc *sc; 416 struct vr_mii_frame *frame; 417 418 #ifdef VR_USESWSHIFT 419 { 420 int s; 421 422 s = splimp(); 423 424 CSR_WRITE_1(sc, VR_MIICMD, 0); 425 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_DIRECTPGM); 426 427 /* 428 * Set up frame for TX. 429 */ 430 431 frame->mii_stdelim = VR_MII_STARTDELIM; 432 frame->mii_opcode = VR_MII_WRITEOP; 433 frame->mii_turnaround = VR_MII_TURNAROUND; 434 435 /* 436 * Turn on data output. 437 */ 438 SIO_SET(VR_MIICMD_DIR); 439 440 vr_mii_sync(sc); 441 442 vr_mii_send(sc, frame->mii_stdelim, 2); 443 vr_mii_send(sc, frame->mii_opcode, 2); 444 vr_mii_send(sc, frame->mii_phyaddr, 5); 445 vr_mii_send(sc, frame->mii_regaddr, 5); 446 vr_mii_send(sc, frame->mii_turnaround, 2); 447 vr_mii_send(sc, frame->mii_data, 16); 448 449 /* Idle bit. */ 450 SIO_SET(VR_MIICMD_CLK); 451 DELAY(1); 452 SIO_CLR(VR_MIICMD_CLK); 453 DELAY(1); 454 455 /* 456 * Turn off xmit. 457 */ 458 SIO_CLR(VR_MIICMD_DIR); 459 460 splx(s); 461 462 return(0); 463 } 464 #else 465 { 466 int s, i; 467 468 s = splimp(); 469 470 /* Set the PHY-adress */ 471 CSR_WRITE_1(sc, VR_PHYADDR, (CSR_READ_1(sc, VR_PHYADDR)& 0xe0)| 472 frame->mii_phyaddr); 473 474 /* Set the register-adress and data to write */ 475 CSR_WRITE_1(sc, VR_MIIADDR, frame->mii_regaddr); 476 CSR_WRITE_2(sc, VR_MIIDATA, frame->mii_data); 477 478 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_WRITE_ENB); 479 480 for (i = 0; i < 10000; i++) { 481 if ((CSR_READ_1(sc, VR_MIICMD) & VR_MIICMD_WRITE_ENB) == 0) 482 break; 483 DELAY(1); 484 } 485 486 (void)splx(s); 487 488 return(0); 489 } 490 #endif 491 492 static int vr_miibus_readreg(dev, phy, reg) 493 device_t dev; 494 int phy, reg; 495 { 496 struct vr_softc *sc; 497 struct vr_mii_frame frame; 498 499 sc = device_get_softc(dev); 500 501 switch (sc->vr_revid) { 502 case REV_ID_VT6102_APOLLO: 503 if (phy != 1) 504 return 0; 505 default: 506 break; 507 } 508 509 bzero((char *)&frame, sizeof(frame)); 510 511 frame.mii_phyaddr = phy; 512 frame.mii_regaddr = reg; 513 vr_mii_readreg(sc, &frame); 514 515 return(frame.mii_data); 516 } 517 518 static int vr_miibus_writereg(dev, phy, reg, data) 519 device_t dev; 520 u_int16_t phy, reg, data; 521 { 522 struct vr_softc *sc; 523 struct vr_mii_frame frame; 524 525 sc = device_get_softc(dev); 526 527 switch (sc->vr_revid) { 528 case REV_ID_VT6102_APOLLO: 529 if (phy != 1) 530 return 0; 531 default: 532 break; 533 } 534 535 bzero((char *)&frame, sizeof(frame)); 536 537 frame.mii_phyaddr = phy; 538 frame.mii_regaddr = reg; 539 frame.mii_data = data; 540 541 vr_mii_writereg(sc, &frame); 542 543 return(0); 544 } 545 546 static void vr_miibus_statchg(dev) 547 device_t dev; 548 { 549 struct vr_softc *sc; 550 struct mii_data *mii; 551 552 sc = device_get_softc(dev); 553 mii = device_get_softc(sc->vr_miibus); 554 vr_setcfg(sc, mii->mii_media_active); 555 556 return; 557 } 558 559 /* 560 * Calculate CRC of a multicast group address, return the lower 6 bits. 561 */ 562 static u_int8_t vr_calchash(addr) 563 u_int8_t *addr; 564 { 565 u_int32_t crc, carry; 566 int i, j; 567 u_int8_t c; 568 569 /* Compute CRC for the address value. */ 570 crc = 0xFFFFFFFF; /* initial value */ 571 572 for (i = 0; i < 6; i++) { 573 c = *(addr + i); 574 for (j = 0; j < 8; j++) { 575 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 576 crc <<= 1; 577 c >>= 1; 578 if (carry) 579 crc = (crc ^ 0x04c11db6) | carry; 580 } 581 } 582 583 /* return the filter bit position */ 584 return((crc >> 26) & 0x0000003F); 585 } 586 587 /* 588 * Program the 64-bit multicast hash filter. 589 */ 590 static void vr_setmulti(sc) 591 struct vr_softc *sc; 592 { 593 struct ifnet *ifp; 594 int h = 0; 595 u_int32_t hashes[2] = { 0, 0 }; 596 struct ifmultiaddr *ifma; 597 u_int8_t rxfilt; 598 int mcnt = 0; 599 600 ifp = &sc->arpcom.ac_if; 601 602 rxfilt = CSR_READ_1(sc, VR_RXCFG); 603 604 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 605 rxfilt |= VR_RXCFG_RX_MULTI; 606 CSR_WRITE_1(sc, VR_RXCFG, rxfilt); 607 CSR_WRITE_4(sc, VR_MAR0, 0xFFFFFFFF); 608 CSR_WRITE_4(sc, VR_MAR1, 0xFFFFFFFF); 609 return; 610 } 611 612 /* first, zot all the existing hash bits */ 613 CSR_WRITE_4(sc, VR_MAR0, 0); 614 CSR_WRITE_4(sc, VR_MAR1, 0); 615 616 /* now program new ones */ 617 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 618 ifma = ifma->ifma_link.le_next) { 619 if (ifma->ifma_addr->sa_family != AF_LINK) 620 continue; 621 h = vr_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 622 if (h < 32) 623 hashes[0] |= (1 << h); 624 else 625 hashes[1] |= (1 << (h - 32)); 626 mcnt++; 627 } 628 629 if (mcnt) 630 rxfilt |= VR_RXCFG_RX_MULTI; 631 else 632 rxfilt &= ~VR_RXCFG_RX_MULTI; 633 634 CSR_WRITE_4(sc, VR_MAR0, hashes[0]); 635 CSR_WRITE_4(sc, VR_MAR1, hashes[1]); 636 CSR_WRITE_1(sc, VR_RXCFG, rxfilt); 637 638 return; 639 } 640 641 /* 642 * In order to fiddle with the 643 * 'full-duplex' and '100Mbps' bits in the netconfig register, we 644 * first have to put the transmit and/or receive logic in the idle state. 645 */ 646 static void vr_setcfg(sc, media) 647 struct vr_softc *sc; 648 int media; 649 { 650 int restart = 0; 651 652 if (CSR_READ_2(sc, VR_COMMAND) & (VR_CMD_TX_ON|VR_CMD_RX_ON)) { 653 restart = 1; 654 VR_CLRBIT16(sc, VR_COMMAND, (VR_CMD_TX_ON|VR_CMD_RX_ON)); 655 } 656 657 if ((media & IFM_GMASK) == IFM_FDX) 658 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_FULLDUPLEX); 659 else 660 VR_CLRBIT16(sc, VR_COMMAND, VR_CMD_FULLDUPLEX); 661 662 if (restart) 663 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_ON|VR_CMD_RX_ON); 664 665 return; 666 } 667 668 static void vr_reset(sc) 669 struct vr_softc *sc; 670 { 671 int i; 672 673 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RESET); 674 675 for (i = 0; i < VR_TIMEOUT; i++) { 676 DELAY(10); 677 if (!(CSR_READ_2(sc, VR_COMMAND) & VR_CMD_RESET)) 678 break; 679 } 680 if (i == VR_TIMEOUT) { 681 if (sc->vr_revid < REV_ID_VT3065_A) 682 printf("vr%d: reset never completed!\n", sc->vr_unit); 683 else { 684 /* Use newer force reset command */ 685 printf("vr%d: Using force reset command.\n", sc->vr_unit); 686 VR_SETBIT(sc, VR_MISC_CR1, VR_MISCCR1_FORSRST); 687 } 688 } 689 690 /* Wait a little while for the chip to get its brains in order. */ 691 DELAY(1000); 692 693 return; 694 } 695 696 /* 697 * Probe for a VIA Rhine chip. Check the PCI vendor and device 698 * IDs against our list and return a device name if we find a match. 699 */ 700 static int vr_probe(dev) 701 device_t dev; 702 { 703 struct vr_type *t; 704 705 t = vr_devs; 706 707 while(t->vr_name != NULL) { 708 if ((pci_get_vendor(dev) == t->vr_vid) && 709 (pci_get_device(dev) == t->vr_did)) { 710 device_set_desc(dev, t->vr_name); 711 return(0); 712 } 713 t++; 714 } 715 716 return(ENXIO); 717 } 718 719 /* 720 * Attach the interface. Allocate softc structures, do ifmedia 721 * setup and ethernet/BPF attach. 722 */ 723 static int vr_attach(dev) 724 device_t dev; 725 { 726 int i, s; 727 u_char eaddr[ETHER_ADDR_LEN]; 728 u_int32_t command; 729 struct vr_softc *sc; 730 struct ifnet *ifp; 731 int unit, error = 0, rid; 732 733 s = splimp(); 734 735 sc = device_get_softc(dev); 736 unit = device_get_unit(dev); 737 bzero(sc, sizeof(struct vr_softc *)); 738 callout_init(&sc->vr_stat_timer); 739 740 /* 741 * Handle power management nonsense. 742 */ 743 744 command = pci_read_config(dev, VR_PCI_CAPID, 4) & 0x000000FF; 745 if (command == 0x01) { 746 747 command = pci_read_config(dev, VR_PCI_PWRMGMTCTRL, 4); 748 if (command & VR_PSTATE_MASK) { 749 u_int32_t iobase, membase, irq; 750 751 /* Save important PCI config data. */ 752 iobase = pci_read_config(dev, VR_PCI_LOIO, 4); 753 membase = pci_read_config(dev, VR_PCI_LOMEM, 4); 754 irq = pci_read_config(dev, VR_PCI_INTLINE, 4); 755 756 /* Reset the power state. */ 757 printf("vr%d: chip is in D%d power mode " 758 "-- setting to D0\n", unit, command & VR_PSTATE_MASK); 759 command &= 0xFFFFFFFC; 760 pci_write_config(dev, VR_PCI_PWRMGMTCTRL, command, 4); 761 762 /* Restore PCI config data. */ 763 pci_write_config(dev, VR_PCI_LOIO, iobase, 4); 764 pci_write_config(dev, VR_PCI_LOMEM, membase, 4); 765 pci_write_config(dev, VR_PCI_INTLINE, irq, 4); 766 } 767 } 768 769 /* 770 * Map control/status registers. 771 */ 772 command = pci_read_config(dev, PCIR_COMMAND, 4); 773 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 774 pci_write_config(dev, PCIR_COMMAND, command, 4); 775 command = pci_read_config(dev, PCIR_COMMAND, 4); 776 sc->vr_revid = pci_read_config(dev, VR_PCI_REVID, 4) & 0x000000FF; 777 778 #ifdef VR_USEIOSPACE 779 if (!(command & PCIM_CMD_PORTEN)) { 780 printf("vr%d: failed to enable I/O ports!\n", unit); 781 free(sc, M_DEVBUF); 782 goto fail; 783 } 784 #else 785 if (!(command & PCIM_CMD_MEMEN)) { 786 printf("vr%d: failed to enable memory mapping!\n", unit); 787 goto fail; 788 } 789 #endif 790 791 rid = VR_RID; 792 sc->vr_res = bus_alloc_resource(dev, VR_RES, &rid, 793 0, ~0, 1, RF_ACTIVE); 794 795 if (sc->vr_res == NULL) { 796 printf("vr%d: couldn't map ports/memory\n", unit); 797 error = ENXIO; 798 goto fail; 799 } 800 801 sc->vr_btag = rman_get_bustag(sc->vr_res); 802 sc->vr_bhandle = rman_get_bushandle(sc->vr_res); 803 804 /* Allocate interrupt */ 805 rid = 0; 806 sc->vr_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 807 RF_SHAREABLE | RF_ACTIVE); 808 809 if (sc->vr_irq == NULL) { 810 printf("vr%d: couldn't map interrupt\n", unit); 811 bus_release_resource(dev, VR_RES, VR_RID, sc->vr_res); 812 error = ENXIO; 813 goto fail; 814 } 815 816 error = bus_setup_intr(dev, sc->vr_irq, INTR_TYPE_NET, 817 vr_intr, sc, &sc->vr_intrhand); 818 819 if (error) { 820 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->vr_irq); 821 bus_release_resource(dev, VR_RES, VR_RID, sc->vr_res); 822 printf("vr%d: couldn't set up irq\n", unit); 823 goto fail; 824 } 825 826 /* 827 * Windows may put the chip in suspend mode when it 828 * shuts down. Be sure to kick it in the head to wake it 829 * up again. 830 */ 831 VR_CLRBIT(sc, VR_STICKHW, (VR_STICKHW_DS0|VR_STICKHW_DS1)); 832 833 /* Reset the adapter. */ 834 vr_reset(sc); 835 836 /* 837 * Turn on bit2 (MIION) in PCI configuration register 0x53 during 838 * initialization and disable AUTOPOLL. 839 */ 840 pci_write_config(dev, VR_PCI_MODE, 841 pci_read_config(dev, VR_PCI_MODE, 4) | (VR_MODE3_MIION << 24), 4); 842 VR_CLRBIT(sc, VR_MIICMD, VR_MIICMD_AUTOPOLL); 843 844 /* 845 * Get station address. The way the Rhine chips work, 846 * you're not allowed to directly access the EEPROM once 847 * they've been programmed a special way. Consequently, 848 * we need to read the node address from the PAR0 and PAR1 849 * registers. 850 */ 851 VR_SETBIT(sc, VR_EECSR, VR_EECSR_LOAD); 852 DELAY(200); 853 for (i = 0; i < ETHER_ADDR_LEN; i++) 854 eaddr[i] = CSR_READ_1(sc, VR_PAR0 + i); 855 856 sc->vr_unit = unit; 857 858 sc->vr_ldata = contigmalloc(sizeof(struct vr_list_data), M_DEVBUF, 859 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 860 861 if (sc->vr_ldata == NULL) { 862 printf("vr%d: no memory for list buffers!\n", unit); 863 bus_teardown_intr(dev, sc->vr_irq, sc->vr_intrhand); 864 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->vr_irq); 865 bus_release_resource(dev, VR_RES, VR_RID, sc->vr_res); 866 error = ENXIO; 867 goto fail; 868 } 869 870 bzero(sc->vr_ldata, sizeof(struct vr_list_data)); 871 872 ifp = &sc->arpcom.ac_if; 873 ifp->if_softc = sc; 874 if_initname(ifp, "vr", unit); 875 ifp->if_mtu = ETHERMTU; 876 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 877 ifp->if_ioctl = vr_ioctl; 878 ifp->if_start = vr_start; 879 ifp->if_watchdog = vr_watchdog; 880 ifp->if_init = vr_init; 881 ifp->if_baudrate = 10000000; 882 ifp->if_snd.ifq_maxlen = VR_TX_LIST_CNT - 1; 883 884 /* 885 * Do MII setup. 886 */ 887 if (mii_phy_probe(dev, &sc->vr_miibus, 888 vr_ifmedia_upd, vr_ifmedia_sts)) { 889 printf("vr%d: MII without any phy!\n", sc->vr_unit); 890 bus_teardown_intr(dev, sc->vr_irq, sc->vr_intrhand); 891 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->vr_irq); 892 bus_release_resource(dev, VR_RES, VR_RID, sc->vr_res); 893 contigfree(sc->vr_ldata, 894 sizeof(struct vr_list_data), M_DEVBUF); 895 error = ENXIO; 896 goto fail; 897 } 898 899 /* 900 * Call MI attach routine. 901 */ 902 ether_ifattach(ifp, eaddr); 903 904 fail: 905 splx(s); 906 return(error); 907 } 908 909 static int vr_detach(dev) 910 device_t dev; 911 { 912 struct vr_softc *sc; 913 struct ifnet *ifp; 914 int s; 915 916 s = splimp(); 917 918 sc = device_get_softc(dev); 919 ifp = &sc->arpcom.ac_if; 920 921 vr_stop(sc); 922 ether_ifdetach(ifp); 923 924 bus_generic_detach(dev); 925 device_delete_child(dev, sc->vr_miibus); 926 927 bus_teardown_intr(dev, sc->vr_irq, sc->vr_intrhand); 928 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->vr_irq); 929 bus_release_resource(dev, VR_RES, VR_RID, sc->vr_res); 930 931 contigfree(sc->vr_ldata, sizeof(struct vr_list_data), M_DEVBUF); 932 933 splx(s); 934 935 return(0); 936 } 937 938 /* 939 * Initialize the transmit descriptors. 940 */ 941 static int vr_list_tx_init(sc) 942 struct vr_softc *sc; 943 { 944 struct vr_chain_data *cd; 945 struct vr_list_data *ld; 946 int i; 947 948 cd = &sc->vr_cdata; 949 ld = sc->vr_ldata; 950 for (i = 0; i < VR_TX_LIST_CNT; i++) { 951 cd->vr_tx_chain[i].vr_ptr = &ld->vr_tx_list[i]; 952 if (i == (VR_TX_LIST_CNT - 1)) 953 cd->vr_tx_chain[i].vr_nextdesc = 954 &cd->vr_tx_chain[0]; 955 else 956 cd->vr_tx_chain[i].vr_nextdesc = 957 &cd->vr_tx_chain[i + 1]; 958 } 959 960 cd->vr_tx_free = &cd->vr_tx_chain[0]; 961 cd->vr_tx_tail = cd->vr_tx_head = NULL; 962 963 return(0); 964 } 965 966 967 /* 968 * Initialize the RX descriptors and allocate mbufs for them. Note that 969 * we arrange the descriptors in a closed ring, so that the last descriptor 970 * points back to the first. 971 */ 972 static int vr_list_rx_init(sc) 973 struct vr_softc *sc; 974 { 975 struct vr_chain_data *cd; 976 struct vr_list_data *ld; 977 int i; 978 979 cd = &sc->vr_cdata; 980 ld = sc->vr_ldata; 981 982 for (i = 0; i < VR_RX_LIST_CNT; i++) { 983 cd->vr_rx_chain[i].vr_ptr = 984 (struct vr_desc *)&ld->vr_rx_list[i]; 985 if (vr_newbuf(sc, &cd->vr_rx_chain[i], NULL) == ENOBUFS) 986 return(ENOBUFS); 987 if (i == (VR_RX_LIST_CNT - 1)) { 988 cd->vr_rx_chain[i].vr_nextdesc = 989 &cd->vr_rx_chain[0]; 990 ld->vr_rx_list[i].vr_next = 991 vtophys(&ld->vr_rx_list[0]); 992 } else { 993 cd->vr_rx_chain[i].vr_nextdesc = 994 &cd->vr_rx_chain[i + 1]; 995 ld->vr_rx_list[i].vr_next = 996 vtophys(&ld->vr_rx_list[i + 1]); 997 } 998 } 999 1000 cd->vr_rx_head = &cd->vr_rx_chain[0]; 1001 1002 return(0); 1003 } 1004 1005 /* 1006 * Initialize an RX descriptor and attach an MBUF cluster. 1007 * Note: the length fields are only 11 bits wide, which means the 1008 * largest size we can specify is 2047. This is important because 1009 * MCLBYTES is 2048, so we have to subtract one otherwise we'll 1010 * overflow the field and make a mess. 1011 */ 1012 static int vr_newbuf(sc, c, m) 1013 struct vr_softc *sc; 1014 struct vr_chain_onefrag *c; 1015 struct mbuf *m; 1016 { 1017 struct mbuf *m_new = NULL; 1018 1019 if (m == NULL) { 1020 MGETHDR(m_new, MB_DONTWAIT, MT_DATA); 1021 if (m_new == NULL) 1022 return(ENOBUFS); 1023 1024 MCLGET(m_new, MB_DONTWAIT); 1025 if (!(m_new->m_flags & M_EXT)) { 1026 m_freem(m_new); 1027 return(ENOBUFS); 1028 } 1029 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1030 } else { 1031 m_new = m; 1032 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1033 m_new->m_data = m_new->m_ext.ext_buf; 1034 } 1035 1036 m_adj(m_new, sizeof(u_int64_t)); 1037 1038 c->vr_mbuf = m_new; 1039 c->vr_ptr->vr_status = VR_RXSTAT; 1040 c->vr_ptr->vr_data = vtophys(mtod(m_new, caddr_t)); 1041 c->vr_ptr->vr_ctl = VR_RXCTL | VR_RXLEN; 1042 1043 return(0); 1044 } 1045 1046 /* 1047 * A frame has been uploaded: pass the resulting mbuf chain up to 1048 * the higher level protocols. 1049 */ 1050 static void vr_rxeof(sc) 1051 struct vr_softc *sc; 1052 { 1053 struct mbuf *m; 1054 struct ifnet *ifp; 1055 struct vr_chain_onefrag *cur_rx; 1056 int total_len = 0; 1057 u_int32_t rxstat; 1058 1059 ifp = &sc->arpcom.ac_if; 1060 1061 while(!((rxstat = sc->vr_cdata.vr_rx_head->vr_ptr->vr_status) & 1062 VR_RXSTAT_OWN)) { 1063 struct mbuf *m0 = NULL; 1064 1065 cur_rx = sc->vr_cdata.vr_rx_head; 1066 sc->vr_cdata.vr_rx_head = cur_rx->vr_nextdesc; 1067 m = cur_rx->vr_mbuf; 1068 1069 /* 1070 * If an error occurs, update stats, clear the 1071 * status word and leave the mbuf cluster in place: 1072 * it should simply get re-used next time this descriptor 1073 * comes up in the ring. 1074 */ 1075 if (rxstat & VR_RXSTAT_RXERR) { 1076 ifp->if_ierrors++; 1077 printf("vr%d: rx error (%02x):", 1078 sc->vr_unit, rxstat & 0x000000ff); 1079 if (rxstat & VR_RXSTAT_CRCERR) 1080 printf(" crc error"); 1081 if (rxstat & VR_RXSTAT_FRAMEALIGNERR) 1082 printf(" frame alignment error\n"); 1083 if (rxstat & VR_RXSTAT_FIFOOFLOW) 1084 printf(" FIFO overflow"); 1085 if (rxstat & VR_RXSTAT_GIANT) 1086 printf(" received giant packet"); 1087 if (rxstat & VR_RXSTAT_RUNT) 1088 printf(" received runt packet"); 1089 if (rxstat & VR_RXSTAT_BUSERR) 1090 printf(" system bus error"); 1091 if (rxstat & VR_RXSTAT_BUFFERR) 1092 printf("rx buffer error"); 1093 printf("\n"); 1094 vr_newbuf(sc, cur_rx, m); 1095 continue; 1096 } 1097 1098 /* No errors; receive the packet. */ 1099 total_len = VR_RXBYTES(cur_rx->vr_ptr->vr_status); 1100 1101 /* 1102 * XXX The VIA Rhine chip includes the CRC with every 1103 * received frame, and there's no way to turn this 1104 * behavior off (at least, I can't find anything in 1105 * the manual that explains how to do it) so we have 1106 * to trim off the CRC manually. 1107 */ 1108 total_len -= ETHER_CRC_LEN; 1109 1110 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 1111 total_len + ETHER_ALIGN, 0, ifp, NULL); 1112 vr_newbuf(sc, cur_rx, m); 1113 if (m0 == NULL) { 1114 ifp->if_ierrors++; 1115 continue; 1116 } 1117 m_adj(m0, ETHER_ALIGN); 1118 m = m0; 1119 1120 ifp->if_ipackets++; 1121 (*ifp->if_input)(ifp, m); 1122 } 1123 1124 return; 1125 } 1126 1127 void vr_rxeoc(sc) 1128 struct vr_softc *sc; 1129 { 1130 struct ifnet *ifp; 1131 int i; 1132 1133 ifp = &sc->arpcom.ac_if; 1134 1135 ifp->if_ierrors++; 1136 1137 VR_CLRBIT16(sc, VR_COMMAND, VR_CMD_RX_ON); 1138 DELAY(10000); 1139 1140 for (i = 0x400; 1141 i && (CSR_READ_2(sc, VR_COMMAND) & VR_CMD_RX_ON); 1142 i--) 1143 ; /* Wait for receiver to stop */ 1144 1145 if (!i) { 1146 printf("vr%d: rx shutdown error!\n", sc->vr_unit); 1147 sc->vr_flags |= VR_F_RESTART; 1148 return; 1149 } 1150 1151 vr_rxeof(sc); 1152 1153 CSR_WRITE_4(sc, VR_RXADDR, vtophys(sc->vr_cdata.vr_rx_head->vr_ptr)); 1154 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RX_ON); 1155 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RX_GO); 1156 1157 return; 1158 } 1159 1160 /* 1161 * A frame was downloaded to the chip. It's safe for us to clean up 1162 * the list buffers. 1163 */ 1164 1165 static void vr_txeof(sc) 1166 struct vr_softc *sc; 1167 { 1168 struct vr_chain *cur_tx; 1169 struct ifnet *ifp; 1170 1171 ifp = &sc->arpcom.ac_if; 1172 1173 /* Reset the timeout timer; if_txeoc will clear it. */ 1174 ifp->if_timer = 5; 1175 1176 /* Sanity check. */ 1177 if (sc->vr_cdata.vr_tx_head == NULL) 1178 return; 1179 1180 /* 1181 * Go through our tx list and free mbufs for those 1182 * frames that have been transmitted. 1183 */ 1184 while(sc->vr_cdata.vr_tx_head->vr_mbuf != NULL) { 1185 u_int32_t txstat; 1186 int i; 1187 1188 cur_tx = sc->vr_cdata.vr_tx_head; 1189 txstat = cur_tx->vr_ptr->vr_status; 1190 1191 if ((txstat & VR_TXSTAT_ABRT) || 1192 (txstat & VR_TXSTAT_UDF)) { 1193 for (i = 0x400; 1194 i && (CSR_READ_2(sc, VR_COMMAND) & VR_CMD_TX_ON); 1195 i--) 1196 ; /* Wait for chip to shutdown */ 1197 if (!i) { 1198 printf("vr%d: tx shutdown timeout\n", sc->vr_unit); 1199 sc->vr_flags |= VR_F_RESTART; 1200 break; 1201 } 1202 VR_TXOWN(cur_tx) = VR_TXSTAT_OWN; 1203 CSR_WRITE_4(sc, VR_TXADDR, vtophys(cur_tx->vr_ptr)); 1204 break; 1205 } 1206 1207 if (txstat & VR_TXSTAT_OWN) 1208 break; 1209 1210 if (txstat & VR_TXSTAT_ERRSUM) { 1211 ifp->if_oerrors++; 1212 if (txstat & VR_TXSTAT_DEFER) 1213 ifp->if_collisions++; 1214 if (txstat & VR_TXSTAT_LATECOLL) 1215 ifp->if_collisions++; 1216 } 1217 1218 ifp->if_collisions +=(txstat & VR_TXSTAT_COLLCNT) >> 3; 1219 1220 ifp->if_opackets++; 1221 if (cur_tx->vr_mbuf != NULL) { 1222 m_freem(cur_tx->vr_mbuf); 1223 cur_tx->vr_mbuf = NULL; 1224 } 1225 1226 if (sc->vr_cdata.vr_tx_head == sc->vr_cdata.vr_tx_tail) { 1227 sc->vr_cdata.vr_tx_head = NULL; 1228 sc->vr_cdata.vr_tx_tail = NULL; 1229 break; 1230 } 1231 1232 sc->vr_cdata.vr_tx_head = cur_tx->vr_nextdesc; 1233 } 1234 1235 return; 1236 } 1237 1238 /* 1239 * TX 'end of channel' interrupt handler. 1240 */ 1241 static void vr_txeoc(sc) 1242 struct vr_softc *sc; 1243 { 1244 struct ifnet *ifp; 1245 1246 ifp = &sc->arpcom.ac_if; 1247 1248 if (sc->vr_cdata.vr_tx_head == NULL) { 1249 ifp->if_flags &= ~IFF_OACTIVE; 1250 sc->vr_cdata.vr_tx_tail = NULL; 1251 ifp->if_timer = 0; 1252 } 1253 1254 return; 1255 } 1256 1257 static void vr_tick(xsc) 1258 void *xsc; 1259 { 1260 struct vr_softc *sc; 1261 struct mii_data *mii; 1262 int s; 1263 1264 s = splimp(); 1265 1266 sc = xsc; 1267 if (sc->vr_flags & VR_F_RESTART) { 1268 printf("vr%d: restarting\n", sc->vr_unit); 1269 vr_stop(sc); 1270 vr_reset(sc); 1271 vr_init(sc); 1272 sc->vr_flags &= ~VR_F_RESTART; 1273 } 1274 1275 mii = device_get_softc(sc->vr_miibus); 1276 mii_tick(mii); 1277 1278 callout_reset(&sc->vr_stat_timer, hz, vr_tick, sc); 1279 1280 splx(s); 1281 1282 return; 1283 } 1284 1285 static void vr_intr(arg) 1286 void *arg; 1287 { 1288 struct vr_softc *sc; 1289 struct ifnet *ifp; 1290 u_int16_t status; 1291 1292 sc = arg; 1293 ifp = &sc->arpcom.ac_if; 1294 1295 /* Supress unwanted interrupts. */ 1296 if (!(ifp->if_flags & IFF_UP)) { 1297 vr_stop(sc); 1298 return; 1299 } 1300 1301 /* Disable interrupts. */ 1302 if ((ifp->if_flags & IFF_POLLING) == 0) 1303 CSR_WRITE_2(sc, VR_IMR, 0x0000); 1304 1305 for (;;) { 1306 1307 status = CSR_READ_2(sc, VR_ISR); 1308 if (status) 1309 CSR_WRITE_2(sc, VR_ISR, status); 1310 1311 if ((status & VR_INTRS) == 0) 1312 break; 1313 1314 if (status & VR_ISR_RX_OK) 1315 vr_rxeof(sc); 1316 1317 if (status & VR_ISR_RX_DROPPED) { 1318 printf("vr%d: rx packet lost\n", sc->vr_unit); 1319 ifp->if_ierrors++; 1320 } 1321 1322 if ((status & VR_ISR_RX_ERR) || (status & VR_ISR_RX_NOBUF) || 1323 (status & VR_ISR_RX_NOBUF) || (status & VR_ISR_RX_OFLOW)) { 1324 printf("vr%d: receive error (%04x)", 1325 sc->vr_unit, status); 1326 if (status & VR_ISR_RX_NOBUF) 1327 printf(" no buffers"); 1328 if (status & VR_ISR_RX_OFLOW) 1329 printf(" overflow"); 1330 if (status & VR_ISR_RX_DROPPED) 1331 printf(" packet lost"); 1332 printf("\n"); 1333 vr_rxeoc(sc); 1334 } 1335 1336 if ((status & VR_ISR_BUSERR) || (status & VR_ISR_TX_UNDERRUN)) { 1337 vr_reset(sc); 1338 vr_init(sc); 1339 break; 1340 } 1341 1342 if ((status & VR_ISR_TX_OK) || (status & VR_ISR_TX_ABRT) || 1343 (status & VR_ISR_TX_ABRT2) || (status & VR_ISR_UDFI)) { 1344 vr_txeof(sc); 1345 if ((status & VR_ISR_UDFI) || 1346 (status & VR_ISR_TX_ABRT2) || 1347 (status & VR_ISR_TX_ABRT)) { 1348 ifp->if_oerrors++; 1349 if (sc->vr_cdata.vr_tx_head != NULL) { 1350 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_ON); 1351 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_GO); 1352 } 1353 } else 1354 vr_txeoc(sc); 1355 } 1356 1357 } 1358 1359 /* Re-enable interrupts. */ 1360 if ((ifp->if_flags & IFF_POLLING) == 0) 1361 CSR_WRITE_2(sc, VR_IMR, VR_INTRS); 1362 1363 if (ifp->if_snd.ifq_head != NULL) { 1364 vr_start(ifp); 1365 } 1366 1367 return; 1368 } 1369 1370 /* 1371 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1372 * pointers to the fragment pointers. 1373 */ 1374 static int vr_encap(sc, c, m_head) 1375 struct vr_softc *sc; 1376 struct vr_chain *c; 1377 struct mbuf *m_head; 1378 { 1379 int frag = 0; 1380 struct vr_desc *f = NULL; 1381 int total_len; 1382 struct mbuf *m; 1383 1384 m = m_head; 1385 total_len = 0; 1386 1387 /* 1388 * The VIA Rhine wants packet buffers to be longword 1389 * aligned, but very often our mbufs aren't. Rather than 1390 * waste time trying to decide when to copy and when not 1391 * to copy, just do it all the time. 1392 */ 1393 if (m != NULL) { 1394 struct mbuf *m_new = NULL; 1395 1396 MGETHDR(m_new, MB_DONTWAIT, MT_DATA); 1397 if (m_new == NULL) { 1398 printf("vr%d: no memory for tx list\n", sc->vr_unit); 1399 return(1); 1400 } 1401 if (m_head->m_pkthdr.len > MHLEN) { 1402 MCLGET(m_new, MB_DONTWAIT); 1403 if (!(m_new->m_flags & M_EXT)) { 1404 m_freem(m_new); 1405 printf("vr%d: no memory for tx list\n", 1406 sc->vr_unit); 1407 return(1); 1408 } 1409 } 1410 m_copydata(m_head, 0, m_head->m_pkthdr.len, 1411 mtod(m_new, caddr_t)); 1412 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 1413 m_freem(m_head); 1414 m_head = m_new; 1415 /* 1416 * The Rhine chip doesn't auto-pad, so we have to make 1417 * sure to pad short frames out to the minimum frame length 1418 * ourselves. 1419 */ 1420 if (m_head->m_len < VR_MIN_FRAMELEN) { 1421 m_new->m_pkthdr.len += VR_MIN_FRAMELEN - m_new->m_len; 1422 m_new->m_len = m_new->m_pkthdr.len; 1423 } 1424 f = c->vr_ptr; 1425 f->vr_data = vtophys(mtod(m_new, caddr_t)); 1426 f->vr_ctl = total_len = m_new->m_len; 1427 f->vr_ctl |= VR_TXCTL_TLINK|VR_TXCTL_FIRSTFRAG; 1428 f->vr_status = 0; 1429 frag = 1; 1430 } 1431 1432 c->vr_mbuf = m_head; 1433 c->vr_ptr->vr_ctl |= VR_TXCTL_LASTFRAG|VR_TXCTL_FINT; 1434 c->vr_ptr->vr_next = vtophys(c->vr_nextdesc->vr_ptr); 1435 1436 return(0); 1437 } 1438 1439 /* 1440 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1441 * to the mbuf data regions directly in the transmit lists. We also save a 1442 * copy of the pointers since the transmit list fragment pointers are 1443 * physical addresses. 1444 */ 1445 1446 static void vr_start(ifp) 1447 struct ifnet *ifp; 1448 { 1449 struct vr_softc *sc; 1450 struct mbuf *m_head = NULL; 1451 struct vr_chain *cur_tx = NULL, *start_tx; 1452 1453 sc = ifp->if_softc; 1454 1455 if (ifp->if_flags & IFF_OACTIVE) 1456 return; 1457 1458 /* 1459 * Check for an available queue slot. If there are none, 1460 * punt. 1461 */ 1462 if (sc->vr_cdata.vr_tx_free->vr_mbuf != NULL) { 1463 ifp->if_flags |= IFF_OACTIVE; 1464 return; 1465 } 1466 1467 start_tx = sc->vr_cdata.vr_tx_free; 1468 1469 while(sc->vr_cdata.vr_tx_free->vr_mbuf == NULL) { 1470 IF_DEQUEUE(&ifp->if_snd, m_head); 1471 if (m_head == NULL) 1472 break; 1473 1474 /* Pick a descriptor off the free list. */ 1475 cur_tx = sc->vr_cdata.vr_tx_free; 1476 sc->vr_cdata.vr_tx_free = cur_tx->vr_nextdesc; 1477 1478 /* Pack the data into the descriptor. */ 1479 if (vr_encap(sc, cur_tx, m_head)) { 1480 IF_PREPEND(&ifp->if_snd, m_head); 1481 ifp->if_flags |= IFF_OACTIVE; 1482 cur_tx = NULL; 1483 break; 1484 } 1485 1486 if (cur_tx != start_tx) 1487 VR_TXOWN(cur_tx) = VR_TXSTAT_OWN; 1488 1489 /* 1490 * If there's a BPF listener, bounce a copy of this frame 1491 * to him. 1492 */ 1493 if (ifp->if_bpf) 1494 bpf_mtap(ifp, cur_tx->vr_mbuf); 1495 1496 VR_TXOWN(cur_tx) = VR_TXSTAT_OWN; 1497 VR_SETBIT16(sc, VR_COMMAND, /*VR_CMD_TX_ON|*/VR_CMD_TX_GO); 1498 } 1499 1500 /* 1501 * If there are no frames queued, bail. 1502 */ 1503 if (cur_tx == NULL) 1504 return; 1505 1506 sc->vr_cdata.vr_tx_tail = cur_tx; 1507 1508 if (sc->vr_cdata.vr_tx_head == NULL) 1509 sc->vr_cdata.vr_tx_head = start_tx; 1510 1511 /* 1512 * Set a timeout in case the chip goes out to lunch. 1513 */ 1514 ifp->if_timer = 5; 1515 1516 return; 1517 } 1518 1519 static void vr_init(xsc) 1520 void *xsc; 1521 { 1522 struct vr_softc *sc = xsc; 1523 struct ifnet *ifp = &sc->arpcom.ac_if; 1524 struct mii_data *mii; 1525 int s, i; 1526 1527 s = splimp(); 1528 1529 mii = device_get_softc(sc->vr_miibus); 1530 1531 /* 1532 * Cancel pending I/O and free all RX/TX buffers. 1533 */ 1534 vr_stop(sc); 1535 vr_reset(sc); 1536 1537 /* 1538 * Set our station address. 1539 */ 1540 for (i = 0; i < ETHER_ADDR_LEN; i++) 1541 CSR_WRITE_1(sc, VR_PAR0 + i, sc->arpcom.ac_enaddr[i]); 1542 1543 /* Set DMA size */ 1544 VR_CLRBIT(sc, VR_BCR0, VR_BCR0_DMA_LENGTH); 1545 VR_SETBIT(sc, VR_BCR0, VR_BCR0_DMA_STORENFWD); 1546 1547 /* 1548 * BCR0 and BCR1 can override the RXCFG and TXCFG registers, 1549 * so we must set both. 1550 */ 1551 VR_CLRBIT(sc, VR_BCR0, VR_BCR0_RX_THRESH); 1552 VR_SETBIT(sc, VR_BCR0, VR_BCR0_RXTHRESH128BYTES); 1553 1554 VR_CLRBIT(sc, VR_BCR1, VR_BCR1_TX_THRESH); 1555 VR_SETBIT(sc, VR_BCR1, VR_BCR1_TXTHRESHSTORENFWD); 1556 1557 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_THRESH); 1558 VR_SETBIT(sc, VR_RXCFG, VR_RXTHRESH_128BYTES); 1559 1560 VR_CLRBIT(sc, VR_TXCFG, VR_TXCFG_TX_THRESH); 1561 VR_SETBIT(sc, VR_TXCFG, VR_TXTHRESH_STORENFWD); 1562 1563 /* Init circular RX list. */ 1564 if (vr_list_rx_init(sc) == ENOBUFS) { 1565 printf("vr%d: initialization failed: no " 1566 "memory for rx buffers\n", sc->vr_unit); 1567 vr_stop(sc); 1568 (void)splx(s); 1569 return; 1570 } 1571 1572 /* 1573 * Init tx descriptors. 1574 */ 1575 vr_list_tx_init(sc); 1576 1577 /* If we want promiscuous mode, set the allframes bit. */ 1578 if (ifp->if_flags & IFF_PROMISC) 1579 VR_SETBIT(sc, VR_RXCFG, VR_RXCFG_RX_PROMISC); 1580 else 1581 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_PROMISC); 1582 1583 /* Set capture broadcast bit to capture broadcast frames. */ 1584 if (ifp->if_flags & IFF_BROADCAST) 1585 VR_SETBIT(sc, VR_RXCFG, VR_RXCFG_RX_BROAD); 1586 else 1587 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_BROAD); 1588 1589 /* 1590 * Program the multicast filter, if necessary. 1591 */ 1592 vr_setmulti(sc); 1593 1594 /* 1595 * Load the address of the RX list. 1596 */ 1597 CSR_WRITE_4(sc, VR_RXADDR, vtophys(sc->vr_cdata.vr_rx_head->vr_ptr)); 1598 1599 /* Enable receiver and transmitter. */ 1600 CSR_WRITE_2(sc, VR_COMMAND, VR_CMD_TX_NOPOLL|VR_CMD_START| 1601 VR_CMD_TX_ON|VR_CMD_RX_ON| 1602 VR_CMD_RX_GO); 1603 1604 CSR_WRITE_4(sc, VR_TXADDR, vtophys(&sc->vr_ldata->vr_tx_list[0])); 1605 1606 /* 1607 * Enable interrupts, unless we are polling. 1608 */ 1609 CSR_WRITE_2(sc, VR_ISR, 0xFFFF); 1610 if ((ifp->if_flags & IFF_POLLING) == 0) 1611 CSR_WRITE_2(sc, VR_IMR, VR_INTRS); 1612 1613 mii_mediachg(mii); 1614 1615 ifp->if_flags |= IFF_RUNNING; 1616 ifp->if_flags &= ~IFF_OACTIVE; 1617 1618 (void)splx(s); 1619 1620 callout_reset(&sc->vr_stat_timer, hz, vr_tick, sc); 1621 1622 return; 1623 } 1624 1625 /* 1626 * Set media options. 1627 */ 1628 static int vr_ifmedia_upd(ifp) 1629 struct ifnet *ifp; 1630 { 1631 struct vr_softc *sc; 1632 1633 sc = ifp->if_softc; 1634 1635 if (ifp->if_flags & IFF_UP) 1636 vr_init(sc); 1637 1638 return(0); 1639 } 1640 1641 /* 1642 * Report current media status. 1643 */ 1644 static void vr_ifmedia_sts(ifp, ifmr) 1645 struct ifnet *ifp; 1646 struct ifmediareq *ifmr; 1647 { 1648 struct vr_softc *sc; 1649 struct mii_data *mii; 1650 1651 sc = ifp->if_softc; 1652 mii = device_get_softc(sc->vr_miibus); 1653 mii_pollstat(mii); 1654 ifmr->ifm_active = mii->mii_media_active; 1655 ifmr->ifm_status = mii->mii_media_status; 1656 1657 return; 1658 } 1659 1660 static int vr_ioctl(ifp, command, data, cr) 1661 struct ifnet *ifp; 1662 u_long command; 1663 caddr_t data; 1664 struct ucred *cr; 1665 { 1666 struct vr_softc *sc = ifp->if_softc; 1667 struct ifreq *ifr = (struct ifreq *) data; 1668 struct mii_data *mii; 1669 int s, error = 0; 1670 1671 s = splimp(); 1672 1673 switch(command) { 1674 case SIOCSIFADDR: 1675 case SIOCGIFADDR: 1676 case SIOCSIFMTU: 1677 error = ether_ioctl(ifp, command, data); 1678 break; 1679 case SIOCSIFFLAGS: 1680 if (ifp->if_flags & IFF_UP) { 1681 vr_init(sc); 1682 } else { 1683 if (ifp->if_flags & IFF_RUNNING) 1684 vr_stop(sc); 1685 } 1686 error = 0; 1687 break; 1688 case SIOCADDMULTI: 1689 case SIOCDELMULTI: 1690 vr_setmulti(sc); 1691 error = 0; 1692 break; 1693 case SIOCGIFMEDIA: 1694 case SIOCSIFMEDIA: 1695 mii = device_get_softc(sc->vr_miibus); 1696 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1697 break; 1698 default: 1699 error = EINVAL; 1700 break; 1701 } 1702 1703 (void)splx(s); 1704 1705 return(error); 1706 } 1707 1708 #ifdef DEVICE_POLLING 1709 1710 static 1711 void 1712 vr_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1713 { 1714 struct vr_softc *sc = ifp->if_softc; 1715 1716 if (cmd == POLL_DEREGISTER) { 1717 CSR_WRITE_2(sc, VR_IMR, VR_INTRS); 1718 } else { 1719 vr_intr(sc); 1720 } 1721 } 1722 1723 #endif 1724 1725 static void vr_watchdog(ifp) 1726 struct ifnet *ifp; 1727 { 1728 struct vr_softc *sc; 1729 1730 sc = ifp->if_softc; 1731 1732 ifp->if_oerrors++; 1733 printf("vr%d: watchdog timeout\n", sc->vr_unit); 1734 1735 #ifdef DEVICE_POLLING 1736 if (++sc->vr_wdogerrors == 1 && (ifp->if_flags & IFF_POLLING) == 0) { 1737 printf("vr%d ints don't seem to be working, " 1738 "emergency switch to polling\n", sc->vr_unit); 1739 emergency_poll_enable("if_vr"); 1740 if (ether_poll_register(vr_poll, ifp)) { 1741 CSR_WRITE_2(sc, VR_IMR, 0x0000); 1742 } 1743 } else 1744 #endif 1745 { 1746 vr_stop(sc); 1747 vr_reset(sc); 1748 vr_init(sc); 1749 } 1750 1751 if (ifp->if_snd.ifq_head != NULL) 1752 vr_start(ifp); 1753 } 1754 1755 /* 1756 * Stop the adapter and free any mbufs allocated to the 1757 * RX and TX lists. 1758 */ 1759 static void vr_stop(sc) 1760 struct vr_softc *sc; 1761 { 1762 int i; 1763 struct ifnet *ifp; 1764 1765 ifp = &sc->arpcom.ac_if; 1766 ifp->if_timer = 0; 1767 1768 callout_stop(&sc->vr_stat_timer); 1769 1770 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_STOP); 1771 VR_CLRBIT16(sc, VR_COMMAND, (VR_CMD_RX_ON|VR_CMD_TX_ON)); 1772 CSR_WRITE_2(sc, VR_IMR, 0x0000); 1773 CSR_WRITE_4(sc, VR_TXADDR, 0x00000000); 1774 CSR_WRITE_4(sc, VR_RXADDR, 0x00000000); 1775 1776 /* 1777 * Free data in the RX lists. 1778 */ 1779 for (i = 0; i < VR_RX_LIST_CNT; i++) { 1780 if (sc->vr_cdata.vr_rx_chain[i].vr_mbuf != NULL) { 1781 m_freem(sc->vr_cdata.vr_rx_chain[i].vr_mbuf); 1782 sc->vr_cdata.vr_rx_chain[i].vr_mbuf = NULL; 1783 } 1784 } 1785 bzero((char *)&sc->vr_ldata->vr_rx_list, 1786 sizeof(sc->vr_ldata->vr_rx_list)); 1787 1788 /* 1789 * Free the TX list buffers. 1790 */ 1791 for (i = 0; i < VR_TX_LIST_CNT; i++) { 1792 if (sc->vr_cdata.vr_tx_chain[i].vr_mbuf != NULL) { 1793 m_freem(sc->vr_cdata.vr_tx_chain[i].vr_mbuf); 1794 sc->vr_cdata.vr_tx_chain[i].vr_mbuf = NULL; 1795 } 1796 } 1797 1798 bzero((char *)&sc->vr_ldata->vr_tx_list, 1799 sizeof(sc->vr_ldata->vr_tx_list)); 1800 1801 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1802 1803 return; 1804 } 1805 1806 /* 1807 * Stop all chip I/O so that the kernel's probe routines don't 1808 * get confused by errant DMAs when rebooting. 1809 */ 1810 static void vr_shutdown(dev) 1811 device_t dev; 1812 { 1813 struct vr_softc *sc; 1814 1815 sc = device_get_softc(dev); 1816 1817 vr_stop(sc); 1818 1819 return; 1820 } 1821