1 /* 2 * Copyright (c) 1997, 1998 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: src/sys/pci/if_vr.c,v 1.26.2.13 2003/02/06 04:46:20 silby Exp $ 33 * $DragonFly: src/sys/dev/netif/vr/if_vr.c,v 1.13 2004/07/02 17:42:20 joerg Exp $ 34 * 35 * $FreeBSD: src/sys/pci/if_vr.c,v 1.26.2.13 2003/02/06 04:46:20 silby Exp $ 36 */ 37 38 /* 39 * VIA Rhine fast ethernet PCI NIC driver 40 * 41 * Supports various network adapters based on the VIA Rhine 42 * and Rhine II PCI controllers, including the D-Link DFE530TX. 43 * Datasheets are available at http://www.via.com.tw. 44 * 45 * Written by Bill Paul <wpaul@ctr.columbia.edu> 46 * Electrical Engineering Department 47 * Columbia University, New York City 48 */ 49 50 /* 51 * The VIA Rhine controllers are similar in some respects to the 52 * the DEC tulip chips, except less complicated. The controller 53 * uses an MII bus and an external physical layer interface. The 54 * receiver has a one entry perfect filter and a 64-bit hash table 55 * multicast filter. Transmit and receive descriptors are similar 56 * to the tulip. 57 * 58 * The Rhine has a serious flaw in its transmit DMA mechanism: 59 * transmit buffers must be longword aligned. Unfortunately, 60 * FreeBSD doesn't guarantee that mbufs will be filled in starting 61 * at longword boundaries, so we have to do a buffer copy before 62 * transmission. 63 */ 64 65 #include <sys/param.h> 66 #include <sys/systm.h> 67 #include <sys/sockio.h> 68 #include <sys/mbuf.h> 69 #include <sys/malloc.h> 70 #include <sys/kernel.h> 71 #include <sys/socket.h> 72 73 #include <net/if.h> 74 #include <net/if_arp.h> 75 #include <net/ethernet.h> 76 #include <net/if_dl.h> 77 #include <net/if_media.h> 78 79 #include <net/bpf.h> 80 81 #include <vm/vm.h> /* for vtophys */ 82 #include <vm/pmap.h> /* for vtophys */ 83 #include <machine/clock.h> /* for DELAY */ 84 #include <machine/bus_pio.h> 85 #include <machine/bus_memio.h> 86 #include <machine/bus.h> 87 #include <machine/resource.h> 88 #include <sys/bus.h> 89 #include <sys/rman.h> 90 91 #include "../mii_layer/mii.h" 92 #include "../mii_layer/miivar.h" 93 94 #include <bus/pci/pcireg.h> 95 #include <bus/pci/pcivar.h> 96 97 #define VR_USEIOSPACE 98 99 #include "if_vrreg.h" 100 101 /* "controller miibus0" required. See GENERIC if you get errors here. */ 102 #include "miibus_if.h" 103 104 #undef VR_USESWSHIFT 105 106 /* 107 * Various supported device vendors/types and their names. 108 */ 109 static struct vr_type vr_devs[] = { 110 { VIA_VENDORID, VIA_DEVICEID_RHINE, 111 "VIA VT3043 Rhine I 10/100BaseTX" }, 112 { VIA_VENDORID, VIA_DEVICEID_RHINE_II, 113 "VIA VT86C100A Rhine II 10/100BaseTX" }, 114 { VIA_VENDORID, VIA_DEVICEID_RHINE_II_2, 115 "VIA VT6102 Rhine II 10/100BaseTX" }, 116 { VIA_VENDORID, VIA_DEVICEID_RHINE_III, 117 "VIA VT6105 Rhine III 10/100BaseTX" }, 118 { VIA_VENDORID, VIA_DEVICEID_RHINE_III_M, 119 "VIA VT6105M Rhine III 10/100BaseTX" }, 120 { DELTA_VENDORID, DELTA_DEVICEID_RHINE_II, 121 "Delta Electronics Rhine II 10/100BaseTX" }, 122 { ADDTRON_VENDORID, ADDTRON_DEVICEID_RHINE_II, 123 "Addtron Technology Rhine II 10/100BaseTX" }, 124 { 0, 0, NULL } 125 }; 126 127 static int vr_probe (device_t); 128 static int vr_attach (device_t); 129 static int vr_detach (device_t); 130 131 static int vr_newbuf (struct vr_softc *, 132 struct vr_chain_onefrag *, 133 struct mbuf *); 134 static int vr_encap (struct vr_softc *, struct vr_chain *, 135 struct mbuf * ); 136 137 static void vr_rxeof (struct vr_softc *); 138 static void vr_rxeoc (struct vr_softc *); 139 static void vr_txeof (struct vr_softc *); 140 static void vr_txeoc (struct vr_softc *); 141 static void vr_tick (void *); 142 static void vr_intr (void *); 143 static void vr_start (struct ifnet *); 144 static int vr_ioctl (struct ifnet *, u_long, caddr_t, 145 struct ucred *); 146 static void vr_init (void *); 147 static void vr_stop (struct vr_softc *); 148 static void vr_watchdog (struct ifnet *); 149 static void vr_shutdown (device_t); 150 static int vr_ifmedia_upd (struct ifnet *); 151 static void vr_ifmedia_sts (struct ifnet *, struct ifmediareq *); 152 153 #ifdef VR_USESWSHIFT 154 static void vr_mii_sync (struct vr_softc *); 155 static void vr_mii_send (struct vr_softc *, u_int32_t, int); 156 #endif 157 static int vr_mii_readreg (struct vr_softc *, struct vr_mii_frame *); 158 static int vr_mii_writereg (struct vr_softc *, struct vr_mii_frame *); 159 static int vr_miibus_readreg (device_t, int, int); 160 static int vr_miibus_writereg (device_t, int, int, int); 161 static void vr_miibus_statchg (device_t); 162 163 static void vr_setcfg (struct vr_softc *, int); 164 static u_int8_t vr_calchash (u_int8_t *); 165 static void vr_setmulti (struct vr_softc *); 166 static void vr_reset (struct vr_softc *); 167 static int vr_list_rx_init (struct vr_softc *); 168 static int vr_list_tx_init (struct vr_softc *); 169 170 #ifdef VR_USEIOSPACE 171 #define VR_RES SYS_RES_IOPORT 172 #define VR_RID VR_PCI_LOIO 173 #else 174 #define VR_RES SYS_RES_MEMORY 175 #define VR_RID VR_PCI_LOMEM 176 #endif 177 178 static device_method_t vr_methods[] = { 179 /* Device interface */ 180 DEVMETHOD(device_probe, vr_probe), 181 DEVMETHOD(device_attach, vr_attach), 182 DEVMETHOD(device_detach, vr_detach), 183 DEVMETHOD(device_shutdown, vr_shutdown), 184 185 /* bus interface */ 186 DEVMETHOD(bus_print_child, bus_generic_print_child), 187 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 188 189 /* MII interface */ 190 DEVMETHOD(miibus_readreg, vr_miibus_readreg), 191 DEVMETHOD(miibus_writereg, vr_miibus_writereg), 192 DEVMETHOD(miibus_statchg, vr_miibus_statchg), 193 194 { 0, 0 } 195 }; 196 197 static driver_t vr_driver = { 198 "vr", 199 vr_methods, 200 sizeof(struct vr_softc) 201 }; 202 203 static devclass_t vr_devclass; 204 205 DECLARE_DUMMY_MODULE(if_vr); 206 DRIVER_MODULE(if_vr, pci, vr_driver, vr_devclass, 0, 0); 207 DRIVER_MODULE(miibus, vr, miibus_driver, miibus_devclass, 0, 0); 208 209 #define VR_SETBIT(sc, reg, x) \ 210 CSR_WRITE_1(sc, reg, \ 211 CSR_READ_1(sc, reg) | x) 212 213 #define VR_CLRBIT(sc, reg, x) \ 214 CSR_WRITE_1(sc, reg, \ 215 CSR_READ_1(sc, reg) & ~x) 216 217 #define VR_SETBIT16(sc, reg, x) \ 218 CSR_WRITE_2(sc, reg, \ 219 CSR_READ_2(sc, reg) | x) 220 221 #define VR_CLRBIT16(sc, reg, x) \ 222 CSR_WRITE_2(sc, reg, \ 223 CSR_READ_2(sc, reg) & ~x) 224 225 #define VR_SETBIT32(sc, reg, x) \ 226 CSR_WRITE_4(sc, reg, \ 227 CSR_READ_4(sc, reg) | x) 228 229 #define VR_CLRBIT32(sc, reg, x) \ 230 CSR_WRITE_4(sc, reg, \ 231 CSR_READ_4(sc, reg) & ~x) 232 233 #define SIO_SET(x) \ 234 CSR_WRITE_1(sc, VR_MIICMD, \ 235 CSR_READ_1(sc, VR_MIICMD) | x) 236 237 #define SIO_CLR(x) \ 238 CSR_WRITE_1(sc, VR_MIICMD, \ 239 CSR_READ_1(sc, VR_MIICMD) & ~x) 240 241 #ifdef VR_USESWSHIFT 242 /* 243 * Sync the PHYs by setting data bit and strobing the clock 32 times. 244 */ 245 static void vr_mii_sync(sc) 246 struct vr_softc *sc; 247 { 248 int i; 249 250 SIO_SET(VR_MIICMD_DIR|VR_MIICMD_DATAIN); 251 252 for (i = 0; i < 32; i++) { 253 SIO_SET(VR_MIICMD_CLK); 254 DELAY(1); 255 SIO_CLR(VR_MIICMD_CLK); 256 DELAY(1); 257 } 258 259 return; 260 } 261 262 /* 263 * Clock a series of bits through the MII. 264 */ 265 static void vr_mii_send(sc, bits, cnt) 266 struct vr_softc *sc; 267 u_int32_t bits; 268 int cnt; 269 { 270 int i; 271 272 SIO_CLR(VR_MIICMD_CLK); 273 274 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 275 if (bits & i) { 276 SIO_SET(VR_MIICMD_DATAIN); 277 } else { 278 SIO_CLR(VR_MIICMD_DATAIN); 279 } 280 DELAY(1); 281 SIO_CLR(VR_MIICMD_CLK); 282 DELAY(1); 283 SIO_SET(VR_MIICMD_CLK); 284 } 285 } 286 #endif 287 288 /* 289 * Read an PHY register through the MII. 290 */ 291 static int vr_mii_readreg(sc, frame) 292 struct vr_softc *sc; 293 struct vr_mii_frame *frame; 294 295 #ifdef VR_USESWSHIFT 296 { 297 int i, ack, s; 298 299 s = splimp(); 300 301 /* 302 * Set up frame for RX. 303 */ 304 frame->mii_stdelim = VR_MII_STARTDELIM; 305 frame->mii_opcode = VR_MII_READOP; 306 frame->mii_turnaround = 0; 307 frame->mii_data = 0; 308 309 CSR_WRITE_1(sc, VR_MIICMD, 0); 310 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_DIRECTPGM); 311 312 /* 313 * Turn on data xmit. 314 */ 315 SIO_SET(VR_MIICMD_DIR); 316 317 vr_mii_sync(sc); 318 319 /* 320 * Send command/address info. 321 */ 322 vr_mii_send(sc, frame->mii_stdelim, 2); 323 vr_mii_send(sc, frame->mii_opcode, 2); 324 vr_mii_send(sc, frame->mii_phyaddr, 5); 325 vr_mii_send(sc, frame->mii_regaddr, 5); 326 327 /* Idle bit */ 328 SIO_CLR((VR_MIICMD_CLK|VR_MIICMD_DATAIN)); 329 DELAY(1); 330 SIO_SET(VR_MIICMD_CLK); 331 DELAY(1); 332 333 /* Turn off xmit. */ 334 SIO_CLR(VR_MIICMD_DIR); 335 336 /* Check for ack */ 337 SIO_CLR(VR_MIICMD_CLK); 338 DELAY(1); 339 ack = CSR_READ_4(sc, VR_MIICMD) & VR_MIICMD_DATAOUT; 340 SIO_SET(VR_MIICMD_CLK); 341 DELAY(1); 342 343 /* 344 * Now try reading data bits. If the ack failed, we still 345 * need to clock through 16 cycles to keep the PHY(s) in sync. 346 */ 347 if (ack) { 348 for(i = 0; i < 16; i++) { 349 SIO_CLR(VR_MIICMD_CLK); 350 DELAY(1); 351 SIO_SET(VR_MIICMD_CLK); 352 DELAY(1); 353 } 354 goto fail; 355 } 356 357 for (i = 0x8000; i; i >>= 1) { 358 SIO_CLR(VR_MIICMD_CLK); 359 DELAY(1); 360 if (!ack) { 361 if (CSR_READ_4(sc, VR_MIICMD) & VR_MIICMD_DATAOUT) 362 frame->mii_data |= i; 363 DELAY(1); 364 } 365 SIO_SET(VR_MIICMD_CLK); 366 DELAY(1); 367 } 368 369 fail: 370 371 SIO_CLR(VR_MIICMD_CLK); 372 DELAY(1); 373 SIO_SET(VR_MIICMD_CLK); 374 DELAY(1); 375 376 splx(s); 377 378 if (ack) 379 return(1); 380 return(0); 381 } 382 #else 383 { 384 int s, i; 385 386 s = splimp(); 387 388 /* Set the PHY-adress */ 389 CSR_WRITE_1(sc, VR_PHYADDR, (CSR_READ_1(sc, VR_PHYADDR)& 0xe0)| 390 frame->mii_phyaddr); 391 392 /* Set the register-adress */ 393 CSR_WRITE_1(sc, VR_MIIADDR, frame->mii_regaddr); 394 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_READ_ENB); 395 396 for (i = 0; i < 10000; i++) { 397 if ((CSR_READ_1(sc, VR_MIICMD) & VR_MIICMD_READ_ENB) == 0) 398 break; 399 DELAY(1); 400 } 401 402 frame->mii_data = CSR_READ_2(sc, VR_MIIDATA); 403 404 (void)splx(s); 405 406 return(0); 407 } 408 #endif 409 410 411 /* 412 * Write to a PHY register through the MII. 413 */ 414 static int vr_mii_writereg(sc, frame) 415 struct vr_softc *sc; 416 struct vr_mii_frame *frame; 417 418 #ifdef VR_USESWSHIFT 419 { 420 int s; 421 422 s = splimp(); 423 424 CSR_WRITE_1(sc, VR_MIICMD, 0); 425 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_DIRECTPGM); 426 427 /* 428 * Set up frame for TX. 429 */ 430 431 frame->mii_stdelim = VR_MII_STARTDELIM; 432 frame->mii_opcode = VR_MII_WRITEOP; 433 frame->mii_turnaround = VR_MII_TURNAROUND; 434 435 /* 436 * Turn on data output. 437 */ 438 SIO_SET(VR_MIICMD_DIR); 439 440 vr_mii_sync(sc); 441 442 vr_mii_send(sc, frame->mii_stdelim, 2); 443 vr_mii_send(sc, frame->mii_opcode, 2); 444 vr_mii_send(sc, frame->mii_phyaddr, 5); 445 vr_mii_send(sc, frame->mii_regaddr, 5); 446 vr_mii_send(sc, frame->mii_turnaround, 2); 447 vr_mii_send(sc, frame->mii_data, 16); 448 449 /* Idle bit. */ 450 SIO_SET(VR_MIICMD_CLK); 451 DELAY(1); 452 SIO_CLR(VR_MIICMD_CLK); 453 DELAY(1); 454 455 /* 456 * Turn off xmit. 457 */ 458 SIO_CLR(VR_MIICMD_DIR); 459 460 splx(s); 461 462 return(0); 463 } 464 #else 465 { 466 int s, i; 467 468 s = splimp(); 469 470 /* Set the PHY-adress */ 471 CSR_WRITE_1(sc, VR_PHYADDR, (CSR_READ_1(sc, VR_PHYADDR)& 0xe0)| 472 frame->mii_phyaddr); 473 474 /* Set the register-adress and data to write */ 475 CSR_WRITE_1(sc, VR_MIIADDR, frame->mii_regaddr); 476 CSR_WRITE_2(sc, VR_MIIDATA, frame->mii_data); 477 478 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_WRITE_ENB); 479 480 for (i = 0; i < 10000; i++) { 481 if ((CSR_READ_1(sc, VR_MIICMD) & VR_MIICMD_WRITE_ENB) == 0) 482 break; 483 DELAY(1); 484 } 485 486 (void)splx(s); 487 488 return(0); 489 } 490 #endif 491 492 static int vr_miibus_readreg(dev, phy, reg) 493 device_t dev; 494 int phy, reg; 495 { 496 struct vr_softc *sc; 497 struct vr_mii_frame frame; 498 499 sc = device_get_softc(dev); 500 501 switch (sc->vr_revid) { 502 case REV_ID_VT6102_APOLLO: 503 if (phy != 1) 504 return 0; 505 default: 506 break; 507 } 508 509 bzero((char *)&frame, sizeof(frame)); 510 511 frame.mii_phyaddr = phy; 512 frame.mii_regaddr = reg; 513 vr_mii_readreg(sc, &frame); 514 515 return(frame.mii_data); 516 } 517 518 static int vr_miibus_writereg(dev, phy, reg, data) 519 device_t dev; 520 u_int16_t phy, reg, data; 521 { 522 struct vr_softc *sc; 523 struct vr_mii_frame frame; 524 525 sc = device_get_softc(dev); 526 527 switch (sc->vr_revid) { 528 case REV_ID_VT6102_APOLLO: 529 if (phy != 1) 530 return 0; 531 default: 532 break; 533 } 534 535 bzero((char *)&frame, sizeof(frame)); 536 537 frame.mii_phyaddr = phy; 538 frame.mii_regaddr = reg; 539 frame.mii_data = data; 540 541 vr_mii_writereg(sc, &frame); 542 543 return(0); 544 } 545 546 static void vr_miibus_statchg(dev) 547 device_t dev; 548 { 549 struct vr_softc *sc; 550 struct mii_data *mii; 551 552 sc = device_get_softc(dev); 553 mii = device_get_softc(sc->vr_miibus); 554 vr_setcfg(sc, mii->mii_media_active); 555 556 return; 557 } 558 559 /* 560 * Calculate CRC of a multicast group address, return the lower 6 bits. 561 */ 562 static u_int8_t vr_calchash(addr) 563 u_int8_t *addr; 564 { 565 u_int32_t crc, carry; 566 int i, j; 567 u_int8_t c; 568 569 /* Compute CRC for the address value. */ 570 crc = 0xFFFFFFFF; /* initial value */ 571 572 for (i = 0; i < 6; i++) { 573 c = *(addr + i); 574 for (j = 0; j < 8; j++) { 575 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 576 crc <<= 1; 577 c >>= 1; 578 if (carry) 579 crc = (crc ^ 0x04c11db6) | carry; 580 } 581 } 582 583 /* return the filter bit position */ 584 return((crc >> 26) & 0x0000003F); 585 } 586 587 /* 588 * Program the 64-bit multicast hash filter. 589 */ 590 static void vr_setmulti(sc) 591 struct vr_softc *sc; 592 { 593 struct ifnet *ifp; 594 int h = 0; 595 u_int32_t hashes[2] = { 0, 0 }; 596 struct ifmultiaddr *ifma; 597 u_int8_t rxfilt; 598 int mcnt = 0; 599 600 ifp = &sc->arpcom.ac_if; 601 602 rxfilt = CSR_READ_1(sc, VR_RXCFG); 603 604 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 605 rxfilt |= VR_RXCFG_RX_MULTI; 606 CSR_WRITE_1(sc, VR_RXCFG, rxfilt); 607 CSR_WRITE_4(sc, VR_MAR0, 0xFFFFFFFF); 608 CSR_WRITE_4(sc, VR_MAR1, 0xFFFFFFFF); 609 return; 610 } 611 612 /* first, zot all the existing hash bits */ 613 CSR_WRITE_4(sc, VR_MAR0, 0); 614 CSR_WRITE_4(sc, VR_MAR1, 0); 615 616 /* now program new ones */ 617 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 618 ifma = ifma->ifma_link.le_next) { 619 if (ifma->ifma_addr->sa_family != AF_LINK) 620 continue; 621 h = vr_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 622 if (h < 32) 623 hashes[0] |= (1 << h); 624 else 625 hashes[1] |= (1 << (h - 32)); 626 mcnt++; 627 } 628 629 if (mcnt) 630 rxfilt |= VR_RXCFG_RX_MULTI; 631 else 632 rxfilt &= ~VR_RXCFG_RX_MULTI; 633 634 CSR_WRITE_4(sc, VR_MAR0, hashes[0]); 635 CSR_WRITE_4(sc, VR_MAR1, hashes[1]); 636 CSR_WRITE_1(sc, VR_RXCFG, rxfilt); 637 638 return; 639 } 640 641 /* 642 * In order to fiddle with the 643 * 'full-duplex' and '100Mbps' bits in the netconfig register, we 644 * first have to put the transmit and/or receive logic in the idle state. 645 */ 646 static void vr_setcfg(sc, media) 647 struct vr_softc *sc; 648 int media; 649 { 650 int restart = 0; 651 652 if (CSR_READ_2(sc, VR_COMMAND) & (VR_CMD_TX_ON|VR_CMD_RX_ON)) { 653 restart = 1; 654 VR_CLRBIT16(sc, VR_COMMAND, (VR_CMD_TX_ON|VR_CMD_RX_ON)); 655 } 656 657 if ((media & IFM_GMASK) == IFM_FDX) 658 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_FULLDUPLEX); 659 else 660 VR_CLRBIT16(sc, VR_COMMAND, VR_CMD_FULLDUPLEX); 661 662 if (restart) 663 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_ON|VR_CMD_RX_ON); 664 665 return; 666 } 667 668 static void vr_reset(sc) 669 struct vr_softc *sc; 670 { 671 int i; 672 673 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RESET); 674 675 for (i = 0; i < VR_TIMEOUT; i++) { 676 DELAY(10); 677 if (!(CSR_READ_2(sc, VR_COMMAND) & VR_CMD_RESET)) 678 break; 679 } 680 if (i == VR_TIMEOUT) { 681 if (sc->vr_revid < REV_ID_VT3065_A) 682 printf("vr%d: reset never completed!\n", sc->vr_unit); 683 else { 684 /* Use newer force reset command */ 685 printf("vr%d: Using force reset command.\n", sc->vr_unit); 686 VR_SETBIT(sc, VR_MISC_CR1, VR_MISCCR1_FORSRST); 687 } 688 } 689 690 /* Wait a little while for the chip to get its brains in order. */ 691 DELAY(1000); 692 693 return; 694 } 695 696 /* 697 * Probe for a VIA Rhine chip. Check the PCI vendor and device 698 * IDs against our list and return a device name if we find a match. 699 */ 700 static int vr_probe(dev) 701 device_t dev; 702 { 703 struct vr_type *t; 704 705 t = vr_devs; 706 707 while(t->vr_name != NULL) { 708 if ((pci_get_vendor(dev) == t->vr_vid) && 709 (pci_get_device(dev) == t->vr_did)) { 710 device_set_desc(dev, t->vr_name); 711 return(0); 712 } 713 t++; 714 } 715 716 return(ENXIO); 717 } 718 719 /* 720 * Attach the interface. Allocate softc structures, do ifmedia 721 * setup and ethernet/BPF attach. 722 */ 723 static int vr_attach(dev) 724 device_t dev; 725 { 726 int i, s; 727 u_char eaddr[ETHER_ADDR_LEN]; 728 u_int32_t command; 729 struct vr_softc *sc; 730 struct ifnet *ifp; 731 int unit, error = 0, rid; 732 733 s = splimp(); 734 735 sc = device_get_softc(dev); 736 unit = device_get_unit(dev); 737 bzero(sc, sizeof(struct vr_softc *)); 738 739 /* 740 * Handle power management nonsense. 741 */ 742 743 command = pci_read_config(dev, VR_PCI_CAPID, 4) & 0x000000FF; 744 if (command == 0x01) { 745 746 command = pci_read_config(dev, VR_PCI_PWRMGMTCTRL, 4); 747 if (command & VR_PSTATE_MASK) { 748 u_int32_t iobase, membase, irq; 749 750 /* Save important PCI config data. */ 751 iobase = pci_read_config(dev, VR_PCI_LOIO, 4); 752 membase = pci_read_config(dev, VR_PCI_LOMEM, 4); 753 irq = pci_read_config(dev, VR_PCI_INTLINE, 4); 754 755 /* Reset the power state. */ 756 printf("vr%d: chip is in D%d power mode " 757 "-- setting to D0\n", unit, command & VR_PSTATE_MASK); 758 command &= 0xFFFFFFFC; 759 pci_write_config(dev, VR_PCI_PWRMGMTCTRL, command, 4); 760 761 /* Restore PCI config data. */ 762 pci_write_config(dev, VR_PCI_LOIO, iobase, 4); 763 pci_write_config(dev, VR_PCI_LOMEM, membase, 4); 764 pci_write_config(dev, VR_PCI_INTLINE, irq, 4); 765 } 766 } 767 768 /* 769 * Map control/status registers. 770 */ 771 command = pci_read_config(dev, PCIR_COMMAND, 4); 772 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 773 pci_write_config(dev, PCIR_COMMAND, command, 4); 774 command = pci_read_config(dev, PCIR_COMMAND, 4); 775 sc->vr_revid = pci_read_config(dev, VR_PCI_REVID, 4) & 0x000000FF; 776 777 #ifdef VR_USEIOSPACE 778 if (!(command & PCIM_CMD_PORTEN)) { 779 printf("vr%d: failed to enable I/O ports!\n", unit); 780 free(sc, M_DEVBUF); 781 goto fail; 782 } 783 #else 784 if (!(command & PCIM_CMD_MEMEN)) { 785 printf("vr%d: failed to enable memory mapping!\n", unit); 786 goto fail; 787 } 788 #endif 789 790 rid = VR_RID; 791 sc->vr_res = bus_alloc_resource(dev, VR_RES, &rid, 792 0, ~0, 1, RF_ACTIVE); 793 794 if (sc->vr_res == NULL) { 795 printf("vr%d: couldn't map ports/memory\n", unit); 796 error = ENXIO; 797 goto fail; 798 } 799 800 sc->vr_btag = rman_get_bustag(sc->vr_res); 801 sc->vr_bhandle = rman_get_bushandle(sc->vr_res); 802 803 /* Allocate interrupt */ 804 rid = 0; 805 sc->vr_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 806 RF_SHAREABLE | RF_ACTIVE); 807 808 if (sc->vr_irq == NULL) { 809 printf("vr%d: couldn't map interrupt\n", unit); 810 bus_release_resource(dev, VR_RES, VR_RID, sc->vr_res); 811 error = ENXIO; 812 goto fail; 813 } 814 815 error = bus_setup_intr(dev, sc->vr_irq, INTR_TYPE_NET, 816 vr_intr, sc, &sc->vr_intrhand); 817 818 if (error) { 819 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->vr_irq); 820 bus_release_resource(dev, VR_RES, VR_RID, sc->vr_res); 821 printf("vr%d: couldn't set up irq\n", unit); 822 goto fail; 823 } 824 825 /* 826 * Windows may put the chip in suspend mode when it 827 * shuts down. Be sure to kick it in the head to wake it 828 * up again. 829 */ 830 VR_CLRBIT(sc, VR_STICKHW, (VR_STICKHW_DS0|VR_STICKHW_DS1)); 831 832 /* Reset the adapter. */ 833 vr_reset(sc); 834 835 /* 836 * Turn on bit2 (MIION) in PCI configuration register 0x53 during 837 * initialization and disable AUTOPOLL. 838 */ 839 pci_write_config(dev, VR_PCI_MODE, 840 pci_read_config(dev, VR_PCI_MODE, 4) | (VR_MODE3_MIION << 24), 4); 841 VR_CLRBIT(sc, VR_MIICMD, VR_MIICMD_AUTOPOLL); 842 843 /* 844 * Get station address. The way the Rhine chips work, 845 * you're not allowed to directly access the EEPROM once 846 * they've been programmed a special way. Consequently, 847 * we need to read the node address from the PAR0 and PAR1 848 * registers. 849 */ 850 VR_SETBIT(sc, VR_EECSR, VR_EECSR_LOAD); 851 DELAY(200); 852 for (i = 0; i < ETHER_ADDR_LEN; i++) 853 eaddr[i] = CSR_READ_1(sc, VR_PAR0 + i); 854 855 sc->vr_unit = unit; 856 857 sc->vr_ldata = contigmalloc(sizeof(struct vr_list_data), M_DEVBUF, 858 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 859 860 if (sc->vr_ldata == NULL) { 861 printf("vr%d: no memory for list buffers!\n", unit); 862 bus_teardown_intr(dev, sc->vr_irq, sc->vr_intrhand); 863 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->vr_irq); 864 bus_release_resource(dev, VR_RES, VR_RID, sc->vr_res); 865 error = ENXIO; 866 goto fail; 867 } 868 869 bzero(sc->vr_ldata, sizeof(struct vr_list_data)); 870 871 ifp = &sc->arpcom.ac_if; 872 ifp->if_softc = sc; 873 if_initname(ifp, "vr", unit); 874 ifp->if_mtu = ETHERMTU; 875 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 876 ifp->if_ioctl = vr_ioctl; 877 ifp->if_output = ether_output; 878 ifp->if_start = vr_start; 879 ifp->if_watchdog = vr_watchdog; 880 ifp->if_init = vr_init; 881 ifp->if_baudrate = 10000000; 882 ifp->if_snd.ifq_maxlen = VR_TX_LIST_CNT - 1; 883 884 /* 885 * Do MII setup. 886 */ 887 if (mii_phy_probe(dev, &sc->vr_miibus, 888 vr_ifmedia_upd, vr_ifmedia_sts)) { 889 printf("vr%d: MII without any phy!\n", sc->vr_unit); 890 bus_teardown_intr(dev, sc->vr_irq, sc->vr_intrhand); 891 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->vr_irq); 892 bus_release_resource(dev, VR_RES, VR_RID, sc->vr_res); 893 contigfree(sc->vr_ldata, 894 sizeof(struct vr_list_data), M_DEVBUF); 895 error = ENXIO; 896 goto fail; 897 } 898 899 callout_handle_init(&sc->vr_stat_ch); 900 901 /* 902 * Call MI attach routine. 903 */ 904 ether_ifattach(ifp, eaddr); 905 906 fail: 907 splx(s); 908 return(error); 909 } 910 911 static int vr_detach(dev) 912 device_t dev; 913 { 914 struct vr_softc *sc; 915 struct ifnet *ifp; 916 int s; 917 918 s = splimp(); 919 920 sc = device_get_softc(dev); 921 ifp = &sc->arpcom.ac_if; 922 923 vr_stop(sc); 924 ether_ifdetach(ifp); 925 926 bus_generic_detach(dev); 927 device_delete_child(dev, sc->vr_miibus); 928 929 bus_teardown_intr(dev, sc->vr_irq, sc->vr_intrhand); 930 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->vr_irq); 931 bus_release_resource(dev, VR_RES, VR_RID, sc->vr_res); 932 933 contigfree(sc->vr_ldata, sizeof(struct vr_list_data), M_DEVBUF); 934 935 splx(s); 936 937 return(0); 938 } 939 940 /* 941 * Initialize the transmit descriptors. 942 */ 943 static int vr_list_tx_init(sc) 944 struct vr_softc *sc; 945 { 946 struct vr_chain_data *cd; 947 struct vr_list_data *ld; 948 int i; 949 950 cd = &sc->vr_cdata; 951 ld = sc->vr_ldata; 952 for (i = 0; i < VR_TX_LIST_CNT; i++) { 953 cd->vr_tx_chain[i].vr_ptr = &ld->vr_tx_list[i]; 954 if (i == (VR_TX_LIST_CNT - 1)) 955 cd->vr_tx_chain[i].vr_nextdesc = 956 &cd->vr_tx_chain[0]; 957 else 958 cd->vr_tx_chain[i].vr_nextdesc = 959 &cd->vr_tx_chain[i + 1]; 960 } 961 962 cd->vr_tx_free = &cd->vr_tx_chain[0]; 963 cd->vr_tx_tail = cd->vr_tx_head = NULL; 964 965 return(0); 966 } 967 968 969 /* 970 * Initialize the RX descriptors and allocate mbufs for them. Note that 971 * we arrange the descriptors in a closed ring, so that the last descriptor 972 * points back to the first. 973 */ 974 static int vr_list_rx_init(sc) 975 struct vr_softc *sc; 976 { 977 struct vr_chain_data *cd; 978 struct vr_list_data *ld; 979 int i; 980 981 cd = &sc->vr_cdata; 982 ld = sc->vr_ldata; 983 984 for (i = 0; i < VR_RX_LIST_CNT; i++) { 985 cd->vr_rx_chain[i].vr_ptr = 986 (struct vr_desc *)&ld->vr_rx_list[i]; 987 if (vr_newbuf(sc, &cd->vr_rx_chain[i], NULL) == ENOBUFS) 988 return(ENOBUFS); 989 if (i == (VR_RX_LIST_CNT - 1)) { 990 cd->vr_rx_chain[i].vr_nextdesc = 991 &cd->vr_rx_chain[0]; 992 ld->vr_rx_list[i].vr_next = 993 vtophys(&ld->vr_rx_list[0]); 994 } else { 995 cd->vr_rx_chain[i].vr_nextdesc = 996 &cd->vr_rx_chain[i + 1]; 997 ld->vr_rx_list[i].vr_next = 998 vtophys(&ld->vr_rx_list[i + 1]); 999 } 1000 } 1001 1002 cd->vr_rx_head = &cd->vr_rx_chain[0]; 1003 1004 return(0); 1005 } 1006 1007 /* 1008 * Initialize an RX descriptor and attach an MBUF cluster. 1009 * Note: the length fields are only 11 bits wide, which means the 1010 * largest size we can specify is 2047. This is important because 1011 * MCLBYTES is 2048, so we have to subtract one otherwise we'll 1012 * overflow the field and make a mess. 1013 */ 1014 static int vr_newbuf(sc, c, m) 1015 struct vr_softc *sc; 1016 struct vr_chain_onefrag *c; 1017 struct mbuf *m; 1018 { 1019 struct mbuf *m_new = NULL; 1020 1021 if (m == NULL) { 1022 MGETHDR(m_new, MB_DONTWAIT, MT_DATA); 1023 if (m_new == NULL) 1024 return(ENOBUFS); 1025 1026 MCLGET(m_new, MB_DONTWAIT); 1027 if (!(m_new->m_flags & M_EXT)) { 1028 m_freem(m_new); 1029 return(ENOBUFS); 1030 } 1031 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1032 } else { 1033 m_new = m; 1034 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1035 m_new->m_data = m_new->m_ext.ext_buf; 1036 } 1037 1038 m_adj(m_new, sizeof(u_int64_t)); 1039 1040 c->vr_mbuf = m_new; 1041 c->vr_ptr->vr_status = VR_RXSTAT; 1042 c->vr_ptr->vr_data = vtophys(mtod(m_new, caddr_t)); 1043 c->vr_ptr->vr_ctl = VR_RXCTL | VR_RXLEN; 1044 1045 return(0); 1046 } 1047 1048 /* 1049 * A frame has been uploaded: pass the resulting mbuf chain up to 1050 * the higher level protocols. 1051 */ 1052 static void vr_rxeof(sc) 1053 struct vr_softc *sc; 1054 { 1055 struct ether_header *eh; 1056 struct mbuf *m; 1057 struct ifnet *ifp; 1058 struct vr_chain_onefrag *cur_rx; 1059 int total_len = 0; 1060 u_int32_t rxstat; 1061 1062 ifp = &sc->arpcom.ac_if; 1063 1064 while(!((rxstat = sc->vr_cdata.vr_rx_head->vr_ptr->vr_status) & 1065 VR_RXSTAT_OWN)) { 1066 struct mbuf *m0 = NULL; 1067 1068 cur_rx = sc->vr_cdata.vr_rx_head; 1069 sc->vr_cdata.vr_rx_head = cur_rx->vr_nextdesc; 1070 m = cur_rx->vr_mbuf; 1071 1072 /* 1073 * If an error occurs, update stats, clear the 1074 * status word and leave the mbuf cluster in place: 1075 * it should simply get re-used next time this descriptor 1076 * comes up in the ring. 1077 */ 1078 if (rxstat & VR_RXSTAT_RXERR) { 1079 ifp->if_ierrors++; 1080 printf("vr%d: rx error (%02x):", 1081 sc->vr_unit, rxstat & 0x000000ff); 1082 if (rxstat & VR_RXSTAT_CRCERR) 1083 printf(" crc error"); 1084 if (rxstat & VR_RXSTAT_FRAMEALIGNERR) 1085 printf(" frame alignment error\n"); 1086 if (rxstat & VR_RXSTAT_FIFOOFLOW) 1087 printf(" FIFO overflow"); 1088 if (rxstat & VR_RXSTAT_GIANT) 1089 printf(" received giant packet"); 1090 if (rxstat & VR_RXSTAT_RUNT) 1091 printf(" received runt packet"); 1092 if (rxstat & VR_RXSTAT_BUSERR) 1093 printf(" system bus error"); 1094 if (rxstat & VR_RXSTAT_BUFFERR) 1095 printf("rx buffer error"); 1096 printf("\n"); 1097 vr_newbuf(sc, cur_rx, m); 1098 continue; 1099 } 1100 1101 /* No errors; receive the packet. */ 1102 total_len = VR_RXBYTES(cur_rx->vr_ptr->vr_status); 1103 1104 /* 1105 * XXX The VIA Rhine chip includes the CRC with every 1106 * received frame, and there's no way to turn this 1107 * behavior off (at least, I can't find anything in 1108 * the manual that explains how to do it) so we have 1109 * to trim off the CRC manually. 1110 */ 1111 total_len -= ETHER_CRC_LEN; 1112 1113 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 1114 total_len + ETHER_ALIGN, 0, ifp, NULL); 1115 vr_newbuf(sc, cur_rx, m); 1116 if (m0 == NULL) { 1117 ifp->if_ierrors++; 1118 continue; 1119 } 1120 m_adj(m0, ETHER_ALIGN); 1121 m = m0; 1122 1123 ifp->if_ipackets++; 1124 eh = mtod(m, struct ether_header *); 1125 1126 /* Remove header from mbuf and pass it on. */ 1127 m_adj(m, sizeof(struct ether_header)); 1128 ether_input(ifp, eh, m); 1129 } 1130 1131 return; 1132 } 1133 1134 void vr_rxeoc(sc) 1135 struct vr_softc *sc; 1136 { 1137 struct ifnet *ifp; 1138 int i; 1139 1140 ifp = &sc->arpcom.ac_if; 1141 1142 ifp->if_ierrors++; 1143 1144 VR_CLRBIT16(sc, VR_COMMAND, VR_CMD_RX_ON); 1145 DELAY(10000); 1146 1147 for (i = 0x400; 1148 i && (CSR_READ_2(sc, VR_COMMAND) & VR_CMD_RX_ON); 1149 i--) 1150 ; /* Wait for receiver to stop */ 1151 1152 if (!i) { 1153 printf("vr%d: rx shutdown error!\n", sc->vr_unit); 1154 sc->vr_flags |= VR_F_RESTART; 1155 return; 1156 } 1157 1158 vr_rxeof(sc); 1159 1160 CSR_WRITE_4(sc, VR_RXADDR, vtophys(sc->vr_cdata.vr_rx_head->vr_ptr)); 1161 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RX_ON); 1162 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RX_GO); 1163 1164 return; 1165 } 1166 1167 /* 1168 * A frame was downloaded to the chip. It's safe for us to clean up 1169 * the list buffers. 1170 */ 1171 1172 static void vr_txeof(sc) 1173 struct vr_softc *sc; 1174 { 1175 struct vr_chain *cur_tx; 1176 struct ifnet *ifp; 1177 1178 ifp = &sc->arpcom.ac_if; 1179 1180 /* Reset the timeout timer; if_txeoc will clear it. */ 1181 ifp->if_timer = 5; 1182 1183 /* Sanity check. */ 1184 if (sc->vr_cdata.vr_tx_head == NULL) 1185 return; 1186 1187 /* 1188 * Go through our tx list and free mbufs for those 1189 * frames that have been transmitted. 1190 */ 1191 while(sc->vr_cdata.vr_tx_head->vr_mbuf != NULL) { 1192 u_int32_t txstat; 1193 int i; 1194 1195 cur_tx = sc->vr_cdata.vr_tx_head; 1196 txstat = cur_tx->vr_ptr->vr_status; 1197 1198 if ((txstat & VR_TXSTAT_ABRT) || 1199 (txstat & VR_TXSTAT_UDF)) { 1200 for (i = 0x400; 1201 i && (CSR_READ_2(sc, VR_COMMAND) & VR_CMD_TX_ON); 1202 i--) 1203 ; /* Wait for chip to shutdown */ 1204 if (!i) { 1205 printf("vr%d: tx shutdown timeout\n", sc->vr_unit); 1206 sc->vr_flags |= VR_F_RESTART; 1207 break; 1208 } 1209 VR_TXOWN(cur_tx) = VR_TXSTAT_OWN; 1210 CSR_WRITE_4(sc, VR_TXADDR, vtophys(cur_tx->vr_ptr)); 1211 break; 1212 } 1213 1214 if (txstat & VR_TXSTAT_OWN) 1215 break; 1216 1217 if (txstat & VR_TXSTAT_ERRSUM) { 1218 ifp->if_oerrors++; 1219 if (txstat & VR_TXSTAT_DEFER) 1220 ifp->if_collisions++; 1221 if (txstat & VR_TXSTAT_LATECOLL) 1222 ifp->if_collisions++; 1223 } 1224 1225 ifp->if_collisions +=(txstat & VR_TXSTAT_COLLCNT) >> 3; 1226 1227 ifp->if_opackets++; 1228 if (cur_tx->vr_mbuf != NULL) { 1229 m_freem(cur_tx->vr_mbuf); 1230 cur_tx->vr_mbuf = NULL; 1231 } 1232 1233 if (sc->vr_cdata.vr_tx_head == sc->vr_cdata.vr_tx_tail) { 1234 sc->vr_cdata.vr_tx_head = NULL; 1235 sc->vr_cdata.vr_tx_tail = NULL; 1236 break; 1237 } 1238 1239 sc->vr_cdata.vr_tx_head = cur_tx->vr_nextdesc; 1240 } 1241 1242 return; 1243 } 1244 1245 /* 1246 * TX 'end of channel' interrupt handler. 1247 */ 1248 static void vr_txeoc(sc) 1249 struct vr_softc *sc; 1250 { 1251 struct ifnet *ifp; 1252 1253 ifp = &sc->arpcom.ac_if; 1254 1255 if (sc->vr_cdata.vr_tx_head == NULL) { 1256 ifp->if_flags &= ~IFF_OACTIVE; 1257 sc->vr_cdata.vr_tx_tail = NULL; 1258 ifp->if_timer = 0; 1259 } 1260 1261 return; 1262 } 1263 1264 static void vr_tick(xsc) 1265 void *xsc; 1266 { 1267 struct vr_softc *sc; 1268 struct mii_data *mii; 1269 int s; 1270 1271 s = splimp(); 1272 1273 sc = xsc; 1274 if (sc->vr_flags & VR_F_RESTART) { 1275 printf("vr%d: restarting\n", sc->vr_unit); 1276 vr_stop(sc); 1277 vr_reset(sc); 1278 vr_init(sc); 1279 sc->vr_flags &= ~VR_F_RESTART; 1280 } 1281 1282 mii = device_get_softc(sc->vr_miibus); 1283 mii_tick(mii); 1284 1285 sc->vr_stat_ch = timeout(vr_tick, sc, hz); 1286 1287 splx(s); 1288 1289 return; 1290 } 1291 1292 static void vr_intr(arg) 1293 void *arg; 1294 { 1295 struct vr_softc *sc; 1296 struct ifnet *ifp; 1297 u_int16_t status; 1298 1299 sc = arg; 1300 ifp = &sc->arpcom.ac_if; 1301 1302 /* Supress unwanted interrupts. */ 1303 if (!(ifp->if_flags & IFF_UP)) { 1304 vr_stop(sc); 1305 return; 1306 } 1307 1308 /* Disable interrupts. */ 1309 if ((ifp->if_flags & IFF_POLLING) == 0) 1310 CSR_WRITE_2(sc, VR_IMR, 0x0000); 1311 1312 for (;;) { 1313 1314 status = CSR_READ_2(sc, VR_ISR); 1315 if (status) 1316 CSR_WRITE_2(sc, VR_ISR, status); 1317 1318 if ((status & VR_INTRS) == 0) 1319 break; 1320 1321 if (status & VR_ISR_RX_OK) 1322 vr_rxeof(sc); 1323 1324 if (status & VR_ISR_RX_DROPPED) { 1325 printf("vr%d: rx packet lost\n", sc->vr_unit); 1326 ifp->if_ierrors++; 1327 } 1328 1329 if ((status & VR_ISR_RX_ERR) || (status & VR_ISR_RX_NOBUF) || 1330 (status & VR_ISR_RX_NOBUF) || (status & VR_ISR_RX_OFLOW)) { 1331 printf("vr%d: receive error (%04x)", 1332 sc->vr_unit, status); 1333 if (status & VR_ISR_RX_NOBUF) 1334 printf(" no buffers"); 1335 if (status & VR_ISR_RX_OFLOW) 1336 printf(" overflow"); 1337 if (status & VR_ISR_RX_DROPPED) 1338 printf(" packet lost"); 1339 printf("\n"); 1340 vr_rxeoc(sc); 1341 } 1342 1343 if ((status & VR_ISR_BUSERR) || (status & VR_ISR_TX_UNDERRUN)) { 1344 vr_reset(sc); 1345 vr_init(sc); 1346 break; 1347 } 1348 1349 if ((status & VR_ISR_TX_OK) || (status & VR_ISR_TX_ABRT) || 1350 (status & VR_ISR_TX_ABRT2) || (status & VR_ISR_UDFI)) { 1351 vr_txeof(sc); 1352 if ((status & VR_ISR_UDFI) || 1353 (status & VR_ISR_TX_ABRT2) || 1354 (status & VR_ISR_TX_ABRT)) { 1355 ifp->if_oerrors++; 1356 if (sc->vr_cdata.vr_tx_head != NULL) { 1357 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_ON); 1358 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_GO); 1359 } 1360 } else 1361 vr_txeoc(sc); 1362 } 1363 1364 } 1365 1366 /* Re-enable interrupts. */ 1367 if ((ifp->if_flags & IFF_POLLING) == 0) 1368 CSR_WRITE_2(sc, VR_IMR, VR_INTRS); 1369 1370 if (ifp->if_snd.ifq_head != NULL) { 1371 vr_start(ifp); 1372 } 1373 1374 return; 1375 } 1376 1377 /* 1378 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1379 * pointers to the fragment pointers. 1380 */ 1381 static int vr_encap(sc, c, m_head) 1382 struct vr_softc *sc; 1383 struct vr_chain *c; 1384 struct mbuf *m_head; 1385 { 1386 int frag = 0; 1387 struct vr_desc *f = NULL; 1388 int total_len; 1389 struct mbuf *m; 1390 1391 m = m_head; 1392 total_len = 0; 1393 1394 /* 1395 * The VIA Rhine wants packet buffers to be longword 1396 * aligned, but very often our mbufs aren't. Rather than 1397 * waste time trying to decide when to copy and when not 1398 * to copy, just do it all the time. 1399 */ 1400 if (m != NULL) { 1401 struct mbuf *m_new = NULL; 1402 1403 MGETHDR(m_new, MB_DONTWAIT, MT_DATA); 1404 if (m_new == NULL) { 1405 printf("vr%d: no memory for tx list\n", sc->vr_unit); 1406 return(1); 1407 } 1408 if (m_head->m_pkthdr.len > MHLEN) { 1409 MCLGET(m_new, MB_DONTWAIT); 1410 if (!(m_new->m_flags & M_EXT)) { 1411 m_freem(m_new); 1412 printf("vr%d: no memory for tx list\n", 1413 sc->vr_unit); 1414 return(1); 1415 } 1416 } 1417 m_copydata(m_head, 0, m_head->m_pkthdr.len, 1418 mtod(m_new, caddr_t)); 1419 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 1420 m_freem(m_head); 1421 m_head = m_new; 1422 /* 1423 * The Rhine chip doesn't auto-pad, so we have to make 1424 * sure to pad short frames out to the minimum frame length 1425 * ourselves. 1426 */ 1427 if (m_head->m_len < VR_MIN_FRAMELEN) { 1428 m_new->m_pkthdr.len += VR_MIN_FRAMELEN - m_new->m_len; 1429 m_new->m_len = m_new->m_pkthdr.len; 1430 } 1431 f = c->vr_ptr; 1432 f->vr_data = vtophys(mtod(m_new, caddr_t)); 1433 f->vr_ctl = total_len = m_new->m_len; 1434 f->vr_ctl |= VR_TXCTL_TLINK|VR_TXCTL_FIRSTFRAG; 1435 f->vr_status = 0; 1436 frag = 1; 1437 } 1438 1439 c->vr_mbuf = m_head; 1440 c->vr_ptr->vr_ctl |= VR_TXCTL_LASTFRAG|VR_TXCTL_FINT; 1441 c->vr_ptr->vr_next = vtophys(c->vr_nextdesc->vr_ptr); 1442 1443 return(0); 1444 } 1445 1446 /* 1447 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1448 * to the mbuf data regions directly in the transmit lists. We also save a 1449 * copy of the pointers since the transmit list fragment pointers are 1450 * physical addresses. 1451 */ 1452 1453 static void vr_start(ifp) 1454 struct ifnet *ifp; 1455 { 1456 struct vr_softc *sc; 1457 struct mbuf *m_head = NULL; 1458 struct vr_chain *cur_tx = NULL, *start_tx; 1459 1460 sc = ifp->if_softc; 1461 1462 if (ifp->if_flags & IFF_OACTIVE) 1463 return; 1464 1465 /* 1466 * Check for an available queue slot. If there are none, 1467 * punt. 1468 */ 1469 if (sc->vr_cdata.vr_tx_free->vr_mbuf != NULL) { 1470 ifp->if_flags |= IFF_OACTIVE; 1471 return; 1472 } 1473 1474 start_tx = sc->vr_cdata.vr_tx_free; 1475 1476 while(sc->vr_cdata.vr_tx_free->vr_mbuf == NULL) { 1477 IF_DEQUEUE(&ifp->if_snd, m_head); 1478 if (m_head == NULL) 1479 break; 1480 1481 /* Pick a descriptor off the free list. */ 1482 cur_tx = sc->vr_cdata.vr_tx_free; 1483 sc->vr_cdata.vr_tx_free = cur_tx->vr_nextdesc; 1484 1485 /* Pack the data into the descriptor. */ 1486 if (vr_encap(sc, cur_tx, m_head)) { 1487 IF_PREPEND(&ifp->if_snd, m_head); 1488 ifp->if_flags |= IFF_OACTIVE; 1489 cur_tx = NULL; 1490 break; 1491 } 1492 1493 if (cur_tx != start_tx) 1494 VR_TXOWN(cur_tx) = VR_TXSTAT_OWN; 1495 1496 /* 1497 * If there's a BPF listener, bounce a copy of this frame 1498 * to him. 1499 */ 1500 if (ifp->if_bpf) 1501 bpf_mtap(ifp, cur_tx->vr_mbuf); 1502 1503 VR_TXOWN(cur_tx) = VR_TXSTAT_OWN; 1504 VR_SETBIT16(sc, VR_COMMAND, /*VR_CMD_TX_ON|*/VR_CMD_TX_GO); 1505 } 1506 1507 /* 1508 * If there are no frames queued, bail. 1509 */ 1510 if (cur_tx == NULL) 1511 return; 1512 1513 sc->vr_cdata.vr_tx_tail = cur_tx; 1514 1515 if (sc->vr_cdata.vr_tx_head == NULL) 1516 sc->vr_cdata.vr_tx_head = start_tx; 1517 1518 /* 1519 * Set a timeout in case the chip goes out to lunch. 1520 */ 1521 ifp->if_timer = 5; 1522 1523 return; 1524 } 1525 1526 static void vr_init(xsc) 1527 void *xsc; 1528 { 1529 struct vr_softc *sc = xsc; 1530 struct ifnet *ifp = &sc->arpcom.ac_if; 1531 struct mii_data *mii; 1532 int s, i; 1533 1534 s = splimp(); 1535 1536 mii = device_get_softc(sc->vr_miibus); 1537 1538 /* 1539 * Cancel pending I/O and free all RX/TX buffers. 1540 */ 1541 vr_stop(sc); 1542 vr_reset(sc); 1543 1544 /* 1545 * Set our station address. 1546 */ 1547 for (i = 0; i < ETHER_ADDR_LEN; i++) 1548 CSR_WRITE_1(sc, VR_PAR0 + i, sc->arpcom.ac_enaddr[i]); 1549 1550 /* Set DMA size */ 1551 VR_CLRBIT(sc, VR_BCR0, VR_BCR0_DMA_LENGTH); 1552 VR_SETBIT(sc, VR_BCR0, VR_BCR0_DMA_STORENFWD); 1553 1554 /* 1555 * BCR0 and BCR1 can override the RXCFG and TXCFG registers, 1556 * so we must set both. 1557 */ 1558 VR_CLRBIT(sc, VR_BCR0, VR_BCR0_RX_THRESH); 1559 VR_SETBIT(sc, VR_BCR0, VR_BCR0_RXTHRESH128BYTES); 1560 1561 VR_CLRBIT(sc, VR_BCR1, VR_BCR1_TX_THRESH); 1562 VR_SETBIT(sc, VR_BCR1, VR_BCR1_TXTHRESHSTORENFWD); 1563 1564 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_THRESH); 1565 VR_SETBIT(sc, VR_RXCFG, VR_RXTHRESH_128BYTES); 1566 1567 VR_CLRBIT(sc, VR_TXCFG, VR_TXCFG_TX_THRESH); 1568 VR_SETBIT(sc, VR_TXCFG, VR_TXTHRESH_STORENFWD); 1569 1570 /* Init circular RX list. */ 1571 if (vr_list_rx_init(sc) == ENOBUFS) { 1572 printf("vr%d: initialization failed: no " 1573 "memory for rx buffers\n", sc->vr_unit); 1574 vr_stop(sc); 1575 (void)splx(s); 1576 return; 1577 } 1578 1579 /* 1580 * Init tx descriptors. 1581 */ 1582 vr_list_tx_init(sc); 1583 1584 /* If we want promiscuous mode, set the allframes bit. */ 1585 if (ifp->if_flags & IFF_PROMISC) 1586 VR_SETBIT(sc, VR_RXCFG, VR_RXCFG_RX_PROMISC); 1587 else 1588 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_PROMISC); 1589 1590 /* Set capture broadcast bit to capture broadcast frames. */ 1591 if (ifp->if_flags & IFF_BROADCAST) 1592 VR_SETBIT(sc, VR_RXCFG, VR_RXCFG_RX_BROAD); 1593 else 1594 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_BROAD); 1595 1596 /* 1597 * Program the multicast filter, if necessary. 1598 */ 1599 vr_setmulti(sc); 1600 1601 /* 1602 * Load the address of the RX list. 1603 */ 1604 CSR_WRITE_4(sc, VR_RXADDR, vtophys(sc->vr_cdata.vr_rx_head->vr_ptr)); 1605 1606 /* Enable receiver and transmitter. */ 1607 CSR_WRITE_2(sc, VR_COMMAND, VR_CMD_TX_NOPOLL|VR_CMD_START| 1608 VR_CMD_TX_ON|VR_CMD_RX_ON| 1609 VR_CMD_RX_GO); 1610 1611 CSR_WRITE_4(sc, VR_TXADDR, vtophys(&sc->vr_ldata->vr_tx_list[0])); 1612 1613 /* 1614 * Enable interrupts, unless we are polling. 1615 */ 1616 CSR_WRITE_2(sc, VR_ISR, 0xFFFF); 1617 if ((ifp->if_flags & IFF_POLLING) == 0) 1618 CSR_WRITE_2(sc, VR_IMR, VR_INTRS); 1619 1620 mii_mediachg(mii); 1621 1622 ifp->if_flags |= IFF_RUNNING; 1623 ifp->if_flags &= ~IFF_OACTIVE; 1624 1625 (void)splx(s); 1626 1627 sc->vr_stat_ch = timeout(vr_tick, sc, hz); 1628 1629 return; 1630 } 1631 1632 /* 1633 * Set media options. 1634 */ 1635 static int vr_ifmedia_upd(ifp) 1636 struct ifnet *ifp; 1637 { 1638 struct vr_softc *sc; 1639 1640 sc = ifp->if_softc; 1641 1642 if (ifp->if_flags & IFF_UP) 1643 vr_init(sc); 1644 1645 return(0); 1646 } 1647 1648 /* 1649 * Report current media status. 1650 */ 1651 static void vr_ifmedia_sts(ifp, ifmr) 1652 struct ifnet *ifp; 1653 struct ifmediareq *ifmr; 1654 { 1655 struct vr_softc *sc; 1656 struct mii_data *mii; 1657 1658 sc = ifp->if_softc; 1659 mii = device_get_softc(sc->vr_miibus); 1660 mii_pollstat(mii); 1661 ifmr->ifm_active = mii->mii_media_active; 1662 ifmr->ifm_status = mii->mii_media_status; 1663 1664 return; 1665 } 1666 1667 static int vr_ioctl(ifp, command, data, cr) 1668 struct ifnet *ifp; 1669 u_long command; 1670 caddr_t data; 1671 struct ucred *cr; 1672 { 1673 struct vr_softc *sc = ifp->if_softc; 1674 struct ifreq *ifr = (struct ifreq *) data; 1675 struct mii_data *mii; 1676 int s, error = 0; 1677 1678 s = splimp(); 1679 1680 switch(command) { 1681 case SIOCSIFADDR: 1682 case SIOCGIFADDR: 1683 case SIOCSIFMTU: 1684 error = ether_ioctl(ifp, command, data); 1685 break; 1686 case SIOCSIFFLAGS: 1687 if (ifp->if_flags & IFF_UP) { 1688 vr_init(sc); 1689 } else { 1690 if (ifp->if_flags & IFF_RUNNING) 1691 vr_stop(sc); 1692 } 1693 error = 0; 1694 break; 1695 case SIOCADDMULTI: 1696 case SIOCDELMULTI: 1697 vr_setmulti(sc); 1698 error = 0; 1699 break; 1700 case SIOCGIFMEDIA: 1701 case SIOCSIFMEDIA: 1702 mii = device_get_softc(sc->vr_miibus); 1703 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1704 break; 1705 default: 1706 error = EINVAL; 1707 break; 1708 } 1709 1710 (void)splx(s); 1711 1712 return(error); 1713 } 1714 1715 #ifdef DEVICE_POLLING 1716 1717 static 1718 void 1719 vr_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1720 { 1721 struct vr_softc *sc = ifp->if_softc; 1722 1723 if (cmd == POLL_DEREGISTER) { 1724 CSR_WRITE_2(sc, VR_IMR, VR_INTRS); 1725 } else { 1726 vr_intr(sc); 1727 } 1728 } 1729 1730 #endif 1731 1732 static void vr_watchdog(ifp) 1733 struct ifnet *ifp; 1734 { 1735 struct vr_softc *sc; 1736 1737 sc = ifp->if_softc; 1738 1739 ifp->if_oerrors++; 1740 printf("vr%d: watchdog timeout\n", sc->vr_unit); 1741 1742 #ifdef DEVICE_POLLING 1743 if (++sc->vr_wdogerrors == 1 && (ifp->if_flags & IFF_POLLING) == 0) { 1744 printf("vr%d ints don't seem to be working, " 1745 "emergency switch to polling\n", sc->vr_unit); 1746 emergency_poll_enable("if_vr"); 1747 if (ether_poll_register(vr_poll, ifp)) { 1748 CSR_WRITE_2(sc, VR_IMR, 0x0000); 1749 } 1750 } else 1751 #endif 1752 { 1753 vr_stop(sc); 1754 vr_reset(sc); 1755 vr_init(sc); 1756 } 1757 1758 if (ifp->if_snd.ifq_head != NULL) 1759 vr_start(ifp); 1760 } 1761 1762 /* 1763 * Stop the adapter and free any mbufs allocated to the 1764 * RX and TX lists. 1765 */ 1766 static void vr_stop(sc) 1767 struct vr_softc *sc; 1768 { 1769 int i; 1770 struct ifnet *ifp; 1771 1772 ifp = &sc->arpcom.ac_if; 1773 ifp->if_timer = 0; 1774 1775 untimeout(vr_tick, sc, sc->vr_stat_ch); 1776 1777 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_STOP); 1778 VR_CLRBIT16(sc, VR_COMMAND, (VR_CMD_RX_ON|VR_CMD_TX_ON)); 1779 CSR_WRITE_2(sc, VR_IMR, 0x0000); 1780 CSR_WRITE_4(sc, VR_TXADDR, 0x00000000); 1781 CSR_WRITE_4(sc, VR_RXADDR, 0x00000000); 1782 1783 /* 1784 * Free data in the RX lists. 1785 */ 1786 for (i = 0; i < VR_RX_LIST_CNT; i++) { 1787 if (sc->vr_cdata.vr_rx_chain[i].vr_mbuf != NULL) { 1788 m_freem(sc->vr_cdata.vr_rx_chain[i].vr_mbuf); 1789 sc->vr_cdata.vr_rx_chain[i].vr_mbuf = NULL; 1790 } 1791 } 1792 bzero((char *)&sc->vr_ldata->vr_rx_list, 1793 sizeof(sc->vr_ldata->vr_rx_list)); 1794 1795 /* 1796 * Free the TX list buffers. 1797 */ 1798 for (i = 0; i < VR_TX_LIST_CNT; i++) { 1799 if (sc->vr_cdata.vr_tx_chain[i].vr_mbuf != NULL) { 1800 m_freem(sc->vr_cdata.vr_tx_chain[i].vr_mbuf); 1801 sc->vr_cdata.vr_tx_chain[i].vr_mbuf = NULL; 1802 } 1803 } 1804 1805 bzero((char *)&sc->vr_ldata->vr_tx_list, 1806 sizeof(sc->vr_ldata->vr_tx_list)); 1807 1808 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1809 1810 return; 1811 } 1812 1813 /* 1814 * Stop all chip I/O so that the kernel's probe routines don't 1815 * get confused by errant DMAs when rebooting. 1816 */ 1817 static void vr_shutdown(dev) 1818 device_t dev; 1819 { 1820 struct vr_softc *sc; 1821 1822 sc = device_get_softc(dev); 1823 1824 vr_stop(sc); 1825 1826 return; 1827 } 1828