1 /* 2 * Copyright (c) 1997, 1998 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: src/sys/pci/if_wb.c,v 1.26.2.6 2003/03/05 18:42:34 njl Exp $ 33 * $DragonFly: src/sys/dev/netif/wb/if_wb.c,v 1.7 2004/01/06 01:40:50 dillon Exp $ 34 * 35 * $FreeBSD: src/sys/pci/if_wb.c,v 1.26.2.6 2003/03/05 18:42:34 njl Exp $ 36 */ 37 38 /* 39 * Winbond fast ethernet PCI NIC driver 40 * 41 * Supports various cheap network adapters based on the Winbond W89C840F 42 * fast ethernet controller chip. This includes adapters manufactured by 43 * Winbond itself and some made by Linksys. 44 * 45 * Written by Bill Paul <wpaul@ctr.columbia.edu> 46 * Electrical Engineering Department 47 * Columbia University, New York City 48 */ 49 50 /* 51 * The Winbond W89C840F chip is a bus master; in some ways it resembles 52 * a DEC 'tulip' chip, only not as complicated. Unfortunately, it has 53 * one major difference which is that while the registers do many of 54 * the same things as a tulip adapter, the offsets are different: where 55 * tulip registers are typically spaced 8 bytes apart, the Winbond 56 * registers are spaced 4 bytes apart. The receiver filter is also 57 * programmed differently. 58 * 59 * Like the tulip, the Winbond chip uses small descriptors containing 60 * a status word, a control word and 32-bit areas that can either be used 61 * to point to two external data blocks, or to point to a single block 62 * and another descriptor in a linked list. Descriptors can be grouped 63 * together in blocks to form fixed length rings or can be chained 64 * together in linked lists. A single packet may be spread out over 65 * several descriptors if necessary. 66 * 67 * For the receive ring, this driver uses a linked list of descriptors, 68 * each pointing to a single mbuf cluster buffer, which us large enough 69 * to hold an entire packet. The link list is looped back to created a 70 * closed ring. 71 * 72 * For transmission, the driver creates a linked list of 'super descriptors' 73 * which each contain several individual descriptors linked toghether. 74 * Each 'super descriptor' contains WB_MAXFRAGS descriptors, which we 75 * abuse as fragment pointers. This allows us to use a buffer managment 76 * scheme very similar to that used in the ThunderLAN and Etherlink XL 77 * drivers. 78 * 79 * Autonegotiation is performed using the external PHY via the MII bus. 80 * The sample boards I have all use a Davicom PHY. 81 * 82 * Note: the author of the Linux driver for the Winbond chip alludes 83 * to some sort of flaw in the chip's design that seems to mandate some 84 * drastic workaround which signigicantly impairs transmit performance. 85 * I have no idea what he's on about: transmit performance with all 86 * three of my test boards seems fine. 87 */ 88 89 #include "opt_bdg.h" 90 91 #include <sys/param.h> 92 #include <sys/systm.h> 93 #include <sys/sockio.h> 94 #include <sys/mbuf.h> 95 #include <sys/malloc.h> 96 #include <sys/kernel.h> 97 #include <sys/socket.h> 98 #include <sys/queue.h> 99 100 #include <net/if.h> 101 #include <net/if_arp.h> 102 #include <net/ethernet.h> 103 #include <net/if_dl.h> 104 #include <net/if_media.h> 105 106 #include <net/bpf.h> 107 108 #include <vm/vm.h> /* for vtophys */ 109 #include <vm/pmap.h> /* for vtophys */ 110 #include <machine/clock.h> /* for DELAY */ 111 #include <machine/bus_memio.h> 112 #include <machine/bus_pio.h> 113 #include <machine/bus.h> 114 #include <machine/resource.h> 115 #include <sys/bus.h> 116 #include <sys/rman.h> 117 118 #include <bus/pci/pcireg.h> 119 #include <bus/pci/pcivar.h> 120 121 #include "../mii_layer/mii.h" 122 #include "../mii_layer/miivar.h" 123 124 /* "controller miibus0" required. See GENERIC if you get errors here. */ 125 #include "miibus_if.h" 126 127 #define WB_USEIOSPACE 128 129 #include "if_wbreg.h" 130 131 /* 132 * Various supported device vendors/types and their names. 133 */ 134 static struct wb_type wb_devs[] = { 135 { WB_VENDORID, WB_DEVICEID_840F, 136 "Winbond W89C840F 10/100BaseTX" }, 137 { CP_VENDORID, CP_DEVICEID_RL100, 138 "Compex RL100-ATX 10/100baseTX" }, 139 { 0, 0, NULL } 140 }; 141 142 static int wb_probe (device_t); 143 static int wb_attach (device_t); 144 static int wb_detach (device_t); 145 146 static void wb_bfree (caddr_t, u_int); 147 static int wb_newbuf (struct wb_softc *, 148 struct wb_chain_onefrag *, 149 struct mbuf *); 150 static int wb_encap (struct wb_softc *, struct wb_chain *, 151 struct mbuf *); 152 153 static void wb_rxeof (struct wb_softc *); 154 static void wb_rxeoc (struct wb_softc *); 155 static void wb_txeof (struct wb_softc *); 156 static void wb_txeoc (struct wb_softc *); 157 static void wb_intr (void *); 158 static void wb_tick (void *); 159 static void wb_start (struct ifnet *); 160 static int wb_ioctl (struct ifnet *, u_long, caddr_t); 161 static void wb_init (void *); 162 static void wb_stop (struct wb_softc *); 163 static void wb_watchdog (struct ifnet *); 164 static void wb_shutdown (device_t); 165 static int wb_ifmedia_upd (struct ifnet *); 166 static void wb_ifmedia_sts (struct ifnet *, struct ifmediareq *); 167 168 static void wb_eeprom_putbyte (struct wb_softc *, int); 169 static void wb_eeprom_getword (struct wb_softc *, int, u_int16_t *); 170 static void wb_read_eeprom (struct wb_softc *, caddr_t, int, 171 int, int); 172 static void wb_mii_sync (struct wb_softc *); 173 static void wb_mii_send (struct wb_softc *, u_int32_t, int); 174 static int wb_mii_readreg (struct wb_softc *, struct wb_mii_frame *); 175 static int wb_mii_writereg (struct wb_softc *, struct wb_mii_frame *); 176 177 static void wb_setcfg (struct wb_softc *, u_int32_t); 178 static u_int8_t wb_calchash (caddr_t); 179 static void wb_setmulti (struct wb_softc *); 180 static void wb_reset (struct wb_softc *); 181 static void wb_fixmedia (struct wb_softc *); 182 static int wb_list_rx_init (struct wb_softc *); 183 static int wb_list_tx_init (struct wb_softc *); 184 185 static int wb_miibus_readreg (device_t, int, int); 186 static int wb_miibus_writereg (device_t, int, int, int); 187 static void wb_miibus_statchg (device_t); 188 189 #ifdef WB_USEIOSPACE 190 #define WB_RES SYS_RES_IOPORT 191 #define WB_RID WB_PCI_LOIO 192 #else 193 #define WB_RES SYS_RES_MEMORY 194 #define WB_RID WB_PCI_LOMEM 195 #endif 196 197 static device_method_t wb_methods[] = { 198 /* Device interface */ 199 DEVMETHOD(device_probe, wb_probe), 200 DEVMETHOD(device_attach, wb_attach), 201 DEVMETHOD(device_detach, wb_detach), 202 DEVMETHOD(device_shutdown, wb_shutdown), 203 204 /* bus interface, for miibus */ 205 DEVMETHOD(bus_print_child, bus_generic_print_child), 206 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 207 208 /* MII interface */ 209 DEVMETHOD(miibus_readreg, wb_miibus_readreg), 210 DEVMETHOD(miibus_writereg, wb_miibus_writereg), 211 DEVMETHOD(miibus_statchg, wb_miibus_statchg), 212 { 0, 0 } 213 }; 214 215 static driver_t wb_driver = { 216 "wb", 217 wb_methods, 218 sizeof(struct wb_softc) 219 }; 220 221 static devclass_t wb_devclass; 222 223 DECLARE_DUMMY_MODULE(if_wb); 224 DRIVER_MODULE(if_wb, pci, wb_driver, wb_devclass, 0, 0); 225 DRIVER_MODULE(miibus, wb, miibus_driver, miibus_devclass, 0, 0); 226 227 #define WB_SETBIT(sc, reg, x) \ 228 CSR_WRITE_4(sc, reg, \ 229 CSR_READ_4(sc, reg) | x) 230 231 #define WB_CLRBIT(sc, reg, x) \ 232 CSR_WRITE_4(sc, reg, \ 233 CSR_READ_4(sc, reg) & ~x) 234 235 #define SIO_SET(x) \ 236 CSR_WRITE_4(sc, WB_SIO, \ 237 CSR_READ_4(sc, WB_SIO) | x) 238 239 #define SIO_CLR(x) \ 240 CSR_WRITE_4(sc, WB_SIO, \ 241 CSR_READ_4(sc, WB_SIO) & ~x) 242 243 /* 244 * Send a read command and address to the EEPROM, check for ACK. 245 */ 246 static void wb_eeprom_putbyte(sc, addr) 247 struct wb_softc *sc; 248 int addr; 249 { 250 int d, i; 251 252 d = addr | WB_EECMD_READ; 253 254 /* 255 * Feed in each bit and stobe the clock. 256 */ 257 for (i = 0x400; i; i >>= 1) { 258 if (d & i) { 259 SIO_SET(WB_SIO_EE_DATAIN); 260 } else { 261 SIO_CLR(WB_SIO_EE_DATAIN); 262 } 263 DELAY(100); 264 SIO_SET(WB_SIO_EE_CLK); 265 DELAY(150); 266 SIO_CLR(WB_SIO_EE_CLK); 267 DELAY(100); 268 } 269 270 return; 271 } 272 273 /* 274 * Read a word of data stored in the EEPROM at address 'addr.' 275 */ 276 static void wb_eeprom_getword(sc, addr, dest) 277 struct wb_softc *sc; 278 int addr; 279 u_int16_t *dest; 280 { 281 int i; 282 u_int16_t word = 0; 283 284 /* Enter EEPROM access mode. */ 285 CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS); 286 287 /* 288 * Send address of word we want to read. 289 */ 290 wb_eeprom_putbyte(sc, addr); 291 292 CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS); 293 294 /* 295 * Start reading bits from EEPROM. 296 */ 297 for (i = 0x8000; i; i >>= 1) { 298 SIO_SET(WB_SIO_EE_CLK); 299 DELAY(100); 300 if (CSR_READ_4(sc, WB_SIO) & WB_SIO_EE_DATAOUT) 301 word |= i; 302 SIO_CLR(WB_SIO_EE_CLK); 303 DELAY(100); 304 } 305 306 /* Turn off EEPROM access mode. */ 307 CSR_WRITE_4(sc, WB_SIO, 0); 308 309 *dest = word; 310 311 return; 312 } 313 314 /* 315 * Read a sequence of words from the EEPROM. 316 */ 317 static void wb_read_eeprom(sc, dest, off, cnt, swap) 318 struct wb_softc *sc; 319 caddr_t dest; 320 int off; 321 int cnt; 322 int swap; 323 { 324 int i; 325 u_int16_t word = 0, *ptr; 326 327 for (i = 0; i < cnt; i++) { 328 wb_eeprom_getword(sc, off + i, &word); 329 ptr = (u_int16_t *)(dest + (i * 2)); 330 if (swap) 331 *ptr = ntohs(word); 332 else 333 *ptr = word; 334 } 335 336 return; 337 } 338 339 /* 340 * Sync the PHYs by setting data bit and strobing the clock 32 times. 341 */ 342 static void wb_mii_sync(sc) 343 struct wb_softc *sc; 344 { 345 int i; 346 347 SIO_SET(WB_SIO_MII_DIR|WB_SIO_MII_DATAIN); 348 349 for (i = 0; i < 32; i++) { 350 SIO_SET(WB_SIO_MII_CLK); 351 DELAY(1); 352 SIO_CLR(WB_SIO_MII_CLK); 353 DELAY(1); 354 } 355 356 return; 357 } 358 359 /* 360 * Clock a series of bits through the MII. 361 */ 362 static void wb_mii_send(sc, bits, cnt) 363 struct wb_softc *sc; 364 u_int32_t bits; 365 int cnt; 366 { 367 int i; 368 369 SIO_CLR(WB_SIO_MII_CLK); 370 371 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 372 if (bits & i) { 373 SIO_SET(WB_SIO_MII_DATAIN); 374 } else { 375 SIO_CLR(WB_SIO_MII_DATAIN); 376 } 377 DELAY(1); 378 SIO_CLR(WB_SIO_MII_CLK); 379 DELAY(1); 380 SIO_SET(WB_SIO_MII_CLK); 381 } 382 } 383 384 /* 385 * Read an PHY register through the MII. 386 */ 387 static int wb_mii_readreg(sc, frame) 388 struct wb_softc *sc; 389 struct wb_mii_frame *frame; 390 391 { 392 int i, ack, s; 393 394 s = splimp(); 395 396 /* 397 * Set up frame for RX. 398 */ 399 frame->mii_stdelim = WB_MII_STARTDELIM; 400 frame->mii_opcode = WB_MII_READOP; 401 frame->mii_turnaround = 0; 402 frame->mii_data = 0; 403 404 CSR_WRITE_4(sc, WB_SIO, 0); 405 406 /* 407 * Turn on data xmit. 408 */ 409 SIO_SET(WB_SIO_MII_DIR); 410 411 wb_mii_sync(sc); 412 413 /* 414 * Send command/address info. 415 */ 416 wb_mii_send(sc, frame->mii_stdelim, 2); 417 wb_mii_send(sc, frame->mii_opcode, 2); 418 wb_mii_send(sc, frame->mii_phyaddr, 5); 419 wb_mii_send(sc, frame->mii_regaddr, 5); 420 421 /* Idle bit */ 422 SIO_CLR((WB_SIO_MII_CLK|WB_SIO_MII_DATAIN)); 423 DELAY(1); 424 SIO_SET(WB_SIO_MII_CLK); 425 DELAY(1); 426 427 /* Turn off xmit. */ 428 SIO_CLR(WB_SIO_MII_DIR); 429 /* Check for ack */ 430 SIO_CLR(WB_SIO_MII_CLK); 431 DELAY(1); 432 ack = CSR_READ_4(sc, WB_SIO) & WB_SIO_MII_DATAOUT; 433 SIO_SET(WB_SIO_MII_CLK); 434 DELAY(1); 435 SIO_CLR(WB_SIO_MII_CLK); 436 DELAY(1); 437 SIO_SET(WB_SIO_MII_CLK); 438 DELAY(1); 439 440 /* 441 * Now try reading data bits. If the ack failed, we still 442 * need to clock through 16 cycles to keep the PHY(s) in sync. 443 */ 444 if (ack) { 445 for(i = 0; i < 16; i++) { 446 SIO_CLR(WB_SIO_MII_CLK); 447 DELAY(1); 448 SIO_SET(WB_SIO_MII_CLK); 449 DELAY(1); 450 } 451 goto fail; 452 } 453 454 for (i = 0x8000; i; i >>= 1) { 455 SIO_CLR(WB_SIO_MII_CLK); 456 DELAY(1); 457 if (!ack) { 458 if (CSR_READ_4(sc, WB_SIO) & WB_SIO_MII_DATAOUT) 459 frame->mii_data |= i; 460 DELAY(1); 461 } 462 SIO_SET(WB_SIO_MII_CLK); 463 DELAY(1); 464 } 465 466 fail: 467 468 SIO_CLR(WB_SIO_MII_CLK); 469 DELAY(1); 470 SIO_SET(WB_SIO_MII_CLK); 471 DELAY(1); 472 473 splx(s); 474 475 if (ack) 476 return(1); 477 return(0); 478 } 479 480 /* 481 * Write to a PHY register through the MII. 482 */ 483 static int wb_mii_writereg(sc, frame) 484 struct wb_softc *sc; 485 struct wb_mii_frame *frame; 486 487 { 488 int s; 489 490 s = splimp(); 491 /* 492 * Set up frame for TX. 493 */ 494 495 frame->mii_stdelim = WB_MII_STARTDELIM; 496 frame->mii_opcode = WB_MII_WRITEOP; 497 frame->mii_turnaround = WB_MII_TURNAROUND; 498 499 /* 500 * Turn on data output. 501 */ 502 SIO_SET(WB_SIO_MII_DIR); 503 504 wb_mii_sync(sc); 505 506 wb_mii_send(sc, frame->mii_stdelim, 2); 507 wb_mii_send(sc, frame->mii_opcode, 2); 508 wb_mii_send(sc, frame->mii_phyaddr, 5); 509 wb_mii_send(sc, frame->mii_regaddr, 5); 510 wb_mii_send(sc, frame->mii_turnaround, 2); 511 wb_mii_send(sc, frame->mii_data, 16); 512 513 /* Idle bit. */ 514 SIO_SET(WB_SIO_MII_CLK); 515 DELAY(1); 516 SIO_CLR(WB_SIO_MII_CLK); 517 DELAY(1); 518 519 /* 520 * Turn off xmit. 521 */ 522 SIO_CLR(WB_SIO_MII_DIR); 523 524 splx(s); 525 526 return(0); 527 } 528 529 static int wb_miibus_readreg(dev, phy, reg) 530 device_t dev; 531 int phy, reg; 532 { 533 struct wb_softc *sc; 534 struct wb_mii_frame frame; 535 536 sc = device_get_softc(dev); 537 538 bzero((char *)&frame, sizeof(frame)); 539 540 frame.mii_phyaddr = phy; 541 frame.mii_regaddr = reg; 542 wb_mii_readreg(sc, &frame); 543 544 return(frame.mii_data); 545 } 546 547 static int wb_miibus_writereg(dev, phy, reg, data) 548 device_t dev; 549 int phy, reg, data; 550 { 551 struct wb_softc *sc; 552 struct wb_mii_frame frame; 553 554 sc = device_get_softc(dev); 555 556 bzero((char *)&frame, sizeof(frame)); 557 558 frame.mii_phyaddr = phy; 559 frame.mii_regaddr = reg; 560 frame.mii_data = data; 561 562 wb_mii_writereg(sc, &frame); 563 564 return(0); 565 } 566 567 static void wb_miibus_statchg(dev) 568 device_t dev; 569 { 570 struct wb_softc *sc; 571 struct mii_data *mii; 572 573 sc = device_get_softc(dev); 574 mii = device_get_softc(sc->wb_miibus); 575 wb_setcfg(sc, mii->mii_media_active); 576 577 return; 578 } 579 580 static u_int8_t wb_calchash(addr) 581 caddr_t addr; 582 { 583 u_int32_t crc, carry; 584 int i, j; 585 u_int8_t c; 586 587 /* Compute CRC for the address value. */ 588 crc = 0xFFFFFFFF; /* initial value */ 589 590 for (i = 0; i < 6; i++) { 591 c = *(addr + i); 592 for (j = 0; j < 8; j++) { 593 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 594 crc <<= 1; 595 c >>= 1; 596 if (carry) 597 crc = (crc ^ 0x04c11db6) | carry; 598 } 599 } 600 601 /* 602 * return the filter bit position 603 * Note: I arrived at the following nonsense 604 * through experimentation. It's not the usual way to 605 * generate the bit position but it's the only thing 606 * I could come up with that works. 607 */ 608 return(~(crc >> 26) & 0x0000003F); 609 } 610 611 /* 612 * Program the 64-bit multicast hash filter. 613 */ 614 static void wb_setmulti(sc) 615 struct wb_softc *sc; 616 { 617 struct ifnet *ifp; 618 int h = 0; 619 u_int32_t hashes[2] = { 0, 0 }; 620 struct ifmultiaddr *ifma; 621 u_int32_t rxfilt; 622 int mcnt = 0; 623 624 ifp = &sc->arpcom.ac_if; 625 626 rxfilt = CSR_READ_4(sc, WB_NETCFG); 627 628 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 629 rxfilt |= WB_NETCFG_RX_MULTI; 630 CSR_WRITE_4(sc, WB_NETCFG, rxfilt); 631 CSR_WRITE_4(sc, WB_MAR0, 0xFFFFFFFF); 632 CSR_WRITE_4(sc, WB_MAR1, 0xFFFFFFFF); 633 return; 634 } 635 636 /* first, zot all the existing hash bits */ 637 CSR_WRITE_4(sc, WB_MAR0, 0); 638 CSR_WRITE_4(sc, WB_MAR1, 0); 639 640 /* now program new ones */ 641 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 642 ifma = ifma->ifma_link.le_next) { 643 if (ifma->ifma_addr->sa_family != AF_LINK) 644 continue; 645 h = wb_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 646 if (h < 32) 647 hashes[0] |= (1 << h); 648 else 649 hashes[1] |= (1 << (h - 32)); 650 mcnt++; 651 } 652 653 if (mcnt) 654 rxfilt |= WB_NETCFG_RX_MULTI; 655 else 656 rxfilt &= ~WB_NETCFG_RX_MULTI; 657 658 CSR_WRITE_4(sc, WB_MAR0, hashes[0]); 659 CSR_WRITE_4(sc, WB_MAR1, hashes[1]); 660 CSR_WRITE_4(sc, WB_NETCFG, rxfilt); 661 662 return; 663 } 664 665 /* 666 * The Winbond manual states that in order to fiddle with the 667 * 'full-duplex' and '100Mbps' bits in the netconfig register, we 668 * first have to put the transmit and/or receive logic in the idle state. 669 */ 670 static void wb_setcfg(sc, media) 671 struct wb_softc *sc; 672 u_int32_t media; 673 { 674 int i, restart = 0; 675 676 if (CSR_READ_4(sc, WB_NETCFG) & (WB_NETCFG_TX_ON|WB_NETCFG_RX_ON)) { 677 restart = 1; 678 WB_CLRBIT(sc, WB_NETCFG, (WB_NETCFG_TX_ON|WB_NETCFG_RX_ON)); 679 680 for (i = 0; i < WB_TIMEOUT; i++) { 681 DELAY(10); 682 if ((CSR_READ_4(sc, WB_ISR) & WB_ISR_TX_IDLE) && 683 (CSR_READ_4(sc, WB_ISR) & WB_ISR_RX_IDLE)) 684 break; 685 } 686 687 if (i == WB_TIMEOUT) 688 printf("wb%d: failed to force tx and " 689 "rx to idle state\n", sc->wb_unit); 690 } 691 692 if (IFM_SUBTYPE(media) == IFM_10_T) 693 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_100MBPS); 694 else 695 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_100MBPS); 696 697 if ((media & IFM_GMASK) == IFM_FDX) 698 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_FULLDUPLEX); 699 else 700 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_FULLDUPLEX); 701 702 if (restart) 703 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON|WB_NETCFG_RX_ON); 704 705 return; 706 } 707 708 static void wb_reset(sc) 709 struct wb_softc *sc; 710 { 711 int i; 712 struct mii_data *mii; 713 714 CSR_WRITE_4(sc, WB_NETCFG, 0); 715 CSR_WRITE_4(sc, WB_BUSCTL, 0); 716 CSR_WRITE_4(sc, WB_TXADDR, 0); 717 CSR_WRITE_4(sc, WB_RXADDR, 0); 718 719 WB_SETBIT(sc, WB_BUSCTL, WB_BUSCTL_RESET); 720 WB_SETBIT(sc, WB_BUSCTL, WB_BUSCTL_RESET); 721 722 for (i = 0; i < WB_TIMEOUT; i++) { 723 DELAY(10); 724 if (!(CSR_READ_4(sc, WB_BUSCTL) & WB_BUSCTL_RESET)) 725 break; 726 } 727 if (i == WB_TIMEOUT) 728 printf("wb%d: reset never completed!\n", sc->wb_unit); 729 730 /* Wait a little while for the chip to get its brains in order. */ 731 DELAY(1000); 732 733 if (sc->wb_miibus == NULL) 734 return; 735 736 mii = device_get_softc(sc->wb_miibus); 737 if (mii == NULL) 738 return; 739 740 if (mii->mii_instance) { 741 struct mii_softc *miisc; 742 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 743 miisc = LIST_NEXT(miisc, mii_list)) 744 mii_phy_reset(miisc); 745 } 746 747 return; 748 } 749 750 static void wb_fixmedia(sc) 751 struct wb_softc *sc; 752 { 753 struct mii_data *mii = NULL; 754 struct ifnet *ifp; 755 u_int32_t media; 756 757 if (sc->wb_miibus == NULL) 758 return; 759 760 mii = device_get_softc(sc->wb_miibus); 761 ifp = &sc->arpcom.ac_if; 762 763 mii_pollstat(mii); 764 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T) { 765 media = mii->mii_media_active & ~IFM_10_T; 766 media |= IFM_100_TX; 767 } else if (IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) { 768 media = mii->mii_media_active & ~IFM_100_TX; 769 media |= IFM_10_T; 770 } else 771 return; 772 773 ifmedia_set(&mii->mii_media, media); 774 775 return; 776 } 777 778 /* 779 * Probe for a Winbond chip. Check the PCI vendor and device 780 * IDs against our list and return a device name if we find a match. 781 */ 782 static int wb_probe(dev) 783 device_t dev; 784 { 785 struct wb_type *t; 786 787 t = wb_devs; 788 789 while(t->wb_name != NULL) { 790 if ((pci_get_vendor(dev) == t->wb_vid) && 791 (pci_get_device(dev) == t->wb_did)) { 792 device_set_desc(dev, t->wb_name); 793 return(0); 794 } 795 t++; 796 } 797 798 return(ENXIO); 799 } 800 801 /* 802 * Attach the interface. Allocate softc structures, do ifmedia 803 * setup and ethernet/BPF attach. 804 */ 805 static int wb_attach(dev) 806 device_t dev; 807 { 808 int s; 809 u_char eaddr[ETHER_ADDR_LEN]; 810 u_int32_t command; 811 struct wb_softc *sc; 812 struct ifnet *ifp; 813 int unit, error = 0, rid; 814 815 s = splimp(); 816 817 sc = device_get_softc(dev); 818 unit = device_get_unit(dev); 819 820 /* 821 * Handle power management nonsense. 822 */ 823 824 command = pci_read_config(dev, WB_PCI_CAPID, 4) & 0x000000FF; 825 if (command == 0x01) { 826 827 command = pci_read_config(dev, WB_PCI_PWRMGMTCTRL, 4); 828 if (command & WB_PSTATE_MASK) { 829 u_int32_t iobase, membase, irq; 830 831 /* Save important PCI config data. */ 832 iobase = pci_read_config(dev, WB_PCI_LOIO, 4); 833 membase = pci_read_config(dev, WB_PCI_LOMEM, 4); 834 irq = pci_read_config(dev, WB_PCI_INTLINE, 4); 835 836 /* Reset the power state. */ 837 printf("wb%d: chip is in D%d power mode " 838 "-- setting to D0\n", unit, command & WB_PSTATE_MASK); 839 command &= 0xFFFFFFFC; 840 pci_write_config(dev, WB_PCI_PWRMGMTCTRL, command, 4); 841 842 /* Restore PCI config data. */ 843 pci_write_config(dev, WB_PCI_LOIO, iobase, 4); 844 pci_write_config(dev, WB_PCI_LOMEM, membase, 4); 845 pci_write_config(dev, WB_PCI_INTLINE, irq, 4); 846 } 847 } 848 849 /* 850 * Map control/status registers. 851 */ 852 command = pci_read_config(dev, PCIR_COMMAND, 4); 853 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 854 pci_write_config(dev, PCIR_COMMAND, command, 4); 855 command = pci_read_config(dev, PCIR_COMMAND, 4); 856 857 #ifdef WB_USEIOSPACE 858 if (!(command & PCIM_CMD_PORTEN)) { 859 printf("wb%d: failed to enable I/O ports!\n", unit); 860 error = ENXIO; 861 goto fail; 862 } 863 #else 864 if (!(command & PCIM_CMD_MEMEN)) { 865 printf("wb%d: failed to enable memory mapping!\n", unit); 866 error = ENXIO; 867 goto fail; 868 } 869 #endif 870 871 rid = WB_RID; 872 sc->wb_res = bus_alloc_resource(dev, WB_RES, &rid, 873 0, ~0, 1, RF_ACTIVE); 874 875 if (sc->wb_res == NULL) { 876 printf("wb%d: couldn't map ports/memory\n", unit); 877 error = ENXIO; 878 goto fail; 879 } 880 881 sc->wb_btag = rman_get_bustag(sc->wb_res); 882 sc->wb_bhandle = rman_get_bushandle(sc->wb_res); 883 884 /* Allocate interrupt */ 885 rid = 0; 886 sc->wb_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 887 RF_SHAREABLE | RF_ACTIVE); 888 889 if (sc->wb_irq == NULL) { 890 printf("wb%d: couldn't map interrupt\n", unit); 891 bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res); 892 error = ENXIO; 893 goto fail; 894 } 895 896 error = bus_setup_intr(dev, sc->wb_irq, INTR_TYPE_NET, 897 wb_intr, sc, &sc->wb_intrhand); 898 899 if (error) { 900 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->wb_irq); 901 bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res); 902 printf("wb%d: couldn't set up irq\n", unit); 903 goto fail; 904 } 905 906 /* Save the cache line size. */ 907 sc->wb_cachesize = pci_read_config(dev, WB_PCI_CACHELEN, 4) & 0xFF; 908 909 /* Reset the adapter. */ 910 wb_reset(sc); 911 912 /* 913 * Get station address from the EEPROM. 914 */ 915 wb_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 0); 916 917 /* 918 * A Winbond chip was detected. Inform the world. 919 */ 920 printf("wb%d: Ethernet address: %6D\n", unit, eaddr, ":"); 921 922 sc->wb_unit = unit; 923 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 924 925 sc->wb_ldata = contigmalloc(sizeof(struct wb_list_data) + 8, M_DEVBUF, 926 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 927 928 if (sc->wb_ldata == NULL) { 929 printf("wb%d: no memory for list buffers!\n", unit); 930 bus_teardown_intr(dev, sc->wb_irq, sc->wb_intrhand); 931 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->wb_irq); 932 bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res); 933 error = ENXIO; 934 goto fail; 935 } 936 937 bzero(sc->wb_ldata, sizeof(struct wb_list_data)); 938 939 ifp = &sc->arpcom.ac_if; 940 ifp->if_softc = sc; 941 if_initname(ifp, "wb", unit); 942 ifp->if_mtu = ETHERMTU; 943 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 944 ifp->if_ioctl = wb_ioctl; 945 ifp->if_output = ether_output; 946 ifp->if_start = wb_start; 947 ifp->if_watchdog = wb_watchdog; 948 ifp->if_init = wb_init; 949 ifp->if_baudrate = 10000000; 950 ifp->if_snd.ifq_maxlen = WB_TX_LIST_CNT - 1; 951 952 /* 953 * Do MII setup. 954 */ 955 if (mii_phy_probe(dev, &sc->wb_miibus, 956 wb_ifmedia_upd, wb_ifmedia_sts)) { 957 contigfree(sc->wb_ldata_ptr, sizeof(struct wb_list_data) + 8, 958 M_DEVBUF); 959 bus_teardown_intr(dev, sc->wb_irq, sc->wb_intrhand); 960 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->wb_irq); 961 bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res); 962 error = ENXIO; 963 goto fail; 964 } 965 966 /* 967 * Call MI attach routine. 968 */ 969 ether_ifattach(ifp, ETHER_BPF_SUPPORTED); 970 971 fail: 972 if (error) 973 device_delete_child(dev, sc->wb_miibus); 974 splx(s); 975 976 return(error); 977 } 978 979 static int wb_detach(dev) 980 device_t dev; 981 { 982 struct wb_softc *sc; 983 struct ifnet *ifp; 984 int s; 985 986 s = splimp(); 987 988 sc = device_get_softc(dev); 989 ifp = &sc->arpcom.ac_if; 990 991 wb_stop(sc); 992 ether_ifdetach(ifp, ETHER_BPF_SUPPORTED); 993 994 /* Delete any miibus and phy devices attached to this interface */ 995 bus_generic_detach(dev); 996 device_delete_child(dev, sc->wb_miibus); 997 998 bus_teardown_intr(dev, sc->wb_irq, sc->wb_intrhand); 999 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->wb_irq); 1000 bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res); 1001 1002 contigfree(sc->wb_ldata_ptr, sizeof(struct wb_list_data) + 8, 1003 M_DEVBUF); 1004 1005 splx(s); 1006 1007 return(0); 1008 } 1009 1010 /* 1011 * Initialize the transmit descriptors. 1012 */ 1013 static int wb_list_tx_init(sc) 1014 struct wb_softc *sc; 1015 { 1016 struct wb_chain_data *cd; 1017 struct wb_list_data *ld; 1018 int i; 1019 1020 cd = &sc->wb_cdata; 1021 ld = sc->wb_ldata; 1022 1023 for (i = 0; i < WB_TX_LIST_CNT; i++) { 1024 cd->wb_tx_chain[i].wb_ptr = &ld->wb_tx_list[i]; 1025 if (i == (WB_TX_LIST_CNT - 1)) { 1026 cd->wb_tx_chain[i].wb_nextdesc = 1027 &cd->wb_tx_chain[0]; 1028 } else { 1029 cd->wb_tx_chain[i].wb_nextdesc = 1030 &cd->wb_tx_chain[i + 1]; 1031 } 1032 } 1033 1034 cd->wb_tx_free = &cd->wb_tx_chain[0]; 1035 cd->wb_tx_tail = cd->wb_tx_head = NULL; 1036 1037 return(0); 1038 } 1039 1040 1041 /* 1042 * Initialize the RX descriptors and allocate mbufs for them. Note that 1043 * we arrange the descriptors in a closed ring, so that the last descriptor 1044 * points back to the first. 1045 */ 1046 static int wb_list_rx_init(sc) 1047 struct wb_softc *sc; 1048 { 1049 struct wb_chain_data *cd; 1050 struct wb_list_data *ld; 1051 int i; 1052 1053 cd = &sc->wb_cdata; 1054 ld = sc->wb_ldata; 1055 1056 for (i = 0; i < WB_RX_LIST_CNT; i++) { 1057 cd->wb_rx_chain[i].wb_ptr = 1058 (struct wb_desc *)&ld->wb_rx_list[i]; 1059 cd->wb_rx_chain[i].wb_buf = (void *)&ld->wb_rxbufs[i]; 1060 if (wb_newbuf(sc, &cd->wb_rx_chain[i], NULL) == ENOBUFS) 1061 return(ENOBUFS); 1062 if (i == (WB_RX_LIST_CNT - 1)) { 1063 cd->wb_rx_chain[i].wb_nextdesc = &cd->wb_rx_chain[0]; 1064 ld->wb_rx_list[i].wb_next = 1065 vtophys(&ld->wb_rx_list[0]); 1066 } else { 1067 cd->wb_rx_chain[i].wb_nextdesc = 1068 &cd->wb_rx_chain[i + 1]; 1069 ld->wb_rx_list[i].wb_next = 1070 vtophys(&ld->wb_rx_list[i + 1]); 1071 } 1072 } 1073 1074 cd->wb_rx_head = &cd->wb_rx_chain[0]; 1075 1076 return(0); 1077 } 1078 1079 static void wb_bfree(buf, size) 1080 caddr_t buf; 1081 u_int size; 1082 { 1083 return; 1084 } 1085 1086 /* 1087 * Initialize an RX descriptor and attach an MBUF cluster. 1088 */ 1089 static int wb_newbuf(sc, c, m) 1090 struct wb_softc *sc; 1091 struct wb_chain_onefrag *c; 1092 struct mbuf *m; 1093 { 1094 struct mbuf *m_new = NULL; 1095 1096 if (m == NULL) { 1097 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1098 if (m_new == NULL) 1099 return(ENOBUFS); 1100 1101 m_new->m_data = m_new->m_ext.ext_buf = c->wb_buf; 1102 m_new->m_flags |= M_EXT; 1103 m_new->m_ext.ext_size = m_new->m_pkthdr.len = 1104 m_new->m_len = WB_BUFBYTES; 1105 m_new->m_ext.ext_free = wb_bfree; 1106 m_new->m_ext.ext_ref = wb_bfree; 1107 } else { 1108 m_new = m; 1109 m_new->m_len = m_new->m_pkthdr.len = WB_BUFBYTES; 1110 m_new->m_data = m_new->m_ext.ext_buf; 1111 } 1112 1113 m_adj(m_new, sizeof(u_int64_t)); 1114 1115 c->wb_mbuf = m_new; 1116 c->wb_ptr->wb_data = vtophys(mtod(m_new, caddr_t)); 1117 c->wb_ptr->wb_ctl = WB_RXCTL_RLINK | 1536; 1118 c->wb_ptr->wb_status = WB_RXSTAT; 1119 1120 return(0); 1121 } 1122 1123 /* 1124 * A frame has been uploaded: pass the resulting mbuf chain up to 1125 * the higher level protocols. 1126 */ 1127 static void wb_rxeof(sc) 1128 struct wb_softc *sc; 1129 { 1130 struct ether_header *eh; 1131 struct mbuf *m = NULL; 1132 struct ifnet *ifp; 1133 struct wb_chain_onefrag *cur_rx; 1134 int total_len = 0; 1135 u_int32_t rxstat; 1136 1137 ifp = &sc->arpcom.ac_if; 1138 1139 while(!((rxstat = sc->wb_cdata.wb_rx_head->wb_ptr->wb_status) & 1140 WB_RXSTAT_OWN)) { 1141 struct mbuf *m0 = NULL; 1142 1143 cur_rx = sc->wb_cdata.wb_rx_head; 1144 sc->wb_cdata.wb_rx_head = cur_rx->wb_nextdesc; 1145 1146 m = cur_rx->wb_mbuf; 1147 1148 if ((rxstat & WB_RXSTAT_MIIERR) || 1149 (WB_RXBYTES(cur_rx->wb_ptr->wb_status) < WB_MIN_FRAMELEN) || 1150 (WB_RXBYTES(cur_rx->wb_ptr->wb_status) > 1536) || 1151 !(rxstat & WB_RXSTAT_LASTFRAG) || 1152 !(rxstat & WB_RXSTAT_RXCMP)) { 1153 ifp->if_ierrors++; 1154 wb_newbuf(sc, cur_rx, m); 1155 printf("wb%x: receiver babbling: possible chip " 1156 "bug, forcing reset\n", sc->wb_unit); 1157 wb_fixmedia(sc); 1158 wb_reset(sc); 1159 wb_init(sc); 1160 return; 1161 } 1162 1163 if (rxstat & WB_RXSTAT_RXERR) { 1164 ifp->if_ierrors++; 1165 wb_newbuf(sc, cur_rx, m); 1166 break; 1167 } 1168 1169 /* No errors; receive the packet. */ 1170 total_len = WB_RXBYTES(cur_rx->wb_ptr->wb_status); 1171 1172 /* 1173 * XXX The Winbond chip includes the CRC with every 1174 * received frame, and there's no way to turn this 1175 * behavior off (at least, I can't find anything in 1176 * the manual that explains how to do it) so we have 1177 * to trim off the CRC manually. 1178 */ 1179 total_len -= ETHER_CRC_LEN; 1180 1181 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 1182 total_len + ETHER_ALIGN, 0, ifp, NULL); 1183 wb_newbuf(sc, cur_rx, m); 1184 if (m0 == NULL) { 1185 ifp->if_ierrors++; 1186 break; 1187 } 1188 m_adj(m0, ETHER_ALIGN); 1189 m = m0; 1190 1191 ifp->if_ipackets++; 1192 eh = mtod(m, struct ether_header *); 1193 1194 /* Remove header from mbuf and pass it on. */ 1195 m_adj(m, sizeof(struct ether_header)); 1196 ether_input(ifp, eh, m); 1197 } 1198 } 1199 1200 void wb_rxeoc(sc) 1201 struct wb_softc *sc; 1202 { 1203 wb_rxeof(sc); 1204 1205 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 1206 CSR_WRITE_4(sc, WB_RXADDR, vtophys(&sc->wb_ldata->wb_rx_list[0])); 1207 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 1208 if (CSR_READ_4(sc, WB_ISR) & WB_RXSTATE_SUSPEND) 1209 CSR_WRITE_4(sc, WB_RXSTART, 0xFFFFFFFF); 1210 1211 return; 1212 } 1213 1214 /* 1215 * A frame was downloaded to the chip. It's safe for us to clean up 1216 * the list buffers. 1217 */ 1218 static void wb_txeof(sc) 1219 struct wb_softc *sc; 1220 { 1221 struct wb_chain *cur_tx; 1222 struct ifnet *ifp; 1223 1224 ifp = &sc->arpcom.ac_if; 1225 1226 /* Clear the timeout timer. */ 1227 ifp->if_timer = 0; 1228 1229 if (sc->wb_cdata.wb_tx_head == NULL) 1230 return; 1231 1232 /* 1233 * Go through our tx list and free mbufs for those 1234 * frames that have been transmitted. 1235 */ 1236 while(sc->wb_cdata.wb_tx_head->wb_mbuf != NULL) { 1237 u_int32_t txstat; 1238 1239 cur_tx = sc->wb_cdata.wb_tx_head; 1240 txstat = WB_TXSTATUS(cur_tx); 1241 1242 if ((txstat & WB_TXSTAT_OWN) || txstat == WB_UNSENT) 1243 break; 1244 1245 if (txstat & WB_TXSTAT_TXERR) { 1246 ifp->if_oerrors++; 1247 if (txstat & WB_TXSTAT_ABORT) 1248 ifp->if_collisions++; 1249 if (txstat & WB_TXSTAT_LATECOLL) 1250 ifp->if_collisions++; 1251 } 1252 1253 ifp->if_collisions += (txstat & WB_TXSTAT_COLLCNT) >> 3; 1254 1255 ifp->if_opackets++; 1256 m_freem(cur_tx->wb_mbuf); 1257 cur_tx->wb_mbuf = NULL; 1258 1259 if (sc->wb_cdata.wb_tx_head == sc->wb_cdata.wb_tx_tail) { 1260 sc->wb_cdata.wb_tx_head = NULL; 1261 sc->wb_cdata.wb_tx_tail = NULL; 1262 break; 1263 } 1264 1265 sc->wb_cdata.wb_tx_head = cur_tx->wb_nextdesc; 1266 } 1267 1268 return; 1269 } 1270 1271 /* 1272 * TX 'end of channel' interrupt handler. 1273 */ 1274 static void wb_txeoc(sc) 1275 struct wb_softc *sc; 1276 { 1277 struct ifnet *ifp; 1278 1279 ifp = &sc->arpcom.ac_if; 1280 1281 ifp->if_timer = 0; 1282 1283 if (sc->wb_cdata.wb_tx_head == NULL) { 1284 ifp->if_flags &= ~IFF_OACTIVE; 1285 sc->wb_cdata.wb_tx_tail = NULL; 1286 } else { 1287 if (WB_TXOWN(sc->wb_cdata.wb_tx_head) == WB_UNSENT) { 1288 WB_TXOWN(sc->wb_cdata.wb_tx_head) = WB_TXSTAT_OWN; 1289 ifp->if_timer = 5; 1290 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 1291 } 1292 } 1293 1294 return; 1295 } 1296 1297 static void wb_intr(arg) 1298 void *arg; 1299 { 1300 struct wb_softc *sc; 1301 struct ifnet *ifp; 1302 u_int32_t status; 1303 1304 sc = arg; 1305 ifp = &sc->arpcom.ac_if; 1306 1307 if (!(ifp->if_flags & IFF_UP)) 1308 return; 1309 1310 /* Disable interrupts. */ 1311 CSR_WRITE_4(sc, WB_IMR, 0x00000000); 1312 1313 for (;;) { 1314 1315 status = CSR_READ_4(sc, WB_ISR); 1316 if (status) 1317 CSR_WRITE_4(sc, WB_ISR, status); 1318 1319 if ((status & WB_INTRS) == 0) 1320 break; 1321 1322 if ((status & WB_ISR_RX_NOBUF) || (status & WB_ISR_RX_ERR)) { 1323 ifp->if_ierrors++; 1324 wb_reset(sc); 1325 if (status & WB_ISR_RX_ERR) 1326 wb_fixmedia(sc); 1327 wb_init(sc); 1328 continue; 1329 } 1330 1331 if (status & WB_ISR_RX_OK) 1332 wb_rxeof(sc); 1333 1334 if (status & WB_ISR_RX_IDLE) 1335 wb_rxeoc(sc); 1336 1337 if (status & WB_ISR_TX_OK) 1338 wb_txeof(sc); 1339 1340 if (status & WB_ISR_TX_NOBUF) 1341 wb_txeoc(sc); 1342 1343 if (status & WB_ISR_TX_IDLE) { 1344 wb_txeof(sc); 1345 if (sc->wb_cdata.wb_tx_head != NULL) { 1346 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1347 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 1348 } 1349 } 1350 1351 if (status & WB_ISR_TX_UNDERRUN) { 1352 ifp->if_oerrors++; 1353 wb_txeof(sc); 1354 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1355 /* Jack up TX threshold */ 1356 sc->wb_txthresh += WB_TXTHRESH_CHUNK; 1357 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_THRESH); 1358 WB_SETBIT(sc, WB_NETCFG, WB_TXTHRESH(sc->wb_txthresh)); 1359 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1360 } 1361 1362 if (status & WB_ISR_BUS_ERR) { 1363 wb_reset(sc); 1364 wb_init(sc); 1365 } 1366 1367 } 1368 1369 /* Re-enable interrupts. */ 1370 CSR_WRITE_4(sc, WB_IMR, WB_INTRS); 1371 1372 if (ifp->if_snd.ifq_head != NULL) { 1373 wb_start(ifp); 1374 } 1375 1376 return; 1377 } 1378 1379 static void wb_tick(xsc) 1380 void *xsc; 1381 { 1382 struct wb_softc *sc; 1383 struct mii_data *mii; 1384 int s; 1385 1386 s = splimp(); 1387 1388 sc = xsc; 1389 mii = device_get_softc(sc->wb_miibus); 1390 1391 mii_tick(mii); 1392 1393 sc->wb_stat_ch = timeout(wb_tick, sc, hz); 1394 1395 splx(s); 1396 1397 return; 1398 } 1399 1400 /* 1401 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1402 * pointers to the fragment pointers. 1403 */ 1404 static int wb_encap(sc, c, m_head) 1405 struct wb_softc *sc; 1406 struct wb_chain *c; 1407 struct mbuf *m_head; 1408 { 1409 int frag = 0; 1410 struct wb_desc *f = NULL; 1411 int total_len; 1412 struct mbuf *m; 1413 1414 /* 1415 * Start packing the mbufs in this chain into 1416 * the fragment pointers. Stop when we run out 1417 * of fragments or hit the end of the mbuf chain. 1418 */ 1419 m = m_head; 1420 total_len = 0; 1421 1422 for (m = m_head, frag = 0; m != NULL; m = m->m_next) { 1423 if (m->m_len != 0) { 1424 if (frag == WB_MAXFRAGS) 1425 break; 1426 total_len += m->m_len; 1427 f = &c->wb_ptr->wb_frag[frag]; 1428 f->wb_ctl = WB_TXCTL_TLINK | m->m_len; 1429 if (frag == 0) { 1430 f->wb_ctl |= WB_TXCTL_FIRSTFRAG; 1431 f->wb_status = 0; 1432 } else 1433 f->wb_status = WB_TXSTAT_OWN; 1434 f->wb_next = vtophys(&c->wb_ptr->wb_frag[frag + 1]); 1435 f->wb_data = vtophys(mtod(m, vm_offset_t)); 1436 frag++; 1437 } 1438 } 1439 1440 /* 1441 * Handle special case: we used up all 16 fragments, 1442 * but we have more mbufs left in the chain. Copy the 1443 * data into an mbuf cluster. Note that we don't 1444 * bother clearing the values in the other fragment 1445 * pointers/counters; it wouldn't gain us anything, 1446 * and would waste cycles. 1447 */ 1448 if (m != NULL) { 1449 struct mbuf *m_new = NULL; 1450 1451 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1452 if (m_new == NULL) 1453 return(1); 1454 if (m_head->m_pkthdr.len > MHLEN) { 1455 MCLGET(m_new, M_DONTWAIT); 1456 if (!(m_new->m_flags & M_EXT)) { 1457 m_freem(m_new); 1458 return(1); 1459 } 1460 } 1461 m_copydata(m_head, 0, m_head->m_pkthdr.len, 1462 mtod(m_new, caddr_t)); 1463 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 1464 m_freem(m_head); 1465 m_head = m_new; 1466 f = &c->wb_ptr->wb_frag[0]; 1467 f->wb_status = 0; 1468 f->wb_data = vtophys(mtod(m_new, caddr_t)); 1469 f->wb_ctl = total_len = m_new->m_len; 1470 f->wb_ctl |= WB_TXCTL_TLINK|WB_TXCTL_FIRSTFRAG; 1471 frag = 1; 1472 } 1473 1474 if (total_len < WB_MIN_FRAMELEN) { 1475 f = &c->wb_ptr->wb_frag[frag]; 1476 f->wb_ctl = WB_MIN_FRAMELEN - total_len; 1477 f->wb_data = vtophys(&sc->wb_cdata.wb_pad); 1478 f->wb_ctl |= WB_TXCTL_TLINK; 1479 f->wb_status = WB_TXSTAT_OWN; 1480 frag++; 1481 } 1482 1483 c->wb_mbuf = m_head; 1484 c->wb_lastdesc = frag - 1; 1485 WB_TXCTL(c) |= WB_TXCTL_LASTFRAG; 1486 WB_TXNEXT(c) = vtophys(&c->wb_nextdesc->wb_ptr->wb_frag[0]); 1487 1488 return(0); 1489 } 1490 1491 /* 1492 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1493 * to the mbuf data regions directly in the transmit lists. We also save a 1494 * copy of the pointers since the transmit list fragment pointers are 1495 * physical addresses. 1496 */ 1497 1498 static void wb_start(ifp) 1499 struct ifnet *ifp; 1500 { 1501 struct wb_softc *sc; 1502 struct mbuf *m_head = NULL; 1503 struct wb_chain *cur_tx = NULL, *start_tx; 1504 1505 sc = ifp->if_softc; 1506 1507 /* 1508 * Check for an available queue slot. If there are none, 1509 * punt. 1510 */ 1511 if (sc->wb_cdata.wb_tx_free->wb_mbuf != NULL) { 1512 ifp->if_flags |= IFF_OACTIVE; 1513 return; 1514 } 1515 1516 start_tx = sc->wb_cdata.wb_tx_free; 1517 1518 while(sc->wb_cdata.wb_tx_free->wb_mbuf == NULL) { 1519 IF_DEQUEUE(&ifp->if_snd, m_head); 1520 if (m_head == NULL) 1521 break; 1522 1523 /* Pick a descriptor off the free list. */ 1524 cur_tx = sc->wb_cdata.wb_tx_free; 1525 sc->wb_cdata.wb_tx_free = cur_tx->wb_nextdesc; 1526 1527 /* Pack the data into the descriptor. */ 1528 wb_encap(sc, cur_tx, m_head); 1529 1530 if (cur_tx != start_tx) 1531 WB_TXOWN(cur_tx) = WB_TXSTAT_OWN; 1532 1533 /* 1534 * If there's a BPF listener, bounce a copy of this frame 1535 * to him. 1536 */ 1537 if (ifp->if_bpf) 1538 bpf_mtap(ifp, cur_tx->wb_mbuf); 1539 } 1540 1541 /* 1542 * If there are no packets queued, bail. 1543 */ 1544 if (cur_tx == NULL) 1545 return; 1546 1547 /* 1548 * Place the request for the upload interrupt 1549 * in the last descriptor in the chain. This way, if 1550 * we're chaining several packets at once, we'll only 1551 * get an interupt once for the whole chain rather than 1552 * once for each packet. 1553 */ 1554 WB_TXCTL(cur_tx) |= WB_TXCTL_FINT; 1555 cur_tx->wb_ptr->wb_frag[0].wb_ctl |= WB_TXCTL_FINT; 1556 sc->wb_cdata.wb_tx_tail = cur_tx; 1557 1558 if (sc->wb_cdata.wb_tx_head == NULL) { 1559 sc->wb_cdata.wb_tx_head = start_tx; 1560 WB_TXOWN(start_tx) = WB_TXSTAT_OWN; 1561 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 1562 } else { 1563 /* 1564 * We need to distinguish between the case where 1565 * the own bit is clear because the chip cleared it 1566 * and where the own bit is clear because we haven't 1567 * set it yet. The magic value WB_UNSET is just some 1568 * ramdomly chosen number which doesn't have the own 1569 * bit set. When we actually transmit the frame, the 1570 * status word will have _only_ the own bit set, so 1571 * the txeoc handler will be able to tell if it needs 1572 * to initiate another transmission to flush out pending 1573 * frames. 1574 */ 1575 WB_TXOWN(start_tx) = WB_UNSENT; 1576 } 1577 1578 /* 1579 * Set a timeout in case the chip goes out to lunch. 1580 */ 1581 ifp->if_timer = 5; 1582 1583 return; 1584 } 1585 1586 static void wb_init(xsc) 1587 void *xsc; 1588 { 1589 struct wb_softc *sc = xsc; 1590 struct ifnet *ifp = &sc->arpcom.ac_if; 1591 int s, i; 1592 struct mii_data *mii; 1593 1594 s = splimp(); 1595 1596 mii = device_get_softc(sc->wb_miibus); 1597 1598 /* 1599 * Cancel pending I/O and free all RX/TX buffers. 1600 */ 1601 wb_stop(sc); 1602 wb_reset(sc); 1603 1604 sc->wb_txthresh = WB_TXTHRESH_INIT; 1605 1606 /* 1607 * Set cache alignment and burst length. 1608 */ 1609 #ifdef foo 1610 CSR_WRITE_4(sc, WB_BUSCTL, WB_BUSCTL_CONFIG); 1611 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_THRESH); 1612 WB_SETBIT(sc, WB_NETCFG, WB_TXTHRESH(sc->wb_txthresh)); 1613 #endif 1614 1615 CSR_WRITE_4(sc, WB_BUSCTL, WB_BUSCTL_MUSTBEONE|WB_BUSCTL_ARBITRATION); 1616 WB_SETBIT(sc, WB_BUSCTL, WB_BURSTLEN_16LONG); 1617 switch(sc->wb_cachesize) { 1618 case 32: 1619 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_32LONG); 1620 break; 1621 case 16: 1622 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_16LONG); 1623 break; 1624 case 8: 1625 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_8LONG); 1626 break; 1627 case 0: 1628 default: 1629 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_NONE); 1630 break; 1631 } 1632 1633 /* This doesn't tend to work too well at 100Mbps. */ 1634 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_EARLY_ON); 1635 1636 /* Init our MAC address */ 1637 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1638 CSR_WRITE_1(sc, WB_NODE0 + i, sc->arpcom.ac_enaddr[i]); 1639 } 1640 1641 /* Init circular RX list. */ 1642 if (wb_list_rx_init(sc) == ENOBUFS) { 1643 printf("wb%d: initialization failed: no " 1644 "memory for rx buffers\n", sc->wb_unit); 1645 wb_stop(sc); 1646 (void)splx(s); 1647 return; 1648 } 1649 1650 /* Init TX descriptors. */ 1651 wb_list_tx_init(sc); 1652 1653 /* If we want promiscuous mode, set the allframes bit. */ 1654 if (ifp->if_flags & IFF_PROMISC) { 1655 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ALLPHYS); 1656 } else { 1657 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ALLPHYS); 1658 } 1659 1660 /* 1661 * Set capture broadcast bit to capture broadcast frames. 1662 */ 1663 if (ifp->if_flags & IFF_BROADCAST) { 1664 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_BROAD); 1665 } else { 1666 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_BROAD); 1667 } 1668 1669 /* 1670 * Program the multicast filter, if necessary. 1671 */ 1672 wb_setmulti(sc); 1673 1674 /* 1675 * Load the address of the RX list. 1676 */ 1677 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 1678 CSR_WRITE_4(sc, WB_RXADDR, vtophys(&sc->wb_ldata->wb_rx_list[0])); 1679 1680 /* 1681 * Enable interrupts. 1682 */ 1683 CSR_WRITE_4(sc, WB_IMR, WB_INTRS); 1684 CSR_WRITE_4(sc, WB_ISR, 0xFFFFFFFF); 1685 1686 /* Enable receiver and transmitter. */ 1687 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 1688 CSR_WRITE_4(sc, WB_RXSTART, 0xFFFFFFFF); 1689 1690 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1691 CSR_WRITE_4(sc, WB_TXADDR, vtophys(&sc->wb_ldata->wb_tx_list[0])); 1692 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1693 1694 mii_mediachg(mii); 1695 1696 ifp->if_flags |= IFF_RUNNING; 1697 ifp->if_flags &= ~IFF_OACTIVE; 1698 1699 (void)splx(s); 1700 1701 sc->wb_stat_ch = timeout(wb_tick, sc, hz); 1702 1703 return; 1704 } 1705 1706 /* 1707 * Set media options. 1708 */ 1709 static int wb_ifmedia_upd(ifp) 1710 struct ifnet *ifp; 1711 { 1712 struct wb_softc *sc; 1713 1714 sc = ifp->if_softc; 1715 1716 if (ifp->if_flags & IFF_UP) 1717 wb_init(sc); 1718 1719 return(0); 1720 } 1721 1722 /* 1723 * Report current media status. 1724 */ 1725 static void wb_ifmedia_sts(ifp, ifmr) 1726 struct ifnet *ifp; 1727 struct ifmediareq *ifmr; 1728 { 1729 struct wb_softc *sc; 1730 struct mii_data *mii; 1731 1732 sc = ifp->if_softc; 1733 1734 mii = device_get_softc(sc->wb_miibus); 1735 1736 mii_pollstat(mii); 1737 ifmr->ifm_active = mii->mii_media_active; 1738 ifmr->ifm_status = mii->mii_media_status; 1739 1740 return; 1741 } 1742 1743 static int wb_ioctl(ifp, command, data) 1744 struct ifnet *ifp; 1745 u_long command; 1746 caddr_t data; 1747 { 1748 struct wb_softc *sc = ifp->if_softc; 1749 struct mii_data *mii; 1750 struct ifreq *ifr = (struct ifreq *) data; 1751 int s, error = 0; 1752 1753 s = splimp(); 1754 1755 switch(command) { 1756 case SIOCSIFADDR: 1757 case SIOCGIFADDR: 1758 case SIOCSIFMTU: 1759 error = ether_ioctl(ifp, command, data); 1760 break; 1761 case SIOCSIFFLAGS: 1762 if (ifp->if_flags & IFF_UP) { 1763 wb_init(sc); 1764 } else { 1765 if (ifp->if_flags & IFF_RUNNING) 1766 wb_stop(sc); 1767 } 1768 error = 0; 1769 break; 1770 case SIOCADDMULTI: 1771 case SIOCDELMULTI: 1772 wb_setmulti(sc); 1773 error = 0; 1774 break; 1775 case SIOCGIFMEDIA: 1776 case SIOCSIFMEDIA: 1777 mii = device_get_softc(sc->wb_miibus); 1778 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1779 break; 1780 default: 1781 error = EINVAL; 1782 break; 1783 } 1784 1785 (void)splx(s); 1786 1787 return(error); 1788 } 1789 1790 static void wb_watchdog(ifp) 1791 struct ifnet *ifp; 1792 { 1793 struct wb_softc *sc; 1794 1795 sc = ifp->if_softc; 1796 1797 ifp->if_oerrors++; 1798 printf("wb%d: watchdog timeout\n", sc->wb_unit); 1799 #ifdef foo 1800 if (!(wb_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT)) 1801 printf("wb%d: no carrier - transceiver cable problem?\n", 1802 sc->wb_unit); 1803 #endif 1804 wb_stop(sc); 1805 wb_reset(sc); 1806 wb_init(sc); 1807 1808 if (ifp->if_snd.ifq_head != NULL) 1809 wb_start(ifp); 1810 1811 return; 1812 } 1813 1814 /* 1815 * Stop the adapter and free any mbufs allocated to the 1816 * RX and TX lists. 1817 */ 1818 static void wb_stop(sc) 1819 struct wb_softc *sc; 1820 { 1821 int i; 1822 struct ifnet *ifp; 1823 1824 ifp = &sc->arpcom.ac_if; 1825 ifp->if_timer = 0; 1826 1827 untimeout(wb_tick, sc, sc->wb_stat_ch); 1828 1829 WB_CLRBIT(sc, WB_NETCFG, (WB_NETCFG_RX_ON|WB_NETCFG_TX_ON)); 1830 CSR_WRITE_4(sc, WB_IMR, 0x00000000); 1831 CSR_WRITE_4(sc, WB_TXADDR, 0x00000000); 1832 CSR_WRITE_4(sc, WB_RXADDR, 0x00000000); 1833 1834 /* 1835 * Free data in the RX lists. 1836 */ 1837 for (i = 0; i < WB_RX_LIST_CNT; i++) { 1838 if (sc->wb_cdata.wb_rx_chain[i].wb_mbuf != NULL) { 1839 m_freem(sc->wb_cdata.wb_rx_chain[i].wb_mbuf); 1840 sc->wb_cdata.wb_rx_chain[i].wb_mbuf = NULL; 1841 } 1842 } 1843 bzero((char *)&sc->wb_ldata->wb_rx_list, 1844 sizeof(sc->wb_ldata->wb_rx_list)); 1845 1846 /* 1847 * Free the TX list buffers. 1848 */ 1849 for (i = 0; i < WB_TX_LIST_CNT; i++) { 1850 if (sc->wb_cdata.wb_tx_chain[i].wb_mbuf != NULL) { 1851 m_freem(sc->wb_cdata.wb_tx_chain[i].wb_mbuf); 1852 sc->wb_cdata.wb_tx_chain[i].wb_mbuf = NULL; 1853 } 1854 } 1855 1856 bzero((char *)&sc->wb_ldata->wb_tx_list, 1857 sizeof(sc->wb_ldata->wb_tx_list)); 1858 1859 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1860 1861 return; 1862 } 1863 1864 /* 1865 * Stop all chip I/O so that the kernel's probe routines don't 1866 * get confused by errant DMAs when rebooting. 1867 */ 1868 static void wb_shutdown(dev) 1869 device_t dev; 1870 { 1871 struct wb_softc *sc; 1872 1873 sc = device_get_softc(dev); 1874 wb_stop(sc); 1875 1876 return; 1877 } 1878