1 /* 2 * Copyright (c) 1997, 1998 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: src/sys/pci/if_wb.c,v 1.26.2.6 2003/03/05 18:42:34 njl Exp $ 33 * $DragonFly: src/sys/dev/netif/wb/if_wb.c,v 1.30 2005/06/14 14:19:22 joerg Exp $ 34 */ 35 36 /* 37 * Winbond fast ethernet PCI NIC driver 38 * 39 * Supports various cheap network adapters based on the Winbond W89C840F 40 * fast ethernet controller chip. This includes adapters manufactured by 41 * Winbond itself and some made by Linksys. 42 * 43 * Written by Bill Paul <wpaul@ctr.columbia.edu> 44 * Electrical Engineering Department 45 * Columbia University, New York City 46 */ 47 48 /* 49 * The Winbond W89C840F chip is a bus master; in some ways it resembles 50 * a DEC 'tulip' chip, only not as complicated. Unfortunately, it has 51 * one major difference which is that while the registers do many of 52 * the same things as a tulip adapter, the offsets are different: where 53 * tulip registers are typically spaced 8 bytes apart, the Winbond 54 * registers are spaced 4 bytes apart. The receiver filter is also 55 * programmed differently. 56 * 57 * Like the tulip, the Winbond chip uses small descriptors containing 58 * a status word, a control word and 32-bit areas that can either be used 59 * to point to two external data blocks, or to point to a single block 60 * and another descriptor in a linked list. Descriptors can be grouped 61 * together in blocks to form fixed length rings or can be chained 62 * together in linked lists. A single packet may be spread out over 63 * several descriptors if necessary. 64 * 65 * For the receive ring, this driver uses a linked list of descriptors, 66 * each pointing to a single mbuf cluster buffer, which us large enough 67 * to hold an entire packet. The link list is looped back to created a 68 * closed ring. 69 * 70 * For transmission, the driver creates a linked list of 'super descriptors' 71 * which each contain several individual descriptors linked toghether. 72 * Each 'super descriptor' contains WB_MAXFRAGS descriptors, which we 73 * abuse as fragment pointers. This allows us to use a buffer managment 74 * scheme very similar to that used in the ThunderLAN and Etherlink XL 75 * drivers. 76 * 77 * Autonegotiation is performed using the external PHY via the MII bus. 78 * The sample boards I have all use a Davicom PHY. 79 * 80 * Note: the author of the Linux driver for the Winbond chip alludes 81 * to some sort of flaw in the chip's design that seems to mandate some 82 * drastic workaround which signigicantly impairs transmit performance. 83 * I have no idea what he's on about: transmit performance with all 84 * three of my test boards seems fine. 85 */ 86 87 #include "opt_bdg.h" 88 89 #include <sys/param.h> 90 #include <sys/systm.h> 91 #include <sys/sockio.h> 92 #include <sys/mbuf.h> 93 #include <sys/malloc.h> 94 #include <sys/kernel.h> 95 #include <sys/socket.h> 96 #include <sys/queue.h> 97 #include <sys/thread2.h> 98 99 #include <net/if.h> 100 #include <net/ifq_var.h> 101 #include <net/if_arp.h> 102 #include <net/ethernet.h> 103 #include <net/if_dl.h> 104 #include <net/if_media.h> 105 106 #include <net/bpf.h> 107 108 #include <vm/vm.h> /* for vtophys */ 109 #include <vm/pmap.h> /* for vtophys */ 110 #include <machine/bus.h> 111 #include <machine/resource.h> 112 #include <sys/bus.h> 113 #include <sys/rman.h> 114 115 #include <bus/pci/pcireg.h> 116 #include <bus/pci/pcivar.h> 117 118 #include <dev/netif/mii_layer/mii.h> 119 #include <dev/netif/mii_layer/miivar.h> 120 121 /* "controller miibus0" required. See GENERIC if you get errors here. */ 122 #include "miibus_if.h" 123 124 #define WB_USEIOSPACE 125 126 #include "if_wbreg.h" 127 128 /* 129 * Various supported device vendors/types and their names. 130 */ 131 static struct wb_type wb_devs[] = { 132 { WB_VENDORID, WB_DEVICEID_840F, 133 "Winbond W89C840F 10/100BaseTX" }, 134 { CP_VENDORID, CP_DEVICEID_RL100, 135 "Compex RL100-ATX 10/100baseTX" }, 136 { 0, 0, NULL } 137 }; 138 139 static int wb_probe(device_t); 140 static int wb_attach(device_t); 141 static int wb_detach(device_t); 142 143 static void wb_bfree(void *); 144 static int wb_newbuf(struct wb_softc *, struct wb_chain_onefrag *, 145 struct mbuf *); 146 static int wb_encap(struct wb_softc *, struct wb_chain *, struct mbuf *); 147 148 static void wb_rxeof(struct wb_softc *); 149 static void wb_rxeoc(struct wb_softc *); 150 static void wb_txeof(struct wb_softc *); 151 static void wb_txeoc(struct wb_softc *); 152 static void wb_intr(void *); 153 static void wb_tick(void *); 154 static void wb_start(struct ifnet *); 155 static int wb_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *); 156 static void wb_init(void *); 157 static void wb_stop(struct wb_softc *); 158 static void wb_watchdog(struct ifnet *); 159 static void wb_shutdown(device_t); 160 static int wb_ifmedia_upd(struct ifnet *); 161 static void wb_ifmedia_sts(struct ifnet *, struct ifmediareq *); 162 163 static void wb_eeprom_putbyte(struct wb_softc *, int); 164 static void wb_eeprom_getword(struct wb_softc *, int, uint16_t *); 165 static void wb_read_eeprom(struct wb_softc *, caddr_t, int, int); 166 static void wb_mii_sync(struct wb_softc *); 167 static void wb_mii_send(struct wb_softc *, uint32_t, int); 168 static int wb_mii_readreg(struct wb_softc *, struct wb_mii_frame *); 169 static int wb_mii_writereg(struct wb_softc *, struct wb_mii_frame *); 170 171 static void wb_setcfg(struct wb_softc *, uint32_t); 172 static void wb_setmulti(struct wb_softc *); 173 static void wb_reset(struct wb_softc *); 174 static void wb_fixmedia(struct wb_softc *); 175 static int wb_list_rx_init(struct wb_softc *); 176 static int wb_list_tx_init(struct wb_softc *); 177 178 static int wb_miibus_readreg(device_t, int, int); 179 static int wb_miibus_writereg(device_t, int, int, int); 180 static void wb_miibus_statchg(device_t); 181 182 #ifdef WB_USEIOSPACE 183 #define WB_RES SYS_RES_IOPORT 184 #define WB_RID WB_PCI_LOIO 185 #else 186 #define WB_RES SYS_RES_MEMORY 187 #define WB_RID WB_PCI_LOMEM 188 #endif 189 190 static device_method_t wb_methods[] = { 191 /* Device interface */ 192 DEVMETHOD(device_probe, wb_probe), 193 DEVMETHOD(device_attach, wb_attach), 194 DEVMETHOD(device_detach, wb_detach), 195 DEVMETHOD(device_shutdown, wb_shutdown), 196 197 /* bus interface, for miibus */ 198 DEVMETHOD(bus_print_child, bus_generic_print_child), 199 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 200 201 /* MII interface */ 202 DEVMETHOD(miibus_readreg, wb_miibus_readreg), 203 DEVMETHOD(miibus_writereg, wb_miibus_writereg), 204 DEVMETHOD(miibus_statchg, wb_miibus_statchg), 205 { 0, 0 } 206 }; 207 208 static DEFINE_CLASS_0(wb, wb_driver, wb_methods, sizeof(struct wb_softc)); 209 static devclass_t wb_devclass; 210 211 DECLARE_DUMMY_MODULE(if_wb); 212 DRIVER_MODULE(if_wb, pci, wb_driver, wb_devclass, 0, 0); 213 DRIVER_MODULE(miibus, wb, miibus_driver, miibus_devclass, 0, 0); 214 215 #define WB_SETBIT(sc, reg, x) \ 216 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x)) 217 218 #define WB_CLRBIT(sc, reg, x) \ 219 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x)) 220 221 #define SIO_SET(x) \ 222 CSR_WRITE_4(sc, WB_SIO, CSR_READ_4(sc, WB_SIO) | (x)) 223 224 #define SIO_CLR(x) \ 225 CSR_WRITE_4(sc, WB_SIO, CSR_READ_4(sc, WB_SIO) & ~(x)) 226 227 /* 228 * Send a read command and address to the EEPROM, check for ACK. 229 */ 230 static void 231 wb_eeprom_putbyte(struct wb_softc *sc, int addr) 232 { 233 int d, i; 234 235 d = addr | WB_EECMD_READ; 236 237 /* 238 * Feed in each bit and stobe the clock. 239 */ 240 for (i = 0x400; i; i >>= 1) { 241 if (d & i) 242 SIO_SET(WB_SIO_EE_DATAIN); 243 else 244 SIO_CLR(WB_SIO_EE_DATAIN); 245 DELAY(100); 246 SIO_SET(WB_SIO_EE_CLK); 247 DELAY(150); 248 SIO_CLR(WB_SIO_EE_CLK); 249 DELAY(100); 250 } 251 } 252 253 /* 254 * Read a word of data stored in the EEPROM at address 'addr.' 255 */ 256 static void 257 wb_eeprom_getword(struct wb_softc *sc, int addr, uint16_t *dest) 258 { 259 int i; 260 uint16_t word = 0; 261 262 /* Enter EEPROM access mode. */ 263 CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS); 264 265 /* 266 * Send address of word we want to read. 267 */ 268 wb_eeprom_putbyte(sc, addr); 269 270 CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS); 271 272 /* 273 * Start reading bits from EEPROM. 274 */ 275 for (i = 0x8000; i; i >>= 1) { 276 SIO_SET(WB_SIO_EE_CLK); 277 DELAY(100); 278 if (CSR_READ_4(sc, WB_SIO) & WB_SIO_EE_DATAOUT) 279 word |= i; 280 SIO_CLR(WB_SIO_EE_CLK); 281 DELAY(100); 282 } 283 284 /* Turn off EEPROM access mode. */ 285 CSR_WRITE_4(sc, WB_SIO, 0); 286 287 *dest = word; 288 } 289 290 /* 291 * Read a sequence of words from the EEPROM. 292 */ 293 static void 294 wb_read_eeprom(struct wb_softc *sc, caddr_t dest, int off, int cnt) 295 { 296 int i; 297 uint16_t word = 0, *ptr; 298 299 for (i = 0; i < cnt; i++) { 300 wb_eeprom_getword(sc, off + i, &word); 301 ptr = (uint16_t *)(dest + (i * 2)); 302 *ptr = word; 303 } 304 } 305 306 /* 307 * Sync the PHYs by setting data bit and strobing the clock 32 times. 308 */ 309 static void 310 wb_mii_sync(struct wb_softc *sc) 311 { 312 int i; 313 314 SIO_SET(WB_SIO_MII_DIR | WB_SIO_MII_DATAIN); 315 316 for (i = 0; i < 32; i++) { 317 SIO_SET(WB_SIO_MII_CLK); 318 DELAY(1); 319 SIO_CLR(WB_SIO_MII_CLK); 320 DELAY(1); 321 } 322 } 323 324 /* 325 * Clock a series of bits through the MII. 326 */ 327 static void 328 wb_mii_send(struct wb_softc *sc, uint32_t bits, int cnt) 329 { 330 int i; 331 332 SIO_CLR(WB_SIO_MII_CLK); 333 334 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 335 if (bits & i) 336 SIO_SET(WB_SIO_MII_DATAIN); 337 else 338 SIO_CLR(WB_SIO_MII_DATAIN); 339 DELAY(1); 340 SIO_CLR(WB_SIO_MII_CLK); 341 DELAY(1); 342 SIO_SET(WB_SIO_MII_CLK); 343 } 344 } 345 346 /* 347 * Read an PHY register through the MII. 348 */ 349 static int 350 wb_mii_readreg(struct wb_softc *sc, struct wb_mii_frame *frame) 351 { 352 int ack, i; 353 354 crit_enter(); 355 356 /* 357 * Set up frame for RX. 358 */ 359 frame->mii_stdelim = WB_MII_STARTDELIM; 360 frame->mii_opcode = WB_MII_READOP; 361 frame->mii_turnaround = 0; 362 frame->mii_data = 0; 363 364 CSR_WRITE_4(sc, WB_SIO, 0); 365 366 /* 367 * Turn on data xmit. 368 */ 369 SIO_SET(WB_SIO_MII_DIR); 370 371 wb_mii_sync(sc); 372 373 /* 374 * Send command/address info. 375 */ 376 wb_mii_send(sc, frame->mii_stdelim, 2); 377 wb_mii_send(sc, frame->mii_opcode, 2); 378 wb_mii_send(sc, frame->mii_phyaddr, 5); 379 wb_mii_send(sc, frame->mii_regaddr, 5); 380 381 /* Idle bit */ 382 SIO_CLR((WB_SIO_MII_CLK | WB_SIO_MII_DATAIN)); 383 DELAY(1); 384 SIO_SET(WB_SIO_MII_CLK); 385 DELAY(1); 386 387 /* Turn off xmit. */ 388 SIO_CLR(WB_SIO_MII_DIR); 389 /* Check for ack */ 390 SIO_CLR(WB_SIO_MII_CLK); 391 DELAY(1); 392 ack = CSR_READ_4(sc, WB_SIO) & WB_SIO_MII_DATAOUT; 393 SIO_SET(WB_SIO_MII_CLK); 394 DELAY(1); 395 SIO_CLR(WB_SIO_MII_CLK); 396 DELAY(1); 397 SIO_SET(WB_SIO_MII_CLK); 398 DELAY(1); 399 400 /* 401 * Now try reading data bits. If the ack failed, we still 402 * need to clock through 16 cycles to keep the PHY(s) in sync. 403 */ 404 if (ack) { 405 for(i = 0; i < 16; i++) { 406 SIO_CLR(WB_SIO_MII_CLK); 407 DELAY(1); 408 SIO_SET(WB_SIO_MII_CLK); 409 DELAY(1); 410 } 411 goto fail; 412 } 413 414 for (i = 0x8000; i; i >>= 1) { 415 SIO_CLR(WB_SIO_MII_CLK); 416 DELAY(1); 417 if (!ack) { 418 if (CSR_READ_4(sc, WB_SIO) & WB_SIO_MII_DATAOUT) 419 frame->mii_data |= i; 420 DELAY(1); 421 } 422 SIO_SET(WB_SIO_MII_CLK); 423 DELAY(1); 424 } 425 426 fail: 427 428 SIO_CLR(WB_SIO_MII_CLK); 429 DELAY(1); 430 SIO_SET(WB_SIO_MII_CLK); 431 DELAY(1); 432 433 crit_exit(); 434 435 if (ack) 436 return(1); 437 return(0); 438 } 439 440 /* 441 * Write to a PHY register through the MII. 442 */ 443 static int 444 wb_mii_writereg(struct wb_softc *sc, struct wb_mii_frame *frame) 445 { 446 447 crit_enter(); 448 /* 449 * Set up frame for TX. 450 */ 451 452 frame->mii_stdelim = WB_MII_STARTDELIM; 453 frame->mii_opcode = WB_MII_WRITEOP; 454 frame->mii_turnaround = WB_MII_TURNAROUND; 455 456 /* 457 * Turn on data output. 458 */ 459 SIO_SET(WB_SIO_MII_DIR); 460 461 wb_mii_sync(sc); 462 463 wb_mii_send(sc, frame->mii_stdelim, 2); 464 wb_mii_send(sc, frame->mii_opcode, 2); 465 wb_mii_send(sc, frame->mii_phyaddr, 5); 466 wb_mii_send(sc, frame->mii_regaddr, 5); 467 wb_mii_send(sc, frame->mii_turnaround, 2); 468 wb_mii_send(sc, frame->mii_data, 16); 469 470 /* Idle bit. */ 471 SIO_SET(WB_SIO_MII_CLK); 472 DELAY(1); 473 SIO_CLR(WB_SIO_MII_CLK); 474 DELAY(1); 475 476 /* 477 * Turn off xmit. 478 */ 479 SIO_CLR(WB_SIO_MII_DIR); 480 481 crit_exit(); 482 483 return(0); 484 } 485 486 static int 487 wb_miibus_readreg(device_t dev, int phy, int reg) 488 { 489 struct wb_softc *sc = device_get_softc(dev); 490 struct wb_mii_frame frame; 491 492 bzero(&frame, sizeof(frame)); 493 494 frame.mii_phyaddr = phy; 495 frame.mii_regaddr = reg; 496 wb_mii_readreg(sc, &frame); 497 498 return(frame.mii_data); 499 } 500 501 static int 502 wb_miibus_writereg(device_t dev, int phy, int reg, int data) 503 { 504 struct wb_softc *sc = device_get_softc(dev); 505 struct wb_mii_frame frame; 506 507 bzero(&frame, sizeof(frame)); 508 509 frame.mii_phyaddr = phy; 510 frame.mii_regaddr = reg; 511 frame.mii_data = data; 512 513 wb_mii_writereg(sc, &frame); 514 515 return(0); 516 } 517 518 static void 519 wb_miibus_statchg(device_t dev) 520 { 521 struct wb_softc *sc = device_get_softc(dev); 522 struct mii_data *mii; 523 524 mii = device_get_softc(sc->wb_miibus); 525 wb_setcfg(sc, mii->mii_media_active); 526 } 527 528 /* 529 * Program the 64-bit multicast hash filter. 530 */ 531 static void 532 wb_setmulti(struct wb_softc *sc) 533 { 534 struct ifnet *ifp = &sc->arpcom.ac_if; 535 int h = 0, mcnt = 0; 536 uint32_t hashes[2] = { 0, 0 }; 537 struct ifmultiaddr *ifma; 538 uint32_t rxfilt; 539 540 rxfilt = CSR_READ_4(sc, WB_NETCFG); 541 542 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 543 rxfilt |= WB_NETCFG_RX_MULTI; 544 CSR_WRITE_4(sc, WB_NETCFG, rxfilt); 545 CSR_WRITE_4(sc, WB_MAR0, 0xFFFFFFFF); 546 CSR_WRITE_4(sc, WB_MAR1, 0xFFFFFFFF); 547 return; 548 } 549 550 /* first, zot all the existing hash bits */ 551 CSR_WRITE_4(sc, WB_MAR0, 0); 552 CSR_WRITE_4(sc, WB_MAR1, 0); 553 554 /* now program new ones */ 555 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 556 if (ifma->ifma_addr->sa_family != AF_LINK) 557 continue; 558 h = ~ether_crc32_be(LLADDR((struct sockaddr_dl *) 559 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 560 if (h < 32) 561 hashes[0] |= (1 << h); 562 else 563 hashes[1] |= (1 << (h - 32)); 564 mcnt++; 565 } 566 567 if (mcnt) 568 rxfilt |= WB_NETCFG_RX_MULTI; 569 else 570 rxfilt &= ~WB_NETCFG_RX_MULTI; 571 572 CSR_WRITE_4(sc, WB_MAR0, hashes[0]); 573 CSR_WRITE_4(sc, WB_MAR1, hashes[1]); 574 CSR_WRITE_4(sc, WB_NETCFG, rxfilt); 575 } 576 577 /* 578 * The Winbond manual states that in order to fiddle with the 579 * 'full-duplex' and '100Mbps' bits in the netconfig register, we 580 * first have to put the transmit and/or receive logic in the idle state. 581 */ 582 static void 583 wb_setcfg(struct wb_softc *sc, uint32_t media) 584 { 585 int i, restart = 0; 586 587 if (CSR_READ_4(sc, WB_NETCFG) & (WB_NETCFG_TX_ON | WB_NETCFG_RX_ON)) { 588 restart = 1; 589 WB_CLRBIT(sc, WB_NETCFG, (WB_NETCFG_TX_ON | WB_NETCFG_RX_ON)); 590 591 for (i = 0; i < WB_TIMEOUT; i++) { 592 DELAY(10); 593 if ((CSR_READ_4(sc, WB_ISR) & WB_ISR_TX_IDLE) && 594 (CSR_READ_4(sc, WB_ISR) & WB_ISR_RX_IDLE)) 595 break; 596 } 597 598 if (i == WB_TIMEOUT) { 599 if_printf(&sc->arpcom.ac_if, "failed to force tx and " 600 "rx to idle state\n"); 601 } 602 } 603 604 if (IFM_SUBTYPE(media) == IFM_10_T) 605 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_100MBPS); 606 else 607 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_100MBPS); 608 609 if ((media & IFM_GMASK) == IFM_FDX) 610 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_FULLDUPLEX); 611 else 612 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_FULLDUPLEX); 613 614 if (restart) 615 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON | WB_NETCFG_RX_ON); 616 } 617 618 static void 619 wb_reset(struct wb_softc *sc) 620 { 621 int i; 622 struct mii_data *mii; 623 624 CSR_WRITE_4(sc, WB_NETCFG, 0); 625 CSR_WRITE_4(sc, WB_BUSCTL, 0); 626 CSR_WRITE_4(sc, WB_TXADDR, 0); 627 CSR_WRITE_4(sc, WB_RXADDR, 0); 628 629 WB_SETBIT(sc, WB_BUSCTL, WB_BUSCTL_RESET); 630 WB_SETBIT(sc, WB_BUSCTL, WB_BUSCTL_RESET); 631 632 for (i = 0; i < WB_TIMEOUT; i++) { 633 DELAY(10); 634 if ((CSR_READ_4(sc, WB_BUSCTL) & WB_BUSCTL_RESET) == 0) 635 break; 636 } 637 if (i == WB_TIMEOUT) 638 if_printf(&sc->arpcom.ac_if, "reset never completed!\n"); 639 640 /* Wait a little while for the chip to get its brains in order. */ 641 DELAY(1000); 642 643 if (sc->wb_miibus == NULL) 644 return; 645 646 mii = device_get_softc(sc->wb_miibus); 647 if (mii == NULL) 648 return; 649 650 if (mii->mii_instance) { 651 struct mii_softc *miisc; 652 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 653 mii_phy_reset(miisc); 654 } 655 } 656 657 static void 658 wb_fixmedia(struct wb_softc *sc) 659 { 660 struct mii_data *mii; 661 uint32_t media; 662 663 if (sc->wb_miibus == NULL) 664 return; 665 666 mii = device_get_softc(sc->wb_miibus); 667 668 mii_pollstat(mii); 669 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T) { 670 media = mii->mii_media_active & ~IFM_10_T; 671 media |= IFM_100_TX; 672 } else if (IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) { 673 media = mii->mii_media_active & ~IFM_100_TX; 674 media |= IFM_10_T; 675 } else 676 return; 677 678 ifmedia_set(&mii->mii_media, media); 679 } 680 681 /* 682 * Probe for a Winbond chip. Check the PCI vendor and device 683 * IDs against our list and return a device name if we find a match. 684 */ 685 static int wb_probe(device_t dev) 686 { 687 struct wb_type *t; 688 uint16_t vendor, product; 689 690 vendor = pci_get_vendor(dev); 691 product = pci_get_device(dev); 692 693 for (t = wb_devs; t->wb_name != NULL; t++) { 694 if (vendor == t->wb_vid && product == t->wb_did) { 695 device_set_desc(dev, t->wb_name); 696 return(0); 697 } 698 } 699 700 return(ENXIO); 701 } 702 703 /* 704 * Attach the interface. Allocate softc structures, do ifmedia 705 * setup and ethernet/BPF attach. 706 */ 707 static int 708 wb_attach(device_t dev) 709 { 710 u_char eaddr[ETHER_ADDR_LEN]; 711 struct wb_softc *sc; 712 struct ifnet *ifp; 713 int error = 0, rid; 714 715 sc = device_get_softc(dev); 716 callout_init(&sc->wb_stat_timer); 717 718 /* 719 * Handle power management nonsense. 720 */ 721 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 722 uint32_t iobase, membase, irq; 723 724 /* Save important PCI config data. */ 725 iobase = pci_read_config(dev, WB_PCI_LOIO, 4); 726 membase = pci_read_config(dev, WB_PCI_LOMEM, 4); 727 irq = pci_read_config(dev, WB_PCI_INTLINE, 4); 728 729 /* Reset the power state. */ 730 device_printf(dev, "chip is in D%d power mode " 731 "-- setting to D0\n", pci_get_powerstate(dev)); 732 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 733 734 /* Restore PCI config data. */ 735 pci_write_config(dev, WB_PCI_LOIO, iobase, 4); 736 pci_write_config(dev, WB_PCI_LOMEM, membase, 4); 737 pci_write_config(dev, WB_PCI_INTLINE, irq, 4); 738 } 739 740 pci_enable_busmaster(dev); 741 742 rid = WB_RID; 743 sc->wb_res = bus_alloc_resource_any(dev, WB_RES, &rid, RF_ACTIVE); 744 745 if (sc->wb_res == NULL) { 746 device_printf(dev, "couldn't map ports/memory\n"); 747 error = ENXIO; 748 goto fail; 749 } 750 751 sc->wb_btag = rman_get_bustag(sc->wb_res); 752 sc->wb_bhandle = rman_get_bushandle(sc->wb_res); 753 754 /* Allocate interrupt */ 755 rid = 0; 756 sc->wb_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 757 RF_SHAREABLE | RF_ACTIVE); 758 759 if (sc->wb_irq == NULL) { 760 device_printf(dev, "couldn't map interrupt\n"); 761 error = ENXIO; 762 goto fail; 763 } 764 765 /* Save the cache line size. */ 766 sc->wb_cachesize = pci_read_config(dev, WB_PCI_CACHELEN, 4) & 0xFF; 767 768 ifp = &sc->arpcom.ac_if; 769 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 770 771 /* Reset the adapter. */ 772 wb_reset(sc); 773 774 /* 775 * Get station address from the EEPROM. 776 */ 777 wb_read_eeprom(sc, (caddr_t)&eaddr, 0, 3); 778 779 sc->wb_ldata = contigmalloc(sizeof(struct wb_list_data) + 8, M_DEVBUF, 780 M_WAITOK, 0, 0xffffffff, PAGE_SIZE, 0); 781 782 if (sc->wb_ldata == NULL) { 783 device_printf(dev, "no memory for list buffers!\n"); 784 error = ENXIO; 785 goto fail; 786 } 787 788 bzero(sc->wb_ldata, sizeof(struct wb_list_data)); 789 790 ifp->if_softc = sc; 791 ifp->if_mtu = ETHERMTU; 792 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 793 ifp->if_ioctl = wb_ioctl; 794 ifp->if_start = wb_start; 795 ifp->if_watchdog = wb_watchdog; 796 ifp->if_init = wb_init; 797 ifp->if_baudrate = 10000000; 798 ifq_set_maxlen(&ifp->if_snd, WB_TX_LIST_CNT - 1); 799 ifq_set_ready(&ifp->if_snd); 800 801 /* 802 * Do MII setup. 803 */ 804 if (mii_phy_probe(dev, &sc->wb_miibus, 805 wb_ifmedia_upd, wb_ifmedia_sts)) { 806 error = ENXIO; 807 goto fail; 808 } 809 810 /* 811 * Call MI attach routine. 812 */ 813 ether_ifattach(ifp, eaddr); 814 815 error = bus_setup_intr(dev, sc->wb_irq, INTR_TYPE_NET, 816 wb_intr, sc, &sc->wb_intrhand, NULL); 817 818 if (error) { 819 device_printf(dev, "couldn't set up irq\n"); 820 ether_ifdetach(ifp); 821 goto fail; 822 } 823 824 return(0); 825 826 fail: 827 wb_detach(dev); 828 return(error); 829 } 830 831 static int 832 wb_detach(device_t dev) 833 { 834 struct wb_softc *sc = device_get_softc(dev); 835 struct ifnet *ifp = &sc->arpcom.ac_if; 836 837 crit_enter(); 838 839 if (device_is_attached(dev)) { 840 if (bus_child_present(dev)) 841 wb_stop(sc); 842 ether_ifdetach(ifp); 843 } 844 845 if (sc->wb_miibus) 846 device_delete_child(dev, sc->wb_miibus); 847 bus_generic_detach(dev); 848 849 if (sc->wb_intrhand) 850 bus_teardown_intr(dev, sc->wb_irq, sc->wb_intrhand); 851 crit_exit(); 852 if (sc->wb_irq); 853 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->wb_irq); 854 if (sc->wb_res) 855 bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res); 856 if (sc->wb_ldata_ptr) { 857 contigfree(sc->wb_ldata_ptr, sizeof(struct wb_list_data) + 8, 858 M_DEVBUF); 859 } 860 861 return(0); 862 } 863 864 /* 865 * Initialize the transmit descriptors. 866 */ 867 static int 868 wb_list_tx_init(struct wb_softc *sc) 869 { 870 struct wb_chain_data *cd; 871 struct wb_list_data *ld; 872 int i, nexti; 873 874 cd = &sc->wb_cdata; 875 ld = sc->wb_ldata; 876 877 for (i = 0; i < WB_TX_LIST_CNT; i++) { 878 nexti = (i == WB_TX_LIST_CNT - 1) ? 0 : i + 1; 879 cd->wb_tx_chain[i].wb_ptr = &ld->wb_tx_list[i]; 880 cd->wb_tx_chain[i].wb_nextdesc = &cd->wb_tx_chain[nexti]; 881 } 882 883 cd->wb_tx_free = &cd->wb_tx_chain[0]; 884 cd->wb_tx_tail = cd->wb_tx_head = NULL; 885 886 return(0); 887 } 888 889 /* 890 * Initialize the RX descriptors and allocate mbufs for them. Note that 891 * we arrange the descriptors in a closed ring, so that the last descriptor 892 * points back to the first. 893 */ 894 static int 895 wb_list_rx_init(struct wb_softc *sc) 896 { 897 struct wb_chain_data *cd; 898 struct wb_list_data *ld; 899 int i, nexti; 900 901 cd = &sc->wb_cdata; 902 ld = sc->wb_ldata; 903 904 for (i = 0; i < WB_RX_LIST_CNT; i++) { 905 cd->wb_rx_chain[i].wb_ptr = &ld->wb_rx_list[i]; 906 cd->wb_rx_chain[i].wb_buf = &ld->wb_rxbufs[i]; 907 if (wb_newbuf(sc, &cd->wb_rx_chain[i], NULL) == ENOBUFS) 908 return(ENOBUFS); 909 nexti = (WB_RX_LIST_CNT - 1) ? 0 : i + 1; 910 cd->wb_rx_chain[i].wb_nextdesc = &cd->wb_rx_chain[nexti]; 911 ld->wb_rx_list[i].wb_next = vtophys(&ld->wb_rx_list[nexti]); 912 } 913 914 cd->wb_rx_head = &cd->wb_rx_chain[0]; 915 916 return(0); 917 } 918 919 static void 920 wb_bfree(void *arg) 921 { 922 } 923 924 /* 925 * Initialize an RX descriptor and attach an MBUF cluster. 926 */ 927 static int 928 wb_newbuf(struct wb_softc *sc, struct wb_chain_onefrag *c, struct mbuf *m) 929 { 930 struct mbuf *m_new = NULL; 931 932 if (m == NULL) { 933 MGETHDR(m_new, MB_DONTWAIT, MT_DATA); 934 if (m_new == NULL) 935 return(ENOBUFS); 936 937 m_new->m_data = m_new->m_ext.ext_buf = c->wb_buf; 938 m_new->m_flags |= M_EXT; 939 m_new->m_ext.ext_size = m_new->m_pkthdr.len = 940 m_new->m_len = WB_BUFBYTES; 941 m_new->m_ext.ext_free = wb_bfree; 942 m_new->m_ext.ext_ref = wb_bfree; 943 } else { 944 m_new = m; 945 m_new->m_len = m_new->m_pkthdr.len = WB_BUFBYTES; 946 m_new->m_data = m_new->m_ext.ext_buf; 947 } 948 949 m_adj(m_new, sizeof(uint64_t)); 950 951 c->wb_mbuf = m_new; 952 c->wb_ptr->wb_data = vtophys(mtod(m_new, caddr_t)); 953 c->wb_ptr->wb_ctl = WB_RXCTL_RLINK | 1536; 954 c->wb_ptr->wb_status = WB_RXSTAT; 955 956 return(0); 957 } 958 959 /* 960 * A frame has been uploaded: pass the resulting mbuf chain up to 961 * the higher level protocols. 962 */ 963 static void 964 wb_rxeof(struct wb_softc *sc) 965 { 966 struct ifnet *ifp = &sc->arpcom.ac_if; 967 struct mbuf *m, *m0; 968 struct wb_chain_onefrag *cur_rx; 969 int total_len = 0; 970 uint32_t rxstat; 971 972 for (;;) { 973 rxstat = sc->wb_cdata.wb_rx_head->wb_ptr->wb_status; 974 if ((rxstat & WB_RXSTAT_OWN) == 0) 975 break; 976 977 cur_rx = sc->wb_cdata.wb_rx_head; 978 sc->wb_cdata.wb_rx_head = cur_rx->wb_nextdesc; 979 980 m = cur_rx->wb_mbuf; 981 982 if ((rxstat & WB_RXSTAT_MIIERR) || 983 (WB_RXBYTES(cur_rx->wb_ptr->wb_status) < WB_MIN_FRAMELEN) || 984 (WB_RXBYTES(cur_rx->wb_ptr->wb_status) > 1536) || 985 (rxstat & WB_RXSTAT_LASTFRAG) == 0|| 986 (rxstat & WB_RXSTAT_RXCMP) == 0) { 987 ifp->if_ierrors++; 988 wb_newbuf(sc, cur_rx, m); 989 if_printf(ifp, "receiver babbling: possible chip " 990 "bug, forcing reset\n"); 991 wb_fixmedia(sc); 992 wb_reset(sc); 993 wb_init(sc); 994 return; 995 } 996 997 if (rxstat & WB_RXSTAT_RXERR) { 998 ifp->if_ierrors++; 999 wb_newbuf(sc, cur_rx, m); 1000 break; 1001 } 1002 1003 /* No errors; receive the packet. */ 1004 total_len = WB_RXBYTES(cur_rx->wb_ptr->wb_status); 1005 1006 /* 1007 * XXX The Winbond chip includes the CRC with every 1008 * received frame, and there's no way to turn this 1009 * behavior off (at least, I can't find anything in 1010 * the manual that explains how to do it) so we have 1011 * to trim off the CRC manually. 1012 */ 1013 total_len -= ETHER_CRC_LEN; 1014 1015 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 1016 total_len + ETHER_ALIGN, 0, ifp, NULL); 1017 wb_newbuf(sc, cur_rx, m); 1018 if (m0 == NULL) { 1019 ifp->if_ierrors++; 1020 break; 1021 } 1022 m_adj(m0, ETHER_ALIGN); 1023 m = m0; 1024 1025 ifp->if_ipackets++; 1026 (*ifp->if_input)(ifp, m); 1027 } 1028 } 1029 1030 static void 1031 wb_rxeoc(struct wb_softc *sc) 1032 { 1033 wb_rxeof(sc); 1034 1035 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 1036 CSR_WRITE_4(sc, WB_RXADDR, vtophys(&sc->wb_ldata->wb_rx_list[0])); 1037 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 1038 if (CSR_READ_4(sc, WB_ISR) & WB_RXSTATE_SUSPEND) 1039 CSR_WRITE_4(sc, WB_RXSTART, 0xFFFFFFFF); 1040 } 1041 1042 /* 1043 * A frame was downloaded to the chip. It's safe for us to clean up 1044 * the list buffers. 1045 */ 1046 static void 1047 wb_txeof(struct wb_softc *sc) 1048 { 1049 struct ifnet *ifp = &sc->arpcom.ac_if; 1050 struct wb_chain *cur_tx; 1051 1052 /* Clear the timeout timer. */ 1053 ifp->if_timer = 0; 1054 1055 if (sc->wb_cdata.wb_tx_head == NULL) 1056 return; 1057 1058 /* 1059 * Go through our tx list and free mbufs for those 1060 * frames that have been transmitted. 1061 */ 1062 while(sc->wb_cdata.wb_tx_head->wb_mbuf != NULL) { 1063 uint32_t txstat; 1064 1065 cur_tx = sc->wb_cdata.wb_tx_head; 1066 txstat = WB_TXSTATUS(cur_tx); 1067 1068 if ((txstat & WB_TXSTAT_OWN) || txstat == WB_UNSENT) 1069 break; 1070 1071 if (txstat & WB_TXSTAT_TXERR) { 1072 ifp->if_oerrors++; 1073 if (txstat & WB_TXSTAT_ABORT) 1074 ifp->if_collisions++; 1075 if (txstat & WB_TXSTAT_LATECOLL) 1076 ifp->if_collisions++; 1077 } 1078 1079 ifp->if_collisions += (txstat & WB_TXSTAT_COLLCNT) >> 3; 1080 1081 ifp->if_opackets++; 1082 m_freem(cur_tx->wb_mbuf); 1083 cur_tx->wb_mbuf = NULL; 1084 1085 if (sc->wb_cdata.wb_tx_head == sc->wb_cdata.wb_tx_tail) { 1086 sc->wb_cdata.wb_tx_head = NULL; 1087 sc->wb_cdata.wb_tx_tail = NULL; 1088 break; 1089 } 1090 1091 sc->wb_cdata.wb_tx_head = cur_tx->wb_nextdesc; 1092 } 1093 } 1094 1095 /* 1096 * TX 'end of channel' interrupt handler. 1097 */ 1098 static void 1099 wb_txeoc(struct wb_softc *sc) 1100 { 1101 struct ifnet *ifp = &sc->arpcom.ac_if; 1102 1103 ifp->if_timer = 0; 1104 1105 if (sc->wb_cdata.wb_tx_head == NULL) { 1106 ifp->if_flags &= ~IFF_OACTIVE; 1107 sc->wb_cdata.wb_tx_tail = NULL; 1108 } else if (WB_TXOWN(sc->wb_cdata.wb_tx_head) == WB_UNSENT) { 1109 WB_TXOWN(sc->wb_cdata.wb_tx_head) = WB_TXSTAT_OWN; 1110 ifp->if_timer = 5; 1111 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 1112 } 1113 } 1114 1115 static void 1116 wb_intr(void *arg) 1117 { 1118 struct wb_softc *sc = arg; 1119 struct ifnet *ifp = &sc->arpcom.ac_if; 1120 uint32_t status; 1121 1122 if ((ifp->if_flags & IFF_UP) == 0) 1123 return; 1124 1125 /* Disable interrupts. */ 1126 CSR_WRITE_4(sc, WB_IMR, 0x00000000); 1127 1128 for (;;) { 1129 status = CSR_READ_4(sc, WB_ISR); 1130 if (status) 1131 CSR_WRITE_4(sc, WB_ISR, status); 1132 1133 if ((status & WB_INTRS) == 0) 1134 break; 1135 1136 if ((status & WB_ISR_RX_NOBUF) || (status & WB_ISR_RX_ERR)) { 1137 ifp->if_ierrors++; 1138 wb_reset(sc); 1139 if (status & WB_ISR_RX_ERR) 1140 wb_fixmedia(sc); 1141 wb_init(sc); 1142 continue; 1143 } 1144 1145 if (status & WB_ISR_RX_OK) 1146 wb_rxeof(sc); 1147 1148 if (status & WB_ISR_RX_IDLE) 1149 wb_rxeoc(sc); 1150 1151 if (status & WB_ISR_TX_OK) 1152 wb_txeof(sc); 1153 1154 if (status & WB_ISR_TX_NOBUF) 1155 wb_txeoc(sc); 1156 1157 if (status & WB_ISR_TX_IDLE) { 1158 wb_txeof(sc); 1159 if (sc->wb_cdata.wb_tx_head != NULL) { 1160 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1161 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 1162 } 1163 } 1164 1165 if (status & WB_ISR_TX_UNDERRUN) { 1166 ifp->if_oerrors++; 1167 wb_txeof(sc); 1168 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1169 /* Jack up TX threshold */ 1170 sc->wb_txthresh += WB_TXTHRESH_CHUNK; 1171 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_THRESH); 1172 WB_SETBIT(sc, WB_NETCFG, WB_TXTHRESH(sc->wb_txthresh)); 1173 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1174 } 1175 1176 if (status & WB_ISR_BUS_ERR) { 1177 wb_reset(sc); 1178 wb_init(sc); 1179 } 1180 } 1181 1182 /* Re-enable interrupts. */ 1183 CSR_WRITE_4(sc, WB_IMR, WB_INTRS); 1184 1185 if (!ifq_is_empty(&ifp->if_snd)) 1186 wb_start(ifp); 1187 } 1188 1189 static void 1190 wb_tick(void *xsc) 1191 { 1192 struct wb_softc *sc = xsc; 1193 struct mii_data *mii = device_get_softc(sc->wb_miibus); 1194 1195 crit_enter(); 1196 1197 mii_tick(mii); 1198 1199 callout_reset(&sc->wb_stat_timer, hz, wb_tick, sc); 1200 1201 crit_exit(); 1202 } 1203 1204 /* 1205 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1206 * pointers to the fragment pointers. 1207 */ 1208 static int 1209 wb_encap(struct wb_softc *sc, struct wb_chain *c, struct mbuf *m_head) 1210 { 1211 struct wb_desc *f = NULL; 1212 struct mbuf *m; 1213 int frag, total_len; 1214 1215 /* 1216 * Start packing the mbufs in this chain into 1217 * the fragment pointers. Stop when we run out 1218 * of fragments or hit the end of the mbuf chain. 1219 */ 1220 total_len = 0; 1221 1222 for (m = m_head, frag = 0; m != NULL; m = m->m_next) { 1223 if (m->m_len != 0) { 1224 if (frag == WB_MAXFRAGS) 1225 break; 1226 total_len += m->m_len; 1227 f = &c->wb_ptr->wb_frag[frag]; 1228 f->wb_ctl = WB_TXCTL_TLINK | m->m_len; 1229 if (frag == 0) { 1230 f->wb_ctl |= WB_TXCTL_FIRSTFRAG; 1231 f->wb_status = 0; 1232 } else { 1233 f->wb_status = WB_TXSTAT_OWN; 1234 } 1235 f->wb_next = vtophys(&c->wb_ptr->wb_frag[frag + 1]); 1236 f->wb_data = vtophys(mtod(m, vm_offset_t)); 1237 frag++; 1238 } 1239 } 1240 1241 /* 1242 * Handle special case: we used up all 16 fragments, 1243 * but we have more mbufs left in the chain. Copy the 1244 * data into an mbuf cluster. Note that we don't 1245 * bother clearing the values in the other fragment 1246 * pointers/counters; it wouldn't gain us anything, 1247 * and would waste cycles. 1248 */ 1249 if (m != NULL) { 1250 struct mbuf *m_new = NULL; 1251 1252 MGETHDR(m_new, MB_DONTWAIT, MT_DATA); 1253 if (m_new == NULL) 1254 return(1); 1255 if (m_head->m_pkthdr.len > MHLEN) { 1256 MCLGET(m_new, MB_DONTWAIT); 1257 if ((m_new->m_flags & M_EXT) == 0) { 1258 m_freem(m_new); 1259 return(1); 1260 } 1261 } 1262 m_copydata(m_head, 0, m_head->m_pkthdr.len, 1263 mtod(m_new, caddr_t)); 1264 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 1265 m_freem(m_head); 1266 m_head = m_new; 1267 f = &c->wb_ptr->wb_frag[0]; 1268 f->wb_status = 0; 1269 f->wb_data = vtophys(mtod(m_new, caddr_t)); 1270 f->wb_ctl = total_len = m_new->m_len; 1271 f->wb_ctl |= WB_TXCTL_TLINK|WB_TXCTL_FIRSTFRAG; 1272 frag = 1; 1273 } 1274 1275 if (total_len < WB_MIN_FRAMELEN) { 1276 f = &c->wb_ptr->wb_frag[frag]; 1277 f->wb_ctl = WB_MIN_FRAMELEN - total_len; 1278 f->wb_data = vtophys(&sc->wb_cdata.wb_pad); 1279 f->wb_ctl |= WB_TXCTL_TLINK; 1280 f->wb_status = WB_TXSTAT_OWN; 1281 frag++; 1282 } 1283 1284 c->wb_mbuf = m_head; 1285 c->wb_lastdesc = frag - 1; 1286 WB_TXCTL(c) |= WB_TXCTL_LASTFRAG; 1287 WB_TXNEXT(c) = vtophys(&c->wb_nextdesc->wb_ptr->wb_frag[0]); 1288 1289 return(0); 1290 } 1291 1292 /* 1293 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1294 * to the mbuf data regions directly in the transmit lists. We also save a 1295 * copy of the pointers since the transmit list fragment pointers are 1296 * physical addresses. 1297 */ 1298 static void 1299 wb_start(struct ifnet *ifp) 1300 { 1301 struct wb_softc *sc = ifp->if_softc; 1302 struct mbuf *m_head = NULL; 1303 struct wb_chain *cur_tx = NULL, *start_tx; 1304 1305 /* 1306 * Check for an available queue slot. If there are none, 1307 * punt. 1308 */ 1309 if (sc->wb_cdata.wb_tx_free->wb_mbuf != NULL) { 1310 ifp->if_flags |= IFF_OACTIVE; 1311 return; 1312 } 1313 1314 start_tx = sc->wb_cdata.wb_tx_free; 1315 1316 while (sc->wb_cdata.wb_tx_free->wb_mbuf == NULL) { 1317 m_head = ifq_dequeue(&ifp->if_snd); 1318 if (m_head == NULL) 1319 break; 1320 1321 /* Pick a descriptor off the free list. */ 1322 cur_tx = sc->wb_cdata.wb_tx_free; 1323 sc->wb_cdata.wb_tx_free = cur_tx->wb_nextdesc; 1324 1325 /* Pack the data into the descriptor. */ 1326 wb_encap(sc, cur_tx, m_head); 1327 1328 if (cur_tx != start_tx) 1329 WB_TXOWN(cur_tx) = WB_TXSTAT_OWN; 1330 1331 BPF_MTAP(ifp, cur_tx->wb_mbuf); 1332 } 1333 1334 /* 1335 * If there are no packets queued, bail. 1336 */ 1337 if (cur_tx == NULL) 1338 return; 1339 1340 /* 1341 * Place the request for the upload interrupt 1342 * in the last descriptor in the chain. This way, if 1343 * we're chaining several packets at once, we'll only 1344 * get an interupt once for the whole chain rather than 1345 * once for each packet. 1346 */ 1347 WB_TXCTL(cur_tx) |= WB_TXCTL_FINT; 1348 cur_tx->wb_ptr->wb_frag[0].wb_ctl |= WB_TXCTL_FINT; 1349 sc->wb_cdata.wb_tx_tail = cur_tx; 1350 1351 if (sc->wb_cdata.wb_tx_head == NULL) { 1352 sc->wb_cdata.wb_tx_head = start_tx; 1353 WB_TXOWN(start_tx) = WB_TXSTAT_OWN; 1354 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 1355 } else { 1356 /* 1357 * We need to distinguish between the case where 1358 * the own bit is clear because the chip cleared it 1359 * and where the own bit is clear because we haven't 1360 * set it yet. The magic value WB_UNSET is just some 1361 * ramdomly chosen number which doesn't have the own 1362 * bit set. When we actually transmit the frame, the 1363 * status word will have _only_ the own bit set, so 1364 * the txeoc handler will be able to tell if it needs 1365 * to initiate another transmission to flush out pending 1366 * frames. 1367 */ 1368 WB_TXOWN(start_tx) = WB_UNSENT; 1369 } 1370 1371 /* 1372 * Set a timeout in case the chip goes out to lunch. 1373 */ 1374 ifp->if_timer = 5; 1375 } 1376 1377 static void 1378 wb_init(void *xsc) 1379 { 1380 struct wb_softc *sc = xsc; 1381 struct ifnet *ifp = &sc->arpcom.ac_if; 1382 int i; 1383 struct mii_data *mii; 1384 1385 crit_enter(); 1386 1387 mii = device_get_softc(sc->wb_miibus); 1388 1389 /* 1390 * Cancel pending I/O and free all RX/TX buffers. 1391 */ 1392 wb_stop(sc); 1393 wb_reset(sc); 1394 1395 sc->wb_txthresh = WB_TXTHRESH_INIT; 1396 1397 /* 1398 * Set cache alignment and burst length. 1399 */ 1400 #ifdef foo 1401 CSR_WRITE_4(sc, WB_BUSCTL, WB_BUSCTL_CONFIG); 1402 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_THRESH); 1403 WB_SETBIT(sc, WB_NETCFG, WB_TXTHRESH(sc->wb_txthresh)); 1404 #endif 1405 1406 CSR_WRITE_4(sc, WB_BUSCTL, WB_BUSCTL_MUSTBEONE | WB_BUSCTL_ARBITRATION); 1407 WB_SETBIT(sc, WB_BUSCTL, WB_BURSTLEN_16LONG); 1408 switch(sc->wb_cachesize) { 1409 case 32: 1410 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_32LONG); 1411 break; 1412 case 16: 1413 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_16LONG); 1414 break; 1415 case 8: 1416 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_8LONG); 1417 break; 1418 case 0: 1419 default: 1420 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_NONE); 1421 break; 1422 } 1423 1424 /* This doesn't tend to work too well at 100Mbps. */ 1425 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_EARLY_ON); 1426 1427 /* Init our MAC address */ 1428 for (i = 0; i < ETHER_ADDR_LEN; i++) 1429 CSR_WRITE_1(sc, WB_NODE0 + i, sc->arpcom.ac_enaddr[i]); 1430 1431 /* Init circular RX list. */ 1432 if (wb_list_rx_init(sc) == ENOBUFS) { 1433 if_printf(ifp, "initialization failed: no " 1434 "memory for rx buffers\n"); 1435 wb_stop(sc); 1436 crit_exit(); 1437 return; 1438 } 1439 1440 /* Init TX descriptors. */ 1441 wb_list_tx_init(sc); 1442 1443 /* If we want promiscuous mode, set the allframes bit. */ 1444 if (ifp->if_flags & IFF_PROMISC) 1445 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ALLPHYS); 1446 else 1447 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ALLPHYS); 1448 1449 /* 1450 * Set capture broadcast bit to capture broadcast frames. 1451 */ 1452 if (ifp->if_flags & IFF_BROADCAST) 1453 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_BROAD); 1454 else 1455 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_BROAD); 1456 1457 /* 1458 * Program the multicast filter, if necessary. 1459 */ 1460 wb_setmulti(sc); 1461 1462 /* 1463 * Load the address of the RX list. 1464 */ 1465 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 1466 CSR_WRITE_4(sc, WB_RXADDR, vtophys(&sc->wb_ldata->wb_rx_list[0])); 1467 1468 /* 1469 * Enable interrupts. 1470 */ 1471 CSR_WRITE_4(sc, WB_IMR, WB_INTRS); 1472 CSR_WRITE_4(sc, WB_ISR, 0xFFFFFFFF); 1473 1474 /* Enable receiver and transmitter. */ 1475 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 1476 CSR_WRITE_4(sc, WB_RXSTART, 0xFFFFFFFF); 1477 1478 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1479 CSR_WRITE_4(sc, WB_TXADDR, vtophys(&sc->wb_ldata->wb_tx_list[0])); 1480 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1481 1482 mii_mediachg(mii); 1483 1484 ifp->if_flags |= IFF_RUNNING; 1485 ifp->if_flags &= ~IFF_OACTIVE; 1486 1487 crit_exit(); 1488 1489 callout_reset(&sc->wb_stat_timer, hz, wb_tick, sc); 1490 } 1491 1492 /* 1493 * Set media options. 1494 */ 1495 static int 1496 wb_ifmedia_upd(struct ifnet *ifp) 1497 { 1498 struct wb_softc *sc = ifp->if_softc; 1499 1500 if (ifp->if_flags & IFF_UP) 1501 wb_init(sc); 1502 1503 return(0); 1504 } 1505 1506 /* 1507 * Report current media status. 1508 */ 1509 static void 1510 wb_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1511 { 1512 struct wb_softc *sc = ifp->if_softc; 1513 struct mii_data *mii = device_get_softc(sc->wb_miibus); 1514 1515 mii_pollstat(mii); 1516 ifmr->ifm_active = mii->mii_media_active; 1517 ifmr->ifm_status = mii->mii_media_status; 1518 } 1519 1520 static int 1521 wb_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr) 1522 { 1523 struct wb_softc *sc = ifp->if_softc; 1524 struct mii_data *mii; 1525 struct ifreq *ifr = (struct ifreq *) data; 1526 int error = 0; 1527 1528 crit_enter(); 1529 1530 switch(command) { 1531 case SIOCSIFFLAGS: 1532 if (ifp->if_flags & IFF_UP) 1533 wb_init(sc); 1534 else if (ifp->if_flags & IFF_RUNNING) 1535 wb_stop(sc); 1536 error = 0; 1537 break; 1538 case SIOCADDMULTI: 1539 case SIOCDELMULTI: 1540 wb_setmulti(sc); 1541 error = 0; 1542 break; 1543 case SIOCGIFMEDIA: 1544 case SIOCSIFMEDIA: 1545 mii = device_get_softc(sc->wb_miibus); 1546 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1547 break; 1548 default: 1549 error = ether_ioctl(ifp, command, data); 1550 break; 1551 } 1552 1553 crit_exit(); 1554 1555 return(error); 1556 } 1557 1558 static void 1559 wb_watchdog(struct ifnet *ifp) 1560 { 1561 struct wb_softc *sc = ifp->if_softc; 1562 1563 ifp->if_oerrors++; 1564 if_printf(ifp, "watchdog timeout\n"); 1565 #ifdef foo 1566 if ((wb_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT) == 0) 1567 if_printf(ifp, "no carrier - transceiver cable problem?\n"); 1568 #endif 1569 wb_stop(sc); 1570 wb_reset(sc); 1571 wb_init(sc); 1572 1573 if (!ifq_is_empty(&ifp->if_snd)) 1574 wb_start(ifp); 1575 } 1576 1577 /* 1578 * Stop the adapter and free any mbufs allocated to the 1579 * RX and TX lists. 1580 */ 1581 static void 1582 wb_stop(struct wb_softc *sc) 1583 { 1584 struct ifnet *ifp = &sc->arpcom.ac_if; 1585 int i; 1586 1587 ifp->if_timer = 0; 1588 1589 callout_stop(&sc->wb_stat_timer); 1590 1591 WB_CLRBIT(sc, WB_NETCFG, (WB_NETCFG_RX_ON | WB_NETCFG_TX_ON)); 1592 CSR_WRITE_4(sc, WB_IMR, 0x00000000); 1593 CSR_WRITE_4(sc, WB_TXADDR, 0x00000000); 1594 CSR_WRITE_4(sc, WB_RXADDR, 0x00000000); 1595 1596 /* 1597 * Free data in the RX lists. 1598 */ 1599 for (i = 0; i < WB_RX_LIST_CNT; i++) { 1600 if (sc->wb_cdata.wb_rx_chain[i].wb_mbuf != NULL) { 1601 m_freem(sc->wb_cdata.wb_rx_chain[i].wb_mbuf); 1602 sc->wb_cdata.wb_rx_chain[i].wb_mbuf = NULL; 1603 } 1604 } 1605 bzero(&sc->wb_ldata->wb_rx_list, sizeof(sc->wb_ldata->wb_rx_list)); 1606 1607 /* 1608 * Free the TX list buffers. 1609 */ 1610 for (i = 0; i < WB_TX_LIST_CNT; i++) { 1611 if (sc->wb_cdata.wb_tx_chain[i].wb_mbuf != NULL) { 1612 m_freem(sc->wb_cdata.wb_tx_chain[i].wb_mbuf); 1613 sc->wb_cdata.wb_tx_chain[i].wb_mbuf = NULL; 1614 } 1615 } 1616 1617 bzero(&sc->wb_ldata->wb_tx_list, sizeof(sc->wb_ldata->wb_tx_list)); 1618 1619 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1620 } 1621 1622 /* 1623 * Stop all chip I/O so that the kernel's probe routines don't 1624 * get confused by errant DMAs when rebooting. 1625 */ 1626 static void 1627 wb_shutdown(device_t dev) 1628 { 1629 struct wb_softc *sc = device_get_softc(dev); 1630 1631 wb_stop(sc); 1632 } 1633