1 /*- 2 * Copyright (c) 1998, 1999 Scott Mitchell 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $Id: if_xereg.h,v 1.5 1999/05/20 21:53:58 scott Exp $ 27 * $FreeBSD: src/sys/dev/xe/if_xereg.h,v 1.6 2003/10/14 22:51:35 rsm Exp $ 28 * $DragonFly: src/sys/dev/netif/xe/if_xereg.h,v 1.3 2005/11/20 10:16:56 sephe Exp $ 29 */ 30 #ifndef DEV_XE_IF_XEREG_H 31 #define DEV_XE_IF_XEREG_H 32 33 /* 34 * Register definitions for Xircom PCMCIA Ethernet controllers, based on 35 * Rev. B of the "Dingo" 10/100 controller used in Xircom CEM56 and RealPort 36 * Ethernet/modem cards. The Dingo can be configured to be register 37 * compatible with the "Mohawk" 10/100 controller used in Xircom CE3 cards 38 * (also some Intel and Compaq OEM versions of the CE3). The older 10Mbps CE2 39 * cards seem to use earlier revisions of the same device. Some registers and 40 * bits below are marked 'CE2 only'; these are used by Werner Koch's xirc2ps 41 * driver that was originally for the CE2 but, according to the spec, aren't 42 * present on the Dingo. They often seem to relate to operation on coax 43 * cables, which Mohawk can do in theory (it has the SSI interface) so they 44 * _might_ also work on Mohawk. I've also noted the few registers that are 45 * specific to Dingo. 46 * 47 * As far as I can tell, the Dingo is basically a Mohawk device with a few 48 * registers and support for a second PCMCIA function (the modem) added. In 49 * Dingo mode the SSI (non-MII) PHY interface of the Mohawk is not available. 50 * The CE2 chip is most likely a Mohawk without the MII and definitely with a 51 * slightly different register set. 52 * 53 * In all cases, the controller uses a paged model of register access. The 54 * first eight registers are always the same, the function of the second eight 55 * is selected by the value in the Page Register (reg 0x01). 56 * 57 * References: 58 * 1. Dingo External Reference Specification, Revision B. Xircom Inc., 59 * Thousand Oaks, California. August 1998. Available under licence from 60 * Xircom, http://www.xircom.com/ 61 * 2. ML6692 100BASE-TX Physical Layer with MII specification. MicroLinear 62 * Corp, San Jose, California. May 1997. Available for download from 63 * http://www.microlinear.com/ 64 * 3. DP83840 10/100 Mb/s Ethernet Physical Layer specification. National 65 * Semiconductor Corp., Arlington, Texas. March 1997. Available for 66 * download from http://www.ns.com/ 67 * 4. Werner Koch's xirc2ps driver for Linux, for all the CE2 and CE3 frobs 68 * that aren't documented in the Xircom spec. Available for download from 69 * http://www.d.shuttle.de/isil/xircom/xirc2ps.html 70 */ 71 72 /******************* 73 * PCMCIA registers 74 *******************/ 75 76 /* 77 * These are probably Dingo-specific, but you won't need them unless you have 78 * a CEM card that needs a bit of hackery to get the Ethernet function to 79 * operate. All addresses are in card attribute space. 80 */ 81 #define DINGO_CIS 0x0000 /* Start of CIS tuples */ 82 #define DINGO_ETH 0x0800 /* Ethernet configuration registers */ 83 #define DINGO_COR 0x0820 /* Dingo configuration option registers */ 84 #define DINGO_2ND 0x0840 /* 2nd function configuration registers */ 85 86 87 /* 88 * Ethernet configuration registers 89 */ 90 #define DINGO_ECOR (DINGO_ETH+0) /* Ethernet Configuration Option Register */ 91 #define DINGO_ECSR (DINGO_ETH+2) /* Ethernet Configuration Status Register */ 92 #define DINGO_EBAR0 (DINGO_ETH+10) /* Ethernet Base Address Register bits 7:4 (3:0 always 0) */ 93 #define DINGO_EBAR1 (DINGO_ETH+12) /* Ethernet Base Address Register bits 15:8 */ 94 95 /* DINGO_ECOR bits */ 96 #define DINGO_ECOR_ETH_ENABLE 0x01 /* 1 = Enable Ethernet part of adapter */ 97 #define DINGO_ECOR_IOB_ENABLE 0x02 /* 1 = Enable EBAR, else use INDEX bits */ 98 #define DINGO_ECOR_INT_ENABLE 0x04 /* 1 = Enable Ethernet interrupts */ 99 #define DINGO_ECOR_IOB_INDEX 0x18 /* 00 = 0x300; 01 = 0x310; 10 = 0x320; 11 = no IO base */ 100 #define DINGO_ECOR_IOB_SHIFT 0x03 101 #define DINGO_ECOR_IRQ_STSCHG 0x20 /* 1 = Route interrupts to -STSCHG pin, else use -INT pin */ 102 #define DINGO_ECOR_IRQ_LEVEL 0x40 /* 1 = Level-triggered interrupts, else edge-triggered */ 103 #define DINGO_ECOR_SRESET 0x80 /* 1 = Soft reset Ethernet adpater. Must write to 0 */ 104 105 /* DINGO_ECSR bits */ 106 #define DINGO_ECSR_INT_ACK 0x01 /* 1 = Host must acknowledge interrupts (Clear ECSR_INT bit) */ 107 #define DINGO_ECSR_INT 0x02 /* 1 = Interrupt service requested */ 108 #define DINGO_ECSR_POWER_DOWN 0x04 /* 1 = Power down Ethernet adapter */ 109 110 /* 111 * EBAR0/EBAR1 set the I/O base address of the Ethernet adapter when 112 * ECOR_IOB_ENABLE is set. 12 significant bits. 113 */ 114 115 116 /* 117 * Dingo configuration registers 118 */ 119 #define DINGO_DCOR0 (DINGO_COR+0) /* Dingo Configuration Options Register 0 */ 120 #define DINGO_DCOR1 (DINGO_COR+2) /* Dingo Configuration Options Register 1 */ 121 #define DINGO_DCOR2 (DINGO_COR+4) /* Dingo Configuration Options Register 2 */ 122 #define DINGO_DCOR3 (DINGO_COR+6) /* Dingo Configuration Options Register 3 */ 123 #define DINGO_DCOR4 (DINGO_COR+8) /* Dingo Configuration Options Register 4 */ 124 125 /* DINGO_DCOR0 bits */ 126 #define DINGO_DCOR0_SF_INT 0x01 /* 1 = Enable 2ndF interrupts (alternate to SFCOR:2) */ 127 #define DINGO_DCOR0_DECODE 0x04 /* 1 = Decode 2ndF interrupts in Dingo, else in 2ndF */ 128 #define DINGO_DCOR0_BUS 0x08 /* 1 = 2ndF bus is ISA, else PCMCIA */ 129 #define DINGO_DCOR0_LED3_POWER 0x10 /* 1 = Drive LED3 line from SFCSR:2 */ 130 #define DINGO_DCOR0_LED3_RESET 0x20 /* 1 = Drive LED3 line from SFCOR:7 */ 131 #define DINGO_DCOR0_MR_POWER 0x40 /* 1 = Drive MRESET line from SFCSR:2 */ 132 #define DINGO_DCOR0_MR_RESET 0x80 /* 1 = Drive MRESET line from SFCOR:7 */ 133 134 /* DINGO_DCOR1 bits */ 135 #define DINGO_DCOR1_INT_STSCHG 0x01 /* 1 = Route 2ndF interrupts to -STSCHG (alternate to SFCOR:5) */ 136 #define DINGO_DCOR1_MSTSCHG 0x02 /* 1 = Route 2ndF -MSTSCHG line to -STSCHG */ 137 #define DINGO_DCOR1_EEDIO 0x04 /* 1 = Use EEDIO pin as data line 6 to 2ndF */ 138 #define DINGO_DCOR1_INT_LEVEL 0x08 /* 1 = Force level-triggered interrupts from 2ndF */ 139 #define DINGO_DCOR1_SHADOW_CSR 0x10 /* Reserved, always write 0 */ 140 #define DINGO_DCOR1_SHADOW_IOB 0x20 /* Reserved, always write 0 */ 141 #define DINGO_DCOR1_CSR_WAIT 0xC0 /* Reserved, always write 0 */ 142 #define DINGO_DCOR1_CSR_SHIFT 0x06 143 144 /* DINGO_DCOR2 bits */ 145 #define DINGO_DCOR2_SHM_BASE 0x0f /* Bits 15-12 of Ethernet shared memory window */ 146 #define DINGO_DCOR2_SHM_SHIFT 0x00 147 #define DINGO_DCOR2_SHADOW_COR 0x10 /* Reserved, always write 0 */ 148 149 /* 150 * DCOR3/DCOR4 configure Dingo to assert -IOIS16 on any access to each pair of 151 * ports in the range SFIOB+0 .. SFIOB+31. Each pair can be set individually, 152 * eg. DCOR3:0 enables this function on ports SFIOB+0 and SFIOB+1. 153 */ 154 155 156 /* 157 * Second function configuration registers 158 */ 159 #define DINGO_SFCOR (DINGO_2ND+0) /* 2nd Function Configuration Option Register */ 160 #define DINGO_SFCSR (DINGO_2ND+2) /* 2nd Function Configuration Status Register */ 161 #define DINGO_SFBAR0 (DINGO_2ND+10) /* 2nd Function Base Address Register bits 7:0 */ 162 #define DINGO_SFBAR1 (DINGO_2ND+12) /* 2nd Function Base Address Register bits 15:8 */ 163 #define DINGO_SFILR (DINGO_2ND+18) /* 2nd Function I/O Limit Register */ 164 165 /* DINGO_SFCOR bits */ 166 #define DINGO_SFCOR_SF_ENABLE 0x01 /* 1 = Enable second fuction */ 167 #define DINGO_SFCOR_IOB_ENABLE 0x02 /* 1 = Enable SFBAR, else use COM_SELECT bits */ 168 #define DINGO_SFCOR_INT_ENABLE 0x04 /* 1 = Enable second function interrupts */ 169 #define DINGO_SFCOR_COM_SELECT 0x18 /* 00 = 0x3f8; 01 = 0x2f8; 10 = 0x3e8; 11 = 0x2e8 */ 170 #define DINGO_SFCOR_COM_SHIFT 0x03 171 #define DINGO_SFCOR_IRQ_STSCHG 0x20 /* 1 = Route interrupts to -STSCHG pin, else use -INT pin */ 172 #define DINGO_SFCOR_IRQ_LEVEL 0x40 /* 1 = Level-triggered interrupts, else edge-triggered */ 173 #define DINGO_SFCOR_SRESET 0x80 /* 1 = Soft reset second function. Must write to 0 */ 174 175 /* DINGO_SFCSR bits */ 176 #define DINGO_SFCSR_INT_ACK 0x01 /* 1 = Host must acknowledge interrupts (Clear SFCSR_INT bit) */ 177 #define DINGO_SFCSR_INT 0x02 /* 1 = Interrupt service requested */ 178 #define DINGO_SFCSR_POWER_DOWN 0x04 /* 1 = Power down second function */ 179 180 /* 181 * SFBAR0/SFBAR1 set the I/O base address of the second function when 182 * SFCOR_IOB_ENABLE is set. 16 significant bits. 183 */ 184 185 /* 186 * SFILR is a bitmap of address lines 7:0 decoded by the second function 187 * device. Eg. a device with 16 ports should write 0x0f to this register. 188 */ 189 190 191 192 /******************************** 193 * Ethernet controller registers 194 ********************************/ 195 196 /* 197 * Common registers (available from any register page) 198 * 199 * Note: The EDP is actually 32 bits wide, occupying registers 2-5. In PCMCIA 200 * operation we can only access 16 bits at once, through registers 4 & 5. 201 */ 202 #define XE_CR 0x00 /* Command register (write) */ 203 #define XE_ESR 0x00 /* Ethernet status register (read) */ 204 #define XE_PR 0x01 /* Page select register */ 205 #define XE_EDP 0x04 /* Ethernet data port */ 206 #define XE_ISR 0x06 /* Ethernet interrupt status register (read) */ 207 #define XE_GIR 0x07 /* Global interrupt register (Dingo only) */ 208 209 /* XE_CR bits */ 210 #define XE_CR_TX_PACKET 0x01 /* Transmit packet */ 211 #define XE_CR_SOFT_RESET 0x02 /* Software reset */ 212 #define XE_CR_ENABLE_INTR 0x04 /* Enable interrupts */ 213 #define XE_CR_FORCE_INTR 0x08 /* Force an interrupt */ 214 #define XE_CR_CLEAR_FIFO 0x10 /* Clear FIFO after transmit overrun */ 215 #define XE_CR_CLEAR_OVERRUN 0x20 /* Clear receive overrun condition */ 216 #define XE_CR_RESTART_TX 0x40 /* Restart TX after 16 collisions or TX underrun */ 217 218 /* XE_ESR bits */ 219 #define XE_ESR_FULL_PACKET_RX 0x01 /* At least one full packet received */ 220 #define XE_ESR_PART_PACKET_RX 0x02 /* At least 64 bytes of packet received */ 221 #define XE_ESR_REJECT_PACKET 0x04 /* Partial packet rejected */ 222 #define XE_ESR_TX_PENDING 0x08 /* At least one packet waiting to transmit */ 223 #define XE_ESR_BAD_POLARITY 0x10 /* Bad cable polarity? (CE2 only) */ 224 #define XE_ESR_MEDIA_SELECT 0x20 /* SSI(?) media select: 1 = Twisted pair; 0 = AUI */ 225 226 /* XE_ISR bits */ 227 #define XE_ISR_TX_OVERFLOW 0x01 /* No space in transmit buffer */ 228 #define XE_ISR_TX_PACKET 0x02 /* Packet sent successfully */ 229 #define XE_ISR_MAC_INTR 0x04 /* Some kind of MAC interrupt happened */ 230 #define XE_ISR_RX_EARLY 0x10 /* Incoming packet in early receive mode */ 231 #define XE_ISR_RX_PACKET 0x20 /* Complete packet received successfully */ 232 #define XE_ISR_RX_REJECT 0x40 /* Partial incoming packet rejected by MAC */ 233 #define XE_ISR_FORCE_INTR 0x80 /* Interrupt forced */ 234 235 /* XE_GIR bits */ 236 #define XE_GIR_ETH_IRQ 0x01 /* Ethernet IRQ pending */ 237 #define XE_GIR_ETH_MASK 0x02 /* 1 = Mask Ethernet interrupts to host */ 238 #define XE_GIR_SF_IRQ 0x04 /* Second function IRQ pending */ 239 #define XE_GIR_SF_MASK 0x08 /* 1 = Mask second function interrupts to host */ 240 241 242 /* 243 * Page 0 registers 244 */ 245 #define XE_TSO 0x08 /* Transmit space open (17 bits) */ 246 #define XE_TRS 0x0a /* Transmit reservation size (CE2 only, removed in rev. 1) */ 247 #define XE_DO 0x0c /* Data offset register (13 bits/3 flags, write) */ 248 #define XE_RSR 0x0c /* Receive status register (read) */ 249 #define XE_TPR 0x0d /* Packets transmitted register (read) */ 250 #define XE_RBC 0x0e /* Received byte count (13 bits/3 flags, read) */ 251 252 /* XE_DO bits */ 253 #define XE_DO_OFFSET 0x1fff /* First byte fetched when CHANGE_OFFSET issued */ 254 #define XE_DO_OFFSET_SHIFT 0x00 255 #define XE_DO_CHANGE_OFFSET 0x2000 /* Flush RX FIFO, start fetching from OFFSET */ 256 #define XE_DO_SHARED_MEM 0x4000 /* Enable shared memory mode */ 257 #define XE_DO_SKIP_RX_PACKET 0x8000 /* Skip to next packet in buffer memory */ 258 259 /* XE_RSR bits */ 260 #define XE_RSR_PHYS_PACKET 0x01 /* 1 = Physical packet, 0 = Multicast packet */ 261 #define XE_RSR_BCAST_PACKET 0x02 /* Broadcast packet */ 262 #define XE_RSR_LONG_PACKET 0x04 /* Packet >1518 bytes */ 263 #define XE_RSR_ADDR_MATCH 0x08 /* Packet matched one of our node addresses */ 264 #define XE_RSR_ALIGN_ERROR 0x10 /* Bad alignment? (CE2 only) */ 265 #define XE_RSR_CRC_ERROR 0x20 /* Incorrect CRC */ 266 #define XE_RSR_RX_OK 0x80 /* No errors on received packet */ 267 268 /* XE_RBC bits */ 269 #define XE_RBC_BYTE_COUNT 0x1fff /* Bytes received for current packet */ 270 #define XE_RBC_COUNT_SHIFT 0x00 271 #define XE_RBC_FULL_PACKET_RX 0x2000 /* These mirror bits 2:0 of ESR, if ECR:7 is set */ 272 #define XE_RBC_PART_PACKET_RX 0x4000 273 #define XE_RBC_REJECT_PACKET 0x8000 274 275 276 /* 277 * Page 1 registers 278 */ 279 #define XE_IMR0 0x0c /* Interrupt mask register 0 */ 280 #define XE_IMR1 0x0d /* Interrupt mask register 1 (CE2 only) */ 281 #define XE_ECR 0x0e /* Ethernet configuration register */ 282 283 /* XE_IMR0 bits */ 284 #define XE_IMR0_TX_OVERFLOW 0x01 /* Masks for bits in ISR */ 285 #define XE_IMR0_TX_PACKET 0x02 286 #define XE_IMR0_MAC_INTR 0x04 287 #define XE_IMR0_TX_RESGRANT 0x08 /* Tx reservation granted (CE2) */ 288 #define XE_IMR0_RX_EARLY 0x10 289 #define XE_IMR0_RX_PACKET 0x20 290 #define XE_IMR0_RX_REJECT 0x40 291 #define XE_IMR0_FORCE_INTR 0x80 292 293 /* XE_IMR1 bits */ 294 #define XE_IMR1_TX_UNDERRUN 0x01 295 296 /* XE_ECR bits */ 297 #define XE_ECR_EARLY_TX 0x01 /* Enable early transmit mode */ 298 #define XE_ECR_EARLY_RX 0x02 /* Enable early receive mode */ 299 #define XE_ECR_FULL_DUPLEX 0x04 /* Enable full-duplex (disable collision detection) */ 300 #define XE_ECR_LONG_TPCABLE 0x08 /* CE2 only */ 301 #define XE_ECR_NO_POL_COL 0x10 /* CE2 only */ 302 #define XE_ECR_NO_LINK_PULSE 0x20 /* Don't check/send link pulses (not 10BT compliant) */ 303 #define XE_ECR_NO_AUTO_TX 0x40 /* CE2 only */ 304 #define XE_ECR_SOFT_COMPAT 0x80 /* Map ESR bits 2:0 to RBC bits 15:13 */ 305 306 307 /* 308 * Page 2 registers 309 */ 310 #define XE_RBS 0x08 /* Receive buffer start (16 bits) */ 311 #define XE_LED 0x0a /* LED control register */ 312 #define XE_LED3 0x0b /* LED3 control register */ 313 #define XE_MSR 0x0c /* Misc. setup register (Mohawk specific register?) */ 314 #define XE_GPR2 0x0d /* General purpose register 2 */ 315 316 /* 317 * LED function selection: 318 * 000 - Disabled 319 * 001 - Collision activity 320 * 010 - !Collision activity 321 * 011 - 10Mbit link detected 322 * 100 - 100Mbit link detected 323 * 101 - 10/100Mbit link detected 324 * 110 - Automatic assertion 325 * 111 - Transmit activity 326 */ 327 328 /* XE_LED bits */ 329 #define XE_LED_LED0_MASK 0x07 /* LED0 function selection */ 330 #define XE_LED_LED0_SHIFT 0x00 331 #define XE_LED_LED1_MASK 0x38 /* LED1 function selection */ 332 #define XE_LED_LED1_SHIFT 0x03 333 #define XE_LED_LED0_RX 0x40 /* Add receive activity to LED0 */ 334 #define XE_LED_LED1_RX 0x80 /* Add receive activity to LED1 */ 335 336 /* XE_LED3 bits */ 337 #define XE_LED3_MASK 0x07 /* LED3 function selection */ 338 #define XE_LED3_SHIFT 0x00 339 #define XE_LED3_RX 0x40 /* Add receive activity to LED3 */ 340 341 /* XE_MSR bits */ 342 #define XE_MSR_128K_SRAM 0x01 /* Select 128K SRAM */ 343 #define XE_MSR_RBS_BIT16 0x02 /* Bit 16 of RBS (only useful with big SRAM) */ 344 #define XE_MSR_MII_SELECT 0x08 /* Select MII instead of SSI interface */ 345 #define XE_MSR_HASH_TABLE 0x20 /* Enable hash table filtering */ 346 347 /* XE_GPR2 bits */ 348 #define XE_GPR2_GP3_OUT 0x01 /* Value written to GP3 line */ 349 #define XE_GPR2_GP4_OUT 0x02 /* Value written to GP4 line */ 350 #define XE_GPR2_GP3_SELECT 0x04 /* 1 = GP3 is output, 0 = GP3 is input */ 351 #define XE_GPR2_GP4_SELECT 0x08 /* 1 = GP4 is output, 0 = GP3 is input */ 352 #define XE_GPR2_GP3_IN 0x10 /* Value read from GP3 line */ 353 #define XE_GPR2_GP4_IN 0x20 /* Value read from GP4 line */ 354 355 356 /* 357 * Page 3 registers 358 */ 359 #define XE_TPT 0x0a /* Transmit packet threshold (13 bits) */ 360 361 362 /* 363 * Page 4 registers 364 */ 365 #define XE_GPR0 0x08 /* General purpose register 0 */ 366 #define XE_GPR1 0x09 /* General purpose register 1 */ 367 #define XE_BOV 0x0a /* Bonding version register (read) */ 368 #define XE_EES 0x0b /* EEPROM control register */ 369 #define XE_LMA 0x0c /* Local memory address (CE2 only) */ 370 #define XE_LMD 0x0e /* Local memory data (CE2 only) */ 371 372 /* XE_GPR0 bits */ 373 #define XE_GPR0_GP1_OUT 0x01 /* Value written to GP1 line */ 374 #define XE_GPR0_GP2_OUT 0x02 /* Value wirtten to GP2 line */ 375 #define XE_GPR0_GP1_SELECT 0x04 /* 1 = GP1 is output, 0 = GP1 is input */ 376 #define XE_GPR0_GP2_SELECT 0x08 /* 1 = GP2 is output, 0 = GP2 is input */ 377 #define XE_GPR0_GP1_IN 0x10 /* Value read from GP1 line */ 378 #define XE_GPR0_GP2_IN 0x20 /* Value read from GP2 line */ 379 380 /* XE_GPR1 bits */ 381 #define XE_GPR1_POWER_DOWN 0x01 /* 0 = Power down analog section */ 382 #define XE_GPR1_AIC 0x04 /* AIC bit (CE2 only) */ 383 384 /* XE_BOV values */ 385 #define XE_BOV_DINGO 0x55 /* Dingo in Dingo mode */ 386 #define XE_BOV_MOHAWK 0x41 /* Original Mohawk */ 387 #define XE_BOV_MOHAWK_REV1 0x45 /* Rev. 1 Mohawk, or Dingo in Mohawk mode */ 388 #define XE_BOV_CEM28 0x11 /* CEM28 */ 389 390 /* XE_EES bits */ 391 #define XE_EES_SCL_OUTPUT 0x01 /* Value written to SCL line, when MANUAL_ROM set */ 392 #define XE_EES_SDA_OUTPUT 0x02 /* Value written to SDA line, when MANUAL_ROM set */ 393 #define XE_EES_SDA_INPUT 0x04 /* Value read from SDA line */ 394 #define XE_EES_SDA_TRISTATE 0x08 /* 1 = SDA is output, 0 = SDA is input */ 395 #define XE_EES_MANUAL_ROM 0x20 /* Enable manual contro of serial EEPROM */ 396 397 398 /* 399 * Page 5 registers (all read only) 400 */ 401 #define XE_CRHA 0x08 /* Current Rx host address (16 bits) */ 402 #define XE_RHSA 0x0a /* Rx host start address (16 bits) */ 403 #define XE_RNSA 0x0c /* Rx network start address (16 bits) */ 404 #define XE_CRNA 0x0e /* Current Rx network address (16 bits) */ 405 406 407 /* 408 * Page 6 registers (all read only) 409 */ 410 #define XE_CTHA 0x08 /* Current Tx host address (16 bits) */ 411 #define XE_THSA 0x0a /* Tx host start address (16 bits) */ 412 #define XE_TNSA 0x0c /* Tx network statr address (16 bits) */ 413 #define XE_CTNA 0x0e /* Current Tx network address (16 bits) */ 414 415 416 /* 417 * Page 8 registers (all read only) 418 */ 419 #define XE_THBC 0x08 /* Tx host byte count (16 bits) */ 420 #define XE_THPS 0x0a /* Tx host packet size (16 bits) */ 421 #define XE_TNBC 0x0c /* Tx network byte count (16 bits) */ 422 #define XE_TNPS 0x0e /* Tx network packet size (16 bits) */ 423 424 425 /* 426 * Page 0x10 registers (all read only) 427 */ 428 #define XE_DINGOID 0x08 /* Dingo ID register (16 bits) (Dingo only) */ 429 #define XE_RevID 0x0a /* Dingo revision ID (16 bits) (Dingo only) */ 430 #define XE_VendorID 0x0c /* Dingo vendor ID (16 bits) (Dingo only) */ 431 432 /* Values for the above registers */ 433 #define XE_DINGOID_DINGO3 0x444b /* In both Dingo and Mohawk modes */ 434 #define XE_RevID_DINGO3 0x0001 435 #define XE_VendorID_DINGO3 0x0041 436 437 438 /* 439 * Page 0x40 registers 440 */ 441 #define XE_CMD0 0x08 /* MAC Command register (write) */ 442 #define XE_RST0 0x09 /* Receive status register */ 443 #define XE_TXST0 0x0b /* Transmit status register 0 */ 444 #define XE_TXST1 0x0c /* Transmit status register 1 */ 445 #define XE_RX0Msk 0x0d /* Receive status mask register */ 446 #define XE_TX0Msk 0x0e /* Transmit status 0 mask register */ 447 #define XE_TX1Msk 0x0f /* Transmit status 1 mask register */ 448 449 /* CMD0 bits */ 450 #define XE_CMD0_TX 0x01 /* CE2 only */ 451 #define XE_CMD0_RX_ENABLE 0x04 /* Enable receiver */ 452 #define XE_CMD0_RX_DISABLE 0x08 /* Disable receiver */ 453 #define XE_CMD0_ABORT 0x10 /* CE2 only */ 454 #define XE_CMD0_ONLINE 0x20 /* Take MAC online */ 455 #define XE_CMD0_ACK_INTR 0x40 /* CE2 only */ 456 #define XE_CMD0_OFFLINE 0x80 /* Take MAC offline */ 457 458 /* RST0 bits */ 459 #define XE_RST0_LONG_PACKET 0x02 /* Packet received with >1518 and <8184 bytes */ 460 #define XE_RST0_CRC_ERROR 0x08 /* Packet received with incorrect CRC */ 461 #define XE_RST0_RX_OVERRUN 0x10 /* Receiver overrun, byte(s) dropped */ 462 #define XE_RST0_RX_ENABLE 0x20 /* Receiver enabled */ 463 #define XE_RST0_RX_ABORT 0x40 /* Receive aborted: CRC, FIFO overrun or addr mismatch */ 464 #define XE_RST0_RX_OK 0x80 /* Complete packet received OK */ 465 466 /* TXST0 bits */ 467 #define XE_TXST0_NO_CARRIER 0x01 /* Lost carrier. Only valid in 10Mbit half-duplex */ 468 #define XE_TXST0_16_COLLISIONS 0x02 /* Packet aborted after 16 collisions */ 469 #define XE_TXST0_TX_UNDERRUN 0x08 /* MAC ran out of data to send */ 470 #define XE_TXST0_LATE_COLLISION 0x10 /* Collision later than 512 bits */ 471 #define XE_TXST0_SQE_FAIL 0x20 /* SQE test failed. */ 472 #define XE_TXST0_TX_ABORT 0x40 /* Transmit aborted: collisions, underrun or overrun */ 473 #define XE_TXST0_TX_OK 0x80 /* Complete packet sent OK */ 474 475 /* TXST1 bits */ 476 #define XE_TXST1_RETRY_COUNT 0x0f /* Collision counter for current packet */ 477 #define XE_TXST1_LINK_STATUS 0x10 /* Valid link status */ 478 479 /* RX0Msk bits */ 480 #define XE_RX0M_MP 0x01 /* Multicast packet? (CE2 only) */ 481 #define XE_RX0M_LONG_PACKET 0x02 /* Masks for bits in RXST0 */ 482 #define XE_RX0M_ALIGN_ERROR 0x04 /* Alignment error (CE2 only) */ 483 #define XE_RX0M_CRC_ERROR 0x08 484 #define XE_RX0M_RX_OVERRUN 0x10 485 #define XE_RX0M_RX_ABORT 0x40 486 #define XE_RX0M_RX_OK 0x80 487 488 /* TX0Msk bits */ 489 #define XE_TX0M_NO_CARRIER 0x01 /* Masks for bits in TXST0 */ 490 #define XE_TX0M_16_COLLISIONS 0x02 491 #define XE_TX0M_TX_UNDERRUN 0x08 492 #define XE_TX0M_LATE_COLLISION 0x10 493 #define XE_TX0M_SQE_FAIL 0x20 494 #define XE_TX0M_TX_ABORT 0x40 495 #define XE_TX0M_TX_OK 0x80 496 497 /* TX1Msk bits */ 498 #define XE_TX1M_PKTDEF 0x20 499 500 501 /* 502 * Page 0x42 registers 503 */ 504 #define XE_SWC0 0x08 /* Software configuration 0 */ 505 #define XE_SWC1 0x09 /* Software configuration 1 */ 506 #define XE_BOC 0x0a /* Back-off configuration */ 507 #define XE_TCD 0x0b /* Transmit collision deferral */ 508 509 /* SWC0 bits */ 510 #define XE_SWC0_LOOPBACK_ENABLE 0x01 /* Enable loopback operation */ 511 #define XE_SWC0_LOOPBACK_SOURCE 0x02 /* 1 = Transceiver, 0 = MAC */ 512 #define XE_SWC0_ACCEPT_ERROR 0x04 /* Accept otherwise OK packets with CRC errors */ 513 #define XE_SWC0_ACCEPT_SHORT 0x08 /* Accept otherwise OK packets that are too short */ 514 #define XE_SWC0_NO_SRC_INSERT 0x20 /* Disable source insertion (CE2) */ 515 #define XE_SWC0_NO_CRC_INSERT 0x40 /* Don't add CRC to outgoing packets */ 516 517 /* SWC1 bits */ 518 #define XE_SWC1_IA_ENABLE 0x01 /* Enable individual address filters */ 519 #define XE_SWC1_ALLMULTI 0x02 /* Accept all multicast packets */ 520 #define XE_SWC1_PROMISCUOUS 0x04 /* Accept all non-multicast packets */ 521 #define XE_SWC1_BCAST_DISABLE 0x08 /* Reject broadcast packets */ 522 #define XE_SWC1_MEDIA_SELECT 0x40 /* AUI media select (Mohawk only) */ 523 #define XE_SWC1_AUTO_MEDIA 0x80 /* Auto media select (Mohawk only) */ 524 525 526 /* 527 * Page 0x44 registers (CE2 only) 528 */ 529 #define XE_TDR0 0x08 /* Time domain reflectometry register 0 */ 530 #define XE_TDR1 0x09 /* Time domain reflectometry register 1 */ 531 #define XE_RXC0 0x0a /* Receive byte count low */ 532 #define XE_RXC1 0x0b /* Receive byte count high */ 533 534 535 /* 536 * Page 0x45 registers (CE2 only) 537 */ 538 #define XE_REV 0x0f /* Revision (read) */ 539 540 541 /* 542 * Page 0x50-0x57: Individual address 0-9 543 * 544 * Used to filter incoming packets by matching against individual node 545 * addresses. If IA matching is enabled (SWC1, bit0) any incoming packet with 546 * a destination matching one of these 10 addresses will be received. IA0 is 547 * always enabled and usually matches the card's unique address. 548 * 549 * Addresses are stored LSB first, ie. IA00 (reg. 8 on page 0x50) contains the 550 * LSB of IA0, and so on. The data is stored contiguously, in that addresses 551 * can be broken across page boundaries. That is: 552 * 553 * Reg: 50/8 50/9 50/a 50/b 50/c 50/d 50/e 50/f 51/8 51/9 ... 57/a 57/b 554 * IA00 IA01 IA02 IA03 IA04 IA05 IA10 IA11 IA12 IA13 ... IA94 IA95 555 */ 556 557 /* 558 * Page 0x58: Multicast hash table filter 559 * 560 * In case the 10 individual addresses aren't enough, we also have a multicast 561 * hash filter, enabled through MSR:5. The most significant six bits of the 562 * CRC on each incoming packet are reversed and used as an index into the 64 563 * bits of the hash table. If the appropriate bit is set the packet it 564 * received, although higher layers may still need to filter it out. The CRC 565 * calculation is as follows: 566 * 567 * crc = 0xffffffff; 568 * poly = 0x04c11db6; 569 * for (i = 0; i < 6; i++) { 570 * current = mcast_addr[i]; 571 * for (k = 1; k <= 8; k++) { 572 * if (crc & 0x80000000); 573 * crc31 = 0x01; 574 * else 575 * crc31 = 0; 576 * bit = crc31 ^ (current & 0x01); 577 * crc <<= 1; 578 * current >>= 1; 579 * if (bit) 580 * crc = (crc ^ poly)|1 581 * } 582 * } 583 */ 584 585 586 587 /**************** 588 * MII registers 589 ****************/ 590 591 /* 592 * Basic MII-compliant PHY register definitions. According to the Dingo spec, 593 * PHYs from (at least) MicroLinear, National Semiconductor, ICS, TDK and 594 * Quality Semiconductor have been used. These apparently all come up with 595 * PHY ID 0x00 unless the "interceptor module" on the Dingo 3 is in use. With 596 * the interceptor enabled, the PHY is faked up to look like an ICS unit with 597 * ID 0x16. The interceptor can be enabled/disabled in software. 598 * 599 * The ML6692 (and maybe others) doesn't have a 10Mbps mode -- this is handled 600 * by an internal 10Mbps transceiver that we know nothing about... some cards 601 * seem to work with the MII in 10Mbps mode, so I guess some PHYs must support 602 * it. The question is, how can you figure out which one you have? Just to 603 * add to the fun there are also 10Mbps _only_ Mohawk/Dingo cards. Aaargh! 604 */ 605 606 /* 607 * Masks for the MII-related bits in GPR2 608 */ 609 #define XE_MII_CLK XE_GPR2_GP3_OUT 610 #define XE_MII_DIR XE_GPR2_GP4_SELECT 611 #define XE_MII_WRD XE_GPR2_GP4_OUT 612 #define XE_MII_RDD XE_GPR2_GP4_IN 613 614 /* 615 * MII PHY ID register values 616 */ 617 #define PHY_ID_ML6692 0x0000 /* MicroLinear ML6692? Or unknown */ 618 #define PHY_ID_ICS1890 0x0015 /* ICS1890 */ 619 #define PHY_ID_QS6612 0x0181 /* Quality QS6612 */ 620 #define PHY_ID_DP83840 0x2000 /* National DP83840 */ 621 622 /* 623 * MII command (etc) bit strings. 624 */ 625 #define XE_MII_STARTDELIM 0x01 626 #define XE_MII_READOP 0x02 627 #define XE_MII_WRITEOP 0x01 628 #define XE_MII_TURNAROUND 0x02 629 630 /* 631 * PHY registers. 632 */ 633 #define PHY_BMCR 0x00 /* Basic Mode Control Register */ 634 #define PHY_BMSR 0x01 /* Basic Mode Status Register */ 635 #define PHY_ID1 0x02 /* PHY ID 1 */ 636 #define PHY_ID2 0x03 /* PHY ID 2 */ 637 #define PHY_ANAR 0x04 /* Auto-Negotiation Advertisment Register */ 638 #define PHY_LPAR 0x05 /* Auto-Negotiation Link Partner Ability Register */ 639 #define PHY_ANER 0x06 /* Auto-Negotiation Expansion Register */ 640 641 /* BMCR bits */ 642 #define PHY_BMCR_RESET 0x8000 /* Soft reset PHY. Self-clearing */ 643 #define PHY_BMCR_LOOPBK 0x4000 /* Enable loopback */ 644 #define PHY_BMCR_SPEEDSEL 0x2000 /* 1=100Mbps, 0=10Mbps */ 645 #define PHY_BMCR_AUTONEGENBL 0x1000 /* Auto-negotiation enabled */ 646 #define PHY_BMCR_ISOLATE 0x0400 /* Isolate ML6692 from MII */ 647 #define PHY_BMCR_AUTONEGRSTR 0x0200 /* Restart auto-negotiation. Self-clearing */ 648 #define PHY_BMCR_DUPLEX 0x0100 /* Full duplex operation */ 649 #define PHY_BMCR_COLLTEST 0x0080 /* Enable collision test */ 650 651 /* BMSR bits */ 652 #define PHY_BMSR_100BT4 0x8000 /* 100Base-T4 capable */ 653 #define PHY_BMSR_100BTXFULL 0x4000 /* 100Base-TX full duplex capable */ 654 #define PHY_BMSR_100BTXHALF 0x2000 /* 100Base-TX half duplex capable */ 655 #define PHY_BMSR_10BTFULL 0x1000 /* 10Base-T full duplex capable */ 656 #define PHY_BMSR_10BTHALF 0x0800 /* 10Base-T half duplex capable */ 657 #define PHY_BMSR_AUTONEGCOMP 0x0020 /* Auto-negotiation complete */ 658 #define PHY_BMSR_CANAUTONEG 0x0008 /* Auto-negotiation supported */ 659 #define PHY_BMSR_LINKSTAT 0x0004 /* Link is up */ 660 #define PHY_BMSR_EXTENDED 0x0001 /* Extended register capabilities */ 661 662 /* ANAR bits */ 663 #define PHY_ANAR_NEXTPAGE 0x8000 /* Additional link code word pages */ 664 #define PHY_ANAR_TLRFLT 0x2000 /* Remote wire fault detected */ 665 #define PHY_ANAR_100BT4 0x0200 /* 100Base-T4 capable */ 666 #define PHY_ANAR_100BTXFULL 0x0100 /* 100Base-TX full duplex capable */ 667 #define PHY_ANAR_100BTXHALF 0x0080 /* 100Base-TX half duplex capable */ 668 #define PHY_ANAR_10BTFULL 0x0040 /* 10Base-T full duplex capable */ 669 #define PHY_ANAR_10BTHALF 0x0020 /* 10Base-T half duplex capable */ 670 #define PHY_ANAR_PROTO4 0x0010 /* Protocol selection (00001 = 802.3) */ 671 #define PHY_ANAR_PROTO3 0x0008 672 #define PHY_ANAR_PROTO2 0x0004 673 #define PHY_ANAR_PROTO1 0x0002 674 #define PHY_ANAR_PROTO0 0x0001 675 #define PHY_ANAR_8023 PHY_ANAR_PROTO0 676 #define PHY_ANAR_DINGO PHY_ANAR_100BT+PHY_ANAR_10BT_FD+PHY_ANAR_10BT+PHY_ANAR_8023 677 #define PHY_ANAR_MOHAWK PHY_ANAR_100BT+PHY_ANAR_10BT_FD+PHY_ANAR_10BT+PHY_ANAR_8023 678 679 /* LPAR bits */ 680 #define PHY_LPAR_NEXTPAGE 0x8000 /* Additional link code word pages */ 681 #define PHY_LPAR_LPACK 0x4000 /* Link partner acknowledged receipt */ 682 #define PHY_LPAR_TLRFLT 0x2000 /* Remote wire fault detected */ 683 #define PHY_LPAR_100BT4 0x0200 /* 100Base-T4 capable */ 684 #define PHY_LPAR_100BTXFULL 0x0100 /* 100Base-TX full duplex capable */ 685 #define PHY_LPAR_100BTXHALF 0x0080 /* 100Base-TX half duplex capable */ 686 #define PHY_LPAR_10BTFULL 0x0040 /* 10Base-T full duplex capable */ 687 #define PHY_LPAR_10BTHALF 0x0020 /* 10Base-T half duplex capable */ 688 #define PHY_LPAR_PROTO4 0x0010 /* Protocol selection (00001 = 802.3) */ 689 #define PHY_LPAR_PROTO3 0x0008 690 #define PHY_LPAR_PROTO2 0x0004 691 #define PHY_LPAR_PROTO1 0x0002 692 #define PHY_LPAR_PROTO0 0x0001 693 694 /* ANER bits */ 695 #define PHY_ANER_MLFAULT 0x0010 /* More than one link is up! */ 696 #define PHY_ANER_LPNPABLE 0x0008 /* Link partner supports next page */ 697 #define PHY_ANER_NPABLE 0x0004 /* Local port supports next page */ 698 #define PHY_ANER_PAGERX 0x0002 /* Page received */ 699 #define PHY_ANER_LPAUTONEG 0x0001 /* Link partner can auto-negotiate */ 700 701 #endif /* DEV_XE_IF_XEREG_H */ 702