1 /* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: src/sys/pci/if_xl.c,v 1.72.2.28 2003/10/08 06:01:57 murray Exp $ 33 * $DragonFly: src/sys/dev/netif/xl/if_xl.c,v 1.30 2005/07/13 17:03:00 joerg Exp $ 34 */ 35 36 /* 37 * 3Com 3c90x Etherlink XL PCI NIC driver 38 * 39 * Supports the 3Com "boomerang", "cyclone" and "hurricane" PCI 40 * bus-master chips (3c90x cards and embedded controllers) including 41 * the following: 42 * 43 * 3Com 3c900-TPO 10Mbps/RJ-45 44 * 3Com 3c900-COMBO 10Mbps/RJ-45,AUI,BNC 45 * 3Com 3c905-TX 10/100Mbps/RJ-45 46 * 3Com 3c905-T4 10/100Mbps/RJ-45 47 * 3Com 3c900B-TPO 10Mbps/RJ-45 48 * 3Com 3c900B-COMBO 10Mbps/RJ-45,AUI,BNC 49 * 3Com 3c900B-TPC 10Mbps/RJ-45,BNC 50 * 3Com 3c900B-FL 10Mbps/Fiber-optic 51 * 3Com 3c905B-COMBO 10/100Mbps/RJ-45,AUI,BNC 52 * 3Com 3c905B-TX 10/100Mbps/RJ-45 53 * 3Com 3c905B-FL/FX 10/100Mbps/Fiber-optic 54 * 3Com 3c905C-TX 10/100Mbps/RJ-45 (Tornado ASIC) 55 * 3Com 3c980-TX 10/100Mbps server adapter (Hurricane ASIC) 56 * 3Com 3c980C-TX 10/100Mbps server adapter (Tornado ASIC) 57 * 3Com 3cSOHO100-TX 10/100Mbps/RJ-45 (Hurricane ASIC) 58 * 3Com 3c450-TX 10/100Mbps/RJ-45 (Tornado ASIC) 59 * 3Com 3c555 10/100Mbps/RJ-45 (MiniPCI, Laptop Hurricane) 60 * 3Com 3c556 10/100Mbps/RJ-45 (MiniPCI, Hurricane ASIC) 61 * 3Com 3c556B 10/100Mbps/RJ-45 (MiniPCI, Hurricane ASIC) 62 * 3Com 3c575TX 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC) 63 * 3Com 3c575B 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC) 64 * 3Com 3c575C 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC) 65 * 3Com 3cxfem656 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC) 66 * 3Com 3cxfem656b 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC) 67 * 3Com 3cxfem656c 10/100Mbps/RJ-45 (Cardbus, Tornado ASIC) 68 * Dell Optiplex GX1 on-board 3c918 10/100Mbps/RJ-45 69 * Dell on-board 3c920 10/100Mbps/RJ-45 70 * Dell Precision on-board 3c905B 10/100Mbps/RJ-45 71 * Dell Latitude laptop docking station embedded 3c905-TX 72 * 73 * Written by Bill Paul <wpaul@ctr.columbia.edu> 74 * Electrical Engineering Department 75 * Columbia University, New York City 76 */ 77 78 /* 79 * The 3c90x series chips use a bus-master DMA interface for transfering 80 * packets to and from the controller chip. Some of the "vortex" cards 81 * (3c59x) also supported a bus master mode, however for those chips 82 * you could only DMA packets to/from a contiguous memory buffer. For 83 * transmission this would mean copying the contents of the queued mbuf 84 * chain into an mbuf cluster and then DMAing the cluster. This extra 85 * copy would sort of defeat the purpose of the bus master support for 86 * any packet that doesn't fit into a single mbuf. 87 * 88 * By contrast, the 3c90x cards support a fragment-based bus master 89 * mode where mbuf chains can be encapsulated using TX descriptors. 90 * This is similar to other PCI chips such as the Texas Instruments 91 * ThunderLAN and the Intel 82557/82558. 92 * 93 * The "vortex" driver (if_vx.c) happens to work for the "boomerang" 94 * bus master chips because they maintain the old PIO interface for 95 * backwards compatibility, but starting with the 3c905B and the 96 * "cyclone" chips, the compatibility interface has been dropped. 97 * Since using bus master DMA is a big win, we use this driver to 98 * support the PCI "boomerang" chips even though they work with the 99 * "vortex" driver in order to obtain better performance. 100 */ 101 102 #include <sys/param.h> 103 #include <sys/systm.h> 104 #include <sys/sockio.h> 105 #include <sys/endian.h> 106 #include <sys/mbuf.h> 107 #include <sys/kernel.h> 108 #include <sys/socket.h> 109 #include <sys/thread2.h> 110 111 #include <net/if.h> 112 #include <net/ifq_var.h> 113 #include <net/if_arp.h> 114 #include <net/ethernet.h> 115 #include <net/if_dl.h> 116 #include <net/if_media.h> 117 #include <net/vlan/if_vlan_var.h> 118 119 #include <net/bpf.h> 120 121 #include <machine/bus_memio.h> 122 #include <machine/bus_pio.h> 123 #include <machine/bus.h> 124 #include <machine/resource.h> 125 #include <sys/bus.h> 126 #include <sys/rman.h> 127 128 #include "../mii_layer/mii.h" 129 #include "../mii_layer/miivar.h" 130 131 #include <bus/pci/pcireg.h> 132 #include <bus/pci/pcivar.h> 133 134 /* "controller miibus0" required. See GENERIC if you get errors here. */ 135 #include "miibus_if.h" 136 137 #include "if_xlreg.h" 138 139 #define XL905B_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 140 141 /* 142 * Various supported device vendors/types and their names. 143 */ 144 static struct xl_type xl_devs[] = { 145 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10BT, 146 "3Com 3c900-TPO Etherlink XL" }, 147 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10BT_COMBO, 148 "3Com 3c900-COMBO Etherlink XL" }, 149 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10_100BT, 150 "3Com 3c905-TX Fast Etherlink XL" }, 151 { TC_VENDORID, TC_DEVICEID_BOOMERANG_100BT4, 152 "3Com 3c905-T4 Fast Etherlink XL" }, 153 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT, 154 "3Com 3c900B-TPO Etherlink XL" }, 155 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT_COMBO, 156 "3Com 3c900B-COMBO Etherlink XL" }, 157 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT_TPC, 158 "3Com 3c900B-TPC Etherlink XL" }, 159 { TC_VENDORID, TC_DEVICEID_CYCLONE_10FL, 160 "3Com 3c900B-FL Etherlink XL" }, 161 { TC_VENDORID, TC_DEVICEID_HURRICANE_10_100BT, 162 "3Com 3c905B-TX Fast Etherlink XL" }, 163 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100BT4, 164 "3Com 3c905B-T4 Fast Etherlink XL" }, 165 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100FX, 166 "3Com 3c905B-FX/SC Fast Etherlink XL" }, 167 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100_COMBO, 168 "3Com 3c905B-COMBO Fast Etherlink XL" }, 169 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT, 170 "3Com 3c905C-TX Fast Etherlink XL" }, 171 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT_920B, 172 "3Com 3c920B-EMB Integrated Fast Etherlink XL" }, 173 { TC_VENDORID, TC_DEVICEID_HURRICANE_10_100BT_SERV, 174 "3Com 3c980 Fast Etherlink XL" }, 175 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT_SERV, 176 "3Com 3c980C Fast Etherlink XL" }, 177 { TC_VENDORID, TC_DEVICEID_HURRICANE_SOHO100TX, 178 "3Com 3cSOHO100-TX OfficeConnect" }, 179 { TC_VENDORID, TC_DEVICEID_TORNADO_HOMECONNECT, 180 "3Com 3c450-TX HomeConnect" }, 181 { TC_VENDORID, TC_DEVICEID_HURRICANE_555, 182 "3Com 3c555 Fast Etherlink XL" }, 183 { TC_VENDORID, TC_DEVICEID_HURRICANE_556, 184 "3Com 3c556 Fast Etherlink XL" }, 185 { TC_VENDORID, TC_DEVICEID_HURRICANE_556B, 186 "3Com 3c556B Fast Etherlink XL" }, 187 { TC_VENDORID, TC_DEVICEID_HURRICANE_575A, 188 "3Com 3c575TX Fast Etherlink XL" }, 189 { TC_VENDORID, TC_DEVICEID_HURRICANE_575B, 190 "3Com 3c575B Fast Etherlink XL" }, 191 { TC_VENDORID, TC_DEVICEID_HURRICANE_575C, 192 "3Com 3c575C Fast Etherlink XL" }, 193 { TC_VENDORID, TC_DEVICEID_HURRICANE_656, 194 "3Com 3c656 Fast Etherlink XL" }, 195 { TC_VENDORID, TC_DEVICEID_HURRICANE_656B, 196 "3Com 3c656B Fast Etherlink XL" }, 197 { TC_VENDORID, TC_DEVICEID_TORNADO_656C, 198 "3Com 3c656C Fast Etherlink XL" }, 199 { 0, 0, NULL } 200 }; 201 202 static int xl_probe (device_t); 203 static int xl_attach (device_t); 204 static int xl_detach (device_t); 205 206 static int xl_newbuf (struct xl_softc *, struct xl_chain_onefrag *); 207 static void xl_stats_update (void *); 208 static int xl_encap (struct xl_softc *, struct xl_chain *, 209 struct mbuf *); 210 static void xl_rxeof (struct xl_softc *); 211 static int xl_rx_resync (struct xl_softc *); 212 static void xl_txeof (struct xl_softc *); 213 static void xl_txeof_90xB (struct xl_softc *); 214 static void xl_txeoc (struct xl_softc *); 215 static void xl_intr (void *); 216 static void xl_start (struct ifnet *); 217 static void xl_start_90xB (struct ifnet *); 218 static int xl_ioctl (struct ifnet *, u_long, caddr_t, 219 struct ucred *); 220 static void xl_init (void *); 221 static void xl_stop (struct xl_softc *); 222 static void xl_watchdog (struct ifnet *); 223 static void xl_shutdown (device_t); 224 static int xl_suspend (device_t); 225 static int xl_resume (device_t); 226 227 static int xl_ifmedia_upd (struct ifnet *); 228 static void xl_ifmedia_sts (struct ifnet *, struct ifmediareq *); 229 230 static int xl_eeprom_wait (struct xl_softc *); 231 static int xl_read_eeprom (struct xl_softc *, caddr_t, int, int, int); 232 static void xl_mii_sync (struct xl_softc *); 233 static void xl_mii_send (struct xl_softc *, u_int32_t, int); 234 static int xl_mii_readreg (struct xl_softc *, struct xl_mii_frame *); 235 static int xl_mii_writereg (struct xl_softc *, struct xl_mii_frame *); 236 237 static void xl_setcfg (struct xl_softc *); 238 static void xl_setmode (struct xl_softc *, int); 239 static void xl_setmulti (struct xl_softc *); 240 static void xl_setmulti_hash (struct xl_softc *); 241 static void xl_reset (struct xl_softc *); 242 static int xl_list_rx_init (struct xl_softc *); 243 static int xl_list_tx_init (struct xl_softc *); 244 static int xl_list_tx_init_90xB (struct xl_softc *); 245 static void xl_wait (struct xl_softc *); 246 static void xl_mediacheck (struct xl_softc *); 247 static void xl_choose_xcvr (struct xl_softc *, int); 248 static void xl_dma_map_addr (void *, bus_dma_segment_t *, int, int); 249 static void xl_dma_map_rxbuf (void *, bus_dma_segment_t *, int, bus_size_t, 250 int); 251 static void xl_dma_map_txbuf (void *, bus_dma_segment_t *, int, bus_size_t, 252 int); 253 #ifdef notdef 254 static void xl_testpacket (struct xl_softc *); 255 #endif 256 257 static int xl_miibus_readreg (device_t, int, int); 258 static int xl_miibus_writereg (device_t, int, int, int); 259 static void xl_miibus_statchg (device_t); 260 static void xl_miibus_mediainit (device_t); 261 262 static device_method_t xl_methods[] = { 263 /* Device interface */ 264 DEVMETHOD(device_probe, xl_probe), 265 DEVMETHOD(device_attach, xl_attach), 266 DEVMETHOD(device_detach, xl_detach), 267 DEVMETHOD(device_shutdown, xl_shutdown), 268 DEVMETHOD(device_suspend, xl_suspend), 269 DEVMETHOD(device_resume, xl_resume), 270 271 /* bus interface */ 272 DEVMETHOD(bus_print_child, bus_generic_print_child), 273 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 274 275 /* MII interface */ 276 DEVMETHOD(miibus_readreg, xl_miibus_readreg), 277 DEVMETHOD(miibus_writereg, xl_miibus_writereg), 278 DEVMETHOD(miibus_statchg, xl_miibus_statchg), 279 DEVMETHOD(miibus_mediainit, xl_miibus_mediainit), 280 281 { 0, 0 } 282 }; 283 284 static driver_t xl_driver = { 285 "xl", 286 xl_methods, 287 sizeof(struct xl_softc) 288 }; 289 290 static devclass_t xl_devclass; 291 292 DECLARE_DUMMY_MODULE(if_xl); 293 MODULE_DEPEND(if_xl, miibus, 1, 1, 1); 294 DRIVER_MODULE(if_xl, pci, xl_driver, xl_devclass, 0, 0); 295 DRIVER_MODULE(miibus, xl, miibus_driver, miibus_devclass, 0, 0); 296 297 static void 298 xl_dma_map_addr(arg, segs, nseg, error) 299 void *arg; 300 bus_dma_segment_t *segs; 301 int nseg, error; 302 { 303 u_int32_t *paddr; 304 305 paddr = arg; 306 *paddr = segs->ds_addr; 307 } 308 309 static void 310 xl_dma_map_rxbuf(arg, segs, nseg, mapsize, error) 311 void *arg; 312 bus_dma_segment_t *segs; 313 int nseg; 314 bus_size_t mapsize; 315 int error; 316 { 317 u_int32_t *paddr; 318 319 if (error) 320 return; 321 KASSERT(nseg == 1, ("xl_dma_map_rxbuf: too many DMA segments")); 322 paddr = arg; 323 *paddr = segs->ds_addr; 324 } 325 326 static void 327 xl_dma_map_txbuf(arg, segs, nseg, mapsize, error) 328 void *arg; 329 bus_dma_segment_t *segs; 330 int nseg; 331 bus_size_t mapsize; 332 int error; 333 { 334 struct xl_list *l; 335 int i, total_len; 336 337 if (error) 338 return; 339 340 KASSERT(nseg <= XL_MAXFRAGS, ("too many DMA segments")); 341 342 total_len = 0; 343 l = arg; 344 for (i = 0; i < nseg; i++) { 345 KASSERT(segs[i].ds_len <= MCLBYTES, ("segment size too large")); 346 l->xl_frag[i].xl_addr = htole32(segs[i].ds_addr); 347 l->xl_frag[i].xl_len = htole32(segs[i].ds_len); 348 total_len += segs[i].ds_len; 349 } 350 l->xl_frag[nseg - 1].xl_len = htole32(segs[nseg - 1].ds_len | 351 XL_LAST_FRAG); 352 l->xl_status = htole32(total_len); 353 l->xl_next = 0; 354 } 355 356 /* 357 * Murphy's law says that it's possible the chip can wedge and 358 * the 'command in progress' bit may never clear. Hence, we wait 359 * only a finite amount of time to avoid getting caught in an 360 * infinite loop. Normally this delay routine would be a macro, 361 * but it isn't called during normal operation so we can afford 362 * to make it a function. 363 */ 364 static void 365 xl_wait(sc) 366 struct xl_softc *sc; 367 { 368 int i; 369 370 for (i = 0; i < XL_TIMEOUT; i++) { 371 if (!(CSR_READ_2(sc, XL_STATUS) & XL_STAT_CMDBUSY)) 372 break; 373 } 374 375 if (i == XL_TIMEOUT) 376 if_printf(&sc->arpcom.ac_if, "command never completed!"); 377 378 return; 379 } 380 381 /* 382 * MII access routines are provided for adapters with external 383 * PHYs (3c905-TX, 3c905-T4, 3c905B-T4) and those with built-in 384 * autoneg logic that's faked up to look like a PHY (3c905B-TX). 385 * Note: if you don't perform the MDIO operations just right, 386 * it's possible to end up with code that works correctly with 387 * some chips/CPUs/processor speeds/bus speeds/etc but not 388 * with others. 389 */ 390 #define MII_SET(x) \ 391 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, \ 392 CSR_READ_2(sc, XL_W4_PHY_MGMT) | (x)) 393 394 #define MII_CLR(x) \ 395 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, \ 396 CSR_READ_2(sc, XL_W4_PHY_MGMT) & ~(x)) 397 398 /* 399 * Sync the PHYs by setting data bit and strobing the clock 32 times. 400 */ 401 static void 402 xl_mii_sync(sc) 403 struct xl_softc *sc; 404 { 405 int i; 406 407 XL_SEL_WIN(4); 408 MII_SET(XL_MII_DIR|XL_MII_DATA); 409 410 for (i = 0; i < 32; i++) { 411 MII_SET(XL_MII_CLK); 412 MII_SET(XL_MII_DATA); 413 MII_SET(XL_MII_DATA); 414 MII_CLR(XL_MII_CLK); 415 MII_SET(XL_MII_DATA); 416 MII_SET(XL_MII_DATA); 417 } 418 419 return; 420 } 421 422 /* 423 * Clock a series of bits through the MII. 424 */ 425 static void 426 xl_mii_send(sc, bits, cnt) 427 struct xl_softc *sc; 428 u_int32_t bits; 429 int cnt; 430 { 431 int i; 432 433 XL_SEL_WIN(4); 434 MII_CLR(XL_MII_CLK); 435 436 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 437 if (bits & i) { 438 MII_SET(XL_MII_DATA); 439 } else { 440 MII_CLR(XL_MII_DATA); 441 } 442 MII_CLR(XL_MII_CLK); 443 MII_SET(XL_MII_CLK); 444 } 445 } 446 447 /* 448 * Read an PHY register through the MII. 449 */ 450 static int 451 xl_mii_readreg(sc, frame) 452 struct xl_softc *sc; 453 struct xl_mii_frame *frame; 454 455 { 456 int i, ack; 457 458 crit_enter(); 459 460 /* 461 * Set up frame for RX. 462 */ 463 frame->mii_stdelim = XL_MII_STARTDELIM; 464 frame->mii_opcode = XL_MII_READOP; 465 frame->mii_turnaround = 0; 466 frame->mii_data = 0; 467 468 /* 469 * Select register window 4. 470 */ 471 472 XL_SEL_WIN(4); 473 474 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, 0); 475 /* 476 * Turn on data xmit. 477 */ 478 MII_SET(XL_MII_DIR); 479 480 xl_mii_sync(sc); 481 482 /* 483 * Send command/address info. 484 */ 485 xl_mii_send(sc, frame->mii_stdelim, 2); 486 xl_mii_send(sc, frame->mii_opcode, 2); 487 xl_mii_send(sc, frame->mii_phyaddr, 5); 488 xl_mii_send(sc, frame->mii_regaddr, 5); 489 490 /* Idle bit */ 491 MII_CLR((XL_MII_CLK|XL_MII_DATA)); 492 MII_SET(XL_MII_CLK); 493 494 /* Turn off xmit. */ 495 MII_CLR(XL_MII_DIR); 496 497 /* Check for ack */ 498 MII_CLR(XL_MII_CLK); 499 ack = CSR_READ_2(sc, XL_W4_PHY_MGMT) & XL_MII_DATA; 500 MII_SET(XL_MII_CLK); 501 502 /* 503 * Now try reading data bits. If the ack failed, we still 504 * need to clock through 16 cycles to keep the PHY(s) in sync. 505 */ 506 if (ack) { 507 for(i = 0; i < 16; i++) { 508 MII_CLR(XL_MII_CLK); 509 MII_SET(XL_MII_CLK); 510 } 511 goto fail; 512 } 513 514 for (i = 0x8000; i; i >>= 1) { 515 MII_CLR(XL_MII_CLK); 516 if (!ack) { 517 if (CSR_READ_2(sc, XL_W4_PHY_MGMT) & XL_MII_DATA) 518 frame->mii_data |= i; 519 } 520 MII_SET(XL_MII_CLK); 521 } 522 523 fail: 524 525 MII_CLR(XL_MII_CLK); 526 MII_SET(XL_MII_CLK); 527 528 crit_exit(); 529 530 if (ack) 531 return(1); 532 return(0); 533 } 534 535 /* 536 * Write to a PHY register through the MII. 537 */ 538 static int 539 xl_mii_writereg(sc, frame) 540 struct xl_softc *sc; 541 struct xl_mii_frame *frame; 542 543 { 544 crit_enter(); 545 546 /* 547 * Set up frame for TX. 548 */ 549 550 frame->mii_stdelim = XL_MII_STARTDELIM; 551 frame->mii_opcode = XL_MII_WRITEOP; 552 frame->mii_turnaround = XL_MII_TURNAROUND; 553 554 /* 555 * Select the window 4. 556 */ 557 XL_SEL_WIN(4); 558 559 /* 560 * Turn on data output. 561 */ 562 MII_SET(XL_MII_DIR); 563 564 xl_mii_sync(sc); 565 566 xl_mii_send(sc, frame->mii_stdelim, 2); 567 xl_mii_send(sc, frame->mii_opcode, 2); 568 xl_mii_send(sc, frame->mii_phyaddr, 5); 569 xl_mii_send(sc, frame->mii_regaddr, 5); 570 xl_mii_send(sc, frame->mii_turnaround, 2); 571 xl_mii_send(sc, frame->mii_data, 16); 572 573 /* Idle bit. */ 574 MII_SET(XL_MII_CLK); 575 MII_CLR(XL_MII_CLK); 576 577 /* 578 * Turn off xmit. 579 */ 580 MII_CLR(XL_MII_DIR); 581 582 crit_exit(); 583 584 return(0); 585 } 586 587 static int 588 xl_miibus_readreg(dev, phy, reg) 589 device_t dev; 590 int phy, reg; 591 { 592 struct xl_softc *sc; 593 struct xl_mii_frame frame; 594 595 sc = device_get_softc(dev); 596 597 /* 598 * Pretend that PHYs are only available at MII address 24. 599 * This is to guard against problems with certain 3Com ASIC 600 * revisions that incorrectly map the internal transceiver 601 * control registers at all MII addresses. This can cause 602 * the miibus code to attach the same PHY several times over. 603 */ 604 if ((!(sc->xl_flags & XL_FLAG_PHYOK)) && phy != 24) 605 return(0); 606 607 bzero((char *)&frame, sizeof(frame)); 608 609 frame.mii_phyaddr = phy; 610 frame.mii_regaddr = reg; 611 xl_mii_readreg(sc, &frame); 612 613 return(frame.mii_data); 614 } 615 616 static int 617 xl_miibus_writereg(dev, phy, reg, data) 618 device_t dev; 619 int phy, reg, data; 620 { 621 struct xl_softc *sc; 622 struct xl_mii_frame frame; 623 624 sc = device_get_softc(dev); 625 626 if ((!(sc->xl_flags & XL_FLAG_PHYOK)) && phy != 24) 627 return(0); 628 629 bzero((char *)&frame, sizeof(frame)); 630 631 frame.mii_phyaddr = phy; 632 frame.mii_regaddr = reg; 633 frame.mii_data = data; 634 635 xl_mii_writereg(sc, &frame); 636 637 return(0); 638 } 639 640 static void 641 xl_miibus_statchg(dev) 642 device_t dev; 643 { 644 struct xl_softc *sc; 645 struct mii_data *mii; 646 647 648 sc = device_get_softc(dev); 649 mii = device_get_softc(sc->xl_miibus); 650 651 xl_setcfg(sc); 652 653 /* Set ASIC's duplex mode to match the PHY. */ 654 XL_SEL_WIN(3); 655 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) 656 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, XL_MACCTRL_DUPLEX); 657 else 658 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, 659 (CSR_READ_1(sc, XL_W3_MAC_CTRL) & ~XL_MACCTRL_DUPLEX)); 660 661 return; 662 } 663 664 /* 665 * Special support for the 3c905B-COMBO. This card has 10/100 support 666 * plus BNC and AUI ports. This means we will have both an miibus attached 667 * plus some non-MII media settings. In order to allow this, we have to 668 * add the extra media to the miibus's ifmedia struct, but we can't do 669 * that during xl_attach() because the miibus hasn't been attached yet. 670 * So instead, we wait until the miibus probe/attach is done, at which 671 * point we will get a callback telling is that it's safe to add our 672 * extra media. 673 */ 674 static void 675 xl_miibus_mediainit(dev) 676 device_t dev; 677 { 678 struct xl_softc *sc; 679 struct mii_data *mii; 680 struct ifmedia *ifm; 681 682 sc = device_get_softc(dev); 683 mii = device_get_softc(sc->xl_miibus); 684 ifm = &mii->mii_media; 685 686 if (sc->xl_media & (XL_MEDIAOPT_AUI|XL_MEDIAOPT_10FL)) { 687 /* 688 * Check for a 10baseFL board in disguise. 689 */ 690 if (sc->xl_type == XL_TYPE_905B && 691 sc->xl_media == XL_MEDIAOPT_10FL) { 692 if (bootverbose) 693 device_printf(dev, "found 10baseFL\n"); 694 ifmedia_add(ifm, IFM_ETHER|IFM_10_FL, 0, NULL); 695 ifmedia_add(ifm, IFM_ETHER|IFM_10_FL|IFM_HDX, 0, NULL); 696 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX) 697 ifmedia_add(ifm, 698 IFM_ETHER|IFM_10_FL|IFM_FDX, 0, NULL); 699 } else { 700 if (bootverbose) 701 device_printf(dev, "found AUI\n"); 702 ifmedia_add(ifm, IFM_ETHER|IFM_10_5, 0, NULL); 703 } 704 } 705 706 if (sc->xl_media & XL_MEDIAOPT_BNC) { 707 if (bootverbose) 708 device_printf(dev, "found BNC\n"); 709 ifmedia_add(ifm, IFM_ETHER|IFM_10_2, 0, NULL); 710 } 711 712 return; 713 } 714 715 /* 716 * The EEPROM is slow: give it time to come ready after issuing 717 * it a command. 718 */ 719 static int 720 xl_eeprom_wait(sc) 721 struct xl_softc *sc; 722 { 723 int i; 724 725 for (i = 0; i < 100; i++) { 726 if (CSR_READ_2(sc, XL_W0_EE_CMD) & XL_EE_BUSY) 727 DELAY(162); 728 else 729 break; 730 } 731 732 if (i == 100) { 733 if_printf(&sc->arpcom.ac_if, "eeprom failed to come ready\n"); 734 return(1); 735 } 736 737 return(0); 738 } 739 740 /* 741 * Read a sequence of words from the EEPROM. Note that ethernet address 742 * data is stored in the EEPROM in network byte order. 743 */ 744 static int 745 xl_read_eeprom(sc, dest, off, cnt, swap) 746 struct xl_softc *sc; 747 caddr_t dest; 748 int off; 749 int cnt; 750 int swap; 751 { 752 int err = 0, i; 753 u_int16_t word = 0, *ptr; 754 #define EEPROM_5BIT_OFFSET(A) ((((A) << 2) & 0x7F00) | ((A) & 0x003F)) 755 #define EEPROM_8BIT_OFFSET(A) ((A) & 0x003F) 756 /* WARNING! DANGER! 757 * It's easy to accidentally overwrite the rom content! 758 * Note: the 3c575 uses 8bit EEPROM offsets. 759 */ 760 XL_SEL_WIN(0); 761 762 if (xl_eeprom_wait(sc)) 763 return(1); 764 765 if (sc->xl_flags & XL_FLAG_EEPROM_OFFSET_30) 766 off += 0x30; 767 768 for (i = 0; i < cnt; i++) { 769 if (sc->xl_flags & XL_FLAG_8BITROM) 770 CSR_WRITE_2(sc, XL_W0_EE_CMD, 771 XL_EE_8BIT_READ | EEPROM_8BIT_OFFSET(off + i)); 772 else 773 CSR_WRITE_2(sc, XL_W0_EE_CMD, 774 XL_EE_READ | EEPROM_5BIT_OFFSET(off + i)); 775 err = xl_eeprom_wait(sc); 776 if (err) 777 break; 778 word = CSR_READ_2(sc, XL_W0_EE_DATA); 779 ptr = (u_int16_t *)(dest + (i * 2)); 780 if (swap) 781 *ptr = ntohs(word); 782 else 783 *ptr = word; 784 } 785 786 return(err ? 1 : 0); 787 } 788 789 /* 790 * NICs older than the 3c905B have only one multicast option, which 791 * is to enable reception of all multicast frames. 792 */ 793 static void 794 xl_setmulti(sc) 795 struct xl_softc *sc; 796 { 797 struct ifnet *ifp; 798 struct ifmultiaddr *ifma; 799 u_int8_t rxfilt; 800 int mcnt = 0; 801 802 ifp = &sc->arpcom.ac_if; 803 804 XL_SEL_WIN(5); 805 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER); 806 807 if (ifp->if_flags & IFF_ALLMULTI) { 808 rxfilt |= XL_RXFILTER_ALLMULTI; 809 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 810 return; 811 } 812 813 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) 814 mcnt++; 815 816 if (mcnt) 817 rxfilt |= XL_RXFILTER_ALLMULTI; 818 else 819 rxfilt &= ~XL_RXFILTER_ALLMULTI; 820 821 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 822 823 return; 824 } 825 826 /* 827 * 3c905B adapters have a hash filter that we can program. 828 */ 829 static void 830 xl_setmulti_hash(sc) 831 struct xl_softc *sc; 832 { 833 struct ifnet *ifp; 834 int h = 0, i; 835 struct ifmultiaddr *ifma; 836 u_int8_t rxfilt; 837 int mcnt = 0; 838 839 ifp = &sc->arpcom.ac_if; 840 841 XL_SEL_WIN(5); 842 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER); 843 844 if (ifp->if_flags & IFF_ALLMULTI) { 845 rxfilt |= XL_RXFILTER_ALLMULTI; 846 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 847 return; 848 } else 849 rxfilt &= ~XL_RXFILTER_ALLMULTI; 850 851 852 /* first, zot all the existing hash bits */ 853 for (i = 0; i < XL_HASHFILT_SIZE; i++) 854 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_HASH|i); 855 856 /* now program new ones */ 857 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 858 if (ifma->ifma_addr->sa_family != AF_LINK) 859 continue; 860 861 /* 862 * Note: the 3c905B currently only supports a 64-bit 863 * hash table, which means we really only need 6 bits, 864 * but the manual indicates that future chip revisions 865 * will have a 256-bit hash table, hence the routine is 866 * set up to calculate 8 bits of position info in case 867 * we need it some day. 868 * Note II, The Sequel: _CURRENT_ versions of the 3c905B 869 * have a 256 bit hash table. This means we have to use 870 * all 8 bits regardless. On older cards, the upper 2 871 * bits will be ignored. Grrrr.... 872 */ 873 h = ether_crc32_be( 874 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 875 ETHER_ADDR_LEN) & 0xff; 876 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_HASH|XL_HASH_SET|h); 877 mcnt++; 878 } 879 880 if (mcnt) 881 rxfilt |= XL_RXFILTER_MULTIHASH; 882 else 883 rxfilt &= ~XL_RXFILTER_MULTIHASH; 884 885 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 886 887 return; 888 } 889 890 #ifdef notdef 891 static void 892 xl_testpacket(sc) 893 struct xl_softc *sc; 894 { 895 struct mbuf *m; 896 struct ifnet *ifp; 897 898 ifp = &sc->arpcom.ac_if; 899 900 MGETHDR(m, MB_DONTWAIT, MT_DATA); 901 902 if (m == NULL) 903 return; 904 905 bcopy(&sc->arpcom.ac_enaddr, 906 mtod(m, struct ether_header *)->ether_dhost, ETHER_ADDR_LEN); 907 bcopy(&sc->arpcom.ac_enaddr, 908 mtod(m, struct ether_header *)->ether_shost, ETHER_ADDR_LEN); 909 mtod(m, struct ether_header *)->ether_type = htons(3); 910 mtod(m, unsigned char *)[14] = 0; 911 mtod(m, unsigned char *)[15] = 0; 912 mtod(m, unsigned char *)[16] = 0xE3; 913 m->m_len = m->m_pkthdr.len = sizeof(struct ether_header) + 3; 914 IF_ENQUEUE(&ifp->if_snd, m); 915 xl_start(ifp); 916 917 return; 918 } 919 #endif 920 921 static void 922 xl_setcfg(sc) 923 struct xl_softc *sc; 924 { 925 u_int32_t icfg; 926 927 XL_SEL_WIN(3); 928 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG); 929 icfg &= ~XL_ICFG_CONNECTOR_MASK; 930 if (sc->xl_media & XL_MEDIAOPT_MII || 931 sc->xl_media & XL_MEDIAOPT_BT4) 932 icfg |= (XL_XCVR_MII << XL_ICFG_CONNECTOR_BITS); 933 if (sc->xl_media & XL_MEDIAOPT_BTX) 934 icfg |= (XL_XCVR_AUTO << XL_ICFG_CONNECTOR_BITS); 935 936 CSR_WRITE_4(sc, XL_W3_INTERNAL_CFG, icfg); 937 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP); 938 939 return; 940 } 941 942 static void 943 xl_setmode(sc, media) 944 struct xl_softc *sc; 945 int media; 946 { 947 struct ifnet *ifp = &sc->arpcom.ac_if; 948 u_int32_t icfg; 949 u_int16_t mediastat; 950 951 if_printf(ifp, "selecting "); 952 953 XL_SEL_WIN(4); 954 mediastat = CSR_READ_2(sc, XL_W4_MEDIA_STATUS); 955 XL_SEL_WIN(3); 956 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG); 957 958 if (sc->xl_media & XL_MEDIAOPT_BT) { 959 if (IFM_SUBTYPE(media) == IFM_10_T) { 960 printf("10baseT transceiver, "); 961 sc->xl_xcvr = XL_XCVR_10BT; 962 icfg &= ~XL_ICFG_CONNECTOR_MASK; 963 icfg |= (XL_XCVR_10BT << XL_ICFG_CONNECTOR_BITS); 964 mediastat |= XL_MEDIASTAT_LINKBEAT| 965 XL_MEDIASTAT_JABGUARD; 966 mediastat &= ~XL_MEDIASTAT_SQEENB; 967 } 968 } 969 970 if (sc->xl_media & XL_MEDIAOPT_BFX) { 971 if (IFM_SUBTYPE(media) == IFM_100_FX) { 972 printf("100baseFX port, "); 973 sc->xl_xcvr = XL_XCVR_100BFX; 974 icfg &= ~XL_ICFG_CONNECTOR_MASK; 975 icfg |= (XL_XCVR_100BFX << XL_ICFG_CONNECTOR_BITS); 976 mediastat |= XL_MEDIASTAT_LINKBEAT; 977 mediastat &= ~XL_MEDIASTAT_SQEENB; 978 } 979 } 980 981 if (sc->xl_media & (XL_MEDIAOPT_AUI|XL_MEDIAOPT_10FL)) { 982 if (IFM_SUBTYPE(media) == IFM_10_5) { 983 printf("AUI port, "); 984 sc->xl_xcvr = XL_XCVR_AUI; 985 icfg &= ~XL_ICFG_CONNECTOR_MASK; 986 icfg |= (XL_XCVR_AUI << XL_ICFG_CONNECTOR_BITS); 987 mediastat &= ~(XL_MEDIASTAT_LINKBEAT| 988 XL_MEDIASTAT_JABGUARD); 989 mediastat |= ~XL_MEDIASTAT_SQEENB; 990 } 991 if (IFM_SUBTYPE(media) == IFM_10_FL) { 992 printf("10baseFL transceiver, "); 993 sc->xl_xcvr = XL_XCVR_AUI; 994 icfg &= ~XL_ICFG_CONNECTOR_MASK; 995 icfg |= (XL_XCVR_AUI << XL_ICFG_CONNECTOR_BITS); 996 mediastat &= ~(XL_MEDIASTAT_LINKBEAT| 997 XL_MEDIASTAT_JABGUARD); 998 mediastat |= ~XL_MEDIASTAT_SQEENB; 999 } 1000 } 1001 1002 if (sc->xl_media & XL_MEDIAOPT_BNC) { 1003 if (IFM_SUBTYPE(media) == IFM_10_2) { 1004 printf("BNC port, "); 1005 sc->xl_xcvr = XL_XCVR_COAX; 1006 icfg &= ~XL_ICFG_CONNECTOR_MASK; 1007 icfg |= (XL_XCVR_COAX << XL_ICFG_CONNECTOR_BITS); 1008 mediastat &= ~(XL_MEDIASTAT_LINKBEAT| 1009 XL_MEDIASTAT_JABGUARD| 1010 XL_MEDIASTAT_SQEENB); 1011 } 1012 } 1013 1014 if ((media & IFM_GMASK) == IFM_FDX || 1015 IFM_SUBTYPE(media) == IFM_100_FX) { 1016 printf("full duplex\n"); 1017 XL_SEL_WIN(3); 1018 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, XL_MACCTRL_DUPLEX); 1019 } else { 1020 printf("half duplex\n"); 1021 XL_SEL_WIN(3); 1022 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, 1023 (CSR_READ_1(sc, XL_W3_MAC_CTRL) & ~XL_MACCTRL_DUPLEX)); 1024 } 1025 1026 if (IFM_SUBTYPE(media) == IFM_10_2) 1027 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_START); 1028 else 1029 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP); 1030 CSR_WRITE_4(sc, XL_W3_INTERNAL_CFG, icfg); 1031 XL_SEL_WIN(4); 1032 CSR_WRITE_2(sc, XL_W4_MEDIA_STATUS, mediastat); 1033 DELAY(800); 1034 XL_SEL_WIN(7); 1035 } 1036 1037 static void 1038 xl_reset(sc) 1039 struct xl_softc *sc; 1040 { 1041 int i; 1042 1043 XL_SEL_WIN(0); 1044 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RESET | 1045 ((sc->xl_flags & XL_FLAG_WEIRDRESET) ? 1046 XL_RESETOPT_DISADVFD:0)); 1047 1048 /* 1049 * If we're using memory mapped register mode, pause briefly 1050 * after issuing the reset command before trying to access any 1051 * other registers. With my 3c575C cardbus card, failing to do 1052 * this results in the system locking up while trying to poll 1053 * the command busy bit in the status register. 1054 */ 1055 if (sc->xl_flags & XL_FLAG_USE_MMIO) 1056 DELAY(100000); 1057 1058 for (i = 0; i < XL_TIMEOUT; i++) { 1059 DELAY(10); 1060 if (!(CSR_READ_2(sc, XL_STATUS) & XL_STAT_CMDBUSY)) 1061 break; 1062 } 1063 1064 if (i == XL_TIMEOUT) 1065 if_printf(&sc->arpcom.ac_if, "reset didn't complete\n"); 1066 1067 /* Reset TX and RX. */ 1068 /* Note: the RX reset takes an absurd amount of time 1069 * on newer versions of the Tornado chips such as those 1070 * on the 3c905CX and newer 3c908C cards. We wait an 1071 * extra amount of time so that xl_wait() doesn't complain 1072 * and annoy the users. 1073 */ 1074 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET); 1075 DELAY(100000); 1076 xl_wait(sc); 1077 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); 1078 xl_wait(sc); 1079 1080 if (sc->xl_flags & XL_FLAG_INVERT_LED_PWR || 1081 sc->xl_flags & XL_FLAG_INVERT_MII_PWR) { 1082 XL_SEL_WIN(2); 1083 CSR_WRITE_2(sc, XL_W2_RESET_OPTIONS, CSR_READ_2(sc, 1084 XL_W2_RESET_OPTIONS) 1085 | ((sc->xl_flags & XL_FLAG_INVERT_LED_PWR)?XL_RESETOPT_INVERT_LED:0) 1086 | ((sc->xl_flags & XL_FLAG_INVERT_MII_PWR)?XL_RESETOPT_INVERT_MII:0) 1087 ); 1088 } 1089 1090 /* Wait a little while for the chip to get its brains in order. */ 1091 DELAY(100000); 1092 return; 1093 } 1094 1095 /* 1096 * Probe for a 3Com Etherlink XL chip. Check the PCI vendor and device 1097 * IDs against our list and return a device name if we find a match. 1098 */ 1099 static int 1100 xl_probe(device_t dev) 1101 { 1102 struct xl_type *t; 1103 uint16_t vid, did; 1104 1105 vid = pci_get_vendor(dev); 1106 did = pci_get_device(dev); 1107 for (t = xl_devs; t->xl_name != NULL; t++) { 1108 if (vid == t->xl_vid && did == t->xl_did) { 1109 device_set_desc(dev, t->xl_name); 1110 return(0); 1111 } 1112 } 1113 return(ENXIO); 1114 } 1115 1116 /* 1117 * This routine is a kludge to work around possible hardware faults 1118 * or manufacturing defects that can cause the media options register 1119 * (or reset options register, as it's called for the first generation 1120 * 3c90x adapters) to return an incorrect result. I have encountered 1121 * one Dell Latitude laptop docking station with an integrated 3c905-TX 1122 * which doesn't have any of the 'mediaopt' bits set. This screws up 1123 * the attach routine pretty badly because it doesn't know what media 1124 * to look for. If we find ourselves in this predicament, this routine 1125 * will try to guess the media options values and warn the user of a 1126 * possible manufacturing defect with his adapter/system/whatever. 1127 */ 1128 static void 1129 xl_mediacheck(sc) 1130 struct xl_softc *sc; 1131 { 1132 struct ifnet *ifp = &sc->arpcom.ac_if; 1133 1134 /* 1135 * If some of the media options bits are set, assume they are 1136 * correct. If not, try to figure it out down below. 1137 * XXX I should check for 10baseFL, but I don't have an adapter 1138 * to test with. 1139 */ 1140 if (sc->xl_media & (XL_MEDIAOPT_MASK & ~XL_MEDIAOPT_VCO)) { 1141 /* 1142 * Check the XCVR value. If it's not in the normal range 1143 * of values, we need to fake it up here. 1144 */ 1145 if (sc->xl_xcvr <= XL_XCVR_AUTO) 1146 return; 1147 else { 1148 if_printf(ifp, "bogus xcvr value in EEPROM (%x)\n", 1149 sc->xl_xcvr); 1150 if_printf(ifp, 1151 "choosing new default based on card type\n"); 1152 } 1153 } else { 1154 if (sc->xl_type == XL_TYPE_905B && 1155 sc->xl_media & XL_MEDIAOPT_10FL) 1156 return; 1157 if_printf(ifp, "WARNING: no media options bits set in " 1158 "the media options register!!\n"); 1159 if_printf(ifp, "this could be a manufacturing defect in " 1160 "your adapter or system\n"); 1161 if_printf(ifp, "attempting to guess media type; you " 1162 "should probably consult your vendor\n"); 1163 } 1164 1165 xl_choose_xcvr(sc, 1); 1166 } 1167 1168 static void 1169 xl_choose_xcvr(sc, verbose) 1170 struct xl_softc *sc; 1171 int verbose; 1172 { 1173 struct ifnet *ifp = &sc->arpcom.ac_if; 1174 u_int16_t devid; 1175 1176 /* 1177 * Read the device ID from the EEPROM. 1178 * This is what's loaded into the PCI device ID register, so it has 1179 * to be correct otherwise we wouldn't have gotten this far. 1180 */ 1181 xl_read_eeprom(sc, (caddr_t)&devid, XL_EE_PRODID, 1, 0); 1182 1183 switch(devid) { 1184 case TC_DEVICEID_BOOMERANG_10BT: /* 3c900-TPO */ 1185 case TC_DEVICEID_KRAKATOA_10BT: /* 3c900B-TPO */ 1186 sc->xl_media = XL_MEDIAOPT_BT; 1187 sc->xl_xcvr = XL_XCVR_10BT; 1188 if (verbose) 1189 if_printf(ifp, "guessing 10BaseT transceiver\n"); 1190 break; 1191 case TC_DEVICEID_BOOMERANG_10BT_COMBO: /* 3c900-COMBO */ 1192 case TC_DEVICEID_KRAKATOA_10BT_COMBO: /* 3c900B-COMBO */ 1193 sc->xl_media = XL_MEDIAOPT_BT|XL_MEDIAOPT_BNC|XL_MEDIAOPT_AUI; 1194 sc->xl_xcvr = XL_XCVR_10BT; 1195 if (verbose) 1196 if_printf(ifp, "guessing COMBO (AUI/BNC/TP)\n"); 1197 break; 1198 case TC_DEVICEID_KRAKATOA_10BT_TPC: /* 3c900B-TPC */ 1199 sc->xl_media = XL_MEDIAOPT_BT|XL_MEDIAOPT_BNC; 1200 sc->xl_xcvr = XL_XCVR_10BT; 1201 if (verbose) 1202 if_printf(ifp, "guessing TPC (BNC/TP)\n"); 1203 break; 1204 case TC_DEVICEID_CYCLONE_10FL: /* 3c900B-FL */ 1205 sc->xl_media = XL_MEDIAOPT_10FL; 1206 sc->xl_xcvr = XL_XCVR_AUI; 1207 if (verbose) 1208 if_printf(ifp, "guessing 10baseFL\n"); 1209 break; 1210 case TC_DEVICEID_BOOMERANG_10_100BT: /* 3c905-TX */ 1211 case TC_DEVICEID_HURRICANE_555: /* 3c555 */ 1212 case TC_DEVICEID_HURRICANE_556: /* 3c556 */ 1213 case TC_DEVICEID_HURRICANE_556B: /* 3c556B */ 1214 case TC_DEVICEID_HURRICANE_575A: /* 3c575TX */ 1215 case TC_DEVICEID_HURRICANE_575B: /* 3c575B */ 1216 case TC_DEVICEID_HURRICANE_575C: /* 3c575C */ 1217 case TC_DEVICEID_HURRICANE_656: /* 3c656 */ 1218 case TC_DEVICEID_HURRICANE_656B: /* 3c656B */ 1219 case TC_DEVICEID_TORNADO_656C: /* 3c656C */ 1220 case TC_DEVICEID_TORNADO_10_100BT_920B: /* 3c920B-EMB */ 1221 sc->xl_media = XL_MEDIAOPT_MII; 1222 sc->xl_xcvr = XL_XCVR_MII; 1223 if (verbose) 1224 if_printf(ifp, "guessing MII\n"); 1225 break; 1226 case TC_DEVICEID_BOOMERANG_100BT4: /* 3c905-T4 */ 1227 case TC_DEVICEID_CYCLONE_10_100BT4: /* 3c905B-T4 */ 1228 sc->xl_media = XL_MEDIAOPT_BT4; 1229 sc->xl_xcvr = XL_XCVR_MII; 1230 if (verbose) 1231 if_printf(ifp, "guessing 100BaseT4/MII\n"); 1232 break; 1233 case TC_DEVICEID_HURRICANE_10_100BT: /* 3c905B-TX */ 1234 case TC_DEVICEID_HURRICANE_10_100BT_SERV:/*3c980-TX */ 1235 case TC_DEVICEID_TORNADO_10_100BT_SERV: /* 3c980C-TX */ 1236 case TC_DEVICEID_HURRICANE_SOHO100TX: /* 3cSOHO100-TX */ 1237 case TC_DEVICEID_TORNADO_10_100BT: /* 3c905C-TX */ 1238 case TC_DEVICEID_TORNADO_HOMECONNECT: /* 3c450-TX */ 1239 sc->xl_media = XL_MEDIAOPT_BTX; 1240 sc->xl_xcvr = XL_XCVR_AUTO; 1241 if (verbose) 1242 if_printf(ifp, "guessing 10/100 internal\n"); 1243 break; 1244 case TC_DEVICEID_CYCLONE_10_100_COMBO: /* 3c905B-COMBO */ 1245 sc->xl_media = XL_MEDIAOPT_BTX|XL_MEDIAOPT_BNC|XL_MEDIAOPT_AUI; 1246 sc->xl_xcvr = XL_XCVR_AUTO; 1247 if (verbose) 1248 if_printf(ifp, "guessing 10/100 plus BNC/AUI\n"); 1249 break; 1250 default: 1251 if_printf(ifp, 1252 "unknown device ID: %x -- defaulting to 10baseT\n", devid); 1253 sc->xl_media = XL_MEDIAOPT_BT; 1254 break; 1255 } 1256 1257 return; 1258 } 1259 1260 /* 1261 * Attach the interface. Allocate softc structures, do ifmedia 1262 * setup and ethernet/BPF attach. 1263 */ 1264 static int 1265 xl_attach(dev) 1266 device_t dev; 1267 { 1268 u_char eaddr[ETHER_ADDR_LEN]; 1269 u_int16_t xcvr[2]; 1270 struct xl_softc *sc; 1271 struct ifnet *ifp; 1272 int media = IFM_ETHER|IFM_100_TX|IFM_FDX; 1273 int error = 0, rid, res; 1274 1275 sc = device_get_softc(dev); 1276 1277 ifmedia_init(&sc->ifmedia, 0, xl_ifmedia_upd, xl_ifmedia_sts); 1278 1279 sc->xl_flags = 0; 1280 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_555) 1281 sc->xl_flags |= XL_FLAG_EEPROM_OFFSET_30 | XL_FLAG_PHYOK; 1282 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_556 || 1283 pci_get_device(dev) == TC_DEVICEID_HURRICANE_556B) 1284 sc->xl_flags |= XL_FLAG_FUNCREG | XL_FLAG_PHYOK | 1285 XL_FLAG_EEPROM_OFFSET_30 | XL_FLAG_WEIRDRESET | 1286 XL_FLAG_INVERT_LED_PWR | XL_FLAG_INVERT_MII_PWR; 1287 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_555 || 1288 pci_get_device(dev) == TC_DEVICEID_HURRICANE_556) 1289 sc->xl_flags |= XL_FLAG_8BITROM; 1290 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_556B) 1291 sc->xl_flags |= XL_FLAG_NO_XCVR_PWR; 1292 1293 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_575A || 1294 pci_get_device(dev) == TC_DEVICEID_HURRICANE_575B || 1295 pci_get_device(dev) == TC_DEVICEID_HURRICANE_575C || 1296 pci_get_device(dev) == TC_DEVICEID_HURRICANE_656B || 1297 pci_get_device(dev) == TC_DEVICEID_TORNADO_656C) 1298 sc->xl_flags |= XL_FLAG_FUNCREG | XL_FLAG_PHYOK | 1299 XL_FLAG_EEPROM_OFFSET_30 | XL_FLAG_8BITROM; 1300 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_656) 1301 sc->xl_flags |= XL_FLAG_FUNCREG | XL_FLAG_PHYOK; 1302 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_575B) 1303 sc->xl_flags |= XL_FLAG_INVERT_LED_PWR; 1304 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_575C) 1305 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR; 1306 if (pci_get_device(dev) == TC_DEVICEID_TORNADO_656C) 1307 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR; 1308 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_656 || 1309 pci_get_device(dev) == TC_DEVICEID_HURRICANE_656B) 1310 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR | 1311 XL_FLAG_INVERT_LED_PWR; 1312 if (pci_get_device(dev) == TC_DEVICEID_TORNADO_10_100BT_920B) 1313 sc->xl_flags |= XL_FLAG_PHYOK; 1314 #ifndef BURN_BRIDGES 1315 /* 1316 * If this is a 3c905B, we have to check one extra thing. 1317 * The 905B supports power management and may be placed in 1318 * a low-power mode (D3 mode), typically by certain operating 1319 * systems which shall not be named. The PCI BIOS is supposed 1320 * to reset the NIC and bring it out of low-power mode, but 1321 * some do not. Consequently, we have to see if this chip 1322 * supports power management, and if so, make sure it's not 1323 * in low-power mode. If power management is available, the 1324 * capid byte will be 0x01. 1325 * 1326 * I _think_ that what actually happens is that the chip 1327 * loses its PCI configuration during the transition from 1328 * D3 back to D0; this means that it should be possible for 1329 * us to save the PCI iobase, membase and IRQ, put the chip 1330 * back in the D0 state, then restore the PCI config ourselves. 1331 */ 1332 1333 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 1334 u_int32_t iobase, membase, irq; 1335 1336 /* Save important PCI config data. */ 1337 iobase = pci_read_config(dev, XL_PCI_LOIO, 4); 1338 membase = pci_read_config(dev, XL_PCI_LOMEM, 4); 1339 irq = pci_read_config(dev, XL_PCI_INTLINE, 4); 1340 1341 /* Reset the power state. */ 1342 device_printf(dev, "chip is in D%d power mode " 1343 "-- setting to D0\n", pci_get_powerstate(dev)); 1344 1345 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 1346 1347 /* Restore PCI config data. */ 1348 pci_write_config(dev, XL_PCI_LOIO, iobase, 4); 1349 pci_write_config(dev, XL_PCI_LOMEM, membase, 4); 1350 pci_write_config(dev, XL_PCI_INTLINE, irq, 4); 1351 } 1352 #endif 1353 /* 1354 * Map control/status registers. 1355 */ 1356 pci_enable_busmaster(dev); 1357 1358 rid = XL_PCI_LOMEM; 1359 res = SYS_RES_MEMORY; 1360 1361 #if 0 1362 sc->xl_res = bus_alloc_resource_any(dev, res, &rid, RF_ACTIVE); 1363 #endif 1364 1365 if (sc->xl_res != NULL) { 1366 sc->xl_flags |= XL_FLAG_USE_MMIO; 1367 if (bootverbose) 1368 device_printf(dev, "using memory mapped I/O\n"); 1369 } else { 1370 rid = XL_PCI_LOIO; 1371 res = SYS_RES_IOPORT; 1372 sc->xl_res = bus_alloc_resource_any(dev, res, &rid, RF_ACTIVE); 1373 if (sc->xl_res == NULL) { 1374 device_printf(dev, "couldn't map ports/memory\n"); 1375 error = ENXIO; 1376 goto fail; 1377 } 1378 if (bootverbose) 1379 device_printf(dev, "using port I/O\n"); 1380 } 1381 1382 sc->xl_btag = rman_get_bustag(sc->xl_res); 1383 sc->xl_bhandle = rman_get_bushandle(sc->xl_res); 1384 1385 if (sc->xl_flags & XL_FLAG_FUNCREG) { 1386 rid = XL_PCI_FUNCMEM; 1387 sc->xl_fres = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 1388 RF_ACTIVE); 1389 1390 if (sc->xl_fres == NULL) { 1391 device_printf(dev, "couldn't map ports/memory\n"); 1392 error = ENXIO; 1393 goto fail; 1394 } 1395 1396 sc->xl_ftag = rman_get_bustag(sc->xl_fres); 1397 sc->xl_fhandle = rman_get_bushandle(sc->xl_fres); 1398 } 1399 1400 /* Allocate interrupt */ 1401 rid = 0; 1402 sc->xl_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1403 RF_SHAREABLE | RF_ACTIVE); 1404 if (sc->xl_irq == NULL) { 1405 device_printf(dev, "couldn't map interrupt\n"); 1406 error = ENXIO; 1407 goto fail; 1408 } 1409 1410 sc->xl_flags |= XL_FLAG_ATTACH_MAPPED; 1411 1412 ifp = &sc->arpcom.ac_if; 1413 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1414 1415 /* Reset the adapter. */ 1416 xl_reset(sc); 1417 1418 /* 1419 * Get station address from the EEPROM. 1420 */ 1421 if (xl_read_eeprom(sc, (caddr_t)&eaddr, XL_EE_OEM_ADR0, 3, 1)) { 1422 device_printf(dev, "failed to read station address\n"); 1423 error = ENXIO; 1424 goto fail; 1425 } 1426 1427 callout_init(&sc->xl_stat_timer); 1428 1429 /* 1430 * Now allocate a tag for the DMA descriptor lists and a chunk 1431 * of DMA-able memory based on the tag. Also obtain the DMA 1432 * addresses of the RX and TX ring, which we'll need later. 1433 * All of our lists are allocated as a contiguous block 1434 * of memory. 1435 */ 1436 error = bus_dma_tag_create(NULL, 8, 0, 1437 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 1438 XL_RX_LIST_SZ, 1, XL_RX_LIST_SZ, 0, 1439 &sc->xl_ldata.xl_rx_tag); 1440 if (error) { 1441 device_printf(dev, "failed to allocate rx dma tag\n"); 1442 goto fail; 1443 } 1444 1445 error = bus_dmamem_alloc(sc->xl_ldata.xl_rx_tag, 1446 (void **)&sc->xl_ldata.xl_rx_list, BUS_DMA_NOWAIT, 1447 &sc->xl_ldata.xl_rx_dmamap); 1448 if (error) { 1449 device_printf(dev, "no memory for rx list buffers!\n"); 1450 bus_dma_tag_destroy(sc->xl_ldata.xl_rx_tag); 1451 sc->xl_ldata.xl_rx_tag = NULL; 1452 goto fail; 1453 } 1454 1455 error = bus_dmamap_load(sc->xl_ldata.xl_rx_tag, 1456 sc->xl_ldata.xl_rx_dmamap, sc->xl_ldata.xl_rx_list, 1457 XL_RX_LIST_SZ, xl_dma_map_addr, 1458 &sc->xl_ldata.xl_rx_dmaaddr, BUS_DMA_NOWAIT); 1459 if (error) { 1460 device_printf(dev, "cannot get dma address of the rx ring!\n"); 1461 bus_dmamem_free(sc->xl_ldata.xl_rx_tag, sc->xl_ldata.xl_rx_list, 1462 sc->xl_ldata.xl_rx_dmamap); 1463 bus_dma_tag_destroy(sc->xl_ldata.xl_rx_tag); 1464 sc->xl_ldata.xl_rx_tag = NULL; 1465 goto fail; 1466 } 1467 1468 error = bus_dma_tag_create(NULL, 8, 0, 1469 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 1470 XL_TX_LIST_SZ, 1, XL_TX_LIST_SZ, 0, 1471 &sc->xl_ldata.xl_tx_tag); 1472 if (error) { 1473 device_printf(dev, "failed to allocate tx dma tag\n"); 1474 goto fail; 1475 } 1476 1477 error = bus_dmamem_alloc(sc->xl_ldata.xl_tx_tag, 1478 (void **)&sc->xl_ldata.xl_tx_list, BUS_DMA_NOWAIT, 1479 &sc->xl_ldata.xl_tx_dmamap); 1480 if (error) { 1481 device_printf(dev, "no memory for list buffers!\n"); 1482 bus_dma_tag_destroy(sc->xl_ldata.xl_tx_tag); 1483 sc->xl_ldata.xl_tx_tag = NULL; 1484 goto fail; 1485 } 1486 1487 error = bus_dmamap_load(sc->xl_ldata.xl_tx_tag, 1488 sc->xl_ldata.xl_tx_dmamap, sc->xl_ldata.xl_tx_list, 1489 XL_TX_LIST_SZ, xl_dma_map_addr, 1490 &sc->xl_ldata.xl_tx_dmaaddr, BUS_DMA_NOWAIT); 1491 if (error) { 1492 device_printf(dev, "cannot get dma address of the tx ring!\n"); 1493 bus_dmamem_free(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_list, 1494 sc->xl_ldata.xl_tx_dmamap); 1495 bus_dma_tag_destroy(sc->xl_ldata.xl_tx_tag); 1496 sc->xl_ldata.xl_tx_tag = NULL; 1497 goto fail; 1498 } 1499 1500 /* 1501 * Allocate a DMA tag for the mapping of mbufs. 1502 */ 1503 error = bus_dma_tag_create(NULL, 1, 0, 1504 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 1505 MCLBYTES * XL_MAXFRAGS, XL_MAXFRAGS, MCLBYTES, 0, 1506 &sc->xl_mtag); 1507 if (error) { 1508 device_printf(dev, "failed to allocate mbuf dma tag\n"); 1509 goto fail; 1510 } 1511 1512 bzero(sc->xl_ldata.xl_tx_list, XL_TX_LIST_SZ); 1513 bzero(sc->xl_ldata.xl_rx_list, XL_RX_LIST_SZ); 1514 1515 /* We need a spare DMA map for the RX ring. */ 1516 error = bus_dmamap_create(sc->xl_mtag, 0, &sc->xl_tmpmap); 1517 if (error) 1518 goto fail; 1519 1520 /* 1521 * Figure out the card type. 3c905B adapters have the 1522 * 'supportsNoTxLength' bit set in the capabilities 1523 * word in the EEPROM. 1524 * Note: my 3c575C cardbus card lies. It returns a value 1525 * of 0x1578 for its capabilities word, which is somewhat 1526 * nonsensical. Another way to distinguish a 3c90x chip 1527 * from a 3c90xB/C chip is to check for the 'supportsLargePackets' 1528 * bit. This will only be set for 3c90x boomerage chips. 1529 */ 1530 xl_read_eeprom(sc, (caddr_t)&sc->xl_caps, XL_EE_CAPS, 1, 0); 1531 if (sc->xl_caps & XL_CAPS_NO_TXLENGTH || 1532 !(sc->xl_caps & XL_CAPS_LARGE_PKTS)) 1533 sc->xl_type = XL_TYPE_905B; 1534 else 1535 sc->xl_type = XL_TYPE_90X; 1536 1537 ifp->if_softc = sc; 1538 ifp->if_mtu = ETHERMTU; 1539 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1540 ifp->if_ioctl = xl_ioctl; 1541 ifp->if_capabilities = 0; 1542 if (sc->xl_type == XL_TYPE_905B) { 1543 ifp->if_start = xl_start_90xB; 1544 ifp->if_capabilities |= IFCAP_HWCSUM; 1545 } else { 1546 ifp->if_start = xl_start; 1547 } 1548 ifp->if_watchdog = xl_watchdog; 1549 ifp->if_init = xl_init; 1550 ifp->if_baudrate = 10000000; 1551 ifq_set_maxlen(&ifp->if_snd, XL_TX_LIST_CNT - 1); 1552 ifq_set_ready(&ifp->if_snd); 1553 /* 1554 * NOTE: features disabled by default. This seems to corrupt 1555 * tx packet data one out of a million packets or so and then 1556 * generates a good checksum so the receiver doesn't 1557 * know the packet is bad 1558 */ 1559 ifp->if_capenable = 0; /*ifp->if_capabilities;*/ 1560 if (ifp->if_capenable & IFCAP_TXCSUM) 1561 ifp->if_hwassist = XL905B_CSUM_FEATURES; 1562 1563 /* 1564 * Now we have to see what sort of media we have. 1565 * This includes probing for an MII interace and a 1566 * possible PHY. 1567 */ 1568 XL_SEL_WIN(3); 1569 sc->xl_media = CSR_READ_2(sc, XL_W3_MEDIA_OPT); 1570 if (bootverbose) 1571 if_printf(ifp, "media options word: %x\n", sc->xl_media); 1572 1573 xl_read_eeprom(sc, (char *)&xcvr, XL_EE_ICFG_0, 2, 0); 1574 sc->xl_xcvr = xcvr[0] | xcvr[1] << 16; 1575 sc->xl_xcvr &= XL_ICFG_CONNECTOR_MASK; 1576 sc->xl_xcvr >>= XL_ICFG_CONNECTOR_BITS; 1577 1578 xl_mediacheck(sc); 1579 1580 if (sc->xl_media & XL_MEDIAOPT_MII || sc->xl_media & XL_MEDIAOPT_BTX 1581 || sc->xl_media & XL_MEDIAOPT_BT4) { 1582 if (bootverbose) 1583 if_printf(ifp, "found MII/AUTO\n"); 1584 xl_setcfg(sc); 1585 if (mii_phy_probe(dev, &sc->xl_miibus, 1586 xl_ifmedia_upd, xl_ifmedia_sts)) { 1587 if_printf(ifp, "no PHY found!\n"); 1588 error = ENXIO; 1589 goto fail; 1590 } 1591 1592 goto done; 1593 } 1594 1595 /* 1596 * Sanity check. If the user has selected "auto" and this isn't 1597 * a 10/100 card of some kind, we need to force the transceiver 1598 * type to something sane. 1599 */ 1600 if (sc->xl_xcvr == XL_XCVR_AUTO) 1601 xl_choose_xcvr(sc, bootverbose); 1602 1603 /* 1604 * Do ifmedia setup. 1605 */ 1606 if (sc->xl_media & XL_MEDIAOPT_BT) { 1607 if (bootverbose) 1608 if_printf(ifp, "found 10baseT\n"); 1609 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL); 1610 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T|IFM_HDX, 0, NULL); 1611 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX) 1612 ifmedia_add(&sc->ifmedia, 1613 IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL); 1614 } 1615 1616 if (sc->xl_media & (XL_MEDIAOPT_AUI|XL_MEDIAOPT_10FL)) { 1617 /* 1618 * Check for a 10baseFL board in disguise. 1619 */ 1620 if (sc->xl_type == XL_TYPE_905B && 1621 sc->xl_media == XL_MEDIAOPT_10FL) { 1622 if (bootverbose) 1623 if_printf(ifp, "found 10baseFL\n"); 1624 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_FL, 0, NULL); 1625 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_FL|IFM_HDX, 1626 0, NULL); 1627 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX) 1628 ifmedia_add(&sc->ifmedia, 1629 IFM_ETHER|IFM_10_FL|IFM_FDX, 0, NULL); 1630 } else { 1631 if (bootverbose) 1632 if_printf(ifp, "found AUI\n"); 1633 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_5, 0, NULL); 1634 } 1635 } 1636 1637 if (sc->xl_media & XL_MEDIAOPT_BNC) { 1638 if (bootverbose) 1639 if_printf(ifp, "found BNC\n"); 1640 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_2, 0, NULL); 1641 } 1642 1643 if (sc->xl_media & XL_MEDIAOPT_BFX) { 1644 if (bootverbose) 1645 if_printf(ifp, "found 100baseFX\n"); 1646 ifp->if_baudrate = 100000000; 1647 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_FX, 0, NULL); 1648 } 1649 1650 /* Choose a default media. */ 1651 switch(sc->xl_xcvr) { 1652 case XL_XCVR_10BT: 1653 media = IFM_ETHER|IFM_10_T; 1654 xl_setmode(sc, media); 1655 break; 1656 case XL_XCVR_AUI: 1657 if (sc->xl_type == XL_TYPE_905B && 1658 sc->xl_media == XL_MEDIAOPT_10FL) { 1659 media = IFM_ETHER|IFM_10_FL; 1660 xl_setmode(sc, media); 1661 } else { 1662 media = IFM_ETHER|IFM_10_5; 1663 xl_setmode(sc, media); 1664 } 1665 break; 1666 case XL_XCVR_COAX: 1667 media = IFM_ETHER|IFM_10_2; 1668 xl_setmode(sc, media); 1669 break; 1670 case XL_XCVR_AUTO: 1671 case XL_XCVR_100BTX: 1672 case XL_XCVR_MII: 1673 /* Chosen by miibus */ 1674 break; 1675 case XL_XCVR_100BFX: 1676 media = IFM_ETHER|IFM_100_FX; 1677 break; 1678 default: 1679 if_printf(ifp, "unknown XCVR type: %d\n", sc->xl_xcvr); 1680 /* 1681 * This will probably be wrong, but it prevents 1682 * the ifmedia code from panicking. 1683 */ 1684 media = IFM_ETHER|IFM_10_T; 1685 break; 1686 } 1687 1688 if (sc->xl_miibus == NULL) 1689 ifmedia_set(&sc->ifmedia, media); 1690 1691 done: 1692 1693 if (sc->xl_flags & XL_FLAG_NO_XCVR_PWR) { 1694 XL_SEL_WIN(0); 1695 CSR_WRITE_2(sc, XL_W0_MFG_ID, XL_NO_XCVR_PWR_MAGICBITS); 1696 } 1697 1698 /* 1699 * Call MI attach routine. 1700 */ 1701 ether_ifattach(ifp, eaddr); 1702 1703 /* 1704 * Tell the upper layer(s) we support long frames. 1705 */ 1706 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1707 1708 /* Hook interrupt last to avoid having to lock softc */ 1709 error = bus_setup_intr(dev, sc->xl_irq, INTR_TYPE_NET, 1710 xl_intr, sc, &sc->xl_intrhand, NULL); 1711 if (error) { 1712 if_printf(ifp, "couldn't set up irq\n"); 1713 ether_ifdetach(ifp); 1714 goto fail; 1715 } 1716 1717 fail: 1718 if (error) 1719 xl_detach(dev); 1720 1721 return(error); 1722 } 1723 1724 /* 1725 * Shutdown hardware and free up resources. This can be called any 1726 * time after the mutex has been initialized. It is called in both 1727 * the error case in attach and the normal detach case so it needs 1728 * to be careful about only freeing resources that have actually been 1729 * allocated. 1730 */ 1731 static int 1732 xl_detach(dev) 1733 device_t dev; 1734 { 1735 struct xl_softc *sc; 1736 struct ifnet *ifp; 1737 int rid, res; 1738 1739 sc = device_get_softc(dev); 1740 ifp = &sc->arpcom.ac_if; 1741 1742 if (sc->xl_flags & XL_FLAG_USE_MMIO) { 1743 rid = XL_PCI_LOMEM; 1744 res = SYS_RES_MEMORY; 1745 } else { 1746 rid = XL_PCI_LOIO; 1747 res = SYS_RES_IOPORT; 1748 } 1749 1750 crit_enter(); 1751 1752 /* 1753 * Only try to communicate with the device if we were able to map 1754 * the ports. This flag is set before ether_ifattach() so it also 1755 * governs our call to ether_ifdetach(). 1756 */ 1757 if (sc->xl_flags & XL_FLAG_ATTACH_MAPPED) { 1758 xl_reset(sc); 1759 xl_stop(sc); 1760 ether_ifdetach(ifp); 1761 } 1762 1763 if (sc->xl_miibus) 1764 device_delete_child(dev, sc->xl_miibus); 1765 bus_generic_detach(dev); 1766 ifmedia_removeall(&sc->ifmedia); 1767 1768 if (sc->xl_intrhand) 1769 bus_teardown_intr(dev, sc->xl_irq, sc->xl_intrhand); 1770 1771 crit_exit(); 1772 1773 if (sc->xl_irq) 1774 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->xl_irq); 1775 if (sc->xl_fres != NULL) 1776 bus_release_resource(dev, SYS_RES_MEMORY, 1777 XL_PCI_FUNCMEM, sc->xl_fres); 1778 if (sc->xl_res) 1779 bus_release_resource(dev, res, rid, sc->xl_res); 1780 1781 if (sc->xl_mtag) { 1782 bus_dmamap_destroy(sc->xl_mtag, sc->xl_tmpmap); 1783 bus_dma_tag_destroy(sc->xl_mtag); 1784 } 1785 if (sc->xl_ldata.xl_rx_tag) { 1786 bus_dmamap_unload(sc->xl_ldata.xl_rx_tag, 1787 sc->xl_ldata.xl_rx_dmamap); 1788 bus_dmamem_free(sc->xl_ldata.xl_rx_tag, sc->xl_ldata.xl_rx_list, 1789 sc->xl_ldata.xl_rx_dmamap); 1790 bus_dma_tag_destroy(sc->xl_ldata.xl_rx_tag); 1791 } 1792 if (sc->xl_ldata.xl_tx_tag) { 1793 bus_dmamap_unload(sc->xl_ldata.xl_tx_tag, 1794 sc->xl_ldata.xl_tx_dmamap); 1795 bus_dmamem_free(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_list, 1796 sc->xl_ldata.xl_tx_dmamap); 1797 bus_dma_tag_destroy(sc->xl_ldata.xl_tx_tag); 1798 } 1799 1800 return(0); 1801 } 1802 1803 /* 1804 * Initialize the transmit descriptors. 1805 */ 1806 static int 1807 xl_list_tx_init(sc) 1808 struct xl_softc *sc; 1809 { 1810 struct xl_chain_data *cd; 1811 struct xl_list_data *ld; 1812 int error, i; 1813 1814 cd = &sc->xl_cdata; 1815 ld = &sc->xl_ldata; 1816 for (i = 0; i < XL_TX_LIST_CNT; i++) { 1817 cd->xl_tx_chain[i].xl_ptr = &ld->xl_tx_list[i]; 1818 error = bus_dmamap_create(sc->xl_mtag, 0, 1819 &cd->xl_tx_chain[i].xl_map); 1820 if (error) 1821 return(error); 1822 cd->xl_tx_chain[i].xl_phys = ld->xl_tx_dmaaddr + 1823 i * sizeof(struct xl_list); 1824 if (i == (XL_TX_LIST_CNT - 1)) 1825 cd->xl_tx_chain[i].xl_next = NULL; 1826 else 1827 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[i + 1]; 1828 } 1829 1830 cd->xl_tx_free = &cd->xl_tx_chain[0]; 1831 cd->xl_tx_tail = cd->xl_tx_head = NULL; 1832 1833 bus_dmamap_sync(ld->xl_tx_tag, ld->xl_tx_dmamap, BUS_DMASYNC_PREWRITE); 1834 return(0); 1835 } 1836 1837 /* 1838 * Initialize the transmit descriptors. 1839 */ 1840 static int 1841 xl_list_tx_init_90xB(sc) 1842 struct xl_softc *sc; 1843 { 1844 struct xl_chain_data *cd; 1845 struct xl_list_data *ld; 1846 int error, i; 1847 1848 cd = &sc->xl_cdata; 1849 ld = &sc->xl_ldata; 1850 for (i = 0; i < XL_TX_LIST_CNT; i++) { 1851 cd->xl_tx_chain[i].xl_ptr = &ld->xl_tx_list[i]; 1852 error = bus_dmamap_create(sc->xl_mtag, 0, 1853 &cd->xl_tx_chain[i].xl_map); 1854 if (error) 1855 return(error); 1856 cd->xl_tx_chain[i].xl_phys = ld->xl_tx_dmaaddr + 1857 i * sizeof(struct xl_list); 1858 if (i == (XL_TX_LIST_CNT - 1)) 1859 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[0]; 1860 else 1861 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[i + 1]; 1862 if (i == 0) 1863 cd->xl_tx_chain[i].xl_prev = 1864 &cd->xl_tx_chain[XL_TX_LIST_CNT - 1]; 1865 else 1866 cd->xl_tx_chain[i].xl_prev = 1867 &cd->xl_tx_chain[i - 1]; 1868 } 1869 1870 bzero(ld->xl_tx_list, XL_TX_LIST_SZ); 1871 ld->xl_tx_list[0].xl_status = htole32(XL_TXSTAT_EMPTY); 1872 1873 cd->xl_tx_prod = 1; 1874 cd->xl_tx_cons = 1; 1875 cd->xl_tx_cnt = 0; 1876 1877 bus_dmamap_sync(ld->xl_tx_tag, ld->xl_tx_dmamap, BUS_DMASYNC_PREWRITE); 1878 return(0); 1879 } 1880 1881 /* 1882 * Initialize the RX descriptors and allocate mbufs for them. Note that 1883 * we arrange the descriptors in a closed ring, so that the last descriptor 1884 * points back to the first. 1885 */ 1886 static int 1887 xl_list_rx_init(sc) 1888 struct xl_softc *sc; 1889 { 1890 struct xl_chain_data *cd; 1891 struct xl_list_data *ld; 1892 int error, i, next; 1893 u_int32_t nextptr; 1894 1895 cd = &sc->xl_cdata; 1896 ld = &sc->xl_ldata; 1897 1898 for (i = 0; i < XL_RX_LIST_CNT; i++) { 1899 cd->xl_rx_chain[i].xl_ptr = &ld->xl_rx_list[i]; 1900 error = bus_dmamap_create(sc->xl_mtag, 0, 1901 &cd->xl_rx_chain[i].xl_map); 1902 if (error) 1903 return(error); 1904 error = xl_newbuf(sc, &cd->xl_rx_chain[i]); 1905 if (error) 1906 return(error); 1907 if (i == (XL_RX_LIST_CNT - 1)) 1908 next = 0; 1909 else 1910 next = i + 1; 1911 nextptr = ld->xl_rx_dmaaddr + 1912 next * sizeof(struct xl_list_onefrag); 1913 cd->xl_rx_chain[i].xl_next = &cd->xl_rx_chain[next]; 1914 ld->xl_rx_list[i].xl_next = htole32(nextptr); 1915 } 1916 1917 bus_dmamap_sync(ld->xl_rx_tag, ld->xl_rx_dmamap, BUS_DMASYNC_PREWRITE); 1918 cd->xl_rx_head = &cd->xl_rx_chain[0]; 1919 1920 return(0); 1921 } 1922 1923 /* 1924 * Initialize an RX descriptor and attach an MBUF cluster. 1925 * If we fail to do so, we need to leave the old mbuf and 1926 * the old DMA map untouched so that it can be reused. 1927 */ 1928 static int 1929 xl_newbuf(sc, c) 1930 struct xl_softc *sc; 1931 struct xl_chain_onefrag *c; 1932 { 1933 struct mbuf *m_new = NULL; 1934 bus_dmamap_t map; 1935 int error; 1936 u_int32_t baddr; 1937 1938 m_new = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR); 1939 if (m_new == NULL) 1940 return(ENOBUFS); 1941 1942 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1943 1944 /* Force longword alignment for packet payload. */ 1945 m_adj(m_new, ETHER_ALIGN); 1946 1947 error = bus_dmamap_load_mbuf(sc->xl_mtag, sc->xl_tmpmap, m_new, 1948 xl_dma_map_rxbuf, &baddr, BUS_DMA_NOWAIT); 1949 if (error) { 1950 m_freem(m_new); 1951 if_printf(&sc->arpcom.ac_if, "can't map mbuf (error %d)\n", 1952 error); 1953 return(error); 1954 } 1955 1956 bus_dmamap_unload(sc->xl_mtag, c->xl_map); 1957 map = c->xl_map; 1958 c->xl_map = sc->xl_tmpmap; 1959 sc->xl_tmpmap = map; 1960 c->xl_mbuf = m_new; 1961 c->xl_ptr->xl_frag.xl_len = htole32(m_new->m_len | XL_LAST_FRAG); 1962 c->xl_ptr->xl_status = 0; 1963 c->xl_ptr->xl_frag.xl_addr = htole32(baddr); 1964 bus_dmamap_sync(sc->xl_mtag, c->xl_map, BUS_DMASYNC_PREREAD); 1965 return(0); 1966 } 1967 1968 static int 1969 xl_rx_resync(sc) 1970 struct xl_softc *sc; 1971 { 1972 struct xl_chain_onefrag *pos; 1973 int i; 1974 1975 pos = sc->xl_cdata.xl_rx_head; 1976 1977 for (i = 0; i < XL_RX_LIST_CNT; i++) { 1978 if (pos->xl_ptr->xl_status) 1979 break; 1980 pos = pos->xl_next; 1981 } 1982 1983 if (i == XL_RX_LIST_CNT) 1984 return(0); 1985 1986 sc->xl_cdata.xl_rx_head = pos; 1987 1988 return(EAGAIN); 1989 } 1990 1991 /* 1992 * A frame has been uploaded: pass the resulting mbuf chain up to 1993 * the higher level protocols. 1994 */ 1995 static void 1996 xl_rxeof(sc) 1997 struct xl_softc *sc; 1998 { 1999 struct mbuf *m; 2000 struct ifnet *ifp; 2001 struct xl_chain_onefrag *cur_rx; 2002 int total_len = 0; 2003 u_int32_t rxstat; 2004 2005 ifp = &sc->arpcom.ac_if; 2006 2007 again: 2008 2009 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag, sc->xl_ldata.xl_rx_dmamap, 2010 BUS_DMASYNC_POSTREAD); 2011 while((rxstat = le32toh(sc->xl_cdata.xl_rx_head->xl_ptr->xl_status))) { 2012 cur_rx = sc->xl_cdata.xl_rx_head; 2013 sc->xl_cdata.xl_rx_head = cur_rx->xl_next; 2014 total_len = rxstat & XL_RXSTAT_LENMASK; 2015 2016 /* 2017 * Since we have told the chip to allow large frames, 2018 * we need to trap giant frame errors in software. We allow 2019 * a little more than the normal frame size to account for 2020 * frames with VLAN tags. 2021 */ 2022 if (total_len > XL_MAX_FRAMELEN) 2023 rxstat |= (XL_RXSTAT_UP_ERROR|XL_RXSTAT_OVERSIZE); 2024 2025 /* 2026 * If an error occurs, update stats, clear the 2027 * status word and leave the mbuf cluster in place: 2028 * it should simply get re-used next time this descriptor 2029 * comes up in the ring. 2030 */ 2031 if (rxstat & XL_RXSTAT_UP_ERROR) { 2032 ifp->if_ierrors++; 2033 cur_rx->xl_ptr->xl_status = 0; 2034 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag, 2035 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE); 2036 continue; 2037 } 2038 2039 /* 2040 * If the error bit was not set, the upload complete 2041 * bit should be set which means we have a valid packet. 2042 * If not, something truly strange has happened. 2043 */ 2044 if (!(rxstat & XL_RXSTAT_UP_CMPLT)) { 2045 if_printf(ifp, 2046 "bad receive status -- packet dropped\n"); 2047 ifp->if_ierrors++; 2048 cur_rx->xl_ptr->xl_status = 0; 2049 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag, 2050 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE); 2051 continue; 2052 } 2053 2054 /* No errors; receive the packet. */ 2055 bus_dmamap_sync(sc->xl_mtag, cur_rx->xl_map, 2056 BUS_DMASYNC_POSTREAD); 2057 m = cur_rx->xl_mbuf; 2058 2059 /* 2060 * Try to conjure up a new mbuf cluster. If that 2061 * fails, it means we have an out of memory condition and 2062 * should leave the buffer in place and continue. This will 2063 * result in a lost packet, but there's little else we 2064 * can do in this situation. 2065 */ 2066 if (xl_newbuf(sc, cur_rx)) { 2067 ifp->if_ierrors++; 2068 cur_rx->xl_ptr->xl_status = 0; 2069 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag, 2070 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE); 2071 continue; 2072 } 2073 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag, 2074 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE); 2075 2076 ifp->if_ipackets++; 2077 m->m_pkthdr.rcvif = ifp; 2078 m->m_pkthdr.len = m->m_len = total_len; 2079 2080 if (ifp->if_capenable & IFCAP_RXCSUM) { 2081 /* Do IP checksum checking. */ 2082 if (rxstat & XL_RXSTAT_IPCKOK) 2083 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 2084 if (!(rxstat & XL_RXSTAT_IPCKERR)) 2085 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 2086 if ((rxstat & XL_RXSTAT_TCPCOK && 2087 !(rxstat & XL_RXSTAT_TCPCKERR)) || 2088 (rxstat & XL_RXSTAT_UDPCKOK && 2089 !(rxstat & XL_RXSTAT_UDPCKERR))) { 2090 m->m_pkthdr.csum_flags |= 2091 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 2092 m->m_pkthdr.csum_data = 0xffff; 2093 } 2094 } 2095 2096 (*ifp->if_input)(ifp, m); 2097 } 2098 2099 /* 2100 * Handle the 'end of channel' condition. When the upload 2101 * engine hits the end of the RX ring, it will stall. This 2102 * is our cue to flush the RX ring, reload the uplist pointer 2103 * register and unstall the engine. 2104 * XXX This is actually a little goofy. With the ThunderLAN 2105 * chip, you get an interrupt when the receiver hits the end 2106 * of the receive ring, which tells you exactly when you 2107 * you need to reload the ring pointer. Here we have to 2108 * fake it. I'm mad at myself for not being clever enough 2109 * to avoid the use of a goto here. 2110 */ 2111 if (CSR_READ_4(sc, XL_UPLIST_PTR) == 0 || 2112 CSR_READ_4(sc, XL_UPLIST_STATUS) & XL_PKTSTAT_UP_STALLED) { 2113 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_STALL); 2114 xl_wait(sc); 2115 CSR_WRITE_4(sc, XL_UPLIST_PTR, sc->xl_ldata.xl_rx_dmaaddr); 2116 sc->xl_cdata.xl_rx_head = &sc->xl_cdata.xl_rx_chain[0]; 2117 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_UNSTALL); 2118 goto again; 2119 } 2120 2121 return; 2122 } 2123 2124 /* 2125 * A frame was downloaded to the chip. It's safe for us to clean up 2126 * the list buffers. 2127 */ 2128 static void 2129 xl_txeof(sc) 2130 struct xl_softc *sc; 2131 { 2132 struct xl_chain *cur_tx; 2133 struct ifnet *ifp; 2134 2135 ifp = &sc->arpcom.ac_if; 2136 2137 /* Clear the timeout timer. */ 2138 ifp->if_timer = 0; 2139 2140 /* 2141 * Go through our tx list and free mbufs for those 2142 * frames that have been uploaded. Note: the 3c905B 2143 * sets a special bit in the status word to let us 2144 * know that a frame has been downloaded, but the 2145 * original 3c900/3c905 adapters don't do that. 2146 * Consequently, we have to use a different test if 2147 * xl_type != XL_TYPE_905B. 2148 */ 2149 while(sc->xl_cdata.xl_tx_head != NULL) { 2150 cur_tx = sc->xl_cdata.xl_tx_head; 2151 2152 if (CSR_READ_4(sc, XL_DOWNLIST_PTR)) 2153 break; 2154 2155 sc->xl_cdata.xl_tx_head = cur_tx->xl_next; 2156 bus_dmamap_sync(sc->xl_mtag, cur_tx->xl_map, 2157 BUS_DMASYNC_POSTWRITE); 2158 bus_dmamap_unload(sc->xl_mtag, cur_tx->xl_map); 2159 m_freem(cur_tx->xl_mbuf); 2160 cur_tx->xl_mbuf = NULL; 2161 ifp->if_opackets++; 2162 2163 cur_tx->xl_next = sc->xl_cdata.xl_tx_free; 2164 sc->xl_cdata.xl_tx_free = cur_tx; 2165 } 2166 2167 if (sc->xl_cdata.xl_tx_head == NULL) { 2168 ifp->if_flags &= ~IFF_OACTIVE; 2169 sc->xl_cdata.xl_tx_tail = NULL; 2170 } else { 2171 if (CSR_READ_4(sc, XL_DMACTL) & XL_DMACTL_DOWN_STALLED || 2172 !CSR_READ_4(sc, XL_DOWNLIST_PTR)) { 2173 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, 2174 sc->xl_cdata.xl_tx_head->xl_phys); 2175 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); 2176 } 2177 } 2178 2179 return; 2180 } 2181 2182 static void 2183 xl_txeof_90xB(sc) 2184 struct xl_softc *sc; 2185 { 2186 struct xl_chain *cur_tx = NULL; 2187 struct ifnet *ifp; 2188 int idx; 2189 2190 ifp = &sc->arpcom.ac_if; 2191 2192 bus_dmamap_sync(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_dmamap, 2193 BUS_DMASYNC_POSTREAD); 2194 idx = sc->xl_cdata.xl_tx_cons; 2195 while(idx != sc->xl_cdata.xl_tx_prod) { 2196 2197 cur_tx = &sc->xl_cdata.xl_tx_chain[idx]; 2198 2199 if (!(le32toh(cur_tx->xl_ptr->xl_status) & 2200 XL_TXSTAT_DL_COMPLETE)) 2201 break; 2202 2203 if (cur_tx->xl_mbuf != NULL) { 2204 bus_dmamap_sync(sc->xl_mtag, cur_tx->xl_map, 2205 BUS_DMASYNC_POSTWRITE); 2206 bus_dmamap_unload(sc->xl_mtag, cur_tx->xl_map); 2207 m_freem(cur_tx->xl_mbuf); 2208 cur_tx->xl_mbuf = NULL; 2209 } 2210 2211 ifp->if_opackets++; 2212 2213 sc->xl_cdata.xl_tx_cnt--; 2214 XL_INC(idx, XL_TX_LIST_CNT); 2215 ifp->if_timer = 0; 2216 } 2217 2218 sc->xl_cdata.xl_tx_cons = idx; 2219 2220 if (cur_tx != NULL) 2221 ifp->if_flags &= ~IFF_OACTIVE; 2222 2223 return; 2224 } 2225 2226 /* 2227 * TX 'end of channel' interrupt handler. Actually, we should 2228 * only get a 'TX complete' interrupt if there's a transmit error, 2229 * so this is really TX error handler. 2230 */ 2231 static void 2232 xl_txeoc(sc) 2233 struct xl_softc *sc; 2234 { 2235 struct ifnet *ifp = &sc->arpcom.ac_if; 2236 u_int8_t txstat; 2237 2238 while((txstat = CSR_READ_1(sc, XL_TX_STATUS))) { 2239 if (txstat & XL_TXSTATUS_UNDERRUN || 2240 txstat & XL_TXSTATUS_JABBER || 2241 txstat & XL_TXSTATUS_RECLAIM) { 2242 if_printf(ifp, "transmission error: %x\n", txstat); 2243 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); 2244 xl_wait(sc); 2245 if (sc->xl_type == XL_TYPE_905B) { 2246 if (sc->xl_cdata.xl_tx_cnt) { 2247 int i; 2248 struct xl_chain *c; 2249 i = sc->xl_cdata.xl_tx_cons; 2250 c = &sc->xl_cdata.xl_tx_chain[i]; 2251 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, 2252 c->xl_phys); 2253 CSR_WRITE_1(sc, XL_DOWN_POLL, 64); 2254 } 2255 } else { 2256 if (sc->xl_cdata.xl_tx_head != NULL) 2257 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, 2258 sc->xl_cdata.xl_tx_head->xl_phys); 2259 } 2260 /* 2261 * Remember to set this for the 2262 * first generation 3c90X chips. 2263 */ 2264 CSR_WRITE_1(sc, XL_TX_FREETHRESH, XL_PACKET_SIZE >> 8); 2265 if (txstat & XL_TXSTATUS_UNDERRUN && 2266 sc->xl_tx_thresh < XL_PACKET_SIZE) { 2267 sc->xl_tx_thresh += XL_MIN_FRAMELEN; 2268 if_printf(ifp, "tx underrun, increasing tx start" 2269 " threshold to %d bytes\n", 2270 sc->xl_tx_thresh); 2271 } 2272 CSR_WRITE_2(sc, XL_COMMAND, 2273 XL_CMD_TX_SET_START|sc->xl_tx_thresh); 2274 if (sc->xl_type == XL_TYPE_905B) { 2275 CSR_WRITE_2(sc, XL_COMMAND, 2276 XL_CMD_SET_TX_RECLAIM|(XL_PACKET_SIZE >> 4)); 2277 } 2278 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE); 2279 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); 2280 } else { 2281 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE); 2282 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); 2283 } 2284 /* 2285 * Write an arbitrary byte to the TX_STATUS register 2286 * to clear this interrupt/error and advance to the next. 2287 */ 2288 CSR_WRITE_1(sc, XL_TX_STATUS, 0x01); 2289 } 2290 2291 return; 2292 } 2293 2294 static void 2295 xl_intr(arg) 2296 void *arg; 2297 { 2298 struct xl_softc *sc; 2299 struct ifnet *ifp; 2300 u_int16_t status; 2301 2302 sc = arg; 2303 ifp = &sc->arpcom.ac_if; 2304 2305 while((status = CSR_READ_2(sc, XL_STATUS)) & XL_INTRS && status != 0xFFFF) { 2306 2307 CSR_WRITE_2(sc, XL_COMMAND, 2308 XL_CMD_INTR_ACK|(status & XL_INTRS)); 2309 2310 if (status & XL_STAT_UP_COMPLETE) { 2311 int curpkts; 2312 2313 curpkts = ifp->if_ipackets; 2314 xl_rxeof(sc); 2315 if (curpkts == ifp->if_ipackets) { 2316 while (xl_rx_resync(sc)) 2317 xl_rxeof(sc); 2318 } 2319 } 2320 2321 if (status & XL_STAT_DOWN_COMPLETE) { 2322 if (sc->xl_type == XL_TYPE_905B) 2323 xl_txeof_90xB(sc); 2324 else 2325 xl_txeof(sc); 2326 } 2327 2328 if (status & XL_STAT_TX_COMPLETE) { 2329 ifp->if_oerrors++; 2330 xl_txeoc(sc); 2331 } 2332 2333 if (status & XL_STAT_ADFAIL) { 2334 xl_reset(sc); 2335 xl_init(sc); 2336 } 2337 2338 if (status & XL_STAT_STATSOFLOW) { 2339 sc->xl_stats_no_timeout = 1; 2340 xl_stats_update(sc); 2341 sc->xl_stats_no_timeout = 0; 2342 } 2343 } 2344 2345 if (!ifq_is_empty(&ifp->if_snd)) 2346 (*ifp->if_start)(ifp); 2347 2348 return; 2349 } 2350 2351 static void 2352 xl_stats_update(xsc) 2353 void *xsc; 2354 { 2355 struct xl_softc *sc; 2356 struct ifnet *ifp; 2357 struct xl_stats xl_stats; 2358 u_int8_t *p; 2359 int i; 2360 struct mii_data *mii = NULL; 2361 2362 bzero((char *)&xl_stats, sizeof(struct xl_stats)); 2363 2364 sc = xsc; 2365 ifp = &sc->arpcom.ac_if; 2366 if (sc->xl_miibus != NULL) 2367 mii = device_get_softc(sc->xl_miibus); 2368 2369 p = (u_int8_t *)&xl_stats; 2370 2371 /* Read all the stats registers. */ 2372 XL_SEL_WIN(6); 2373 2374 for (i = 0; i < 16; i++) 2375 *p++ = CSR_READ_1(sc, XL_W6_CARRIER_LOST + i); 2376 2377 ifp->if_ierrors += xl_stats.xl_rx_overrun; 2378 2379 ifp->if_collisions += xl_stats.xl_tx_multi_collision + 2380 xl_stats.xl_tx_single_collision + 2381 xl_stats.xl_tx_late_collision; 2382 2383 /* 2384 * Boomerang and cyclone chips have an extra stats counter 2385 * in window 4 (BadSSD). We have to read this too in order 2386 * to clear out all the stats registers and avoid a statsoflow 2387 * interrupt. 2388 */ 2389 XL_SEL_WIN(4); 2390 CSR_READ_1(sc, XL_W4_BADSSD); 2391 2392 if ((mii != NULL) && (!sc->xl_stats_no_timeout)) 2393 mii_tick(mii); 2394 2395 XL_SEL_WIN(7); 2396 2397 if (!sc->xl_stats_no_timeout) 2398 callout_reset(&sc->xl_stat_timer, hz, xl_stats_update, sc); 2399 2400 return; 2401 } 2402 2403 /* 2404 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 2405 * pointers to the fragment pointers. 2406 */ 2407 static int 2408 xl_encap(sc, c, m_head) 2409 struct xl_softc *sc; 2410 struct xl_chain *c; 2411 struct mbuf *m_head; 2412 { 2413 int error; 2414 u_int32_t status; 2415 struct ifnet *ifp; 2416 2417 ifp = &sc->arpcom.ac_if; 2418 2419 /* 2420 * Start packing the mbufs in this chain into 2421 * the fragment pointers. Stop when we run out 2422 * of fragments or hit the end of the mbuf chain. 2423 */ 2424 error = bus_dmamap_load_mbuf(sc->xl_mtag, c->xl_map, m_head, 2425 xl_dma_map_txbuf, c->xl_ptr, BUS_DMA_NOWAIT); 2426 2427 if (error && error != EFBIG) { 2428 m_freem(m_head); 2429 if_printf(ifp, "can't map mbuf (error %d)\n", error); 2430 return(1); 2431 } 2432 2433 /* 2434 * Handle special case: we used up all 63 fragments, 2435 * but we have more mbufs left in the chain. Copy the 2436 * data into an mbuf cluster. Note that we don't 2437 * bother clearing the values in the other fragment 2438 * pointers/counters; it wouldn't gain us anything, 2439 * and would waste cycles. 2440 */ 2441 if (error) { 2442 struct mbuf *m_new; 2443 2444 m_new = m_defrag(m_head, MB_DONTWAIT); 2445 if (m_new == NULL) { 2446 m_freem(m_head); 2447 return(1); 2448 } else { 2449 m_head = m_new; 2450 } 2451 2452 error = bus_dmamap_load_mbuf(sc->xl_mtag, c->xl_map, 2453 m_head, xl_dma_map_txbuf, c->xl_ptr, BUS_DMA_NOWAIT); 2454 if (error) { 2455 m_freem(m_head); 2456 if_printf(ifp, "can't map mbuf (error %d)\n", error); 2457 return(1); 2458 } 2459 } 2460 2461 if (sc->xl_type == XL_TYPE_905B) { 2462 status = XL_TXSTAT_RND_DEFEAT; 2463 2464 if (m_head->m_pkthdr.csum_flags) { 2465 if (m_head->m_pkthdr.csum_flags & CSUM_IP) 2466 status |= XL_TXSTAT_IPCKSUM; 2467 if (m_head->m_pkthdr.csum_flags & CSUM_TCP) 2468 status |= XL_TXSTAT_TCPCKSUM; 2469 if (m_head->m_pkthdr.csum_flags & CSUM_UDP) 2470 status |= XL_TXSTAT_UDPCKSUM; 2471 } 2472 c->xl_ptr->xl_status = htole32(status); 2473 } 2474 2475 c->xl_mbuf = m_head; 2476 bus_dmamap_sync(sc->xl_mtag, c->xl_map, BUS_DMASYNC_PREWRITE); 2477 return(0); 2478 } 2479 2480 /* 2481 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 2482 * to the mbuf data regions directly in the transmit lists. We also save a 2483 * copy of the pointers since the transmit list fragment pointers are 2484 * physical addresses. 2485 */ 2486 static void 2487 xl_start(ifp) 2488 struct ifnet *ifp; 2489 { 2490 struct xl_softc *sc; 2491 struct mbuf *m_head = NULL; 2492 struct xl_chain *prev = NULL, *cur_tx = NULL, *start_tx; 2493 struct xl_chain *prev_tx; 2494 u_int32_t status; 2495 int error; 2496 2497 sc = ifp->if_softc; 2498 /* 2499 * Check for an available queue slot. If there are none, 2500 * punt. 2501 */ 2502 if (sc->xl_cdata.xl_tx_free == NULL) { 2503 xl_txeoc(sc); 2504 xl_txeof(sc); 2505 if (sc->xl_cdata.xl_tx_free == NULL) { 2506 ifp->if_flags |= IFF_OACTIVE; 2507 return; 2508 } 2509 } 2510 2511 start_tx = sc->xl_cdata.xl_tx_free; 2512 2513 while(sc->xl_cdata.xl_tx_free != NULL) { 2514 m_head = ifq_dequeue(&ifp->if_snd); 2515 if (m_head == NULL) 2516 break; 2517 2518 /* Pick a descriptor off the free list. */ 2519 prev_tx = cur_tx; 2520 cur_tx = sc->xl_cdata.xl_tx_free; 2521 2522 /* Pack the data into the descriptor. */ 2523 error = xl_encap(sc, cur_tx, m_head); 2524 if (error) { 2525 cur_tx = prev_tx; 2526 continue; 2527 } 2528 2529 sc->xl_cdata.xl_tx_free = cur_tx->xl_next; 2530 cur_tx->xl_next = NULL; 2531 2532 /* Chain it together. */ 2533 if (prev != NULL) { 2534 prev->xl_next = cur_tx; 2535 prev->xl_ptr->xl_next = htole32(cur_tx->xl_phys); 2536 } 2537 prev = cur_tx; 2538 2539 BPF_MTAP(ifp, cur_tx->xl_mbuf); 2540 } 2541 2542 /* 2543 * If there are no packets queued, bail. 2544 */ 2545 if (cur_tx == NULL) { 2546 return; 2547 } 2548 2549 /* 2550 * Place the request for the upload interrupt 2551 * in the last descriptor in the chain. This way, if 2552 * we're chaining several packets at once, we'll only 2553 * get an interupt once for the whole chain rather than 2554 * once for each packet. 2555 */ 2556 cur_tx->xl_ptr->xl_status = htole32(le32toh(cur_tx->xl_ptr->xl_status) | 2557 XL_TXSTAT_DL_INTR); 2558 bus_dmamap_sync(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_dmamap, 2559 BUS_DMASYNC_PREWRITE); 2560 2561 /* 2562 * Queue the packets. If the TX channel is clear, update 2563 * the downlist pointer register. 2564 */ 2565 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_STALL); 2566 xl_wait(sc); 2567 2568 if (sc->xl_cdata.xl_tx_head != NULL) { 2569 sc->xl_cdata.xl_tx_tail->xl_next = start_tx; 2570 sc->xl_cdata.xl_tx_tail->xl_ptr->xl_next = 2571 htole32(start_tx->xl_phys); 2572 status = sc->xl_cdata.xl_tx_tail->xl_ptr->xl_status; 2573 sc->xl_cdata.xl_tx_tail->xl_ptr->xl_status = 2574 htole32(le32toh(status) & ~XL_TXSTAT_DL_INTR); 2575 sc->xl_cdata.xl_tx_tail = cur_tx; 2576 } else { 2577 sc->xl_cdata.xl_tx_head = start_tx; 2578 sc->xl_cdata.xl_tx_tail = cur_tx; 2579 } 2580 if (!CSR_READ_4(sc, XL_DOWNLIST_PTR)) 2581 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, start_tx->xl_phys); 2582 2583 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); 2584 2585 XL_SEL_WIN(7); 2586 2587 /* 2588 * Set a timeout in case the chip goes out to lunch. 2589 */ 2590 ifp->if_timer = 5; 2591 2592 /* 2593 * XXX Under certain conditions, usually on slower machines 2594 * where interrupts may be dropped, it's possible for the 2595 * adapter to chew up all the buffers in the receive ring 2596 * and stall, without us being able to do anything about it. 2597 * To guard against this, we need to make a pass over the 2598 * RX queue to make sure there aren't any packets pending. 2599 * Doing it here means we can flush the receive ring at the 2600 * same time the chip is DMAing the transmit descriptors we 2601 * just gave it. 2602 * 2603 * 3Com goes to some lengths to emphasize the Parallel Tasking (tm) 2604 * nature of their chips in all their marketing literature; 2605 * we may as well take advantage of it. :) 2606 */ 2607 xl_rxeof(sc); 2608 2609 return; 2610 } 2611 2612 static void 2613 xl_start_90xB(ifp) 2614 struct ifnet *ifp; 2615 { 2616 struct xl_softc *sc; 2617 struct mbuf *m_head = NULL; 2618 struct xl_chain *prev = NULL, *cur_tx = NULL, *start_tx; 2619 struct xl_chain *prev_tx; 2620 int error, idx; 2621 2622 sc = ifp->if_softc; 2623 2624 if (ifp->if_flags & IFF_OACTIVE) { 2625 return; 2626 } 2627 2628 idx = sc->xl_cdata.xl_tx_prod; 2629 start_tx = &sc->xl_cdata.xl_tx_chain[idx]; 2630 2631 while (sc->xl_cdata.xl_tx_chain[idx].xl_mbuf == NULL) { 2632 2633 if ((XL_TX_LIST_CNT - sc->xl_cdata.xl_tx_cnt) < 3) { 2634 ifp->if_flags |= IFF_OACTIVE; 2635 break; 2636 } 2637 2638 m_head = ifq_dequeue(&ifp->if_snd); 2639 if (m_head == NULL) 2640 break; 2641 2642 prev_tx = cur_tx; 2643 cur_tx = &sc->xl_cdata.xl_tx_chain[idx]; 2644 2645 /* Pack the data into the descriptor. */ 2646 error = xl_encap(sc, cur_tx, m_head); 2647 if (error) { 2648 cur_tx = prev_tx; 2649 continue; 2650 } 2651 2652 /* Chain it together. */ 2653 if (prev != NULL) 2654 prev->xl_ptr->xl_next = htole32(cur_tx->xl_phys); 2655 prev = cur_tx; 2656 2657 BPF_MTAP(ifp, cur_tx->xl_mbuf); 2658 2659 XL_INC(idx, XL_TX_LIST_CNT); 2660 sc->xl_cdata.xl_tx_cnt++; 2661 } 2662 2663 /* 2664 * If there are no packets queued, bail. 2665 */ 2666 if (cur_tx == NULL) { 2667 return; 2668 } 2669 2670 /* 2671 * Place the request for the upload interrupt 2672 * in the last descriptor in the chain. This way, if 2673 * we're chaining several packets at once, we'll only 2674 * get an interupt once for the whole chain rather than 2675 * once for each packet. 2676 */ 2677 cur_tx->xl_ptr->xl_status = htole32(le32toh(cur_tx->xl_ptr->xl_status) | 2678 XL_TXSTAT_DL_INTR); 2679 bus_dmamap_sync(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_dmamap, 2680 BUS_DMASYNC_PREWRITE); 2681 2682 /* Start transmission */ 2683 sc->xl_cdata.xl_tx_prod = idx; 2684 start_tx->xl_prev->xl_ptr->xl_next = htole32(start_tx->xl_phys); 2685 2686 /* 2687 * Set a timeout in case the chip goes out to lunch. 2688 */ 2689 ifp->if_timer = 5; 2690 2691 return; 2692 } 2693 2694 static void 2695 xl_init(xsc) 2696 void *xsc; 2697 { 2698 struct xl_softc *sc = xsc; 2699 struct ifnet *ifp = &sc->arpcom.ac_if; 2700 int error, i; 2701 u_int16_t rxfilt = 0; 2702 struct mii_data *mii = NULL; 2703 2704 crit_enter(); 2705 2706 /* 2707 * Cancel pending I/O and free all RX/TX buffers. 2708 */ 2709 xl_stop(sc); 2710 2711 if (sc->xl_miibus == NULL) { 2712 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET); 2713 xl_wait(sc); 2714 } 2715 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); 2716 xl_wait(sc); 2717 DELAY(10000); 2718 2719 if (sc->xl_miibus != NULL) 2720 mii = device_get_softc(sc->xl_miibus); 2721 2722 /* Init our MAC address */ 2723 XL_SEL_WIN(2); 2724 for (i = 0; i < ETHER_ADDR_LEN; i++) { 2725 CSR_WRITE_1(sc, XL_W2_STATION_ADDR_LO + i, 2726 sc->arpcom.ac_enaddr[i]); 2727 } 2728 2729 /* Clear the station mask. */ 2730 for (i = 0; i < 3; i++) 2731 CSR_WRITE_2(sc, XL_W2_STATION_MASK_LO + (i * 2), 0); 2732 #ifdef notdef 2733 /* Reset TX and RX. */ 2734 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET); 2735 xl_wait(sc); 2736 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); 2737 xl_wait(sc); 2738 #endif 2739 /* Init circular RX list. */ 2740 error = xl_list_rx_init(sc); 2741 if (error) { 2742 if_printf(ifp, "initialization of the rx ring failed (%d)\n", 2743 error); 2744 xl_stop(sc); 2745 crit_exit(); 2746 return; 2747 } 2748 2749 /* Init TX descriptors. */ 2750 if (sc->xl_type == XL_TYPE_905B) 2751 error = xl_list_tx_init_90xB(sc); 2752 else 2753 error = xl_list_tx_init(sc); 2754 if (error) { 2755 if_printf(ifp, "initialization of the tx ring failed (%d)\n", 2756 error); 2757 xl_stop(sc); 2758 crit_exit(); 2759 return; 2760 } 2761 2762 /* 2763 * Set the TX freethresh value. 2764 * Note that this has no effect on 3c905B "cyclone" 2765 * cards but is required for 3c900/3c905 "boomerang" 2766 * cards in order to enable the download engine. 2767 */ 2768 CSR_WRITE_1(sc, XL_TX_FREETHRESH, XL_PACKET_SIZE >> 8); 2769 2770 /* Set the TX start threshold for best performance. */ 2771 sc->xl_tx_thresh = XL_MIN_FRAMELEN; 2772 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_SET_START|sc->xl_tx_thresh); 2773 2774 /* 2775 * If this is a 3c905B, also set the tx reclaim threshold. 2776 * This helps cut down on the number of tx reclaim errors 2777 * that could happen on a busy network. The chip multiplies 2778 * the register value by 16 to obtain the actual threshold 2779 * in bytes, so we divide by 16 when setting the value here. 2780 * The existing threshold value can be examined by reading 2781 * the register at offset 9 in window 5. 2782 */ 2783 if (sc->xl_type == XL_TYPE_905B) { 2784 CSR_WRITE_2(sc, XL_COMMAND, 2785 XL_CMD_SET_TX_RECLAIM|(XL_PACKET_SIZE >> 4)); 2786 } 2787 2788 /* Set RX filter bits. */ 2789 XL_SEL_WIN(5); 2790 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER); 2791 2792 /* Set the individual bit to receive frames for this host only. */ 2793 rxfilt |= XL_RXFILTER_INDIVIDUAL; 2794 2795 /* If we want promiscuous mode, set the allframes bit. */ 2796 if (ifp->if_flags & IFF_PROMISC) { 2797 rxfilt |= XL_RXFILTER_ALLFRAMES; 2798 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 2799 } else { 2800 rxfilt &= ~XL_RXFILTER_ALLFRAMES; 2801 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 2802 } 2803 2804 /* 2805 * Set capture broadcast bit to capture broadcast frames. 2806 */ 2807 if (ifp->if_flags & IFF_BROADCAST) { 2808 rxfilt |= XL_RXFILTER_BROADCAST; 2809 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 2810 } else { 2811 rxfilt &= ~XL_RXFILTER_BROADCAST; 2812 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 2813 } 2814 2815 /* 2816 * Program the multicast filter, if necessary. 2817 */ 2818 if (sc->xl_type == XL_TYPE_905B) 2819 xl_setmulti_hash(sc); 2820 else 2821 xl_setmulti(sc); 2822 2823 /* 2824 * Load the address of the RX list. We have to 2825 * stall the upload engine before we can manipulate 2826 * the uplist pointer register, then unstall it when 2827 * we're finished. We also have to wait for the 2828 * stall command to complete before proceeding. 2829 * Note that we have to do this after any RX resets 2830 * have completed since the uplist register is cleared 2831 * by a reset. 2832 */ 2833 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_STALL); 2834 xl_wait(sc); 2835 CSR_WRITE_4(sc, XL_UPLIST_PTR, sc->xl_ldata.xl_rx_dmaaddr); 2836 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_UNSTALL); 2837 xl_wait(sc); 2838 2839 2840 if (sc->xl_type == XL_TYPE_905B) { 2841 /* Set polling interval */ 2842 CSR_WRITE_1(sc, XL_DOWN_POLL, 64); 2843 /* Load the address of the TX list */ 2844 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_STALL); 2845 xl_wait(sc); 2846 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, 2847 sc->xl_cdata.xl_tx_chain[0].xl_phys); 2848 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); 2849 xl_wait(sc); 2850 } 2851 2852 /* 2853 * If the coax transceiver is on, make sure to enable 2854 * the DC-DC converter. 2855 */ 2856 XL_SEL_WIN(3); 2857 if (sc->xl_xcvr == XL_XCVR_COAX) 2858 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_START); 2859 else 2860 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP); 2861 2862 /* 2863 * increase packet size to allow reception of 802.1q or ISL packets. 2864 * For the 3c90x chip, set the 'allow large packets' bit in the MAC 2865 * control register. For 3c90xB/C chips, use the RX packet size 2866 * register. 2867 */ 2868 2869 if (sc->xl_type == XL_TYPE_905B) 2870 CSR_WRITE_2(sc, XL_W3_MAXPKTSIZE, XL_PACKET_SIZE); 2871 else { 2872 u_int8_t macctl; 2873 macctl = CSR_READ_1(sc, XL_W3_MAC_CTRL); 2874 macctl |= XL_MACCTRL_ALLOW_LARGE_PACK; 2875 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, macctl); 2876 } 2877 2878 /* Clear out the stats counters. */ 2879 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_DISABLE); 2880 sc->xl_stats_no_timeout = 1; 2881 xl_stats_update(sc); 2882 sc->xl_stats_no_timeout = 0; 2883 XL_SEL_WIN(4); 2884 CSR_WRITE_2(sc, XL_W4_NET_DIAG, XL_NETDIAG_UPPER_BYTES_ENABLE); 2885 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_ENABLE); 2886 2887 /* 2888 * Enable interrupts. 2889 */ 2890 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ACK|0xFF); 2891 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STAT_ENB|XL_INTRS); 2892 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|XL_INTRS); 2893 if (sc->xl_flags & XL_FLAG_FUNCREG) 2894 bus_space_write_4(sc->xl_ftag, sc->xl_fhandle, 4, 0x8000); 2895 2896 /* Set the RX early threshold */ 2897 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_THRESH|(XL_PACKET_SIZE >>2)); 2898 CSR_WRITE_2(sc, XL_DMACTL, XL_DMACTL_UP_RX_EARLY); 2899 2900 /* Enable receiver and transmitter. */ 2901 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE); 2902 xl_wait(sc); 2903 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_ENABLE); 2904 xl_wait(sc); 2905 2906 if (mii != NULL) 2907 mii_mediachg(mii); 2908 2909 /* Select window 7 for normal operations. */ 2910 XL_SEL_WIN(7); 2911 2912 ifp->if_flags |= IFF_RUNNING; 2913 ifp->if_flags &= ~IFF_OACTIVE; 2914 2915 callout_reset(&sc->xl_stat_timer, hz, xl_stats_update, sc); 2916 2917 crit_exit(); 2918 } 2919 2920 /* 2921 * Set media options. 2922 */ 2923 static int 2924 xl_ifmedia_upd(ifp) 2925 struct ifnet *ifp; 2926 { 2927 struct xl_softc *sc; 2928 struct ifmedia *ifm = NULL; 2929 struct mii_data *mii = NULL; 2930 2931 sc = ifp->if_softc; 2932 if (sc->xl_miibus != NULL) 2933 mii = device_get_softc(sc->xl_miibus); 2934 if (mii == NULL) 2935 ifm = &sc->ifmedia; 2936 else 2937 ifm = &mii->mii_media; 2938 2939 switch(IFM_SUBTYPE(ifm->ifm_media)) { 2940 case IFM_100_FX: 2941 case IFM_10_FL: 2942 case IFM_10_2: 2943 case IFM_10_5: 2944 xl_setmode(sc, ifm->ifm_media); 2945 return(0); 2946 break; 2947 default: 2948 break; 2949 } 2950 2951 if (sc->xl_media & XL_MEDIAOPT_MII || sc->xl_media & XL_MEDIAOPT_BTX 2952 || sc->xl_media & XL_MEDIAOPT_BT4) { 2953 xl_init(sc); 2954 } else { 2955 xl_setmode(sc, ifm->ifm_media); 2956 } 2957 2958 return(0); 2959 } 2960 2961 /* 2962 * Report current media status. 2963 */ 2964 static void 2965 xl_ifmedia_sts(ifp, ifmr) 2966 struct ifnet *ifp; 2967 struct ifmediareq *ifmr; 2968 { 2969 struct xl_softc *sc; 2970 u_int32_t icfg; 2971 struct mii_data *mii = NULL; 2972 2973 sc = ifp->if_softc; 2974 if (sc->xl_miibus != NULL) 2975 mii = device_get_softc(sc->xl_miibus); 2976 2977 XL_SEL_WIN(3); 2978 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG) & XL_ICFG_CONNECTOR_MASK; 2979 icfg >>= XL_ICFG_CONNECTOR_BITS; 2980 2981 ifmr->ifm_active = IFM_ETHER; 2982 2983 switch(icfg) { 2984 case XL_XCVR_10BT: 2985 ifmr->ifm_active = IFM_ETHER|IFM_10_T; 2986 if (CSR_READ_1(sc, XL_W3_MAC_CTRL) & XL_MACCTRL_DUPLEX) 2987 ifmr->ifm_active |= IFM_FDX; 2988 else 2989 ifmr->ifm_active |= IFM_HDX; 2990 break; 2991 case XL_XCVR_AUI: 2992 if (sc->xl_type == XL_TYPE_905B && 2993 sc->xl_media == XL_MEDIAOPT_10FL) { 2994 ifmr->ifm_active = IFM_ETHER|IFM_10_FL; 2995 if (CSR_READ_1(sc, XL_W3_MAC_CTRL) & XL_MACCTRL_DUPLEX) 2996 ifmr->ifm_active |= IFM_FDX; 2997 else 2998 ifmr->ifm_active |= IFM_HDX; 2999 } else 3000 ifmr->ifm_active = IFM_ETHER|IFM_10_5; 3001 break; 3002 case XL_XCVR_COAX: 3003 ifmr->ifm_active = IFM_ETHER|IFM_10_2; 3004 break; 3005 /* 3006 * XXX MII and BTX/AUTO should be separate cases. 3007 */ 3008 3009 case XL_XCVR_100BTX: 3010 case XL_XCVR_AUTO: 3011 case XL_XCVR_MII: 3012 if (mii != NULL) { 3013 mii_pollstat(mii); 3014 ifmr->ifm_active = mii->mii_media_active; 3015 ifmr->ifm_status = mii->mii_media_status; 3016 } 3017 break; 3018 case XL_XCVR_100BFX: 3019 ifmr->ifm_active = IFM_ETHER|IFM_100_FX; 3020 break; 3021 default: 3022 if_printf(ifp, "unknown XCVR type: %d\n", icfg); 3023 break; 3024 } 3025 3026 return; 3027 } 3028 3029 static int 3030 xl_ioctl(ifp, command, data, cr) 3031 struct ifnet *ifp; 3032 u_long command; 3033 caddr_t data; 3034 struct ucred *cr; 3035 { 3036 struct xl_softc *sc = ifp->if_softc; 3037 struct ifreq *ifr = (struct ifreq *) data; 3038 int error = 0; 3039 struct mii_data *mii = NULL; 3040 u_int8_t rxfilt; 3041 3042 crit_enter(); 3043 3044 switch(command) { 3045 case SIOCSIFFLAGS: 3046 XL_SEL_WIN(5); 3047 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER); 3048 if (ifp->if_flags & IFF_UP) { 3049 if (ifp->if_flags & IFF_RUNNING && 3050 ifp->if_flags & IFF_PROMISC && 3051 !(sc->xl_if_flags & IFF_PROMISC)) { 3052 rxfilt |= XL_RXFILTER_ALLFRAMES; 3053 CSR_WRITE_2(sc, XL_COMMAND, 3054 XL_CMD_RX_SET_FILT|rxfilt); 3055 XL_SEL_WIN(7); 3056 } else if (ifp->if_flags & IFF_RUNNING && 3057 !(ifp->if_flags & IFF_PROMISC) && 3058 sc->xl_if_flags & IFF_PROMISC) { 3059 rxfilt &= ~XL_RXFILTER_ALLFRAMES; 3060 CSR_WRITE_2(sc, XL_COMMAND, 3061 XL_CMD_RX_SET_FILT|rxfilt); 3062 XL_SEL_WIN(7); 3063 } else 3064 xl_init(sc); 3065 } else { 3066 if (ifp->if_flags & IFF_RUNNING) 3067 xl_stop(sc); 3068 } 3069 sc->xl_if_flags = ifp->if_flags; 3070 error = 0; 3071 break; 3072 case SIOCADDMULTI: 3073 case SIOCDELMULTI: 3074 if (sc->xl_type == XL_TYPE_905B) 3075 xl_setmulti_hash(sc); 3076 else 3077 xl_setmulti(sc); 3078 error = 0; 3079 break; 3080 case SIOCGIFMEDIA: 3081 case SIOCSIFMEDIA: 3082 if (sc->xl_miibus != NULL) 3083 mii = device_get_softc(sc->xl_miibus); 3084 if (mii == NULL) 3085 error = ifmedia_ioctl(ifp, ifr, 3086 &sc->ifmedia, command); 3087 else 3088 error = ifmedia_ioctl(ifp, ifr, 3089 &mii->mii_media, command); 3090 break; 3091 case SIOCSIFCAP: 3092 ifp->if_capenable = ifr->ifr_reqcap; 3093 if (ifp->if_capenable & IFCAP_TXCSUM) 3094 ifp->if_hwassist = XL905B_CSUM_FEATURES; 3095 else 3096 ifp->if_hwassist = 0; 3097 break; 3098 default: 3099 error = ether_ioctl(ifp, command, data); 3100 break; 3101 } 3102 3103 crit_exit(); 3104 3105 return(error); 3106 } 3107 3108 static void 3109 xl_watchdog(ifp) 3110 struct ifnet *ifp; 3111 { 3112 struct xl_softc *sc; 3113 u_int16_t status = 0; 3114 3115 sc = ifp->if_softc; 3116 3117 ifp->if_oerrors++; 3118 XL_SEL_WIN(4); 3119 status = CSR_READ_2(sc, XL_W4_MEDIA_STATUS); 3120 if_printf(ifp, "watchdog timeout\n"); 3121 3122 if (status & XL_MEDIASTAT_CARRIER) 3123 if_printf(ifp, "no carrier - transceiver cable problem?\n"); 3124 xl_txeoc(sc); 3125 xl_txeof(sc); 3126 xl_rxeof(sc); 3127 xl_reset(sc); 3128 xl_init(sc); 3129 3130 if (!ifq_is_empty(&ifp->if_snd)) 3131 (*ifp->if_start)(ifp); 3132 } 3133 3134 /* 3135 * Stop the adapter and free any mbufs allocated to the 3136 * RX and TX lists. 3137 */ 3138 static void 3139 xl_stop(sc) 3140 struct xl_softc *sc; 3141 { 3142 int i; 3143 struct ifnet *ifp; 3144 3145 ifp = &sc->arpcom.ac_if; 3146 ifp->if_timer = 0; 3147 3148 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_DISABLE); 3149 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_DISABLE); 3150 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB); 3151 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_DISCARD); 3152 xl_wait(sc); 3153 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_DISABLE); 3154 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP); 3155 DELAY(800); 3156 3157 #ifdef foo 3158 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET); 3159 xl_wait(sc); 3160 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); 3161 xl_wait(sc); 3162 #endif 3163 3164 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ACK|XL_STAT_INTLATCH); 3165 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STAT_ENB|0); 3166 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|0); 3167 if (sc->xl_flags & XL_FLAG_FUNCREG) bus_space_write_4 (sc->xl_ftag, sc->xl_fhandle, 4, 0x8000); 3168 3169 /* Stop the stats updater. */ 3170 callout_stop(&sc->xl_stat_timer); 3171 3172 /* 3173 * Free data in the RX lists. 3174 */ 3175 for (i = 0; i < XL_RX_LIST_CNT; i++) { 3176 if (sc->xl_cdata.xl_rx_chain[i].xl_mbuf != NULL) { 3177 bus_dmamap_unload(sc->xl_mtag, 3178 sc->xl_cdata.xl_rx_chain[i].xl_map); 3179 bus_dmamap_destroy(sc->xl_mtag, 3180 sc->xl_cdata.xl_rx_chain[i].xl_map); 3181 m_freem(sc->xl_cdata.xl_rx_chain[i].xl_mbuf); 3182 sc->xl_cdata.xl_rx_chain[i].xl_mbuf = NULL; 3183 } 3184 } 3185 bzero(sc->xl_ldata.xl_rx_list, XL_RX_LIST_SZ); 3186 /* 3187 * Free the TX list buffers. 3188 */ 3189 for (i = 0; i < XL_TX_LIST_CNT; i++) { 3190 if (sc->xl_cdata.xl_tx_chain[i].xl_mbuf != NULL) { 3191 bus_dmamap_unload(sc->xl_mtag, 3192 sc->xl_cdata.xl_tx_chain[i].xl_map); 3193 bus_dmamap_destroy(sc->xl_mtag, 3194 sc->xl_cdata.xl_tx_chain[i].xl_map); 3195 m_freem(sc->xl_cdata.xl_tx_chain[i].xl_mbuf); 3196 sc->xl_cdata.xl_tx_chain[i].xl_mbuf = NULL; 3197 } 3198 } 3199 bzero(sc->xl_ldata.xl_tx_list, XL_TX_LIST_SZ); 3200 3201 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 3202 3203 return; 3204 } 3205 3206 /* 3207 * Stop all chip I/O so that the kernel's probe routines don't 3208 * get confused by errant DMAs when rebooting. 3209 */ 3210 static void 3211 xl_shutdown(dev) 3212 device_t dev; 3213 { 3214 struct xl_softc *sc; 3215 3216 sc = device_get_softc(dev); 3217 3218 xl_reset(sc); 3219 xl_stop(sc); 3220 3221 return; 3222 } 3223 3224 static int 3225 xl_suspend(dev) 3226 device_t dev; 3227 { 3228 struct xl_softc *sc = device_get_softc(dev); 3229 3230 crit_enter(); 3231 3232 xl_stop(sc); 3233 3234 crit_exit(); 3235 3236 return(0); 3237 } 3238 3239 static int 3240 xl_resume(dev) 3241 device_t dev; 3242 { 3243 struct xl_softc *sc; 3244 struct ifnet *ifp; 3245 3246 sc = device_get_softc(dev); 3247 ifp = &sc->arpcom.ac_if; 3248 3249 crit_enter(); 3250 3251 xl_reset(sc); 3252 if (ifp->if_flags & IFF_UP) 3253 xl_init(sc); 3254 3255 crit_exit(); 3256 3257 return(0); 3258 } 3259