1 /* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: src/sys/pci/if_xl.c,v 1.72.2.28 2003/10/08 06:01:57 murray Exp $ 33 */ 34 35 /* 36 * 3Com 3c90x Etherlink XL PCI NIC driver 37 * 38 * Supports the 3Com "boomerang", "cyclone" and "hurricane" PCI 39 * bus-master chips (3c90x cards and embedded controllers) including 40 * the following: 41 * 42 * 3Com 3c900-TPO 10Mbps/RJ-45 43 * 3Com 3c900-COMBO 10Mbps/RJ-45,AUI,BNC 44 * 3Com 3c905-TX 10/100Mbps/RJ-45 45 * 3Com 3c905-T4 10/100Mbps/RJ-45 46 * 3Com 3c900B-TPO 10Mbps/RJ-45 47 * 3Com 3c900B-COMBO 10Mbps/RJ-45,AUI,BNC 48 * 3Com 3c900B-TPC 10Mbps/RJ-45,BNC 49 * 3Com 3c900B-FL 10Mbps/Fiber-optic 50 * 3Com 3c905B-COMBO 10/100Mbps/RJ-45,AUI,BNC 51 * 3Com 3c905B-TX 10/100Mbps/RJ-45 52 * 3Com 3c905B-FL/FX 10/100Mbps/Fiber-optic 53 * 3Com 3c905C-TX 10/100Mbps/RJ-45 (Tornado ASIC) 54 * 3Com 3c980-TX 10/100Mbps server adapter (Hurricane ASIC) 55 * 3Com 3c980C-TX 10/100Mbps server adapter (Tornado ASIC) 56 * 3Com 3cSOHO100-TX 10/100Mbps/RJ-45 (Hurricane ASIC) 57 * 3Com 3c450-TX 10/100Mbps/RJ-45 (Tornado ASIC) 58 * 3Com 3c555 10/100Mbps/RJ-45 (MiniPCI, Laptop Hurricane) 59 * 3Com 3c556 10/100Mbps/RJ-45 (MiniPCI, Hurricane ASIC) 60 * 3Com 3c556B 10/100Mbps/RJ-45 (MiniPCI, Hurricane ASIC) 61 * 3Com 3c575TX 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC) 62 * 3Com 3c575B 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC) 63 * 3Com 3c575C 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC) 64 * 3Com 3cxfem656 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC) 65 * 3Com 3cxfem656b 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC) 66 * 3Com 3cxfem656c 10/100Mbps/RJ-45 (Cardbus, Tornado ASIC) 67 * Dell Optiplex GX1 on-board 3c918 10/100Mbps/RJ-45 68 * Dell on-board 3c920 10/100Mbps/RJ-45 69 * Dell Precision on-board 3c905B 10/100Mbps/RJ-45 70 * Dell Latitude laptop docking station embedded 3c905-TX 71 * 72 * Written by Bill Paul <wpaul@ctr.columbia.edu> 73 * Electrical Engineering Department 74 * Columbia University, New York City 75 */ 76 77 /* 78 * The 3c90x series chips use a bus-master DMA interface for transfering 79 * packets to and from the controller chip. Some of the "vortex" cards 80 * (3c59x) also supported a bus master mode, however for those chips 81 * you could only DMA packets to/from a contiguous memory buffer. For 82 * transmission this would mean copying the contents of the queued mbuf 83 * chain into an mbuf cluster and then DMAing the cluster. This extra 84 * copy would sort of defeat the purpose of the bus master support for 85 * any packet that doesn't fit into a single mbuf. 86 * 87 * By contrast, the 3c90x cards support a fragment-based bus master 88 * mode where mbuf chains can be encapsulated using TX descriptors. 89 * This is similar to other PCI chips such as the Texas Instruments 90 * ThunderLAN and the Intel 82557/82558. 91 * 92 * The "vortex" driver (if_vx.c) happens to work for the "boomerang" 93 * bus master chips because they maintain the old PIO interface for 94 * backwards compatibility, but starting with the 3c905B and the 95 * "cyclone" chips, the compatibility interface has been dropped. 96 * Since using bus master DMA is a big win, we use this driver to 97 * support the PCI "boomerang" chips even though they work with the 98 * "vortex" driver in order to obtain better performance. 99 */ 100 101 #include "opt_ifpoll.h" 102 103 #include <sys/param.h> 104 #include <sys/systm.h> 105 #include <sys/sockio.h> 106 #include <sys/endian.h> 107 #include <sys/mbuf.h> 108 #include <sys/kernel.h> 109 #include <sys/socket.h> 110 #include <sys/serialize.h> 111 #include <sys/bus.h> 112 #include <sys/rman.h> 113 #include <sys/thread2.h> 114 #include <sys/interrupt.h> 115 116 #include <net/if.h> 117 #include <net/ifq_var.h> 118 #include <net/if_arp.h> 119 #include <net/ethernet.h> 120 #include <net/if_dl.h> 121 #include <net/if_media.h> 122 #include <net/if_poll.h> 123 #include <net/vlan/if_vlan_var.h> 124 125 #include <net/bpf.h> 126 127 #include "../mii_layer/mii.h" 128 #include "../mii_layer/miivar.h" 129 130 #include <bus/pci/pcireg.h> 131 #include <bus/pci/pcivar.h> 132 133 /* "controller miibus0" required. See GENERIC if you get errors here. */ 134 #include "miibus_if.h" 135 136 #include "if_xlreg.h" 137 138 #define XL905B_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 139 140 /* 141 * Various supported device vendors/types and their names. 142 */ 143 static struct xl_type xl_devs[] = { 144 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10BT, 145 "3Com 3c900-TPO Etherlink XL" }, 146 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10BT_COMBO, 147 "3Com 3c900-COMBO Etherlink XL" }, 148 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10_100BT, 149 "3Com 3c905-TX Fast Etherlink XL" }, 150 { TC_VENDORID, TC_DEVICEID_BOOMERANG_100BT4, 151 "3Com 3c905-T4 Fast Etherlink XL" }, 152 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT, 153 "3Com 3c900B-TPO Etherlink XL" }, 154 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT_COMBO, 155 "3Com 3c900B-COMBO Etherlink XL" }, 156 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT_TPC, 157 "3Com 3c900B-TPC Etherlink XL" }, 158 { TC_VENDORID, TC_DEVICEID_CYCLONE_10FL, 159 "3Com 3c900B-FL Etherlink XL" }, 160 { TC_VENDORID, TC_DEVICEID_HURRICANE_10_100BT, 161 "3Com 3c905B-TX Fast Etherlink XL" }, 162 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100BT4, 163 "3Com 3c905B-T4 Fast Etherlink XL" }, 164 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100FX, 165 "3Com 3c905B-FX/SC Fast Etherlink XL" }, 166 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100_COMBO, 167 "3Com 3c905B-COMBO Fast Etherlink XL" }, 168 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT, 169 "3Com 3c905C-TX Fast Etherlink XL" }, 170 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT_920B, 171 "3Com 3c920B-EMB Integrated Fast Etherlink XL" }, 172 { TC_VENDORID, TC_DEVICEID_HURRICANE_10_100BT_SERV, 173 "3Com 3c980 Fast Etherlink XL" }, 174 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT_SERV, 175 "3Com 3c980C Fast Etherlink XL" }, 176 { TC_VENDORID, TC_DEVICEID_HURRICANE_SOHO100TX, 177 "3Com 3cSOHO100-TX OfficeConnect" }, 178 { TC_VENDORID, TC_DEVICEID_TORNADO_HOMECONNECT, 179 "3Com 3c450-TX HomeConnect" }, 180 { TC_VENDORID, TC_DEVICEID_HURRICANE_555, 181 "3Com 3c555 Fast Etherlink XL" }, 182 { TC_VENDORID, TC_DEVICEID_HURRICANE_556, 183 "3Com 3c556 Fast Etherlink XL" }, 184 { TC_VENDORID, TC_DEVICEID_HURRICANE_556B, 185 "3Com 3c556B Fast Etherlink XL" }, 186 { TC_VENDORID, TC_DEVICEID_HURRICANE_575A, 187 "3Com 3c575TX Fast Etherlink XL" }, 188 { TC_VENDORID, TC_DEVICEID_HURRICANE_575B, 189 "3Com 3c575B Fast Etherlink XL" }, 190 { TC_VENDORID, TC_DEVICEID_HURRICANE_575C, 191 "3Com 3c575C Fast Etherlink XL" }, 192 { TC_VENDORID, TC_DEVICEID_HURRICANE_656, 193 "3Com 3c656 Fast Etherlink XL" }, 194 { TC_VENDORID, TC_DEVICEID_HURRICANE_656B, 195 "3Com 3c656B Fast Etherlink XL" }, 196 { TC_VENDORID, TC_DEVICEID_TORNADO_656C, 197 "3Com 3c656C Fast Etherlink XL" }, 198 { 0, 0, NULL } 199 }; 200 201 static int xl_probe (device_t); 202 static int xl_attach (device_t); 203 static int xl_detach (device_t); 204 static void xl_shutdown (device_t); 205 static int xl_suspend (device_t); 206 static int xl_resume (device_t); 207 208 static int xl_newbuf (struct xl_softc *, struct xl_chain_onefrag *, 209 int); 210 static void xl_stats_update (void *); 211 static void xl_stats_update_serialized(void *); 212 static int xl_encap (struct xl_softc *, struct xl_chain *, 213 struct mbuf *); 214 static void xl_rxeof (struct xl_softc *, int); 215 static int xl_rx_resync (struct xl_softc *); 216 static void xl_txeof (struct xl_softc *); 217 static void xl_txeof_90xB (struct xl_softc *); 218 static void xl_txeoc (struct xl_softc *); 219 static void xl_intr (void *); 220 static void xl_start_body (struct ifnet *, int); 221 static void xl_start (struct ifnet *); 222 static void xl_start_90xB (struct ifnet *); 223 static int xl_ioctl (struct ifnet *, u_long, caddr_t, 224 struct ucred *); 225 static void xl_init (void *); 226 static void xl_stop (struct xl_softc *); 227 static void xl_watchdog (struct ifnet *); 228 #ifdef IFPOLL_ENABLE 229 static void xl_start_poll (struct ifnet *); 230 static void xl_npoll (struct ifnet *, struct ifpoll_info *); 231 static void xl_npoll_compat (struct ifnet *, void *, int); 232 #endif 233 static void xl_enable_intrs (struct xl_softc *, uint16_t); 234 235 static int xl_ifmedia_upd (struct ifnet *); 236 static void xl_ifmedia_sts (struct ifnet *, struct ifmediareq *); 237 238 static int xl_eeprom_wait (struct xl_softc *); 239 static int xl_read_eeprom (struct xl_softc *, caddr_t, int, int, int); 240 static void xl_mii_sync (struct xl_softc *); 241 static void xl_mii_send (struct xl_softc *, u_int32_t, int); 242 static int xl_mii_readreg (struct xl_softc *, struct xl_mii_frame *); 243 static int xl_mii_writereg (struct xl_softc *, struct xl_mii_frame *); 244 245 static void xl_setcfg (struct xl_softc *); 246 static void xl_setmode (struct xl_softc *, int); 247 static void xl_setmulti (struct xl_softc *); 248 static void xl_setmulti_hash (struct xl_softc *); 249 static void xl_reset (struct xl_softc *); 250 static int xl_list_rx_init (struct xl_softc *); 251 static void xl_list_tx_init (struct xl_softc *); 252 static void xl_list_tx_init_90xB(struct xl_softc *); 253 static void xl_wait (struct xl_softc *); 254 static void xl_mediacheck (struct xl_softc *); 255 static void xl_choose_xcvr (struct xl_softc *, int); 256 257 static int xl_dma_alloc (device_t); 258 static void xl_dma_free (device_t); 259 260 #ifdef notdef 261 static void xl_testpacket (struct xl_softc *); 262 #endif 263 264 static int xl_miibus_readreg (device_t, int, int); 265 static int xl_miibus_writereg (device_t, int, int, int); 266 static void xl_miibus_statchg (device_t); 267 static void xl_miibus_mediainit (device_t); 268 269 static device_method_t xl_methods[] = { 270 /* Device interface */ 271 DEVMETHOD(device_probe, xl_probe), 272 DEVMETHOD(device_attach, xl_attach), 273 DEVMETHOD(device_detach, xl_detach), 274 DEVMETHOD(device_shutdown, xl_shutdown), 275 DEVMETHOD(device_suspend, xl_suspend), 276 DEVMETHOD(device_resume, xl_resume), 277 278 /* bus interface */ 279 DEVMETHOD(bus_print_child, bus_generic_print_child), 280 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 281 282 /* MII interface */ 283 DEVMETHOD(miibus_readreg, xl_miibus_readreg), 284 DEVMETHOD(miibus_writereg, xl_miibus_writereg), 285 DEVMETHOD(miibus_statchg, xl_miibus_statchg), 286 DEVMETHOD(miibus_mediainit, xl_miibus_mediainit), 287 288 { 0, 0 } 289 }; 290 291 static driver_t xl_driver = { 292 "xl", 293 xl_methods, 294 sizeof(struct xl_softc) 295 }; 296 297 static devclass_t xl_devclass; 298 299 DECLARE_DUMMY_MODULE(if_xl); 300 MODULE_DEPEND(if_xl, miibus, 1, 1, 1); 301 DRIVER_MODULE(if_xl, pci, xl_driver, xl_devclass, NULL, NULL); 302 DRIVER_MODULE(if_xl, cardbus, xl_driver, xl_devclass, NULL, NULL); 303 DRIVER_MODULE(miibus, xl, miibus_driver, miibus_devclass, NULL, NULL); 304 305 static void 306 xl_enable_intrs(struct xl_softc *sc, uint16_t intrs) 307 { 308 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ACK | 0xFF); 309 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB | intrs); 310 if (sc->xl_flags & XL_FLAG_FUNCREG) 311 bus_space_write_4(sc->xl_ftag, sc->xl_fhandle, 4, 0x8000); 312 sc->xl_npoll.ifpc_stcount = 0; 313 } 314 315 /* 316 * Murphy's law says that it's possible the chip can wedge and 317 * the 'command in progress' bit may never clear. Hence, we wait 318 * only a finite amount of time to avoid getting caught in an 319 * infinite loop. Normally this delay routine would be a macro, 320 * but it isn't called during normal operation so we can afford 321 * to make it a function. 322 */ 323 static void 324 xl_wait(struct xl_softc *sc) 325 { 326 int i; 327 328 for (i = 0; i < XL_TIMEOUT; i++) { 329 if (!(CSR_READ_2(sc, XL_STATUS) & XL_STAT_CMDBUSY)) 330 break; 331 } 332 333 if (i == XL_TIMEOUT) 334 if_printf(&sc->arpcom.ac_if, "command never completed!"); 335 336 return; 337 } 338 339 /* 340 * MII access routines are provided for adapters with external 341 * PHYs (3c905-TX, 3c905-T4, 3c905B-T4) and those with built-in 342 * autoneg logic that's faked up to look like a PHY (3c905B-TX). 343 * Note: if you don't perform the MDIO operations just right, 344 * it's possible to end up with code that works correctly with 345 * some chips/CPUs/processor speeds/bus speeds/etc but not 346 * with others. 347 */ 348 #define MII_SET(x) \ 349 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, \ 350 CSR_READ_2(sc, XL_W4_PHY_MGMT) | (x)) 351 352 #define MII_CLR(x) \ 353 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, \ 354 CSR_READ_2(sc, XL_W4_PHY_MGMT) & ~(x)) 355 356 /* 357 * Sync the PHYs by setting data bit and strobing the clock 32 times. 358 */ 359 static void 360 xl_mii_sync(struct xl_softc *sc) 361 { 362 int i; 363 364 XL_SEL_WIN(4); 365 MII_SET(XL_MII_DIR|XL_MII_DATA); 366 367 for (i = 0; i < 32; i++) { 368 MII_SET(XL_MII_CLK); 369 MII_SET(XL_MII_DATA); 370 MII_SET(XL_MII_DATA); 371 MII_CLR(XL_MII_CLK); 372 MII_SET(XL_MII_DATA); 373 MII_SET(XL_MII_DATA); 374 } 375 376 return; 377 } 378 379 /* 380 * Clock a series of bits through the MII. 381 */ 382 static void 383 xl_mii_send(struct xl_softc *sc, u_int32_t bits, int cnt) 384 { 385 int i; 386 387 XL_SEL_WIN(4); 388 MII_CLR(XL_MII_CLK); 389 390 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 391 if (bits & i) { 392 MII_SET(XL_MII_DATA); 393 } else { 394 MII_CLR(XL_MII_DATA); 395 } 396 MII_CLR(XL_MII_CLK); 397 MII_SET(XL_MII_CLK); 398 } 399 } 400 401 /* 402 * Read an PHY register through the MII. 403 */ 404 static int 405 xl_mii_readreg(struct xl_softc *sc, struct xl_mii_frame *frame) 406 { 407 int i, ack; 408 409 /* 410 * Set up frame for RX. 411 */ 412 frame->mii_stdelim = XL_MII_STARTDELIM; 413 frame->mii_opcode = XL_MII_READOP; 414 frame->mii_turnaround = 0; 415 frame->mii_data = 0; 416 417 /* 418 * Select register window 4. 419 */ 420 421 XL_SEL_WIN(4); 422 423 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, 0); 424 /* 425 * Turn on data xmit. 426 */ 427 MII_SET(XL_MII_DIR); 428 429 xl_mii_sync(sc); 430 431 /* 432 * Send command/address info. 433 */ 434 xl_mii_send(sc, frame->mii_stdelim, 2); 435 xl_mii_send(sc, frame->mii_opcode, 2); 436 xl_mii_send(sc, frame->mii_phyaddr, 5); 437 xl_mii_send(sc, frame->mii_regaddr, 5); 438 439 /* Idle bit */ 440 MII_CLR((XL_MII_CLK|XL_MII_DATA)); 441 MII_SET(XL_MII_CLK); 442 443 /* Turn off xmit. */ 444 MII_CLR(XL_MII_DIR); 445 446 /* Check for ack */ 447 MII_CLR(XL_MII_CLK); 448 ack = CSR_READ_2(sc, XL_W4_PHY_MGMT) & XL_MII_DATA; 449 MII_SET(XL_MII_CLK); 450 451 /* 452 * Now try reading data bits. If the ack failed, we still 453 * need to clock through 16 cycles to keep the PHY(s) in sync. 454 */ 455 if (ack) { 456 for(i = 0; i < 16; i++) { 457 MII_CLR(XL_MII_CLK); 458 MII_SET(XL_MII_CLK); 459 } 460 goto fail; 461 } 462 463 for (i = 0x8000; i; i >>= 1) { 464 MII_CLR(XL_MII_CLK); 465 if (!ack) { 466 if (CSR_READ_2(sc, XL_W4_PHY_MGMT) & XL_MII_DATA) 467 frame->mii_data |= i; 468 } 469 MII_SET(XL_MII_CLK); 470 } 471 472 fail: 473 474 MII_CLR(XL_MII_CLK); 475 MII_SET(XL_MII_CLK); 476 477 if (ack) 478 return(1); 479 return(0); 480 } 481 482 /* 483 * Write to a PHY register through the MII. 484 */ 485 static int 486 xl_mii_writereg(struct xl_softc *sc, struct xl_mii_frame *frame) 487 { 488 /* 489 * Set up frame for TX. 490 */ 491 492 frame->mii_stdelim = XL_MII_STARTDELIM; 493 frame->mii_opcode = XL_MII_WRITEOP; 494 frame->mii_turnaround = XL_MII_TURNAROUND; 495 496 /* 497 * Select the window 4. 498 */ 499 XL_SEL_WIN(4); 500 501 /* 502 * Turn on data output. 503 */ 504 MII_SET(XL_MII_DIR); 505 506 xl_mii_sync(sc); 507 508 xl_mii_send(sc, frame->mii_stdelim, 2); 509 xl_mii_send(sc, frame->mii_opcode, 2); 510 xl_mii_send(sc, frame->mii_phyaddr, 5); 511 xl_mii_send(sc, frame->mii_regaddr, 5); 512 xl_mii_send(sc, frame->mii_turnaround, 2); 513 xl_mii_send(sc, frame->mii_data, 16); 514 515 /* Idle bit. */ 516 MII_SET(XL_MII_CLK); 517 MII_CLR(XL_MII_CLK); 518 519 /* 520 * Turn off xmit. 521 */ 522 MII_CLR(XL_MII_DIR); 523 524 return(0); 525 } 526 527 static int 528 xl_miibus_readreg(device_t dev, int phy, int reg) 529 { 530 struct xl_softc *sc; 531 struct xl_mii_frame frame; 532 533 sc = device_get_softc(dev); 534 535 /* 536 * Pretend that PHYs are only available at MII address 24. 537 * This is to guard against problems with certain 3Com ASIC 538 * revisions that incorrectly map the internal transceiver 539 * control registers at all MII addresses. This can cause 540 * the miibus code to attach the same PHY several times over. 541 */ 542 if ((!(sc->xl_flags & XL_FLAG_PHYOK)) && phy != 24) 543 return(0); 544 545 bzero((char *)&frame, sizeof(frame)); 546 547 frame.mii_phyaddr = phy; 548 frame.mii_regaddr = reg; 549 xl_mii_readreg(sc, &frame); 550 551 return(frame.mii_data); 552 } 553 554 static int 555 xl_miibus_writereg(device_t dev, int phy, int reg, int data) 556 { 557 struct xl_softc *sc; 558 struct xl_mii_frame frame; 559 560 sc = device_get_softc(dev); 561 562 if ((!(sc->xl_flags & XL_FLAG_PHYOK)) && phy != 24) 563 return(0); 564 565 bzero((char *)&frame, sizeof(frame)); 566 567 frame.mii_phyaddr = phy; 568 frame.mii_regaddr = reg; 569 frame.mii_data = data; 570 571 xl_mii_writereg(sc, &frame); 572 573 return(0); 574 } 575 576 static void 577 xl_miibus_statchg(device_t dev) 578 { 579 struct xl_softc *sc; 580 struct mii_data *mii; 581 582 sc = device_get_softc(dev); 583 mii = device_get_softc(sc->xl_miibus); 584 585 ASSERT_SERIALIZED(sc->arpcom.ac_if.if_serializer); 586 587 xl_setcfg(sc); 588 589 /* Set ASIC's duplex mode to match the PHY. */ 590 XL_SEL_WIN(3); 591 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) 592 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, XL_MACCTRL_DUPLEX); 593 else 594 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, 595 (CSR_READ_1(sc, XL_W3_MAC_CTRL) & ~XL_MACCTRL_DUPLEX)); 596 } 597 598 /* 599 * Special support for the 3c905B-COMBO. This card has 10/100 support 600 * plus BNC and AUI ports. This means we will have both an miibus attached 601 * plus some non-MII media settings. In order to allow this, we have to 602 * add the extra media to the miibus's ifmedia struct, but we can't do 603 * that during xl_attach() because the miibus hasn't been attached yet. 604 * So instead, we wait until the miibus probe/attach is done, at which 605 * point we will get a callback telling is that it's safe to add our 606 * extra media. 607 */ 608 static void 609 xl_miibus_mediainit(device_t dev) 610 { 611 struct xl_softc *sc; 612 struct mii_data *mii; 613 struct ifmedia *ifm; 614 615 sc = device_get_softc(dev); 616 mii = device_get_softc(sc->xl_miibus); 617 ifm = &mii->mii_media; 618 619 if (sc->xl_media & (XL_MEDIAOPT_AUI|XL_MEDIAOPT_10FL)) { 620 /* 621 * Check for a 10baseFL board in disguise. 622 */ 623 if (sc->xl_type == XL_TYPE_905B && 624 sc->xl_media == XL_MEDIAOPT_10FL) { 625 if (bootverbose) 626 device_printf(dev, "found 10baseFL\n"); 627 ifmedia_add(ifm, IFM_ETHER|IFM_10_FL, 0, NULL); 628 ifmedia_add(ifm, IFM_ETHER|IFM_10_FL|IFM_HDX, 0, NULL); 629 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX) 630 ifmedia_add(ifm, 631 IFM_ETHER|IFM_10_FL|IFM_FDX, 0, NULL); 632 } else { 633 if (bootverbose) 634 device_printf(dev, "found AUI\n"); 635 ifmedia_add(ifm, IFM_ETHER|IFM_10_5, 0, NULL); 636 } 637 } 638 639 if (sc->xl_media & XL_MEDIAOPT_BNC) { 640 if (bootverbose) 641 device_printf(dev, "found BNC\n"); 642 ifmedia_add(ifm, IFM_ETHER|IFM_10_2, 0, NULL); 643 } 644 645 return; 646 } 647 648 /* 649 * The EEPROM is slow: give it time to come ready after issuing 650 * it a command. 651 */ 652 static int 653 xl_eeprom_wait(struct xl_softc *sc) 654 { 655 int i; 656 657 for (i = 0; i < 100; i++) { 658 if (CSR_READ_2(sc, XL_W0_EE_CMD) & XL_EE_BUSY) 659 DELAY(162); 660 else 661 break; 662 } 663 664 if (i == 100) { 665 if_printf(&sc->arpcom.ac_if, "eeprom failed to come ready\n"); 666 return(1); 667 } 668 669 return(0); 670 } 671 672 /* 673 * Read a sequence of words from the EEPROM. Note that ethernet address 674 * data is stored in the EEPROM in network byte order. 675 */ 676 static int 677 xl_read_eeprom(struct xl_softc *sc, caddr_t dest, int off, int cnt, int swap) 678 { 679 int err = 0, i; 680 u_int16_t word = 0, *ptr; 681 #define EEPROM_5BIT_OFFSET(A) ((((A) << 2) & 0x7F00) | ((A) & 0x003F)) 682 #define EEPROM_8BIT_OFFSET(A) ((A) & 0x003F) 683 /* WARNING! DANGER! 684 * It's easy to accidentally overwrite the rom content! 685 * Note: the 3c575 uses 8bit EEPROM offsets. 686 */ 687 XL_SEL_WIN(0); 688 689 if (xl_eeprom_wait(sc)) 690 return(1); 691 692 if (sc->xl_flags & XL_FLAG_EEPROM_OFFSET_30) 693 off += 0x30; 694 695 for (i = 0; i < cnt; i++) { 696 if (sc->xl_flags & XL_FLAG_8BITROM) 697 CSR_WRITE_2(sc, XL_W0_EE_CMD, 698 XL_EE_8BIT_READ | EEPROM_8BIT_OFFSET(off + i)); 699 else 700 CSR_WRITE_2(sc, XL_W0_EE_CMD, 701 XL_EE_READ | EEPROM_5BIT_OFFSET(off + i)); 702 err = xl_eeprom_wait(sc); 703 if (err) 704 break; 705 word = CSR_READ_2(sc, XL_W0_EE_DATA); 706 ptr = (u_int16_t *)(dest + (i * 2)); 707 if (swap) 708 *ptr = ntohs(word); 709 else 710 *ptr = word; 711 } 712 713 return(err ? 1 : 0); 714 } 715 716 /* 717 * NICs older than the 3c905B have only one multicast option, which 718 * is to enable reception of all multicast frames. 719 */ 720 static void 721 xl_setmulti(struct xl_softc *sc) 722 { 723 struct ifnet *ifp; 724 struct ifmultiaddr *ifma; 725 u_int8_t rxfilt; 726 int mcnt = 0; 727 728 ifp = &sc->arpcom.ac_if; 729 730 XL_SEL_WIN(5); 731 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER); 732 733 if (ifp->if_flags & IFF_ALLMULTI) { 734 rxfilt |= XL_RXFILTER_ALLMULTI; 735 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 736 return; 737 } 738 739 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) 740 mcnt++; 741 742 if (mcnt) 743 rxfilt |= XL_RXFILTER_ALLMULTI; 744 else 745 rxfilt &= ~XL_RXFILTER_ALLMULTI; 746 747 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 748 749 return; 750 } 751 752 /* 753 * 3c905B adapters have a hash filter that we can program. 754 */ 755 static void 756 xl_setmulti_hash(struct xl_softc *sc) 757 { 758 struct ifnet *ifp; 759 int h = 0, i; 760 struct ifmultiaddr *ifma; 761 u_int8_t rxfilt; 762 int mcnt = 0; 763 764 ifp = &sc->arpcom.ac_if; 765 766 XL_SEL_WIN(5); 767 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER); 768 769 if (ifp->if_flags & IFF_ALLMULTI) { 770 rxfilt |= XL_RXFILTER_ALLMULTI; 771 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 772 return; 773 } else 774 rxfilt &= ~XL_RXFILTER_ALLMULTI; 775 776 777 /* first, zot all the existing hash bits */ 778 for (i = 0; i < XL_HASHFILT_SIZE; i++) 779 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_HASH|i); 780 781 /* now program new ones */ 782 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 783 if (ifma->ifma_addr->sa_family != AF_LINK) 784 continue; 785 786 /* 787 * Note: the 3c905B currently only supports a 64-bit 788 * hash table, which means we really only need 6 bits, 789 * but the manual indicates that future chip revisions 790 * will have a 256-bit hash table, hence the routine is 791 * set up to calculate 8 bits of position info in case 792 * we need it some day. 793 * Note II, The Sequel: _CURRENT_ versions of the 3c905B 794 * have a 256 bit hash table. This means we have to use 795 * all 8 bits regardless. On older cards, the upper 2 796 * bits will be ignored. Grrrr.... 797 */ 798 h = ether_crc32_be( 799 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 800 ETHER_ADDR_LEN) & 0xff; 801 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_HASH|XL_HASH_SET|h); 802 mcnt++; 803 } 804 805 if (mcnt) 806 rxfilt |= XL_RXFILTER_MULTIHASH; 807 else 808 rxfilt &= ~XL_RXFILTER_MULTIHASH; 809 810 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 811 812 return; 813 } 814 815 #ifdef notdef 816 static void 817 xl_testpacket(struct xl_softc *sc) 818 { 819 struct mbuf *m; 820 struct ifnet *ifp; 821 822 ifp = &sc->arpcom.ac_if; 823 824 MGETHDR(m, MB_DONTWAIT, MT_DATA); 825 826 if (m == NULL) 827 return; 828 829 bcopy(&sc->arpcom.ac_enaddr, 830 mtod(m, struct ether_header *)->ether_dhost, ETHER_ADDR_LEN); 831 bcopy(&sc->arpcom.ac_enaddr, 832 mtod(m, struct ether_header *)->ether_shost, ETHER_ADDR_LEN); 833 mtod(m, struct ether_header *)->ether_type = htons(3); 834 mtod(m, unsigned char *)[14] = 0; 835 mtod(m, unsigned char *)[15] = 0; 836 mtod(m, unsigned char *)[16] = 0xE3; 837 m->m_len = m->m_pkthdr.len = sizeof(struct ether_header) + 3; 838 IF_ENQUEUE(&ifp->if_snd, m); 839 xl_start(ifp); 840 841 return; 842 } 843 #endif 844 845 static void 846 xl_setcfg(struct xl_softc *sc) 847 { 848 u_int32_t icfg; 849 850 XL_SEL_WIN(3); 851 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG); 852 icfg &= ~XL_ICFG_CONNECTOR_MASK; 853 if (sc->xl_media & XL_MEDIAOPT_MII || 854 sc->xl_media & XL_MEDIAOPT_BT4) 855 icfg |= (XL_XCVR_MII << XL_ICFG_CONNECTOR_BITS); 856 if (sc->xl_media & XL_MEDIAOPT_BTX) 857 icfg |= (XL_XCVR_AUTO << XL_ICFG_CONNECTOR_BITS); 858 859 CSR_WRITE_4(sc, XL_W3_INTERNAL_CFG, icfg); 860 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP); 861 862 return; 863 } 864 865 static void 866 xl_setmode(struct xl_softc *sc, int media) 867 { 868 struct ifnet *ifp = &sc->arpcom.ac_if; 869 u_int32_t icfg; 870 u_int16_t mediastat; 871 872 if_printf(ifp, "selecting "); 873 874 XL_SEL_WIN(4); 875 mediastat = CSR_READ_2(sc, XL_W4_MEDIA_STATUS); 876 XL_SEL_WIN(3); 877 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG); 878 879 if (sc->xl_media & XL_MEDIAOPT_BT) { 880 if (IFM_SUBTYPE(media) == IFM_10_T) { 881 kprintf("10baseT transceiver, "); 882 sc->xl_xcvr = XL_XCVR_10BT; 883 icfg &= ~XL_ICFG_CONNECTOR_MASK; 884 icfg |= (XL_XCVR_10BT << XL_ICFG_CONNECTOR_BITS); 885 mediastat |= XL_MEDIASTAT_LINKBEAT| 886 XL_MEDIASTAT_JABGUARD; 887 mediastat &= ~XL_MEDIASTAT_SQEENB; 888 } 889 } 890 891 if (sc->xl_media & XL_MEDIAOPT_BFX) { 892 if (IFM_SUBTYPE(media) == IFM_100_FX) { 893 kprintf("100baseFX port, "); 894 sc->xl_xcvr = XL_XCVR_100BFX; 895 icfg &= ~XL_ICFG_CONNECTOR_MASK; 896 icfg |= (XL_XCVR_100BFX << XL_ICFG_CONNECTOR_BITS); 897 mediastat |= XL_MEDIASTAT_LINKBEAT; 898 mediastat &= ~XL_MEDIASTAT_SQEENB; 899 } 900 } 901 902 if (sc->xl_media & (XL_MEDIAOPT_AUI|XL_MEDIAOPT_10FL)) { 903 if (IFM_SUBTYPE(media) == IFM_10_5) { 904 kprintf("AUI port, "); 905 sc->xl_xcvr = XL_XCVR_AUI; 906 icfg &= ~XL_ICFG_CONNECTOR_MASK; 907 icfg |= (XL_XCVR_AUI << XL_ICFG_CONNECTOR_BITS); 908 mediastat &= ~(XL_MEDIASTAT_LINKBEAT| 909 XL_MEDIASTAT_JABGUARD); 910 mediastat |= ~XL_MEDIASTAT_SQEENB; 911 } 912 if (IFM_SUBTYPE(media) == IFM_10_FL) { 913 kprintf("10baseFL transceiver, "); 914 sc->xl_xcvr = XL_XCVR_AUI; 915 icfg &= ~XL_ICFG_CONNECTOR_MASK; 916 icfg |= (XL_XCVR_AUI << XL_ICFG_CONNECTOR_BITS); 917 mediastat &= ~(XL_MEDIASTAT_LINKBEAT| 918 XL_MEDIASTAT_JABGUARD); 919 mediastat |= ~XL_MEDIASTAT_SQEENB; 920 } 921 } 922 923 if (sc->xl_media & XL_MEDIAOPT_BNC) { 924 if (IFM_SUBTYPE(media) == IFM_10_2) { 925 kprintf("BNC port, "); 926 sc->xl_xcvr = XL_XCVR_COAX; 927 icfg &= ~XL_ICFG_CONNECTOR_MASK; 928 icfg |= (XL_XCVR_COAX << XL_ICFG_CONNECTOR_BITS); 929 mediastat &= ~(XL_MEDIASTAT_LINKBEAT| 930 XL_MEDIASTAT_JABGUARD| 931 XL_MEDIASTAT_SQEENB); 932 } 933 } 934 935 if ((media & IFM_GMASK) == IFM_FDX || 936 IFM_SUBTYPE(media) == IFM_100_FX) { 937 kprintf("full duplex\n"); 938 XL_SEL_WIN(3); 939 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, XL_MACCTRL_DUPLEX); 940 } else { 941 kprintf("half duplex\n"); 942 XL_SEL_WIN(3); 943 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, 944 (CSR_READ_1(sc, XL_W3_MAC_CTRL) & ~XL_MACCTRL_DUPLEX)); 945 } 946 947 if (IFM_SUBTYPE(media) == IFM_10_2) 948 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_START); 949 else 950 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP); 951 CSR_WRITE_4(sc, XL_W3_INTERNAL_CFG, icfg); 952 XL_SEL_WIN(4); 953 CSR_WRITE_2(sc, XL_W4_MEDIA_STATUS, mediastat); 954 DELAY(800); 955 XL_SEL_WIN(7); 956 } 957 958 static void 959 xl_reset(struct xl_softc *sc) 960 { 961 int i; 962 963 XL_SEL_WIN(0); 964 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RESET | 965 ((sc->xl_flags & XL_FLAG_WEIRDRESET) ? 966 XL_RESETOPT_DISADVFD:0)); 967 968 /* 969 * If we're using memory mapped register mode, pause briefly 970 * after issuing the reset command before trying to access any 971 * other registers. With my 3c575C cardbus card, failing to do 972 * this results in the system locking up while trying to poll 973 * the command busy bit in the status register. 974 */ 975 if (sc->xl_flags & XL_FLAG_USE_MMIO) 976 DELAY(100000); 977 978 for (i = 0; i < XL_TIMEOUT; i++) { 979 DELAY(10); 980 if (!(CSR_READ_2(sc, XL_STATUS) & XL_STAT_CMDBUSY)) 981 break; 982 } 983 984 if (i == XL_TIMEOUT) 985 if_printf(&sc->arpcom.ac_if, "reset didn't complete\n"); 986 987 /* Reset TX and RX. */ 988 /* Note: the RX reset takes an absurd amount of time 989 * on newer versions of the Tornado chips such as those 990 * on the 3c905CX and newer 3c908C cards. We wait an 991 * extra amount of time so that xl_wait() doesn't complain 992 * and annoy the users. 993 */ 994 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET); 995 DELAY(100000); 996 xl_wait(sc); 997 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); 998 xl_wait(sc); 999 1000 if (sc->xl_flags & XL_FLAG_INVERT_LED_PWR || 1001 sc->xl_flags & XL_FLAG_INVERT_MII_PWR) { 1002 XL_SEL_WIN(2); 1003 CSR_WRITE_2(sc, XL_W2_RESET_OPTIONS, CSR_READ_2(sc, 1004 XL_W2_RESET_OPTIONS) 1005 | ((sc->xl_flags & XL_FLAG_INVERT_LED_PWR)?XL_RESETOPT_INVERT_LED:0) 1006 | ((sc->xl_flags & XL_FLAG_INVERT_MII_PWR)?XL_RESETOPT_INVERT_MII:0) 1007 ); 1008 } 1009 1010 /* Wait a little while for the chip to get its brains in order. */ 1011 DELAY(100000); 1012 return; 1013 } 1014 1015 /* 1016 * Probe for a 3Com Etherlink XL chip. Check the PCI vendor and device 1017 * IDs against our list and return a device name if we find a match. 1018 */ 1019 static int 1020 xl_probe(device_t dev) 1021 { 1022 struct xl_type *t; 1023 uint16_t vid, did; 1024 1025 vid = pci_get_vendor(dev); 1026 did = pci_get_device(dev); 1027 for (t = xl_devs; t->xl_name != NULL; t++) { 1028 if (vid == t->xl_vid && did == t->xl_did) { 1029 device_set_desc(dev, t->xl_name); 1030 return(0); 1031 } 1032 } 1033 return(ENXIO); 1034 } 1035 1036 /* 1037 * This routine is a kludge to work around possible hardware faults 1038 * or manufacturing defects that can cause the media options register 1039 * (or reset options register, as it's called for the first generation 1040 * 3c90x adapters) to return an incorrect result. I have encountered 1041 * one Dell Latitude laptop docking station with an integrated 3c905-TX 1042 * which doesn't have any of the 'mediaopt' bits set. This screws up 1043 * the attach routine pretty badly because it doesn't know what media 1044 * to look for. If we find ourselves in this predicament, this routine 1045 * will try to guess the media options values and warn the user of a 1046 * possible manufacturing defect with his adapter/system/whatever. 1047 */ 1048 static void 1049 xl_mediacheck(struct xl_softc *sc) 1050 { 1051 struct ifnet *ifp = &sc->arpcom.ac_if; 1052 1053 /* 1054 * If some of the media options bits are set, assume they are 1055 * correct. If not, try to figure it out down below. 1056 * XXX I should check for 10baseFL, but I don't have an adapter 1057 * to test with. 1058 */ 1059 if (sc->xl_media & (XL_MEDIAOPT_MASK & ~XL_MEDIAOPT_VCO)) { 1060 /* 1061 * Check the XCVR value. If it's not in the normal range 1062 * of values, we need to fake it up here. 1063 */ 1064 if (sc->xl_xcvr <= XL_XCVR_AUTO) 1065 return; 1066 else { 1067 if_printf(ifp, "bogus xcvr value in EEPROM (%x)\n", 1068 sc->xl_xcvr); 1069 if_printf(ifp, 1070 "choosing new default based on card type\n"); 1071 } 1072 } else { 1073 if (sc->xl_type == XL_TYPE_905B && 1074 sc->xl_media & XL_MEDIAOPT_10FL) 1075 return; 1076 if_printf(ifp, "WARNING: no media options bits set in " 1077 "the media options register!!\n"); 1078 if_printf(ifp, "this could be a manufacturing defect in " 1079 "your adapter or system\n"); 1080 if_printf(ifp, "attempting to guess media type; you " 1081 "should probably consult your vendor\n"); 1082 } 1083 1084 xl_choose_xcvr(sc, 1); 1085 } 1086 1087 static void 1088 xl_choose_xcvr(struct xl_softc *sc, int verbose) 1089 { 1090 struct ifnet *ifp = &sc->arpcom.ac_if; 1091 u_int16_t devid; 1092 1093 /* 1094 * Read the device ID from the EEPROM. 1095 * This is what's loaded into the PCI device ID register, so it has 1096 * to be correct otherwise we wouldn't have gotten this far. 1097 */ 1098 xl_read_eeprom(sc, (caddr_t)&devid, XL_EE_PRODID, 1, 0); 1099 1100 switch(devid) { 1101 case TC_DEVICEID_BOOMERANG_10BT: /* 3c900-TPO */ 1102 case TC_DEVICEID_KRAKATOA_10BT: /* 3c900B-TPO */ 1103 sc->xl_media = XL_MEDIAOPT_BT; 1104 sc->xl_xcvr = XL_XCVR_10BT; 1105 if (verbose) 1106 if_printf(ifp, "guessing 10BaseT transceiver\n"); 1107 break; 1108 case TC_DEVICEID_BOOMERANG_10BT_COMBO: /* 3c900-COMBO */ 1109 case TC_DEVICEID_KRAKATOA_10BT_COMBO: /* 3c900B-COMBO */ 1110 sc->xl_media = XL_MEDIAOPT_BT|XL_MEDIAOPT_BNC|XL_MEDIAOPT_AUI; 1111 sc->xl_xcvr = XL_XCVR_10BT; 1112 if (verbose) 1113 if_printf(ifp, "guessing COMBO (AUI/BNC/TP)\n"); 1114 break; 1115 case TC_DEVICEID_KRAKATOA_10BT_TPC: /* 3c900B-TPC */ 1116 sc->xl_media = XL_MEDIAOPT_BT|XL_MEDIAOPT_BNC; 1117 sc->xl_xcvr = XL_XCVR_10BT; 1118 if (verbose) 1119 if_printf(ifp, "guessing TPC (BNC/TP)\n"); 1120 break; 1121 case TC_DEVICEID_CYCLONE_10FL: /* 3c900B-FL */ 1122 sc->xl_media = XL_MEDIAOPT_10FL; 1123 sc->xl_xcvr = XL_XCVR_AUI; 1124 if (verbose) 1125 if_printf(ifp, "guessing 10baseFL\n"); 1126 break; 1127 case TC_DEVICEID_BOOMERANG_10_100BT: /* 3c905-TX */ 1128 case TC_DEVICEID_HURRICANE_555: /* 3c555 */ 1129 case TC_DEVICEID_HURRICANE_556: /* 3c556 */ 1130 case TC_DEVICEID_HURRICANE_556B: /* 3c556B */ 1131 case TC_DEVICEID_HURRICANE_575A: /* 3c575TX */ 1132 case TC_DEVICEID_HURRICANE_575B: /* 3c575B */ 1133 case TC_DEVICEID_HURRICANE_575C: /* 3c575C */ 1134 case TC_DEVICEID_HURRICANE_656: /* 3c656 */ 1135 case TC_DEVICEID_HURRICANE_656B: /* 3c656B */ 1136 case TC_DEVICEID_TORNADO_656C: /* 3c656C */ 1137 case TC_DEVICEID_TORNADO_10_100BT_920B: /* 3c920B-EMB */ 1138 sc->xl_media = XL_MEDIAOPT_MII; 1139 sc->xl_xcvr = XL_XCVR_MII; 1140 if (verbose) 1141 if_printf(ifp, "guessing MII\n"); 1142 break; 1143 case TC_DEVICEID_BOOMERANG_100BT4: /* 3c905-T4 */ 1144 case TC_DEVICEID_CYCLONE_10_100BT4: /* 3c905B-T4 */ 1145 sc->xl_media = XL_MEDIAOPT_BT4; 1146 sc->xl_xcvr = XL_XCVR_MII; 1147 if (verbose) 1148 if_printf(ifp, "guessing 100BaseT4/MII\n"); 1149 break; 1150 case TC_DEVICEID_HURRICANE_10_100BT: /* 3c905B-TX */ 1151 case TC_DEVICEID_HURRICANE_10_100BT_SERV:/*3c980-TX */ 1152 case TC_DEVICEID_TORNADO_10_100BT_SERV: /* 3c980C-TX */ 1153 case TC_DEVICEID_HURRICANE_SOHO100TX: /* 3cSOHO100-TX */ 1154 case TC_DEVICEID_TORNADO_10_100BT: /* 3c905C-TX */ 1155 case TC_DEVICEID_TORNADO_HOMECONNECT: /* 3c450-TX */ 1156 sc->xl_media = XL_MEDIAOPT_BTX; 1157 sc->xl_xcvr = XL_XCVR_AUTO; 1158 if (verbose) 1159 if_printf(ifp, "guessing 10/100 internal\n"); 1160 break; 1161 case TC_DEVICEID_CYCLONE_10_100_COMBO: /* 3c905B-COMBO */ 1162 sc->xl_media = XL_MEDIAOPT_BTX|XL_MEDIAOPT_BNC|XL_MEDIAOPT_AUI; 1163 sc->xl_xcvr = XL_XCVR_AUTO; 1164 if (verbose) 1165 if_printf(ifp, "guessing 10/100 plus BNC/AUI\n"); 1166 break; 1167 default: 1168 if_printf(ifp, 1169 "unknown device ID: %x -- defaulting to 10baseT\n", devid); 1170 sc->xl_media = XL_MEDIAOPT_BT; 1171 break; 1172 } 1173 1174 return; 1175 } 1176 1177 /* 1178 * Attach the interface. Allocate softc structures, do ifmedia 1179 * setup and ethernet/BPF attach. 1180 */ 1181 static int 1182 xl_attach(device_t dev) 1183 { 1184 u_char eaddr[ETHER_ADDR_LEN]; 1185 u_int16_t xcvr[2]; 1186 struct xl_softc *sc; 1187 struct ifnet *ifp; 1188 int media = IFM_ETHER|IFM_100_TX|IFM_FDX; 1189 int error = 0, rid, res; 1190 uint16_t did; 1191 1192 sc = device_get_softc(dev); 1193 1194 ifmedia_init(&sc->ifmedia, 0, xl_ifmedia_upd, xl_ifmedia_sts); 1195 1196 did = pci_get_device(dev); 1197 1198 sc->xl_flags = 0; 1199 if (did == TC_DEVICEID_HURRICANE_555) 1200 sc->xl_flags |= XL_FLAG_EEPROM_OFFSET_30 | XL_FLAG_PHYOK; 1201 if (did == TC_DEVICEID_HURRICANE_556 || 1202 did == TC_DEVICEID_HURRICANE_556B) 1203 sc->xl_flags |= XL_FLAG_FUNCREG | XL_FLAG_PHYOK | 1204 XL_FLAG_EEPROM_OFFSET_30 | XL_FLAG_WEIRDRESET | 1205 XL_FLAG_INVERT_LED_PWR | XL_FLAG_INVERT_MII_PWR; 1206 if (did == TC_DEVICEID_HURRICANE_555 || 1207 did == TC_DEVICEID_HURRICANE_556) 1208 sc->xl_flags |= XL_FLAG_8BITROM; 1209 if (did == TC_DEVICEID_HURRICANE_556B) 1210 sc->xl_flags |= XL_FLAG_NO_XCVR_PWR; 1211 if (did == TC_DEVICEID_HURRICANE_575B || 1212 did == TC_DEVICEID_HURRICANE_575C || 1213 did == TC_DEVICEID_HURRICANE_656B || 1214 did == TC_DEVICEID_TORNADO_656C) 1215 sc->xl_flags |= XL_FLAG_FUNCREG; 1216 if (did == TC_DEVICEID_HURRICANE_575A || 1217 did == TC_DEVICEID_HURRICANE_575B || 1218 did == TC_DEVICEID_HURRICANE_575C || 1219 did == TC_DEVICEID_HURRICANE_656B || 1220 did == TC_DEVICEID_TORNADO_656C) 1221 sc->xl_flags |= XL_FLAG_PHYOK | XL_FLAG_EEPROM_OFFSET_30 | 1222 XL_FLAG_8BITROM; 1223 if (did == TC_DEVICEID_HURRICANE_656) 1224 sc->xl_flags |= XL_FLAG_FUNCREG | XL_FLAG_PHYOK; 1225 if (did == TC_DEVICEID_HURRICANE_575B) 1226 sc->xl_flags |= XL_FLAG_INVERT_LED_PWR; 1227 if (did == TC_DEVICEID_HURRICANE_575C) 1228 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR; 1229 if (did == TC_DEVICEID_TORNADO_656C) 1230 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR; 1231 if (did == TC_DEVICEID_HURRICANE_656 || 1232 did == TC_DEVICEID_HURRICANE_656B) 1233 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR | 1234 XL_FLAG_INVERT_LED_PWR; 1235 if (did == TC_DEVICEID_TORNADO_10_100BT_920B) 1236 sc->xl_flags |= XL_FLAG_PHYOK; 1237 #ifndef BURN_BRIDGES 1238 /* 1239 * If this is a 3c905B, we have to check one extra thing. 1240 * The 905B supports power management and may be placed in 1241 * a low-power mode (D3 mode), typically by certain operating 1242 * systems which shall not be named. The PCI BIOS is supposed 1243 * to reset the NIC and bring it out of low-power mode, but 1244 * some do not. Consequently, we have to see if this chip 1245 * supports power management, and if so, make sure it's not 1246 * in low-power mode. If power management is available, the 1247 * capid byte will be 0x01. 1248 * 1249 * I _think_ that what actually happens is that the chip 1250 * loses its PCI configuration during the transition from 1251 * D3 back to D0; this means that it should be possible for 1252 * us to save the PCI iobase, membase and IRQ, put the chip 1253 * back in the D0 state, then restore the PCI config ourselves. 1254 */ 1255 1256 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 1257 u_int32_t iobase, membase, irq; 1258 1259 /* Save important PCI config data. */ 1260 iobase = pci_read_config(dev, XL_PCI_LOIO, 4); 1261 membase = pci_read_config(dev, XL_PCI_LOMEM, 4); 1262 irq = pci_read_config(dev, XL_PCI_INTLINE, 4); 1263 1264 /* Reset the power state. */ 1265 device_printf(dev, "chip is in D%d power mode " 1266 "-- setting to D0\n", pci_get_powerstate(dev)); 1267 1268 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 1269 1270 /* Restore PCI config data. */ 1271 pci_write_config(dev, XL_PCI_LOIO, iobase, 4); 1272 pci_write_config(dev, XL_PCI_LOMEM, membase, 4); 1273 pci_write_config(dev, XL_PCI_INTLINE, irq, 4); 1274 } 1275 #endif 1276 /* 1277 * Map control/status registers. 1278 */ 1279 pci_enable_busmaster(dev); 1280 1281 rid = XL_PCI_LOMEM; 1282 res = SYS_RES_MEMORY; 1283 1284 #if 0 1285 sc->xl_res = bus_alloc_resource_any(dev, res, &rid, RF_ACTIVE); 1286 #endif 1287 1288 if (sc->xl_res != NULL) { 1289 sc->xl_flags |= XL_FLAG_USE_MMIO; 1290 if (bootverbose) 1291 device_printf(dev, "using memory mapped I/O\n"); 1292 } else { 1293 rid = XL_PCI_LOIO; 1294 res = SYS_RES_IOPORT; 1295 sc->xl_res = bus_alloc_resource_any(dev, res, &rid, RF_ACTIVE); 1296 if (sc->xl_res == NULL) { 1297 device_printf(dev, "couldn't map ports/memory\n"); 1298 error = ENXIO; 1299 goto fail; 1300 } 1301 if (bootverbose) 1302 device_printf(dev, "using port I/O\n"); 1303 } 1304 1305 sc->xl_btag = rman_get_bustag(sc->xl_res); 1306 sc->xl_bhandle = rman_get_bushandle(sc->xl_res); 1307 1308 if (sc->xl_flags & XL_FLAG_FUNCREG) { 1309 rid = XL_PCI_FUNCMEM; 1310 sc->xl_fres = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 1311 RF_ACTIVE); 1312 1313 if (sc->xl_fres == NULL) { 1314 device_printf(dev, "couldn't map funcreg memory\n"); 1315 error = ENXIO; 1316 goto fail; 1317 } 1318 1319 sc->xl_ftag = rman_get_bustag(sc->xl_fres); 1320 sc->xl_fhandle = rman_get_bushandle(sc->xl_fres); 1321 } 1322 1323 /* Allocate interrupt */ 1324 rid = 0; 1325 sc->xl_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1326 RF_SHAREABLE | RF_ACTIVE); 1327 if (sc->xl_irq == NULL) { 1328 device_printf(dev, "couldn't map interrupt\n"); 1329 error = ENXIO; 1330 goto fail; 1331 } 1332 1333 ifp = &sc->arpcom.ac_if; 1334 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1335 1336 /* Reset the adapter. */ 1337 xl_reset(sc); 1338 1339 /* 1340 * Get station address from the EEPROM. 1341 */ 1342 if (xl_read_eeprom(sc, (caddr_t)&eaddr, XL_EE_OEM_ADR0, 3, 1)) { 1343 device_printf(dev, "failed to read station address\n"); 1344 error = ENXIO; 1345 goto fail; 1346 } 1347 1348 callout_init(&sc->xl_stat_timer); 1349 1350 error = xl_dma_alloc(dev); 1351 if (error) 1352 goto fail; 1353 1354 /* 1355 * Figure out the card type. 3c905B adapters have the 1356 * 'supportsNoTxLength' bit set in the capabilities 1357 * word in the EEPROM. 1358 * Note: my 3c575C cardbus card lies. It returns a value 1359 * of 0x1578 for its capabilities word, which is somewhat 1360 * nonsensical. Another way to distinguish a 3c90x chip 1361 * from a 3c90xB/C chip is to check for the 'supportsLargePackets' 1362 * bit. This will only be set for 3c90x boomerage chips. 1363 */ 1364 xl_read_eeprom(sc, (caddr_t)&sc->xl_caps, XL_EE_CAPS, 1, 0); 1365 if (sc->xl_caps & XL_CAPS_NO_TXLENGTH || 1366 !(sc->xl_caps & XL_CAPS_LARGE_PKTS)) 1367 sc->xl_type = XL_TYPE_905B; 1368 else 1369 sc->xl_type = XL_TYPE_90X; 1370 if (bootverbose) { 1371 device_printf(dev, "type %s\n", 1372 sc->xl_type == XL_TYPE_905B ? "90XB" : "90X"); 1373 } 1374 1375 ifp->if_softc = sc; 1376 ifp->if_mtu = ETHERMTU; 1377 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1378 ifp->if_ioctl = xl_ioctl; 1379 if (sc->xl_type == XL_TYPE_905B) { 1380 ifp->if_start = xl_start_90xB; 1381 ifp->if_capabilities |= IFCAP_HWCSUM | IFCAP_VLAN_MTU; 1382 } else { 1383 ifp->if_start = xl_start; 1384 } 1385 ifp->if_watchdog = xl_watchdog; 1386 ifp->if_init = xl_init; 1387 #ifdef IFPOLL_ENABLE 1388 ifp->if_npoll = xl_npoll; 1389 #endif 1390 ifp->if_baudrate = 10000000; 1391 ifq_set_maxlen(&ifp->if_snd, XL_TX_LIST_CNT - 1); 1392 ifq_set_ready(&ifp->if_snd); 1393 /* 1394 * NOTE: Hardware checksum features disabled by default. 1395 * This seems to corrupt tx packet data one out of a 1396 * million packets or so and then generates a good checksum 1397 * so the receiver doesn't know the packet is bad 1398 */ 1399 ifp->if_capenable = ifp->if_capabilities & ~IFCAP_HWCSUM; 1400 if (ifp->if_capenable & IFCAP_TXCSUM) 1401 ifp->if_hwassist = XL905B_CSUM_FEATURES; 1402 1403 /* 1404 * Now we have to see what sort of media we have. 1405 * This includes probing for an MII interace and a 1406 * possible PHY. 1407 */ 1408 XL_SEL_WIN(3); 1409 sc->xl_media = CSR_READ_2(sc, XL_W3_MEDIA_OPT); 1410 if (bootverbose) 1411 if_printf(ifp, "media options word: %x\n", sc->xl_media); 1412 1413 xl_read_eeprom(sc, (char *)&xcvr, XL_EE_ICFG_0, 2, 0); 1414 sc->xl_xcvr = xcvr[0] | xcvr[1] << 16; 1415 sc->xl_xcvr &= XL_ICFG_CONNECTOR_MASK; 1416 sc->xl_xcvr >>= XL_ICFG_CONNECTOR_BITS; 1417 1418 xl_mediacheck(sc); 1419 1420 if (sc->xl_media & XL_MEDIAOPT_MII || sc->xl_media & XL_MEDIAOPT_BTX 1421 || sc->xl_media & XL_MEDIAOPT_BT4) { 1422 if (bootverbose) 1423 if_printf(ifp, "found MII/AUTO\n"); 1424 xl_setcfg(sc); 1425 1426 error = mii_phy_probe(dev, &sc->xl_miibus, 1427 xl_ifmedia_upd, xl_ifmedia_sts); 1428 if (error) { 1429 if_printf(ifp, "no PHY found!\n"); 1430 goto fail; 1431 } 1432 1433 goto done; 1434 } 1435 1436 /* 1437 * Sanity check. If the user has selected "auto" and this isn't 1438 * a 10/100 card of some kind, we need to force the transceiver 1439 * type to something sane. 1440 */ 1441 if (sc->xl_xcvr == XL_XCVR_AUTO) 1442 xl_choose_xcvr(sc, bootverbose); 1443 1444 /* 1445 * Do ifmedia setup. 1446 */ 1447 if (sc->xl_media & XL_MEDIAOPT_BT) { 1448 if (bootverbose) 1449 if_printf(ifp, "found 10baseT\n"); 1450 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL); 1451 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T|IFM_HDX, 0, NULL); 1452 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX) 1453 ifmedia_add(&sc->ifmedia, 1454 IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL); 1455 } 1456 1457 if (sc->xl_media & (XL_MEDIAOPT_AUI|XL_MEDIAOPT_10FL)) { 1458 /* 1459 * Check for a 10baseFL board in disguise. 1460 */ 1461 if (sc->xl_type == XL_TYPE_905B && 1462 sc->xl_media == XL_MEDIAOPT_10FL) { 1463 if (bootverbose) 1464 if_printf(ifp, "found 10baseFL\n"); 1465 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_FL, 0, NULL); 1466 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_FL|IFM_HDX, 1467 0, NULL); 1468 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX) 1469 ifmedia_add(&sc->ifmedia, 1470 IFM_ETHER|IFM_10_FL|IFM_FDX, 0, NULL); 1471 } else { 1472 if (bootverbose) 1473 if_printf(ifp, "found AUI\n"); 1474 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_5, 0, NULL); 1475 } 1476 } 1477 1478 if (sc->xl_media & XL_MEDIAOPT_BNC) { 1479 if (bootverbose) 1480 if_printf(ifp, "found BNC\n"); 1481 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_2, 0, NULL); 1482 } 1483 1484 if (sc->xl_media & XL_MEDIAOPT_BFX) { 1485 if (bootverbose) 1486 if_printf(ifp, "found 100baseFX\n"); 1487 ifp->if_baudrate = 100000000; 1488 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_FX, 0, NULL); 1489 } 1490 1491 /* Choose a default media. */ 1492 switch(sc->xl_xcvr) { 1493 case XL_XCVR_10BT: 1494 media = IFM_ETHER|IFM_10_T; 1495 xl_setmode(sc, media); 1496 break; 1497 case XL_XCVR_AUI: 1498 if (sc->xl_type == XL_TYPE_905B && 1499 sc->xl_media == XL_MEDIAOPT_10FL) { 1500 media = IFM_ETHER|IFM_10_FL; 1501 xl_setmode(sc, media); 1502 } else { 1503 media = IFM_ETHER|IFM_10_5; 1504 xl_setmode(sc, media); 1505 } 1506 break; 1507 case XL_XCVR_COAX: 1508 media = IFM_ETHER|IFM_10_2; 1509 xl_setmode(sc, media); 1510 break; 1511 case XL_XCVR_AUTO: 1512 case XL_XCVR_100BTX: 1513 case XL_XCVR_MII: 1514 /* Chosen by miibus */ 1515 break; 1516 case XL_XCVR_100BFX: 1517 media = IFM_ETHER|IFM_100_FX; 1518 break; 1519 default: 1520 if_printf(ifp, "unknown XCVR type: %d\n", sc->xl_xcvr); 1521 /* 1522 * This will probably be wrong, but it prevents 1523 * the ifmedia code from panicking. 1524 */ 1525 media = IFM_ETHER|IFM_10_T; 1526 break; 1527 } 1528 1529 if (sc->xl_miibus == NULL) 1530 ifmedia_set(&sc->ifmedia, media); 1531 1532 done: 1533 1534 if (sc->xl_flags & XL_FLAG_NO_XCVR_PWR) { 1535 XL_SEL_WIN(0); 1536 CSR_WRITE_2(sc, XL_W0_MFG_ID, XL_NO_XCVR_PWR_MAGICBITS); 1537 } 1538 1539 /* 1540 * Call MI attach routine. 1541 */ 1542 ether_ifattach(ifp, eaddr, NULL); 1543 1544 #ifdef IFPOLL_ENABLE 1545 ifpoll_compat_setup(&sc->xl_npoll, NULL, NULL, device_get_unit(dev), 1546 ifp->if_serializer); 1547 #endif 1548 1549 /* 1550 * Tell the upper layer(s) we support long frames. 1551 */ 1552 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1553 1554 /* Hook interrupt last to avoid having to lock softc */ 1555 error = bus_setup_intr(dev, sc->xl_irq, INTR_MPSAFE, 1556 xl_intr, sc, &sc->xl_intrhand, 1557 ifp->if_serializer); 1558 if (error) { 1559 if_printf(ifp, "couldn't set up irq\n"); 1560 ether_ifdetach(ifp); 1561 goto fail; 1562 } 1563 1564 ifp->if_cpuid = rman_get_cpuid(sc->xl_irq); 1565 KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus); 1566 1567 return 0; 1568 1569 fail: 1570 xl_detach(dev); 1571 return error; 1572 } 1573 1574 /* 1575 * Shutdown hardware and free up resources. This can be called any 1576 * time after the mutex has been initialized. It is called in both 1577 * the error case in attach and the normal detach case so it needs 1578 * to be careful about only freeing resources that have actually been 1579 * allocated. 1580 */ 1581 static int 1582 xl_detach(device_t dev) 1583 { 1584 struct xl_softc *sc; 1585 struct ifnet *ifp; 1586 int rid, res; 1587 1588 sc = device_get_softc(dev); 1589 ifp = &sc->arpcom.ac_if; 1590 1591 if (sc->xl_flags & XL_FLAG_USE_MMIO) { 1592 rid = XL_PCI_LOMEM; 1593 res = SYS_RES_MEMORY; 1594 } else { 1595 rid = XL_PCI_LOIO; 1596 res = SYS_RES_IOPORT; 1597 } 1598 1599 if (device_is_attached(dev)) { 1600 lwkt_serialize_enter(ifp->if_serializer); 1601 xl_reset(sc); 1602 xl_stop(sc); 1603 bus_teardown_intr(dev, sc->xl_irq, sc->xl_intrhand); 1604 lwkt_serialize_exit(ifp->if_serializer); 1605 1606 ether_ifdetach(ifp); 1607 } 1608 1609 if (sc->xl_miibus) 1610 device_delete_child(dev, sc->xl_miibus); 1611 bus_generic_detach(dev); 1612 ifmedia_removeall(&sc->ifmedia); 1613 1614 if (sc->xl_irq) 1615 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->xl_irq); 1616 if (sc->xl_fres != NULL) 1617 bus_release_resource(dev, SYS_RES_MEMORY, 1618 XL_PCI_FUNCMEM, sc->xl_fres); 1619 if (sc->xl_res) 1620 bus_release_resource(dev, res, rid, sc->xl_res); 1621 1622 xl_dma_free(dev); 1623 1624 return(0); 1625 } 1626 1627 static int 1628 xl_dma_alloc(device_t dev) 1629 { 1630 struct xl_softc *sc; 1631 struct xl_chain_data *cd; 1632 struct xl_list_data *ld; 1633 bus_dmamem_t dmem; 1634 int i, error; 1635 1636 sc = device_get_softc(dev); 1637 cd = &sc->xl_cdata; 1638 ld = &sc->xl_ldata; 1639 1640 /* 1641 * Allocate the parent bus DMA tag appropriate for PCI. 1642 */ 1643 error = bus_dma_tag_create(NULL, 1, 0, 1644 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, 1645 NULL, NULL, 1646 BUS_SPACE_MAXSIZE_32BIT, 0, 1647 BUS_SPACE_MAXSIZE_32BIT, 1648 0, &sc->xl_parent_tag); 1649 if (error) { 1650 device_printf(dev, "could not allocate parent dma tag\n"); 1651 return error; 1652 } 1653 1654 /* 1655 * Now allocate a tag for the DMA descriptor lists and a chunk 1656 * of DMA-able memory based on the tag. Also obtain the DMA 1657 * addresses of the RX and TX ring, which we'll need later. 1658 * All of our lists are allocated as a contiguous block 1659 * of memory. 1660 */ 1661 error = bus_dmamem_coherent(sc->xl_parent_tag, XL_LIST_ALIGN, 0, 1662 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 1663 XL_RX_LIST_SZ, BUS_DMA_WAITOK, &dmem); 1664 if (error) { 1665 device_printf(dev, "failed to allocate rx list\n"); 1666 return error; 1667 } 1668 ld->xl_rx_tag = dmem.dmem_tag; 1669 ld->xl_rx_dmamap = dmem.dmem_map; 1670 ld->xl_rx_list = dmem.dmem_addr; 1671 ld->xl_rx_dmaaddr = dmem.dmem_busaddr; 1672 1673 error = bus_dmamem_coherent(sc->xl_parent_tag, XL_LIST_ALIGN, 0, 1674 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 1675 XL_TX_LIST_SZ, BUS_DMA_WAITOK, &dmem); 1676 if (error) { 1677 device_printf(dev, "failed to allocate tx list\n"); 1678 return error; 1679 } 1680 ld->xl_tx_tag = dmem.dmem_tag; 1681 ld->xl_tx_dmamap = dmem.dmem_map; 1682 ld->xl_tx_list = dmem.dmem_addr; 1683 ld->xl_tx_dmaaddr = dmem.dmem_busaddr; 1684 1685 /* 1686 * Allocate a DMA tag for the mapping of mbufs. 1687 */ 1688 error = bus_dma_tag_create(sc->xl_parent_tag, 1, 0, 1689 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 1690 NULL, NULL, 1691 MCLBYTES, 1, MCLBYTES, 1692 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, 1693 &sc->xl_rx_mtag); 1694 if (error) { 1695 device_printf(dev, "failed to allocate RX mbuf dma tag\n"); 1696 return error; 1697 } 1698 1699 /* 1700 * Allocate a spare DMA map for the RX ring. 1701 */ 1702 error = bus_dmamap_create(sc->xl_rx_mtag, BUS_DMA_WAITOK, 1703 &sc->xl_tmpmap); 1704 if (error) { 1705 device_printf(dev, "failed to create RX mbuf tmp dma map\n"); 1706 bus_dma_tag_destroy(sc->xl_rx_mtag); 1707 sc->xl_rx_mtag = NULL; 1708 return error; 1709 } 1710 1711 for (i = 0; i < XL_RX_LIST_CNT; i++) { 1712 error = bus_dmamap_create(sc->xl_rx_mtag, BUS_DMA_WAITOK, 1713 &cd->xl_rx_chain[i].xl_map); 1714 if (error) { 1715 device_printf(dev, "failed to create %dth " 1716 "rx descriptor dma map!\n", i); 1717 return error; 1718 } 1719 cd->xl_rx_chain[i].xl_ptr = &ld->xl_rx_list[i]; 1720 } 1721 1722 error = bus_dma_tag_create(sc->xl_parent_tag, 1, 0, 1723 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 1724 NULL, NULL, 1725 MCLBYTES, XL_MAXFRAGS, MCLBYTES, 1726 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK, 1727 &sc->xl_tx_mtag); 1728 if (error) { 1729 device_printf(dev, "failed to allocate TX mbuf dma tag\n"); 1730 return error; 1731 } 1732 1733 for (i = 0; i < XL_TX_LIST_CNT; i++) { 1734 error = bus_dmamap_create(sc->xl_tx_mtag, BUS_DMA_WAITOK, 1735 &cd->xl_tx_chain[i].xl_map); 1736 if (error) { 1737 device_printf(dev, "failed to create %dth " 1738 "tx descriptor dma map!\n", i); 1739 return error; 1740 } 1741 cd->xl_tx_chain[i].xl_ptr = &ld->xl_tx_list[i]; 1742 } 1743 return 0; 1744 } 1745 1746 static void 1747 xl_dma_free(device_t dev) 1748 { 1749 struct xl_softc *sc; 1750 struct xl_chain_data *cd; 1751 struct xl_list_data *ld; 1752 int i; 1753 1754 sc = device_get_softc(dev); 1755 cd = &sc->xl_cdata; 1756 ld = &sc->xl_ldata; 1757 1758 for (i = 0; i < XL_RX_LIST_CNT; ++i) { 1759 if (cd->xl_rx_chain[i].xl_ptr != NULL) { 1760 if (cd->xl_rx_chain[i].xl_mbuf != NULL) { 1761 bus_dmamap_unload(sc->xl_rx_mtag, 1762 cd->xl_rx_chain[i].xl_map); 1763 m_freem(cd->xl_rx_chain[i].xl_mbuf); 1764 } 1765 bus_dmamap_destroy(sc->xl_rx_mtag, 1766 cd->xl_rx_chain[i].xl_map); 1767 } 1768 } 1769 1770 for (i = 0; i < XL_TX_LIST_CNT; ++i) { 1771 if (cd->xl_tx_chain[i].xl_ptr != NULL) { 1772 if (cd->xl_tx_chain[i].xl_mbuf != NULL) { 1773 bus_dmamap_unload(sc->xl_tx_mtag, 1774 cd->xl_tx_chain[i].xl_map); 1775 m_freem(cd->xl_tx_chain[i].xl_mbuf); 1776 } 1777 bus_dmamap_destroy(sc->xl_tx_mtag, 1778 cd->xl_tx_chain[i].xl_map); 1779 } 1780 } 1781 1782 if (ld->xl_rx_tag) { 1783 bus_dmamap_unload(ld->xl_rx_tag, ld->xl_rx_dmamap); 1784 bus_dmamem_free(ld->xl_rx_tag, ld->xl_rx_list, 1785 ld->xl_rx_dmamap); 1786 bus_dma_tag_destroy(ld->xl_rx_tag); 1787 } 1788 1789 if (ld->xl_tx_tag) { 1790 bus_dmamap_unload(ld->xl_tx_tag, ld->xl_tx_dmamap); 1791 bus_dmamem_free(ld->xl_tx_tag, ld->xl_tx_list, 1792 ld->xl_tx_dmamap); 1793 bus_dma_tag_destroy(ld->xl_tx_tag); 1794 } 1795 1796 if (sc->xl_rx_mtag) { 1797 bus_dmamap_destroy(sc->xl_rx_mtag, sc->xl_tmpmap); 1798 bus_dma_tag_destroy(sc->xl_rx_mtag); 1799 } 1800 if (sc->xl_tx_mtag) 1801 bus_dma_tag_destroy(sc->xl_tx_mtag); 1802 1803 if (sc->xl_parent_tag) 1804 bus_dma_tag_destroy(sc->xl_parent_tag); 1805 } 1806 1807 /* 1808 * Initialize the transmit descriptors. 1809 */ 1810 static void 1811 xl_list_tx_init(struct xl_softc *sc) 1812 { 1813 struct xl_chain_data *cd; 1814 struct xl_list_data *ld; 1815 int i; 1816 1817 cd = &sc->xl_cdata; 1818 ld = &sc->xl_ldata; 1819 for (i = 0; i < XL_TX_LIST_CNT; i++) { 1820 cd->xl_tx_chain[i].xl_phys = ld->xl_tx_dmaaddr + 1821 i * sizeof(struct xl_list); 1822 if (i == (XL_TX_LIST_CNT - 1)) 1823 cd->xl_tx_chain[i].xl_next = NULL; 1824 else 1825 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[i + 1]; 1826 } 1827 1828 cd->xl_tx_free = &cd->xl_tx_chain[0]; 1829 cd->xl_tx_tail = cd->xl_tx_head = NULL; 1830 } 1831 1832 /* 1833 * Initialize the transmit descriptors. 1834 */ 1835 static void 1836 xl_list_tx_init_90xB(struct xl_softc *sc) 1837 { 1838 struct xl_chain_data *cd; 1839 struct xl_list_data *ld; 1840 int i; 1841 1842 cd = &sc->xl_cdata; 1843 ld = &sc->xl_ldata; 1844 for (i = 0; i < XL_TX_LIST_CNT; i++) { 1845 cd->xl_tx_chain[i].xl_phys = ld->xl_tx_dmaaddr + 1846 i * sizeof(struct xl_list); 1847 if (i == (XL_TX_LIST_CNT - 1)) 1848 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[0]; 1849 else 1850 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[i + 1]; 1851 if (i == 0) { 1852 cd->xl_tx_chain[i].xl_prev = 1853 &cd->xl_tx_chain[XL_TX_LIST_CNT - 1]; 1854 } else { 1855 cd->xl_tx_chain[i].xl_prev = 1856 &cd->xl_tx_chain[i - 1]; 1857 } 1858 } 1859 1860 ld->xl_tx_list[0].xl_status = htole32(XL_TXSTAT_EMPTY); 1861 1862 cd->xl_tx_prod = 1; 1863 cd->xl_tx_cons = 1; 1864 cd->xl_tx_cnt = 0; 1865 } 1866 1867 /* 1868 * Initialize the RX descriptors and allocate mbufs for them. Note that 1869 * we arrange the descriptors in a closed ring, so that the last descriptor 1870 * points back to the first. 1871 */ 1872 static int 1873 xl_list_rx_init(struct xl_softc *sc) 1874 { 1875 struct xl_chain_data *cd; 1876 struct xl_list_data *ld; 1877 int error, i, next; 1878 u_int32_t nextptr; 1879 1880 cd = &sc->xl_cdata; 1881 ld = &sc->xl_ldata; 1882 1883 for (i = 0; i < XL_RX_LIST_CNT; i++) { 1884 error = xl_newbuf(sc, &cd->xl_rx_chain[i], 1); 1885 if (error) 1886 return(error); 1887 if (i == (XL_RX_LIST_CNT - 1)) 1888 next = 0; 1889 else 1890 next = i + 1; 1891 nextptr = ld->xl_rx_dmaaddr + 1892 next * sizeof(struct xl_list_onefrag); 1893 cd->xl_rx_chain[i].xl_next = &cd->xl_rx_chain[next]; 1894 ld->xl_rx_list[i].xl_next = htole32(nextptr); 1895 } 1896 1897 cd->xl_rx_head = &cd->xl_rx_chain[0]; 1898 1899 return(0); 1900 } 1901 1902 /* 1903 * Initialize an RX descriptor and attach an MBUF cluster. 1904 * If we fail to do so, we need to leave the old mbuf and 1905 * the old DMA map untouched so that it can be reused. 1906 */ 1907 static int 1908 xl_newbuf(struct xl_softc *sc, struct xl_chain_onefrag *c, int init) 1909 { 1910 struct mbuf *m_new; 1911 bus_dmamap_t map; 1912 int error, nsegs; 1913 bus_dma_segment_t seg; 1914 1915 m_new = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR); 1916 if (m_new == NULL) 1917 return(ENOBUFS); 1918 1919 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1920 1921 /* Force longword alignment for packet payload. */ 1922 m_adj(m_new, ETHER_ALIGN); 1923 1924 error = bus_dmamap_load_mbuf_segment(sc->xl_rx_mtag, sc->xl_tmpmap, 1925 m_new, &seg, 1, &nsegs, BUS_DMA_NOWAIT); 1926 if (error) { 1927 m_freem(m_new); 1928 if (init) { 1929 if_printf(&sc->arpcom.ac_if, 1930 "can't map mbuf (error %d)\n", error); 1931 } 1932 return(error); 1933 } 1934 1935 if (c->xl_mbuf != NULL) { 1936 bus_dmamap_sync(sc->xl_rx_mtag, c->xl_map, 1937 BUS_DMASYNC_POSTREAD); 1938 bus_dmamap_unload(sc->xl_rx_mtag, c->xl_map); 1939 } 1940 1941 map = c->xl_map; 1942 c->xl_map = sc->xl_tmpmap; 1943 sc->xl_tmpmap = map; 1944 c->xl_mbuf = m_new; 1945 1946 c->xl_ptr->xl_frag.xl_len = htole32(seg.ds_len | XL_LAST_FRAG); 1947 c->xl_ptr->xl_frag.xl_addr = htole32(seg.ds_addr); 1948 c->xl_ptr->xl_status = 0; 1949 1950 return(0); 1951 } 1952 1953 static int 1954 xl_rx_resync(struct xl_softc *sc) 1955 { 1956 struct xl_chain_onefrag *pos; 1957 int i; 1958 1959 pos = sc->xl_cdata.xl_rx_head; 1960 1961 for (i = 0; i < XL_RX_LIST_CNT; i++) { 1962 if (pos->xl_ptr->xl_status) 1963 break; 1964 pos = pos->xl_next; 1965 } 1966 1967 if (i == XL_RX_LIST_CNT) 1968 return(0); 1969 1970 sc->xl_cdata.xl_rx_head = pos; 1971 1972 return(EAGAIN); 1973 } 1974 1975 /* 1976 * A frame has been uploaded: pass the resulting mbuf chain up to 1977 * the higher level protocols. 1978 */ 1979 static void 1980 xl_rxeof(struct xl_softc *sc, int count) 1981 { 1982 struct mbuf *m; 1983 struct ifnet *ifp; 1984 struct xl_chain_onefrag *cur_rx; 1985 int total_len = 0; 1986 u_int32_t rxstat; 1987 1988 ifp = &sc->arpcom.ac_if; 1989 again: 1990 while((rxstat = le32toh(sc->xl_cdata.xl_rx_head->xl_ptr->xl_status))) { 1991 #ifdef IFPOLL_ENABLE 1992 if (count >= 0 && count-- == 0) 1993 break; 1994 #endif 1995 cur_rx = sc->xl_cdata.xl_rx_head; 1996 sc->xl_cdata.xl_rx_head = cur_rx->xl_next; 1997 total_len = rxstat & XL_RXSTAT_LENMASK; 1998 1999 /* 2000 * Since we have told the chip to allow large frames, 2001 * we need to trap giant frame errors in software. We allow 2002 * a little more than the normal frame size to account for 2003 * frames with VLAN tags. 2004 */ 2005 if (total_len > XL_MAX_FRAMELEN) 2006 rxstat |= (XL_RXSTAT_UP_ERROR|XL_RXSTAT_OVERSIZE); 2007 2008 /* 2009 * If an error occurs, update stats, clear the 2010 * status word and leave the mbuf cluster in place: 2011 * it should simply get re-used next time this descriptor 2012 * comes up in the ring. 2013 */ 2014 if (rxstat & XL_RXSTAT_UP_ERROR) { 2015 ifp->if_ierrors++; 2016 cur_rx->xl_ptr->xl_status = 0; 2017 continue; 2018 } 2019 2020 /* 2021 * If the error bit was not set, the upload complete 2022 * bit should be set which means we have a valid packet. 2023 * If not, something truly strange has happened. 2024 */ 2025 if (!(rxstat & XL_RXSTAT_UP_CMPLT)) { 2026 if_printf(ifp, 2027 "bad receive status -- packet dropped\n"); 2028 ifp->if_ierrors++; 2029 cur_rx->xl_ptr->xl_status = 0; 2030 continue; 2031 } 2032 2033 /* No errors; receive the packet. */ 2034 m = cur_rx->xl_mbuf; 2035 2036 /* 2037 * Try to conjure up a new mbuf cluster. If that 2038 * fails, it means we have an out of memory condition and 2039 * should leave the buffer in place and continue. This will 2040 * result in a lost packet, but there's little else we 2041 * can do in this situation. 2042 */ 2043 if (xl_newbuf(sc, cur_rx, 0)) { 2044 ifp->if_ierrors++; 2045 cur_rx->xl_ptr->xl_status = 0; 2046 continue; 2047 } 2048 2049 ifp->if_ipackets++; 2050 m->m_pkthdr.rcvif = ifp; 2051 m->m_pkthdr.len = m->m_len = total_len; 2052 2053 if (ifp->if_capenable & IFCAP_RXCSUM) { 2054 /* Do IP checksum checking. */ 2055 if (rxstat & XL_RXSTAT_IPCKOK) 2056 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 2057 if (!(rxstat & XL_RXSTAT_IPCKERR)) 2058 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 2059 if ((rxstat & XL_RXSTAT_TCPCOK && 2060 !(rxstat & XL_RXSTAT_TCPCKERR)) || 2061 (rxstat & XL_RXSTAT_UDPCKOK && 2062 !(rxstat & XL_RXSTAT_UDPCKERR))) { 2063 m->m_pkthdr.csum_flags |= 2064 CSUM_DATA_VALID|CSUM_PSEUDO_HDR| 2065 CSUM_FRAG_NOT_CHECKED; 2066 m->m_pkthdr.csum_data = 0xffff; 2067 } 2068 } 2069 2070 ifp->if_input(ifp, m); 2071 } 2072 2073 if (sc->xl_type != XL_TYPE_905B) { 2074 /* 2075 * Handle the 'end of channel' condition. When the upload 2076 * engine hits the end of the RX ring, it will stall. This 2077 * is our cue to flush the RX ring, reload the uplist pointer 2078 * register and unstall the engine. 2079 * XXX This is actually a little goofy. With the ThunderLAN 2080 * chip, you get an interrupt when the receiver hits the end 2081 * of the receive ring, which tells you exactly when you 2082 * you need to reload the ring pointer. Here we have to 2083 * fake it. I'm mad at myself for not being clever enough 2084 * to avoid the use of a goto here. 2085 */ 2086 if (CSR_READ_4(sc, XL_UPLIST_PTR) == 0 || 2087 CSR_READ_4(sc, XL_UPLIST_STATUS) & XL_PKTSTAT_UP_STALLED) { 2088 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_STALL); 2089 xl_wait(sc); 2090 CSR_WRITE_4(sc, XL_UPLIST_PTR, 2091 sc->xl_ldata.xl_rx_dmaaddr); 2092 sc->xl_cdata.xl_rx_head = &sc->xl_cdata.xl_rx_chain[0]; 2093 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_UNSTALL); 2094 goto again; 2095 } 2096 } 2097 } 2098 2099 /* 2100 * A frame was downloaded to the chip. It's safe for us to clean up 2101 * the list buffers. 2102 */ 2103 static void 2104 xl_txeof(struct xl_softc *sc) 2105 { 2106 struct xl_chain *cur_tx; 2107 struct ifnet *ifp; 2108 2109 ifp = &sc->arpcom.ac_if; 2110 2111 /* Clear the timeout timer. */ 2112 ifp->if_timer = 0; 2113 2114 /* 2115 * Go through our tx list and free mbufs for those 2116 * frames that have been uploaded. Note: the 3c905B 2117 * sets a special bit in the status word to let us 2118 * know that a frame has been downloaded, but the 2119 * original 3c900/3c905 adapters don't do that. 2120 * Consequently, we have to use a different test if 2121 * xl_type != XL_TYPE_905B. 2122 */ 2123 while(sc->xl_cdata.xl_tx_head != NULL) { 2124 cur_tx = sc->xl_cdata.xl_tx_head; 2125 2126 if (CSR_READ_4(sc, XL_DOWNLIST_PTR)) 2127 break; 2128 2129 sc->xl_cdata.xl_tx_head = cur_tx->xl_next; 2130 bus_dmamap_unload(sc->xl_tx_mtag, cur_tx->xl_map); 2131 m_freem(cur_tx->xl_mbuf); 2132 cur_tx->xl_mbuf = NULL; 2133 ifp->if_opackets++; 2134 2135 cur_tx->xl_next = sc->xl_cdata.xl_tx_free; 2136 sc->xl_cdata.xl_tx_free = cur_tx; 2137 } 2138 2139 if (sc->xl_cdata.xl_tx_head == NULL) { 2140 ifp->if_flags &= ~IFF_OACTIVE; 2141 sc->xl_cdata.xl_tx_tail = NULL; 2142 } else { 2143 if (CSR_READ_4(sc, XL_DMACTL) & XL_DMACTL_DOWN_STALLED || 2144 !CSR_READ_4(sc, XL_DOWNLIST_PTR)) { 2145 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, 2146 sc->xl_cdata.xl_tx_head->xl_phys); 2147 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); 2148 } 2149 } 2150 2151 return; 2152 } 2153 2154 static void 2155 xl_txeof_90xB(struct xl_softc *sc) 2156 { 2157 struct xl_chain *cur_tx = NULL; 2158 struct ifnet *ifp; 2159 int idx; 2160 2161 ifp = &sc->arpcom.ac_if; 2162 2163 idx = sc->xl_cdata.xl_tx_cons; 2164 while(idx != sc->xl_cdata.xl_tx_prod) { 2165 2166 cur_tx = &sc->xl_cdata.xl_tx_chain[idx]; 2167 2168 if (!(le32toh(cur_tx->xl_ptr->xl_status) & 2169 XL_TXSTAT_DL_COMPLETE)) 2170 break; 2171 2172 if (cur_tx->xl_mbuf != NULL) { 2173 bus_dmamap_unload(sc->xl_tx_mtag, cur_tx->xl_map); 2174 m_freem(cur_tx->xl_mbuf); 2175 cur_tx->xl_mbuf = NULL; 2176 } 2177 2178 ifp->if_opackets++; 2179 2180 sc->xl_cdata.xl_tx_cnt--; 2181 XL_INC(idx, XL_TX_LIST_CNT); 2182 ifp->if_timer = 0; 2183 } 2184 2185 sc->xl_cdata.xl_tx_cons = idx; 2186 2187 if (cur_tx != NULL) 2188 ifp->if_flags &= ~IFF_OACTIVE; 2189 2190 return; 2191 } 2192 2193 /* 2194 * TX 'end of channel' interrupt handler. Actually, we should 2195 * only get a 'TX complete' interrupt if there's a transmit error, 2196 * so this is really TX error handler. 2197 */ 2198 static void 2199 xl_txeoc(struct xl_softc *sc) 2200 { 2201 struct ifnet *ifp = &sc->arpcom.ac_if; 2202 u_int8_t txstat; 2203 2204 while((txstat = CSR_READ_1(sc, XL_TX_STATUS))) { 2205 if (txstat & XL_TXSTATUS_UNDERRUN || 2206 txstat & XL_TXSTATUS_JABBER || 2207 txstat & XL_TXSTATUS_RECLAIM) { 2208 if_printf(ifp, "transmission error: %x\n", txstat); 2209 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); 2210 xl_wait(sc); 2211 if (sc->xl_type == XL_TYPE_905B) { 2212 if (sc->xl_cdata.xl_tx_cnt) { 2213 int i; 2214 struct xl_chain *c; 2215 i = sc->xl_cdata.xl_tx_cons; 2216 c = &sc->xl_cdata.xl_tx_chain[i]; 2217 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, 2218 c->xl_phys); 2219 CSR_WRITE_1(sc, XL_DOWN_POLL, 64); 2220 } 2221 } else { 2222 if (sc->xl_cdata.xl_tx_head != NULL) 2223 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, 2224 sc->xl_cdata.xl_tx_head->xl_phys); 2225 } 2226 /* 2227 * Remember to set this for the 2228 * first generation 3c90X chips. 2229 */ 2230 CSR_WRITE_1(sc, XL_TX_FREETHRESH, XL_PACKET_SIZE >> 8); 2231 if (txstat & XL_TXSTATUS_UNDERRUN && 2232 sc->xl_tx_thresh < XL_PACKET_SIZE) { 2233 sc->xl_tx_thresh += XL_MIN_FRAMELEN; 2234 if_printf(ifp, "tx underrun, increasing tx start" 2235 " threshold to %d bytes\n", 2236 sc->xl_tx_thresh); 2237 } 2238 CSR_WRITE_2(sc, XL_COMMAND, 2239 XL_CMD_TX_SET_START|sc->xl_tx_thresh); 2240 if (sc->xl_type == XL_TYPE_905B) { 2241 CSR_WRITE_2(sc, XL_COMMAND, 2242 XL_CMD_SET_TX_RECLAIM|(XL_PACKET_SIZE >> 4)); 2243 } 2244 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE); 2245 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); 2246 } else { 2247 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE); 2248 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); 2249 } 2250 /* 2251 * Write an arbitrary byte to the TX_STATUS register 2252 * to clear this interrupt/error and advance to the next. 2253 */ 2254 CSR_WRITE_1(sc, XL_TX_STATUS, 0x01); 2255 } 2256 2257 return; 2258 } 2259 2260 #ifdef IFPOLL_ENABLE 2261 2262 static void 2263 xl_start_poll(struct ifnet *ifp) 2264 { 2265 xl_start_body(ifp, 0); 2266 } 2267 2268 static void 2269 xl_npoll_compat(struct ifnet *ifp, void *arg __unused, int count) 2270 { 2271 struct xl_softc *sc = ifp->if_softc; 2272 2273 ASSERT_SERIALIZED(ifp->if_serializer); 2274 2275 if (sc->xl_npoll.ifpc_stcount-- == 0) { 2276 uint16_t status; 2277 2278 sc->xl_npoll.ifpc_stcount = sc->xl_npoll.ifpc_stfrac; 2279 2280 /* XXX copy & pasted from xl_intr() */ 2281 status = CSR_READ_2(sc, XL_STATUS); 2282 if ((status & XL_INTRS) && status != 0xFFFF) { 2283 CSR_WRITE_2(sc, XL_COMMAND, 2284 XL_CMD_INTR_ACK | (status & XL_INTRS)); 2285 2286 if (status & XL_STAT_TX_COMPLETE) { 2287 ifp->if_oerrors++; 2288 xl_txeoc(sc); 2289 } 2290 2291 if (status & XL_STAT_ADFAIL) { 2292 xl_reset(sc); 2293 xl_init(sc); 2294 } 2295 2296 if (status & XL_STAT_STATSOFLOW) { 2297 sc->xl_stats_no_timeout = 1; 2298 xl_stats_update_serialized(sc); 2299 sc->xl_stats_no_timeout = 0; 2300 } 2301 } 2302 } 2303 2304 xl_rxeof(sc, count); 2305 if (sc->xl_type == XL_TYPE_905B) 2306 xl_txeof_90xB(sc); 2307 else 2308 xl_txeof(sc); 2309 2310 if (!ifq_is_empty(&ifp->if_snd)) 2311 if_devstart(ifp); 2312 } 2313 2314 static void 2315 xl_npoll(struct ifnet *ifp, struct ifpoll_info *info) 2316 { 2317 struct xl_softc *sc = ifp->if_softc; 2318 2319 ASSERT_SERIALIZED(ifp->if_serializer); 2320 2321 if (info != NULL) { 2322 int cpuid = sc->xl_npoll.ifpc_cpuid; 2323 2324 info->ifpi_rx[cpuid].poll_func = xl_npoll_compat; 2325 info->ifpi_rx[cpuid].arg = NULL; 2326 info->ifpi_rx[cpuid].serializer = ifp->if_serializer; 2327 2328 if (ifp->if_flags & IFF_RUNNING) 2329 xl_enable_intrs(sc, 0); 2330 if (sc->xl_type != XL_TYPE_905B) 2331 ifp->if_start = xl_start_poll; 2332 ifp->if_npoll_cpuid = cpuid; 2333 } else { 2334 if (sc->xl_type != XL_TYPE_905B) 2335 ifp->if_start = xl_start; 2336 if (ifp->if_flags & IFF_RUNNING) 2337 xl_enable_intrs(sc, XL_INTRS); 2338 ifp->if_npoll_cpuid = -1; 2339 } 2340 } 2341 2342 #endif /* IFPOLL_ENABLE */ 2343 2344 static void 2345 xl_intr(void *arg) 2346 { 2347 struct xl_softc *sc; 2348 struct ifnet *ifp; 2349 u_int16_t status; 2350 2351 sc = arg; 2352 ifp = &sc->arpcom.ac_if; 2353 2354 ASSERT_SERIALIZED(ifp->if_serializer); 2355 2356 while(((status = CSR_READ_2(sc, XL_STATUS)) & XL_INTRS) && 2357 status != 0xFFFF) { 2358 2359 CSR_WRITE_2(sc, XL_COMMAND, 2360 XL_CMD_INTR_ACK|(status & XL_INTRS)); 2361 2362 if (status & XL_STAT_UP_COMPLETE) { 2363 int curpkts; 2364 2365 curpkts = ifp->if_ipackets; 2366 xl_rxeof(sc, -1); 2367 if (curpkts == ifp->if_ipackets) { 2368 while (xl_rx_resync(sc)) 2369 xl_rxeof(sc, -1); 2370 } 2371 } 2372 2373 if (status & XL_STAT_DOWN_COMPLETE) { 2374 if (sc->xl_type == XL_TYPE_905B) 2375 xl_txeof_90xB(sc); 2376 else 2377 xl_txeof(sc); 2378 } 2379 2380 if (status & XL_STAT_TX_COMPLETE) { 2381 ifp->if_oerrors++; 2382 xl_txeoc(sc); 2383 } 2384 2385 if (status & XL_STAT_ADFAIL) { 2386 xl_reset(sc); 2387 xl_init(sc); 2388 } 2389 2390 if (status & XL_STAT_STATSOFLOW) { 2391 sc->xl_stats_no_timeout = 1; 2392 xl_stats_update_serialized(sc); 2393 sc->xl_stats_no_timeout = 0; 2394 } 2395 } 2396 2397 if (!ifq_is_empty(&ifp->if_snd)) 2398 if_devstart(ifp); 2399 } 2400 2401 static void 2402 xl_stats_update(void *xsc) 2403 { 2404 struct xl_softc *sc = xsc; 2405 2406 lwkt_serialize_enter(sc->arpcom.ac_if.if_serializer); 2407 xl_stats_update_serialized(xsc); 2408 lwkt_serialize_exit(sc->arpcom.ac_if.if_serializer); 2409 } 2410 2411 static void 2412 xl_stats_update_serialized(void *xsc) 2413 { 2414 struct xl_softc *sc; 2415 struct ifnet *ifp; 2416 struct xl_stats xl_stats; 2417 u_int8_t *p; 2418 int i; 2419 struct mii_data *mii = NULL; 2420 2421 bzero((char *)&xl_stats, sizeof(struct xl_stats)); 2422 2423 sc = xsc; 2424 ifp = &sc->arpcom.ac_if; 2425 if (sc->xl_miibus != NULL) 2426 mii = device_get_softc(sc->xl_miibus); 2427 2428 p = (u_int8_t *)&xl_stats; 2429 2430 /* Read all the stats registers. */ 2431 XL_SEL_WIN(6); 2432 2433 for (i = 0; i < 16; i++) 2434 *p++ = CSR_READ_1(sc, XL_W6_CARRIER_LOST + i); 2435 2436 ifp->if_ierrors += xl_stats.xl_rx_overrun; 2437 2438 ifp->if_collisions += xl_stats.xl_tx_multi_collision + 2439 xl_stats.xl_tx_single_collision + 2440 xl_stats.xl_tx_late_collision; 2441 2442 /* 2443 * Boomerang and cyclone chips have an extra stats counter 2444 * in window 4 (BadSSD). We have to read this too in order 2445 * to clear out all the stats registers and avoid a statsoflow 2446 * interrupt. 2447 */ 2448 XL_SEL_WIN(4); 2449 CSR_READ_1(sc, XL_W4_BADSSD); 2450 2451 if ((mii != NULL) && (!sc->xl_stats_no_timeout)) 2452 mii_tick(mii); 2453 2454 XL_SEL_WIN(7); 2455 2456 if (!sc->xl_stats_no_timeout) 2457 callout_reset(&sc->xl_stat_timer, hz, xl_stats_update, sc); 2458 2459 return; 2460 } 2461 2462 /* 2463 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 2464 * pointers to the fragment pointers. 2465 */ 2466 static int 2467 xl_encap(struct xl_softc *sc, struct xl_chain *c, struct mbuf *m_head) 2468 { 2469 int error, nsegs, i; 2470 u_int32_t status; 2471 bus_dma_segment_t segs[XL_MAXFRAGS]; 2472 struct xl_list *l; 2473 2474 error = bus_dmamap_load_mbuf_defrag(sc->xl_tx_mtag, c->xl_map, &m_head, 2475 segs, XL_MAXFRAGS, &nsegs, BUS_DMA_NOWAIT); 2476 if (error) { 2477 m_freem(m_head); 2478 return error; 2479 } 2480 bus_dmamap_sync(sc->xl_tx_mtag, c->xl_map, BUS_DMASYNC_PREWRITE); 2481 2482 if (sc->xl_type == XL_TYPE_905B) { 2483 status = XL_TXSTAT_RND_DEFEAT; 2484 if (m_head->m_pkthdr.csum_flags) { 2485 if (m_head->m_pkthdr.csum_flags & CSUM_IP) 2486 status |= XL_TXSTAT_IPCKSUM; 2487 if (m_head->m_pkthdr.csum_flags & CSUM_TCP) 2488 status |= XL_TXSTAT_TCPCKSUM; 2489 if (m_head->m_pkthdr.csum_flags & CSUM_UDP) 2490 status |= XL_TXSTAT_UDPCKSUM; 2491 } 2492 } else { 2493 status = m_head->m_pkthdr.len; 2494 } 2495 2496 l = c->xl_ptr; 2497 for (i = 0; i < nsegs; i++) { 2498 l->xl_frag[i].xl_addr = htole32(segs[i].ds_addr); 2499 l->xl_frag[i].xl_len = htole32(segs[i].ds_len); 2500 } 2501 l->xl_frag[nsegs - 1].xl_len = 2502 htole32(segs[nsegs - 1].ds_len | XL_LAST_FRAG); 2503 l->xl_status = htole32(status); 2504 l->xl_next = 0; 2505 2506 c->xl_mbuf = m_head; 2507 2508 return(0); 2509 } 2510 2511 static void 2512 xl_start(struct ifnet *ifp) 2513 { 2514 ASSERT_SERIALIZED(ifp->if_serializer); 2515 xl_start_body(ifp, 1); 2516 } 2517 2518 /* 2519 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 2520 * to the mbuf data regions directly in the transmit lists. We also save a 2521 * copy of the pointers since the transmit list fragment pointers are 2522 * physical addresses. 2523 */ 2524 static void 2525 xl_start_body(struct ifnet *ifp, int proc_rx) 2526 { 2527 struct xl_softc *sc; 2528 struct mbuf *m_head = NULL; 2529 struct xl_chain *prev = NULL, *cur_tx = NULL, *start_tx; 2530 struct xl_chain *prev_tx; 2531 u_int32_t status; 2532 int error; 2533 2534 sc = ifp->if_softc; 2535 /* 2536 * Check for an available queue slot. If there are none, 2537 * punt. 2538 */ 2539 if (sc->xl_cdata.xl_tx_free == NULL) { 2540 xl_txeoc(sc); 2541 xl_txeof(sc); 2542 if (sc->xl_cdata.xl_tx_free == NULL) { 2543 ifp->if_flags |= IFF_OACTIVE; 2544 return; 2545 } 2546 } 2547 2548 start_tx = sc->xl_cdata.xl_tx_free; 2549 2550 while(sc->xl_cdata.xl_tx_free != NULL) { 2551 m_head = ifq_dequeue(&ifp->if_snd, NULL); 2552 if (m_head == NULL) 2553 break; 2554 2555 /* Pick a descriptor off the free list. */ 2556 prev_tx = cur_tx; 2557 cur_tx = sc->xl_cdata.xl_tx_free; 2558 2559 /* Pack the data into the descriptor. */ 2560 error = xl_encap(sc, cur_tx, m_head); 2561 if (error) { 2562 cur_tx = prev_tx; 2563 continue; 2564 } 2565 2566 sc->xl_cdata.xl_tx_free = cur_tx->xl_next; 2567 cur_tx->xl_next = NULL; 2568 2569 /* Chain it together. */ 2570 if (prev != NULL) { 2571 prev->xl_next = cur_tx; 2572 prev->xl_ptr->xl_next = htole32(cur_tx->xl_phys); 2573 } 2574 prev = cur_tx; 2575 2576 BPF_MTAP(ifp, cur_tx->xl_mbuf); 2577 } 2578 2579 /* 2580 * If there are no packets queued, bail. 2581 */ 2582 if (cur_tx == NULL) 2583 return; 2584 2585 /* 2586 * Place the request for the upload interrupt 2587 * in the last descriptor in the chain. This way, if 2588 * we're chaining several packets at once, we'll only 2589 * get an interupt once for the whole chain rather than 2590 * once for each packet. 2591 */ 2592 cur_tx->xl_ptr->xl_status = htole32(le32toh(cur_tx->xl_ptr->xl_status) | 2593 XL_TXSTAT_DL_INTR); 2594 2595 /* 2596 * Queue the packets. If the TX channel is clear, update 2597 * the downlist pointer register. 2598 */ 2599 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_STALL); 2600 xl_wait(sc); 2601 2602 if (sc->xl_cdata.xl_tx_head != NULL) { 2603 sc->xl_cdata.xl_tx_tail->xl_next = start_tx; 2604 sc->xl_cdata.xl_tx_tail->xl_ptr->xl_next = 2605 htole32(start_tx->xl_phys); 2606 status = sc->xl_cdata.xl_tx_tail->xl_ptr->xl_status; 2607 sc->xl_cdata.xl_tx_tail->xl_ptr->xl_status = 2608 htole32(le32toh(status) & ~XL_TXSTAT_DL_INTR); 2609 sc->xl_cdata.xl_tx_tail = cur_tx; 2610 } else { 2611 sc->xl_cdata.xl_tx_head = start_tx; 2612 sc->xl_cdata.xl_tx_tail = cur_tx; 2613 } 2614 2615 if (!CSR_READ_4(sc, XL_DOWNLIST_PTR)) 2616 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, start_tx->xl_phys); 2617 2618 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); 2619 2620 XL_SEL_WIN(7); 2621 2622 /* 2623 * Set a timeout in case the chip goes out to lunch. 2624 */ 2625 ifp->if_timer = 5; 2626 2627 if (proc_rx) { 2628 /* 2629 * XXX Under certain conditions, usually on slower machines 2630 * where interrupts may be dropped, it's possible for the 2631 * adapter to chew up all the buffers in the receive ring 2632 * and stall, without us being able to do anything about it. 2633 * To guard against this, we need to make a pass over the 2634 * RX queue to make sure there aren't any packets pending. 2635 * Doing it here means we can flush the receive ring at the 2636 * same time the chip is DMAing the transmit descriptors we 2637 * just gave it. 2638 * 2639 * 3Com goes to some lengths to emphasize the Parallel 2640 * Tasking (tm) nature of their chips in all their marketing 2641 * literature; we may as well take advantage of it. :) 2642 */ 2643 xl_rxeof(sc, -1); 2644 } 2645 } 2646 2647 static void 2648 xl_start_90xB(struct ifnet *ifp) 2649 { 2650 struct xl_softc *sc; 2651 struct mbuf *m_head = NULL; 2652 struct xl_chain *prev = NULL, *cur_tx = NULL, *start_tx; 2653 struct xl_chain *prev_tx; 2654 int error, idx; 2655 2656 ASSERT_SERIALIZED(ifp->if_serializer); 2657 2658 sc = ifp->if_softc; 2659 2660 if ((ifp->if_flags & (IFF_OACTIVE | IFF_RUNNING)) != IFF_RUNNING) 2661 return; 2662 2663 idx = sc->xl_cdata.xl_tx_prod; 2664 start_tx = &sc->xl_cdata.xl_tx_chain[idx]; 2665 2666 while (sc->xl_cdata.xl_tx_chain[idx].xl_mbuf == NULL) { 2667 2668 if ((XL_TX_LIST_CNT - sc->xl_cdata.xl_tx_cnt) < 3) { 2669 ifp->if_flags |= IFF_OACTIVE; 2670 break; 2671 } 2672 2673 m_head = ifq_dequeue(&ifp->if_snd, NULL); 2674 if (m_head == NULL) 2675 break; 2676 2677 prev_tx = cur_tx; 2678 cur_tx = &sc->xl_cdata.xl_tx_chain[idx]; 2679 2680 /* Pack the data into the descriptor. */ 2681 error = xl_encap(sc, cur_tx, m_head); 2682 if (error) { 2683 cur_tx = prev_tx; 2684 continue; 2685 } 2686 2687 /* Chain it together. */ 2688 if (prev != NULL) 2689 prev->xl_ptr->xl_next = htole32(cur_tx->xl_phys); 2690 prev = cur_tx; 2691 2692 BPF_MTAP(ifp, cur_tx->xl_mbuf); 2693 2694 XL_INC(idx, XL_TX_LIST_CNT); 2695 sc->xl_cdata.xl_tx_cnt++; 2696 } 2697 2698 /* 2699 * If there are no packets queued, bail. 2700 */ 2701 if (cur_tx == NULL) 2702 return; 2703 2704 /* 2705 * Place the request for the upload interrupt 2706 * in the last descriptor in the chain. This way, if 2707 * we're chaining several packets at once, we'll only 2708 * get an interupt once for the whole chain rather than 2709 * once for each packet. 2710 */ 2711 cur_tx->xl_ptr->xl_status = htole32(le32toh(cur_tx->xl_ptr->xl_status) | 2712 XL_TXSTAT_DL_INTR); 2713 2714 /* Start transmission */ 2715 sc->xl_cdata.xl_tx_prod = idx; 2716 start_tx->xl_prev->xl_ptr->xl_next = htole32(start_tx->xl_phys); 2717 2718 /* 2719 * Set a timeout in case the chip goes out to lunch. 2720 */ 2721 ifp->if_timer = 5; 2722 } 2723 2724 static void 2725 xl_init(void *xsc) 2726 { 2727 struct xl_softc *sc = xsc; 2728 struct ifnet *ifp = &sc->arpcom.ac_if; 2729 int error, i; 2730 u_int16_t rxfilt = 0; 2731 struct mii_data *mii = NULL; 2732 2733 ASSERT_SERIALIZED(ifp->if_serializer); 2734 2735 /* 2736 * Cancel pending I/O and free all RX/TX buffers. 2737 */ 2738 xl_stop(sc); 2739 2740 if (sc->xl_miibus == NULL) { 2741 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET); 2742 xl_wait(sc); 2743 } 2744 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); 2745 xl_wait(sc); 2746 DELAY(10000); 2747 2748 if (sc->xl_miibus != NULL) 2749 mii = device_get_softc(sc->xl_miibus); 2750 2751 /* Init our MAC address */ 2752 XL_SEL_WIN(2); 2753 for (i = 0; i < ETHER_ADDR_LEN; i++) { 2754 CSR_WRITE_1(sc, XL_W2_STATION_ADDR_LO + i, 2755 sc->arpcom.ac_enaddr[i]); 2756 } 2757 2758 /* Clear the station mask. */ 2759 for (i = 0; i < 3; i++) 2760 CSR_WRITE_2(sc, XL_W2_STATION_MASK_LO + (i * 2), 0); 2761 #ifdef notdef 2762 /* Reset TX and RX. */ 2763 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET); 2764 xl_wait(sc); 2765 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); 2766 xl_wait(sc); 2767 #endif 2768 /* Init circular RX list. */ 2769 error = xl_list_rx_init(sc); 2770 if (error) { 2771 if_printf(ifp, "initialization of the rx ring failed (%d)\n", 2772 error); 2773 xl_stop(sc); 2774 return; 2775 } 2776 2777 /* Init TX descriptors. */ 2778 if (sc->xl_type == XL_TYPE_905B) 2779 xl_list_tx_init_90xB(sc); 2780 else 2781 xl_list_tx_init(sc); 2782 2783 /* 2784 * Set the TX freethresh value. 2785 * Note that this has no effect on 3c905B "cyclone" 2786 * cards but is required for 3c900/3c905 "boomerang" 2787 * cards in order to enable the download engine. 2788 */ 2789 CSR_WRITE_1(sc, XL_TX_FREETHRESH, XL_PACKET_SIZE >> 8); 2790 2791 /* Set the TX start threshold for best performance. */ 2792 sc->xl_tx_thresh = XL_MIN_FRAMELEN; 2793 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_SET_START|sc->xl_tx_thresh); 2794 2795 /* 2796 * If this is a 3c905B, also set the tx reclaim threshold. 2797 * This helps cut down on the number of tx reclaim errors 2798 * that could happen on a busy network. The chip multiplies 2799 * the register value by 16 to obtain the actual threshold 2800 * in bytes, so we divide by 16 when setting the value here. 2801 * The existing threshold value can be examined by reading 2802 * the register at offset 9 in window 5. 2803 */ 2804 if (sc->xl_type == XL_TYPE_905B) { 2805 CSR_WRITE_2(sc, XL_COMMAND, 2806 XL_CMD_SET_TX_RECLAIM|(XL_PACKET_SIZE >> 4)); 2807 } 2808 2809 /* Set RX filter bits. */ 2810 XL_SEL_WIN(5); 2811 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER); 2812 2813 /* Set the individual bit to receive frames for this host only. */ 2814 rxfilt |= XL_RXFILTER_INDIVIDUAL; 2815 2816 /* If we want promiscuous mode, set the allframes bit. */ 2817 if (ifp->if_flags & IFF_PROMISC) { 2818 rxfilt |= XL_RXFILTER_ALLFRAMES; 2819 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 2820 } else { 2821 rxfilt &= ~XL_RXFILTER_ALLFRAMES; 2822 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 2823 } 2824 2825 /* 2826 * Set capture broadcast bit to capture broadcast frames. 2827 */ 2828 if (ifp->if_flags & IFF_BROADCAST) { 2829 rxfilt |= XL_RXFILTER_BROADCAST; 2830 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 2831 } else { 2832 rxfilt &= ~XL_RXFILTER_BROADCAST; 2833 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 2834 } 2835 2836 /* 2837 * Program the multicast filter, if necessary. 2838 */ 2839 if (sc->xl_type == XL_TYPE_905B) 2840 xl_setmulti_hash(sc); 2841 else 2842 xl_setmulti(sc); 2843 2844 if (sc->xl_type == XL_TYPE_905B) { 2845 /* Set UP polling interval */ 2846 CSR_WRITE_1(sc, XL_UP_POLL, 64); 2847 } 2848 2849 /* 2850 * Load the address of the RX list. We have to 2851 * stall the upload engine before we can manipulate 2852 * the uplist pointer register, then unstall it when 2853 * we're finished. We also have to wait for the 2854 * stall command to complete before proceeding. 2855 * Note that we have to do this after any RX resets 2856 * have completed since the uplist register is cleared 2857 * by a reset. 2858 */ 2859 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_STALL); 2860 xl_wait(sc); 2861 CSR_WRITE_4(sc, XL_UPLIST_PTR, sc->xl_ldata.xl_rx_dmaaddr); 2862 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_UNSTALL); 2863 xl_wait(sc); 2864 2865 if (sc->xl_type == XL_TYPE_905B) { 2866 /* Set DN polling interval */ 2867 CSR_WRITE_1(sc, XL_DOWN_POLL, 64); 2868 2869 /* Load the address of the TX list */ 2870 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_STALL); 2871 xl_wait(sc); 2872 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, 2873 sc->xl_cdata.xl_tx_chain[0].xl_phys); 2874 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); 2875 xl_wait(sc); 2876 } 2877 2878 /* 2879 * If the coax transceiver is on, make sure to enable 2880 * the DC-DC converter. 2881 */ 2882 XL_SEL_WIN(3); 2883 if (sc->xl_xcvr == XL_XCVR_COAX) 2884 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_START); 2885 else 2886 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP); 2887 2888 /* 2889 * increase packet size to allow reception of 802.1q or ISL packets. 2890 * For the 3c90x chip, set the 'allow large packets' bit in the MAC 2891 * control register. For 3c90xB/C chips, use the RX packet size 2892 * register. 2893 */ 2894 2895 if (sc->xl_type == XL_TYPE_905B) { 2896 CSR_WRITE_2(sc, XL_W3_MAXPKTSIZE, XL_PACKET_SIZE); 2897 } else { 2898 u_int8_t macctl; 2899 macctl = CSR_READ_1(sc, XL_W3_MAC_CTRL); 2900 macctl |= XL_MACCTRL_ALLOW_LARGE_PACK; 2901 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, macctl); 2902 } 2903 2904 /* Clear out the stats counters. */ 2905 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_DISABLE); 2906 sc->xl_stats_no_timeout = 1; 2907 xl_stats_update_serialized(sc); 2908 sc->xl_stats_no_timeout = 0; 2909 XL_SEL_WIN(4); 2910 CSR_WRITE_2(sc, XL_W4_NET_DIAG, XL_NETDIAG_UPPER_BYTES_ENABLE); 2911 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_ENABLE); 2912 2913 /* 2914 * Enable interrupts. 2915 */ 2916 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STAT_ENB | XL_INTRS); 2917 #ifdef IFPOLL_ENABLE 2918 /* Do not enable interrupt if polling(4) is enabled */ 2919 if (ifp->if_flags & IFF_NPOLLING) 2920 xl_enable_intrs(sc, 0); 2921 else 2922 #endif 2923 xl_enable_intrs(sc, XL_INTRS); 2924 2925 /* Set the RX early threshold */ 2926 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_THRESH|(XL_PACKET_SIZE >>2)); 2927 CSR_WRITE_2(sc, XL_DMACTL, XL_DMACTL_UP_RX_EARLY); 2928 2929 /* Enable receiver and transmitter. */ 2930 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE); 2931 xl_wait(sc); 2932 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_ENABLE); 2933 xl_wait(sc); 2934 2935 if (mii != NULL) 2936 mii_mediachg(mii); 2937 2938 /* Select window 7 for normal operations. */ 2939 XL_SEL_WIN(7); 2940 2941 ifp->if_flags |= IFF_RUNNING; 2942 ifp->if_flags &= ~IFF_OACTIVE; 2943 2944 callout_reset(&sc->xl_stat_timer, hz, xl_stats_update, sc); 2945 } 2946 2947 /* 2948 * Set media options. 2949 */ 2950 static int 2951 xl_ifmedia_upd(struct ifnet *ifp) 2952 { 2953 struct xl_softc *sc; 2954 struct ifmedia *ifm = NULL; 2955 struct mii_data *mii = NULL; 2956 2957 ASSERT_SERIALIZED(ifp->if_serializer); 2958 2959 sc = ifp->if_softc; 2960 if (sc->xl_miibus != NULL) 2961 mii = device_get_softc(sc->xl_miibus); 2962 if (mii == NULL) 2963 ifm = &sc->ifmedia; 2964 else 2965 ifm = &mii->mii_media; 2966 2967 switch(IFM_SUBTYPE(ifm->ifm_media)) { 2968 case IFM_100_FX: 2969 case IFM_10_FL: 2970 case IFM_10_2: 2971 case IFM_10_5: 2972 xl_setmode(sc, ifm->ifm_media); 2973 return(0); 2974 break; 2975 default: 2976 break; 2977 } 2978 2979 if (sc->xl_media & XL_MEDIAOPT_MII || sc->xl_media & XL_MEDIAOPT_BTX 2980 || sc->xl_media & XL_MEDIAOPT_BT4) { 2981 xl_init(sc); 2982 } else { 2983 xl_setmode(sc, ifm->ifm_media); 2984 } 2985 2986 return(0); 2987 } 2988 2989 /* 2990 * Report current media status. 2991 */ 2992 static void 2993 xl_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 2994 { 2995 struct xl_softc *sc; 2996 u_int32_t icfg; 2997 struct mii_data *mii = NULL; 2998 2999 ASSERT_SERIALIZED(ifp->if_serializer); 3000 3001 sc = ifp->if_softc; 3002 if (sc->xl_miibus != NULL) 3003 mii = device_get_softc(sc->xl_miibus); 3004 3005 XL_SEL_WIN(3); 3006 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG) & XL_ICFG_CONNECTOR_MASK; 3007 icfg >>= XL_ICFG_CONNECTOR_BITS; 3008 3009 ifmr->ifm_active = IFM_ETHER; 3010 3011 switch(icfg) { 3012 case XL_XCVR_10BT: 3013 ifmr->ifm_active = IFM_ETHER|IFM_10_T; 3014 if (CSR_READ_1(sc, XL_W3_MAC_CTRL) & XL_MACCTRL_DUPLEX) 3015 ifmr->ifm_active |= IFM_FDX; 3016 else 3017 ifmr->ifm_active |= IFM_HDX; 3018 break; 3019 case XL_XCVR_AUI: 3020 if (sc->xl_type == XL_TYPE_905B && 3021 sc->xl_media == XL_MEDIAOPT_10FL) { 3022 ifmr->ifm_active = IFM_ETHER|IFM_10_FL; 3023 if (CSR_READ_1(sc, XL_W3_MAC_CTRL) & XL_MACCTRL_DUPLEX) 3024 ifmr->ifm_active |= IFM_FDX; 3025 else 3026 ifmr->ifm_active |= IFM_HDX; 3027 } else 3028 ifmr->ifm_active = IFM_ETHER|IFM_10_5; 3029 break; 3030 case XL_XCVR_COAX: 3031 ifmr->ifm_active = IFM_ETHER|IFM_10_2; 3032 break; 3033 /* 3034 * XXX MII and BTX/AUTO should be separate cases. 3035 */ 3036 3037 case XL_XCVR_100BTX: 3038 case XL_XCVR_AUTO: 3039 case XL_XCVR_MII: 3040 if (mii != NULL) { 3041 mii_pollstat(mii); 3042 ifmr->ifm_active = mii->mii_media_active; 3043 ifmr->ifm_status = mii->mii_media_status; 3044 } 3045 break; 3046 case XL_XCVR_100BFX: 3047 ifmr->ifm_active = IFM_ETHER|IFM_100_FX; 3048 break; 3049 default: 3050 if_printf(ifp, "unknown XCVR type: %d\n", icfg); 3051 break; 3052 } 3053 3054 return; 3055 } 3056 3057 static int 3058 xl_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr) 3059 { 3060 struct xl_softc *sc = ifp->if_softc; 3061 struct ifreq *ifr = (struct ifreq *) data; 3062 int error = 0; 3063 struct mii_data *mii = NULL; 3064 u_int8_t rxfilt; 3065 3066 ASSERT_SERIALIZED(ifp->if_serializer); 3067 3068 switch(command) { 3069 case SIOCSIFFLAGS: 3070 XL_SEL_WIN(5); 3071 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER); 3072 if (ifp->if_flags & IFF_UP) { 3073 if (ifp->if_flags & IFF_RUNNING && 3074 ifp->if_flags & IFF_PROMISC && 3075 !(sc->xl_if_flags & IFF_PROMISC)) { 3076 rxfilt |= XL_RXFILTER_ALLFRAMES; 3077 CSR_WRITE_2(sc, XL_COMMAND, 3078 XL_CMD_RX_SET_FILT|rxfilt); 3079 XL_SEL_WIN(7); 3080 } else if (ifp->if_flags & IFF_RUNNING && 3081 !(ifp->if_flags & IFF_PROMISC) && 3082 sc->xl_if_flags & IFF_PROMISC) { 3083 rxfilt &= ~XL_RXFILTER_ALLFRAMES; 3084 CSR_WRITE_2(sc, XL_COMMAND, 3085 XL_CMD_RX_SET_FILT|rxfilt); 3086 XL_SEL_WIN(7); 3087 } else 3088 xl_init(sc); 3089 } else { 3090 if (ifp->if_flags & IFF_RUNNING) 3091 xl_stop(sc); 3092 } 3093 sc->xl_if_flags = ifp->if_flags; 3094 error = 0; 3095 break; 3096 case SIOCADDMULTI: 3097 case SIOCDELMULTI: 3098 if (sc->xl_type == XL_TYPE_905B) 3099 xl_setmulti_hash(sc); 3100 else 3101 xl_setmulti(sc); 3102 error = 0; 3103 break; 3104 case SIOCGIFMEDIA: 3105 case SIOCSIFMEDIA: 3106 if (sc->xl_miibus != NULL) 3107 mii = device_get_softc(sc->xl_miibus); 3108 if (mii == NULL) 3109 error = ifmedia_ioctl(ifp, ifr, 3110 &sc->ifmedia, command); 3111 else 3112 error = ifmedia_ioctl(ifp, ifr, 3113 &mii->mii_media, command); 3114 break; 3115 case SIOCSIFCAP: 3116 ifp->if_capenable &= ~IFCAP_HWCSUM; 3117 ifp->if_capenable |= (ifr->ifr_reqcap & IFCAP_HWCSUM); 3118 if (ifp->if_capenable & IFCAP_HWCSUM) 3119 ifp->if_hwassist = XL905B_CSUM_FEATURES; 3120 else 3121 ifp->if_hwassist = 0; 3122 break; 3123 default: 3124 error = ether_ioctl(ifp, command, data); 3125 break; 3126 } 3127 return(error); 3128 } 3129 3130 static void 3131 xl_watchdog(struct ifnet *ifp) 3132 { 3133 struct xl_softc *sc; 3134 u_int16_t status = 0; 3135 3136 ASSERT_SERIALIZED(ifp->if_serializer); 3137 3138 sc = ifp->if_softc; 3139 3140 ifp->if_oerrors++; 3141 XL_SEL_WIN(4); 3142 status = CSR_READ_2(sc, XL_W4_MEDIA_STATUS); 3143 if_printf(ifp, "watchdog timeout\n"); 3144 3145 if (status & XL_MEDIASTAT_CARRIER) 3146 if_printf(ifp, "no carrier - transceiver cable problem?\n"); 3147 xl_txeoc(sc); 3148 xl_txeof(sc); 3149 xl_rxeof(sc, -1); 3150 xl_reset(sc); 3151 xl_init(sc); 3152 3153 if (!ifq_is_empty(&ifp->if_snd)) 3154 if_devstart(ifp); 3155 } 3156 3157 /* 3158 * Stop the adapter and free any mbufs allocated to the 3159 * RX and TX lists. 3160 */ 3161 static void 3162 xl_stop(struct xl_softc *sc) 3163 { 3164 int i; 3165 struct ifnet *ifp; 3166 3167 ifp = &sc->arpcom.ac_if; 3168 ASSERT_SERIALIZED(ifp->if_serializer); 3169 3170 ifp->if_timer = 0; 3171 3172 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_DISABLE); 3173 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_DISABLE); 3174 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB); 3175 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_DISCARD); 3176 xl_wait(sc); 3177 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_DISABLE); 3178 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP); 3179 DELAY(800); 3180 3181 #ifdef foo 3182 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET); 3183 xl_wait(sc); 3184 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); 3185 xl_wait(sc); 3186 #endif 3187 3188 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ACK|XL_STAT_INTLATCH); 3189 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STAT_ENB|0); 3190 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|0); 3191 if (sc->xl_flags & XL_FLAG_FUNCREG) 3192 bus_space_write_4(sc->xl_ftag, sc->xl_fhandle, 4, 0x8000); 3193 3194 /* Stop the stats updater. */ 3195 callout_stop(&sc->xl_stat_timer); 3196 3197 /* 3198 * Free data in the RX lists. 3199 */ 3200 for (i = 0; i < XL_RX_LIST_CNT; i++) { 3201 if (sc->xl_cdata.xl_rx_chain[i].xl_mbuf != NULL) { 3202 bus_dmamap_unload(sc->xl_rx_mtag, 3203 sc->xl_cdata.xl_rx_chain[i].xl_map); 3204 m_freem(sc->xl_cdata.xl_rx_chain[i].xl_mbuf); 3205 sc->xl_cdata.xl_rx_chain[i].xl_mbuf = NULL; 3206 } 3207 } 3208 bzero(sc->xl_ldata.xl_rx_list, XL_RX_LIST_SZ); 3209 3210 /* 3211 * Free the TX list buffers. 3212 */ 3213 for (i = 0; i < XL_TX_LIST_CNT; i++) { 3214 if (sc->xl_cdata.xl_tx_chain[i].xl_mbuf != NULL) { 3215 bus_dmamap_unload(sc->xl_tx_mtag, 3216 sc->xl_cdata.xl_tx_chain[i].xl_map); 3217 m_freem(sc->xl_cdata.xl_tx_chain[i].xl_mbuf); 3218 sc->xl_cdata.xl_tx_chain[i].xl_mbuf = NULL; 3219 } 3220 } 3221 bzero(sc->xl_ldata.xl_tx_list, XL_TX_LIST_SZ); 3222 3223 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 3224 } 3225 3226 /* 3227 * Stop all chip I/O so that the kernel's probe routines don't 3228 * get confused by errant DMAs when rebooting. 3229 */ 3230 static void 3231 xl_shutdown(device_t dev) 3232 { 3233 struct xl_softc *sc = device_get_softc(dev); 3234 3235 lwkt_serialize_enter(sc->arpcom.ac_if.if_serializer); 3236 xl_reset(sc); 3237 xl_stop(sc); 3238 lwkt_serialize_exit(sc->arpcom.ac_if.if_serializer); 3239 } 3240 3241 static int 3242 xl_suspend(device_t dev) 3243 { 3244 struct xl_softc *sc = device_get_softc(dev); 3245 3246 lwkt_serialize_enter(sc->arpcom.ac_if.if_serializer); 3247 xl_stop(sc); 3248 lwkt_serialize_exit(sc->arpcom.ac_if.if_serializer); 3249 3250 return(0); 3251 } 3252 3253 static int 3254 xl_resume(device_t dev) 3255 { 3256 struct xl_softc *sc; 3257 struct ifnet *ifp; 3258 3259 sc = device_get_softc(dev); 3260 ifp = &sc->arpcom.ac_if; 3261 3262 lwkt_serialize_enter(ifp->if_serializer); 3263 xl_reset(sc); 3264 if (ifp->if_flags & IFF_UP) 3265 xl_init(sc); 3266 lwkt_serialize_exit(ifp->if_serializer); 3267 3268 return(0); 3269 } 3270