1 /* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: src/sys/pci/if_xl.c,v 1.72.2.28 2003/10/08 06:01:57 murray Exp $ 33 * $DragonFly: src/sys/dev/netif/xl/if_xl.c,v 1.45 2006/08/01 18:13:21 swildner Exp $ 34 */ 35 36 /* 37 * 3Com 3c90x Etherlink XL PCI NIC driver 38 * 39 * Supports the 3Com "boomerang", "cyclone" and "hurricane" PCI 40 * bus-master chips (3c90x cards and embedded controllers) including 41 * the following: 42 * 43 * 3Com 3c900-TPO 10Mbps/RJ-45 44 * 3Com 3c900-COMBO 10Mbps/RJ-45,AUI,BNC 45 * 3Com 3c905-TX 10/100Mbps/RJ-45 46 * 3Com 3c905-T4 10/100Mbps/RJ-45 47 * 3Com 3c900B-TPO 10Mbps/RJ-45 48 * 3Com 3c900B-COMBO 10Mbps/RJ-45,AUI,BNC 49 * 3Com 3c900B-TPC 10Mbps/RJ-45,BNC 50 * 3Com 3c900B-FL 10Mbps/Fiber-optic 51 * 3Com 3c905B-COMBO 10/100Mbps/RJ-45,AUI,BNC 52 * 3Com 3c905B-TX 10/100Mbps/RJ-45 53 * 3Com 3c905B-FL/FX 10/100Mbps/Fiber-optic 54 * 3Com 3c905C-TX 10/100Mbps/RJ-45 (Tornado ASIC) 55 * 3Com 3c980-TX 10/100Mbps server adapter (Hurricane ASIC) 56 * 3Com 3c980C-TX 10/100Mbps server adapter (Tornado ASIC) 57 * 3Com 3cSOHO100-TX 10/100Mbps/RJ-45 (Hurricane ASIC) 58 * 3Com 3c450-TX 10/100Mbps/RJ-45 (Tornado ASIC) 59 * 3Com 3c555 10/100Mbps/RJ-45 (MiniPCI, Laptop Hurricane) 60 * 3Com 3c556 10/100Mbps/RJ-45 (MiniPCI, Hurricane ASIC) 61 * 3Com 3c556B 10/100Mbps/RJ-45 (MiniPCI, Hurricane ASIC) 62 * 3Com 3c575TX 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC) 63 * 3Com 3c575B 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC) 64 * 3Com 3c575C 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC) 65 * 3Com 3cxfem656 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC) 66 * 3Com 3cxfem656b 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC) 67 * 3Com 3cxfem656c 10/100Mbps/RJ-45 (Cardbus, Tornado ASIC) 68 * Dell Optiplex GX1 on-board 3c918 10/100Mbps/RJ-45 69 * Dell on-board 3c920 10/100Mbps/RJ-45 70 * Dell Precision on-board 3c905B 10/100Mbps/RJ-45 71 * Dell Latitude laptop docking station embedded 3c905-TX 72 * 73 * Written by Bill Paul <wpaul@ctr.columbia.edu> 74 * Electrical Engineering Department 75 * Columbia University, New York City 76 */ 77 78 /* 79 * The 3c90x series chips use a bus-master DMA interface for transfering 80 * packets to and from the controller chip. Some of the "vortex" cards 81 * (3c59x) also supported a bus master mode, however for those chips 82 * you could only DMA packets to/from a contiguous memory buffer. For 83 * transmission this would mean copying the contents of the queued mbuf 84 * chain into an mbuf cluster and then DMAing the cluster. This extra 85 * copy would sort of defeat the purpose of the bus master support for 86 * any packet that doesn't fit into a single mbuf. 87 * 88 * By contrast, the 3c90x cards support a fragment-based bus master 89 * mode where mbuf chains can be encapsulated using TX descriptors. 90 * This is similar to other PCI chips such as the Texas Instruments 91 * ThunderLAN and the Intel 82557/82558. 92 * 93 * The "vortex" driver (if_vx.c) happens to work for the "boomerang" 94 * bus master chips because they maintain the old PIO interface for 95 * backwards compatibility, but starting with the 3c905B and the 96 * "cyclone" chips, the compatibility interface has been dropped. 97 * Since using bus master DMA is a big win, we use this driver to 98 * support the PCI "boomerang" chips even though they work with the 99 * "vortex" driver in order to obtain better performance. 100 */ 101 102 #include "opt_polling.h" 103 104 #include <sys/param.h> 105 #include <sys/systm.h> 106 #include <sys/sockio.h> 107 #include <sys/endian.h> 108 #include <sys/mbuf.h> 109 #include <sys/kernel.h> 110 #include <sys/socket.h> 111 #include <sys/serialize.h> 112 #include <sys/thread2.h> 113 114 #include <net/if.h> 115 #include <net/ifq_var.h> 116 #include <net/if_arp.h> 117 #include <net/ethernet.h> 118 #include <net/if_dl.h> 119 #include <net/if_media.h> 120 #include <net/vlan/if_vlan_var.h> 121 122 #include <net/bpf.h> 123 124 #include <machine/bus_memio.h> 125 #include <machine/bus_pio.h> 126 #include <machine/bus.h> 127 #include <machine/resource.h> 128 #include <sys/bus.h> 129 #include <sys/rman.h> 130 131 #include "../mii_layer/mii.h" 132 #include "../mii_layer/miivar.h" 133 134 #include <bus/pci/pcireg.h> 135 #include <bus/pci/pcivar.h> 136 137 /* "controller miibus0" required. See GENERIC if you get errors here. */ 138 #include "miibus_if.h" 139 140 #include "if_xlreg.h" 141 142 #define XL905B_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 143 144 /* 145 * Various supported device vendors/types and their names. 146 */ 147 static struct xl_type xl_devs[] = { 148 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10BT, 149 "3Com 3c900-TPO Etherlink XL" }, 150 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10BT_COMBO, 151 "3Com 3c900-COMBO Etherlink XL" }, 152 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10_100BT, 153 "3Com 3c905-TX Fast Etherlink XL" }, 154 { TC_VENDORID, TC_DEVICEID_BOOMERANG_100BT4, 155 "3Com 3c905-T4 Fast Etherlink XL" }, 156 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT, 157 "3Com 3c900B-TPO Etherlink XL" }, 158 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT_COMBO, 159 "3Com 3c900B-COMBO Etherlink XL" }, 160 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT_TPC, 161 "3Com 3c900B-TPC Etherlink XL" }, 162 { TC_VENDORID, TC_DEVICEID_CYCLONE_10FL, 163 "3Com 3c900B-FL Etherlink XL" }, 164 { TC_VENDORID, TC_DEVICEID_HURRICANE_10_100BT, 165 "3Com 3c905B-TX Fast Etherlink XL" }, 166 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100BT4, 167 "3Com 3c905B-T4 Fast Etherlink XL" }, 168 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100FX, 169 "3Com 3c905B-FX/SC Fast Etherlink XL" }, 170 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100_COMBO, 171 "3Com 3c905B-COMBO Fast Etherlink XL" }, 172 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT, 173 "3Com 3c905C-TX Fast Etherlink XL" }, 174 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT_920B, 175 "3Com 3c920B-EMB Integrated Fast Etherlink XL" }, 176 { TC_VENDORID, TC_DEVICEID_HURRICANE_10_100BT_SERV, 177 "3Com 3c980 Fast Etherlink XL" }, 178 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT_SERV, 179 "3Com 3c980C Fast Etherlink XL" }, 180 { TC_VENDORID, TC_DEVICEID_HURRICANE_SOHO100TX, 181 "3Com 3cSOHO100-TX OfficeConnect" }, 182 { TC_VENDORID, TC_DEVICEID_TORNADO_HOMECONNECT, 183 "3Com 3c450-TX HomeConnect" }, 184 { TC_VENDORID, TC_DEVICEID_HURRICANE_555, 185 "3Com 3c555 Fast Etherlink XL" }, 186 { TC_VENDORID, TC_DEVICEID_HURRICANE_556, 187 "3Com 3c556 Fast Etherlink XL" }, 188 { TC_VENDORID, TC_DEVICEID_HURRICANE_556B, 189 "3Com 3c556B Fast Etherlink XL" }, 190 { TC_VENDORID, TC_DEVICEID_HURRICANE_575A, 191 "3Com 3c575TX Fast Etherlink XL" }, 192 { TC_VENDORID, TC_DEVICEID_HURRICANE_575B, 193 "3Com 3c575B Fast Etherlink XL" }, 194 { TC_VENDORID, TC_DEVICEID_HURRICANE_575C, 195 "3Com 3c575C Fast Etherlink XL" }, 196 { TC_VENDORID, TC_DEVICEID_HURRICANE_656, 197 "3Com 3c656 Fast Etherlink XL" }, 198 { TC_VENDORID, TC_DEVICEID_HURRICANE_656B, 199 "3Com 3c656B Fast Etherlink XL" }, 200 { TC_VENDORID, TC_DEVICEID_TORNADO_656C, 201 "3Com 3c656C Fast Etherlink XL" }, 202 { 0, 0, NULL } 203 }; 204 205 static int xl_probe (device_t); 206 static int xl_attach (device_t); 207 static int xl_detach (device_t); 208 209 static int xl_newbuf (struct xl_softc *, struct xl_chain_onefrag *); 210 static void xl_stats_update (void *); 211 static void xl_stats_update_serialized(void *); 212 static int xl_encap (struct xl_softc *, struct xl_chain *, 213 struct mbuf *); 214 static void xl_rxeof (struct xl_softc *, int); 215 static int xl_rx_resync (struct xl_softc *); 216 static void xl_txeof (struct xl_softc *); 217 static void xl_txeof_90xB (struct xl_softc *); 218 static void xl_txeoc (struct xl_softc *); 219 static void xl_intr (void *); 220 static void xl_start_body (struct ifnet *, int); 221 static void xl_start (struct ifnet *); 222 static void xl_start_90xB (struct ifnet *); 223 static int xl_ioctl (struct ifnet *, u_long, caddr_t, 224 struct ucred *); 225 static void xl_init (void *); 226 static void xl_stop (struct xl_softc *); 227 static void xl_watchdog (struct ifnet *); 228 static void xl_shutdown (device_t); 229 static int xl_suspend (device_t); 230 static int xl_resume (device_t); 231 #ifdef DEVICE_POLLING 232 static void xl_poll (struct ifnet *, enum poll_cmd, int); 233 #endif 234 static void xl_enable_intrs (struct xl_softc *, uint16_t); 235 236 static int xl_ifmedia_upd (struct ifnet *); 237 static void xl_ifmedia_sts (struct ifnet *, struct ifmediareq *); 238 239 static int xl_eeprom_wait (struct xl_softc *); 240 static int xl_read_eeprom (struct xl_softc *, caddr_t, int, int, int); 241 static void xl_mii_sync (struct xl_softc *); 242 static void xl_mii_send (struct xl_softc *, u_int32_t, int); 243 static int xl_mii_readreg (struct xl_softc *, struct xl_mii_frame *); 244 static int xl_mii_writereg (struct xl_softc *, struct xl_mii_frame *); 245 246 static void xl_setcfg (struct xl_softc *); 247 static void xl_setmode (struct xl_softc *, int); 248 static void xl_setmulti (struct xl_softc *); 249 static void xl_setmulti_hash (struct xl_softc *); 250 static void xl_reset (struct xl_softc *); 251 static int xl_list_rx_init (struct xl_softc *); 252 static void xl_list_tx_init (struct xl_softc *); 253 static void xl_list_tx_init_90xB(struct xl_softc *); 254 static void xl_wait (struct xl_softc *); 255 static void xl_mediacheck (struct xl_softc *); 256 static void xl_choose_xcvr (struct xl_softc *, int); 257 static void xl_dma_map_addr (void *, bus_dma_segment_t *, int, int); 258 static void xl_dma_map_rxbuf (void *, bus_dma_segment_t *, int, bus_size_t, 259 int); 260 static void xl_dma_map_txbuf (void *, bus_dma_segment_t *, int, bus_size_t, 261 int); 262 263 static int xl_dma_alloc (device_t); 264 static void xl_dma_free (device_t); 265 266 #ifdef notdef 267 static void xl_testpacket (struct xl_softc *); 268 #endif 269 270 static int xl_miibus_readreg (device_t, int, int); 271 static int xl_miibus_writereg (device_t, int, int, int); 272 static void xl_miibus_statchg (device_t); 273 static void xl_miibus_mediainit (device_t); 274 275 static device_method_t xl_methods[] = { 276 /* Device interface */ 277 DEVMETHOD(device_probe, xl_probe), 278 DEVMETHOD(device_attach, xl_attach), 279 DEVMETHOD(device_detach, xl_detach), 280 DEVMETHOD(device_shutdown, xl_shutdown), 281 DEVMETHOD(device_suspend, xl_suspend), 282 DEVMETHOD(device_resume, xl_resume), 283 284 /* bus interface */ 285 DEVMETHOD(bus_print_child, bus_generic_print_child), 286 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 287 288 /* MII interface */ 289 DEVMETHOD(miibus_readreg, xl_miibus_readreg), 290 DEVMETHOD(miibus_writereg, xl_miibus_writereg), 291 DEVMETHOD(miibus_statchg, xl_miibus_statchg), 292 DEVMETHOD(miibus_mediainit, xl_miibus_mediainit), 293 294 { 0, 0 } 295 }; 296 297 static driver_t xl_driver = { 298 "xl", 299 xl_methods, 300 sizeof(struct xl_softc) 301 }; 302 303 static devclass_t xl_devclass; 304 305 DECLARE_DUMMY_MODULE(if_xl); 306 MODULE_DEPEND(if_xl, miibus, 1, 1, 1); 307 DRIVER_MODULE(if_xl, pci, xl_driver, xl_devclass, 0, 0); 308 DRIVER_MODULE(if_xl, cardbus, xl_driver, xl_devclass, 0, 0); 309 DRIVER_MODULE(miibus, xl, miibus_driver, miibus_devclass, 0, 0); 310 311 static void 312 xl_enable_intrs(struct xl_softc *sc, uint16_t intrs) 313 { 314 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ACK | 0xFF); 315 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB | intrs); 316 if (sc->xl_flags & XL_FLAG_FUNCREG) 317 bus_space_write_4(sc->xl_ftag, sc->xl_fhandle, 4, 0x8000); 318 } 319 320 static void 321 xl_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 322 { 323 u_int32_t *paddr; 324 325 paddr = arg; 326 *paddr = segs->ds_addr; 327 } 328 329 static void 330 xl_dma_map_rxbuf(void *arg, bus_dma_segment_t *segs, int nseg, 331 bus_size_t mapsize, int error) 332 { 333 u_int32_t *paddr; 334 335 if (error) 336 return; 337 KASSERT(nseg == 1, ("xl_dma_map_rxbuf: too many DMA segments")); 338 paddr = arg; 339 *paddr = segs->ds_addr; 340 } 341 342 static void 343 xl_dma_map_txbuf(void *arg, bus_dma_segment_t *segs, int nseg, 344 bus_size_t mapsize, int error) 345 { 346 struct xl_list *l; 347 int i, total_len; 348 349 if (error) 350 return; 351 352 KASSERT(nseg <= XL_MAXFRAGS, ("too many DMA segments")); 353 354 total_len = 0; 355 l = arg; 356 for (i = 0; i < nseg; i++) { 357 KASSERT(segs[i].ds_len <= MCLBYTES, ("segment size too large")); 358 l->xl_frag[i].xl_addr = htole32(segs[i].ds_addr); 359 l->xl_frag[i].xl_len = htole32(segs[i].ds_len); 360 total_len += segs[i].ds_len; 361 } 362 l->xl_frag[nseg - 1].xl_len = htole32(segs[nseg - 1].ds_len | 363 XL_LAST_FRAG); 364 l->xl_status = htole32(total_len); 365 l->xl_next = 0; 366 } 367 368 /* 369 * Murphy's law says that it's possible the chip can wedge and 370 * the 'command in progress' bit may never clear. Hence, we wait 371 * only a finite amount of time to avoid getting caught in an 372 * infinite loop. Normally this delay routine would be a macro, 373 * but it isn't called during normal operation so we can afford 374 * to make it a function. 375 */ 376 static void 377 xl_wait(struct xl_softc *sc) 378 { 379 int i; 380 381 for (i = 0; i < XL_TIMEOUT; i++) { 382 if (!(CSR_READ_2(sc, XL_STATUS) & XL_STAT_CMDBUSY)) 383 break; 384 } 385 386 if (i == XL_TIMEOUT) 387 if_printf(&sc->arpcom.ac_if, "command never completed!"); 388 389 return; 390 } 391 392 /* 393 * MII access routines are provided for adapters with external 394 * PHYs (3c905-TX, 3c905-T4, 3c905B-T4) and those with built-in 395 * autoneg logic that's faked up to look like a PHY (3c905B-TX). 396 * Note: if you don't perform the MDIO operations just right, 397 * it's possible to end up with code that works correctly with 398 * some chips/CPUs/processor speeds/bus speeds/etc but not 399 * with others. 400 */ 401 #define MII_SET(x) \ 402 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, \ 403 CSR_READ_2(sc, XL_W4_PHY_MGMT) | (x)) 404 405 #define MII_CLR(x) \ 406 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, \ 407 CSR_READ_2(sc, XL_W4_PHY_MGMT) & ~(x)) 408 409 /* 410 * Sync the PHYs by setting data bit and strobing the clock 32 times. 411 */ 412 static void 413 xl_mii_sync(struct xl_softc *sc) 414 { 415 int i; 416 417 XL_SEL_WIN(4); 418 MII_SET(XL_MII_DIR|XL_MII_DATA); 419 420 for (i = 0; i < 32; i++) { 421 MII_SET(XL_MII_CLK); 422 MII_SET(XL_MII_DATA); 423 MII_SET(XL_MII_DATA); 424 MII_CLR(XL_MII_CLK); 425 MII_SET(XL_MII_DATA); 426 MII_SET(XL_MII_DATA); 427 } 428 429 return; 430 } 431 432 /* 433 * Clock a series of bits through the MII. 434 */ 435 static void 436 xl_mii_send(struct xl_softc *sc, u_int32_t bits, int cnt) 437 { 438 int i; 439 440 XL_SEL_WIN(4); 441 MII_CLR(XL_MII_CLK); 442 443 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 444 if (bits & i) { 445 MII_SET(XL_MII_DATA); 446 } else { 447 MII_CLR(XL_MII_DATA); 448 } 449 MII_CLR(XL_MII_CLK); 450 MII_SET(XL_MII_CLK); 451 } 452 } 453 454 /* 455 * Read an PHY register through the MII. 456 */ 457 static int 458 xl_mii_readreg(struct xl_softc *sc, struct xl_mii_frame *frame) 459 { 460 int i, ack; 461 462 /* 463 * Set up frame for RX. 464 */ 465 frame->mii_stdelim = XL_MII_STARTDELIM; 466 frame->mii_opcode = XL_MII_READOP; 467 frame->mii_turnaround = 0; 468 frame->mii_data = 0; 469 470 /* 471 * Select register window 4. 472 */ 473 474 XL_SEL_WIN(4); 475 476 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, 0); 477 /* 478 * Turn on data xmit. 479 */ 480 MII_SET(XL_MII_DIR); 481 482 xl_mii_sync(sc); 483 484 /* 485 * Send command/address info. 486 */ 487 xl_mii_send(sc, frame->mii_stdelim, 2); 488 xl_mii_send(sc, frame->mii_opcode, 2); 489 xl_mii_send(sc, frame->mii_phyaddr, 5); 490 xl_mii_send(sc, frame->mii_regaddr, 5); 491 492 /* Idle bit */ 493 MII_CLR((XL_MII_CLK|XL_MII_DATA)); 494 MII_SET(XL_MII_CLK); 495 496 /* Turn off xmit. */ 497 MII_CLR(XL_MII_DIR); 498 499 /* Check for ack */ 500 MII_CLR(XL_MII_CLK); 501 ack = CSR_READ_2(sc, XL_W4_PHY_MGMT) & XL_MII_DATA; 502 MII_SET(XL_MII_CLK); 503 504 /* 505 * Now try reading data bits. If the ack failed, we still 506 * need to clock through 16 cycles to keep the PHY(s) in sync. 507 */ 508 if (ack) { 509 for(i = 0; i < 16; i++) { 510 MII_CLR(XL_MII_CLK); 511 MII_SET(XL_MII_CLK); 512 } 513 goto fail; 514 } 515 516 for (i = 0x8000; i; i >>= 1) { 517 MII_CLR(XL_MII_CLK); 518 if (!ack) { 519 if (CSR_READ_2(sc, XL_W4_PHY_MGMT) & XL_MII_DATA) 520 frame->mii_data |= i; 521 } 522 MII_SET(XL_MII_CLK); 523 } 524 525 fail: 526 527 MII_CLR(XL_MII_CLK); 528 MII_SET(XL_MII_CLK); 529 530 if (ack) 531 return(1); 532 return(0); 533 } 534 535 /* 536 * Write to a PHY register through the MII. 537 */ 538 static int 539 xl_mii_writereg(struct xl_softc *sc, struct xl_mii_frame *frame) 540 { 541 /* 542 * Set up frame for TX. 543 */ 544 545 frame->mii_stdelim = XL_MII_STARTDELIM; 546 frame->mii_opcode = XL_MII_WRITEOP; 547 frame->mii_turnaround = XL_MII_TURNAROUND; 548 549 /* 550 * Select the window 4. 551 */ 552 XL_SEL_WIN(4); 553 554 /* 555 * Turn on data output. 556 */ 557 MII_SET(XL_MII_DIR); 558 559 xl_mii_sync(sc); 560 561 xl_mii_send(sc, frame->mii_stdelim, 2); 562 xl_mii_send(sc, frame->mii_opcode, 2); 563 xl_mii_send(sc, frame->mii_phyaddr, 5); 564 xl_mii_send(sc, frame->mii_regaddr, 5); 565 xl_mii_send(sc, frame->mii_turnaround, 2); 566 xl_mii_send(sc, frame->mii_data, 16); 567 568 /* Idle bit. */ 569 MII_SET(XL_MII_CLK); 570 MII_CLR(XL_MII_CLK); 571 572 /* 573 * Turn off xmit. 574 */ 575 MII_CLR(XL_MII_DIR); 576 577 return(0); 578 } 579 580 static int 581 xl_miibus_readreg(device_t dev, int phy, int reg) 582 { 583 struct xl_softc *sc; 584 struct xl_mii_frame frame; 585 586 sc = device_get_softc(dev); 587 588 /* 589 * Pretend that PHYs are only available at MII address 24. 590 * This is to guard against problems with certain 3Com ASIC 591 * revisions that incorrectly map the internal transceiver 592 * control registers at all MII addresses. This can cause 593 * the miibus code to attach the same PHY several times over. 594 */ 595 if ((!(sc->xl_flags & XL_FLAG_PHYOK)) && phy != 24) 596 return(0); 597 598 bzero((char *)&frame, sizeof(frame)); 599 600 frame.mii_phyaddr = phy; 601 frame.mii_regaddr = reg; 602 xl_mii_readreg(sc, &frame); 603 604 return(frame.mii_data); 605 } 606 607 static int 608 xl_miibus_writereg(device_t dev, int phy, int reg, int data) 609 { 610 struct xl_softc *sc; 611 struct xl_mii_frame frame; 612 613 sc = device_get_softc(dev); 614 615 if ((!(sc->xl_flags & XL_FLAG_PHYOK)) && phy != 24) 616 return(0); 617 618 bzero((char *)&frame, sizeof(frame)); 619 620 frame.mii_phyaddr = phy; 621 frame.mii_regaddr = reg; 622 frame.mii_data = data; 623 624 xl_mii_writereg(sc, &frame); 625 626 return(0); 627 } 628 629 static void 630 xl_miibus_statchg(device_t dev) 631 { 632 struct xl_softc *sc; 633 struct mii_data *mii; 634 635 636 sc = device_get_softc(dev); 637 mii = device_get_softc(sc->xl_miibus); 638 639 xl_setcfg(sc); 640 641 /* Set ASIC's duplex mode to match the PHY. */ 642 XL_SEL_WIN(3); 643 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) 644 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, XL_MACCTRL_DUPLEX); 645 else 646 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, 647 (CSR_READ_1(sc, XL_W3_MAC_CTRL) & ~XL_MACCTRL_DUPLEX)); 648 649 return; 650 } 651 652 /* 653 * Special support for the 3c905B-COMBO. This card has 10/100 support 654 * plus BNC and AUI ports. This means we will have both an miibus attached 655 * plus some non-MII media settings. In order to allow this, we have to 656 * add the extra media to the miibus's ifmedia struct, but we can't do 657 * that during xl_attach() because the miibus hasn't been attached yet. 658 * So instead, we wait until the miibus probe/attach is done, at which 659 * point we will get a callback telling is that it's safe to add our 660 * extra media. 661 */ 662 static void 663 xl_miibus_mediainit(device_t dev) 664 { 665 struct xl_softc *sc; 666 struct mii_data *mii; 667 struct ifmedia *ifm; 668 669 sc = device_get_softc(dev); 670 mii = device_get_softc(sc->xl_miibus); 671 ifm = &mii->mii_media; 672 673 if (sc->xl_media & (XL_MEDIAOPT_AUI|XL_MEDIAOPT_10FL)) { 674 /* 675 * Check for a 10baseFL board in disguise. 676 */ 677 if (sc->xl_type == XL_TYPE_905B && 678 sc->xl_media == XL_MEDIAOPT_10FL) { 679 if (bootverbose) 680 device_printf(dev, "found 10baseFL\n"); 681 ifmedia_add(ifm, IFM_ETHER|IFM_10_FL, 0, NULL); 682 ifmedia_add(ifm, IFM_ETHER|IFM_10_FL|IFM_HDX, 0, NULL); 683 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX) 684 ifmedia_add(ifm, 685 IFM_ETHER|IFM_10_FL|IFM_FDX, 0, NULL); 686 } else { 687 if (bootverbose) 688 device_printf(dev, "found AUI\n"); 689 ifmedia_add(ifm, IFM_ETHER|IFM_10_5, 0, NULL); 690 } 691 } 692 693 if (sc->xl_media & XL_MEDIAOPT_BNC) { 694 if (bootverbose) 695 device_printf(dev, "found BNC\n"); 696 ifmedia_add(ifm, IFM_ETHER|IFM_10_2, 0, NULL); 697 } 698 699 return; 700 } 701 702 /* 703 * The EEPROM is slow: give it time to come ready after issuing 704 * it a command. 705 */ 706 static int 707 xl_eeprom_wait(struct xl_softc *sc) 708 { 709 int i; 710 711 for (i = 0; i < 100; i++) { 712 if (CSR_READ_2(sc, XL_W0_EE_CMD) & XL_EE_BUSY) 713 DELAY(162); 714 else 715 break; 716 } 717 718 if (i == 100) { 719 if_printf(&sc->arpcom.ac_if, "eeprom failed to come ready\n"); 720 return(1); 721 } 722 723 return(0); 724 } 725 726 /* 727 * Read a sequence of words from the EEPROM. Note that ethernet address 728 * data is stored in the EEPROM in network byte order. 729 */ 730 static int 731 xl_read_eeprom(struct xl_softc *sc, caddr_t dest, int off, int cnt, int swap) 732 { 733 int err = 0, i; 734 u_int16_t word = 0, *ptr; 735 #define EEPROM_5BIT_OFFSET(A) ((((A) << 2) & 0x7F00) | ((A) & 0x003F)) 736 #define EEPROM_8BIT_OFFSET(A) ((A) & 0x003F) 737 /* WARNING! DANGER! 738 * It's easy to accidentally overwrite the rom content! 739 * Note: the 3c575 uses 8bit EEPROM offsets. 740 */ 741 XL_SEL_WIN(0); 742 743 if (xl_eeprom_wait(sc)) 744 return(1); 745 746 if (sc->xl_flags & XL_FLAG_EEPROM_OFFSET_30) 747 off += 0x30; 748 749 for (i = 0; i < cnt; i++) { 750 if (sc->xl_flags & XL_FLAG_8BITROM) 751 CSR_WRITE_2(sc, XL_W0_EE_CMD, 752 XL_EE_8BIT_READ | EEPROM_8BIT_OFFSET(off + i)); 753 else 754 CSR_WRITE_2(sc, XL_W0_EE_CMD, 755 XL_EE_READ | EEPROM_5BIT_OFFSET(off + i)); 756 err = xl_eeprom_wait(sc); 757 if (err) 758 break; 759 word = CSR_READ_2(sc, XL_W0_EE_DATA); 760 ptr = (u_int16_t *)(dest + (i * 2)); 761 if (swap) 762 *ptr = ntohs(word); 763 else 764 *ptr = word; 765 } 766 767 return(err ? 1 : 0); 768 } 769 770 /* 771 * NICs older than the 3c905B have only one multicast option, which 772 * is to enable reception of all multicast frames. 773 */ 774 static void 775 xl_setmulti(struct xl_softc *sc) 776 { 777 struct ifnet *ifp; 778 struct ifmultiaddr *ifma; 779 u_int8_t rxfilt; 780 int mcnt = 0; 781 782 ifp = &sc->arpcom.ac_if; 783 784 XL_SEL_WIN(5); 785 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER); 786 787 if (ifp->if_flags & IFF_ALLMULTI) { 788 rxfilt |= XL_RXFILTER_ALLMULTI; 789 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 790 return; 791 } 792 793 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) 794 mcnt++; 795 796 if (mcnt) 797 rxfilt |= XL_RXFILTER_ALLMULTI; 798 else 799 rxfilt &= ~XL_RXFILTER_ALLMULTI; 800 801 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 802 803 return; 804 } 805 806 /* 807 * 3c905B adapters have a hash filter that we can program. 808 */ 809 static void 810 xl_setmulti_hash(struct xl_softc *sc) 811 { 812 struct ifnet *ifp; 813 int h = 0, i; 814 struct ifmultiaddr *ifma; 815 u_int8_t rxfilt; 816 int mcnt = 0; 817 818 ifp = &sc->arpcom.ac_if; 819 820 XL_SEL_WIN(5); 821 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER); 822 823 if (ifp->if_flags & IFF_ALLMULTI) { 824 rxfilt |= XL_RXFILTER_ALLMULTI; 825 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 826 return; 827 } else 828 rxfilt &= ~XL_RXFILTER_ALLMULTI; 829 830 831 /* first, zot all the existing hash bits */ 832 for (i = 0; i < XL_HASHFILT_SIZE; i++) 833 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_HASH|i); 834 835 /* now program new ones */ 836 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 837 if (ifma->ifma_addr->sa_family != AF_LINK) 838 continue; 839 840 /* 841 * Note: the 3c905B currently only supports a 64-bit 842 * hash table, which means we really only need 6 bits, 843 * but the manual indicates that future chip revisions 844 * will have a 256-bit hash table, hence the routine is 845 * set up to calculate 8 bits of position info in case 846 * we need it some day. 847 * Note II, The Sequel: _CURRENT_ versions of the 3c905B 848 * have a 256 bit hash table. This means we have to use 849 * all 8 bits regardless. On older cards, the upper 2 850 * bits will be ignored. Grrrr.... 851 */ 852 h = ether_crc32_be( 853 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 854 ETHER_ADDR_LEN) & 0xff; 855 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_HASH|XL_HASH_SET|h); 856 mcnt++; 857 } 858 859 if (mcnt) 860 rxfilt |= XL_RXFILTER_MULTIHASH; 861 else 862 rxfilt &= ~XL_RXFILTER_MULTIHASH; 863 864 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 865 866 return; 867 } 868 869 #ifdef notdef 870 static void 871 xl_testpacket(struct xl_softc *sc) 872 { 873 struct mbuf *m; 874 struct ifnet *ifp; 875 876 ifp = &sc->arpcom.ac_if; 877 878 MGETHDR(m, MB_DONTWAIT, MT_DATA); 879 880 if (m == NULL) 881 return; 882 883 bcopy(&sc->arpcom.ac_enaddr, 884 mtod(m, struct ether_header *)->ether_dhost, ETHER_ADDR_LEN); 885 bcopy(&sc->arpcom.ac_enaddr, 886 mtod(m, struct ether_header *)->ether_shost, ETHER_ADDR_LEN); 887 mtod(m, struct ether_header *)->ether_type = htons(3); 888 mtod(m, unsigned char *)[14] = 0; 889 mtod(m, unsigned char *)[15] = 0; 890 mtod(m, unsigned char *)[16] = 0xE3; 891 m->m_len = m->m_pkthdr.len = sizeof(struct ether_header) + 3; 892 IF_ENQUEUE(&ifp->if_snd, m); 893 xl_start(ifp); 894 895 return; 896 } 897 #endif 898 899 static void 900 xl_setcfg(struct xl_softc *sc) 901 { 902 u_int32_t icfg; 903 904 XL_SEL_WIN(3); 905 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG); 906 icfg &= ~XL_ICFG_CONNECTOR_MASK; 907 if (sc->xl_media & XL_MEDIAOPT_MII || 908 sc->xl_media & XL_MEDIAOPT_BT4) 909 icfg |= (XL_XCVR_MII << XL_ICFG_CONNECTOR_BITS); 910 if (sc->xl_media & XL_MEDIAOPT_BTX) 911 icfg |= (XL_XCVR_AUTO << XL_ICFG_CONNECTOR_BITS); 912 913 CSR_WRITE_4(sc, XL_W3_INTERNAL_CFG, icfg); 914 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP); 915 916 return; 917 } 918 919 static void 920 xl_setmode(struct xl_softc *sc, int media) 921 { 922 struct ifnet *ifp = &sc->arpcom.ac_if; 923 u_int32_t icfg; 924 u_int16_t mediastat; 925 926 if_printf(ifp, "selecting "); 927 928 XL_SEL_WIN(4); 929 mediastat = CSR_READ_2(sc, XL_W4_MEDIA_STATUS); 930 XL_SEL_WIN(3); 931 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG); 932 933 if (sc->xl_media & XL_MEDIAOPT_BT) { 934 if (IFM_SUBTYPE(media) == IFM_10_T) { 935 printf("10baseT transceiver, "); 936 sc->xl_xcvr = XL_XCVR_10BT; 937 icfg &= ~XL_ICFG_CONNECTOR_MASK; 938 icfg |= (XL_XCVR_10BT << XL_ICFG_CONNECTOR_BITS); 939 mediastat |= XL_MEDIASTAT_LINKBEAT| 940 XL_MEDIASTAT_JABGUARD; 941 mediastat &= ~XL_MEDIASTAT_SQEENB; 942 } 943 } 944 945 if (sc->xl_media & XL_MEDIAOPT_BFX) { 946 if (IFM_SUBTYPE(media) == IFM_100_FX) { 947 printf("100baseFX port, "); 948 sc->xl_xcvr = XL_XCVR_100BFX; 949 icfg &= ~XL_ICFG_CONNECTOR_MASK; 950 icfg |= (XL_XCVR_100BFX << XL_ICFG_CONNECTOR_BITS); 951 mediastat |= XL_MEDIASTAT_LINKBEAT; 952 mediastat &= ~XL_MEDIASTAT_SQEENB; 953 } 954 } 955 956 if (sc->xl_media & (XL_MEDIAOPT_AUI|XL_MEDIAOPT_10FL)) { 957 if (IFM_SUBTYPE(media) == IFM_10_5) { 958 printf("AUI port, "); 959 sc->xl_xcvr = XL_XCVR_AUI; 960 icfg &= ~XL_ICFG_CONNECTOR_MASK; 961 icfg |= (XL_XCVR_AUI << XL_ICFG_CONNECTOR_BITS); 962 mediastat &= ~(XL_MEDIASTAT_LINKBEAT| 963 XL_MEDIASTAT_JABGUARD); 964 mediastat |= ~XL_MEDIASTAT_SQEENB; 965 } 966 if (IFM_SUBTYPE(media) == IFM_10_FL) { 967 printf("10baseFL transceiver, "); 968 sc->xl_xcvr = XL_XCVR_AUI; 969 icfg &= ~XL_ICFG_CONNECTOR_MASK; 970 icfg |= (XL_XCVR_AUI << XL_ICFG_CONNECTOR_BITS); 971 mediastat &= ~(XL_MEDIASTAT_LINKBEAT| 972 XL_MEDIASTAT_JABGUARD); 973 mediastat |= ~XL_MEDIASTAT_SQEENB; 974 } 975 } 976 977 if (sc->xl_media & XL_MEDIAOPT_BNC) { 978 if (IFM_SUBTYPE(media) == IFM_10_2) { 979 printf("BNC port, "); 980 sc->xl_xcvr = XL_XCVR_COAX; 981 icfg &= ~XL_ICFG_CONNECTOR_MASK; 982 icfg |= (XL_XCVR_COAX << XL_ICFG_CONNECTOR_BITS); 983 mediastat &= ~(XL_MEDIASTAT_LINKBEAT| 984 XL_MEDIASTAT_JABGUARD| 985 XL_MEDIASTAT_SQEENB); 986 } 987 } 988 989 if ((media & IFM_GMASK) == IFM_FDX || 990 IFM_SUBTYPE(media) == IFM_100_FX) { 991 printf("full duplex\n"); 992 XL_SEL_WIN(3); 993 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, XL_MACCTRL_DUPLEX); 994 } else { 995 printf("half duplex\n"); 996 XL_SEL_WIN(3); 997 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, 998 (CSR_READ_1(sc, XL_W3_MAC_CTRL) & ~XL_MACCTRL_DUPLEX)); 999 } 1000 1001 if (IFM_SUBTYPE(media) == IFM_10_2) 1002 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_START); 1003 else 1004 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP); 1005 CSR_WRITE_4(sc, XL_W3_INTERNAL_CFG, icfg); 1006 XL_SEL_WIN(4); 1007 CSR_WRITE_2(sc, XL_W4_MEDIA_STATUS, mediastat); 1008 DELAY(800); 1009 XL_SEL_WIN(7); 1010 } 1011 1012 static void 1013 xl_reset(struct xl_softc *sc) 1014 { 1015 int i; 1016 1017 XL_SEL_WIN(0); 1018 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RESET | 1019 ((sc->xl_flags & XL_FLAG_WEIRDRESET) ? 1020 XL_RESETOPT_DISADVFD:0)); 1021 1022 /* 1023 * If we're using memory mapped register mode, pause briefly 1024 * after issuing the reset command before trying to access any 1025 * other registers. With my 3c575C cardbus card, failing to do 1026 * this results in the system locking up while trying to poll 1027 * the command busy bit in the status register. 1028 */ 1029 if (sc->xl_flags & XL_FLAG_USE_MMIO) 1030 DELAY(100000); 1031 1032 for (i = 0; i < XL_TIMEOUT; i++) { 1033 DELAY(10); 1034 if (!(CSR_READ_2(sc, XL_STATUS) & XL_STAT_CMDBUSY)) 1035 break; 1036 } 1037 1038 if (i == XL_TIMEOUT) 1039 if_printf(&sc->arpcom.ac_if, "reset didn't complete\n"); 1040 1041 /* Reset TX and RX. */ 1042 /* Note: the RX reset takes an absurd amount of time 1043 * on newer versions of the Tornado chips such as those 1044 * on the 3c905CX and newer 3c908C cards. We wait an 1045 * extra amount of time so that xl_wait() doesn't complain 1046 * and annoy the users. 1047 */ 1048 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET); 1049 DELAY(100000); 1050 xl_wait(sc); 1051 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); 1052 xl_wait(sc); 1053 1054 if (sc->xl_flags & XL_FLAG_INVERT_LED_PWR || 1055 sc->xl_flags & XL_FLAG_INVERT_MII_PWR) { 1056 XL_SEL_WIN(2); 1057 CSR_WRITE_2(sc, XL_W2_RESET_OPTIONS, CSR_READ_2(sc, 1058 XL_W2_RESET_OPTIONS) 1059 | ((sc->xl_flags & XL_FLAG_INVERT_LED_PWR)?XL_RESETOPT_INVERT_LED:0) 1060 | ((sc->xl_flags & XL_FLAG_INVERT_MII_PWR)?XL_RESETOPT_INVERT_MII:0) 1061 ); 1062 } 1063 1064 /* Wait a little while for the chip to get its brains in order. */ 1065 DELAY(100000); 1066 return; 1067 } 1068 1069 /* 1070 * Probe for a 3Com Etherlink XL chip. Check the PCI vendor and device 1071 * IDs against our list and return a device name if we find a match. 1072 */ 1073 static int 1074 xl_probe(device_t dev) 1075 { 1076 struct xl_type *t; 1077 uint16_t vid, did; 1078 1079 vid = pci_get_vendor(dev); 1080 did = pci_get_device(dev); 1081 for (t = xl_devs; t->xl_name != NULL; t++) { 1082 if (vid == t->xl_vid && did == t->xl_did) { 1083 device_set_desc(dev, t->xl_name); 1084 return(0); 1085 } 1086 } 1087 return(ENXIO); 1088 } 1089 1090 /* 1091 * This routine is a kludge to work around possible hardware faults 1092 * or manufacturing defects that can cause the media options register 1093 * (or reset options register, as it's called for the first generation 1094 * 3c90x adapters) to return an incorrect result. I have encountered 1095 * one Dell Latitude laptop docking station with an integrated 3c905-TX 1096 * which doesn't have any of the 'mediaopt' bits set. This screws up 1097 * the attach routine pretty badly because it doesn't know what media 1098 * to look for. If we find ourselves in this predicament, this routine 1099 * will try to guess the media options values and warn the user of a 1100 * possible manufacturing defect with his adapter/system/whatever. 1101 */ 1102 static void 1103 xl_mediacheck(struct xl_softc *sc) 1104 { 1105 struct ifnet *ifp = &sc->arpcom.ac_if; 1106 1107 /* 1108 * If some of the media options bits are set, assume they are 1109 * correct. If not, try to figure it out down below. 1110 * XXX I should check for 10baseFL, but I don't have an adapter 1111 * to test with. 1112 */ 1113 if (sc->xl_media & (XL_MEDIAOPT_MASK & ~XL_MEDIAOPT_VCO)) { 1114 /* 1115 * Check the XCVR value. If it's not in the normal range 1116 * of values, we need to fake it up here. 1117 */ 1118 if (sc->xl_xcvr <= XL_XCVR_AUTO) 1119 return; 1120 else { 1121 if_printf(ifp, "bogus xcvr value in EEPROM (%x)\n", 1122 sc->xl_xcvr); 1123 if_printf(ifp, 1124 "choosing new default based on card type\n"); 1125 } 1126 } else { 1127 if (sc->xl_type == XL_TYPE_905B && 1128 sc->xl_media & XL_MEDIAOPT_10FL) 1129 return; 1130 if_printf(ifp, "WARNING: no media options bits set in " 1131 "the media options register!!\n"); 1132 if_printf(ifp, "this could be a manufacturing defect in " 1133 "your adapter or system\n"); 1134 if_printf(ifp, "attempting to guess media type; you " 1135 "should probably consult your vendor\n"); 1136 } 1137 1138 xl_choose_xcvr(sc, 1); 1139 } 1140 1141 static void 1142 xl_choose_xcvr(struct xl_softc *sc, int verbose) 1143 { 1144 struct ifnet *ifp = &sc->arpcom.ac_if; 1145 u_int16_t devid; 1146 1147 /* 1148 * Read the device ID from the EEPROM. 1149 * This is what's loaded into the PCI device ID register, so it has 1150 * to be correct otherwise we wouldn't have gotten this far. 1151 */ 1152 xl_read_eeprom(sc, (caddr_t)&devid, XL_EE_PRODID, 1, 0); 1153 1154 switch(devid) { 1155 case TC_DEVICEID_BOOMERANG_10BT: /* 3c900-TPO */ 1156 case TC_DEVICEID_KRAKATOA_10BT: /* 3c900B-TPO */ 1157 sc->xl_media = XL_MEDIAOPT_BT; 1158 sc->xl_xcvr = XL_XCVR_10BT; 1159 if (verbose) 1160 if_printf(ifp, "guessing 10BaseT transceiver\n"); 1161 break; 1162 case TC_DEVICEID_BOOMERANG_10BT_COMBO: /* 3c900-COMBO */ 1163 case TC_DEVICEID_KRAKATOA_10BT_COMBO: /* 3c900B-COMBO */ 1164 sc->xl_media = XL_MEDIAOPT_BT|XL_MEDIAOPT_BNC|XL_MEDIAOPT_AUI; 1165 sc->xl_xcvr = XL_XCVR_10BT; 1166 if (verbose) 1167 if_printf(ifp, "guessing COMBO (AUI/BNC/TP)\n"); 1168 break; 1169 case TC_DEVICEID_KRAKATOA_10BT_TPC: /* 3c900B-TPC */ 1170 sc->xl_media = XL_MEDIAOPT_BT|XL_MEDIAOPT_BNC; 1171 sc->xl_xcvr = XL_XCVR_10BT; 1172 if (verbose) 1173 if_printf(ifp, "guessing TPC (BNC/TP)\n"); 1174 break; 1175 case TC_DEVICEID_CYCLONE_10FL: /* 3c900B-FL */ 1176 sc->xl_media = XL_MEDIAOPT_10FL; 1177 sc->xl_xcvr = XL_XCVR_AUI; 1178 if (verbose) 1179 if_printf(ifp, "guessing 10baseFL\n"); 1180 break; 1181 case TC_DEVICEID_BOOMERANG_10_100BT: /* 3c905-TX */ 1182 case TC_DEVICEID_HURRICANE_555: /* 3c555 */ 1183 case TC_DEVICEID_HURRICANE_556: /* 3c556 */ 1184 case TC_DEVICEID_HURRICANE_556B: /* 3c556B */ 1185 case TC_DEVICEID_HURRICANE_575A: /* 3c575TX */ 1186 case TC_DEVICEID_HURRICANE_575B: /* 3c575B */ 1187 case TC_DEVICEID_HURRICANE_575C: /* 3c575C */ 1188 case TC_DEVICEID_HURRICANE_656: /* 3c656 */ 1189 case TC_DEVICEID_HURRICANE_656B: /* 3c656B */ 1190 case TC_DEVICEID_TORNADO_656C: /* 3c656C */ 1191 case TC_DEVICEID_TORNADO_10_100BT_920B: /* 3c920B-EMB */ 1192 sc->xl_media = XL_MEDIAOPT_MII; 1193 sc->xl_xcvr = XL_XCVR_MII; 1194 if (verbose) 1195 if_printf(ifp, "guessing MII\n"); 1196 break; 1197 case TC_DEVICEID_BOOMERANG_100BT4: /* 3c905-T4 */ 1198 case TC_DEVICEID_CYCLONE_10_100BT4: /* 3c905B-T4 */ 1199 sc->xl_media = XL_MEDIAOPT_BT4; 1200 sc->xl_xcvr = XL_XCVR_MII; 1201 if (verbose) 1202 if_printf(ifp, "guessing 100BaseT4/MII\n"); 1203 break; 1204 case TC_DEVICEID_HURRICANE_10_100BT: /* 3c905B-TX */ 1205 case TC_DEVICEID_HURRICANE_10_100BT_SERV:/*3c980-TX */ 1206 case TC_DEVICEID_TORNADO_10_100BT_SERV: /* 3c980C-TX */ 1207 case TC_DEVICEID_HURRICANE_SOHO100TX: /* 3cSOHO100-TX */ 1208 case TC_DEVICEID_TORNADO_10_100BT: /* 3c905C-TX */ 1209 case TC_DEVICEID_TORNADO_HOMECONNECT: /* 3c450-TX */ 1210 sc->xl_media = XL_MEDIAOPT_BTX; 1211 sc->xl_xcvr = XL_XCVR_AUTO; 1212 if (verbose) 1213 if_printf(ifp, "guessing 10/100 internal\n"); 1214 break; 1215 case TC_DEVICEID_CYCLONE_10_100_COMBO: /* 3c905B-COMBO */ 1216 sc->xl_media = XL_MEDIAOPT_BTX|XL_MEDIAOPT_BNC|XL_MEDIAOPT_AUI; 1217 sc->xl_xcvr = XL_XCVR_AUTO; 1218 if (verbose) 1219 if_printf(ifp, "guessing 10/100 plus BNC/AUI\n"); 1220 break; 1221 default: 1222 if_printf(ifp, 1223 "unknown device ID: %x -- defaulting to 10baseT\n", devid); 1224 sc->xl_media = XL_MEDIAOPT_BT; 1225 break; 1226 } 1227 1228 return; 1229 } 1230 1231 /* 1232 * Attach the interface. Allocate softc structures, do ifmedia 1233 * setup and ethernet/BPF attach. 1234 */ 1235 static int 1236 xl_attach(device_t dev) 1237 { 1238 u_char eaddr[ETHER_ADDR_LEN]; 1239 u_int16_t xcvr[2]; 1240 struct xl_softc *sc; 1241 struct ifnet *ifp; 1242 int media = IFM_ETHER|IFM_100_TX|IFM_FDX; 1243 int error = 0, rid, res; 1244 uint16_t did; 1245 1246 sc = device_get_softc(dev); 1247 1248 ifmedia_init(&sc->ifmedia, 0, xl_ifmedia_upd, xl_ifmedia_sts); 1249 1250 did = pci_get_device(dev); 1251 1252 sc->xl_flags = 0; 1253 if (did == TC_DEVICEID_HURRICANE_555) 1254 sc->xl_flags |= XL_FLAG_EEPROM_OFFSET_30 | XL_FLAG_PHYOK; 1255 if (did == TC_DEVICEID_HURRICANE_556 || 1256 did == TC_DEVICEID_HURRICANE_556B) 1257 sc->xl_flags |= XL_FLAG_FUNCREG | XL_FLAG_PHYOK | 1258 XL_FLAG_EEPROM_OFFSET_30 | XL_FLAG_WEIRDRESET | 1259 XL_FLAG_INVERT_LED_PWR | XL_FLAG_INVERT_MII_PWR; 1260 if (did == TC_DEVICEID_HURRICANE_555 || 1261 did == TC_DEVICEID_HURRICANE_556) 1262 sc->xl_flags |= XL_FLAG_8BITROM; 1263 if (did == TC_DEVICEID_HURRICANE_556B) 1264 sc->xl_flags |= XL_FLAG_NO_XCVR_PWR; 1265 if (did == TC_DEVICEID_HURRICANE_575B || 1266 did == TC_DEVICEID_HURRICANE_575C || 1267 did == TC_DEVICEID_HURRICANE_656B || 1268 did == TC_DEVICEID_TORNADO_656C) 1269 sc->xl_flags |= XL_FLAG_FUNCREG; 1270 if (did == TC_DEVICEID_HURRICANE_575A || 1271 did == TC_DEVICEID_HURRICANE_575B || 1272 did == TC_DEVICEID_HURRICANE_575C || 1273 did == TC_DEVICEID_HURRICANE_656B || 1274 did == TC_DEVICEID_TORNADO_656C) 1275 sc->xl_flags |= XL_FLAG_PHYOK | XL_FLAG_EEPROM_OFFSET_30 | 1276 XL_FLAG_8BITROM; 1277 if (did == TC_DEVICEID_HURRICANE_656) 1278 sc->xl_flags |= XL_FLAG_FUNCREG | XL_FLAG_PHYOK; 1279 if (did == TC_DEVICEID_HURRICANE_575B) 1280 sc->xl_flags |= XL_FLAG_INVERT_LED_PWR; 1281 if (did == TC_DEVICEID_HURRICANE_575C) 1282 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR; 1283 if (did == TC_DEVICEID_TORNADO_656C) 1284 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR; 1285 if (did == TC_DEVICEID_HURRICANE_656 || 1286 did == TC_DEVICEID_HURRICANE_656B) 1287 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR | 1288 XL_FLAG_INVERT_LED_PWR; 1289 if (did == TC_DEVICEID_TORNADO_10_100BT_920B) 1290 sc->xl_flags |= XL_FLAG_PHYOK; 1291 #ifndef BURN_BRIDGES 1292 /* 1293 * If this is a 3c905B, we have to check one extra thing. 1294 * The 905B supports power management and may be placed in 1295 * a low-power mode (D3 mode), typically by certain operating 1296 * systems which shall not be named. The PCI BIOS is supposed 1297 * to reset the NIC and bring it out of low-power mode, but 1298 * some do not. Consequently, we have to see if this chip 1299 * supports power management, and if so, make sure it's not 1300 * in low-power mode. If power management is available, the 1301 * capid byte will be 0x01. 1302 * 1303 * I _think_ that what actually happens is that the chip 1304 * loses its PCI configuration during the transition from 1305 * D3 back to D0; this means that it should be possible for 1306 * us to save the PCI iobase, membase and IRQ, put the chip 1307 * back in the D0 state, then restore the PCI config ourselves. 1308 */ 1309 1310 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 1311 u_int32_t iobase, membase, irq; 1312 1313 /* Save important PCI config data. */ 1314 iobase = pci_read_config(dev, XL_PCI_LOIO, 4); 1315 membase = pci_read_config(dev, XL_PCI_LOMEM, 4); 1316 irq = pci_read_config(dev, XL_PCI_INTLINE, 4); 1317 1318 /* Reset the power state. */ 1319 device_printf(dev, "chip is in D%d power mode " 1320 "-- setting to D0\n", pci_get_powerstate(dev)); 1321 1322 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 1323 1324 /* Restore PCI config data. */ 1325 pci_write_config(dev, XL_PCI_LOIO, iobase, 4); 1326 pci_write_config(dev, XL_PCI_LOMEM, membase, 4); 1327 pci_write_config(dev, XL_PCI_INTLINE, irq, 4); 1328 } 1329 #endif 1330 /* 1331 * Map control/status registers. 1332 */ 1333 pci_enable_busmaster(dev); 1334 1335 rid = XL_PCI_LOMEM; 1336 res = SYS_RES_MEMORY; 1337 1338 #if 0 1339 sc->xl_res = bus_alloc_resource_any(dev, res, &rid, RF_ACTIVE); 1340 #endif 1341 1342 if (sc->xl_res != NULL) { 1343 sc->xl_flags |= XL_FLAG_USE_MMIO; 1344 if (bootverbose) 1345 device_printf(dev, "using memory mapped I/O\n"); 1346 } else { 1347 rid = XL_PCI_LOIO; 1348 res = SYS_RES_IOPORT; 1349 sc->xl_res = bus_alloc_resource_any(dev, res, &rid, RF_ACTIVE); 1350 if (sc->xl_res == NULL) { 1351 device_printf(dev, "couldn't map ports/memory\n"); 1352 error = ENXIO; 1353 goto fail; 1354 } 1355 if (bootverbose) 1356 device_printf(dev, "using port I/O\n"); 1357 } 1358 1359 sc->xl_btag = rman_get_bustag(sc->xl_res); 1360 sc->xl_bhandle = rman_get_bushandle(sc->xl_res); 1361 1362 if (sc->xl_flags & XL_FLAG_FUNCREG) { 1363 rid = XL_PCI_FUNCMEM; 1364 sc->xl_fres = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 1365 RF_ACTIVE); 1366 1367 if (sc->xl_fres == NULL) { 1368 device_printf(dev, "couldn't map funcreg memory\n"); 1369 error = ENXIO; 1370 goto fail; 1371 } 1372 1373 sc->xl_ftag = rman_get_bustag(sc->xl_fres); 1374 sc->xl_fhandle = rman_get_bushandle(sc->xl_fres); 1375 } 1376 1377 /* Allocate interrupt */ 1378 rid = 0; 1379 sc->xl_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1380 RF_SHAREABLE | RF_ACTIVE); 1381 if (sc->xl_irq == NULL) { 1382 device_printf(dev, "couldn't map interrupt\n"); 1383 error = ENXIO; 1384 goto fail; 1385 } 1386 1387 ifp = &sc->arpcom.ac_if; 1388 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1389 1390 /* Reset the adapter. */ 1391 xl_reset(sc); 1392 1393 /* 1394 * Get station address from the EEPROM. 1395 */ 1396 if (xl_read_eeprom(sc, (caddr_t)&eaddr, XL_EE_OEM_ADR0, 3, 1)) { 1397 device_printf(dev, "failed to read station address\n"); 1398 error = ENXIO; 1399 goto fail; 1400 } 1401 1402 callout_init(&sc->xl_stat_timer); 1403 1404 error = xl_dma_alloc(dev); 1405 if (error) 1406 goto fail; 1407 1408 /* 1409 * Figure out the card type. 3c905B adapters have the 1410 * 'supportsNoTxLength' bit set in the capabilities 1411 * word in the EEPROM. 1412 * Note: my 3c575C cardbus card lies. It returns a value 1413 * of 0x1578 for its capabilities word, which is somewhat 1414 * nonsensical. Another way to distinguish a 3c90x chip 1415 * from a 3c90xB/C chip is to check for the 'supportsLargePackets' 1416 * bit. This will only be set for 3c90x boomerage chips. 1417 */ 1418 xl_read_eeprom(sc, (caddr_t)&sc->xl_caps, XL_EE_CAPS, 1, 0); 1419 if (sc->xl_caps & XL_CAPS_NO_TXLENGTH || 1420 !(sc->xl_caps & XL_CAPS_LARGE_PKTS)) 1421 sc->xl_type = XL_TYPE_905B; 1422 else 1423 sc->xl_type = XL_TYPE_90X; 1424 if (bootverbose) { 1425 device_printf(dev, "type %s\n", 1426 sc->xl_type == XL_TYPE_905B ? "90XB" : "90X"); 1427 } 1428 1429 ifp->if_softc = sc; 1430 ifp->if_mtu = ETHERMTU; 1431 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1432 ifp->if_ioctl = xl_ioctl; 1433 ifp->if_capabilities = 0; 1434 if (sc->xl_type == XL_TYPE_905B) { 1435 ifp->if_start = xl_start_90xB; 1436 ifp->if_capabilities |= IFCAP_HWCSUM; 1437 } else { 1438 ifp->if_start = xl_start; 1439 } 1440 ifp->if_watchdog = xl_watchdog; 1441 ifp->if_init = xl_init; 1442 #ifdef DEVICE_POLLING 1443 ifp->if_poll = xl_poll; 1444 #endif 1445 ifp->if_baudrate = 10000000; 1446 ifq_set_maxlen(&ifp->if_snd, XL_TX_LIST_CNT - 1); 1447 ifq_set_ready(&ifp->if_snd); 1448 /* 1449 * NOTE: features disabled by default. This seems to corrupt 1450 * tx packet data one out of a million packets or so and then 1451 * generates a good checksum so the receiver doesn't 1452 * know the packet is bad 1453 */ 1454 ifp->if_capenable = 0; /*ifp->if_capabilities;*/ 1455 if (ifp->if_capenable & IFCAP_TXCSUM) 1456 ifp->if_hwassist = XL905B_CSUM_FEATURES; 1457 1458 /* 1459 * Now we have to see what sort of media we have. 1460 * This includes probing for an MII interace and a 1461 * possible PHY. 1462 */ 1463 XL_SEL_WIN(3); 1464 sc->xl_media = CSR_READ_2(sc, XL_W3_MEDIA_OPT); 1465 if (bootverbose) 1466 if_printf(ifp, "media options word: %x\n", sc->xl_media); 1467 1468 xl_read_eeprom(sc, (char *)&xcvr, XL_EE_ICFG_0, 2, 0); 1469 sc->xl_xcvr = xcvr[0] | xcvr[1] << 16; 1470 sc->xl_xcvr &= XL_ICFG_CONNECTOR_MASK; 1471 sc->xl_xcvr >>= XL_ICFG_CONNECTOR_BITS; 1472 1473 xl_mediacheck(sc); 1474 1475 if (sc->xl_media & XL_MEDIAOPT_MII || sc->xl_media & XL_MEDIAOPT_BTX 1476 || sc->xl_media & XL_MEDIAOPT_BT4) { 1477 if (bootverbose) 1478 if_printf(ifp, "found MII/AUTO\n"); 1479 xl_setcfg(sc); 1480 1481 error = mii_phy_probe(dev, &sc->xl_miibus, 1482 xl_ifmedia_upd, xl_ifmedia_sts); 1483 if (error) { 1484 if_printf(ifp, "no PHY found!\n"); 1485 goto fail; 1486 } 1487 1488 goto done; 1489 } 1490 1491 /* 1492 * Sanity check. If the user has selected "auto" and this isn't 1493 * a 10/100 card of some kind, we need to force the transceiver 1494 * type to something sane. 1495 */ 1496 if (sc->xl_xcvr == XL_XCVR_AUTO) 1497 xl_choose_xcvr(sc, bootverbose); 1498 1499 /* 1500 * Do ifmedia setup. 1501 */ 1502 if (sc->xl_media & XL_MEDIAOPT_BT) { 1503 if (bootverbose) 1504 if_printf(ifp, "found 10baseT\n"); 1505 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL); 1506 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T|IFM_HDX, 0, NULL); 1507 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX) 1508 ifmedia_add(&sc->ifmedia, 1509 IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL); 1510 } 1511 1512 if (sc->xl_media & (XL_MEDIAOPT_AUI|XL_MEDIAOPT_10FL)) { 1513 /* 1514 * Check for a 10baseFL board in disguise. 1515 */ 1516 if (sc->xl_type == XL_TYPE_905B && 1517 sc->xl_media == XL_MEDIAOPT_10FL) { 1518 if (bootverbose) 1519 if_printf(ifp, "found 10baseFL\n"); 1520 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_FL, 0, NULL); 1521 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_FL|IFM_HDX, 1522 0, NULL); 1523 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX) 1524 ifmedia_add(&sc->ifmedia, 1525 IFM_ETHER|IFM_10_FL|IFM_FDX, 0, NULL); 1526 } else { 1527 if (bootverbose) 1528 if_printf(ifp, "found AUI\n"); 1529 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_5, 0, NULL); 1530 } 1531 } 1532 1533 if (sc->xl_media & XL_MEDIAOPT_BNC) { 1534 if (bootverbose) 1535 if_printf(ifp, "found BNC\n"); 1536 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_2, 0, NULL); 1537 } 1538 1539 if (sc->xl_media & XL_MEDIAOPT_BFX) { 1540 if (bootverbose) 1541 if_printf(ifp, "found 100baseFX\n"); 1542 ifp->if_baudrate = 100000000; 1543 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_FX, 0, NULL); 1544 } 1545 1546 /* Choose a default media. */ 1547 switch(sc->xl_xcvr) { 1548 case XL_XCVR_10BT: 1549 media = IFM_ETHER|IFM_10_T; 1550 xl_setmode(sc, media); 1551 break; 1552 case XL_XCVR_AUI: 1553 if (sc->xl_type == XL_TYPE_905B && 1554 sc->xl_media == XL_MEDIAOPT_10FL) { 1555 media = IFM_ETHER|IFM_10_FL; 1556 xl_setmode(sc, media); 1557 } else { 1558 media = IFM_ETHER|IFM_10_5; 1559 xl_setmode(sc, media); 1560 } 1561 break; 1562 case XL_XCVR_COAX: 1563 media = IFM_ETHER|IFM_10_2; 1564 xl_setmode(sc, media); 1565 break; 1566 case XL_XCVR_AUTO: 1567 case XL_XCVR_100BTX: 1568 case XL_XCVR_MII: 1569 /* Chosen by miibus */ 1570 break; 1571 case XL_XCVR_100BFX: 1572 media = IFM_ETHER|IFM_100_FX; 1573 break; 1574 default: 1575 if_printf(ifp, "unknown XCVR type: %d\n", sc->xl_xcvr); 1576 /* 1577 * This will probably be wrong, but it prevents 1578 * the ifmedia code from panicking. 1579 */ 1580 media = IFM_ETHER|IFM_10_T; 1581 break; 1582 } 1583 1584 if (sc->xl_miibus == NULL) 1585 ifmedia_set(&sc->ifmedia, media); 1586 1587 done: 1588 1589 if (sc->xl_flags & XL_FLAG_NO_XCVR_PWR) { 1590 XL_SEL_WIN(0); 1591 CSR_WRITE_2(sc, XL_W0_MFG_ID, XL_NO_XCVR_PWR_MAGICBITS); 1592 } 1593 1594 /* 1595 * Call MI attach routine. 1596 */ 1597 ether_ifattach(ifp, eaddr, NULL); 1598 1599 /* 1600 * Tell the upper layer(s) we support long frames. 1601 */ 1602 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1603 1604 /* Hook interrupt last to avoid having to lock softc */ 1605 error = bus_setup_intr(dev, sc->xl_irq, INTR_NETSAFE, 1606 xl_intr, sc, &sc->xl_intrhand, 1607 ifp->if_serializer); 1608 if (error) { 1609 if_printf(ifp, "couldn't set up irq\n"); 1610 ether_ifdetach(ifp); 1611 goto fail; 1612 } 1613 1614 return 0; 1615 1616 fail: 1617 xl_detach(dev); 1618 return error; 1619 } 1620 1621 /* 1622 * Shutdown hardware and free up resources. This can be called any 1623 * time after the mutex has been initialized. It is called in both 1624 * the error case in attach and the normal detach case so it needs 1625 * to be careful about only freeing resources that have actually been 1626 * allocated. 1627 */ 1628 static int 1629 xl_detach(device_t dev) 1630 { 1631 struct xl_softc *sc; 1632 struct ifnet *ifp; 1633 int rid, res; 1634 1635 sc = device_get_softc(dev); 1636 ifp = &sc->arpcom.ac_if; 1637 1638 if (sc->xl_flags & XL_FLAG_USE_MMIO) { 1639 rid = XL_PCI_LOMEM; 1640 res = SYS_RES_MEMORY; 1641 } else { 1642 rid = XL_PCI_LOIO; 1643 res = SYS_RES_IOPORT; 1644 } 1645 1646 if (device_is_attached(dev)) { 1647 lwkt_serialize_enter(ifp->if_serializer); 1648 xl_reset(sc); 1649 xl_stop(sc); 1650 bus_teardown_intr(dev, sc->xl_irq, sc->xl_intrhand); 1651 lwkt_serialize_exit(ifp->if_serializer); 1652 1653 ether_ifdetach(ifp); 1654 } 1655 1656 if (sc->xl_miibus) 1657 device_delete_child(dev, sc->xl_miibus); 1658 bus_generic_detach(dev); 1659 ifmedia_removeall(&sc->ifmedia); 1660 1661 if (sc->xl_irq) 1662 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->xl_irq); 1663 if (sc->xl_fres != NULL) 1664 bus_release_resource(dev, SYS_RES_MEMORY, 1665 XL_PCI_FUNCMEM, sc->xl_fres); 1666 if (sc->xl_res) 1667 bus_release_resource(dev, res, rid, sc->xl_res); 1668 1669 xl_dma_free(dev); 1670 1671 return(0); 1672 } 1673 1674 static int 1675 xl_dma_alloc(device_t dev) 1676 { 1677 struct xl_softc *sc; 1678 struct xl_chain_data *cd; 1679 struct xl_list_data *ld; 1680 int i, error; 1681 1682 sc = device_get_softc(dev); 1683 cd = &sc->xl_cdata; 1684 ld = &sc->xl_ldata; 1685 1686 /* 1687 * Now allocate a tag for the DMA descriptor lists and a chunk 1688 * of DMA-able memory based on the tag. Also obtain the DMA 1689 * addresses of the RX and TX ring, which we'll need later. 1690 * All of our lists are allocated as a contiguous block 1691 * of memory. 1692 */ 1693 error = bus_dma_tag_create(NULL, 8, 0, 1694 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, 1695 NULL, NULL, 1696 XL_RX_LIST_SZ, 1, XL_RX_LIST_SZ, 1697 0, &ld->xl_rx_tag); 1698 if (error) { 1699 device_printf(dev, "failed to allocate rx dma tag\n"); 1700 return error; 1701 } 1702 1703 error = bus_dmamem_alloc(ld->xl_rx_tag, (void **)&ld->xl_rx_list, 1704 BUS_DMA_WAITOK | BUS_DMA_ZERO, 1705 &ld->xl_rx_dmamap); 1706 if (error) { 1707 device_printf(dev, "no memory for rx list buffers!\n"); 1708 bus_dma_tag_destroy(ld->xl_rx_tag); 1709 ld->xl_rx_tag = NULL; 1710 return error; 1711 } 1712 1713 error = bus_dmamap_load(ld->xl_rx_tag, ld->xl_rx_dmamap, 1714 ld->xl_rx_list, XL_RX_LIST_SZ, 1715 xl_dma_map_addr, &ld->xl_rx_dmaaddr, 1716 BUS_DMA_WAITOK); 1717 if (error) { 1718 device_printf(dev, "cannot get dma address of the rx ring!\n"); 1719 bus_dmamem_free(ld->xl_rx_tag, ld->xl_rx_list, 1720 ld->xl_rx_dmamap); 1721 bus_dma_tag_destroy(ld->xl_rx_tag); 1722 ld->xl_rx_tag = NULL; 1723 return error; 1724 } 1725 1726 error = bus_dma_tag_create(NULL, 8, 0, 1727 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, 1728 NULL, NULL, 1729 XL_TX_LIST_SZ, 1, XL_TX_LIST_SZ, 1730 0, &ld->xl_tx_tag); 1731 if (error) { 1732 device_printf(dev, "failed to allocate tx dma tag\n"); 1733 return error; 1734 } 1735 1736 error = bus_dmamem_alloc(ld->xl_tx_tag, (void **)&ld->xl_tx_list, 1737 BUS_DMA_WAITOK | BUS_DMA_ZERO, 1738 &ld->xl_tx_dmamap); 1739 if (error) { 1740 device_printf(dev, "no memory for list buffers!\n"); 1741 bus_dma_tag_destroy(ld->xl_tx_tag); 1742 ld->xl_tx_tag = NULL; 1743 return error; 1744 } 1745 1746 error = bus_dmamap_load(ld->xl_tx_tag, ld->xl_tx_dmamap, 1747 ld->xl_tx_list, XL_TX_LIST_SZ, 1748 xl_dma_map_addr, &ld->xl_tx_dmaaddr, 1749 BUS_DMA_WAITOK); 1750 if (error) { 1751 device_printf(dev, "cannot get dma address of the tx ring!\n"); 1752 bus_dmamem_free(ld->xl_tx_tag, ld->xl_tx_list, 1753 ld->xl_tx_dmamap); 1754 bus_dma_tag_destroy(ld->xl_tx_tag); 1755 ld->xl_tx_tag = NULL; 1756 return error; 1757 } 1758 1759 /* 1760 * Allocate a DMA tag for the mapping of mbufs. 1761 */ 1762 error = bus_dma_tag_create(NULL, 1, 0, 1763 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, 1764 NULL, NULL, 1765 MCLBYTES * XL_MAXFRAGS, XL_MAXFRAGS, 1766 MCLBYTES, 0, &sc->xl_mtag); 1767 if (error) { 1768 device_printf(dev, "failed to allocate mbuf dma tag\n"); 1769 return error; 1770 } 1771 1772 /* 1773 * Allocate a spare DMA map for the RX ring. 1774 */ 1775 error = bus_dmamap_create(sc->xl_mtag, 0, &sc->xl_tmpmap); 1776 if (error) { 1777 device_printf(dev, "failed to create mbuf dma map\n"); 1778 bus_dma_tag_destroy(sc->xl_mtag); 1779 sc->xl_mtag = NULL; 1780 return error; 1781 } 1782 1783 for (i = 0; i < XL_RX_LIST_CNT; i++) { 1784 error = bus_dmamap_create(sc->xl_mtag, 0, 1785 &cd->xl_rx_chain[i].xl_map); 1786 if (error) { 1787 device_printf(dev, "failed to create %dth " 1788 "rx descriptor dma map!\n", i); 1789 return error; 1790 } 1791 cd->xl_rx_chain[i].xl_ptr = &ld->xl_rx_list[i]; 1792 } 1793 1794 for (i = 0; i < XL_TX_LIST_CNT; i++) { 1795 error = bus_dmamap_create(sc->xl_mtag, 0, 1796 &cd->xl_tx_chain[i].xl_map); 1797 if (error) { 1798 device_printf(dev, "failed to create %dth " 1799 "tx descriptor dma map!\n", i); 1800 return error; 1801 } 1802 cd->xl_tx_chain[i].xl_ptr = &ld->xl_tx_list[i]; 1803 } 1804 return 0; 1805 } 1806 1807 static void 1808 xl_dma_free(device_t dev) 1809 { 1810 struct xl_softc *sc; 1811 struct xl_chain_data *cd; 1812 struct xl_list_data *ld; 1813 int i; 1814 1815 sc = device_get_softc(dev); 1816 cd = &sc->xl_cdata; 1817 ld = &sc->xl_ldata; 1818 1819 for (i = 0; i < XL_RX_LIST_CNT; ++i) { 1820 if (cd->xl_rx_chain[i].xl_ptr != NULL) { 1821 if (cd->xl_rx_chain[i].xl_mbuf != NULL) { 1822 bus_dmamap_unload(sc->xl_mtag, 1823 cd->xl_rx_chain[i].xl_map); 1824 m_freem(cd->xl_rx_chain[i].xl_mbuf); 1825 } 1826 bus_dmamap_destroy(sc->xl_mtag, 1827 cd->xl_rx_chain[i].xl_map); 1828 } 1829 } 1830 1831 for (i = 0; i < XL_TX_LIST_CNT; ++i) { 1832 if (cd->xl_tx_chain[i].xl_ptr != NULL) { 1833 if (cd->xl_tx_chain[i].xl_mbuf != NULL) { 1834 bus_dmamap_unload(sc->xl_mtag, 1835 cd->xl_tx_chain[i].xl_map); 1836 m_freem(cd->xl_tx_chain[i].xl_mbuf); 1837 } 1838 bus_dmamap_destroy(sc->xl_mtag, 1839 cd->xl_tx_chain[i].xl_map); 1840 } 1841 } 1842 1843 if (ld->xl_rx_tag) { 1844 bus_dmamap_unload(ld->xl_rx_tag, ld->xl_rx_dmamap); 1845 bus_dmamem_free(ld->xl_rx_tag, ld->xl_rx_list, 1846 ld->xl_rx_dmamap); 1847 bus_dma_tag_destroy(ld->xl_rx_tag); 1848 } 1849 1850 if (ld->xl_tx_tag) { 1851 bus_dmamap_unload(ld->xl_tx_tag, ld->xl_tx_dmamap); 1852 bus_dmamem_free(ld->xl_tx_tag, ld->xl_tx_list, 1853 ld->xl_tx_dmamap); 1854 bus_dma_tag_destroy(ld->xl_tx_tag); 1855 } 1856 1857 if (sc->xl_mtag) { 1858 bus_dmamap_destroy(sc->xl_mtag, sc->xl_tmpmap); 1859 bus_dma_tag_destroy(sc->xl_mtag); 1860 } 1861 } 1862 1863 /* 1864 * Initialize the transmit descriptors. 1865 */ 1866 static void 1867 xl_list_tx_init(struct xl_softc *sc) 1868 { 1869 struct xl_chain_data *cd; 1870 struct xl_list_data *ld; 1871 int i; 1872 1873 cd = &sc->xl_cdata; 1874 ld = &sc->xl_ldata; 1875 for (i = 0; i < XL_TX_LIST_CNT; i++) { 1876 cd->xl_tx_chain[i].xl_phys = ld->xl_tx_dmaaddr + 1877 i * sizeof(struct xl_list); 1878 if (i == (XL_TX_LIST_CNT - 1)) 1879 cd->xl_tx_chain[i].xl_next = NULL; 1880 else 1881 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[i + 1]; 1882 } 1883 1884 cd->xl_tx_free = &cd->xl_tx_chain[0]; 1885 cd->xl_tx_tail = cd->xl_tx_head = NULL; 1886 1887 bus_dmamap_sync(ld->xl_tx_tag, ld->xl_tx_dmamap, BUS_DMASYNC_PREWRITE); 1888 } 1889 1890 /* 1891 * Initialize the transmit descriptors. 1892 */ 1893 static void 1894 xl_list_tx_init_90xB(struct xl_softc *sc) 1895 { 1896 struct xl_chain_data *cd; 1897 struct xl_list_data *ld; 1898 int i; 1899 1900 cd = &sc->xl_cdata; 1901 ld = &sc->xl_ldata; 1902 for (i = 0; i < XL_TX_LIST_CNT; i++) { 1903 cd->xl_tx_chain[i].xl_phys = ld->xl_tx_dmaaddr + 1904 i * sizeof(struct xl_list); 1905 if (i == (XL_TX_LIST_CNT - 1)) 1906 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[0]; 1907 else 1908 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[i + 1]; 1909 if (i == 0) { 1910 cd->xl_tx_chain[i].xl_prev = 1911 &cd->xl_tx_chain[XL_TX_LIST_CNT - 1]; 1912 } else { 1913 cd->xl_tx_chain[i].xl_prev = 1914 &cd->xl_tx_chain[i - 1]; 1915 } 1916 } 1917 1918 ld->xl_tx_list[0].xl_status = htole32(XL_TXSTAT_EMPTY); 1919 1920 cd->xl_tx_prod = 1; 1921 cd->xl_tx_cons = 1; 1922 cd->xl_tx_cnt = 0; 1923 1924 bus_dmamap_sync(ld->xl_tx_tag, ld->xl_tx_dmamap, BUS_DMASYNC_PREWRITE); 1925 } 1926 1927 /* 1928 * Initialize the RX descriptors and allocate mbufs for them. Note that 1929 * we arrange the descriptors in a closed ring, so that the last descriptor 1930 * points back to the first. 1931 */ 1932 static int 1933 xl_list_rx_init(struct xl_softc *sc) 1934 { 1935 struct xl_chain_data *cd; 1936 struct xl_list_data *ld; 1937 int error, i, next; 1938 u_int32_t nextptr; 1939 1940 cd = &sc->xl_cdata; 1941 ld = &sc->xl_ldata; 1942 1943 for (i = 0; i < XL_RX_LIST_CNT; i++) { 1944 error = xl_newbuf(sc, &cd->xl_rx_chain[i]); 1945 if (error) 1946 return(error); 1947 if (i == (XL_RX_LIST_CNT - 1)) 1948 next = 0; 1949 else 1950 next = i + 1; 1951 nextptr = ld->xl_rx_dmaaddr + 1952 next * sizeof(struct xl_list_onefrag); 1953 cd->xl_rx_chain[i].xl_next = &cd->xl_rx_chain[next]; 1954 ld->xl_rx_list[i].xl_next = htole32(nextptr); 1955 } 1956 1957 bus_dmamap_sync(ld->xl_rx_tag, ld->xl_rx_dmamap, BUS_DMASYNC_PREWRITE); 1958 cd->xl_rx_head = &cd->xl_rx_chain[0]; 1959 1960 return(0); 1961 } 1962 1963 /* 1964 * Initialize an RX descriptor and attach an MBUF cluster. 1965 * If we fail to do so, we need to leave the old mbuf and 1966 * the old DMA map untouched so that it can be reused. 1967 */ 1968 static int 1969 xl_newbuf(struct xl_softc *sc, struct xl_chain_onefrag *c) 1970 { 1971 struct mbuf *m_new; 1972 bus_dmamap_t map; 1973 int error; 1974 u_int32_t baddr; 1975 1976 m_new = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR); 1977 if (m_new == NULL) 1978 return(ENOBUFS); 1979 1980 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1981 1982 /* Force longword alignment for packet payload. */ 1983 m_adj(m_new, ETHER_ALIGN); 1984 1985 error = bus_dmamap_load_mbuf(sc->xl_mtag, sc->xl_tmpmap, m_new, 1986 xl_dma_map_rxbuf, &baddr, BUS_DMA_NOWAIT); 1987 if (error) { 1988 m_freem(m_new); 1989 if_printf(&sc->arpcom.ac_if, "can't map mbuf (error %d)\n", 1990 error); 1991 return(error); 1992 } 1993 1994 bus_dmamap_unload(sc->xl_mtag, c->xl_map); 1995 map = c->xl_map; 1996 c->xl_map = sc->xl_tmpmap; 1997 sc->xl_tmpmap = map; 1998 c->xl_mbuf = m_new; 1999 c->xl_ptr->xl_frag.xl_len = htole32(m_new->m_len | XL_LAST_FRAG); 2000 c->xl_ptr->xl_status = 0; 2001 c->xl_ptr->xl_frag.xl_addr = htole32(baddr); 2002 bus_dmamap_sync(sc->xl_mtag, c->xl_map, BUS_DMASYNC_PREREAD); 2003 return(0); 2004 } 2005 2006 static int 2007 xl_rx_resync(struct xl_softc *sc) 2008 { 2009 struct xl_chain_onefrag *pos; 2010 int i; 2011 2012 pos = sc->xl_cdata.xl_rx_head; 2013 2014 for (i = 0; i < XL_RX_LIST_CNT; i++) { 2015 if (pos->xl_ptr->xl_status) 2016 break; 2017 pos = pos->xl_next; 2018 } 2019 2020 if (i == XL_RX_LIST_CNT) 2021 return(0); 2022 2023 sc->xl_cdata.xl_rx_head = pos; 2024 2025 return(EAGAIN); 2026 } 2027 2028 /* 2029 * A frame has been uploaded: pass the resulting mbuf chain up to 2030 * the higher level protocols. 2031 */ 2032 static void 2033 xl_rxeof(struct xl_softc *sc, int count) 2034 { 2035 struct mbuf *m; 2036 struct ifnet *ifp; 2037 struct xl_chain_onefrag *cur_rx; 2038 int total_len = 0; 2039 u_int32_t rxstat; 2040 2041 ifp = &sc->arpcom.ac_if; 2042 2043 again: 2044 2045 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag, sc->xl_ldata.xl_rx_dmamap, 2046 BUS_DMASYNC_POSTREAD); 2047 while((rxstat = le32toh(sc->xl_cdata.xl_rx_head->xl_ptr->xl_status))) { 2048 #ifdef DEVICE_POLLING 2049 if (count >= 0 && count-- == 0) 2050 break; 2051 #endif 2052 cur_rx = sc->xl_cdata.xl_rx_head; 2053 sc->xl_cdata.xl_rx_head = cur_rx->xl_next; 2054 total_len = rxstat & XL_RXSTAT_LENMASK; 2055 2056 /* 2057 * Since we have told the chip to allow large frames, 2058 * we need to trap giant frame errors in software. We allow 2059 * a little more than the normal frame size to account for 2060 * frames with VLAN tags. 2061 */ 2062 if (total_len > XL_MAX_FRAMELEN) 2063 rxstat |= (XL_RXSTAT_UP_ERROR|XL_RXSTAT_OVERSIZE); 2064 2065 /* 2066 * If an error occurs, update stats, clear the 2067 * status word and leave the mbuf cluster in place: 2068 * it should simply get re-used next time this descriptor 2069 * comes up in the ring. 2070 */ 2071 if (rxstat & XL_RXSTAT_UP_ERROR) { 2072 ifp->if_ierrors++; 2073 cur_rx->xl_ptr->xl_status = 0; 2074 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag, 2075 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE); 2076 continue; 2077 } 2078 2079 /* 2080 * If the error bit was not set, the upload complete 2081 * bit should be set which means we have a valid packet. 2082 * If not, something truly strange has happened. 2083 */ 2084 if (!(rxstat & XL_RXSTAT_UP_CMPLT)) { 2085 if_printf(ifp, 2086 "bad receive status -- packet dropped\n"); 2087 ifp->if_ierrors++; 2088 cur_rx->xl_ptr->xl_status = 0; 2089 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag, 2090 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE); 2091 continue; 2092 } 2093 2094 /* No errors; receive the packet. */ 2095 bus_dmamap_sync(sc->xl_mtag, cur_rx->xl_map, 2096 BUS_DMASYNC_POSTREAD); 2097 m = cur_rx->xl_mbuf; 2098 2099 /* 2100 * Try to conjure up a new mbuf cluster. If that 2101 * fails, it means we have an out of memory condition and 2102 * should leave the buffer in place and continue. This will 2103 * result in a lost packet, but there's little else we 2104 * can do in this situation. 2105 */ 2106 if (xl_newbuf(sc, cur_rx)) { 2107 ifp->if_ierrors++; 2108 cur_rx->xl_ptr->xl_status = 0; 2109 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag, 2110 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE); 2111 continue; 2112 } 2113 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag, 2114 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE); 2115 2116 ifp->if_ipackets++; 2117 m->m_pkthdr.rcvif = ifp; 2118 m->m_pkthdr.len = m->m_len = total_len; 2119 2120 if (ifp->if_capenable & IFCAP_RXCSUM) { 2121 /* Do IP checksum checking. */ 2122 if (rxstat & XL_RXSTAT_IPCKOK) 2123 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 2124 if (!(rxstat & XL_RXSTAT_IPCKERR)) 2125 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 2126 if ((rxstat & XL_RXSTAT_TCPCOK && 2127 !(rxstat & XL_RXSTAT_TCPCKERR)) || 2128 (rxstat & XL_RXSTAT_UDPCKOK && 2129 !(rxstat & XL_RXSTAT_UDPCKERR))) { 2130 m->m_pkthdr.csum_flags |= 2131 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 2132 m->m_pkthdr.csum_data = 0xffff; 2133 } 2134 } 2135 2136 ifp->if_input(ifp, m); 2137 } 2138 2139 if (sc->xl_type != XL_TYPE_905B) { 2140 /* 2141 * Handle the 'end of channel' condition. When the upload 2142 * engine hits the end of the RX ring, it will stall. This 2143 * is our cue to flush the RX ring, reload the uplist pointer 2144 * register and unstall the engine. 2145 * XXX This is actually a little goofy. With the ThunderLAN 2146 * chip, you get an interrupt when the receiver hits the end 2147 * of the receive ring, which tells you exactly when you 2148 * you need to reload the ring pointer. Here we have to 2149 * fake it. I'm mad at myself for not being clever enough 2150 * to avoid the use of a goto here. 2151 */ 2152 if (CSR_READ_4(sc, XL_UPLIST_PTR) == 0 || 2153 CSR_READ_4(sc, XL_UPLIST_STATUS) & XL_PKTSTAT_UP_STALLED) { 2154 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_STALL); 2155 xl_wait(sc); 2156 CSR_WRITE_4(sc, XL_UPLIST_PTR, 2157 sc->xl_ldata.xl_rx_dmaaddr); 2158 sc->xl_cdata.xl_rx_head = &sc->xl_cdata.xl_rx_chain[0]; 2159 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_UNSTALL); 2160 goto again; 2161 } 2162 } 2163 } 2164 2165 /* 2166 * A frame was downloaded to the chip. It's safe for us to clean up 2167 * the list buffers. 2168 */ 2169 static void 2170 xl_txeof(struct xl_softc *sc) 2171 { 2172 struct xl_chain *cur_tx; 2173 struct ifnet *ifp; 2174 2175 ifp = &sc->arpcom.ac_if; 2176 2177 /* Clear the timeout timer. */ 2178 ifp->if_timer = 0; 2179 2180 /* 2181 * Go through our tx list and free mbufs for those 2182 * frames that have been uploaded. Note: the 3c905B 2183 * sets a special bit in the status word to let us 2184 * know that a frame has been downloaded, but the 2185 * original 3c900/3c905 adapters don't do that. 2186 * Consequently, we have to use a different test if 2187 * xl_type != XL_TYPE_905B. 2188 */ 2189 while(sc->xl_cdata.xl_tx_head != NULL) { 2190 cur_tx = sc->xl_cdata.xl_tx_head; 2191 2192 if (CSR_READ_4(sc, XL_DOWNLIST_PTR)) 2193 break; 2194 2195 sc->xl_cdata.xl_tx_head = cur_tx->xl_next; 2196 bus_dmamap_sync(sc->xl_mtag, cur_tx->xl_map, 2197 BUS_DMASYNC_POSTWRITE); 2198 bus_dmamap_unload(sc->xl_mtag, cur_tx->xl_map); 2199 m_freem(cur_tx->xl_mbuf); 2200 cur_tx->xl_mbuf = NULL; 2201 ifp->if_opackets++; 2202 2203 cur_tx->xl_next = sc->xl_cdata.xl_tx_free; 2204 sc->xl_cdata.xl_tx_free = cur_tx; 2205 } 2206 2207 if (sc->xl_cdata.xl_tx_head == NULL) { 2208 ifp->if_flags &= ~IFF_OACTIVE; 2209 sc->xl_cdata.xl_tx_tail = NULL; 2210 } else { 2211 if (CSR_READ_4(sc, XL_DMACTL) & XL_DMACTL_DOWN_STALLED || 2212 !CSR_READ_4(sc, XL_DOWNLIST_PTR)) { 2213 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, 2214 sc->xl_cdata.xl_tx_head->xl_phys); 2215 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); 2216 } 2217 } 2218 2219 return; 2220 } 2221 2222 static void 2223 xl_txeof_90xB(struct xl_softc *sc) 2224 { 2225 struct xl_chain *cur_tx = NULL; 2226 struct ifnet *ifp; 2227 int idx; 2228 2229 ifp = &sc->arpcom.ac_if; 2230 2231 bus_dmamap_sync(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_dmamap, 2232 BUS_DMASYNC_POSTREAD); 2233 idx = sc->xl_cdata.xl_tx_cons; 2234 while(idx != sc->xl_cdata.xl_tx_prod) { 2235 2236 cur_tx = &sc->xl_cdata.xl_tx_chain[idx]; 2237 2238 if (!(le32toh(cur_tx->xl_ptr->xl_status) & 2239 XL_TXSTAT_DL_COMPLETE)) 2240 break; 2241 2242 if (cur_tx->xl_mbuf != NULL) { 2243 bus_dmamap_sync(sc->xl_mtag, cur_tx->xl_map, 2244 BUS_DMASYNC_POSTWRITE); 2245 bus_dmamap_unload(sc->xl_mtag, cur_tx->xl_map); 2246 m_freem(cur_tx->xl_mbuf); 2247 cur_tx->xl_mbuf = NULL; 2248 } 2249 2250 ifp->if_opackets++; 2251 2252 sc->xl_cdata.xl_tx_cnt--; 2253 XL_INC(idx, XL_TX_LIST_CNT); 2254 ifp->if_timer = 0; 2255 } 2256 2257 sc->xl_cdata.xl_tx_cons = idx; 2258 2259 if (cur_tx != NULL) 2260 ifp->if_flags &= ~IFF_OACTIVE; 2261 2262 return; 2263 } 2264 2265 /* 2266 * TX 'end of channel' interrupt handler. Actually, we should 2267 * only get a 'TX complete' interrupt if there's a transmit error, 2268 * so this is really TX error handler. 2269 */ 2270 static void 2271 xl_txeoc(struct xl_softc *sc) 2272 { 2273 struct ifnet *ifp = &sc->arpcom.ac_if; 2274 u_int8_t txstat; 2275 2276 while((txstat = CSR_READ_1(sc, XL_TX_STATUS))) { 2277 if (txstat & XL_TXSTATUS_UNDERRUN || 2278 txstat & XL_TXSTATUS_JABBER || 2279 txstat & XL_TXSTATUS_RECLAIM) { 2280 if_printf(ifp, "transmission error: %x\n", txstat); 2281 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); 2282 xl_wait(sc); 2283 if (sc->xl_type == XL_TYPE_905B) { 2284 if (sc->xl_cdata.xl_tx_cnt) { 2285 int i; 2286 struct xl_chain *c; 2287 i = sc->xl_cdata.xl_tx_cons; 2288 c = &sc->xl_cdata.xl_tx_chain[i]; 2289 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, 2290 c->xl_phys); 2291 CSR_WRITE_1(sc, XL_DOWN_POLL, 64); 2292 } 2293 } else { 2294 if (sc->xl_cdata.xl_tx_head != NULL) 2295 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, 2296 sc->xl_cdata.xl_tx_head->xl_phys); 2297 } 2298 /* 2299 * Remember to set this for the 2300 * first generation 3c90X chips. 2301 */ 2302 CSR_WRITE_1(sc, XL_TX_FREETHRESH, XL_PACKET_SIZE >> 8); 2303 if (txstat & XL_TXSTATUS_UNDERRUN && 2304 sc->xl_tx_thresh < XL_PACKET_SIZE) { 2305 sc->xl_tx_thresh += XL_MIN_FRAMELEN; 2306 if_printf(ifp, "tx underrun, increasing tx start" 2307 " threshold to %d bytes\n", 2308 sc->xl_tx_thresh); 2309 } 2310 CSR_WRITE_2(sc, XL_COMMAND, 2311 XL_CMD_TX_SET_START|sc->xl_tx_thresh); 2312 if (sc->xl_type == XL_TYPE_905B) { 2313 CSR_WRITE_2(sc, XL_COMMAND, 2314 XL_CMD_SET_TX_RECLAIM|(XL_PACKET_SIZE >> 4)); 2315 } 2316 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE); 2317 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); 2318 } else { 2319 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE); 2320 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); 2321 } 2322 /* 2323 * Write an arbitrary byte to the TX_STATUS register 2324 * to clear this interrupt/error and advance to the next. 2325 */ 2326 CSR_WRITE_1(sc, XL_TX_STATUS, 0x01); 2327 } 2328 2329 return; 2330 } 2331 2332 #ifdef DEVICE_POLLING 2333 2334 static void 2335 xl_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 2336 { 2337 struct xl_softc *sc = ifp->if_softc; 2338 2339 switch (cmd) { 2340 case POLL_REGISTER: 2341 xl_enable_intrs(sc, 0); 2342 break; 2343 case POLL_DEREGISTER: 2344 xl_enable_intrs(sc, XL_INTRS); 2345 break; 2346 case POLL_ONLY: 2347 case POLL_AND_CHECK_STATUS: 2348 xl_rxeof(sc, count); 2349 if (sc->xl_type == XL_TYPE_905B) 2350 xl_txeof_90xB(sc); 2351 else 2352 xl_txeof(sc); 2353 2354 if (!ifq_is_empty(&ifp->if_snd)) { 2355 if (sc->xl_type == XL_TYPE_905B) 2356 xl_start_90xB(ifp); 2357 else 2358 xl_start_body(ifp, 0); 2359 } 2360 2361 if (cmd == POLL_AND_CHECK_STATUS) { 2362 uint16_t status; 2363 2364 /* XXX copy & pasted from xl_intr() */ 2365 status = CSR_READ_2(sc, XL_STATUS); 2366 if ((status & XL_INTRS) && status != 0xFFFF) { 2367 CSR_WRITE_2(sc, XL_COMMAND, 2368 XL_CMD_INTR_ACK | (status & XL_INTRS)); 2369 2370 if (status & XL_STAT_TX_COMPLETE) { 2371 ifp->if_oerrors++; 2372 xl_txeoc(sc); 2373 } 2374 2375 if (status & XL_STAT_ADFAIL) { 2376 xl_reset(sc); 2377 xl_init(sc); 2378 } 2379 2380 if (status & XL_STAT_STATSOFLOW) { 2381 sc->xl_stats_no_timeout = 1; 2382 xl_stats_update_serialized(sc); 2383 sc->xl_stats_no_timeout = 0; 2384 } 2385 } 2386 } 2387 break; 2388 } 2389 } 2390 2391 #endif /* DEVICE_POLLING */ 2392 2393 static void 2394 xl_intr(void *arg) 2395 { 2396 struct xl_softc *sc; 2397 struct ifnet *ifp; 2398 u_int16_t status; 2399 2400 sc = arg; 2401 ifp = &sc->arpcom.ac_if; 2402 2403 while(((status = CSR_READ_2(sc, XL_STATUS)) & XL_INTRS) && 2404 status != 0xFFFF) { 2405 2406 CSR_WRITE_2(sc, XL_COMMAND, 2407 XL_CMD_INTR_ACK|(status & XL_INTRS)); 2408 2409 if (status & XL_STAT_UP_COMPLETE) { 2410 int curpkts; 2411 2412 curpkts = ifp->if_ipackets; 2413 xl_rxeof(sc, -1); 2414 if (curpkts == ifp->if_ipackets) { 2415 while (xl_rx_resync(sc)) 2416 xl_rxeof(sc, -1); 2417 } 2418 } 2419 2420 if (status & XL_STAT_DOWN_COMPLETE) { 2421 if (sc->xl_type == XL_TYPE_905B) 2422 xl_txeof_90xB(sc); 2423 else 2424 xl_txeof(sc); 2425 } 2426 2427 if (status & XL_STAT_TX_COMPLETE) { 2428 ifp->if_oerrors++; 2429 xl_txeoc(sc); 2430 } 2431 2432 if (status & XL_STAT_ADFAIL) { 2433 xl_reset(sc); 2434 xl_init(sc); 2435 } 2436 2437 if (status & XL_STAT_STATSOFLOW) { 2438 sc->xl_stats_no_timeout = 1; 2439 xl_stats_update_serialized(sc); 2440 sc->xl_stats_no_timeout = 0; 2441 } 2442 } 2443 2444 if (!ifq_is_empty(&ifp->if_snd)) 2445 (*ifp->if_start)(ifp); 2446 2447 return; 2448 } 2449 2450 static void 2451 xl_stats_update(void *xsc) 2452 { 2453 struct xl_softc *sc = xsc; 2454 2455 lwkt_serialize_enter(sc->arpcom.ac_if.if_serializer); 2456 xl_stats_update_serialized(xsc); 2457 lwkt_serialize_exit(sc->arpcom.ac_if.if_serializer); 2458 } 2459 2460 static void 2461 xl_stats_update_serialized(void *xsc) 2462 { 2463 struct xl_softc *sc; 2464 struct ifnet *ifp; 2465 struct xl_stats xl_stats; 2466 u_int8_t *p; 2467 int i; 2468 struct mii_data *mii = NULL; 2469 2470 bzero((char *)&xl_stats, sizeof(struct xl_stats)); 2471 2472 sc = xsc; 2473 ifp = &sc->arpcom.ac_if; 2474 if (sc->xl_miibus != NULL) 2475 mii = device_get_softc(sc->xl_miibus); 2476 2477 p = (u_int8_t *)&xl_stats; 2478 2479 /* Read all the stats registers. */ 2480 XL_SEL_WIN(6); 2481 2482 for (i = 0; i < 16; i++) 2483 *p++ = CSR_READ_1(sc, XL_W6_CARRIER_LOST + i); 2484 2485 ifp->if_ierrors += xl_stats.xl_rx_overrun; 2486 2487 ifp->if_collisions += xl_stats.xl_tx_multi_collision + 2488 xl_stats.xl_tx_single_collision + 2489 xl_stats.xl_tx_late_collision; 2490 2491 /* 2492 * Boomerang and cyclone chips have an extra stats counter 2493 * in window 4 (BadSSD). We have to read this too in order 2494 * to clear out all the stats registers and avoid a statsoflow 2495 * interrupt. 2496 */ 2497 XL_SEL_WIN(4); 2498 CSR_READ_1(sc, XL_W4_BADSSD); 2499 2500 if ((mii != NULL) && (!sc->xl_stats_no_timeout)) 2501 mii_tick(mii); 2502 2503 XL_SEL_WIN(7); 2504 2505 if (!sc->xl_stats_no_timeout) 2506 callout_reset(&sc->xl_stat_timer, hz, xl_stats_update, sc); 2507 2508 return; 2509 } 2510 2511 /* 2512 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 2513 * pointers to the fragment pointers. 2514 */ 2515 static int 2516 xl_encap(struct xl_softc *sc, struct xl_chain *c, struct mbuf *m_head) 2517 { 2518 int error; 2519 u_int32_t status; 2520 struct ifnet *ifp; 2521 2522 ifp = &sc->arpcom.ac_if; 2523 2524 /* 2525 * Start packing the mbufs in this chain into 2526 * the fragment pointers. Stop when we run out 2527 * of fragments or hit the end of the mbuf chain. 2528 */ 2529 error = bus_dmamap_load_mbuf(sc->xl_mtag, c->xl_map, m_head, 2530 xl_dma_map_txbuf, c->xl_ptr, BUS_DMA_NOWAIT); 2531 2532 if (error && error != EFBIG) { 2533 m_freem(m_head); 2534 if_printf(ifp, "can't map mbuf (error %d)\n", error); 2535 return(1); 2536 } 2537 2538 /* 2539 * Handle special case: we used up all 63 fragments, 2540 * but we have more mbufs left in the chain. Copy the 2541 * data into an mbuf cluster. Note that we don't 2542 * bother clearing the values in the other fragment 2543 * pointers/counters; it wouldn't gain us anything, 2544 * and would waste cycles. 2545 */ 2546 if (error) { 2547 struct mbuf *m_new; 2548 2549 m_new = m_defrag(m_head, MB_DONTWAIT); 2550 if (m_new == NULL) { 2551 m_freem(m_head); 2552 return(1); 2553 } else { 2554 m_head = m_new; 2555 } 2556 2557 error = bus_dmamap_load_mbuf(sc->xl_mtag, c->xl_map, 2558 m_head, xl_dma_map_txbuf, c->xl_ptr, BUS_DMA_NOWAIT); 2559 if (error) { 2560 m_freem(m_head); 2561 if_printf(ifp, "can't map mbuf (error %d)\n", error); 2562 return(1); 2563 } 2564 } 2565 2566 if (sc->xl_type == XL_TYPE_905B) { 2567 status = XL_TXSTAT_RND_DEFEAT; 2568 2569 if (m_head->m_pkthdr.csum_flags) { 2570 if (m_head->m_pkthdr.csum_flags & CSUM_IP) 2571 status |= XL_TXSTAT_IPCKSUM; 2572 if (m_head->m_pkthdr.csum_flags & CSUM_TCP) 2573 status |= XL_TXSTAT_TCPCKSUM; 2574 if (m_head->m_pkthdr.csum_flags & CSUM_UDP) 2575 status |= XL_TXSTAT_UDPCKSUM; 2576 } 2577 c->xl_ptr->xl_status = htole32(status); 2578 } 2579 2580 c->xl_mbuf = m_head; 2581 bus_dmamap_sync(sc->xl_mtag, c->xl_map, BUS_DMASYNC_PREWRITE); 2582 return(0); 2583 } 2584 2585 static void 2586 xl_start(struct ifnet *ifp) 2587 { 2588 xl_start_body(ifp, 1); 2589 } 2590 2591 /* 2592 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 2593 * to the mbuf data regions directly in the transmit lists. We also save a 2594 * copy of the pointers since the transmit list fragment pointers are 2595 * physical addresses. 2596 */ 2597 static void 2598 xl_start_body(struct ifnet *ifp, int proc_rx) 2599 { 2600 struct xl_softc *sc; 2601 struct mbuf *m_head = NULL; 2602 struct xl_chain *prev = NULL, *cur_tx = NULL, *start_tx; 2603 struct xl_chain *prev_tx; 2604 u_int32_t status; 2605 int error; 2606 2607 sc = ifp->if_softc; 2608 /* 2609 * Check for an available queue slot. If there are none, 2610 * punt. 2611 */ 2612 if (sc->xl_cdata.xl_tx_free == NULL) { 2613 xl_txeoc(sc); 2614 xl_txeof(sc); 2615 if (sc->xl_cdata.xl_tx_free == NULL) { 2616 ifp->if_flags |= IFF_OACTIVE; 2617 return; 2618 } 2619 } 2620 2621 start_tx = sc->xl_cdata.xl_tx_free; 2622 2623 while(sc->xl_cdata.xl_tx_free != NULL) { 2624 m_head = ifq_dequeue(&ifp->if_snd, NULL); 2625 if (m_head == NULL) 2626 break; 2627 2628 /* Pick a descriptor off the free list. */ 2629 prev_tx = cur_tx; 2630 cur_tx = sc->xl_cdata.xl_tx_free; 2631 2632 /* Pack the data into the descriptor. */ 2633 error = xl_encap(sc, cur_tx, m_head); 2634 if (error) { 2635 cur_tx = prev_tx; 2636 continue; 2637 } 2638 2639 sc->xl_cdata.xl_tx_free = cur_tx->xl_next; 2640 cur_tx->xl_next = NULL; 2641 2642 /* Chain it together. */ 2643 if (prev != NULL) { 2644 prev->xl_next = cur_tx; 2645 prev->xl_ptr->xl_next = htole32(cur_tx->xl_phys); 2646 } 2647 prev = cur_tx; 2648 2649 BPF_MTAP(ifp, cur_tx->xl_mbuf); 2650 } 2651 2652 /* 2653 * If there are no packets queued, bail. 2654 */ 2655 if (cur_tx == NULL) 2656 return; 2657 2658 /* 2659 * Place the request for the upload interrupt 2660 * in the last descriptor in the chain. This way, if 2661 * we're chaining several packets at once, we'll only 2662 * get an interupt once for the whole chain rather than 2663 * once for each packet. 2664 */ 2665 cur_tx->xl_ptr->xl_status = htole32(le32toh(cur_tx->xl_ptr->xl_status) | 2666 XL_TXSTAT_DL_INTR); 2667 2668 /* 2669 * Queue the packets. If the TX channel is clear, update 2670 * the downlist pointer register. 2671 */ 2672 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_STALL); 2673 xl_wait(sc); 2674 2675 if (sc->xl_cdata.xl_tx_head != NULL) { 2676 sc->xl_cdata.xl_tx_tail->xl_next = start_tx; 2677 sc->xl_cdata.xl_tx_tail->xl_ptr->xl_next = 2678 htole32(start_tx->xl_phys); 2679 status = sc->xl_cdata.xl_tx_tail->xl_ptr->xl_status; 2680 sc->xl_cdata.xl_tx_tail->xl_ptr->xl_status = 2681 htole32(le32toh(status) & ~XL_TXSTAT_DL_INTR); 2682 sc->xl_cdata.xl_tx_tail = cur_tx; 2683 } else { 2684 sc->xl_cdata.xl_tx_head = start_tx; 2685 sc->xl_cdata.xl_tx_tail = cur_tx; 2686 } 2687 bus_dmamap_sync(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_dmamap, 2688 BUS_DMASYNC_PREWRITE); 2689 2690 if (!CSR_READ_4(sc, XL_DOWNLIST_PTR)) 2691 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, start_tx->xl_phys); 2692 2693 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); 2694 2695 XL_SEL_WIN(7); 2696 2697 /* 2698 * Set a timeout in case the chip goes out to lunch. 2699 */ 2700 ifp->if_timer = 5; 2701 2702 if (proc_rx) { 2703 /* 2704 * XXX Under certain conditions, usually on slower machines 2705 * where interrupts may be dropped, it's possible for the 2706 * adapter to chew up all the buffers in the receive ring 2707 * and stall, without us being able to do anything about it. 2708 * To guard against this, we need to make a pass over the 2709 * RX queue to make sure there aren't any packets pending. 2710 * Doing it here means we can flush the receive ring at the 2711 * same time the chip is DMAing the transmit descriptors we 2712 * just gave it. 2713 * 2714 * 3Com goes to some lengths to emphasize the Parallel 2715 * Tasking (tm) nature of their chips in all their marketing 2716 * literature; we may as well take advantage of it. :) 2717 */ 2718 xl_rxeof(sc, -1); 2719 } 2720 } 2721 2722 static void 2723 xl_start_90xB(struct ifnet *ifp) 2724 { 2725 struct xl_softc *sc; 2726 struct mbuf *m_head = NULL; 2727 struct xl_chain *prev = NULL, *cur_tx = NULL, *start_tx; 2728 struct xl_chain *prev_tx; 2729 int error, idx; 2730 2731 sc = ifp->if_softc; 2732 2733 if (ifp->if_flags & IFF_OACTIVE) 2734 return; 2735 2736 idx = sc->xl_cdata.xl_tx_prod; 2737 start_tx = &sc->xl_cdata.xl_tx_chain[idx]; 2738 2739 while (sc->xl_cdata.xl_tx_chain[idx].xl_mbuf == NULL) { 2740 2741 if ((XL_TX_LIST_CNT - sc->xl_cdata.xl_tx_cnt) < 3) { 2742 ifp->if_flags |= IFF_OACTIVE; 2743 break; 2744 } 2745 2746 m_head = ifq_dequeue(&ifp->if_snd, NULL); 2747 if (m_head == NULL) 2748 break; 2749 2750 prev_tx = cur_tx; 2751 cur_tx = &sc->xl_cdata.xl_tx_chain[idx]; 2752 2753 /* Pack the data into the descriptor. */ 2754 error = xl_encap(sc, cur_tx, m_head); 2755 if (error) { 2756 cur_tx = prev_tx; 2757 continue; 2758 } 2759 2760 /* Chain it together. */ 2761 if (prev != NULL) 2762 prev->xl_ptr->xl_next = htole32(cur_tx->xl_phys); 2763 prev = cur_tx; 2764 2765 BPF_MTAP(ifp, cur_tx->xl_mbuf); 2766 2767 XL_INC(idx, XL_TX_LIST_CNT); 2768 sc->xl_cdata.xl_tx_cnt++; 2769 } 2770 2771 /* 2772 * If there are no packets queued, bail. 2773 */ 2774 if (cur_tx == NULL) 2775 return; 2776 2777 /* 2778 * Place the request for the upload interrupt 2779 * in the last descriptor in the chain. This way, if 2780 * we're chaining several packets at once, we'll only 2781 * get an interupt once for the whole chain rather than 2782 * once for each packet. 2783 */ 2784 cur_tx->xl_ptr->xl_status = htole32(le32toh(cur_tx->xl_ptr->xl_status) | 2785 XL_TXSTAT_DL_INTR); 2786 2787 /* Start transmission */ 2788 sc->xl_cdata.xl_tx_prod = idx; 2789 start_tx->xl_prev->xl_ptr->xl_next = htole32(start_tx->xl_phys); 2790 2791 bus_dmamap_sync(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_dmamap, 2792 BUS_DMASYNC_PREWRITE); 2793 2794 /* 2795 * Set a timeout in case the chip goes out to lunch. 2796 */ 2797 ifp->if_timer = 5; 2798 } 2799 2800 static void 2801 xl_init(void *xsc) 2802 { 2803 struct xl_softc *sc = xsc; 2804 struct ifnet *ifp = &sc->arpcom.ac_if; 2805 int error, i; 2806 u_int16_t rxfilt = 0; 2807 struct mii_data *mii = NULL; 2808 2809 /* 2810 * Cancel pending I/O and free all RX/TX buffers. 2811 */ 2812 xl_stop(sc); 2813 2814 if (sc->xl_miibus == NULL) { 2815 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET); 2816 xl_wait(sc); 2817 } 2818 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); 2819 xl_wait(sc); 2820 DELAY(10000); 2821 2822 if (sc->xl_miibus != NULL) 2823 mii = device_get_softc(sc->xl_miibus); 2824 2825 /* Init our MAC address */ 2826 XL_SEL_WIN(2); 2827 for (i = 0; i < ETHER_ADDR_LEN; i++) { 2828 CSR_WRITE_1(sc, XL_W2_STATION_ADDR_LO + i, 2829 sc->arpcom.ac_enaddr[i]); 2830 } 2831 2832 /* Clear the station mask. */ 2833 for (i = 0; i < 3; i++) 2834 CSR_WRITE_2(sc, XL_W2_STATION_MASK_LO + (i * 2), 0); 2835 #ifdef notdef 2836 /* Reset TX and RX. */ 2837 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET); 2838 xl_wait(sc); 2839 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); 2840 xl_wait(sc); 2841 #endif 2842 /* Init circular RX list. */ 2843 error = xl_list_rx_init(sc); 2844 if (error) { 2845 if_printf(ifp, "initialization of the rx ring failed (%d)\n", 2846 error); 2847 xl_stop(sc); 2848 return; 2849 } 2850 2851 /* Init TX descriptors. */ 2852 if (sc->xl_type == XL_TYPE_905B) 2853 xl_list_tx_init_90xB(sc); 2854 else 2855 xl_list_tx_init(sc); 2856 2857 /* 2858 * Set the TX freethresh value. 2859 * Note that this has no effect on 3c905B "cyclone" 2860 * cards but is required for 3c900/3c905 "boomerang" 2861 * cards in order to enable the download engine. 2862 */ 2863 CSR_WRITE_1(sc, XL_TX_FREETHRESH, XL_PACKET_SIZE >> 8); 2864 2865 /* Set the TX start threshold for best performance. */ 2866 sc->xl_tx_thresh = XL_MIN_FRAMELEN; 2867 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_SET_START|sc->xl_tx_thresh); 2868 2869 /* 2870 * If this is a 3c905B, also set the tx reclaim threshold. 2871 * This helps cut down on the number of tx reclaim errors 2872 * that could happen on a busy network. The chip multiplies 2873 * the register value by 16 to obtain the actual threshold 2874 * in bytes, so we divide by 16 when setting the value here. 2875 * The existing threshold value can be examined by reading 2876 * the register at offset 9 in window 5. 2877 */ 2878 if (sc->xl_type == XL_TYPE_905B) { 2879 CSR_WRITE_2(sc, XL_COMMAND, 2880 XL_CMD_SET_TX_RECLAIM|(XL_PACKET_SIZE >> 4)); 2881 } 2882 2883 /* Set RX filter bits. */ 2884 XL_SEL_WIN(5); 2885 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER); 2886 2887 /* Set the individual bit to receive frames for this host only. */ 2888 rxfilt |= XL_RXFILTER_INDIVIDUAL; 2889 2890 /* If we want promiscuous mode, set the allframes bit. */ 2891 if (ifp->if_flags & IFF_PROMISC) { 2892 rxfilt |= XL_RXFILTER_ALLFRAMES; 2893 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 2894 } else { 2895 rxfilt &= ~XL_RXFILTER_ALLFRAMES; 2896 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 2897 } 2898 2899 /* 2900 * Set capture broadcast bit to capture broadcast frames. 2901 */ 2902 if (ifp->if_flags & IFF_BROADCAST) { 2903 rxfilt |= XL_RXFILTER_BROADCAST; 2904 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 2905 } else { 2906 rxfilt &= ~XL_RXFILTER_BROADCAST; 2907 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 2908 } 2909 2910 /* 2911 * Program the multicast filter, if necessary. 2912 */ 2913 if (sc->xl_type == XL_TYPE_905B) 2914 xl_setmulti_hash(sc); 2915 else 2916 xl_setmulti(sc); 2917 2918 if (sc->xl_type == XL_TYPE_905B) { 2919 /* Set UP polling interval */ 2920 CSR_WRITE_1(sc, XL_UP_POLL, 64); 2921 } 2922 2923 /* 2924 * Load the address of the RX list. We have to 2925 * stall the upload engine before we can manipulate 2926 * the uplist pointer register, then unstall it when 2927 * we're finished. We also have to wait for the 2928 * stall command to complete before proceeding. 2929 * Note that we have to do this after any RX resets 2930 * have completed since the uplist register is cleared 2931 * by a reset. 2932 */ 2933 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_STALL); 2934 xl_wait(sc); 2935 CSR_WRITE_4(sc, XL_UPLIST_PTR, sc->xl_ldata.xl_rx_dmaaddr); 2936 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_UNSTALL); 2937 xl_wait(sc); 2938 2939 if (sc->xl_type == XL_TYPE_905B) { 2940 /* Set DN polling interval */ 2941 CSR_WRITE_1(sc, XL_DOWN_POLL, 64); 2942 2943 /* Load the address of the TX list */ 2944 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_STALL); 2945 xl_wait(sc); 2946 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, 2947 sc->xl_cdata.xl_tx_chain[0].xl_phys); 2948 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); 2949 xl_wait(sc); 2950 } 2951 2952 /* 2953 * If the coax transceiver is on, make sure to enable 2954 * the DC-DC converter. 2955 */ 2956 XL_SEL_WIN(3); 2957 if (sc->xl_xcvr == XL_XCVR_COAX) 2958 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_START); 2959 else 2960 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP); 2961 2962 /* 2963 * increase packet size to allow reception of 802.1q or ISL packets. 2964 * For the 3c90x chip, set the 'allow large packets' bit in the MAC 2965 * control register. For 3c90xB/C chips, use the RX packet size 2966 * register. 2967 */ 2968 2969 if (sc->xl_type == XL_TYPE_905B) { 2970 CSR_WRITE_2(sc, XL_W3_MAXPKTSIZE, XL_PACKET_SIZE); 2971 } else { 2972 u_int8_t macctl; 2973 macctl = CSR_READ_1(sc, XL_W3_MAC_CTRL); 2974 macctl |= XL_MACCTRL_ALLOW_LARGE_PACK; 2975 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, macctl); 2976 } 2977 2978 /* Clear out the stats counters. */ 2979 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_DISABLE); 2980 sc->xl_stats_no_timeout = 1; 2981 xl_stats_update_serialized(sc); 2982 sc->xl_stats_no_timeout = 0; 2983 XL_SEL_WIN(4); 2984 CSR_WRITE_2(sc, XL_W4_NET_DIAG, XL_NETDIAG_UPPER_BYTES_ENABLE); 2985 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_ENABLE); 2986 2987 /* 2988 * Enable interrupts. 2989 */ 2990 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STAT_ENB | XL_INTRS); 2991 #ifdef DEVICE_POLLING 2992 /* Do not enable interrupt if polling(4) is enabled */ 2993 if ((ifp->if_flags & IFF_POLLING) != 0) 2994 xl_enable_intrs(sc, 0); 2995 else 2996 #endif 2997 xl_enable_intrs(sc, XL_INTRS); 2998 2999 /* Set the RX early threshold */ 3000 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_THRESH|(XL_PACKET_SIZE >>2)); 3001 CSR_WRITE_2(sc, XL_DMACTL, XL_DMACTL_UP_RX_EARLY); 3002 3003 /* Enable receiver and transmitter. */ 3004 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE); 3005 xl_wait(sc); 3006 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_ENABLE); 3007 xl_wait(sc); 3008 3009 if (mii != NULL) 3010 mii_mediachg(mii); 3011 3012 /* Select window 7 for normal operations. */ 3013 XL_SEL_WIN(7); 3014 3015 ifp->if_flags |= IFF_RUNNING; 3016 ifp->if_flags &= ~IFF_OACTIVE; 3017 3018 callout_reset(&sc->xl_stat_timer, hz, xl_stats_update, sc); 3019 } 3020 3021 /* 3022 * Set media options. 3023 */ 3024 static int 3025 xl_ifmedia_upd(struct ifnet *ifp) 3026 { 3027 struct xl_softc *sc; 3028 struct ifmedia *ifm = NULL; 3029 struct mii_data *mii = NULL; 3030 3031 sc = ifp->if_softc; 3032 if (sc->xl_miibus != NULL) 3033 mii = device_get_softc(sc->xl_miibus); 3034 if (mii == NULL) 3035 ifm = &sc->ifmedia; 3036 else 3037 ifm = &mii->mii_media; 3038 3039 switch(IFM_SUBTYPE(ifm->ifm_media)) { 3040 case IFM_100_FX: 3041 case IFM_10_FL: 3042 case IFM_10_2: 3043 case IFM_10_5: 3044 xl_setmode(sc, ifm->ifm_media); 3045 return(0); 3046 break; 3047 default: 3048 break; 3049 } 3050 3051 if (sc->xl_media & XL_MEDIAOPT_MII || sc->xl_media & XL_MEDIAOPT_BTX 3052 || sc->xl_media & XL_MEDIAOPT_BT4) { 3053 xl_init(sc); 3054 } else { 3055 xl_setmode(sc, ifm->ifm_media); 3056 } 3057 3058 return(0); 3059 } 3060 3061 /* 3062 * Report current media status. 3063 */ 3064 static void 3065 xl_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 3066 { 3067 struct xl_softc *sc; 3068 u_int32_t icfg; 3069 struct mii_data *mii = NULL; 3070 3071 sc = ifp->if_softc; 3072 if (sc->xl_miibus != NULL) 3073 mii = device_get_softc(sc->xl_miibus); 3074 3075 XL_SEL_WIN(3); 3076 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG) & XL_ICFG_CONNECTOR_MASK; 3077 icfg >>= XL_ICFG_CONNECTOR_BITS; 3078 3079 ifmr->ifm_active = IFM_ETHER; 3080 3081 switch(icfg) { 3082 case XL_XCVR_10BT: 3083 ifmr->ifm_active = IFM_ETHER|IFM_10_T; 3084 if (CSR_READ_1(sc, XL_W3_MAC_CTRL) & XL_MACCTRL_DUPLEX) 3085 ifmr->ifm_active |= IFM_FDX; 3086 else 3087 ifmr->ifm_active |= IFM_HDX; 3088 break; 3089 case XL_XCVR_AUI: 3090 if (sc->xl_type == XL_TYPE_905B && 3091 sc->xl_media == XL_MEDIAOPT_10FL) { 3092 ifmr->ifm_active = IFM_ETHER|IFM_10_FL; 3093 if (CSR_READ_1(sc, XL_W3_MAC_CTRL) & XL_MACCTRL_DUPLEX) 3094 ifmr->ifm_active |= IFM_FDX; 3095 else 3096 ifmr->ifm_active |= IFM_HDX; 3097 } else 3098 ifmr->ifm_active = IFM_ETHER|IFM_10_5; 3099 break; 3100 case XL_XCVR_COAX: 3101 ifmr->ifm_active = IFM_ETHER|IFM_10_2; 3102 break; 3103 /* 3104 * XXX MII and BTX/AUTO should be separate cases. 3105 */ 3106 3107 case XL_XCVR_100BTX: 3108 case XL_XCVR_AUTO: 3109 case XL_XCVR_MII: 3110 if (mii != NULL) { 3111 mii_pollstat(mii); 3112 ifmr->ifm_active = mii->mii_media_active; 3113 ifmr->ifm_status = mii->mii_media_status; 3114 } 3115 break; 3116 case XL_XCVR_100BFX: 3117 ifmr->ifm_active = IFM_ETHER|IFM_100_FX; 3118 break; 3119 default: 3120 if_printf(ifp, "unknown XCVR type: %d\n", icfg); 3121 break; 3122 } 3123 3124 return; 3125 } 3126 3127 static int 3128 xl_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr) 3129 { 3130 struct xl_softc *sc = ifp->if_softc; 3131 struct ifreq *ifr = (struct ifreq *) data; 3132 int error = 0; 3133 struct mii_data *mii = NULL; 3134 u_int8_t rxfilt; 3135 3136 switch(command) { 3137 case SIOCSIFFLAGS: 3138 XL_SEL_WIN(5); 3139 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER); 3140 if (ifp->if_flags & IFF_UP) { 3141 if (ifp->if_flags & IFF_RUNNING && 3142 ifp->if_flags & IFF_PROMISC && 3143 !(sc->xl_if_flags & IFF_PROMISC)) { 3144 rxfilt |= XL_RXFILTER_ALLFRAMES; 3145 CSR_WRITE_2(sc, XL_COMMAND, 3146 XL_CMD_RX_SET_FILT|rxfilt); 3147 XL_SEL_WIN(7); 3148 } else if (ifp->if_flags & IFF_RUNNING && 3149 !(ifp->if_flags & IFF_PROMISC) && 3150 sc->xl_if_flags & IFF_PROMISC) { 3151 rxfilt &= ~XL_RXFILTER_ALLFRAMES; 3152 CSR_WRITE_2(sc, XL_COMMAND, 3153 XL_CMD_RX_SET_FILT|rxfilt); 3154 XL_SEL_WIN(7); 3155 } else 3156 xl_init(sc); 3157 } else { 3158 if (ifp->if_flags & IFF_RUNNING) 3159 xl_stop(sc); 3160 } 3161 sc->xl_if_flags = ifp->if_flags; 3162 error = 0; 3163 break; 3164 case SIOCADDMULTI: 3165 case SIOCDELMULTI: 3166 if (sc->xl_type == XL_TYPE_905B) 3167 xl_setmulti_hash(sc); 3168 else 3169 xl_setmulti(sc); 3170 error = 0; 3171 break; 3172 case SIOCGIFMEDIA: 3173 case SIOCSIFMEDIA: 3174 if (sc->xl_miibus != NULL) 3175 mii = device_get_softc(sc->xl_miibus); 3176 if (mii == NULL) 3177 error = ifmedia_ioctl(ifp, ifr, 3178 &sc->ifmedia, command); 3179 else 3180 error = ifmedia_ioctl(ifp, ifr, 3181 &mii->mii_media, command); 3182 break; 3183 case SIOCSIFCAP: 3184 ifp->if_capenable = ifr->ifr_reqcap; 3185 if (ifp->if_capenable & IFCAP_TXCSUM) 3186 ifp->if_hwassist = XL905B_CSUM_FEATURES; 3187 else 3188 ifp->if_hwassist = 0; 3189 break; 3190 default: 3191 error = ether_ioctl(ifp, command, data); 3192 break; 3193 } 3194 return(error); 3195 } 3196 3197 static void 3198 xl_watchdog(struct ifnet *ifp) 3199 { 3200 struct xl_softc *sc; 3201 u_int16_t status = 0; 3202 3203 sc = ifp->if_softc; 3204 3205 ifp->if_oerrors++; 3206 XL_SEL_WIN(4); 3207 status = CSR_READ_2(sc, XL_W4_MEDIA_STATUS); 3208 if_printf(ifp, "watchdog timeout\n"); 3209 3210 if (status & XL_MEDIASTAT_CARRIER) 3211 if_printf(ifp, "no carrier - transceiver cable problem?\n"); 3212 xl_txeoc(sc); 3213 xl_txeof(sc); 3214 xl_rxeof(sc, -1); 3215 xl_reset(sc); 3216 xl_init(sc); 3217 3218 if (!ifq_is_empty(&ifp->if_snd)) 3219 (*ifp->if_start)(ifp); 3220 } 3221 3222 /* 3223 * Stop the adapter and free any mbufs allocated to the 3224 * RX and TX lists. 3225 */ 3226 static void 3227 xl_stop(struct xl_softc *sc) 3228 { 3229 int i; 3230 struct ifnet *ifp; 3231 3232 ifp = &sc->arpcom.ac_if; 3233 ifp->if_timer = 0; 3234 3235 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_DISABLE); 3236 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_DISABLE); 3237 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB); 3238 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_DISCARD); 3239 xl_wait(sc); 3240 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_DISABLE); 3241 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP); 3242 DELAY(800); 3243 3244 #ifdef foo 3245 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET); 3246 xl_wait(sc); 3247 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); 3248 xl_wait(sc); 3249 #endif 3250 3251 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ACK|XL_STAT_INTLATCH); 3252 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STAT_ENB|0); 3253 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|0); 3254 if (sc->xl_flags & XL_FLAG_FUNCREG) 3255 bus_space_write_4(sc->xl_ftag, sc->xl_fhandle, 4, 0x8000); 3256 3257 /* Stop the stats updater. */ 3258 callout_stop(&sc->xl_stat_timer); 3259 3260 /* 3261 * Free data in the RX lists. 3262 */ 3263 for (i = 0; i < XL_RX_LIST_CNT; i++) { 3264 if (sc->xl_cdata.xl_rx_chain[i].xl_mbuf != NULL) { 3265 bus_dmamap_unload(sc->xl_mtag, 3266 sc->xl_cdata.xl_rx_chain[i].xl_map); 3267 m_freem(sc->xl_cdata.xl_rx_chain[i].xl_mbuf); 3268 sc->xl_cdata.xl_rx_chain[i].xl_mbuf = NULL; 3269 } 3270 } 3271 bzero(sc->xl_ldata.xl_rx_list, XL_RX_LIST_SZ); 3272 3273 /* 3274 * Free the TX list buffers. 3275 */ 3276 for (i = 0; i < XL_TX_LIST_CNT; i++) { 3277 if (sc->xl_cdata.xl_tx_chain[i].xl_mbuf != NULL) { 3278 bus_dmamap_unload(sc->xl_mtag, 3279 sc->xl_cdata.xl_tx_chain[i].xl_map); 3280 m_freem(sc->xl_cdata.xl_tx_chain[i].xl_mbuf); 3281 sc->xl_cdata.xl_tx_chain[i].xl_mbuf = NULL; 3282 } 3283 } 3284 bzero(sc->xl_ldata.xl_tx_list, XL_TX_LIST_SZ); 3285 3286 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 3287 } 3288 3289 /* 3290 * Stop all chip I/O so that the kernel's probe routines don't 3291 * get confused by errant DMAs when rebooting. 3292 */ 3293 static void 3294 xl_shutdown(device_t dev) 3295 { 3296 struct xl_softc *sc = device_get_softc(dev); 3297 3298 lwkt_serialize_enter(sc->arpcom.ac_if.if_serializer); 3299 xl_reset(sc); 3300 xl_stop(sc); 3301 lwkt_serialize_exit(sc->arpcom.ac_if.if_serializer); 3302 } 3303 3304 static int 3305 xl_suspend(device_t dev) 3306 { 3307 struct xl_softc *sc = device_get_softc(dev); 3308 3309 lwkt_serialize_enter(sc->arpcom.ac_if.if_serializer); 3310 xl_stop(sc); 3311 lwkt_serialize_exit(sc->arpcom.ac_if.if_serializer); 3312 3313 return(0); 3314 } 3315 3316 static int 3317 xl_resume(device_t dev) 3318 { 3319 struct xl_softc *sc; 3320 struct ifnet *ifp; 3321 3322 sc = device_get_softc(dev); 3323 ifp = &sc->arpcom.ac_if; 3324 3325 lwkt_serialize_enter(ifp->if_serializer); 3326 xl_reset(sc); 3327 if (ifp->if_flags & IFF_UP) 3328 xl_init(sc); 3329 lwkt_serialize_exit(ifp->if_serializer); 3330 3331 return(0); 3332 } 3333