1 /* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: src/sys/pci/if_xl.c,v 1.72.2.28 2003/10/08 06:01:57 murray Exp $ 33 * $DragonFly: src/sys/dev/netif/xl/if_xl.c,v 1.54 2008/08/17 04:32:35 sephe Exp $ 34 */ 35 36 /* 37 * 3Com 3c90x Etherlink XL PCI NIC driver 38 * 39 * Supports the 3Com "boomerang", "cyclone" and "hurricane" PCI 40 * bus-master chips (3c90x cards and embedded controllers) including 41 * the following: 42 * 43 * 3Com 3c900-TPO 10Mbps/RJ-45 44 * 3Com 3c900-COMBO 10Mbps/RJ-45,AUI,BNC 45 * 3Com 3c905-TX 10/100Mbps/RJ-45 46 * 3Com 3c905-T4 10/100Mbps/RJ-45 47 * 3Com 3c900B-TPO 10Mbps/RJ-45 48 * 3Com 3c900B-COMBO 10Mbps/RJ-45,AUI,BNC 49 * 3Com 3c900B-TPC 10Mbps/RJ-45,BNC 50 * 3Com 3c900B-FL 10Mbps/Fiber-optic 51 * 3Com 3c905B-COMBO 10/100Mbps/RJ-45,AUI,BNC 52 * 3Com 3c905B-TX 10/100Mbps/RJ-45 53 * 3Com 3c905B-FL/FX 10/100Mbps/Fiber-optic 54 * 3Com 3c905C-TX 10/100Mbps/RJ-45 (Tornado ASIC) 55 * 3Com 3c980-TX 10/100Mbps server adapter (Hurricane ASIC) 56 * 3Com 3c980C-TX 10/100Mbps server adapter (Tornado ASIC) 57 * 3Com 3cSOHO100-TX 10/100Mbps/RJ-45 (Hurricane ASIC) 58 * 3Com 3c450-TX 10/100Mbps/RJ-45 (Tornado ASIC) 59 * 3Com 3c555 10/100Mbps/RJ-45 (MiniPCI, Laptop Hurricane) 60 * 3Com 3c556 10/100Mbps/RJ-45 (MiniPCI, Hurricane ASIC) 61 * 3Com 3c556B 10/100Mbps/RJ-45 (MiniPCI, Hurricane ASIC) 62 * 3Com 3c575TX 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC) 63 * 3Com 3c575B 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC) 64 * 3Com 3c575C 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC) 65 * 3Com 3cxfem656 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC) 66 * 3Com 3cxfem656b 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC) 67 * 3Com 3cxfem656c 10/100Mbps/RJ-45 (Cardbus, Tornado ASIC) 68 * Dell Optiplex GX1 on-board 3c918 10/100Mbps/RJ-45 69 * Dell on-board 3c920 10/100Mbps/RJ-45 70 * Dell Precision on-board 3c905B 10/100Mbps/RJ-45 71 * Dell Latitude laptop docking station embedded 3c905-TX 72 * 73 * Written by Bill Paul <wpaul@ctr.columbia.edu> 74 * Electrical Engineering Department 75 * Columbia University, New York City 76 */ 77 78 /* 79 * The 3c90x series chips use a bus-master DMA interface for transfering 80 * packets to and from the controller chip. Some of the "vortex" cards 81 * (3c59x) also supported a bus master mode, however for those chips 82 * you could only DMA packets to/from a contiguous memory buffer. For 83 * transmission this would mean copying the contents of the queued mbuf 84 * chain into an mbuf cluster and then DMAing the cluster. This extra 85 * copy would sort of defeat the purpose of the bus master support for 86 * any packet that doesn't fit into a single mbuf. 87 * 88 * By contrast, the 3c90x cards support a fragment-based bus master 89 * mode where mbuf chains can be encapsulated using TX descriptors. 90 * This is similar to other PCI chips such as the Texas Instruments 91 * ThunderLAN and the Intel 82557/82558. 92 * 93 * The "vortex" driver (if_vx.c) happens to work for the "boomerang" 94 * bus master chips because they maintain the old PIO interface for 95 * backwards compatibility, but starting with the 3c905B and the 96 * "cyclone" chips, the compatibility interface has been dropped. 97 * Since using bus master DMA is a big win, we use this driver to 98 * support the PCI "boomerang" chips even though they work with the 99 * "vortex" driver in order to obtain better performance. 100 */ 101 102 #include "opt_polling.h" 103 #include "opt_ethernet.h" 104 105 #include <sys/param.h> 106 #include <sys/systm.h> 107 #include <sys/sockio.h> 108 #include <sys/endian.h> 109 #include <sys/mbuf.h> 110 #include <sys/kernel.h> 111 #include <sys/socket.h> 112 #include <sys/serialize.h> 113 #include <sys/bus.h> 114 #include <sys/rman.h> 115 #include <sys/thread2.h> 116 #include <sys/interrupt.h> 117 118 #include <net/if.h> 119 #include <net/ifq_var.h> 120 #include <net/if_arp.h> 121 #include <net/ethernet.h> 122 #include <net/if_dl.h> 123 #include <net/if_media.h> 124 #include <net/vlan/if_vlan_var.h> 125 126 #include <net/bpf.h> 127 128 #include "../mii_layer/mii.h" 129 #include "../mii_layer/miivar.h" 130 131 #include <bus/pci/pcireg.h> 132 #include <bus/pci/pcivar.h> 133 134 /* "controller miibus0" required. See GENERIC if you get errors here. */ 135 #include "miibus_if.h" 136 137 #include "if_xlreg.h" 138 139 #define XL905B_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 140 141 /* 142 * Various supported device vendors/types and their names. 143 */ 144 static struct xl_type xl_devs[] = { 145 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10BT, 146 "3Com 3c900-TPO Etherlink XL" }, 147 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10BT_COMBO, 148 "3Com 3c900-COMBO Etherlink XL" }, 149 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10_100BT, 150 "3Com 3c905-TX Fast Etherlink XL" }, 151 { TC_VENDORID, TC_DEVICEID_BOOMERANG_100BT4, 152 "3Com 3c905-T4 Fast Etherlink XL" }, 153 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT, 154 "3Com 3c900B-TPO Etherlink XL" }, 155 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT_COMBO, 156 "3Com 3c900B-COMBO Etherlink XL" }, 157 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT_TPC, 158 "3Com 3c900B-TPC Etherlink XL" }, 159 { TC_VENDORID, TC_DEVICEID_CYCLONE_10FL, 160 "3Com 3c900B-FL Etherlink XL" }, 161 { TC_VENDORID, TC_DEVICEID_HURRICANE_10_100BT, 162 "3Com 3c905B-TX Fast Etherlink XL" }, 163 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100BT4, 164 "3Com 3c905B-T4 Fast Etherlink XL" }, 165 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100FX, 166 "3Com 3c905B-FX/SC Fast Etherlink XL" }, 167 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100_COMBO, 168 "3Com 3c905B-COMBO Fast Etherlink XL" }, 169 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT, 170 "3Com 3c905C-TX Fast Etherlink XL" }, 171 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT_920B, 172 "3Com 3c920B-EMB Integrated Fast Etherlink XL" }, 173 { TC_VENDORID, TC_DEVICEID_HURRICANE_10_100BT_SERV, 174 "3Com 3c980 Fast Etherlink XL" }, 175 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT_SERV, 176 "3Com 3c980C Fast Etherlink XL" }, 177 { TC_VENDORID, TC_DEVICEID_HURRICANE_SOHO100TX, 178 "3Com 3cSOHO100-TX OfficeConnect" }, 179 { TC_VENDORID, TC_DEVICEID_TORNADO_HOMECONNECT, 180 "3Com 3c450-TX HomeConnect" }, 181 { TC_VENDORID, TC_DEVICEID_HURRICANE_555, 182 "3Com 3c555 Fast Etherlink XL" }, 183 { TC_VENDORID, TC_DEVICEID_HURRICANE_556, 184 "3Com 3c556 Fast Etherlink XL" }, 185 { TC_VENDORID, TC_DEVICEID_HURRICANE_556B, 186 "3Com 3c556B Fast Etherlink XL" }, 187 { TC_VENDORID, TC_DEVICEID_HURRICANE_575A, 188 "3Com 3c575TX Fast Etherlink XL" }, 189 { TC_VENDORID, TC_DEVICEID_HURRICANE_575B, 190 "3Com 3c575B Fast Etherlink XL" }, 191 { TC_VENDORID, TC_DEVICEID_HURRICANE_575C, 192 "3Com 3c575C Fast Etherlink XL" }, 193 { TC_VENDORID, TC_DEVICEID_HURRICANE_656, 194 "3Com 3c656 Fast Etherlink XL" }, 195 { TC_VENDORID, TC_DEVICEID_HURRICANE_656B, 196 "3Com 3c656B Fast Etherlink XL" }, 197 { TC_VENDORID, TC_DEVICEID_TORNADO_656C, 198 "3Com 3c656C Fast Etherlink XL" }, 199 { 0, 0, NULL } 200 }; 201 202 static int xl_probe (device_t); 203 static int xl_attach (device_t); 204 static int xl_detach (device_t); 205 static void xl_shutdown (device_t); 206 static int xl_suspend (device_t); 207 static int xl_resume (device_t); 208 209 static int xl_newbuf (struct xl_softc *, struct xl_chain_onefrag *); 210 static void xl_stats_update (void *); 211 static void xl_stats_update_serialized(void *); 212 static int xl_encap (struct xl_softc *, struct xl_chain *, 213 struct mbuf *); 214 static void xl_rxeof (struct xl_softc *, int); 215 static int xl_rx_resync (struct xl_softc *); 216 static void xl_txeof (struct xl_softc *); 217 static void xl_txeof_90xB (struct xl_softc *); 218 static void xl_txeoc (struct xl_softc *); 219 static void xl_intr (void *); 220 static void xl_start_body (struct ifnet *, int); 221 static void xl_start (struct ifnet *); 222 static void xl_start_poll (struct ifnet *); 223 static void xl_start_90xB (struct ifnet *); 224 static int xl_ioctl (struct ifnet *, u_long, caddr_t, 225 struct ucred *); 226 static void xl_init (void *); 227 static void xl_stop (struct xl_softc *); 228 static void xl_watchdog (struct ifnet *); 229 #ifdef DEVICE_POLLING 230 static void xl_poll (struct ifnet *, enum poll_cmd, int); 231 #endif 232 static void xl_enable_intrs (struct xl_softc *, uint16_t); 233 234 static int xl_ifmedia_upd (struct ifnet *); 235 static void xl_ifmedia_sts (struct ifnet *, struct ifmediareq *); 236 237 static int xl_eeprom_wait (struct xl_softc *); 238 static int xl_read_eeprom (struct xl_softc *, caddr_t, int, int, int); 239 static void xl_mii_sync (struct xl_softc *); 240 static void xl_mii_send (struct xl_softc *, u_int32_t, int); 241 static int xl_mii_readreg (struct xl_softc *, struct xl_mii_frame *); 242 static int xl_mii_writereg (struct xl_softc *, struct xl_mii_frame *); 243 244 static void xl_setcfg (struct xl_softc *); 245 static void xl_setmode (struct xl_softc *, int); 246 static void xl_setmulti (struct xl_softc *); 247 static void xl_setmulti_hash (struct xl_softc *); 248 static void xl_reset (struct xl_softc *); 249 static int xl_list_rx_init (struct xl_softc *); 250 static void xl_list_tx_init (struct xl_softc *); 251 static void xl_list_tx_init_90xB(struct xl_softc *); 252 static void xl_wait (struct xl_softc *); 253 static void xl_mediacheck (struct xl_softc *); 254 static void xl_choose_xcvr (struct xl_softc *, int); 255 static void xl_dma_map_addr (void *, bus_dma_segment_t *, int, int); 256 static void xl_dma_map_rxbuf (void *, bus_dma_segment_t *, int, bus_size_t, 257 int); 258 static void xl_dma_map_txbuf (void *, bus_dma_segment_t *, int, bus_size_t, 259 int); 260 261 static int xl_dma_alloc (device_t); 262 static void xl_dma_free (device_t); 263 264 #ifdef notdef 265 static void xl_testpacket (struct xl_softc *); 266 #endif 267 268 static int xl_miibus_readreg (device_t, int, int); 269 static int xl_miibus_writereg (device_t, int, int, int); 270 static void xl_miibus_statchg (device_t); 271 static void xl_miibus_mediainit (device_t); 272 273 static device_method_t xl_methods[] = { 274 /* Device interface */ 275 DEVMETHOD(device_probe, xl_probe), 276 DEVMETHOD(device_attach, xl_attach), 277 DEVMETHOD(device_detach, xl_detach), 278 DEVMETHOD(device_shutdown, xl_shutdown), 279 DEVMETHOD(device_suspend, xl_suspend), 280 DEVMETHOD(device_resume, xl_resume), 281 282 /* bus interface */ 283 DEVMETHOD(bus_print_child, bus_generic_print_child), 284 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 285 286 /* MII interface */ 287 DEVMETHOD(miibus_readreg, xl_miibus_readreg), 288 DEVMETHOD(miibus_writereg, xl_miibus_writereg), 289 DEVMETHOD(miibus_statchg, xl_miibus_statchg), 290 DEVMETHOD(miibus_mediainit, xl_miibus_mediainit), 291 292 { 0, 0 } 293 }; 294 295 static driver_t xl_driver = { 296 "xl", 297 xl_methods, 298 sizeof(struct xl_softc) 299 }; 300 301 static devclass_t xl_devclass; 302 303 DECLARE_DUMMY_MODULE(if_xl); 304 MODULE_DEPEND(if_xl, miibus, 1, 1, 1); 305 DRIVER_MODULE(if_xl, pci, xl_driver, xl_devclass, 0, 0); 306 DRIVER_MODULE(if_xl, cardbus, xl_driver, xl_devclass, 0, 0); 307 DRIVER_MODULE(miibus, xl, miibus_driver, miibus_devclass, 0, 0); 308 309 static void 310 xl_enable_intrs(struct xl_softc *sc, uint16_t intrs) 311 { 312 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ACK | 0xFF); 313 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB | intrs); 314 if (sc->xl_flags & XL_FLAG_FUNCREG) 315 bus_space_write_4(sc->xl_ftag, sc->xl_fhandle, 4, 0x8000); 316 } 317 318 static void 319 xl_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 320 { 321 u_int32_t *paddr; 322 323 paddr = arg; 324 *paddr = segs->ds_addr; 325 } 326 327 static void 328 xl_dma_map_rxbuf(void *arg, bus_dma_segment_t *segs, int nseg, 329 bus_size_t mapsize, int error) 330 { 331 u_int32_t *paddr; 332 333 if (error) 334 return; 335 KASSERT(nseg == 1, ("xl_dma_map_rxbuf: too many DMA segments")); 336 paddr = arg; 337 *paddr = segs->ds_addr; 338 } 339 340 static void 341 xl_dma_map_txbuf(void *arg, bus_dma_segment_t *segs, int nseg, 342 bus_size_t mapsize, int error) 343 { 344 struct xl_list *l; 345 int i, total_len; 346 347 if (error) 348 return; 349 350 KASSERT(nseg <= XL_MAXFRAGS, ("too many DMA segments")); 351 352 total_len = 0; 353 l = arg; 354 for (i = 0; i < nseg; i++) { 355 KASSERT(segs[i].ds_len <= MCLBYTES, ("segment size too large")); 356 l->xl_frag[i].xl_addr = htole32(segs[i].ds_addr); 357 l->xl_frag[i].xl_len = htole32(segs[i].ds_len); 358 total_len += segs[i].ds_len; 359 } 360 l->xl_frag[nseg - 1].xl_len = htole32(segs[nseg - 1].ds_len | 361 XL_LAST_FRAG); 362 l->xl_status = htole32(total_len); 363 l->xl_next = 0; 364 } 365 366 /* 367 * Murphy's law says that it's possible the chip can wedge and 368 * the 'command in progress' bit may never clear. Hence, we wait 369 * only a finite amount of time to avoid getting caught in an 370 * infinite loop. Normally this delay routine would be a macro, 371 * but it isn't called during normal operation so we can afford 372 * to make it a function. 373 */ 374 static void 375 xl_wait(struct xl_softc *sc) 376 { 377 int i; 378 379 for (i = 0; i < XL_TIMEOUT; i++) { 380 if (!(CSR_READ_2(sc, XL_STATUS) & XL_STAT_CMDBUSY)) 381 break; 382 } 383 384 if (i == XL_TIMEOUT) 385 if_printf(&sc->arpcom.ac_if, "command never completed!"); 386 387 return; 388 } 389 390 /* 391 * MII access routines are provided for adapters with external 392 * PHYs (3c905-TX, 3c905-T4, 3c905B-T4) and those with built-in 393 * autoneg logic that's faked up to look like a PHY (3c905B-TX). 394 * Note: if you don't perform the MDIO operations just right, 395 * it's possible to end up with code that works correctly with 396 * some chips/CPUs/processor speeds/bus speeds/etc but not 397 * with others. 398 */ 399 #define MII_SET(x) \ 400 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, \ 401 CSR_READ_2(sc, XL_W4_PHY_MGMT) | (x)) 402 403 #define MII_CLR(x) \ 404 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, \ 405 CSR_READ_2(sc, XL_W4_PHY_MGMT) & ~(x)) 406 407 /* 408 * Sync the PHYs by setting data bit and strobing the clock 32 times. 409 */ 410 static void 411 xl_mii_sync(struct xl_softc *sc) 412 { 413 int i; 414 415 XL_SEL_WIN(4); 416 MII_SET(XL_MII_DIR|XL_MII_DATA); 417 418 for (i = 0; i < 32; i++) { 419 MII_SET(XL_MII_CLK); 420 MII_SET(XL_MII_DATA); 421 MII_SET(XL_MII_DATA); 422 MII_CLR(XL_MII_CLK); 423 MII_SET(XL_MII_DATA); 424 MII_SET(XL_MII_DATA); 425 } 426 427 return; 428 } 429 430 /* 431 * Clock a series of bits through the MII. 432 */ 433 static void 434 xl_mii_send(struct xl_softc *sc, u_int32_t bits, int cnt) 435 { 436 int i; 437 438 XL_SEL_WIN(4); 439 MII_CLR(XL_MII_CLK); 440 441 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 442 if (bits & i) { 443 MII_SET(XL_MII_DATA); 444 } else { 445 MII_CLR(XL_MII_DATA); 446 } 447 MII_CLR(XL_MII_CLK); 448 MII_SET(XL_MII_CLK); 449 } 450 } 451 452 /* 453 * Read an PHY register through the MII. 454 */ 455 static int 456 xl_mii_readreg(struct xl_softc *sc, struct xl_mii_frame *frame) 457 { 458 int i, ack; 459 460 /* 461 * Set up frame for RX. 462 */ 463 frame->mii_stdelim = XL_MII_STARTDELIM; 464 frame->mii_opcode = XL_MII_READOP; 465 frame->mii_turnaround = 0; 466 frame->mii_data = 0; 467 468 /* 469 * Select register window 4. 470 */ 471 472 XL_SEL_WIN(4); 473 474 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, 0); 475 /* 476 * Turn on data xmit. 477 */ 478 MII_SET(XL_MII_DIR); 479 480 xl_mii_sync(sc); 481 482 /* 483 * Send command/address info. 484 */ 485 xl_mii_send(sc, frame->mii_stdelim, 2); 486 xl_mii_send(sc, frame->mii_opcode, 2); 487 xl_mii_send(sc, frame->mii_phyaddr, 5); 488 xl_mii_send(sc, frame->mii_regaddr, 5); 489 490 /* Idle bit */ 491 MII_CLR((XL_MII_CLK|XL_MII_DATA)); 492 MII_SET(XL_MII_CLK); 493 494 /* Turn off xmit. */ 495 MII_CLR(XL_MII_DIR); 496 497 /* Check for ack */ 498 MII_CLR(XL_MII_CLK); 499 ack = CSR_READ_2(sc, XL_W4_PHY_MGMT) & XL_MII_DATA; 500 MII_SET(XL_MII_CLK); 501 502 /* 503 * Now try reading data bits. If the ack failed, we still 504 * need to clock through 16 cycles to keep the PHY(s) in sync. 505 */ 506 if (ack) { 507 for(i = 0; i < 16; i++) { 508 MII_CLR(XL_MII_CLK); 509 MII_SET(XL_MII_CLK); 510 } 511 goto fail; 512 } 513 514 for (i = 0x8000; i; i >>= 1) { 515 MII_CLR(XL_MII_CLK); 516 if (!ack) { 517 if (CSR_READ_2(sc, XL_W4_PHY_MGMT) & XL_MII_DATA) 518 frame->mii_data |= i; 519 } 520 MII_SET(XL_MII_CLK); 521 } 522 523 fail: 524 525 MII_CLR(XL_MII_CLK); 526 MII_SET(XL_MII_CLK); 527 528 if (ack) 529 return(1); 530 return(0); 531 } 532 533 /* 534 * Write to a PHY register through the MII. 535 */ 536 static int 537 xl_mii_writereg(struct xl_softc *sc, struct xl_mii_frame *frame) 538 { 539 /* 540 * Set up frame for TX. 541 */ 542 543 frame->mii_stdelim = XL_MII_STARTDELIM; 544 frame->mii_opcode = XL_MII_WRITEOP; 545 frame->mii_turnaround = XL_MII_TURNAROUND; 546 547 /* 548 * Select the window 4. 549 */ 550 XL_SEL_WIN(4); 551 552 /* 553 * Turn on data output. 554 */ 555 MII_SET(XL_MII_DIR); 556 557 xl_mii_sync(sc); 558 559 xl_mii_send(sc, frame->mii_stdelim, 2); 560 xl_mii_send(sc, frame->mii_opcode, 2); 561 xl_mii_send(sc, frame->mii_phyaddr, 5); 562 xl_mii_send(sc, frame->mii_regaddr, 5); 563 xl_mii_send(sc, frame->mii_turnaround, 2); 564 xl_mii_send(sc, frame->mii_data, 16); 565 566 /* Idle bit. */ 567 MII_SET(XL_MII_CLK); 568 MII_CLR(XL_MII_CLK); 569 570 /* 571 * Turn off xmit. 572 */ 573 MII_CLR(XL_MII_DIR); 574 575 return(0); 576 } 577 578 static int 579 xl_miibus_readreg(device_t dev, int phy, int reg) 580 { 581 struct xl_softc *sc; 582 struct xl_mii_frame frame; 583 584 sc = device_get_softc(dev); 585 586 /* 587 * Pretend that PHYs are only available at MII address 24. 588 * This is to guard against problems with certain 3Com ASIC 589 * revisions that incorrectly map the internal transceiver 590 * control registers at all MII addresses. This can cause 591 * the miibus code to attach the same PHY several times over. 592 */ 593 if ((!(sc->xl_flags & XL_FLAG_PHYOK)) && phy != 24) 594 return(0); 595 596 bzero((char *)&frame, sizeof(frame)); 597 598 frame.mii_phyaddr = phy; 599 frame.mii_regaddr = reg; 600 xl_mii_readreg(sc, &frame); 601 602 return(frame.mii_data); 603 } 604 605 static int 606 xl_miibus_writereg(device_t dev, int phy, int reg, int data) 607 { 608 struct xl_softc *sc; 609 struct xl_mii_frame frame; 610 611 sc = device_get_softc(dev); 612 613 if ((!(sc->xl_flags & XL_FLAG_PHYOK)) && phy != 24) 614 return(0); 615 616 bzero((char *)&frame, sizeof(frame)); 617 618 frame.mii_phyaddr = phy; 619 frame.mii_regaddr = reg; 620 frame.mii_data = data; 621 622 xl_mii_writereg(sc, &frame); 623 624 return(0); 625 } 626 627 static void 628 xl_miibus_statchg(device_t dev) 629 { 630 struct xl_softc *sc; 631 struct mii_data *mii; 632 633 sc = device_get_softc(dev); 634 mii = device_get_softc(sc->xl_miibus); 635 636 ASSERT_SERIALIZED(sc->arpcom.ac_if.if_serializer); 637 638 xl_setcfg(sc); 639 640 /* Set ASIC's duplex mode to match the PHY. */ 641 XL_SEL_WIN(3); 642 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) 643 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, XL_MACCTRL_DUPLEX); 644 else 645 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, 646 (CSR_READ_1(sc, XL_W3_MAC_CTRL) & ~XL_MACCTRL_DUPLEX)); 647 } 648 649 /* 650 * Special support for the 3c905B-COMBO. This card has 10/100 support 651 * plus BNC and AUI ports. This means we will have both an miibus attached 652 * plus some non-MII media settings. In order to allow this, we have to 653 * add the extra media to the miibus's ifmedia struct, but we can't do 654 * that during xl_attach() because the miibus hasn't been attached yet. 655 * So instead, we wait until the miibus probe/attach is done, at which 656 * point we will get a callback telling is that it's safe to add our 657 * extra media. 658 */ 659 static void 660 xl_miibus_mediainit(device_t dev) 661 { 662 struct xl_softc *sc; 663 struct mii_data *mii; 664 struct ifmedia *ifm; 665 666 sc = device_get_softc(dev); 667 mii = device_get_softc(sc->xl_miibus); 668 ifm = &mii->mii_media; 669 670 if (sc->xl_media & (XL_MEDIAOPT_AUI|XL_MEDIAOPT_10FL)) { 671 /* 672 * Check for a 10baseFL board in disguise. 673 */ 674 if (sc->xl_type == XL_TYPE_905B && 675 sc->xl_media == XL_MEDIAOPT_10FL) { 676 if (bootverbose) 677 device_printf(dev, "found 10baseFL\n"); 678 ifmedia_add(ifm, IFM_ETHER|IFM_10_FL, 0, NULL); 679 ifmedia_add(ifm, IFM_ETHER|IFM_10_FL|IFM_HDX, 0, NULL); 680 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX) 681 ifmedia_add(ifm, 682 IFM_ETHER|IFM_10_FL|IFM_FDX, 0, NULL); 683 } else { 684 if (bootverbose) 685 device_printf(dev, "found AUI\n"); 686 ifmedia_add(ifm, IFM_ETHER|IFM_10_5, 0, NULL); 687 } 688 } 689 690 if (sc->xl_media & XL_MEDIAOPT_BNC) { 691 if (bootverbose) 692 device_printf(dev, "found BNC\n"); 693 ifmedia_add(ifm, IFM_ETHER|IFM_10_2, 0, NULL); 694 } 695 696 return; 697 } 698 699 /* 700 * The EEPROM is slow: give it time to come ready after issuing 701 * it a command. 702 */ 703 static int 704 xl_eeprom_wait(struct xl_softc *sc) 705 { 706 int i; 707 708 for (i = 0; i < 100; i++) { 709 if (CSR_READ_2(sc, XL_W0_EE_CMD) & XL_EE_BUSY) 710 DELAY(162); 711 else 712 break; 713 } 714 715 if (i == 100) { 716 if_printf(&sc->arpcom.ac_if, "eeprom failed to come ready\n"); 717 return(1); 718 } 719 720 return(0); 721 } 722 723 /* 724 * Read a sequence of words from the EEPROM. Note that ethernet address 725 * data is stored in the EEPROM in network byte order. 726 */ 727 static int 728 xl_read_eeprom(struct xl_softc *sc, caddr_t dest, int off, int cnt, int swap) 729 { 730 int err = 0, i; 731 u_int16_t word = 0, *ptr; 732 #define EEPROM_5BIT_OFFSET(A) ((((A) << 2) & 0x7F00) | ((A) & 0x003F)) 733 #define EEPROM_8BIT_OFFSET(A) ((A) & 0x003F) 734 /* WARNING! DANGER! 735 * It's easy to accidentally overwrite the rom content! 736 * Note: the 3c575 uses 8bit EEPROM offsets. 737 */ 738 XL_SEL_WIN(0); 739 740 if (xl_eeprom_wait(sc)) 741 return(1); 742 743 if (sc->xl_flags & XL_FLAG_EEPROM_OFFSET_30) 744 off += 0x30; 745 746 for (i = 0; i < cnt; i++) { 747 if (sc->xl_flags & XL_FLAG_8BITROM) 748 CSR_WRITE_2(sc, XL_W0_EE_CMD, 749 XL_EE_8BIT_READ | EEPROM_8BIT_OFFSET(off + i)); 750 else 751 CSR_WRITE_2(sc, XL_W0_EE_CMD, 752 XL_EE_READ | EEPROM_5BIT_OFFSET(off + i)); 753 err = xl_eeprom_wait(sc); 754 if (err) 755 break; 756 word = CSR_READ_2(sc, XL_W0_EE_DATA); 757 ptr = (u_int16_t *)(dest + (i * 2)); 758 if (swap) 759 *ptr = ntohs(word); 760 else 761 *ptr = word; 762 } 763 764 return(err ? 1 : 0); 765 } 766 767 /* 768 * NICs older than the 3c905B have only one multicast option, which 769 * is to enable reception of all multicast frames. 770 */ 771 static void 772 xl_setmulti(struct xl_softc *sc) 773 { 774 struct ifnet *ifp; 775 struct ifmultiaddr *ifma; 776 u_int8_t rxfilt; 777 int mcnt = 0; 778 779 ifp = &sc->arpcom.ac_if; 780 781 XL_SEL_WIN(5); 782 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER); 783 784 if (ifp->if_flags & IFF_ALLMULTI) { 785 rxfilt |= XL_RXFILTER_ALLMULTI; 786 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 787 return; 788 } 789 790 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) 791 mcnt++; 792 793 if (mcnt) 794 rxfilt |= XL_RXFILTER_ALLMULTI; 795 else 796 rxfilt &= ~XL_RXFILTER_ALLMULTI; 797 798 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 799 800 return; 801 } 802 803 /* 804 * 3c905B adapters have a hash filter that we can program. 805 */ 806 static void 807 xl_setmulti_hash(struct xl_softc *sc) 808 { 809 struct ifnet *ifp; 810 int h = 0, i; 811 struct ifmultiaddr *ifma; 812 u_int8_t rxfilt; 813 int mcnt = 0; 814 815 ifp = &sc->arpcom.ac_if; 816 817 XL_SEL_WIN(5); 818 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER); 819 820 if (ifp->if_flags & IFF_ALLMULTI) { 821 rxfilt |= XL_RXFILTER_ALLMULTI; 822 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 823 return; 824 } else 825 rxfilt &= ~XL_RXFILTER_ALLMULTI; 826 827 828 /* first, zot all the existing hash bits */ 829 for (i = 0; i < XL_HASHFILT_SIZE; i++) 830 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_HASH|i); 831 832 /* now program new ones */ 833 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 834 if (ifma->ifma_addr->sa_family != AF_LINK) 835 continue; 836 837 /* 838 * Note: the 3c905B currently only supports a 64-bit 839 * hash table, which means we really only need 6 bits, 840 * but the manual indicates that future chip revisions 841 * will have a 256-bit hash table, hence the routine is 842 * set up to calculate 8 bits of position info in case 843 * we need it some day. 844 * Note II, The Sequel: _CURRENT_ versions of the 3c905B 845 * have a 256 bit hash table. This means we have to use 846 * all 8 bits regardless. On older cards, the upper 2 847 * bits will be ignored. Grrrr.... 848 */ 849 h = ether_crc32_be( 850 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 851 ETHER_ADDR_LEN) & 0xff; 852 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_HASH|XL_HASH_SET|h); 853 mcnt++; 854 } 855 856 if (mcnt) 857 rxfilt |= XL_RXFILTER_MULTIHASH; 858 else 859 rxfilt &= ~XL_RXFILTER_MULTIHASH; 860 861 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 862 863 return; 864 } 865 866 #ifdef notdef 867 static void 868 xl_testpacket(struct xl_softc *sc) 869 { 870 struct mbuf *m; 871 struct ifnet *ifp; 872 873 ifp = &sc->arpcom.ac_if; 874 875 MGETHDR(m, MB_DONTWAIT, MT_DATA); 876 877 if (m == NULL) 878 return; 879 880 bcopy(&sc->arpcom.ac_enaddr, 881 mtod(m, struct ether_header *)->ether_dhost, ETHER_ADDR_LEN); 882 bcopy(&sc->arpcom.ac_enaddr, 883 mtod(m, struct ether_header *)->ether_shost, ETHER_ADDR_LEN); 884 mtod(m, struct ether_header *)->ether_type = htons(3); 885 mtod(m, unsigned char *)[14] = 0; 886 mtod(m, unsigned char *)[15] = 0; 887 mtod(m, unsigned char *)[16] = 0xE3; 888 m->m_len = m->m_pkthdr.len = sizeof(struct ether_header) + 3; 889 IF_ENQUEUE(&ifp->if_snd, m); 890 xl_start(ifp); 891 892 return; 893 } 894 #endif 895 896 static void 897 xl_setcfg(struct xl_softc *sc) 898 { 899 u_int32_t icfg; 900 901 XL_SEL_WIN(3); 902 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG); 903 icfg &= ~XL_ICFG_CONNECTOR_MASK; 904 if (sc->xl_media & XL_MEDIAOPT_MII || 905 sc->xl_media & XL_MEDIAOPT_BT4) 906 icfg |= (XL_XCVR_MII << XL_ICFG_CONNECTOR_BITS); 907 if (sc->xl_media & XL_MEDIAOPT_BTX) 908 icfg |= (XL_XCVR_AUTO << XL_ICFG_CONNECTOR_BITS); 909 910 CSR_WRITE_4(sc, XL_W3_INTERNAL_CFG, icfg); 911 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP); 912 913 return; 914 } 915 916 static void 917 xl_setmode(struct xl_softc *sc, int media) 918 { 919 struct ifnet *ifp = &sc->arpcom.ac_if; 920 u_int32_t icfg; 921 u_int16_t mediastat; 922 923 if_printf(ifp, "selecting "); 924 925 XL_SEL_WIN(4); 926 mediastat = CSR_READ_2(sc, XL_W4_MEDIA_STATUS); 927 XL_SEL_WIN(3); 928 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG); 929 930 if (sc->xl_media & XL_MEDIAOPT_BT) { 931 if (IFM_SUBTYPE(media) == IFM_10_T) { 932 kprintf("10baseT transceiver, "); 933 sc->xl_xcvr = XL_XCVR_10BT; 934 icfg &= ~XL_ICFG_CONNECTOR_MASK; 935 icfg |= (XL_XCVR_10BT << XL_ICFG_CONNECTOR_BITS); 936 mediastat |= XL_MEDIASTAT_LINKBEAT| 937 XL_MEDIASTAT_JABGUARD; 938 mediastat &= ~XL_MEDIASTAT_SQEENB; 939 } 940 } 941 942 if (sc->xl_media & XL_MEDIAOPT_BFX) { 943 if (IFM_SUBTYPE(media) == IFM_100_FX) { 944 kprintf("100baseFX port, "); 945 sc->xl_xcvr = XL_XCVR_100BFX; 946 icfg &= ~XL_ICFG_CONNECTOR_MASK; 947 icfg |= (XL_XCVR_100BFX << XL_ICFG_CONNECTOR_BITS); 948 mediastat |= XL_MEDIASTAT_LINKBEAT; 949 mediastat &= ~XL_MEDIASTAT_SQEENB; 950 } 951 } 952 953 if (sc->xl_media & (XL_MEDIAOPT_AUI|XL_MEDIAOPT_10FL)) { 954 if (IFM_SUBTYPE(media) == IFM_10_5) { 955 kprintf("AUI port, "); 956 sc->xl_xcvr = XL_XCVR_AUI; 957 icfg &= ~XL_ICFG_CONNECTOR_MASK; 958 icfg |= (XL_XCVR_AUI << XL_ICFG_CONNECTOR_BITS); 959 mediastat &= ~(XL_MEDIASTAT_LINKBEAT| 960 XL_MEDIASTAT_JABGUARD); 961 mediastat |= ~XL_MEDIASTAT_SQEENB; 962 } 963 if (IFM_SUBTYPE(media) == IFM_10_FL) { 964 kprintf("10baseFL transceiver, "); 965 sc->xl_xcvr = XL_XCVR_AUI; 966 icfg &= ~XL_ICFG_CONNECTOR_MASK; 967 icfg |= (XL_XCVR_AUI << XL_ICFG_CONNECTOR_BITS); 968 mediastat &= ~(XL_MEDIASTAT_LINKBEAT| 969 XL_MEDIASTAT_JABGUARD); 970 mediastat |= ~XL_MEDIASTAT_SQEENB; 971 } 972 } 973 974 if (sc->xl_media & XL_MEDIAOPT_BNC) { 975 if (IFM_SUBTYPE(media) == IFM_10_2) { 976 kprintf("BNC port, "); 977 sc->xl_xcvr = XL_XCVR_COAX; 978 icfg &= ~XL_ICFG_CONNECTOR_MASK; 979 icfg |= (XL_XCVR_COAX << XL_ICFG_CONNECTOR_BITS); 980 mediastat &= ~(XL_MEDIASTAT_LINKBEAT| 981 XL_MEDIASTAT_JABGUARD| 982 XL_MEDIASTAT_SQEENB); 983 } 984 } 985 986 if ((media & IFM_GMASK) == IFM_FDX || 987 IFM_SUBTYPE(media) == IFM_100_FX) { 988 kprintf("full duplex\n"); 989 XL_SEL_WIN(3); 990 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, XL_MACCTRL_DUPLEX); 991 } else { 992 kprintf("half duplex\n"); 993 XL_SEL_WIN(3); 994 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, 995 (CSR_READ_1(sc, XL_W3_MAC_CTRL) & ~XL_MACCTRL_DUPLEX)); 996 } 997 998 if (IFM_SUBTYPE(media) == IFM_10_2) 999 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_START); 1000 else 1001 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP); 1002 CSR_WRITE_4(sc, XL_W3_INTERNAL_CFG, icfg); 1003 XL_SEL_WIN(4); 1004 CSR_WRITE_2(sc, XL_W4_MEDIA_STATUS, mediastat); 1005 DELAY(800); 1006 XL_SEL_WIN(7); 1007 } 1008 1009 static void 1010 xl_reset(struct xl_softc *sc) 1011 { 1012 int i; 1013 1014 XL_SEL_WIN(0); 1015 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RESET | 1016 ((sc->xl_flags & XL_FLAG_WEIRDRESET) ? 1017 XL_RESETOPT_DISADVFD:0)); 1018 1019 /* 1020 * If we're using memory mapped register mode, pause briefly 1021 * after issuing the reset command before trying to access any 1022 * other registers. With my 3c575C cardbus card, failing to do 1023 * this results in the system locking up while trying to poll 1024 * the command busy bit in the status register. 1025 */ 1026 if (sc->xl_flags & XL_FLAG_USE_MMIO) 1027 DELAY(100000); 1028 1029 for (i = 0; i < XL_TIMEOUT; i++) { 1030 DELAY(10); 1031 if (!(CSR_READ_2(sc, XL_STATUS) & XL_STAT_CMDBUSY)) 1032 break; 1033 } 1034 1035 if (i == XL_TIMEOUT) 1036 if_printf(&sc->arpcom.ac_if, "reset didn't complete\n"); 1037 1038 /* Reset TX and RX. */ 1039 /* Note: the RX reset takes an absurd amount of time 1040 * on newer versions of the Tornado chips such as those 1041 * on the 3c905CX and newer 3c908C cards. We wait an 1042 * extra amount of time so that xl_wait() doesn't complain 1043 * and annoy the users. 1044 */ 1045 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET); 1046 DELAY(100000); 1047 xl_wait(sc); 1048 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); 1049 xl_wait(sc); 1050 1051 if (sc->xl_flags & XL_FLAG_INVERT_LED_PWR || 1052 sc->xl_flags & XL_FLAG_INVERT_MII_PWR) { 1053 XL_SEL_WIN(2); 1054 CSR_WRITE_2(sc, XL_W2_RESET_OPTIONS, CSR_READ_2(sc, 1055 XL_W2_RESET_OPTIONS) 1056 | ((sc->xl_flags & XL_FLAG_INVERT_LED_PWR)?XL_RESETOPT_INVERT_LED:0) 1057 | ((sc->xl_flags & XL_FLAG_INVERT_MII_PWR)?XL_RESETOPT_INVERT_MII:0) 1058 ); 1059 } 1060 1061 /* Wait a little while for the chip to get its brains in order. */ 1062 DELAY(100000); 1063 return; 1064 } 1065 1066 /* 1067 * Probe for a 3Com Etherlink XL chip. Check the PCI vendor and device 1068 * IDs against our list and return a device name if we find a match. 1069 */ 1070 static int 1071 xl_probe(device_t dev) 1072 { 1073 struct xl_type *t; 1074 uint16_t vid, did; 1075 1076 vid = pci_get_vendor(dev); 1077 did = pci_get_device(dev); 1078 for (t = xl_devs; t->xl_name != NULL; t++) { 1079 if (vid == t->xl_vid && did == t->xl_did) { 1080 device_set_desc(dev, t->xl_name); 1081 return(0); 1082 } 1083 } 1084 return(ENXIO); 1085 } 1086 1087 /* 1088 * This routine is a kludge to work around possible hardware faults 1089 * or manufacturing defects that can cause the media options register 1090 * (or reset options register, as it's called for the first generation 1091 * 3c90x adapters) to return an incorrect result. I have encountered 1092 * one Dell Latitude laptop docking station with an integrated 3c905-TX 1093 * which doesn't have any of the 'mediaopt' bits set. This screws up 1094 * the attach routine pretty badly because it doesn't know what media 1095 * to look for. If we find ourselves in this predicament, this routine 1096 * will try to guess the media options values and warn the user of a 1097 * possible manufacturing defect with his adapter/system/whatever. 1098 */ 1099 static void 1100 xl_mediacheck(struct xl_softc *sc) 1101 { 1102 struct ifnet *ifp = &sc->arpcom.ac_if; 1103 1104 /* 1105 * If some of the media options bits are set, assume they are 1106 * correct. If not, try to figure it out down below. 1107 * XXX I should check for 10baseFL, but I don't have an adapter 1108 * to test with. 1109 */ 1110 if (sc->xl_media & (XL_MEDIAOPT_MASK & ~XL_MEDIAOPT_VCO)) { 1111 /* 1112 * Check the XCVR value. If it's not in the normal range 1113 * of values, we need to fake it up here. 1114 */ 1115 if (sc->xl_xcvr <= XL_XCVR_AUTO) 1116 return; 1117 else { 1118 if_printf(ifp, "bogus xcvr value in EEPROM (%x)\n", 1119 sc->xl_xcvr); 1120 if_printf(ifp, 1121 "choosing new default based on card type\n"); 1122 } 1123 } else { 1124 if (sc->xl_type == XL_TYPE_905B && 1125 sc->xl_media & XL_MEDIAOPT_10FL) 1126 return; 1127 if_printf(ifp, "WARNING: no media options bits set in " 1128 "the media options register!!\n"); 1129 if_printf(ifp, "this could be a manufacturing defect in " 1130 "your adapter or system\n"); 1131 if_printf(ifp, "attempting to guess media type; you " 1132 "should probably consult your vendor\n"); 1133 } 1134 1135 xl_choose_xcvr(sc, 1); 1136 } 1137 1138 static void 1139 xl_choose_xcvr(struct xl_softc *sc, int verbose) 1140 { 1141 struct ifnet *ifp = &sc->arpcom.ac_if; 1142 u_int16_t devid; 1143 1144 /* 1145 * Read the device ID from the EEPROM. 1146 * This is what's loaded into the PCI device ID register, so it has 1147 * to be correct otherwise we wouldn't have gotten this far. 1148 */ 1149 xl_read_eeprom(sc, (caddr_t)&devid, XL_EE_PRODID, 1, 0); 1150 1151 switch(devid) { 1152 case TC_DEVICEID_BOOMERANG_10BT: /* 3c900-TPO */ 1153 case TC_DEVICEID_KRAKATOA_10BT: /* 3c900B-TPO */ 1154 sc->xl_media = XL_MEDIAOPT_BT; 1155 sc->xl_xcvr = XL_XCVR_10BT; 1156 if (verbose) 1157 if_printf(ifp, "guessing 10BaseT transceiver\n"); 1158 break; 1159 case TC_DEVICEID_BOOMERANG_10BT_COMBO: /* 3c900-COMBO */ 1160 case TC_DEVICEID_KRAKATOA_10BT_COMBO: /* 3c900B-COMBO */ 1161 sc->xl_media = XL_MEDIAOPT_BT|XL_MEDIAOPT_BNC|XL_MEDIAOPT_AUI; 1162 sc->xl_xcvr = XL_XCVR_10BT; 1163 if (verbose) 1164 if_printf(ifp, "guessing COMBO (AUI/BNC/TP)\n"); 1165 break; 1166 case TC_DEVICEID_KRAKATOA_10BT_TPC: /* 3c900B-TPC */ 1167 sc->xl_media = XL_MEDIAOPT_BT|XL_MEDIAOPT_BNC; 1168 sc->xl_xcvr = XL_XCVR_10BT; 1169 if (verbose) 1170 if_printf(ifp, "guessing TPC (BNC/TP)\n"); 1171 break; 1172 case TC_DEVICEID_CYCLONE_10FL: /* 3c900B-FL */ 1173 sc->xl_media = XL_MEDIAOPT_10FL; 1174 sc->xl_xcvr = XL_XCVR_AUI; 1175 if (verbose) 1176 if_printf(ifp, "guessing 10baseFL\n"); 1177 break; 1178 case TC_DEVICEID_BOOMERANG_10_100BT: /* 3c905-TX */ 1179 case TC_DEVICEID_HURRICANE_555: /* 3c555 */ 1180 case TC_DEVICEID_HURRICANE_556: /* 3c556 */ 1181 case TC_DEVICEID_HURRICANE_556B: /* 3c556B */ 1182 case TC_DEVICEID_HURRICANE_575A: /* 3c575TX */ 1183 case TC_DEVICEID_HURRICANE_575B: /* 3c575B */ 1184 case TC_DEVICEID_HURRICANE_575C: /* 3c575C */ 1185 case TC_DEVICEID_HURRICANE_656: /* 3c656 */ 1186 case TC_DEVICEID_HURRICANE_656B: /* 3c656B */ 1187 case TC_DEVICEID_TORNADO_656C: /* 3c656C */ 1188 case TC_DEVICEID_TORNADO_10_100BT_920B: /* 3c920B-EMB */ 1189 sc->xl_media = XL_MEDIAOPT_MII; 1190 sc->xl_xcvr = XL_XCVR_MII; 1191 if (verbose) 1192 if_printf(ifp, "guessing MII\n"); 1193 break; 1194 case TC_DEVICEID_BOOMERANG_100BT4: /* 3c905-T4 */ 1195 case TC_DEVICEID_CYCLONE_10_100BT4: /* 3c905B-T4 */ 1196 sc->xl_media = XL_MEDIAOPT_BT4; 1197 sc->xl_xcvr = XL_XCVR_MII; 1198 if (verbose) 1199 if_printf(ifp, "guessing 100BaseT4/MII\n"); 1200 break; 1201 case TC_DEVICEID_HURRICANE_10_100BT: /* 3c905B-TX */ 1202 case TC_DEVICEID_HURRICANE_10_100BT_SERV:/*3c980-TX */ 1203 case TC_DEVICEID_TORNADO_10_100BT_SERV: /* 3c980C-TX */ 1204 case TC_DEVICEID_HURRICANE_SOHO100TX: /* 3cSOHO100-TX */ 1205 case TC_DEVICEID_TORNADO_10_100BT: /* 3c905C-TX */ 1206 case TC_DEVICEID_TORNADO_HOMECONNECT: /* 3c450-TX */ 1207 sc->xl_media = XL_MEDIAOPT_BTX; 1208 sc->xl_xcvr = XL_XCVR_AUTO; 1209 if (verbose) 1210 if_printf(ifp, "guessing 10/100 internal\n"); 1211 break; 1212 case TC_DEVICEID_CYCLONE_10_100_COMBO: /* 3c905B-COMBO */ 1213 sc->xl_media = XL_MEDIAOPT_BTX|XL_MEDIAOPT_BNC|XL_MEDIAOPT_AUI; 1214 sc->xl_xcvr = XL_XCVR_AUTO; 1215 if (verbose) 1216 if_printf(ifp, "guessing 10/100 plus BNC/AUI\n"); 1217 break; 1218 default: 1219 if_printf(ifp, 1220 "unknown device ID: %x -- defaulting to 10baseT\n", devid); 1221 sc->xl_media = XL_MEDIAOPT_BT; 1222 break; 1223 } 1224 1225 return; 1226 } 1227 1228 /* 1229 * Attach the interface. Allocate softc structures, do ifmedia 1230 * setup and ethernet/BPF attach. 1231 */ 1232 static int 1233 xl_attach(device_t dev) 1234 { 1235 u_char eaddr[ETHER_ADDR_LEN]; 1236 u_int16_t xcvr[2]; 1237 struct xl_softc *sc; 1238 struct ifnet *ifp; 1239 int media = IFM_ETHER|IFM_100_TX|IFM_FDX; 1240 int error = 0, rid, res; 1241 uint16_t did; 1242 1243 sc = device_get_softc(dev); 1244 1245 ifmedia_init(&sc->ifmedia, 0, xl_ifmedia_upd, xl_ifmedia_sts); 1246 1247 did = pci_get_device(dev); 1248 1249 sc->xl_flags = 0; 1250 if (did == TC_DEVICEID_HURRICANE_555) 1251 sc->xl_flags |= XL_FLAG_EEPROM_OFFSET_30 | XL_FLAG_PHYOK; 1252 if (did == TC_DEVICEID_HURRICANE_556 || 1253 did == TC_DEVICEID_HURRICANE_556B) 1254 sc->xl_flags |= XL_FLAG_FUNCREG | XL_FLAG_PHYOK | 1255 XL_FLAG_EEPROM_OFFSET_30 | XL_FLAG_WEIRDRESET | 1256 XL_FLAG_INVERT_LED_PWR | XL_FLAG_INVERT_MII_PWR; 1257 if (did == TC_DEVICEID_HURRICANE_555 || 1258 did == TC_DEVICEID_HURRICANE_556) 1259 sc->xl_flags |= XL_FLAG_8BITROM; 1260 if (did == TC_DEVICEID_HURRICANE_556B) 1261 sc->xl_flags |= XL_FLAG_NO_XCVR_PWR; 1262 if (did == TC_DEVICEID_HURRICANE_575B || 1263 did == TC_DEVICEID_HURRICANE_575C || 1264 did == TC_DEVICEID_HURRICANE_656B || 1265 did == TC_DEVICEID_TORNADO_656C) 1266 sc->xl_flags |= XL_FLAG_FUNCREG; 1267 if (did == TC_DEVICEID_HURRICANE_575A || 1268 did == TC_DEVICEID_HURRICANE_575B || 1269 did == TC_DEVICEID_HURRICANE_575C || 1270 did == TC_DEVICEID_HURRICANE_656B || 1271 did == TC_DEVICEID_TORNADO_656C) 1272 sc->xl_flags |= XL_FLAG_PHYOK | XL_FLAG_EEPROM_OFFSET_30 | 1273 XL_FLAG_8BITROM; 1274 if (did == TC_DEVICEID_HURRICANE_656) 1275 sc->xl_flags |= XL_FLAG_FUNCREG | XL_FLAG_PHYOK; 1276 if (did == TC_DEVICEID_HURRICANE_575B) 1277 sc->xl_flags |= XL_FLAG_INVERT_LED_PWR; 1278 if (did == TC_DEVICEID_HURRICANE_575C) 1279 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR; 1280 if (did == TC_DEVICEID_TORNADO_656C) 1281 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR; 1282 if (did == TC_DEVICEID_HURRICANE_656 || 1283 did == TC_DEVICEID_HURRICANE_656B) 1284 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR | 1285 XL_FLAG_INVERT_LED_PWR; 1286 if (did == TC_DEVICEID_TORNADO_10_100BT_920B) 1287 sc->xl_flags |= XL_FLAG_PHYOK; 1288 #ifndef BURN_BRIDGES 1289 /* 1290 * If this is a 3c905B, we have to check one extra thing. 1291 * The 905B supports power management and may be placed in 1292 * a low-power mode (D3 mode), typically by certain operating 1293 * systems which shall not be named. The PCI BIOS is supposed 1294 * to reset the NIC and bring it out of low-power mode, but 1295 * some do not. Consequently, we have to see if this chip 1296 * supports power management, and if so, make sure it's not 1297 * in low-power mode. If power management is available, the 1298 * capid byte will be 0x01. 1299 * 1300 * I _think_ that what actually happens is that the chip 1301 * loses its PCI configuration during the transition from 1302 * D3 back to D0; this means that it should be possible for 1303 * us to save the PCI iobase, membase and IRQ, put the chip 1304 * back in the D0 state, then restore the PCI config ourselves. 1305 */ 1306 1307 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 1308 u_int32_t iobase, membase, irq; 1309 1310 /* Save important PCI config data. */ 1311 iobase = pci_read_config(dev, XL_PCI_LOIO, 4); 1312 membase = pci_read_config(dev, XL_PCI_LOMEM, 4); 1313 irq = pci_read_config(dev, XL_PCI_INTLINE, 4); 1314 1315 /* Reset the power state. */ 1316 device_printf(dev, "chip is in D%d power mode " 1317 "-- setting to D0\n", pci_get_powerstate(dev)); 1318 1319 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 1320 1321 /* Restore PCI config data. */ 1322 pci_write_config(dev, XL_PCI_LOIO, iobase, 4); 1323 pci_write_config(dev, XL_PCI_LOMEM, membase, 4); 1324 pci_write_config(dev, XL_PCI_INTLINE, irq, 4); 1325 } 1326 #endif 1327 /* 1328 * Map control/status registers. 1329 */ 1330 pci_enable_busmaster(dev); 1331 1332 rid = XL_PCI_LOMEM; 1333 res = SYS_RES_MEMORY; 1334 1335 #if 0 1336 sc->xl_res = bus_alloc_resource_any(dev, res, &rid, RF_ACTIVE); 1337 #endif 1338 1339 if (sc->xl_res != NULL) { 1340 sc->xl_flags |= XL_FLAG_USE_MMIO; 1341 if (bootverbose) 1342 device_printf(dev, "using memory mapped I/O\n"); 1343 } else { 1344 rid = XL_PCI_LOIO; 1345 res = SYS_RES_IOPORT; 1346 sc->xl_res = bus_alloc_resource_any(dev, res, &rid, RF_ACTIVE); 1347 if (sc->xl_res == NULL) { 1348 device_printf(dev, "couldn't map ports/memory\n"); 1349 error = ENXIO; 1350 goto fail; 1351 } 1352 if (bootverbose) 1353 device_printf(dev, "using port I/O\n"); 1354 } 1355 1356 sc->xl_btag = rman_get_bustag(sc->xl_res); 1357 sc->xl_bhandle = rman_get_bushandle(sc->xl_res); 1358 1359 if (sc->xl_flags & XL_FLAG_FUNCREG) { 1360 rid = XL_PCI_FUNCMEM; 1361 sc->xl_fres = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 1362 RF_ACTIVE); 1363 1364 if (sc->xl_fres == NULL) { 1365 device_printf(dev, "couldn't map funcreg memory\n"); 1366 error = ENXIO; 1367 goto fail; 1368 } 1369 1370 sc->xl_ftag = rman_get_bustag(sc->xl_fres); 1371 sc->xl_fhandle = rman_get_bushandle(sc->xl_fres); 1372 } 1373 1374 /* Allocate interrupt */ 1375 rid = 0; 1376 sc->xl_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1377 RF_SHAREABLE | RF_ACTIVE); 1378 if (sc->xl_irq == NULL) { 1379 device_printf(dev, "couldn't map interrupt\n"); 1380 error = ENXIO; 1381 goto fail; 1382 } 1383 1384 ifp = &sc->arpcom.ac_if; 1385 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1386 1387 /* Reset the adapter. */ 1388 xl_reset(sc); 1389 1390 /* 1391 * Get station address from the EEPROM. 1392 */ 1393 if (xl_read_eeprom(sc, (caddr_t)&eaddr, XL_EE_OEM_ADR0, 3, 1)) { 1394 device_printf(dev, "failed to read station address\n"); 1395 error = ENXIO; 1396 goto fail; 1397 } 1398 1399 callout_init(&sc->xl_stat_timer); 1400 1401 error = xl_dma_alloc(dev); 1402 if (error) 1403 goto fail; 1404 1405 /* 1406 * Figure out the card type. 3c905B adapters have the 1407 * 'supportsNoTxLength' bit set in the capabilities 1408 * word in the EEPROM. 1409 * Note: my 3c575C cardbus card lies. It returns a value 1410 * of 0x1578 for its capabilities word, which is somewhat 1411 * nonsensical. Another way to distinguish a 3c90x chip 1412 * from a 3c90xB/C chip is to check for the 'supportsLargePackets' 1413 * bit. This will only be set for 3c90x boomerage chips. 1414 */ 1415 xl_read_eeprom(sc, (caddr_t)&sc->xl_caps, XL_EE_CAPS, 1, 0); 1416 if (sc->xl_caps & XL_CAPS_NO_TXLENGTH || 1417 !(sc->xl_caps & XL_CAPS_LARGE_PKTS)) 1418 sc->xl_type = XL_TYPE_905B; 1419 else 1420 sc->xl_type = XL_TYPE_90X; 1421 if (bootverbose) { 1422 device_printf(dev, "type %s\n", 1423 sc->xl_type == XL_TYPE_905B ? "90XB" : "90X"); 1424 } 1425 1426 ifp->if_softc = sc; 1427 ifp->if_mtu = ETHERMTU; 1428 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1429 ifp->if_ioctl = xl_ioctl; 1430 if (sc->xl_type == XL_TYPE_905B) { 1431 ifp->if_start = xl_start_90xB; 1432 ifp->if_capabilities |= IFCAP_HWCSUM | IFCAP_VLAN_MTU; 1433 } else { 1434 ifp->if_start = xl_start; 1435 } 1436 ifp->if_watchdog = xl_watchdog; 1437 ifp->if_init = xl_init; 1438 #ifdef DEVICE_POLLING 1439 ifp->if_poll = xl_poll; 1440 #endif 1441 ifp->if_baudrate = 10000000; 1442 ifq_set_maxlen(&ifp->if_snd, XL_TX_LIST_CNT - 1); 1443 ifq_set_ready(&ifp->if_snd); 1444 /* 1445 * NOTE: Hardware checksum features disabled by default. 1446 * This seems to corrupt tx packet data one out of a 1447 * million packets or so and then generates a good checksum 1448 * so the receiver doesn't know the packet is bad 1449 */ 1450 ifp->if_capenable = ifp->if_capabilities & ~IFCAP_HWCSUM; 1451 if (ifp->if_capenable & IFCAP_TXCSUM) 1452 ifp->if_hwassist = XL905B_CSUM_FEATURES; 1453 1454 /* 1455 * Now we have to see what sort of media we have. 1456 * This includes probing for an MII interace and a 1457 * possible PHY. 1458 */ 1459 XL_SEL_WIN(3); 1460 sc->xl_media = CSR_READ_2(sc, XL_W3_MEDIA_OPT); 1461 if (bootverbose) 1462 if_printf(ifp, "media options word: %x\n", sc->xl_media); 1463 1464 xl_read_eeprom(sc, (char *)&xcvr, XL_EE_ICFG_0, 2, 0); 1465 sc->xl_xcvr = xcvr[0] | xcvr[1] << 16; 1466 sc->xl_xcvr &= XL_ICFG_CONNECTOR_MASK; 1467 sc->xl_xcvr >>= XL_ICFG_CONNECTOR_BITS; 1468 1469 xl_mediacheck(sc); 1470 1471 if (sc->xl_media & XL_MEDIAOPT_MII || sc->xl_media & XL_MEDIAOPT_BTX 1472 || sc->xl_media & XL_MEDIAOPT_BT4) { 1473 if (bootverbose) 1474 if_printf(ifp, "found MII/AUTO\n"); 1475 xl_setcfg(sc); 1476 1477 error = mii_phy_probe(dev, &sc->xl_miibus, 1478 xl_ifmedia_upd, xl_ifmedia_sts); 1479 if (error) { 1480 if_printf(ifp, "no PHY found!\n"); 1481 goto fail; 1482 } 1483 1484 goto done; 1485 } 1486 1487 /* 1488 * Sanity check. If the user has selected "auto" and this isn't 1489 * a 10/100 card of some kind, we need to force the transceiver 1490 * type to something sane. 1491 */ 1492 if (sc->xl_xcvr == XL_XCVR_AUTO) 1493 xl_choose_xcvr(sc, bootverbose); 1494 1495 /* 1496 * Do ifmedia setup. 1497 */ 1498 if (sc->xl_media & XL_MEDIAOPT_BT) { 1499 if (bootverbose) 1500 if_printf(ifp, "found 10baseT\n"); 1501 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL); 1502 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T|IFM_HDX, 0, NULL); 1503 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX) 1504 ifmedia_add(&sc->ifmedia, 1505 IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL); 1506 } 1507 1508 if (sc->xl_media & (XL_MEDIAOPT_AUI|XL_MEDIAOPT_10FL)) { 1509 /* 1510 * Check for a 10baseFL board in disguise. 1511 */ 1512 if (sc->xl_type == XL_TYPE_905B && 1513 sc->xl_media == XL_MEDIAOPT_10FL) { 1514 if (bootverbose) 1515 if_printf(ifp, "found 10baseFL\n"); 1516 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_FL, 0, NULL); 1517 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_FL|IFM_HDX, 1518 0, NULL); 1519 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX) 1520 ifmedia_add(&sc->ifmedia, 1521 IFM_ETHER|IFM_10_FL|IFM_FDX, 0, NULL); 1522 } else { 1523 if (bootverbose) 1524 if_printf(ifp, "found AUI\n"); 1525 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_5, 0, NULL); 1526 } 1527 } 1528 1529 if (sc->xl_media & XL_MEDIAOPT_BNC) { 1530 if (bootverbose) 1531 if_printf(ifp, "found BNC\n"); 1532 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_2, 0, NULL); 1533 } 1534 1535 if (sc->xl_media & XL_MEDIAOPT_BFX) { 1536 if (bootverbose) 1537 if_printf(ifp, "found 100baseFX\n"); 1538 ifp->if_baudrate = 100000000; 1539 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_FX, 0, NULL); 1540 } 1541 1542 /* Choose a default media. */ 1543 switch(sc->xl_xcvr) { 1544 case XL_XCVR_10BT: 1545 media = IFM_ETHER|IFM_10_T; 1546 xl_setmode(sc, media); 1547 break; 1548 case XL_XCVR_AUI: 1549 if (sc->xl_type == XL_TYPE_905B && 1550 sc->xl_media == XL_MEDIAOPT_10FL) { 1551 media = IFM_ETHER|IFM_10_FL; 1552 xl_setmode(sc, media); 1553 } else { 1554 media = IFM_ETHER|IFM_10_5; 1555 xl_setmode(sc, media); 1556 } 1557 break; 1558 case XL_XCVR_COAX: 1559 media = IFM_ETHER|IFM_10_2; 1560 xl_setmode(sc, media); 1561 break; 1562 case XL_XCVR_AUTO: 1563 case XL_XCVR_100BTX: 1564 case XL_XCVR_MII: 1565 /* Chosen by miibus */ 1566 break; 1567 case XL_XCVR_100BFX: 1568 media = IFM_ETHER|IFM_100_FX; 1569 break; 1570 default: 1571 if_printf(ifp, "unknown XCVR type: %d\n", sc->xl_xcvr); 1572 /* 1573 * This will probably be wrong, but it prevents 1574 * the ifmedia code from panicking. 1575 */ 1576 media = IFM_ETHER|IFM_10_T; 1577 break; 1578 } 1579 1580 if (sc->xl_miibus == NULL) 1581 ifmedia_set(&sc->ifmedia, media); 1582 1583 done: 1584 1585 if (sc->xl_flags & XL_FLAG_NO_XCVR_PWR) { 1586 XL_SEL_WIN(0); 1587 CSR_WRITE_2(sc, XL_W0_MFG_ID, XL_NO_XCVR_PWR_MAGICBITS); 1588 } 1589 1590 /* 1591 * Call MI attach routine. 1592 */ 1593 ether_ifattach(ifp, eaddr, NULL); 1594 1595 /* 1596 * Tell the upper layer(s) we support long frames. 1597 */ 1598 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1599 1600 /* Hook interrupt last to avoid having to lock softc */ 1601 error = bus_setup_intr(dev, sc->xl_irq, INTR_MPSAFE, 1602 xl_intr, sc, &sc->xl_intrhand, 1603 ifp->if_serializer); 1604 if (error) { 1605 if_printf(ifp, "couldn't set up irq\n"); 1606 ether_ifdetach(ifp); 1607 goto fail; 1608 } 1609 1610 ifp->if_cpuid = ithread_cpuid(rman_get_start(sc->xl_irq)); 1611 KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus); 1612 1613 return 0; 1614 1615 fail: 1616 xl_detach(dev); 1617 return error; 1618 } 1619 1620 /* 1621 * Shutdown hardware and free up resources. This can be called any 1622 * time after the mutex has been initialized. It is called in both 1623 * the error case in attach and the normal detach case so it needs 1624 * to be careful about only freeing resources that have actually been 1625 * allocated. 1626 */ 1627 static int 1628 xl_detach(device_t dev) 1629 { 1630 struct xl_softc *sc; 1631 struct ifnet *ifp; 1632 int rid, res; 1633 1634 sc = device_get_softc(dev); 1635 ifp = &sc->arpcom.ac_if; 1636 1637 if (sc->xl_flags & XL_FLAG_USE_MMIO) { 1638 rid = XL_PCI_LOMEM; 1639 res = SYS_RES_MEMORY; 1640 } else { 1641 rid = XL_PCI_LOIO; 1642 res = SYS_RES_IOPORT; 1643 } 1644 1645 if (device_is_attached(dev)) { 1646 lwkt_serialize_enter(ifp->if_serializer); 1647 xl_reset(sc); 1648 xl_stop(sc); 1649 bus_teardown_intr(dev, sc->xl_irq, sc->xl_intrhand); 1650 lwkt_serialize_exit(ifp->if_serializer); 1651 1652 ether_ifdetach(ifp); 1653 } 1654 1655 if (sc->xl_miibus) 1656 device_delete_child(dev, sc->xl_miibus); 1657 bus_generic_detach(dev); 1658 ifmedia_removeall(&sc->ifmedia); 1659 1660 if (sc->xl_irq) 1661 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->xl_irq); 1662 if (sc->xl_fres != NULL) 1663 bus_release_resource(dev, SYS_RES_MEMORY, 1664 XL_PCI_FUNCMEM, sc->xl_fres); 1665 if (sc->xl_res) 1666 bus_release_resource(dev, res, rid, sc->xl_res); 1667 1668 xl_dma_free(dev); 1669 1670 return(0); 1671 } 1672 1673 static int 1674 xl_dma_alloc(device_t dev) 1675 { 1676 struct xl_softc *sc; 1677 struct xl_chain_data *cd; 1678 struct xl_list_data *ld; 1679 int i, error; 1680 1681 sc = device_get_softc(dev); 1682 cd = &sc->xl_cdata; 1683 ld = &sc->xl_ldata; 1684 1685 /* 1686 * Now allocate a tag for the DMA descriptor lists and a chunk 1687 * of DMA-able memory based on the tag. Also obtain the DMA 1688 * addresses of the RX and TX ring, which we'll need later. 1689 * All of our lists are allocated as a contiguous block 1690 * of memory. 1691 */ 1692 error = bus_dma_tag_create(NULL, 8, 0, 1693 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, 1694 NULL, NULL, 1695 XL_RX_LIST_SZ, 1, XL_RX_LIST_SZ, 1696 0, &ld->xl_rx_tag); 1697 if (error) { 1698 device_printf(dev, "failed to allocate rx dma tag\n"); 1699 return error; 1700 } 1701 1702 error = bus_dmamem_alloc(ld->xl_rx_tag, (void **)&ld->xl_rx_list, 1703 BUS_DMA_WAITOK | BUS_DMA_ZERO, 1704 &ld->xl_rx_dmamap); 1705 if (error) { 1706 device_printf(dev, "no memory for rx list buffers!\n"); 1707 bus_dma_tag_destroy(ld->xl_rx_tag); 1708 ld->xl_rx_tag = NULL; 1709 return error; 1710 } 1711 1712 error = bus_dmamap_load(ld->xl_rx_tag, ld->xl_rx_dmamap, 1713 ld->xl_rx_list, XL_RX_LIST_SZ, 1714 xl_dma_map_addr, &ld->xl_rx_dmaaddr, 1715 BUS_DMA_WAITOK); 1716 if (error) { 1717 device_printf(dev, "cannot get dma address of the rx ring!\n"); 1718 bus_dmamem_free(ld->xl_rx_tag, ld->xl_rx_list, 1719 ld->xl_rx_dmamap); 1720 bus_dma_tag_destroy(ld->xl_rx_tag); 1721 ld->xl_rx_tag = NULL; 1722 return error; 1723 } 1724 1725 error = bus_dma_tag_create(NULL, 8, 0, 1726 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, 1727 NULL, NULL, 1728 XL_TX_LIST_SZ, 1, XL_TX_LIST_SZ, 1729 0, &ld->xl_tx_tag); 1730 if (error) { 1731 device_printf(dev, "failed to allocate tx dma tag\n"); 1732 return error; 1733 } 1734 1735 error = bus_dmamem_alloc(ld->xl_tx_tag, (void **)&ld->xl_tx_list, 1736 BUS_DMA_WAITOK | BUS_DMA_ZERO, 1737 &ld->xl_tx_dmamap); 1738 if (error) { 1739 device_printf(dev, "no memory for list buffers!\n"); 1740 bus_dma_tag_destroy(ld->xl_tx_tag); 1741 ld->xl_tx_tag = NULL; 1742 return error; 1743 } 1744 1745 error = bus_dmamap_load(ld->xl_tx_tag, ld->xl_tx_dmamap, 1746 ld->xl_tx_list, XL_TX_LIST_SZ, 1747 xl_dma_map_addr, &ld->xl_tx_dmaaddr, 1748 BUS_DMA_WAITOK); 1749 if (error) { 1750 device_printf(dev, "cannot get dma address of the tx ring!\n"); 1751 bus_dmamem_free(ld->xl_tx_tag, ld->xl_tx_list, 1752 ld->xl_tx_dmamap); 1753 bus_dma_tag_destroy(ld->xl_tx_tag); 1754 ld->xl_tx_tag = NULL; 1755 return error; 1756 } 1757 1758 /* 1759 * Allocate a DMA tag for the mapping of mbufs. 1760 */ 1761 error = bus_dma_tag_create(NULL, 1, 0, 1762 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, 1763 NULL, NULL, 1764 MCLBYTES * XL_MAXFRAGS, XL_MAXFRAGS, 1765 MCLBYTES, 0, &sc->xl_mtag); 1766 if (error) { 1767 device_printf(dev, "failed to allocate mbuf dma tag\n"); 1768 return error; 1769 } 1770 1771 /* 1772 * Allocate a spare DMA map for the RX ring. 1773 */ 1774 error = bus_dmamap_create(sc->xl_mtag, 0, &sc->xl_tmpmap); 1775 if (error) { 1776 device_printf(dev, "failed to create mbuf dma map\n"); 1777 bus_dma_tag_destroy(sc->xl_mtag); 1778 sc->xl_mtag = NULL; 1779 return error; 1780 } 1781 1782 for (i = 0; i < XL_RX_LIST_CNT; i++) { 1783 error = bus_dmamap_create(sc->xl_mtag, 0, 1784 &cd->xl_rx_chain[i].xl_map); 1785 if (error) { 1786 device_printf(dev, "failed to create %dth " 1787 "rx descriptor dma map!\n", i); 1788 return error; 1789 } 1790 cd->xl_rx_chain[i].xl_ptr = &ld->xl_rx_list[i]; 1791 } 1792 1793 for (i = 0; i < XL_TX_LIST_CNT; i++) { 1794 error = bus_dmamap_create(sc->xl_mtag, 0, 1795 &cd->xl_tx_chain[i].xl_map); 1796 if (error) { 1797 device_printf(dev, "failed to create %dth " 1798 "tx descriptor dma map!\n", i); 1799 return error; 1800 } 1801 cd->xl_tx_chain[i].xl_ptr = &ld->xl_tx_list[i]; 1802 } 1803 return 0; 1804 } 1805 1806 static void 1807 xl_dma_free(device_t dev) 1808 { 1809 struct xl_softc *sc; 1810 struct xl_chain_data *cd; 1811 struct xl_list_data *ld; 1812 int i; 1813 1814 sc = device_get_softc(dev); 1815 cd = &sc->xl_cdata; 1816 ld = &sc->xl_ldata; 1817 1818 for (i = 0; i < XL_RX_LIST_CNT; ++i) { 1819 if (cd->xl_rx_chain[i].xl_ptr != NULL) { 1820 if (cd->xl_rx_chain[i].xl_mbuf != NULL) { 1821 bus_dmamap_unload(sc->xl_mtag, 1822 cd->xl_rx_chain[i].xl_map); 1823 m_freem(cd->xl_rx_chain[i].xl_mbuf); 1824 } 1825 bus_dmamap_destroy(sc->xl_mtag, 1826 cd->xl_rx_chain[i].xl_map); 1827 } 1828 } 1829 1830 for (i = 0; i < XL_TX_LIST_CNT; ++i) { 1831 if (cd->xl_tx_chain[i].xl_ptr != NULL) { 1832 if (cd->xl_tx_chain[i].xl_mbuf != NULL) { 1833 bus_dmamap_unload(sc->xl_mtag, 1834 cd->xl_tx_chain[i].xl_map); 1835 m_freem(cd->xl_tx_chain[i].xl_mbuf); 1836 } 1837 bus_dmamap_destroy(sc->xl_mtag, 1838 cd->xl_tx_chain[i].xl_map); 1839 } 1840 } 1841 1842 if (ld->xl_rx_tag) { 1843 bus_dmamap_unload(ld->xl_rx_tag, ld->xl_rx_dmamap); 1844 bus_dmamem_free(ld->xl_rx_tag, ld->xl_rx_list, 1845 ld->xl_rx_dmamap); 1846 bus_dma_tag_destroy(ld->xl_rx_tag); 1847 } 1848 1849 if (ld->xl_tx_tag) { 1850 bus_dmamap_unload(ld->xl_tx_tag, ld->xl_tx_dmamap); 1851 bus_dmamem_free(ld->xl_tx_tag, ld->xl_tx_list, 1852 ld->xl_tx_dmamap); 1853 bus_dma_tag_destroy(ld->xl_tx_tag); 1854 } 1855 1856 if (sc->xl_mtag) { 1857 bus_dmamap_destroy(sc->xl_mtag, sc->xl_tmpmap); 1858 bus_dma_tag_destroy(sc->xl_mtag); 1859 } 1860 } 1861 1862 /* 1863 * Initialize the transmit descriptors. 1864 */ 1865 static void 1866 xl_list_tx_init(struct xl_softc *sc) 1867 { 1868 struct xl_chain_data *cd; 1869 struct xl_list_data *ld; 1870 int i; 1871 1872 cd = &sc->xl_cdata; 1873 ld = &sc->xl_ldata; 1874 for (i = 0; i < XL_TX_LIST_CNT; i++) { 1875 cd->xl_tx_chain[i].xl_phys = ld->xl_tx_dmaaddr + 1876 i * sizeof(struct xl_list); 1877 if (i == (XL_TX_LIST_CNT - 1)) 1878 cd->xl_tx_chain[i].xl_next = NULL; 1879 else 1880 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[i + 1]; 1881 } 1882 1883 cd->xl_tx_free = &cd->xl_tx_chain[0]; 1884 cd->xl_tx_tail = cd->xl_tx_head = NULL; 1885 1886 bus_dmamap_sync(ld->xl_tx_tag, ld->xl_tx_dmamap, BUS_DMASYNC_PREWRITE); 1887 } 1888 1889 /* 1890 * Initialize the transmit descriptors. 1891 */ 1892 static void 1893 xl_list_tx_init_90xB(struct xl_softc *sc) 1894 { 1895 struct xl_chain_data *cd; 1896 struct xl_list_data *ld; 1897 int i; 1898 1899 cd = &sc->xl_cdata; 1900 ld = &sc->xl_ldata; 1901 for (i = 0; i < XL_TX_LIST_CNT; i++) { 1902 cd->xl_tx_chain[i].xl_phys = ld->xl_tx_dmaaddr + 1903 i * sizeof(struct xl_list); 1904 if (i == (XL_TX_LIST_CNT - 1)) 1905 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[0]; 1906 else 1907 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[i + 1]; 1908 if (i == 0) { 1909 cd->xl_tx_chain[i].xl_prev = 1910 &cd->xl_tx_chain[XL_TX_LIST_CNT - 1]; 1911 } else { 1912 cd->xl_tx_chain[i].xl_prev = 1913 &cd->xl_tx_chain[i - 1]; 1914 } 1915 } 1916 1917 ld->xl_tx_list[0].xl_status = htole32(XL_TXSTAT_EMPTY); 1918 1919 cd->xl_tx_prod = 1; 1920 cd->xl_tx_cons = 1; 1921 cd->xl_tx_cnt = 0; 1922 1923 bus_dmamap_sync(ld->xl_tx_tag, ld->xl_tx_dmamap, BUS_DMASYNC_PREWRITE); 1924 } 1925 1926 /* 1927 * Initialize the RX descriptors and allocate mbufs for them. Note that 1928 * we arrange the descriptors in a closed ring, so that the last descriptor 1929 * points back to the first. 1930 */ 1931 static int 1932 xl_list_rx_init(struct xl_softc *sc) 1933 { 1934 struct xl_chain_data *cd; 1935 struct xl_list_data *ld; 1936 int error, i, next; 1937 u_int32_t nextptr; 1938 1939 cd = &sc->xl_cdata; 1940 ld = &sc->xl_ldata; 1941 1942 for (i = 0; i < XL_RX_LIST_CNT; i++) { 1943 error = xl_newbuf(sc, &cd->xl_rx_chain[i]); 1944 if (error) 1945 return(error); 1946 if (i == (XL_RX_LIST_CNT - 1)) 1947 next = 0; 1948 else 1949 next = i + 1; 1950 nextptr = ld->xl_rx_dmaaddr + 1951 next * sizeof(struct xl_list_onefrag); 1952 cd->xl_rx_chain[i].xl_next = &cd->xl_rx_chain[next]; 1953 ld->xl_rx_list[i].xl_next = htole32(nextptr); 1954 } 1955 1956 bus_dmamap_sync(ld->xl_rx_tag, ld->xl_rx_dmamap, BUS_DMASYNC_PREWRITE); 1957 cd->xl_rx_head = &cd->xl_rx_chain[0]; 1958 1959 return(0); 1960 } 1961 1962 /* 1963 * Initialize an RX descriptor and attach an MBUF cluster. 1964 * If we fail to do so, we need to leave the old mbuf and 1965 * the old DMA map untouched so that it can be reused. 1966 */ 1967 static int 1968 xl_newbuf(struct xl_softc *sc, struct xl_chain_onefrag *c) 1969 { 1970 struct mbuf *m_new; 1971 bus_dmamap_t map; 1972 int error; 1973 u_int32_t baddr; 1974 1975 m_new = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR); 1976 if (m_new == NULL) 1977 return(ENOBUFS); 1978 1979 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1980 1981 /* Force longword alignment for packet payload. */ 1982 m_adj(m_new, ETHER_ALIGN); 1983 1984 error = bus_dmamap_load_mbuf(sc->xl_mtag, sc->xl_tmpmap, m_new, 1985 xl_dma_map_rxbuf, &baddr, BUS_DMA_NOWAIT); 1986 if (error) { 1987 m_freem(m_new); 1988 if_printf(&sc->arpcom.ac_if, "can't map mbuf (error %d)\n", 1989 error); 1990 return(error); 1991 } 1992 1993 bus_dmamap_unload(sc->xl_mtag, c->xl_map); 1994 map = c->xl_map; 1995 c->xl_map = sc->xl_tmpmap; 1996 sc->xl_tmpmap = map; 1997 c->xl_mbuf = m_new; 1998 c->xl_ptr->xl_frag.xl_len = htole32(m_new->m_len | XL_LAST_FRAG); 1999 c->xl_ptr->xl_status = 0; 2000 c->xl_ptr->xl_frag.xl_addr = htole32(baddr); 2001 bus_dmamap_sync(sc->xl_mtag, c->xl_map, BUS_DMASYNC_PREREAD); 2002 return(0); 2003 } 2004 2005 static int 2006 xl_rx_resync(struct xl_softc *sc) 2007 { 2008 struct xl_chain_onefrag *pos; 2009 int i; 2010 2011 pos = sc->xl_cdata.xl_rx_head; 2012 2013 for (i = 0; i < XL_RX_LIST_CNT; i++) { 2014 if (pos->xl_ptr->xl_status) 2015 break; 2016 pos = pos->xl_next; 2017 } 2018 2019 if (i == XL_RX_LIST_CNT) 2020 return(0); 2021 2022 sc->xl_cdata.xl_rx_head = pos; 2023 2024 return(EAGAIN); 2025 } 2026 2027 /* 2028 * A frame has been uploaded: pass the resulting mbuf chain up to 2029 * the higher level protocols. 2030 */ 2031 static void 2032 xl_rxeof(struct xl_softc *sc, int count) 2033 { 2034 struct mbuf *m; 2035 struct ifnet *ifp; 2036 struct xl_chain_onefrag *cur_rx; 2037 int total_len = 0; 2038 u_int32_t rxstat; 2039 #ifdef ETHER_INPUT_CHAIN 2040 struct mbuf_chain chain[MAXCPU]; 2041 #endif 2042 2043 ifp = &sc->arpcom.ac_if; 2044 2045 #ifdef ETHER_INPUT_CHAIN 2046 ether_input_chain_init(chain); 2047 #endif 2048 2049 again: 2050 2051 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag, sc->xl_ldata.xl_rx_dmamap, 2052 BUS_DMASYNC_POSTREAD); 2053 while((rxstat = le32toh(sc->xl_cdata.xl_rx_head->xl_ptr->xl_status))) { 2054 #ifdef DEVICE_POLLING 2055 if (count >= 0 && count-- == 0) 2056 break; 2057 #endif 2058 cur_rx = sc->xl_cdata.xl_rx_head; 2059 sc->xl_cdata.xl_rx_head = cur_rx->xl_next; 2060 total_len = rxstat & XL_RXSTAT_LENMASK; 2061 2062 /* 2063 * Since we have told the chip to allow large frames, 2064 * we need to trap giant frame errors in software. We allow 2065 * a little more than the normal frame size to account for 2066 * frames with VLAN tags. 2067 */ 2068 if (total_len > XL_MAX_FRAMELEN) 2069 rxstat |= (XL_RXSTAT_UP_ERROR|XL_RXSTAT_OVERSIZE); 2070 2071 /* 2072 * If an error occurs, update stats, clear the 2073 * status word and leave the mbuf cluster in place: 2074 * it should simply get re-used next time this descriptor 2075 * comes up in the ring. 2076 */ 2077 if (rxstat & XL_RXSTAT_UP_ERROR) { 2078 ifp->if_ierrors++; 2079 cur_rx->xl_ptr->xl_status = 0; 2080 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag, 2081 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE); 2082 continue; 2083 } 2084 2085 /* 2086 * If the error bit was not set, the upload complete 2087 * bit should be set which means we have a valid packet. 2088 * If not, something truly strange has happened. 2089 */ 2090 if (!(rxstat & XL_RXSTAT_UP_CMPLT)) { 2091 if_printf(ifp, 2092 "bad receive status -- packet dropped\n"); 2093 ifp->if_ierrors++; 2094 cur_rx->xl_ptr->xl_status = 0; 2095 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag, 2096 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE); 2097 continue; 2098 } 2099 2100 /* No errors; receive the packet. */ 2101 bus_dmamap_sync(sc->xl_mtag, cur_rx->xl_map, 2102 BUS_DMASYNC_POSTREAD); 2103 m = cur_rx->xl_mbuf; 2104 2105 /* 2106 * Try to conjure up a new mbuf cluster. If that 2107 * fails, it means we have an out of memory condition and 2108 * should leave the buffer in place and continue. This will 2109 * result in a lost packet, but there's little else we 2110 * can do in this situation. 2111 */ 2112 if (xl_newbuf(sc, cur_rx)) { 2113 ifp->if_ierrors++; 2114 cur_rx->xl_ptr->xl_status = 0; 2115 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag, 2116 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE); 2117 continue; 2118 } 2119 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag, 2120 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE); 2121 2122 ifp->if_ipackets++; 2123 m->m_pkthdr.rcvif = ifp; 2124 m->m_pkthdr.len = m->m_len = total_len; 2125 2126 if (ifp->if_capenable & IFCAP_RXCSUM) { 2127 /* Do IP checksum checking. */ 2128 if (rxstat & XL_RXSTAT_IPCKOK) 2129 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 2130 if (!(rxstat & XL_RXSTAT_IPCKERR)) 2131 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 2132 if ((rxstat & XL_RXSTAT_TCPCOK && 2133 !(rxstat & XL_RXSTAT_TCPCKERR)) || 2134 (rxstat & XL_RXSTAT_UDPCKOK && 2135 !(rxstat & XL_RXSTAT_UDPCKERR))) { 2136 m->m_pkthdr.csum_flags |= 2137 CSUM_DATA_VALID|CSUM_PSEUDO_HDR| 2138 CSUM_FRAG_NOT_CHECKED; 2139 m->m_pkthdr.csum_data = 0xffff; 2140 } 2141 } 2142 2143 #ifdef ETHER_INPUT_CHAIN 2144 ether_input_chain2(ifp, m, chain); 2145 #else 2146 ifp->if_input(ifp, m); 2147 #endif 2148 } 2149 2150 if (sc->xl_type != XL_TYPE_905B) { 2151 /* 2152 * Handle the 'end of channel' condition. When the upload 2153 * engine hits the end of the RX ring, it will stall. This 2154 * is our cue to flush the RX ring, reload the uplist pointer 2155 * register and unstall the engine. 2156 * XXX This is actually a little goofy. With the ThunderLAN 2157 * chip, you get an interrupt when the receiver hits the end 2158 * of the receive ring, which tells you exactly when you 2159 * you need to reload the ring pointer. Here we have to 2160 * fake it. I'm mad at myself for not being clever enough 2161 * to avoid the use of a goto here. 2162 */ 2163 if (CSR_READ_4(sc, XL_UPLIST_PTR) == 0 || 2164 CSR_READ_4(sc, XL_UPLIST_STATUS) & XL_PKTSTAT_UP_STALLED) { 2165 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_STALL); 2166 xl_wait(sc); 2167 CSR_WRITE_4(sc, XL_UPLIST_PTR, 2168 sc->xl_ldata.xl_rx_dmaaddr); 2169 sc->xl_cdata.xl_rx_head = &sc->xl_cdata.xl_rx_chain[0]; 2170 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_UNSTALL); 2171 goto again; 2172 } 2173 } 2174 2175 #ifdef ETHER_INPUT_CHAIN 2176 ether_input_dispatch(chain); 2177 #endif 2178 } 2179 2180 /* 2181 * A frame was downloaded to the chip. It's safe for us to clean up 2182 * the list buffers. 2183 */ 2184 static void 2185 xl_txeof(struct xl_softc *sc) 2186 { 2187 struct xl_chain *cur_tx; 2188 struct ifnet *ifp; 2189 2190 ifp = &sc->arpcom.ac_if; 2191 2192 /* Clear the timeout timer. */ 2193 ifp->if_timer = 0; 2194 2195 /* 2196 * Go through our tx list and free mbufs for those 2197 * frames that have been uploaded. Note: the 3c905B 2198 * sets a special bit in the status word to let us 2199 * know that a frame has been downloaded, but the 2200 * original 3c900/3c905 adapters don't do that. 2201 * Consequently, we have to use a different test if 2202 * xl_type != XL_TYPE_905B. 2203 */ 2204 while(sc->xl_cdata.xl_tx_head != NULL) { 2205 cur_tx = sc->xl_cdata.xl_tx_head; 2206 2207 if (CSR_READ_4(sc, XL_DOWNLIST_PTR)) 2208 break; 2209 2210 sc->xl_cdata.xl_tx_head = cur_tx->xl_next; 2211 bus_dmamap_sync(sc->xl_mtag, cur_tx->xl_map, 2212 BUS_DMASYNC_POSTWRITE); 2213 bus_dmamap_unload(sc->xl_mtag, cur_tx->xl_map); 2214 m_freem(cur_tx->xl_mbuf); 2215 cur_tx->xl_mbuf = NULL; 2216 ifp->if_opackets++; 2217 2218 cur_tx->xl_next = sc->xl_cdata.xl_tx_free; 2219 sc->xl_cdata.xl_tx_free = cur_tx; 2220 } 2221 2222 if (sc->xl_cdata.xl_tx_head == NULL) { 2223 ifp->if_flags &= ~IFF_OACTIVE; 2224 sc->xl_cdata.xl_tx_tail = NULL; 2225 } else { 2226 if (CSR_READ_4(sc, XL_DMACTL) & XL_DMACTL_DOWN_STALLED || 2227 !CSR_READ_4(sc, XL_DOWNLIST_PTR)) { 2228 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, 2229 sc->xl_cdata.xl_tx_head->xl_phys); 2230 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); 2231 } 2232 } 2233 2234 return; 2235 } 2236 2237 static void 2238 xl_txeof_90xB(struct xl_softc *sc) 2239 { 2240 struct xl_chain *cur_tx = NULL; 2241 struct ifnet *ifp; 2242 int idx; 2243 2244 ifp = &sc->arpcom.ac_if; 2245 2246 bus_dmamap_sync(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_dmamap, 2247 BUS_DMASYNC_POSTREAD); 2248 idx = sc->xl_cdata.xl_tx_cons; 2249 while(idx != sc->xl_cdata.xl_tx_prod) { 2250 2251 cur_tx = &sc->xl_cdata.xl_tx_chain[idx]; 2252 2253 if (!(le32toh(cur_tx->xl_ptr->xl_status) & 2254 XL_TXSTAT_DL_COMPLETE)) 2255 break; 2256 2257 if (cur_tx->xl_mbuf != NULL) { 2258 bus_dmamap_sync(sc->xl_mtag, cur_tx->xl_map, 2259 BUS_DMASYNC_POSTWRITE); 2260 bus_dmamap_unload(sc->xl_mtag, cur_tx->xl_map); 2261 m_freem(cur_tx->xl_mbuf); 2262 cur_tx->xl_mbuf = NULL; 2263 } 2264 2265 ifp->if_opackets++; 2266 2267 sc->xl_cdata.xl_tx_cnt--; 2268 XL_INC(idx, XL_TX_LIST_CNT); 2269 ifp->if_timer = 0; 2270 } 2271 2272 sc->xl_cdata.xl_tx_cons = idx; 2273 2274 if (cur_tx != NULL) 2275 ifp->if_flags &= ~IFF_OACTIVE; 2276 2277 return; 2278 } 2279 2280 /* 2281 * TX 'end of channel' interrupt handler. Actually, we should 2282 * only get a 'TX complete' interrupt if there's a transmit error, 2283 * so this is really TX error handler. 2284 */ 2285 static void 2286 xl_txeoc(struct xl_softc *sc) 2287 { 2288 struct ifnet *ifp = &sc->arpcom.ac_if; 2289 u_int8_t txstat; 2290 2291 while((txstat = CSR_READ_1(sc, XL_TX_STATUS))) { 2292 if (txstat & XL_TXSTATUS_UNDERRUN || 2293 txstat & XL_TXSTATUS_JABBER || 2294 txstat & XL_TXSTATUS_RECLAIM) { 2295 if_printf(ifp, "transmission error: %x\n", txstat); 2296 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); 2297 xl_wait(sc); 2298 if (sc->xl_type == XL_TYPE_905B) { 2299 if (sc->xl_cdata.xl_tx_cnt) { 2300 int i; 2301 struct xl_chain *c; 2302 i = sc->xl_cdata.xl_tx_cons; 2303 c = &sc->xl_cdata.xl_tx_chain[i]; 2304 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, 2305 c->xl_phys); 2306 CSR_WRITE_1(sc, XL_DOWN_POLL, 64); 2307 } 2308 } else { 2309 if (sc->xl_cdata.xl_tx_head != NULL) 2310 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, 2311 sc->xl_cdata.xl_tx_head->xl_phys); 2312 } 2313 /* 2314 * Remember to set this for the 2315 * first generation 3c90X chips. 2316 */ 2317 CSR_WRITE_1(sc, XL_TX_FREETHRESH, XL_PACKET_SIZE >> 8); 2318 if (txstat & XL_TXSTATUS_UNDERRUN && 2319 sc->xl_tx_thresh < XL_PACKET_SIZE) { 2320 sc->xl_tx_thresh += XL_MIN_FRAMELEN; 2321 if_printf(ifp, "tx underrun, increasing tx start" 2322 " threshold to %d bytes\n", 2323 sc->xl_tx_thresh); 2324 } 2325 CSR_WRITE_2(sc, XL_COMMAND, 2326 XL_CMD_TX_SET_START|sc->xl_tx_thresh); 2327 if (sc->xl_type == XL_TYPE_905B) { 2328 CSR_WRITE_2(sc, XL_COMMAND, 2329 XL_CMD_SET_TX_RECLAIM|(XL_PACKET_SIZE >> 4)); 2330 } 2331 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE); 2332 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); 2333 } else { 2334 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE); 2335 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); 2336 } 2337 /* 2338 * Write an arbitrary byte to the TX_STATUS register 2339 * to clear this interrupt/error and advance to the next. 2340 */ 2341 CSR_WRITE_1(sc, XL_TX_STATUS, 0x01); 2342 } 2343 2344 return; 2345 } 2346 2347 #ifdef DEVICE_POLLING 2348 2349 static void 2350 xl_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 2351 { 2352 struct xl_softc *sc = ifp->if_softc; 2353 2354 ASSERT_SERIALIZED(ifp->if_serializer); 2355 2356 switch (cmd) { 2357 case POLL_REGISTER: 2358 xl_enable_intrs(sc, 0); 2359 if (sc->xl_type != XL_TYPE_905B) 2360 ifp->if_start = xl_start_poll; 2361 break; 2362 case POLL_DEREGISTER: 2363 if (sc->xl_type != XL_TYPE_905B) 2364 ifp->if_start = xl_start; 2365 xl_enable_intrs(sc, XL_INTRS); 2366 break; 2367 case POLL_ONLY: 2368 case POLL_AND_CHECK_STATUS: 2369 xl_rxeof(sc, count); 2370 if (sc->xl_type == XL_TYPE_905B) 2371 xl_txeof_90xB(sc); 2372 else 2373 xl_txeof(sc); 2374 2375 if (!ifq_is_empty(&ifp->if_snd)) 2376 if_devstart(ifp); 2377 2378 if (cmd == POLL_AND_CHECK_STATUS) { 2379 uint16_t status; 2380 2381 /* XXX copy & pasted from xl_intr() */ 2382 status = CSR_READ_2(sc, XL_STATUS); 2383 if ((status & XL_INTRS) && status != 0xFFFF) { 2384 CSR_WRITE_2(sc, XL_COMMAND, 2385 XL_CMD_INTR_ACK | (status & XL_INTRS)); 2386 2387 if (status & XL_STAT_TX_COMPLETE) { 2388 ifp->if_oerrors++; 2389 xl_txeoc(sc); 2390 } 2391 2392 if (status & XL_STAT_ADFAIL) { 2393 xl_reset(sc); 2394 xl_init(sc); 2395 } 2396 2397 if (status & XL_STAT_STATSOFLOW) { 2398 sc->xl_stats_no_timeout = 1; 2399 xl_stats_update_serialized(sc); 2400 sc->xl_stats_no_timeout = 0; 2401 } 2402 } 2403 } 2404 break; 2405 } 2406 } 2407 2408 #endif /* DEVICE_POLLING */ 2409 2410 static void 2411 xl_intr(void *arg) 2412 { 2413 struct xl_softc *sc; 2414 struct ifnet *ifp; 2415 u_int16_t status; 2416 2417 sc = arg; 2418 ifp = &sc->arpcom.ac_if; 2419 2420 ASSERT_SERIALIZED(ifp->if_serializer); 2421 2422 while(((status = CSR_READ_2(sc, XL_STATUS)) & XL_INTRS) && 2423 status != 0xFFFF) { 2424 2425 CSR_WRITE_2(sc, XL_COMMAND, 2426 XL_CMD_INTR_ACK|(status & XL_INTRS)); 2427 2428 if (status & XL_STAT_UP_COMPLETE) { 2429 int curpkts; 2430 2431 curpkts = ifp->if_ipackets; 2432 xl_rxeof(sc, -1); 2433 if (curpkts == ifp->if_ipackets) { 2434 while (xl_rx_resync(sc)) 2435 xl_rxeof(sc, -1); 2436 } 2437 } 2438 2439 if (status & XL_STAT_DOWN_COMPLETE) { 2440 if (sc->xl_type == XL_TYPE_905B) 2441 xl_txeof_90xB(sc); 2442 else 2443 xl_txeof(sc); 2444 } 2445 2446 if (status & XL_STAT_TX_COMPLETE) { 2447 ifp->if_oerrors++; 2448 xl_txeoc(sc); 2449 } 2450 2451 if (status & XL_STAT_ADFAIL) { 2452 xl_reset(sc); 2453 xl_init(sc); 2454 } 2455 2456 if (status & XL_STAT_STATSOFLOW) { 2457 sc->xl_stats_no_timeout = 1; 2458 xl_stats_update_serialized(sc); 2459 sc->xl_stats_no_timeout = 0; 2460 } 2461 } 2462 2463 if (!ifq_is_empty(&ifp->if_snd)) 2464 if_devstart(ifp); 2465 } 2466 2467 static void 2468 xl_stats_update(void *xsc) 2469 { 2470 struct xl_softc *sc = xsc; 2471 2472 lwkt_serialize_enter(sc->arpcom.ac_if.if_serializer); 2473 xl_stats_update_serialized(xsc); 2474 lwkt_serialize_exit(sc->arpcom.ac_if.if_serializer); 2475 } 2476 2477 static void 2478 xl_stats_update_serialized(void *xsc) 2479 { 2480 struct xl_softc *sc; 2481 struct ifnet *ifp; 2482 struct xl_stats xl_stats; 2483 u_int8_t *p; 2484 int i; 2485 struct mii_data *mii = NULL; 2486 2487 bzero((char *)&xl_stats, sizeof(struct xl_stats)); 2488 2489 sc = xsc; 2490 ifp = &sc->arpcom.ac_if; 2491 if (sc->xl_miibus != NULL) 2492 mii = device_get_softc(sc->xl_miibus); 2493 2494 p = (u_int8_t *)&xl_stats; 2495 2496 /* Read all the stats registers. */ 2497 XL_SEL_WIN(6); 2498 2499 for (i = 0; i < 16; i++) 2500 *p++ = CSR_READ_1(sc, XL_W6_CARRIER_LOST + i); 2501 2502 ifp->if_ierrors += xl_stats.xl_rx_overrun; 2503 2504 ifp->if_collisions += xl_stats.xl_tx_multi_collision + 2505 xl_stats.xl_tx_single_collision + 2506 xl_stats.xl_tx_late_collision; 2507 2508 /* 2509 * Boomerang and cyclone chips have an extra stats counter 2510 * in window 4 (BadSSD). We have to read this too in order 2511 * to clear out all the stats registers and avoid a statsoflow 2512 * interrupt. 2513 */ 2514 XL_SEL_WIN(4); 2515 CSR_READ_1(sc, XL_W4_BADSSD); 2516 2517 if ((mii != NULL) && (!sc->xl_stats_no_timeout)) 2518 mii_tick(mii); 2519 2520 XL_SEL_WIN(7); 2521 2522 if (!sc->xl_stats_no_timeout) 2523 callout_reset(&sc->xl_stat_timer, hz, xl_stats_update, sc); 2524 2525 return; 2526 } 2527 2528 /* 2529 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 2530 * pointers to the fragment pointers. 2531 */ 2532 static int 2533 xl_encap(struct xl_softc *sc, struct xl_chain *c, struct mbuf *m_head) 2534 { 2535 int error; 2536 u_int32_t status; 2537 struct ifnet *ifp; 2538 2539 ifp = &sc->arpcom.ac_if; 2540 2541 /* 2542 * Start packing the mbufs in this chain into 2543 * the fragment pointers. Stop when we run out 2544 * of fragments or hit the end of the mbuf chain. 2545 */ 2546 error = bus_dmamap_load_mbuf(sc->xl_mtag, c->xl_map, m_head, 2547 xl_dma_map_txbuf, c->xl_ptr, BUS_DMA_NOWAIT); 2548 2549 if (error && error != EFBIG) { 2550 m_freem(m_head); 2551 if_printf(ifp, "can't map mbuf (error %d)\n", error); 2552 return(1); 2553 } 2554 2555 /* 2556 * Handle special case: we used up all 63 fragments, 2557 * but we have more mbufs left in the chain. Copy the 2558 * data into an mbuf cluster. Note that we don't 2559 * bother clearing the values in the other fragment 2560 * pointers/counters; it wouldn't gain us anything, 2561 * and would waste cycles. 2562 */ 2563 if (error) { 2564 struct mbuf *m_new; 2565 2566 m_new = m_defrag(m_head, MB_DONTWAIT); 2567 if (m_new == NULL) { 2568 m_freem(m_head); 2569 return(1); 2570 } else { 2571 m_head = m_new; 2572 } 2573 2574 error = bus_dmamap_load_mbuf(sc->xl_mtag, c->xl_map, 2575 m_head, xl_dma_map_txbuf, c->xl_ptr, BUS_DMA_NOWAIT); 2576 if (error) { 2577 m_freem(m_head); 2578 if_printf(ifp, "can't map mbuf (error %d)\n", error); 2579 return(1); 2580 } 2581 } 2582 2583 if (sc->xl_type == XL_TYPE_905B) { 2584 status = XL_TXSTAT_RND_DEFEAT; 2585 2586 if (m_head->m_pkthdr.csum_flags) { 2587 if (m_head->m_pkthdr.csum_flags & CSUM_IP) 2588 status |= XL_TXSTAT_IPCKSUM; 2589 if (m_head->m_pkthdr.csum_flags & CSUM_TCP) 2590 status |= XL_TXSTAT_TCPCKSUM; 2591 if (m_head->m_pkthdr.csum_flags & CSUM_UDP) 2592 status |= XL_TXSTAT_UDPCKSUM; 2593 } 2594 c->xl_ptr->xl_status = htole32(status); 2595 } 2596 2597 c->xl_mbuf = m_head; 2598 bus_dmamap_sync(sc->xl_mtag, c->xl_map, BUS_DMASYNC_PREWRITE); 2599 return(0); 2600 } 2601 2602 static void 2603 xl_start(struct ifnet *ifp) 2604 { 2605 ASSERT_SERIALIZED(ifp->if_serializer); 2606 xl_start_body(ifp, 1); 2607 } 2608 2609 static void 2610 xl_start_poll(struct ifnet *ifp) 2611 { 2612 xl_start_body(ifp, 0); 2613 } 2614 2615 /* 2616 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 2617 * to the mbuf data regions directly in the transmit lists. We also save a 2618 * copy of the pointers since the transmit list fragment pointers are 2619 * physical addresses. 2620 */ 2621 static void 2622 xl_start_body(struct ifnet *ifp, int proc_rx) 2623 { 2624 struct xl_softc *sc; 2625 struct mbuf *m_head = NULL; 2626 struct xl_chain *prev = NULL, *cur_tx = NULL, *start_tx; 2627 struct xl_chain *prev_tx; 2628 u_int32_t status; 2629 int error; 2630 2631 sc = ifp->if_softc; 2632 /* 2633 * Check for an available queue slot. If there are none, 2634 * punt. 2635 */ 2636 if (sc->xl_cdata.xl_tx_free == NULL) { 2637 xl_txeoc(sc); 2638 xl_txeof(sc); 2639 if (sc->xl_cdata.xl_tx_free == NULL) { 2640 ifp->if_flags |= IFF_OACTIVE; 2641 return; 2642 } 2643 } 2644 2645 start_tx = sc->xl_cdata.xl_tx_free; 2646 2647 while(sc->xl_cdata.xl_tx_free != NULL) { 2648 m_head = ifq_dequeue(&ifp->if_snd, NULL); 2649 if (m_head == NULL) 2650 break; 2651 2652 /* Pick a descriptor off the free list. */ 2653 prev_tx = cur_tx; 2654 cur_tx = sc->xl_cdata.xl_tx_free; 2655 2656 /* Pack the data into the descriptor. */ 2657 error = xl_encap(sc, cur_tx, m_head); 2658 if (error) { 2659 cur_tx = prev_tx; 2660 continue; 2661 } 2662 2663 sc->xl_cdata.xl_tx_free = cur_tx->xl_next; 2664 cur_tx->xl_next = NULL; 2665 2666 /* Chain it together. */ 2667 if (prev != NULL) { 2668 prev->xl_next = cur_tx; 2669 prev->xl_ptr->xl_next = htole32(cur_tx->xl_phys); 2670 } 2671 prev = cur_tx; 2672 2673 BPF_MTAP(ifp, cur_tx->xl_mbuf); 2674 } 2675 2676 /* 2677 * If there are no packets queued, bail. 2678 */ 2679 if (cur_tx == NULL) 2680 return; 2681 2682 /* 2683 * Place the request for the upload interrupt 2684 * in the last descriptor in the chain. This way, if 2685 * we're chaining several packets at once, we'll only 2686 * get an interupt once for the whole chain rather than 2687 * once for each packet. 2688 */ 2689 cur_tx->xl_ptr->xl_status = htole32(le32toh(cur_tx->xl_ptr->xl_status) | 2690 XL_TXSTAT_DL_INTR); 2691 2692 /* 2693 * Queue the packets. If the TX channel is clear, update 2694 * the downlist pointer register. 2695 */ 2696 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_STALL); 2697 xl_wait(sc); 2698 2699 if (sc->xl_cdata.xl_tx_head != NULL) { 2700 sc->xl_cdata.xl_tx_tail->xl_next = start_tx; 2701 sc->xl_cdata.xl_tx_tail->xl_ptr->xl_next = 2702 htole32(start_tx->xl_phys); 2703 status = sc->xl_cdata.xl_tx_tail->xl_ptr->xl_status; 2704 sc->xl_cdata.xl_tx_tail->xl_ptr->xl_status = 2705 htole32(le32toh(status) & ~XL_TXSTAT_DL_INTR); 2706 sc->xl_cdata.xl_tx_tail = cur_tx; 2707 } else { 2708 sc->xl_cdata.xl_tx_head = start_tx; 2709 sc->xl_cdata.xl_tx_tail = cur_tx; 2710 } 2711 bus_dmamap_sync(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_dmamap, 2712 BUS_DMASYNC_PREWRITE); 2713 2714 if (!CSR_READ_4(sc, XL_DOWNLIST_PTR)) 2715 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, start_tx->xl_phys); 2716 2717 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); 2718 2719 XL_SEL_WIN(7); 2720 2721 /* 2722 * Set a timeout in case the chip goes out to lunch. 2723 */ 2724 ifp->if_timer = 5; 2725 2726 if (proc_rx) { 2727 /* 2728 * XXX Under certain conditions, usually on slower machines 2729 * where interrupts may be dropped, it's possible for the 2730 * adapter to chew up all the buffers in the receive ring 2731 * and stall, without us being able to do anything about it. 2732 * To guard against this, we need to make a pass over the 2733 * RX queue to make sure there aren't any packets pending. 2734 * Doing it here means we can flush the receive ring at the 2735 * same time the chip is DMAing the transmit descriptors we 2736 * just gave it. 2737 * 2738 * 3Com goes to some lengths to emphasize the Parallel 2739 * Tasking (tm) nature of their chips in all their marketing 2740 * literature; we may as well take advantage of it. :) 2741 */ 2742 xl_rxeof(sc, -1); 2743 } 2744 } 2745 2746 static void 2747 xl_start_90xB(struct ifnet *ifp) 2748 { 2749 struct xl_softc *sc; 2750 struct mbuf *m_head = NULL; 2751 struct xl_chain *prev = NULL, *cur_tx = NULL, *start_tx; 2752 struct xl_chain *prev_tx; 2753 int error, idx; 2754 2755 ASSERT_SERIALIZED(ifp->if_serializer); 2756 2757 sc = ifp->if_softc; 2758 2759 if ((ifp->if_flags & (IFF_OACTIVE | IFF_RUNNING)) != IFF_RUNNING) 2760 return; 2761 2762 idx = sc->xl_cdata.xl_tx_prod; 2763 start_tx = &sc->xl_cdata.xl_tx_chain[idx]; 2764 2765 while (sc->xl_cdata.xl_tx_chain[idx].xl_mbuf == NULL) { 2766 2767 if ((XL_TX_LIST_CNT - sc->xl_cdata.xl_tx_cnt) < 3) { 2768 ifp->if_flags |= IFF_OACTIVE; 2769 break; 2770 } 2771 2772 m_head = ifq_dequeue(&ifp->if_snd, NULL); 2773 if (m_head == NULL) 2774 break; 2775 2776 prev_tx = cur_tx; 2777 cur_tx = &sc->xl_cdata.xl_tx_chain[idx]; 2778 2779 /* Pack the data into the descriptor. */ 2780 error = xl_encap(sc, cur_tx, m_head); 2781 if (error) { 2782 cur_tx = prev_tx; 2783 continue; 2784 } 2785 2786 /* Chain it together. */ 2787 if (prev != NULL) 2788 prev->xl_ptr->xl_next = htole32(cur_tx->xl_phys); 2789 prev = cur_tx; 2790 2791 BPF_MTAP(ifp, cur_tx->xl_mbuf); 2792 2793 XL_INC(idx, XL_TX_LIST_CNT); 2794 sc->xl_cdata.xl_tx_cnt++; 2795 } 2796 2797 /* 2798 * If there are no packets queued, bail. 2799 */ 2800 if (cur_tx == NULL) 2801 return; 2802 2803 /* 2804 * Place the request for the upload interrupt 2805 * in the last descriptor in the chain. This way, if 2806 * we're chaining several packets at once, we'll only 2807 * get an interupt once for the whole chain rather than 2808 * once for each packet. 2809 */ 2810 cur_tx->xl_ptr->xl_status = htole32(le32toh(cur_tx->xl_ptr->xl_status) | 2811 XL_TXSTAT_DL_INTR); 2812 2813 /* Start transmission */ 2814 sc->xl_cdata.xl_tx_prod = idx; 2815 start_tx->xl_prev->xl_ptr->xl_next = htole32(start_tx->xl_phys); 2816 2817 bus_dmamap_sync(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_dmamap, 2818 BUS_DMASYNC_PREWRITE); 2819 2820 /* 2821 * Set a timeout in case the chip goes out to lunch. 2822 */ 2823 ifp->if_timer = 5; 2824 } 2825 2826 static void 2827 xl_init(void *xsc) 2828 { 2829 struct xl_softc *sc = xsc; 2830 struct ifnet *ifp = &sc->arpcom.ac_if; 2831 int error, i; 2832 u_int16_t rxfilt = 0; 2833 struct mii_data *mii = NULL; 2834 2835 ASSERT_SERIALIZED(ifp->if_serializer); 2836 2837 /* 2838 * Cancel pending I/O and free all RX/TX buffers. 2839 */ 2840 xl_stop(sc); 2841 2842 if (sc->xl_miibus == NULL) { 2843 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET); 2844 xl_wait(sc); 2845 } 2846 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); 2847 xl_wait(sc); 2848 DELAY(10000); 2849 2850 if (sc->xl_miibus != NULL) 2851 mii = device_get_softc(sc->xl_miibus); 2852 2853 /* Init our MAC address */ 2854 XL_SEL_WIN(2); 2855 for (i = 0; i < ETHER_ADDR_LEN; i++) { 2856 CSR_WRITE_1(sc, XL_W2_STATION_ADDR_LO + i, 2857 sc->arpcom.ac_enaddr[i]); 2858 } 2859 2860 /* Clear the station mask. */ 2861 for (i = 0; i < 3; i++) 2862 CSR_WRITE_2(sc, XL_W2_STATION_MASK_LO + (i * 2), 0); 2863 #ifdef notdef 2864 /* Reset TX and RX. */ 2865 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET); 2866 xl_wait(sc); 2867 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); 2868 xl_wait(sc); 2869 #endif 2870 /* Init circular RX list. */ 2871 error = xl_list_rx_init(sc); 2872 if (error) { 2873 if_printf(ifp, "initialization of the rx ring failed (%d)\n", 2874 error); 2875 xl_stop(sc); 2876 return; 2877 } 2878 2879 /* Init TX descriptors. */ 2880 if (sc->xl_type == XL_TYPE_905B) 2881 xl_list_tx_init_90xB(sc); 2882 else 2883 xl_list_tx_init(sc); 2884 2885 /* 2886 * Set the TX freethresh value. 2887 * Note that this has no effect on 3c905B "cyclone" 2888 * cards but is required for 3c900/3c905 "boomerang" 2889 * cards in order to enable the download engine. 2890 */ 2891 CSR_WRITE_1(sc, XL_TX_FREETHRESH, XL_PACKET_SIZE >> 8); 2892 2893 /* Set the TX start threshold for best performance. */ 2894 sc->xl_tx_thresh = XL_MIN_FRAMELEN; 2895 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_SET_START|sc->xl_tx_thresh); 2896 2897 /* 2898 * If this is a 3c905B, also set the tx reclaim threshold. 2899 * This helps cut down on the number of tx reclaim errors 2900 * that could happen on a busy network. The chip multiplies 2901 * the register value by 16 to obtain the actual threshold 2902 * in bytes, so we divide by 16 when setting the value here. 2903 * The existing threshold value can be examined by reading 2904 * the register at offset 9 in window 5. 2905 */ 2906 if (sc->xl_type == XL_TYPE_905B) { 2907 CSR_WRITE_2(sc, XL_COMMAND, 2908 XL_CMD_SET_TX_RECLAIM|(XL_PACKET_SIZE >> 4)); 2909 } 2910 2911 /* Set RX filter bits. */ 2912 XL_SEL_WIN(5); 2913 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER); 2914 2915 /* Set the individual bit to receive frames for this host only. */ 2916 rxfilt |= XL_RXFILTER_INDIVIDUAL; 2917 2918 /* If we want promiscuous mode, set the allframes bit. */ 2919 if (ifp->if_flags & IFF_PROMISC) { 2920 rxfilt |= XL_RXFILTER_ALLFRAMES; 2921 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 2922 } else { 2923 rxfilt &= ~XL_RXFILTER_ALLFRAMES; 2924 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 2925 } 2926 2927 /* 2928 * Set capture broadcast bit to capture broadcast frames. 2929 */ 2930 if (ifp->if_flags & IFF_BROADCAST) { 2931 rxfilt |= XL_RXFILTER_BROADCAST; 2932 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 2933 } else { 2934 rxfilt &= ~XL_RXFILTER_BROADCAST; 2935 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 2936 } 2937 2938 /* 2939 * Program the multicast filter, if necessary. 2940 */ 2941 if (sc->xl_type == XL_TYPE_905B) 2942 xl_setmulti_hash(sc); 2943 else 2944 xl_setmulti(sc); 2945 2946 if (sc->xl_type == XL_TYPE_905B) { 2947 /* Set UP polling interval */ 2948 CSR_WRITE_1(sc, XL_UP_POLL, 64); 2949 } 2950 2951 /* 2952 * Load the address of the RX list. We have to 2953 * stall the upload engine before we can manipulate 2954 * the uplist pointer register, then unstall it when 2955 * we're finished. We also have to wait for the 2956 * stall command to complete before proceeding. 2957 * Note that we have to do this after any RX resets 2958 * have completed since the uplist register is cleared 2959 * by a reset. 2960 */ 2961 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_STALL); 2962 xl_wait(sc); 2963 CSR_WRITE_4(sc, XL_UPLIST_PTR, sc->xl_ldata.xl_rx_dmaaddr); 2964 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_UNSTALL); 2965 xl_wait(sc); 2966 2967 if (sc->xl_type == XL_TYPE_905B) { 2968 /* Set DN polling interval */ 2969 CSR_WRITE_1(sc, XL_DOWN_POLL, 64); 2970 2971 /* Load the address of the TX list */ 2972 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_STALL); 2973 xl_wait(sc); 2974 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, 2975 sc->xl_cdata.xl_tx_chain[0].xl_phys); 2976 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); 2977 xl_wait(sc); 2978 } 2979 2980 /* 2981 * If the coax transceiver is on, make sure to enable 2982 * the DC-DC converter. 2983 */ 2984 XL_SEL_WIN(3); 2985 if (sc->xl_xcvr == XL_XCVR_COAX) 2986 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_START); 2987 else 2988 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP); 2989 2990 /* 2991 * increase packet size to allow reception of 802.1q or ISL packets. 2992 * For the 3c90x chip, set the 'allow large packets' bit in the MAC 2993 * control register. For 3c90xB/C chips, use the RX packet size 2994 * register. 2995 */ 2996 2997 if (sc->xl_type == XL_TYPE_905B) { 2998 CSR_WRITE_2(sc, XL_W3_MAXPKTSIZE, XL_PACKET_SIZE); 2999 } else { 3000 u_int8_t macctl; 3001 macctl = CSR_READ_1(sc, XL_W3_MAC_CTRL); 3002 macctl |= XL_MACCTRL_ALLOW_LARGE_PACK; 3003 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, macctl); 3004 } 3005 3006 /* Clear out the stats counters. */ 3007 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_DISABLE); 3008 sc->xl_stats_no_timeout = 1; 3009 xl_stats_update_serialized(sc); 3010 sc->xl_stats_no_timeout = 0; 3011 XL_SEL_WIN(4); 3012 CSR_WRITE_2(sc, XL_W4_NET_DIAG, XL_NETDIAG_UPPER_BYTES_ENABLE); 3013 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_ENABLE); 3014 3015 /* 3016 * Enable interrupts. 3017 */ 3018 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STAT_ENB | XL_INTRS); 3019 #ifdef DEVICE_POLLING 3020 /* Do not enable interrupt if polling(4) is enabled */ 3021 if ((ifp->if_flags & IFF_POLLING) != 0) 3022 xl_enable_intrs(sc, 0); 3023 else 3024 #endif 3025 xl_enable_intrs(sc, XL_INTRS); 3026 3027 /* Set the RX early threshold */ 3028 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_THRESH|(XL_PACKET_SIZE >>2)); 3029 CSR_WRITE_2(sc, XL_DMACTL, XL_DMACTL_UP_RX_EARLY); 3030 3031 /* Enable receiver and transmitter. */ 3032 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE); 3033 xl_wait(sc); 3034 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_ENABLE); 3035 xl_wait(sc); 3036 3037 if (mii != NULL) 3038 mii_mediachg(mii); 3039 3040 /* Select window 7 for normal operations. */ 3041 XL_SEL_WIN(7); 3042 3043 ifp->if_flags |= IFF_RUNNING; 3044 ifp->if_flags &= ~IFF_OACTIVE; 3045 3046 callout_reset(&sc->xl_stat_timer, hz, xl_stats_update, sc); 3047 } 3048 3049 /* 3050 * Set media options. 3051 */ 3052 static int 3053 xl_ifmedia_upd(struct ifnet *ifp) 3054 { 3055 struct xl_softc *sc; 3056 struct ifmedia *ifm = NULL; 3057 struct mii_data *mii = NULL; 3058 3059 ASSERT_SERIALIZED(ifp->if_serializer); 3060 3061 sc = ifp->if_softc; 3062 if (sc->xl_miibus != NULL) 3063 mii = device_get_softc(sc->xl_miibus); 3064 if (mii == NULL) 3065 ifm = &sc->ifmedia; 3066 else 3067 ifm = &mii->mii_media; 3068 3069 switch(IFM_SUBTYPE(ifm->ifm_media)) { 3070 case IFM_100_FX: 3071 case IFM_10_FL: 3072 case IFM_10_2: 3073 case IFM_10_5: 3074 xl_setmode(sc, ifm->ifm_media); 3075 return(0); 3076 break; 3077 default: 3078 break; 3079 } 3080 3081 if (sc->xl_media & XL_MEDIAOPT_MII || sc->xl_media & XL_MEDIAOPT_BTX 3082 || sc->xl_media & XL_MEDIAOPT_BT4) { 3083 xl_init(sc); 3084 } else { 3085 xl_setmode(sc, ifm->ifm_media); 3086 } 3087 3088 return(0); 3089 } 3090 3091 /* 3092 * Report current media status. 3093 */ 3094 static void 3095 xl_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 3096 { 3097 struct xl_softc *sc; 3098 u_int32_t icfg; 3099 struct mii_data *mii = NULL; 3100 3101 ASSERT_SERIALIZED(ifp->if_serializer); 3102 3103 sc = ifp->if_softc; 3104 if (sc->xl_miibus != NULL) 3105 mii = device_get_softc(sc->xl_miibus); 3106 3107 XL_SEL_WIN(3); 3108 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG) & XL_ICFG_CONNECTOR_MASK; 3109 icfg >>= XL_ICFG_CONNECTOR_BITS; 3110 3111 ifmr->ifm_active = IFM_ETHER; 3112 3113 switch(icfg) { 3114 case XL_XCVR_10BT: 3115 ifmr->ifm_active = IFM_ETHER|IFM_10_T; 3116 if (CSR_READ_1(sc, XL_W3_MAC_CTRL) & XL_MACCTRL_DUPLEX) 3117 ifmr->ifm_active |= IFM_FDX; 3118 else 3119 ifmr->ifm_active |= IFM_HDX; 3120 break; 3121 case XL_XCVR_AUI: 3122 if (sc->xl_type == XL_TYPE_905B && 3123 sc->xl_media == XL_MEDIAOPT_10FL) { 3124 ifmr->ifm_active = IFM_ETHER|IFM_10_FL; 3125 if (CSR_READ_1(sc, XL_W3_MAC_CTRL) & XL_MACCTRL_DUPLEX) 3126 ifmr->ifm_active |= IFM_FDX; 3127 else 3128 ifmr->ifm_active |= IFM_HDX; 3129 } else 3130 ifmr->ifm_active = IFM_ETHER|IFM_10_5; 3131 break; 3132 case XL_XCVR_COAX: 3133 ifmr->ifm_active = IFM_ETHER|IFM_10_2; 3134 break; 3135 /* 3136 * XXX MII and BTX/AUTO should be separate cases. 3137 */ 3138 3139 case XL_XCVR_100BTX: 3140 case XL_XCVR_AUTO: 3141 case XL_XCVR_MII: 3142 if (mii != NULL) { 3143 mii_pollstat(mii); 3144 ifmr->ifm_active = mii->mii_media_active; 3145 ifmr->ifm_status = mii->mii_media_status; 3146 } 3147 break; 3148 case XL_XCVR_100BFX: 3149 ifmr->ifm_active = IFM_ETHER|IFM_100_FX; 3150 break; 3151 default: 3152 if_printf(ifp, "unknown XCVR type: %d\n", icfg); 3153 break; 3154 } 3155 3156 return; 3157 } 3158 3159 static int 3160 xl_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr) 3161 { 3162 struct xl_softc *sc = ifp->if_softc; 3163 struct ifreq *ifr = (struct ifreq *) data; 3164 int error = 0; 3165 struct mii_data *mii = NULL; 3166 u_int8_t rxfilt; 3167 3168 ASSERT_SERIALIZED(ifp->if_serializer); 3169 3170 switch(command) { 3171 case SIOCSIFFLAGS: 3172 XL_SEL_WIN(5); 3173 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER); 3174 if (ifp->if_flags & IFF_UP) { 3175 if (ifp->if_flags & IFF_RUNNING && 3176 ifp->if_flags & IFF_PROMISC && 3177 !(sc->xl_if_flags & IFF_PROMISC)) { 3178 rxfilt |= XL_RXFILTER_ALLFRAMES; 3179 CSR_WRITE_2(sc, XL_COMMAND, 3180 XL_CMD_RX_SET_FILT|rxfilt); 3181 XL_SEL_WIN(7); 3182 } else if (ifp->if_flags & IFF_RUNNING && 3183 !(ifp->if_flags & IFF_PROMISC) && 3184 sc->xl_if_flags & IFF_PROMISC) { 3185 rxfilt &= ~XL_RXFILTER_ALLFRAMES; 3186 CSR_WRITE_2(sc, XL_COMMAND, 3187 XL_CMD_RX_SET_FILT|rxfilt); 3188 XL_SEL_WIN(7); 3189 } else 3190 xl_init(sc); 3191 } else { 3192 if (ifp->if_flags & IFF_RUNNING) 3193 xl_stop(sc); 3194 } 3195 sc->xl_if_flags = ifp->if_flags; 3196 error = 0; 3197 break; 3198 case SIOCADDMULTI: 3199 case SIOCDELMULTI: 3200 if (sc->xl_type == XL_TYPE_905B) 3201 xl_setmulti_hash(sc); 3202 else 3203 xl_setmulti(sc); 3204 error = 0; 3205 break; 3206 case SIOCGIFMEDIA: 3207 case SIOCSIFMEDIA: 3208 if (sc->xl_miibus != NULL) 3209 mii = device_get_softc(sc->xl_miibus); 3210 if (mii == NULL) 3211 error = ifmedia_ioctl(ifp, ifr, 3212 &sc->ifmedia, command); 3213 else 3214 error = ifmedia_ioctl(ifp, ifr, 3215 &mii->mii_media, command); 3216 break; 3217 case SIOCSIFCAP: 3218 ifp->if_capenable &= ~IFCAP_HWCSUM; 3219 ifp->if_capenable |= (ifr->ifr_reqcap & IFCAP_HWCSUM); 3220 if (ifp->if_capenable & IFCAP_HWCSUM) 3221 ifp->if_hwassist = XL905B_CSUM_FEATURES; 3222 else 3223 ifp->if_hwassist = 0; 3224 break; 3225 default: 3226 error = ether_ioctl(ifp, command, data); 3227 break; 3228 } 3229 return(error); 3230 } 3231 3232 static void 3233 xl_watchdog(struct ifnet *ifp) 3234 { 3235 struct xl_softc *sc; 3236 u_int16_t status = 0; 3237 3238 ASSERT_SERIALIZED(ifp->if_serializer); 3239 3240 sc = ifp->if_softc; 3241 3242 ifp->if_oerrors++; 3243 XL_SEL_WIN(4); 3244 status = CSR_READ_2(sc, XL_W4_MEDIA_STATUS); 3245 if_printf(ifp, "watchdog timeout\n"); 3246 3247 if (status & XL_MEDIASTAT_CARRIER) 3248 if_printf(ifp, "no carrier - transceiver cable problem?\n"); 3249 xl_txeoc(sc); 3250 xl_txeof(sc); 3251 xl_rxeof(sc, -1); 3252 xl_reset(sc); 3253 xl_init(sc); 3254 3255 if (!ifq_is_empty(&ifp->if_snd)) 3256 if_devstart(ifp); 3257 } 3258 3259 /* 3260 * Stop the adapter and free any mbufs allocated to the 3261 * RX and TX lists. 3262 */ 3263 static void 3264 xl_stop(struct xl_softc *sc) 3265 { 3266 int i; 3267 struct ifnet *ifp; 3268 3269 ifp = &sc->arpcom.ac_if; 3270 ASSERT_SERIALIZED(ifp->if_serializer); 3271 3272 ifp->if_timer = 0; 3273 3274 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_DISABLE); 3275 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_DISABLE); 3276 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB); 3277 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_DISCARD); 3278 xl_wait(sc); 3279 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_DISABLE); 3280 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP); 3281 DELAY(800); 3282 3283 #ifdef foo 3284 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET); 3285 xl_wait(sc); 3286 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); 3287 xl_wait(sc); 3288 #endif 3289 3290 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ACK|XL_STAT_INTLATCH); 3291 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STAT_ENB|0); 3292 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|0); 3293 if (sc->xl_flags & XL_FLAG_FUNCREG) 3294 bus_space_write_4(sc->xl_ftag, sc->xl_fhandle, 4, 0x8000); 3295 3296 /* Stop the stats updater. */ 3297 callout_stop(&sc->xl_stat_timer); 3298 3299 /* 3300 * Free data in the RX lists. 3301 */ 3302 for (i = 0; i < XL_RX_LIST_CNT; i++) { 3303 if (sc->xl_cdata.xl_rx_chain[i].xl_mbuf != NULL) { 3304 bus_dmamap_unload(sc->xl_mtag, 3305 sc->xl_cdata.xl_rx_chain[i].xl_map); 3306 m_freem(sc->xl_cdata.xl_rx_chain[i].xl_mbuf); 3307 sc->xl_cdata.xl_rx_chain[i].xl_mbuf = NULL; 3308 } 3309 } 3310 bzero(sc->xl_ldata.xl_rx_list, XL_RX_LIST_SZ); 3311 3312 /* 3313 * Free the TX list buffers. 3314 */ 3315 for (i = 0; i < XL_TX_LIST_CNT; i++) { 3316 if (sc->xl_cdata.xl_tx_chain[i].xl_mbuf != NULL) { 3317 bus_dmamap_unload(sc->xl_mtag, 3318 sc->xl_cdata.xl_tx_chain[i].xl_map); 3319 m_freem(sc->xl_cdata.xl_tx_chain[i].xl_mbuf); 3320 sc->xl_cdata.xl_tx_chain[i].xl_mbuf = NULL; 3321 } 3322 } 3323 bzero(sc->xl_ldata.xl_tx_list, XL_TX_LIST_SZ); 3324 3325 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 3326 } 3327 3328 /* 3329 * Stop all chip I/O so that the kernel's probe routines don't 3330 * get confused by errant DMAs when rebooting. 3331 */ 3332 static void 3333 xl_shutdown(device_t dev) 3334 { 3335 struct xl_softc *sc = device_get_softc(dev); 3336 3337 lwkt_serialize_enter(sc->arpcom.ac_if.if_serializer); 3338 xl_reset(sc); 3339 xl_stop(sc); 3340 lwkt_serialize_exit(sc->arpcom.ac_if.if_serializer); 3341 } 3342 3343 static int 3344 xl_suspend(device_t dev) 3345 { 3346 struct xl_softc *sc = device_get_softc(dev); 3347 3348 lwkt_serialize_enter(sc->arpcom.ac_if.if_serializer); 3349 xl_stop(sc); 3350 lwkt_serialize_exit(sc->arpcom.ac_if.if_serializer); 3351 3352 return(0); 3353 } 3354 3355 static int 3356 xl_resume(device_t dev) 3357 { 3358 struct xl_softc *sc; 3359 struct ifnet *ifp; 3360 3361 sc = device_get_softc(dev); 3362 ifp = &sc->arpcom.ac_if; 3363 3364 lwkt_serialize_enter(ifp->if_serializer); 3365 xl_reset(sc); 3366 if (ifp->if_flags & IFF_UP) 3367 xl_init(sc); 3368 lwkt_serialize_exit(ifp->if_serializer); 3369 3370 return(0); 3371 } 3372