1 /* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: src/sys/pci/if_xl.c,v 1.72.2.28 2003/10/08 06:01:57 murray Exp $ 33 * $DragonFly: src/sys/dev/netif/xl/if_xl.c,v 1.15 2004/09/15 01:24:48 joerg Exp $ 34 */ 35 36 /* 37 * 3Com 3c90x Etherlink XL PCI NIC driver 38 * 39 * Supports the 3Com "boomerang", "cyclone" and "hurricane" PCI 40 * bus-master chips (3c90x cards and embedded controllers) including 41 * the following: 42 * 43 * 3Com 3c900-TPO 10Mbps/RJ-45 44 * 3Com 3c900-COMBO 10Mbps/RJ-45,AUI,BNC 45 * 3Com 3c905-TX 10/100Mbps/RJ-45 46 * 3Com 3c905-T4 10/100Mbps/RJ-45 47 * 3Com 3c900B-TPO 10Mbps/RJ-45 48 * 3Com 3c900B-COMBO 10Mbps/RJ-45,AUI,BNC 49 * 3Com 3c900B-TPC 10Mbps/RJ-45,BNC 50 * 3Com 3c900B-FL 10Mbps/Fiber-optic 51 * 3Com 3c905B-COMBO 10/100Mbps/RJ-45,AUI,BNC 52 * 3Com 3c905B-TX 10/100Mbps/RJ-45 53 * 3Com 3c905B-FL/FX 10/100Mbps/Fiber-optic 54 * 3Com 3c905C-TX 10/100Mbps/RJ-45 (Tornado ASIC) 55 * 3Com 3c980-TX 10/100Mbps server adapter (Hurricane ASIC) 56 * 3Com 3c980C-TX 10/100Mbps server adapter (Tornado ASIC) 57 * 3Com 3cSOHO100-TX 10/100Mbps/RJ-45 (Hurricane ASIC) 58 * 3Com 3c450-TX 10/100Mbps/RJ-45 (Tornado ASIC) 59 * 3Com 3c555 10/100Mbps/RJ-45 (MiniPCI, Laptop Hurricane) 60 * 3Com 3c556 10/100Mbps/RJ-45 (MiniPCI, Hurricane ASIC) 61 * 3Com 3c556B 10/100Mbps/RJ-45 (MiniPCI, Hurricane ASIC) 62 * 3Com 3c575TX 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC) 63 * 3Com 3c575B 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC) 64 * 3Com 3c575C 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC) 65 * 3Com 3cxfem656 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC) 66 * 3Com 3cxfem656b 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC) 67 * 3Com 3cxfem656c 10/100Mbps/RJ-45 (Cardbus, Tornado ASIC) 68 * Dell Optiplex GX1 on-board 3c918 10/100Mbps/RJ-45 69 * Dell on-board 3c920 10/100Mbps/RJ-45 70 * Dell Precision on-board 3c905B 10/100Mbps/RJ-45 71 * Dell Latitude laptop docking station embedded 3c905-TX 72 * 73 * Written by Bill Paul <wpaul@ctr.columbia.edu> 74 * Electrical Engineering Department 75 * Columbia University, New York City 76 */ 77 78 /* 79 * The 3c90x series chips use a bus-master DMA interface for transfering 80 * packets to and from the controller chip. Some of the "vortex" cards 81 * (3c59x) also supported a bus master mode, however for those chips 82 * you could only DMA packets to/from a contiguous memory buffer. For 83 * transmission this would mean copying the contents of the queued mbuf 84 * chain into an mbuf cluster and then DMAing the cluster. This extra 85 * copy would sort of defeat the purpose of the bus master support for 86 * any packet that doesn't fit into a single mbuf. 87 * 88 * By contrast, the 3c90x cards support a fragment-based bus master 89 * mode where mbuf chains can be encapsulated using TX descriptors. 90 * This is similar to other PCI chips such as the Texas Instruments 91 * ThunderLAN and the Intel 82557/82558. 92 * 93 * The "vortex" driver (if_vx.c) happens to work for the "boomerang" 94 * bus master chips because they maintain the old PIO interface for 95 * backwards compatibility, but starting with the 3c905B and the 96 * "cyclone" chips, the compatibility interface has been dropped. 97 * Since using bus master DMA is a big win, we use this driver to 98 * support the PCI "boomerang" chips even though they work with the 99 * "vortex" driver in order to obtain better performance. 100 * 101 * This driver is in the /sys/pci directory because it only supports 102 * PCI-based NICs. 103 */ 104 105 #include <sys/param.h> 106 #include <sys/systm.h> 107 #include <sys/sockio.h> 108 #include <sys/endian.h> 109 #include <sys/mbuf.h> 110 #include <sys/kernel.h> 111 #include <sys/socket.h> 112 113 #include <net/if.h> 114 #include <net/if_arp.h> 115 #include <net/ethernet.h> 116 #include <net/if_dl.h> 117 #include <net/if_media.h> 118 #include <net/vlan/if_vlan_var.h> 119 120 #include <net/bpf.h> 121 122 #include <machine/bus_memio.h> 123 #include <machine/bus_pio.h> 124 #include <machine/bus.h> 125 #include <machine/clock.h> /* for DELAY */ 126 #include <machine/resource.h> 127 #include <sys/bus.h> 128 #include <sys/rman.h> 129 130 #include "../mii_layer/mii.h" 131 #include "../mii_layer/miivar.h" 132 133 #include <bus/pci/pcireg.h> 134 #include <bus/pci/pcivar.h> 135 136 /* "controller miibus0" required. See GENERIC if you get errors here. */ 137 #include "miibus_if.h" 138 139 #include "if_xlreg.h" 140 141 #define XL905B_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 142 143 /* 144 * Various supported device vendors/types and their names. 145 */ 146 static struct xl_type xl_devs[] = { 147 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10BT, 148 "3Com 3c900-TPO Etherlink XL" }, 149 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10BT_COMBO, 150 "3Com 3c900-COMBO Etherlink XL" }, 151 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10_100BT, 152 "3Com 3c905-TX Fast Etherlink XL" }, 153 { TC_VENDORID, TC_DEVICEID_BOOMERANG_100BT4, 154 "3Com 3c905-T4 Fast Etherlink XL" }, 155 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT, 156 "3Com 3c900B-TPO Etherlink XL" }, 157 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT_COMBO, 158 "3Com 3c900B-COMBO Etherlink XL" }, 159 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT_TPC, 160 "3Com 3c900B-TPC Etherlink XL" }, 161 { TC_VENDORID, TC_DEVICEID_CYCLONE_10FL, 162 "3Com 3c900B-FL Etherlink XL" }, 163 { TC_VENDORID, TC_DEVICEID_HURRICANE_10_100BT, 164 "3Com 3c905B-TX Fast Etherlink XL" }, 165 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100BT4, 166 "3Com 3c905B-T4 Fast Etherlink XL" }, 167 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100FX, 168 "3Com 3c905B-FX/SC Fast Etherlink XL" }, 169 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100_COMBO, 170 "3Com 3c905B-COMBO Fast Etherlink XL" }, 171 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT, 172 "3Com 3c905C-TX Fast Etherlink XL" }, 173 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT_920B, 174 "3Com 3c920B-EMB Integrated Fast Etherlink XL" }, 175 { TC_VENDORID, TC_DEVICEID_HURRICANE_10_100BT_SERV, 176 "3Com 3c980 Fast Etherlink XL" }, 177 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT_SERV, 178 "3Com 3c980C Fast Etherlink XL" }, 179 { TC_VENDORID, TC_DEVICEID_HURRICANE_SOHO100TX, 180 "3Com 3cSOHO100-TX OfficeConnect" }, 181 { TC_VENDORID, TC_DEVICEID_TORNADO_HOMECONNECT, 182 "3Com 3c450-TX HomeConnect" }, 183 { TC_VENDORID, TC_DEVICEID_HURRICANE_555, 184 "3Com 3c555 Fast Etherlink XL" }, 185 { TC_VENDORID, TC_DEVICEID_HURRICANE_556, 186 "3Com 3c556 Fast Etherlink XL" }, 187 { TC_VENDORID, TC_DEVICEID_HURRICANE_556B, 188 "3Com 3c556B Fast Etherlink XL" }, 189 { TC_VENDORID, TC_DEVICEID_HURRICANE_575A, 190 "3Com 3c575TX Fast Etherlink XL" }, 191 { TC_VENDORID, TC_DEVICEID_HURRICANE_575B, 192 "3Com 3c575B Fast Etherlink XL" }, 193 { TC_VENDORID, TC_DEVICEID_HURRICANE_575C, 194 "3Com 3c575C Fast Etherlink XL" }, 195 { TC_VENDORID, TC_DEVICEID_HURRICANE_656, 196 "3Com 3c656 Fast Etherlink XL" }, 197 { TC_VENDORID, TC_DEVICEID_HURRICANE_656B, 198 "3Com 3c656B Fast Etherlink XL" }, 199 { TC_VENDORID, TC_DEVICEID_TORNADO_656C, 200 "3Com 3c656C Fast Etherlink XL" }, 201 { 0, 0, NULL } 202 }; 203 204 static int xl_probe (device_t); 205 static int xl_attach (device_t); 206 static int xl_detach (device_t); 207 208 static int xl_newbuf (struct xl_softc *, struct xl_chain_onefrag *); 209 static void xl_stats_update (void *); 210 static int xl_encap (struct xl_softc *, struct xl_chain *, 211 struct mbuf *); 212 static void xl_rxeof (struct xl_softc *); 213 static int xl_rx_resync (struct xl_softc *); 214 static void xl_txeof (struct xl_softc *); 215 static void xl_txeof_90xB (struct xl_softc *); 216 static void xl_txeoc (struct xl_softc *); 217 static void xl_intr (void *); 218 static void xl_start (struct ifnet *); 219 static void xl_start_90xB (struct ifnet *); 220 static int xl_ioctl (struct ifnet *, u_long, caddr_t, 221 struct ucred *); 222 static void xl_init (void *); 223 static void xl_stop (struct xl_softc *); 224 static void xl_watchdog (struct ifnet *); 225 static void xl_shutdown (device_t); 226 static int xl_suspend (device_t); 227 static int xl_resume (device_t); 228 229 static int xl_ifmedia_upd (struct ifnet *); 230 static void xl_ifmedia_sts (struct ifnet *, struct ifmediareq *); 231 232 static int xl_eeprom_wait (struct xl_softc *); 233 static int xl_read_eeprom (struct xl_softc *, caddr_t, int, int, int); 234 static void xl_mii_sync (struct xl_softc *); 235 static void xl_mii_send (struct xl_softc *, u_int32_t, int); 236 static int xl_mii_readreg (struct xl_softc *, struct xl_mii_frame *); 237 static int xl_mii_writereg (struct xl_softc *, struct xl_mii_frame *); 238 239 static void xl_setcfg (struct xl_softc *); 240 static void xl_setmode (struct xl_softc *, int); 241 static u_int8_t xl_calchash (caddr_t); 242 static void xl_setmulti (struct xl_softc *); 243 static void xl_setmulti_hash (struct xl_softc *); 244 static void xl_reset (struct xl_softc *); 245 static int xl_list_rx_init (struct xl_softc *); 246 static int xl_list_tx_init (struct xl_softc *); 247 static int xl_list_tx_init_90xB (struct xl_softc *); 248 static void xl_wait (struct xl_softc *); 249 static void xl_mediacheck (struct xl_softc *); 250 static void xl_choose_xcvr (struct xl_softc *, int); 251 static void xl_dma_map_addr (void *, bus_dma_segment_t *, int, int); 252 static void xl_dma_map_rxbuf (void *, bus_dma_segment_t *, int, bus_size_t, 253 int); 254 static void xl_dma_map_txbuf (void *, bus_dma_segment_t *, int, bus_size_t, 255 int); 256 #ifdef notdef 257 static void xl_testpacket (struct xl_softc *); 258 #endif 259 260 static int xl_miibus_readreg (device_t, int, int); 261 static int xl_miibus_writereg (device_t, int, int, int); 262 static void xl_miibus_statchg (device_t); 263 static void xl_miibus_mediainit (device_t); 264 265 static device_method_t xl_methods[] = { 266 /* Device interface */ 267 DEVMETHOD(device_probe, xl_probe), 268 DEVMETHOD(device_attach, xl_attach), 269 DEVMETHOD(device_detach, xl_detach), 270 DEVMETHOD(device_shutdown, xl_shutdown), 271 DEVMETHOD(device_suspend, xl_suspend), 272 DEVMETHOD(device_resume, xl_resume), 273 274 /* bus interface */ 275 DEVMETHOD(bus_print_child, bus_generic_print_child), 276 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 277 278 /* MII interface */ 279 DEVMETHOD(miibus_readreg, xl_miibus_readreg), 280 DEVMETHOD(miibus_writereg, xl_miibus_writereg), 281 DEVMETHOD(miibus_statchg, xl_miibus_statchg), 282 DEVMETHOD(miibus_mediainit, xl_miibus_mediainit), 283 284 { 0, 0 } 285 }; 286 287 static driver_t xl_driver = { 288 "xl", 289 xl_methods, 290 sizeof(struct xl_softc) 291 }; 292 293 static devclass_t xl_devclass; 294 295 DECLARE_DUMMY_MODULE(if_xl); 296 MODULE_DEPEND(if_xl, miibus, 1, 1, 1); 297 DRIVER_MODULE(if_xl, pci, xl_driver, xl_devclass, 0, 0); 298 DRIVER_MODULE(miibus, xl, miibus_driver, miibus_devclass, 0, 0); 299 300 static void 301 xl_dma_map_addr(arg, segs, nseg, error) 302 void *arg; 303 bus_dma_segment_t *segs; 304 int nseg, error; 305 { 306 u_int32_t *paddr; 307 308 paddr = arg; 309 *paddr = segs->ds_addr; 310 } 311 312 static void 313 xl_dma_map_rxbuf(arg, segs, nseg, mapsize, error) 314 void *arg; 315 bus_dma_segment_t *segs; 316 int nseg; 317 bus_size_t mapsize; 318 int error; 319 { 320 u_int32_t *paddr; 321 322 if (error) 323 return; 324 KASSERT(nseg == 1, ("xl_dma_map_rxbuf: too many DMA segments")); 325 paddr = arg; 326 *paddr = segs->ds_addr; 327 } 328 329 static void 330 xl_dma_map_txbuf(arg, segs, nseg, mapsize, error) 331 void *arg; 332 bus_dma_segment_t *segs; 333 int nseg; 334 bus_size_t mapsize; 335 int error; 336 { 337 struct xl_list *l; 338 int i, total_len; 339 340 if (error) 341 return; 342 343 KASSERT(nseg <= XL_MAXFRAGS, ("too many DMA segments")); 344 345 total_len = 0; 346 l = arg; 347 for (i = 0; i < nseg; i++) { 348 KASSERT(segs[i].ds_len <= MCLBYTES, ("segment size too large")); 349 l->xl_frag[i].xl_addr = htole32(segs[i].ds_addr); 350 l->xl_frag[i].xl_len = htole32(segs[i].ds_len); 351 total_len += segs[i].ds_len; 352 } 353 l->xl_frag[nseg - 1].xl_len = htole32(segs[nseg - 1].ds_len | 354 XL_LAST_FRAG); 355 l->xl_status = htole32(total_len); 356 l->xl_next = 0; 357 } 358 359 /* 360 * Murphy's law says that it's possible the chip can wedge and 361 * the 'command in progress' bit may never clear. Hence, we wait 362 * only a finite amount of time to avoid getting caught in an 363 * infinite loop. Normally this delay routine would be a macro, 364 * but it isn't called during normal operation so we can afford 365 * to make it a function. 366 */ 367 static void 368 xl_wait(sc) 369 struct xl_softc *sc; 370 { 371 int i; 372 373 for (i = 0; i < XL_TIMEOUT; i++) { 374 if (!(CSR_READ_2(sc, XL_STATUS) & XL_STAT_CMDBUSY)) 375 break; 376 } 377 378 if (i == XL_TIMEOUT) 379 printf("xl%d: command never completed!\n", sc->xl_unit); 380 381 return; 382 } 383 384 /* 385 * MII access routines are provided for adapters with external 386 * PHYs (3c905-TX, 3c905-T4, 3c905B-T4) and those with built-in 387 * autoneg logic that's faked up to look like a PHY (3c905B-TX). 388 * Note: if you don't perform the MDIO operations just right, 389 * it's possible to end up with code that works correctly with 390 * some chips/CPUs/processor speeds/bus speeds/etc but not 391 * with others. 392 */ 393 #define MII_SET(x) \ 394 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, \ 395 CSR_READ_2(sc, XL_W4_PHY_MGMT) | (x)) 396 397 #define MII_CLR(x) \ 398 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, \ 399 CSR_READ_2(sc, XL_W4_PHY_MGMT) & ~(x)) 400 401 /* 402 * Sync the PHYs by setting data bit and strobing the clock 32 times. 403 */ 404 static void 405 xl_mii_sync(sc) 406 struct xl_softc *sc; 407 { 408 int i; 409 410 XL_SEL_WIN(4); 411 MII_SET(XL_MII_DIR|XL_MII_DATA); 412 413 for (i = 0; i < 32; i++) { 414 MII_SET(XL_MII_CLK); 415 MII_SET(XL_MII_DATA); 416 MII_SET(XL_MII_DATA); 417 MII_CLR(XL_MII_CLK); 418 MII_SET(XL_MII_DATA); 419 MII_SET(XL_MII_DATA); 420 } 421 422 return; 423 } 424 425 /* 426 * Clock a series of bits through the MII. 427 */ 428 static void 429 xl_mii_send(sc, bits, cnt) 430 struct xl_softc *sc; 431 u_int32_t bits; 432 int cnt; 433 { 434 int i; 435 436 XL_SEL_WIN(4); 437 MII_CLR(XL_MII_CLK); 438 439 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 440 if (bits & i) { 441 MII_SET(XL_MII_DATA); 442 } else { 443 MII_CLR(XL_MII_DATA); 444 } 445 MII_CLR(XL_MII_CLK); 446 MII_SET(XL_MII_CLK); 447 } 448 } 449 450 /* 451 * Read an PHY register through the MII. 452 */ 453 static int 454 xl_mii_readreg(sc, frame) 455 struct xl_softc *sc; 456 struct xl_mii_frame *frame; 457 458 { 459 int i, ack, s; 460 461 s = splimp(); 462 463 /* 464 * Set up frame for RX. 465 */ 466 frame->mii_stdelim = XL_MII_STARTDELIM; 467 frame->mii_opcode = XL_MII_READOP; 468 frame->mii_turnaround = 0; 469 frame->mii_data = 0; 470 471 /* 472 * Select register window 4. 473 */ 474 475 XL_SEL_WIN(4); 476 477 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, 0); 478 /* 479 * Turn on data xmit. 480 */ 481 MII_SET(XL_MII_DIR); 482 483 xl_mii_sync(sc); 484 485 /* 486 * Send command/address info. 487 */ 488 xl_mii_send(sc, frame->mii_stdelim, 2); 489 xl_mii_send(sc, frame->mii_opcode, 2); 490 xl_mii_send(sc, frame->mii_phyaddr, 5); 491 xl_mii_send(sc, frame->mii_regaddr, 5); 492 493 /* Idle bit */ 494 MII_CLR((XL_MII_CLK|XL_MII_DATA)); 495 MII_SET(XL_MII_CLK); 496 497 /* Turn off xmit. */ 498 MII_CLR(XL_MII_DIR); 499 500 /* Check for ack */ 501 MII_CLR(XL_MII_CLK); 502 ack = CSR_READ_2(sc, XL_W4_PHY_MGMT) & XL_MII_DATA; 503 MII_SET(XL_MII_CLK); 504 505 /* 506 * Now try reading data bits. If the ack failed, we still 507 * need to clock through 16 cycles to keep the PHY(s) in sync. 508 */ 509 if (ack) { 510 for(i = 0; i < 16; i++) { 511 MII_CLR(XL_MII_CLK); 512 MII_SET(XL_MII_CLK); 513 } 514 goto fail; 515 } 516 517 for (i = 0x8000; i; i >>= 1) { 518 MII_CLR(XL_MII_CLK); 519 if (!ack) { 520 if (CSR_READ_2(sc, XL_W4_PHY_MGMT) & XL_MII_DATA) 521 frame->mii_data |= i; 522 } 523 MII_SET(XL_MII_CLK); 524 } 525 526 fail: 527 528 MII_CLR(XL_MII_CLK); 529 MII_SET(XL_MII_CLK); 530 531 splx(s); 532 533 if (ack) 534 return(1); 535 return(0); 536 } 537 538 /* 539 * Write to a PHY register through the MII. 540 */ 541 static int 542 xl_mii_writereg(sc, frame) 543 struct xl_softc *sc; 544 struct xl_mii_frame *frame; 545 546 { 547 int s; 548 549 s = splimp(); 550 551 /* 552 * Set up frame for TX. 553 */ 554 555 frame->mii_stdelim = XL_MII_STARTDELIM; 556 frame->mii_opcode = XL_MII_WRITEOP; 557 frame->mii_turnaround = XL_MII_TURNAROUND; 558 559 /* 560 * Select the window 4. 561 */ 562 XL_SEL_WIN(4); 563 564 /* 565 * Turn on data output. 566 */ 567 MII_SET(XL_MII_DIR); 568 569 xl_mii_sync(sc); 570 571 xl_mii_send(sc, frame->mii_stdelim, 2); 572 xl_mii_send(sc, frame->mii_opcode, 2); 573 xl_mii_send(sc, frame->mii_phyaddr, 5); 574 xl_mii_send(sc, frame->mii_regaddr, 5); 575 xl_mii_send(sc, frame->mii_turnaround, 2); 576 xl_mii_send(sc, frame->mii_data, 16); 577 578 /* Idle bit. */ 579 MII_SET(XL_MII_CLK); 580 MII_CLR(XL_MII_CLK); 581 582 /* 583 * Turn off xmit. 584 */ 585 MII_CLR(XL_MII_DIR); 586 587 splx(s); 588 589 return(0); 590 } 591 592 static int 593 xl_miibus_readreg(dev, phy, reg) 594 device_t dev; 595 int phy, reg; 596 { 597 struct xl_softc *sc; 598 struct xl_mii_frame frame; 599 600 sc = device_get_softc(dev); 601 602 /* 603 * Pretend that PHYs are only available at MII address 24. 604 * This is to guard against problems with certain 3Com ASIC 605 * revisions that incorrectly map the internal transceiver 606 * control registers at all MII addresses. This can cause 607 * the miibus code to attach the same PHY several times over. 608 */ 609 if ((!(sc->xl_flags & XL_FLAG_PHYOK)) && phy != 24) 610 return(0); 611 612 bzero((char *)&frame, sizeof(frame)); 613 614 frame.mii_phyaddr = phy; 615 frame.mii_regaddr = reg; 616 xl_mii_readreg(sc, &frame); 617 618 return(frame.mii_data); 619 } 620 621 static int 622 xl_miibus_writereg(dev, phy, reg, data) 623 device_t dev; 624 int phy, reg, data; 625 { 626 struct xl_softc *sc; 627 struct xl_mii_frame frame; 628 629 sc = device_get_softc(dev); 630 631 if ((!(sc->xl_flags & XL_FLAG_PHYOK)) && phy != 24) 632 return(0); 633 634 bzero((char *)&frame, sizeof(frame)); 635 636 frame.mii_phyaddr = phy; 637 frame.mii_regaddr = reg; 638 frame.mii_data = data; 639 640 xl_mii_writereg(sc, &frame); 641 642 return(0); 643 } 644 645 static void 646 xl_miibus_statchg(dev) 647 device_t dev; 648 { 649 struct xl_softc *sc; 650 struct mii_data *mii; 651 652 653 sc = device_get_softc(dev); 654 mii = device_get_softc(sc->xl_miibus); 655 656 xl_setcfg(sc); 657 658 /* Set ASIC's duplex mode to match the PHY. */ 659 XL_SEL_WIN(3); 660 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) 661 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, XL_MACCTRL_DUPLEX); 662 else 663 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, 664 (CSR_READ_1(sc, XL_W3_MAC_CTRL) & ~XL_MACCTRL_DUPLEX)); 665 666 return; 667 } 668 669 /* 670 * Special support for the 3c905B-COMBO. This card has 10/100 support 671 * plus BNC and AUI ports. This means we will have both an miibus attached 672 * plus some non-MII media settings. In order to allow this, we have to 673 * add the extra media to the miibus's ifmedia struct, but we can't do 674 * that during xl_attach() because the miibus hasn't been attached yet. 675 * So instead, we wait until the miibus probe/attach is done, at which 676 * point we will get a callback telling is that it's safe to add our 677 * extra media. 678 */ 679 static void 680 xl_miibus_mediainit(dev) 681 device_t dev; 682 { 683 struct xl_softc *sc; 684 struct mii_data *mii; 685 struct ifmedia *ifm; 686 687 sc = device_get_softc(dev); 688 mii = device_get_softc(sc->xl_miibus); 689 ifm = &mii->mii_media; 690 691 if (sc->xl_media & (XL_MEDIAOPT_AUI|XL_MEDIAOPT_10FL)) { 692 /* 693 * Check for a 10baseFL board in disguise. 694 */ 695 if (sc->xl_type == XL_TYPE_905B && 696 sc->xl_media == XL_MEDIAOPT_10FL) { 697 if (bootverbose) 698 printf("xl%d: found 10baseFL\n", sc->xl_unit); 699 ifmedia_add(ifm, IFM_ETHER|IFM_10_FL, 0, NULL); 700 ifmedia_add(ifm, IFM_ETHER|IFM_10_FL|IFM_HDX, 0, NULL); 701 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX) 702 ifmedia_add(ifm, 703 IFM_ETHER|IFM_10_FL|IFM_FDX, 0, NULL); 704 } else { 705 if (bootverbose) 706 printf("xl%d: found AUI\n", sc->xl_unit); 707 ifmedia_add(ifm, IFM_ETHER|IFM_10_5, 0, NULL); 708 } 709 } 710 711 if (sc->xl_media & XL_MEDIAOPT_BNC) { 712 if (bootverbose) 713 printf("xl%d: found BNC\n", sc->xl_unit); 714 ifmedia_add(ifm, IFM_ETHER|IFM_10_2, 0, NULL); 715 } 716 717 return; 718 } 719 720 /* 721 * The EEPROM is slow: give it time to come ready after issuing 722 * it a command. 723 */ 724 static int 725 xl_eeprom_wait(sc) 726 struct xl_softc *sc; 727 { 728 int i; 729 730 for (i = 0; i < 100; i++) { 731 if (CSR_READ_2(sc, XL_W0_EE_CMD) & XL_EE_BUSY) 732 DELAY(162); 733 else 734 break; 735 } 736 737 if (i == 100) { 738 printf("xl%d: eeprom failed to come ready\n", sc->xl_unit); 739 return(1); 740 } 741 742 return(0); 743 } 744 745 /* 746 * Read a sequence of words from the EEPROM. Note that ethernet address 747 * data is stored in the EEPROM in network byte order. 748 */ 749 static int 750 xl_read_eeprom(sc, dest, off, cnt, swap) 751 struct xl_softc *sc; 752 caddr_t dest; 753 int off; 754 int cnt; 755 int swap; 756 { 757 int err = 0, i; 758 u_int16_t word = 0, *ptr; 759 #define EEPROM_5BIT_OFFSET(A) ((((A) << 2) & 0x7F00) | ((A) & 0x003F)) 760 #define EEPROM_8BIT_OFFSET(A) ((A) & 0x003F) 761 /* WARNING! DANGER! 762 * It's easy to accidentally overwrite the rom content! 763 * Note: the 3c575 uses 8bit EEPROM offsets. 764 */ 765 XL_SEL_WIN(0); 766 767 if (xl_eeprom_wait(sc)) 768 return(1); 769 770 if (sc->xl_flags & XL_FLAG_EEPROM_OFFSET_30) 771 off += 0x30; 772 773 for (i = 0; i < cnt; i++) { 774 if (sc->xl_flags & XL_FLAG_8BITROM) 775 CSR_WRITE_2(sc, XL_W0_EE_CMD, 776 XL_EE_8BIT_READ | EEPROM_8BIT_OFFSET(off + i)); 777 else 778 CSR_WRITE_2(sc, XL_W0_EE_CMD, 779 XL_EE_READ | EEPROM_5BIT_OFFSET(off + i)); 780 err = xl_eeprom_wait(sc); 781 if (err) 782 break; 783 word = CSR_READ_2(sc, XL_W0_EE_DATA); 784 ptr = (u_int16_t *)(dest + (i * 2)); 785 if (swap) 786 *ptr = ntohs(word); 787 else 788 *ptr = word; 789 } 790 791 return(err ? 1 : 0); 792 } 793 794 /* 795 * This routine is taken from the 3Com Etherlink XL manual, 796 * page 10-7. It calculates a CRC of the supplied multicast 797 * group address and returns the lower 8 bits, which are used 798 * as the multicast filter position. 799 * Note: the 3c905B currently only supports a 64-bit hash table, 800 * which means we really only need 6 bits, but the manual indicates 801 * that future chip revisions will have a 256-bit hash table, 802 * hence the routine is set up to calculate 8 bits of position 803 * info in case we need it some day. 804 * Note II, The Sequel: _CURRENT_ versions of the 3c905B have a 805 * 256 bit hash table. This means we have to use all 8 bits regardless. 806 * On older cards, the upper 2 bits will be ignored. Grrrr.... 807 */ 808 static u_int8_t xl_calchash(addr) 809 caddr_t addr; 810 { 811 u_int32_t crc, carry; 812 int i, j; 813 u_int8_t c; 814 815 /* Compute CRC for the address value. */ 816 crc = 0xFFFFFFFF; /* initial value */ 817 818 for (i = 0; i < 6; i++) { 819 c = *(addr + i); 820 for (j = 0; j < 8; j++) { 821 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 822 crc <<= 1; 823 c >>= 1; 824 if (carry) 825 crc = (crc ^ 0x04c11db6) | carry; 826 } 827 } 828 829 /* return the filter bit position */ 830 return(crc & 0x000000FF); 831 } 832 833 /* 834 * NICs older than the 3c905B have only one multicast option, which 835 * is to enable reception of all multicast frames. 836 */ 837 static void 838 xl_setmulti(sc) 839 struct xl_softc *sc; 840 { 841 struct ifnet *ifp; 842 struct ifmultiaddr *ifma; 843 u_int8_t rxfilt; 844 int mcnt = 0; 845 846 ifp = &sc->arpcom.ac_if; 847 848 XL_SEL_WIN(5); 849 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER); 850 851 if (ifp->if_flags & IFF_ALLMULTI) { 852 rxfilt |= XL_RXFILTER_ALLMULTI; 853 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 854 return; 855 } 856 857 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 858 ifma = ifma->ifma_link.le_next) 859 mcnt++; 860 861 if (mcnt) 862 rxfilt |= XL_RXFILTER_ALLMULTI; 863 else 864 rxfilt &= ~XL_RXFILTER_ALLMULTI; 865 866 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 867 868 return; 869 } 870 871 /* 872 * 3c905B adapters have a hash filter that we can program. 873 */ 874 static void 875 xl_setmulti_hash(sc) 876 struct xl_softc *sc; 877 { 878 struct ifnet *ifp; 879 int h = 0, i; 880 struct ifmultiaddr *ifma; 881 u_int8_t rxfilt; 882 int mcnt = 0; 883 884 ifp = &sc->arpcom.ac_if; 885 886 XL_SEL_WIN(5); 887 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER); 888 889 if (ifp->if_flags & IFF_ALLMULTI) { 890 rxfilt |= XL_RXFILTER_ALLMULTI; 891 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 892 return; 893 } else 894 rxfilt &= ~XL_RXFILTER_ALLMULTI; 895 896 897 /* first, zot all the existing hash bits */ 898 for (i = 0; i < XL_HASHFILT_SIZE; i++) 899 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_HASH|i); 900 901 /* now program new ones */ 902 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 903 ifma = ifma->ifma_link.le_next) { 904 if (ifma->ifma_addr->sa_family != AF_LINK) 905 continue; 906 h = xl_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 907 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_HASH|XL_HASH_SET|h); 908 mcnt++; 909 } 910 911 if (mcnt) 912 rxfilt |= XL_RXFILTER_MULTIHASH; 913 else 914 rxfilt &= ~XL_RXFILTER_MULTIHASH; 915 916 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 917 918 return; 919 } 920 921 #ifdef notdef 922 static void 923 xl_testpacket(sc) 924 struct xl_softc *sc; 925 { 926 struct mbuf *m; 927 struct ifnet *ifp; 928 929 ifp = &sc->arpcom.ac_if; 930 931 MGETHDR(m, MB_DONTWAIT, MT_DATA); 932 933 if (m == NULL) 934 return; 935 936 bcopy(&sc->arpcom.ac_enaddr, 937 mtod(m, struct ether_header *)->ether_dhost, ETHER_ADDR_LEN); 938 bcopy(&sc->arpcom.ac_enaddr, 939 mtod(m, struct ether_header *)->ether_shost, ETHER_ADDR_LEN); 940 mtod(m, struct ether_header *)->ether_type = htons(3); 941 mtod(m, unsigned char *)[14] = 0; 942 mtod(m, unsigned char *)[15] = 0; 943 mtod(m, unsigned char *)[16] = 0xE3; 944 m->m_len = m->m_pkthdr.len = sizeof(struct ether_header) + 3; 945 IF_ENQUEUE(&ifp->if_snd, m); 946 xl_start(ifp); 947 948 return; 949 } 950 #endif 951 952 static void 953 xl_setcfg(sc) 954 struct xl_softc *sc; 955 { 956 u_int32_t icfg; 957 958 XL_SEL_WIN(3); 959 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG); 960 icfg &= ~XL_ICFG_CONNECTOR_MASK; 961 if (sc->xl_media & XL_MEDIAOPT_MII || 962 sc->xl_media & XL_MEDIAOPT_BT4) 963 icfg |= (XL_XCVR_MII << XL_ICFG_CONNECTOR_BITS); 964 if (sc->xl_media & XL_MEDIAOPT_BTX) 965 icfg |= (XL_XCVR_AUTO << XL_ICFG_CONNECTOR_BITS); 966 967 CSR_WRITE_4(sc, XL_W3_INTERNAL_CFG, icfg); 968 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP); 969 970 return; 971 } 972 973 static void 974 xl_setmode(sc, media) 975 struct xl_softc *sc; 976 int media; 977 { 978 u_int32_t icfg; 979 u_int16_t mediastat; 980 981 printf("xl%d: selecting ", sc->xl_unit); 982 983 XL_SEL_WIN(4); 984 mediastat = CSR_READ_2(sc, XL_W4_MEDIA_STATUS); 985 XL_SEL_WIN(3); 986 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG); 987 988 if (sc->xl_media & XL_MEDIAOPT_BT) { 989 if (IFM_SUBTYPE(media) == IFM_10_T) { 990 printf("10baseT transceiver, "); 991 sc->xl_xcvr = XL_XCVR_10BT; 992 icfg &= ~XL_ICFG_CONNECTOR_MASK; 993 icfg |= (XL_XCVR_10BT << XL_ICFG_CONNECTOR_BITS); 994 mediastat |= XL_MEDIASTAT_LINKBEAT| 995 XL_MEDIASTAT_JABGUARD; 996 mediastat &= ~XL_MEDIASTAT_SQEENB; 997 } 998 } 999 1000 if (sc->xl_media & XL_MEDIAOPT_BFX) { 1001 if (IFM_SUBTYPE(media) == IFM_100_FX) { 1002 printf("100baseFX port, "); 1003 sc->xl_xcvr = XL_XCVR_100BFX; 1004 icfg &= ~XL_ICFG_CONNECTOR_MASK; 1005 icfg |= (XL_XCVR_100BFX << XL_ICFG_CONNECTOR_BITS); 1006 mediastat |= XL_MEDIASTAT_LINKBEAT; 1007 mediastat &= ~XL_MEDIASTAT_SQEENB; 1008 } 1009 } 1010 1011 if (sc->xl_media & (XL_MEDIAOPT_AUI|XL_MEDIAOPT_10FL)) { 1012 if (IFM_SUBTYPE(media) == IFM_10_5) { 1013 printf("AUI port, "); 1014 sc->xl_xcvr = XL_XCVR_AUI; 1015 icfg &= ~XL_ICFG_CONNECTOR_MASK; 1016 icfg |= (XL_XCVR_AUI << XL_ICFG_CONNECTOR_BITS); 1017 mediastat &= ~(XL_MEDIASTAT_LINKBEAT| 1018 XL_MEDIASTAT_JABGUARD); 1019 mediastat |= ~XL_MEDIASTAT_SQEENB; 1020 } 1021 if (IFM_SUBTYPE(media) == IFM_10_FL) { 1022 printf("10baseFL transceiver, "); 1023 sc->xl_xcvr = XL_XCVR_AUI; 1024 icfg &= ~XL_ICFG_CONNECTOR_MASK; 1025 icfg |= (XL_XCVR_AUI << XL_ICFG_CONNECTOR_BITS); 1026 mediastat &= ~(XL_MEDIASTAT_LINKBEAT| 1027 XL_MEDIASTAT_JABGUARD); 1028 mediastat |= ~XL_MEDIASTAT_SQEENB; 1029 } 1030 } 1031 1032 if (sc->xl_media & XL_MEDIAOPT_BNC) { 1033 if (IFM_SUBTYPE(media) == IFM_10_2) { 1034 printf("BNC port, "); 1035 sc->xl_xcvr = XL_XCVR_COAX; 1036 icfg &= ~XL_ICFG_CONNECTOR_MASK; 1037 icfg |= (XL_XCVR_COAX << XL_ICFG_CONNECTOR_BITS); 1038 mediastat &= ~(XL_MEDIASTAT_LINKBEAT| 1039 XL_MEDIASTAT_JABGUARD| 1040 XL_MEDIASTAT_SQEENB); 1041 } 1042 } 1043 1044 if ((media & IFM_GMASK) == IFM_FDX || 1045 IFM_SUBTYPE(media) == IFM_100_FX) { 1046 printf("full duplex\n"); 1047 XL_SEL_WIN(3); 1048 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, XL_MACCTRL_DUPLEX); 1049 } else { 1050 printf("half duplex\n"); 1051 XL_SEL_WIN(3); 1052 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, 1053 (CSR_READ_1(sc, XL_W3_MAC_CTRL) & ~XL_MACCTRL_DUPLEX)); 1054 } 1055 1056 if (IFM_SUBTYPE(media) == IFM_10_2) 1057 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_START); 1058 else 1059 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP); 1060 CSR_WRITE_4(sc, XL_W3_INTERNAL_CFG, icfg); 1061 XL_SEL_WIN(4); 1062 CSR_WRITE_2(sc, XL_W4_MEDIA_STATUS, mediastat); 1063 DELAY(800); 1064 XL_SEL_WIN(7); 1065 1066 return; 1067 } 1068 1069 static void 1070 xl_reset(sc) 1071 struct xl_softc *sc; 1072 { 1073 int i; 1074 1075 XL_SEL_WIN(0); 1076 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RESET | 1077 ((sc->xl_flags & XL_FLAG_WEIRDRESET) ? 1078 XL_RESETOPT_DISADVFD:0)); 1079 1080 /* 1081 * If we're using memory mapped register mode, pause briefly 1082 * after issuing the reset command before trying to access any 1083 * other registers. With my 3c575C cardbus card, failing to do 1084 * this results in the system locking up while trying to poll 1085 * the command busy bit in the status register. 1086 */ 1087 if (sc->xl_flags & XL_FLAG_USE_MMIO) 1088 DELAY(100000); 1089 1090 for (i = 0; i < XL_TIMEOUT; i++) { 1091 DELAY(10); 1092 if (!(CSR_READ_2(sc, XL_STATUS) & XL_STAT_CMDBUSY)) 1093 break; 1094 } 1095 1096 if (i == XL_TIMEOUT) 1097 printf("xl%d: reset didn't complete\n", sc->xl_unit); 1098 1099 /* Reset TX and RX. */ 1100 /* Note: the RX reset takes an absurd amount of time 1101 * on newer versions of the Tornado chips such as those 1102 * on the 3c905CX and newer 3c908C cards. We wait an 1103 * extra amount of time so that xl_wait() doesn't complain 1104 * and annoy the users. 1105 */ 1106 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET); 1107 DELAY(100000); 1108 xl_wait(sc); 1109 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); 1110 xl_wait(sc); 1111 1112 if (sc->xl_flags & XL_FLAG_INVERT_LED_PWR || 1113 sc->xl_flags & XL_FLAG_INVERT_MII_PWR) { 1114 XL_SEL_WIN(2); 1115 CSR_WRITE_2(sc, XL_W2_RESET_OPTIONS, CSR_READ_2(sc, 1116 XL_W2_RESET_OPTIONS) 1117 | ((sc->xl_flags & XL_FLAG_INVERT_LED_PWR)?XL_RESETOPT_INVERT_LED:0) 1118 | ((sc->xl_flags & XL_FLAG_INVERT_MII_PWR)?XL_RESETOPT_INVERT_MII:0) 1119 ); 1120 } 1121 1122 /* Wait a little while for the chip to get its brains in order. */ 1123 DELAY(100000); 1124 return; 1125 } 1126 1127 /* 1128 * Probe for a 3Com Etherlink XL chip. Check the PCI vendor and device 1129 * IDs against our list and return a device name if we find a match. 1130 */ 1131 static int 1132 xl_probe(dev) 1133 device_t dev; 1134 { 1135 struct xl_type *t; 1136 1137 t = xl_devs; 1138 1139 while(t->xl_name != NULL) { 1140 if ((pci_get_vendor(dev) == t->xl_vid) && 1141 (pci_get_device(dev) == t->xl_did)) { 1142 device_set_desc(dev, t->xl_name); 1143 return(0); 1144 } 1145 t++; 1146 } 1147 1148 return(ENXIO); 1149 } 1150 1151 /* 1152 * This routine is a kludge to work around possible hardware faults 1153 * or manufacturing defects that can cause the media options register 1154 * (or reset options register, as it's called for the first generation 1155 * 3c90x adapters) to return an incorrect result. I have encountered 1156 * one Dell Latitude laptop docking station with an integrated 3c905-TX 1157 * which doesn't have any of the 'mediaopt' bits set. This screws up 1158 * the attach routine pretty badly because it doesn't know what media 1159 * to look for. If we find ourselves in this predicament, this routine 1160 * will try to guess the media options values and warn the user of a 1161 * possible manufacturing defect with his adapter/system/whatever. 1162 */ 1163 static void 1164 xl_mediacheck(sc) 1165 struct xl_softc *sc; 1166 { 1167 1168 /* 1169 * If some of the media options bits are set, assume they are 1170 * correct. If not, try to figure it out down below. 1171 * XXX I should check for 10baseFL, but I don't have an adapter 1172 * to test with. 1173 */ 1174 if (sc->xl_media & (XL_MEDIAOPT_MASK & ~XL_MEDIAOPT_VCO)) { 1175 /* 1176 * Check the XCVR value. If it's not in the normal range 1177 * of values, we need to fake it up here. 1178 */ 1179 if (sc->xl_xcvr <= XL_XCVR_AUTO) 1180 return; 1181 else { 1182 printf("xl%d: bogus xcvr value " 1183 "in EEPROM (%x)\n", sc->xl_unit, sc->xl_xcvr); 1184 printf("xl%d: choosing new default based " 1185 "on card type\n", sc->xl_unit); 1186 } 1187 } else { 1188 if (sc->xl_type == XL_TYPE_905B && 1189 sc->xl_media & XL_MEDIAOPT_10FL) 1190 return; 1191 printf("xl%d: WARNING: no media options bits set in " 1192 "the media options register!!\n", sc->xl_unit); 1193 printf("xl%d: this could be a manufacturing defect in " 1194 "your adapter or system\n", sc->xl_unit); 1195 printf("xl%d: attempting to guess media type; you " 1196 "should probably consult your vendor\n", sc->xl_unit); 1197 } 1198 1199 xl_choose_xcvr(sc, 1); 1200 1201 return; 1202 } 1203 1204 static void 1205 xl_choose_xcvr(sc, verbose) 1206 struct xl_softc *sc; 1207 int verbose; 1208 { 1209 u_int16_t devid; 1210 1211 /* 1212 * Read the device ID from the EEPROM. 1213 * This is what's loaded into the PCI device ID register, so it has 1214 * to be correct otherwise we wouldn't have gotten this far. 1215 */ 1216 xl_read_eeprom(sc, (caddr_t)&devid, XL_EE_PRODID, 1, 0); 1217 1218 switch(devid) { 1219 case TC_DEVICEID_BOOMERANG_10BT: /* 3c900-TPO */ 1220 case TC_DEVICEID_KRAKATOA_10BT: /* 3c900B-TPO */ 1221 sc->xl_media = XL_MEDIAOPT_BT; 1222 sc->xl_xcvr = XL_XCVR_10BT; 1223 if (verbose) 1224 printf("xl%d: guessing 10BaseT " 1225 "transceiver\n", sc->xl_unit); 1226 break; 1227 case TC_DEVICEID_BOOMERANG_10BT_COMBO: /* 3c900-COMBO */ 1228 case TC_DEVICEID_KRAKATOA_10BT_COMBO: /* 3c900B-COMBO */ 1229 sc->xl_media = XL_MEDIAOPT_BT|XL_MEDIAOPT_BNC|XL_MEDIAOPT_AUI; 1230 sc->xl_xcvr = XL_XCVR_10BT; 1231 if (verbose) 1232 printf("xl%d: guessing COMBO " 1233 "(AUI/BNC/TP)\n", sc->xl_unit); 1234 break; 1235 case TC_DEVICEID_KRAKATOA_10BT_TPC: /* 3c900B-TPC */ 1236 sc->xl_media = XL_MEDIAOPT_BT|XL_MEDIAOPT_BNC; 1237 sc->xl_xcvr = XL_XCVR_10BT; 1238 if (verbose) 1239 printf("xl%d: guessing TPC (BNC/TP)\n", sc->xl_unit); 1240 break; 1241 case TC_DEVICEID_CYCLONE_10FL: /* 3c900B-FL */ 1242 sc->xl_media = XL_MEDIAOPT_10FL; 1243 sc->xl_xcvr = XL_XCVR_AUI; 1244 if (verbose) 1245 printf("xl%d: guessing 10baseFL\n", sc->xl_unit); 1246 break; 1247 case TC_DEVICEID_BOOMERANG_10_100BT: /* 3c905-TX */ 1248 case TC_DEVICEID_HURRICANE_555: /* 3c555 */ 1249 case TC_DEVICEID_HURRICANE_556: /* 3c556 */ 1250 case TC_DEVICEID_HURRICANE_556B: /* 3c556B */ 1251 case TC_DEVICEID_HURRICANE_575A: /* 3c575TX */ 1252 case TC_DEVICEID_HURRICANE_575B: /* 3c575B */ 1253 case TC_DEVICEID_HURRICANE_575C: /* 3c575C */ 1254 case TC_DEVICEID_HURRICANE_656: /* 3c656 */ 1255 case TC_DEVICEID_HURRICANE_656B: /* 3c656B */ 1256 case TC_DEVICEID_TORNADO_656C: /* 3c656C */ 1257 case TC_DEVICEID_TORNADO_10_100BT_920B: /* 3c920B-EMB */ 1258 sc->xl_media = XL_MEDIAOPT_MII; 1259 sc->xl_xcvr = XL_XCVR_MII; 1260 if (verbose) 1261 printf("xl%d: guessing MII\n", sc->xl_unit); 1262 break; 1263 case TC_DEVICEID_BOOMERANG_100BT4: /* 3c905-T4 */ 1264 case TC_DEVICEID_CYCLONE_10_100BT4: /* 3c905B-T4 */ 1265 sc->xl_media = XL_MEDIAOPT_BT4; 1266 sc->xl_xcvr = XL_XCVR_MII; 1267 if (verbose) 1268 printf("xl%d: guessing 100BaseT4/MII\n", sc->xl_unit); 1269 break; 1270 case TC_DEVICEID_HURRICANE_10_100BT: /* 3c905B-TX */ 1271 case TC_DEVICEID_HURRICANE_10_100BT_SERV:/*3c980-TX */ 1272 case TC_DEVICEID_TORNADO_10_100BT_SERV: /* 3c980C-TX */ 1273 case TC_DEVICEID_HURRICANE_SOHO100TX: /* 3cSOHO100-TX */ 1274 case TC_DEVICEID_TORNADO_10_100BT: /* 3c905C-TX */ 1275 case TC_DEVICEID_TORNADO_HOMECONNECT: /* 3c450-TX */ 1276 sc->xl_media = XL_MEDIAOPT_BTX; 1277 sc->xl_xcvr = XL_XCVR_AUTO; 1278 if (verbose) 1279 printf("xl%d: guessing 10/100 internal\n", sc->xl_unit); 1280 break; 1281 case TC_DEVICEID_CYCLONE_10_100_COMBO: /* 3c905B-COMBO */ 1282 sc->xl_media = XL_MEDIAOPT_BTX|XL_MEDIAOPT_BNC|XL_MEDIAOPT_AUI; 1283 sc->xl_xcvr = XL_XCVR_AUTO; 1284 if (verbose) 1285 printf("xl%d: guessing 10/100 " 1286 "plus BNC/AUI\n", sc->xl_unit); 1287 break; 1288 default: 1289 printf("xl%d: unknown device ID: %x -- " 1290 "defaulting to 10baseT\n", sc->xl_unit, devid); 1291 sc->xl_media = XL_MEDIAOPT_BT; 1292 break; 1293 } 1294 1295 return; 1296 } 1297 1298 /* 1299 * Attach the interface. Allocate softc structures, do ifmedia 1300 * setup and ethernet/BPF attach. 1301 */ 1302 static int 1303 xl_attach(dev) 1304 device_t dev; 1305 { 1306 int s; 1307 u_char eaddr[ETHER_ADDR_LEN]; 1308 u_int16_t xcvr[2]; 1309 u_int32_t command; 1310 struct xl_softc *sc; 1311 struct ifnet *ifp; 1312 int media = IFM_ETHER|IFM_100_TX|IFM_FDX; 1313 int unit, error = 0, rid, res; 1314 1315 s = splimp(); 1316 1317 sc = device_get_softc(dev); 1318 unit = device_get_unit(dev); 1319 1320 ifmedia_init(&sc->ifmedia, 0, xl_ifmedia_upd, xl_ifmedia_sts); 1321 1322 sc->xl_flags = 0; 1323 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_555) 1324 sc->xl_flags |= XL_FLAG_EEPROM_OFFSET_30 | XL_FLAG_PHYOK; 1325 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_556 || 1326 pci_get_device(dev) == TC_DEVICEID_HURRICANE_556B) 1327 sc->xl_flags |= XL_FLAG_FUNCREG | XL_FLAG_PHYOK | 1328 XL_FLAG_EEPROM_OFFSET_30 | XL_FLAG_WEIRDRESET | 1329 XL_FLAG_INVERT_LED_PWR | XL_FLAG_INVERT_MII_PWR; 1330 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_555 || 1331 pci_get_device(dev) == TC_DEVICEID_HURRICANE_556) 1332 sc->xl_flags |= XL_FLAG_8BITROM; 1333 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_556B) 1334 sc->xl_flags |= XL_FLAG_NO_XCVR_PWR; 1335 1336 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_575A || 1337 pci_get_device(dev) == TC_DEVICEID_HURRICANE_575B || 1338 pci_get_device(dev) == TC_DEVICEID_HURRICANE_575C || 1339 pci_get_device(dev) == TC_DEVICEID_HURRICANE_656B || 1340 pci_get_device(dev) == TC_DEVICEID_TORNADO_656C) 1341 sc->xl_flags |= XL_FLAG_FUNCREG | XL_FLAG_PHYOK | 1342 XL_FLAG_EEPROM_OFFSET_30 | XL_FLAG_8BITROM; 1343 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_656) 1344 sc->xl_flags |= XL_FLAG_FUNCREG | XL_FLAG_PHYOK; 1345 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_575B) 1346 sc->xl_flags |= XL_FLAG_INVERT_LED_PWR; 1347 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_575C) 1348 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR; 1349 if (pci_get_device(dev) == TC_DEVICEID_TORNADO_656C) 1350 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR; 1351 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_656 || 1352 pci_get_device(dev) == TC_DEVICEID_HURRICANE_656B) 1353 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR | 1354 XL_FLAG_INVERT_LED_PWR; 1355 if (pci_get_device(dev) == TC_DEVICEID_TORNADO_10_100BT_920B) 1356 sc->xl_flags |= XL_FLAG_PHYOK; 1357 #ifndef BURN_BRIDGES 1358 /* 1359 * If this is a 3c905B, we have to check one extra thing. 1360 * The 905B supports power management and may be placed in 1361 * a low-power mode (D3 mode), typically by certain operating 1362 * systems which shall not be named. The PCI BIOS is supposed 1363 * to reset the NIC and bring it out of low-power mode, but 1364 * some do not. Consequently, we have to see if this chip 1365 * supports power management, and if so, make sure it's not 1366 * in low-power mode. If power management is available, the 1367 * capid byte will be 0x01. 1368 * 1369 * I _think_ that what actually happens is that the chip 1370 * loses its PCI configuration during the transition from 1371 * D3 back to D0; this means that it should be possible for 1372 * us to save the PCI iobase, membase and IRQ, put the chip 1373 * back in the D0 state, then restore the PCI config ourselves. 1374 */ 1375 1376 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 1377 u_int32_t iobase, membase, irq; 1378 1379 /* Save important PCI config data. */ 1380 iobase = pci_read_config(dev, XL_PCI_LOIO, 4); 1381 membase = pci_read_config(dev, XL_PCI_LOMEM, 4); 1382 irq = pci_read_config(dev, XL_PCI_INTLINE, 4); 1383 1384 /* Reset the power state. */ 1385 printf("xl%d: chip is in D%d power mode " 1386 "-- setting to D0\n", unit, 1387 pci_get_powerstate(dev)); 1388 1389 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 1390 1391 /* Restore PCI config data. */ 1392 pci_write_config(dev, XL_PCI_LOIO, iobase, 4); 1393 pci_write_config(dev, XL_PCI_LOMEM, membase, 4); 1394 pci_write_config(dev, XL_PCI_INTLINE, irq, 4); 1395 } 1396 #endif 1397 /* 1398 * Map control/status registers. 1399 */ 1400 pci_enable_busmaster(dev); 1401 pci_enable_io(dev, SYS_RES_IOPORT); 1402 pci_enable_io(dev, SYS_RES_MEMORY); 1403 command = pci_read_config(dev, PCIR_COMMAND, 4); 1404 1405 if (!(command & PCIM_CMD_PORTEN) && !(command & PCIM_CMD_MEMEN)) { 1406 printf("xl%d: failed to enable I/O ports and memory mappings!\n", unit); 1407 error = ENXIO; 1408 goto fail; 1409 } 1410 1411 rid = XL_PCI_LOMEM; 1412 res = SYS_RES_MEMORY; 1413 1414 #if 0 1415 sc->xl_res = bus_alloc_resource(dev, res, &rid, 1416 0, ~0, 1, RF_ACTIVE); 1417 #endif 1418 1419 if (sc->xl_res != NULL) { 1420 sc->xl_flags |= XL_FLAG_USE_MMIO; 1421 if (bootverbose) 1422 printf("xl%d: using memory mapped I/O\n", unit); 1423 } else { 1424 rid = XL_PCI_LOIO; 1425 res = SYS_RES_IOPORT; 1426 sc->xl_res = bus_alloc_resource(dev, res, &rid, 1427 0, ~0, 1, RF_ACTIVE); 1428 if (sc->xl_res == NULL) { 1429 printf ("xl%d: couldn't map ports/memory\n", unit); 1430 error = ENXIO; 1431 goto fail; 1432 } 1433 if (bootverbose) 1434 printf("xl%d: using port I/O\n", unit); 1435 } 1436 1437 sc->xl_btag = rman_get_bustag(sc->xl_res); 1438 sc->xl_bhandle = rman_get_bushandle(sc->xl_res); 1439 1440 if (sc->xl_flags & XL_FLAG_FUNCREG) { 1441 rid = XL_PCI_FUNCMEM; 1442 sc->xl_fres = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 1443 0, ~0, 1, RF_ACTIVE); 1444 1445 if (sc->xl_fres == NULL) { 1446 printf ("xl%d: couldn't map ports/memory\n", unit); 1447 error = ENXIO; 1448 goto fail; 1449 } 1450 1451 sc->xl_ftag = rman_get_bustag(sc->xl_fres); 1452 sc->xl_fhandle = rman_get_bushandle(sc->xl_fres); 1453 } 1454 1455 /* Allocate interrupt */ 1456 rid = 0; 1457 sc->xl_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 1458 RF_SHAREABLE | RF_ACTIVE); 1459 if (sc->xl_irq == NULL) { 1460 printf("xl%d: couldn't map interrupt\n", unit); 1461 error = ENXIO; 1462 goto fail; 1463 } 1464 1465 sc->xl_flags |= XL_FLAG_ATTACH_MAPPED; 1466 1467 /* Reset the adapter. */ 1468 xl_reset(sc); 1469 1470 /* 1471 * Get station address from the EEPROM. 1472 */ 1473 if (xl_read_eeprom(sc, (caddr_t)&eaddr, XL_EE_OEM_ADR0, 3, 1)) { 1474 printf("xl%d: failed to read station address\n", sc->xl_unit); 1475 error = ENXIO; 1476 goto fail; 1477 } 1478 1479 sc->xl_unit = unit; 1480 callout_init(&sc->xl_stat_timer); 1481 1482 /* 1483 * Now allocate a tag for the DMA descriptor lists and a chunk 1484 * of DMA-able memory based on the tag. Also obtain the DMA 1485 * addresses of the RX and TX ring, which we'll need later. 1486 * All of our lists are allocated as a contiguous block 1487 * of memory. 1488 */ 1489 error = bus_dma_tag_create(NULL, 8, 0, 1490 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 1491 XL_RX_LIST_SZ, 1, XL_RX_LIST_SZ, 0, 1492 &sc->xl_ldata.xl_rx_tag); 1493 if (error) { 1494 printf("xl%d: failed to allocate rx dma tag\n", unit); 1495 goto fail; 1496 } 1497 1498 error = bus_dmamem_alloc(sc->xl_ldata.xl_rx_tag, 1499 (void **)&sc->xl_ldata.xl_rx_list, BUS_DMA_NOWAIT, 1500 &sc->xl_ldata.xl_rx_dmamap); 1501 if (error) { 1502 printf("xl%d: no memory for rx list buffers!\n", unit); 1503 bus_dma_tag_destroy(sc->xl_ldata.xl_rx_tag); 1504 sc->xl_ldata.xl_rx_tag = NULL; 1505 goto fail; 1506 } 1507 1508 error = bus_dmamap_load(sc->xl_ldata.xl_rx_tag, 1509 sc->xl_ldata.xl_rx_dmamap, sc->xl_ldata.xl_rx_list, 1510 XL_RX_LIST_SZ, xl_dma_map_addr, 1511 &sc->xl_ldata.xl_rx_dmaaddr, BUS_DMA_NOWAIT); 1512 if (error) { 1513 printf("xl%d: cannot get dma address of the rx ring!\n", unit); 1514 bus_dmamem_free(sc->xl_ldata.xl_rx_tag, sc->xl_ldata.xl_rx_list, 1515 sc->xl_ldata.xl_rx_dmamap); 1516 bus_dma_tag_destroy(sc->xl_ldata.xl_rx_tag); 1517 sc->xl_ldata.xl_rx_tag = NULL; 1518 goto fail; 1519 } 1520 1521 error = bus_dma_tag_create(NULL, 8, 0, 1522 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 1523 XL_TX_LIST_SZ, 1, XL_TX_LIST_SZ, 0, 1524 &sc->xl_ldata.xl_tx_tag); 1525 if (error) { 1526 printf("xl%d: failed to allocate tx dma tag\n", unit); 1527 goto fail; 1528 } 1529 1530 error = bus_dmamem_alloc(sc->xl_ldata.xl_tx_tag, 1531 (void **)&sc->xl_ldata.xl_tx_list, BUS_DMA_NOWAIT, 1532 &sc->xl_ldata.xl_tx_dmamap); 1533 if (error) { 1534 printf("xl%d: no memory for list buffers!\n", unit); 1535 bus_dma_tag_destroy(sc->xl_ldata.xl_tx_tag); 1536 sc->xl_ldata.xl_tx_tag = NULL; 1537 goto fail; 1538 } 1539 1540 error = bus_dmamap_load(sc->xl_ldata.xl_tx_tag, 1541 sc->xl_ldata.xl_tx_dmamap, sc->xl_ldata.xl_tx_list, 1542 XL_TX_LIST_SZ, xl_dma_map_addr, 1543 &sc->xl_ldata.xl_tx_dmaaddr, BUS_DMA_NOWAIT); 1544 if (error) { 1545 printf("xl%d: cannot get dma address of the tx ring!\n", unit); 1546 bus_dmamem_free(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_list, 1547 sc->xl_ldata.xl_tx_dmamap); 1548 bus_dma_tag_destroy(sc->xl_ldata.xl_tx_tag); 1549 sc->xl_ldata.xl_tx_tag = NULL; 1550 goto fail; 1551 } 1552 1553 /* 1554 * Allocate a DMA tag for the mapping of mbufs. 1555 */ 1556 error = bus_dma_tag_create(NULL, 1, 0, 1557 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 1558 MCLBYTES * XL_MAXFRAGS, XL_MAXFRAGS, MCLBYTES, 0, 1559 &sc->xl_mtag); 1560 if (error) { 1561 printf("xl%d: failed to allocate mbuf dma tag\n", unit); 1562 goto fail; 1563 } 1564 1565 bzero(sc->xl_ldata.xl_tx_list, XL_TX_LIST_SZ); 1566 bzero(sc->xl_ldata.xl_rx_list, XL_RX_LIST_SZ); 1567 1568 /* We need a spare DMA map for the RX ring. */ 1569 error = bus_dmamap_create(sc->xl_mtag, 0, &sc->xl_tmpmap); 1570 if (error) 1571 goto fail; 1572 1573 /* 1574 * Figure out the card type. 3c905B adapters have the 1575 * 'supportsNoTxLength' bit set in the capabilities 1576 * word in the EEPROM. 1577 * Note: my 3c575C cardbus card lies. It returns a value 1578 * of 0x1578 for its capabilities word, which is somewhat 1579 * nonsensical. Another way to distinguish a 3c90x chip 1580 * from a 3c90xB/C chip is to check for the 'supportsLargePackets' 1581 * bit. This will only be set for 3c90x boomerage chips. 1582 */ 1583 xl_read_eeprom(sc, (caddr_t)&sc->xl_caps, XL_EE_CAPS, 1, 0); 1584 if (sc->xl_caps & XL_CAPS_NO_TXLENGTH || 1585 !(sc->xl_caps & XL_CAPS_LARGE_PKTS)) 1586 sc->xl_type = XL_TYPE_905B; 1587 else 1588 sc->xl_type = XL_TYPE_90X; 1589 1590 ifp = &sc->arpcom.ac_if; 1591 ifp->if_softc = sc; 1592 if_initname(ifp, "xl", unit); 1593 ifp->if_mtu = ETHERMTU; 1594 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1595 ifp->if_ioctl = xl_ioctl; 1596 ifp->if_capabilities = 0; 1597 if (sc->xl_type == XL_TYPE_905B) { 1598 ifp->if_start = xl_start_90xB; 1599 ifp->if_capabilities |= IFCAP_HWCSUM; 1600 } else { 1601 ifp->if_start = xl_start; 1602 } 1603 ifp->if_watchdog = xl_watchdog; 1604 ifp->if_init = xl_init; 1605 ifp->if_baudrate = 10000000; 1606 ifp->if_snd.ifq_maxlen = XL_TX_LIST_CNT - 1; 1607 /* 1608 * NOTE: features disabled by default. This seems to corrupt 1609 * tx packet data one out of a million packets or so and then 1610 * generates a good checksum so the receiver doesn't 1611 * know the packet is bad 1612 */ 1613 ifp->if_capenable = 0; /*ifp->if_capabilities;*/ 1614 if (ifp->if_capenable & IFCAP_TXCSUM) 1615 ifp->if_hwassist = XL905B_CSUM_FEATURES; 1616 1617 /* 1618 * Now we have to see what sort of media we have. 1619 * This includes probing for an MII interace and a 1620 * possible PHY. 1621 */ 1622 XL_SEL_WIN(3); 1623 sc->xl_media = CSR_READ_2(sc, XL_W3_MEDIA_OPT); 1624 if (bootverbose) 1625 printf("xl%d: media options word: %x\n", sc->xl_unit, 1626 sc->xl_media); 1627 1628 xl_read_eeprom(sc, (char *)&xcvr, XL_EE_ICFG_0, 2, 0); 1629 sc->xl_xcvr = xcvr[0] | xcvr[1] << 16; 1630 sc->xl_xcvr &= XL_ICFG_CONNECTOR_MASK; 1631 sc->xl_xcvr >>= XL_ICFG_CONNECTOR_BITS; 1632 1633 xl_mediacheck(sc); 1634 1635 if (sc->xl_media & XL_MEDIAOPT_MII || sc->xl_media & XL_MEDIAOPT_BTX 1636 || sc->xl_media & XL_MEDIAOPT_BT4) { 1637 if (bootverbose) 1638 printf("xl%d: found MII/AUTO\n", sc->xl_unit); 1639 xl_setcfg(sc); 1640 if (mii_phy_probe(dev, &sc->xl_miibus, 1641 xl_ifmedia_upd, xl_ifmedia_sts)) { 1642 printf("xl%d: no PHY found!\n", sc->xl_unit); 1643 error = ENXIO; 1644 goto fail; 1645 } 1646 1647 goto done; 1648 } 1649 1650 /* 1651 * Sanity check. If the user has selected "auto" and this isn't 1652 * a 10/100 card of some kind, we need to force the transceiver 1653 * type to something sane. 1654 */ 1655 if (sc->xl_xcvr == XL_XCVR_AUTO) 1656 xl_choose_xcvr(sc, bootverbose); 1657 1658 /* 1659 * Do ifmedia setup. 1660 */ 1661 if (sc->xl_media & XL_MEDIAOPT_BT) { 1662 if (bootverbose) 1663 printf("xl%d: found 10baseT\n", sc->xl_unit); 1664 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL); 1665 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T|IFM_HDX, 0, NULL); 1666 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX) 1667 ifmedia_add(&sc->ifmedia, 1668 IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL); 1669 } 1670 1671 if (sc->xl_media & (XL_MEDIAOPT_AUI|XL_MEDIAOPT_10FL)) { 1672 /* 1673 * Check for a 10baseFL board in disguise. 1674 */ 1675 if (sc->xl_type == XL_TYPE_905B && 1676 sc->xl_media == XL_MEDIAOPT_10FL) { 1677 if (bootverbose) 1678 printf("xl%d: found 10baseFL\n", sc->xl_unit); 1679 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_FL, 0, NULL); 1680 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_FL|IFM_HDX, 1681 0, NULL); 1682 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX) 1683 ifmedia_add(&sc->ifmedia, 1684 IFM_ETHER|IFM_10_FL|IFM_FDX, 0, NULL); 1685 } else { 1686 if (bootverbose) 1687 printf("xl%d: found AUI\n", sc->xl_unit); 1688 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_5, 0, NULL); 1689 } 1690 } 1691 1692 if (sc->xl_media & XL_MEDIAOPT_BNC) { 1693 if (bootverbose) 1694 printf("xl%d: found BNC\n", sc->xl_unit); 1695 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_2, 0, NULL); 1696 } 1697 1698 if (sc->xl_media & XL_MEDIAOPT_BFX) { 1699 if (bootverbose) 1700 printf("xl%d: found 100baseFX\n", sc->xl_unit); 1701 ifp->if_baudrate = 100000000; 1702 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_FX, 0, NULL); 1703 } 1704 1705 /* Choose a default media. */ 1706 switch(sc->xl_xcvr) { 1707 case XL_XCVR_10BT: 1708 media = IFM_ETHER|IFM_10_T; 1709 xl_setmode(sc, media); 1710 break; 1711 case XL_XCVR_AUI: 1712 if (sc->xl_type == XL_TYPE_905B && 1713 sc->xl_media == XL_MEDIAOPT_10FL) { 1714 media = IFM_ETHER|IFM_10_FL; 1715 xl_setmode(sc, media); 1716 } else { 1717 media = IFM_ETHER|IFM_10_5; 1718 xl_setmode(sc, media); 1719 } 1720 break; 1721 case XL_XCVR_COAX: 1722 media = IFM_ETHER|IFM_10_2; 1723 xl_setmode(sc, media); 1724 break; 1725 case XL_XCVR_AUTO: 1726 case XL_XCVR_100BTX: 1727 case XL_XCVR_MII: 1728 /* Chosen by miibus */ 1729 break; 1730 case XL_XCVR_100BFX: 1731 media = IFM_ETHER|IFM_100_FX; 1732 break; 1733 default: 1734 printf("xl%d: unknown XCVR type: %d\n", sc->xl_unit, 1735 sc->xl_xcvr); 1736 /* 1737 * This will probably be wrong, but it prevents 1738 * the ifmedia code from panicking. 1739 */ 1740 media = IFM_ETHER|IFM_10_T; 1741 break; 1742 } 1743 1744 if (sc->xl_miibus == NULL) 1745 ifmedia_set(&sc->ifmedia, media); 1746 1747 done: 1748 1749 if (sc->xl_flags & XL_FLAG_NO_XCVR_PWR) { 1750 XL_SEL_WIN(0); 1751 CSR_WRITE_2(sc, XL_W0_MFG_ID, XL_NO_XCVR_PWR_MAGICBITS); 1752 } 1753 1754 /* 1755 * Call MI attach routine. 1756 */ 1757 ether_ifattach(ifp, eaddr); 1758 1759 /* 1760 * Tell the upper layer(s) we support long frames. 1761 */ 1762 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1763 1764 /* Hook interrupt last to avoid having to lock softc */ 1765 error = bus_setup_intr(dev, sc->xl_irq, INTR_TYPE_NET, 1766 xl_intr, sc, &sc->xl_intrhand); 1767 if (error) { 1768 printf("xl%d: couldn't set up irq\n", unit); 1769 ether_ifdetach(ifp); 1770 goto fail; 1771 } 1772 1773 fail: 1774 if (error) 1775 xl_detach(dev); 1776 1777 splx(s); 1778 1779 return(error); 1780 } 1781 1782 /* 1783 * Shutdown hardware and free up resources. This can be called any 1784 * time after the mutex has been initialized. It is called in both 1785 * the error case in attach and the normal detach case so it needs 1786 * to be careful about only freeing resources that have actually been 1787 * allocated. 1788 */ 1789 static int 1790 xl_detach(dev) 1791 device_t dev; 1792 { 1793 struct xl_softc *sc; 1794 struct ifnet *ifp; 1795 int rid, res; 1796 int s; 1797 1798 s = splimp(); 1799 1800 sc = device_get_softc(dev); 1801 ifp = &sc->arpcom.ac_if; 1802 1803 if (sc->xl_flags & XL_FLAG_USE_MMIO) { 1804 rid = XL_PCI_LOMEM; 1805 res = SYS_RES_MEMORY; 1806 } else { 1807 rid = XL_PCI_LOIO; 1808 res = SYS_RES_IOPORT; 1809 } 1810 1811 /* 1812 * Only try to communicate with the device if we were able to map 1813 * the ports. This flag is set before ether_ifattach() so it also 1814 * governs our call to ether_ifdetach(). 1815 */ 1816 if (sc->xl_flags & XL_FLAG_ATTACH_MAPPED) { 1817 xl_reset(sc); 1818 xl_stop(sc); 1819 ether_ifdetach(ifp); 1820 } 1821 1822 if (sc->xl_miibus) 1823 device_delete_child(dev, sc->xl_miibus); 1824 bus_generic_detach(dev); 1825 ifmedia_removeall(&sc->ifmedia); 1826 1827 if (sc->xl_intrhand) 1828 bus_teardown_intr(dev, sc->xl_irq, sc->xl_intrhand); 1829 if (sc->xl_irq) 1830 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->xl_irq); 1831 if (sc->xl_fres != NULL) 1832 bus_release_resource(dev, SYS_RES_MEMORY, 1833 XL_PCI_FUNCMEM, sc->xl_fres); 1834 if (sc->xl_res) 1835 bus_release_resource(dev, res, rid, sc->xl_res); 1836 1837 if (sc->xl_mtag) { 1838 bus_dmamap_destroy(sc->xl_mtag, sc->xl_tmpmap); 1839 bus_dma_tag_destroy(sc->xl_mtag); 1840 } 1841 if (sc->xl_ldata.xl_rx_tag) { 1842 bus_dmamap_unload(sc->xl_ldata.xl_rx_tag, 1843 sc->xl_ldata.xl_rx_dmamap); 1844 bus_dmamem_free(sc->xl_ldata.xl_rx_tag, sc->xl_ldata.xl_rx_list, 1845 sc->xl_ldata.xl_rx_dmamap); 1846 bus_dma_tag_destroy(sc->xl_ldata.xl_rx_tag); 1847 } 1848 if (sc->xl_ldata.xl_tx_tag) { 1849 bus_dmamap_unload(sc->xl_ldata.xl_tx_tag, 1850 sc->xl_ldata.xl_tx_dmamap); 1851 bus_dmamem_free(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_list, 1852 sc->xl_ldata.xl_tx_dmamap); 1853 bus_dma_tag_destroy(sc->xl_ldata.xl_tx_tag); 1854 } 1855 1856 splx(s); 1857 1858 return(0); 1859 } 1860 1861 /* 1862 * Initialize the transmit descriptors. 1863 */ 1864 static int 1865 xl_list_tx_init(sc) 1866 struct xl_softc *sc; 1867 { 1868 struct xl_chain_data *cd; 1869 struct xl_list_data *ld; 1870 int error, i; 1871 1872 cd = &sc->xl_cdata; 1873 ld = &sc->xl_ldata; 1874 for (i = 0; i < XL_TX_LIST_CNT; i++) { 1875 cd->xl_tx_chain[i].xl_ptr = &ld->xl_tx_list[i]; 1876 error = bus_dmamap_create(sc->xl_mtag, 0, 1877 &cd->xl_tx_chain[i].xl_map); 1878 if (error) 1879 return(error); 1880 cd->xl_tx_chain[i].xl_phys = ld->xl_tx_dmaaddr + 1881 i * sizeof(struct xl_list); 1882 if (i == (XL_TX_LIST_CNT - 1)) 1883 cd->xl_tx_chain[i].xl_next = NULL; 1884 else 1885 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[i + 1]; 1886 } 1887 1888 cd->xl_tx_free = &cd->xl_tx_chain[0]; 1889 cd->xl_tx_tail = cd->xl_tx_head = NULL; 1890 1891 bus_dmamap_sync(ld->xl_tx_tag, ld->xl_tx_dmamap, BUS_DMASYNC_PREWRITE); 1892 return(0); 1893 } 1894 1895 /* 1896 * Initialize the transmit descriptors. 1897 */ 1898 static int 1899 xl_list_tx_init_90xB(sc) 1900 struct xl_softc *sc; 1901 { 1902 struct xl_chain_data *cd; 1903 struct xl_list_data *ld; 1904 int error, i; 1905 1906 cd = &sc->xl_cdata; 1907 ld = &sc->xl_ldata; 1908 for (i = 0; i < XL_TX_LIST_CNT; i++) { 1909 cd->xl_tx_chain[i].xl_ptr = &ld->xl_tx_list[i]; 1910 error = bus_dmamap_create(sc->xl_mtag, 0, 1911 &cd->xl_tx_chain[i].xl_map); 1912 if (error) 1913 return(error); 1914 cd->xl_tx_chain[i].xl_phys = ld->xl_tx_dmaaddr + 1915 i * sizeof(struct xl_list); 1916 if (i == (XL_TX_LIST_CNT - 1)) 1917 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[0]; 1918 else 1919 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[i + 1]; 1920 if (i == 0) 1921 cd->xl_tx_chain[i].xl_prev = 1922 &cd->xl_tx_chain[XL_TX_LIST_CNT - 1]; 1923 else 1924 cd->xl_tx_chain[i].xl_prev = 1925 &cd->xl_tx_chain[i - 1]; 1926 } 1927 1928 bzero(ld->xl_tx_list, XL_TX_LIST_SZ); 1929 ld->xl_tx_list[0].xl_status = htole32(XL_TXSTAT_EMPTY); 1930 1931 cd->xl_tx_prod = 1; 1932 cd->xl_tx_cons = 1; 1933 cd->xl_tx_cnt = 0; 1934 1935 bus_dmamap_sync(ld->xl_tx_tag, ld->xl_tx_dmamap, BUS_DMASYNC_PREWRITE); 1936 return(0); 1937 } 1938 1939 /* 1940 * Initialize the RX descriptors and allocate mbufs for them. Note that 1941 * we arrange the descriptors in a closed ring, so that the last descriptor 1942 * points back to the first. 1943 */ 1944 static int 1945 xl_list_rx_init(sc) 1946 struct xl_softc *sc; 1947 { 1948 struct xl_chain_data *cd; 1949 struct xl_list_data *ld; 1950 int error, i, next; 1951 u_int32_t nextptr; 1952 1953 cd = &sc->xl_cdata; 1954 ld = &sc->xl_ldata; 1955 1956 for (i = 0; i < XL_RX_LIST_CNT; i++) { 1957 cd->xl_rx_chain[i].xl_ptr = &ld->xl_rx_list[i]; 1958 error = bus_dmamap_create(sc->xl_mtag, 0, 1959 &cd->xl_rx_chain[i].xl_map); 1960 if (error) 1961 return(error); 1962 error = xl_newbuf(sc, &cd->xl_rx_chain[i]); 1963 if (error) 1964 return(error); 1965 if (i == (XL_RX_LIST_CNT - 1)) 1966 next = 0; 1967 else 1968 next = i + 1; 1969 nextptr = ld->xl_rx_dmaaddr + 1970 next * sizeof(struct xl_list_onefrag); 1971 cd->xl_rx_chain[i].xl_next = &cd->xl_rx_chain[next]; 1972 ld->xl_rx_list[i].xl_next = htole32(nextptr); 1973 } 1974 1975 bus_dmamap_sync(ld->xl_rx_tag, ld->xl_rx_dmamap, BUS_DMASYNC_PREWRITE); 1976 cd->xl_rx_head = &cd->xl_rx_chain[0]; 1977 1978 return(0); 1979 } 1980 1981 /* 1982 * Initialize an RX descriptor and attach an MBUF cluster. 1983 * If we fail to do so, we need to leave the old mbuf and 1984 * the old DMA map untouched so that it can be reused. 1985 */ 1986 static int 1987 xl_newbuf(sc, c) 1988 struct xl_softc *sc; 1989 struct xl_chain_onefrag *c; 1990 { 1991 struct mbuf *m_new = NULL; 1992 bus_dmamap_t map; 1993 int error; 1994 u_int32_t baddr; 1995 1996 m_new = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR); 1997 if (m_new == NULL) 1998 return(ENOBUFS); 1999 2000 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 2001 2002 /* Force longword alignment for packet payload. */ 2003 m_adj(m_new, ETHER_ALIGN); 2004 2005 error = bus_dmamap_load_mbuf(sc->xl_mtag, sc->xl_tmpmap, m_new, 2006 xl_dma_map_rxbuf, &baddr, BUS_DMA_NOWAIT); 2007 if (error) { 2008 m_freem(m_new); 2009 printf("xl%d: can't map mbuf (error %d)\n", sc->xl_unit, error); 2010 return(error); 2011 } 2012 2013 bus_dmamap_unload(sc->xl_mtag, c->xl_map); 2014 map = c->xl_map; 2015 c->xl_map = sc->xl_tmpmap; 2016 sc->xl_tmpmap = map; 2017 c->xl_mbuf = m_new; 2018 c->xl_ptr->xl_frag.xl_len = htole32(m_new->m_len | XL_LAST_FRAG); 2019 c->xl_ptr->xl_status = 0; 2020 c->xl_ptr->xl_frag.xl_addr = htole32(baddr); 2021 bus_dmamap_sync(sc->xl_mtag, c->xl_map, BUS_DMASYNC_PREREAD); 2022 return(0); 2023 } 2024 2025 static int 2026 xl_rx_resync(sc) 2027 struct xl_softc *sc; 2028 { 2029 struct xl_chain_onefrag *pos; 2030 int i; 2031 2032 pos = sc->xl_cdata.xl_rx_head; 2033 2034 for (i = 0; i < XL_RX_LIST_CNT; i++) { 2035 if (pos->xl_ptr->xl_status) 2036 break; 2037 pos = pos->xl_next; 2038 } 2039 2040 if (i == XL_RX_LIST_CNT) 2041 return(0); 2042 2043 sc->xl_cdata.xl_rx_head = pos; 2044 2045 return(EAGAIN); 2046 } 2047 2048 /* 2049 * A frame has been uploaded: pass the resulting mbuf chain up to 2050 * the higher level protocols. 2051 */ 2052 static void 2053 xl_rxeof(sc) 2054 struct xl_softc *sc; 2055 { 2056 struct mbuf *m; 2057 struct ifnet *ifp; 2058 struct xl_chain_onefrag *cur_rx; 2059 int total_len = 0; 2060 u_int32_t rxstat; 2061 2062 ifp = &sc->arpcom.ac_if; 2063 2064 again: 2065 2066 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag, sc->xl_ldata.xl_rx_dmamap, 2067 BUS_DMASYNC_POSTREAD); 2068 while((rxstat = le32toh(sc->xl_cdata.xl_rx_head->xl_ptr->xl_status))) { 2069 cur_rx = sc->xl_cdata.xl_rx_head; 2070 sc->xl_cdata.xl_rx_head = cur_rx->xl_next; 2071 total_len = rxstat & XL_RXSTAT_LENMASK; 2072 2073 /* 2074 * Since we have told the chip to allow large frames, 2075 * we need to trap giant frame errors in software. We allow 2076 * a little more than the normal frame size to account for 2077 * frames with VLAN tags. 2078 */ 2079 if (total_len > XL_MAX_FRAMELEN) 2080 rxstat |= (XL_RXSTAT_UP_ERROR|XL_RXSTAT_OVERSIZE); 2081 2082 /* 2083 * If an error occurs, update stats, clear the 2084 * status word and leave the mbuf cluster in place: 2085 * it should simply get re-used next time this descriptor 2086 * comes up in the ring. 2087 */ 2088 if (rxstat & XL_RXSTAT_UP_ERROR) { 2089 ifp->if_ierrors++; 2090 cur_rx->xl_ptr->xl_status = 0; 2091 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag, 2092 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE); 2093 continue; 2094 } 2095 2096 /* 2097 * If the error bit was not set, the upload complete 2098 * bit should be set which means we have a valid packet. 2099 * If not, something truly strange has happened. 2100 */ 2101 if (!(rxstat & XL_RXSTAT_UP_CMPLT)) { 2102 printf("xl%d: bad receive status -- " 2103 "packet dropped\n", sc->xl_unit); 2104 ifp->if_ierrors++; 2105 cur_rx->xl_ptr->xl_status = 0; 2106 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag, 2107 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE); 2108 continue; 2109 } 2110 2111 /* No errors; receive the packet. */ 2112 bus_dmamap_sync(sc->xl_mtag, cur_rx->xl_map, 2113 BUS_DMASYNC_POSTREAD); 2114 m = cur_rx->xl_mbuf; 2115 2116 /* 2117 * Try to conjure up a new mbuf cluster. If that 2118 * fails, it means we have an out of memory condition and 2119 * should leave the buffer in place and continue. This will 2120 * result in a lost packet, but there's little else we 2121 * can do in this situation. 2122 */ 2123 if (xl_newbuf(sc, cur_rx)) { 2124 ifp->if_ierrors++; 2125 cur_rx->xl_ptr->xl_status = 0; 2126 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag, 2127 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE); 2128 continue; 2129 } 2130 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag, 2131 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE); 2132 2133 ifp->if_ipackets++; 2134 m->m_pkthdr.rcvif = ifp; 2135 m->m_pkthdr.len = m->m_len = total_len; 2136 2137 if (ifp->if_capenable & IFCAP_RXCSUM) { 2138 /* Do IP checksum checking. */ 2139 if (rxstat & XL_RXSTAT_IPCKOK) 2140 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 2141 if (!(rxstat & XL_RXSTAT_IPCKERR)) 2142 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 2143 if ((rxstat & XL_RXSTAT_TCPCOK && 2144 !(rxstat & XL_RXSTAT_TCPCKERR)) || 2145 (rxstat & XL_RXSTAT_UDPCKOK && 2146 !(rxstat & XL_RXSTAT_UDPCKERR))) { 2147 m->m_pkthdr.csum_flags |= 2148 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 2149 m->m_pkthdr.csum_data = 0xffff; 2150 } 2151 } 2152 2153 (*ifp->if_input)(ifp, m); 2154 } 2155 2156 /* 2157 * Handle the 'end of channel' condition. When the upload 2158 * engine hits the end of the RX ring, it will stall. This 2159 * is our cue to flush the RX ring, reload the uplist pointer 2160 * register and unstall the engine. 2161 * XXX This is actually a little goofy. With the ThunderLAN 2162 * chip, you get an interrupt when the receiver hits the end 2163 * of the receive ring, which tells you exactly when you 2164 * you need to reload the ring pointer. Here we have to 2165 * fake it. I'm mad at myself for not being clever enough 2166 * to avoid the use of a goto here. 2167 */ 2168 if (CSR_READ_4(sc, XL_UPLIST_PTR) == 0 || 2169 CSR_READ_4(sc, XL_UPLIST_STATUS) & XL_PKTSTAT_UP_STALLED) { 2170 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_STALL); 2171 xl_wait(sc); 2172 CSR_WRITE_4(sc, XL_UPLIST_PTR, sc->xl_ldata.xl_rx_dmaaddr); 2173 sc->xl_cdata.xl_rx_head = &sc->xl_cdata.xl_rx_chain[0]; 2174 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_UNSTALL); 2175 goto again; 2176 } 2177 2178 return; 2179 } 2180 2181 /* 2182 * A frame was downloaded to the chip. It's safe for us to clean up 2183 * the list buffers. 2184 */ 2185 static void 2186 xl_txeof(sc) 2187 struct xl_softc *sc; 2188 { 2189 struct xl_chain *cur_tx; 2190 struct ifnet *ifp; 2191 2192 ifp = &sc->arpcom.ac_if; 2193 2194 /* Clear the timeout timer. */ 2195 ifp->if_timer = 0; 2196 2197 /* 2198 * Go through our tx list and free mbufs for those 2199 * frames that have been uploaded. Note: the 3c905B 2200 * sets a special bit in the status word to let us 2201 * know that a frame has been downloaded, but the 2202 * original 3c900/3c905 adapters don't do that. 2203 * Consequently, we have to use a different test if 2204 * xl_type != XL_TYPE_905B. 2205 */ 2206 while(sc->xl_cdata.xl_tx_head != NULL) { 2207 cur_tx = sc->xl_cdata.xl_tx_head; 2208 2209 if (CSR_READ_4(sc, XL_DOWNLIST_PTR)) 2210 break; 2211 2212 sc->xl_cdata.xl_tx_head = cur_tx->xl_next; 2213 bus_dmamap_sync(sc->xl_mtag, cur_tx->xl_map, 2214 BUS_DMASYNC_POSTWRITE); 2215 bus_dmamap_unload(sc->xl_mtag, cur_tx->xl_map); 2216 m_freem(cur_tx->xl_mbuf); 2217 cur_tx->xl_mbuf = NULL; 2218 ifp->if_opackets++; 2219 2220 cur_tx->xl_next = sc->xl_cdata.xl_tx_free; 2221 sc->xl_cdata.xl_tx_free = cur_tx; 2222 } 2223 2224 if (sc->xl_cdata.xl_tx_head == NULL) { 2225 ifp->if_flags &= ~IFF_OACTIVE; 2226 sc->xl_cdata.xl_tx_tail = NULL; 2227 } else { 2228 if (CSR_READ_4(sc, XL_DMACTL) & XL_DMACTL_DOWN_STALLED || 2229 !CSR_READ_4(sc, XL_DOWNLIST_PTR)) { 2230 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, 2231 sc->xl_cdata.xl_tx_head->xl_phys); 2232 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); 2233 } 2234 } 2235 2236 return; 2237 } 2238 2239 static void 2240 xl_txeof_90xB(sc) 2241 struct xl_softc *sc; 2242 { 2243 struct xl_chain *cur_tx = NULL; 2244 struct ifnet *ifp; 2245 int idx; 2246 2247 ifp = &sc->arpcom.ac_if; 2248 2249 bus_dmamap_sync(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_dmamap, 2250 BUS_DMASYNC_POSTREAD); 2251 idx = sc->xl_cdata.xl_tx_cons; 2252 while(idx != sc->xl_cdata.xl_tx_prod) { 2253 2254 cur_tx = &sc->xl_cdata.xl_tx_chain[idx]; 2255 2256 if (!(le32toh(cur_tx->xl_ptr->xl_status) & 2257 XL_TXSTAT_DL_COMPLETE)) 2258 break; 2259 2260 if (cur_tx->xl_mbuf != NULL) { 2261 bus_dmamap_sync(sc->xl_mtag, cur_tx->xl_map, 2262 BUS_DMASYNC_POSTWRITE); 2263 bus_dmamap_unload(sc->xl_mtag, cur_tx->xl_map); 2264 m_freem(cur_tx->xl_mbuf); 2265 cur_tx->xl_mbuf = NULL; 2266 } 2267 2268 ifp->if_opackets++; 2269 2270 sc->xl_cdata.xl_tx_cnt--; 2271 XL_INC(idx, XL_TX_LIST_CNT); 2272 ifp->if_timer = 0; 2273 } 2274 2275 sc->xl_cdata.xl_tx_cons = idx; 2276 2277 if (cur_tx != NULL) 2278 ifp->if_flags &= ~IFF_OACTIVE; 2279 2280 return; 2281 } 2282 2283 /* 2284 * TX 'end of channel' interrupt handler. Actually, we should 2285 * only get a 'TX complete' interrupt if there's a transmit error, 2286 * so this is really TX error handler. 2287 */ 2288 static void 2289 xl_txeoc(sc) 2290 struct xl_softc *sc; 2291 { 2292 u_int8_t txstat; 2293 2294 while((txstat = CSR_READ_1(sc, XL_TX_STATUS))) { 2295 if (txstat & XL_TXSTATUS_UNDERRUN || 2296 txstat & XL_TXSTATUS_JABBER || 2297 txstat & XL_TXSTATUS_RECLAIM) { 2298 printf("xl%d: transmission error: %x\n", 2299 sc->xl_unit, txstat); 2300 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); 2301 xl_wait(sc); 2302 if (sc->xl_type == XL_TYPE_905B) { 2303 if (sc->xl_cdata.xl_tx_cnt) { 2304 int i; 2305 struct xl_chain *c; 2306 i = sc->xl_cdata.xl_tx_cons; 2307 c = &sc->xl_cdata.xl_tx_chain[i]; 2308 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, 2309 c->xl_phys); 2310 CSR_WRITE_1(sc, XL_DOWN_POLL, 64); 2311 } 2312 } else { 2313 if (sc->xl_cdata.xl_tx_head != NULL) 2314 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, 2315 sc->xl_cdata.xl_tx_head->xl_phys); 2316 } 2317 /* 2318 * Remember to set this for the 2319 * first generation 3c90X chips. 2320 */ 2321 CSR_WRITE_1(sc, XL_TX_FREETHRESH, XL_PACKET_SIZE >> 8); 2322 if (txstat & XL_TXSTATUS_UNDERRUN && 2323 sc->xl_tx_thresh < XL_PACKET_SIZE) { 2324 sc->xl_tx_thresh += XL_MIN_FRAMELEN; 2325 printf("xl%d: tx underrun, increasing tx start" 2326 " threshold to %d bytes\n", sc->xl_unit, 2327 sc->xl_tx_thresh); 2328 } 2329 CSR_WRITE_2(sc, XL_COMMAND, 2330 XL_CMD_TX_SET_START|sc->xl_tx_thresh); 2331 if (sc->xl_type == XL_TYPE_905B) { 2332 CSR_WRITE_2(sc, XL_COMMAND, 2333 XL_CMD_SET_TX_RECLAIM|(XL_PACKET_SIZE >> 4)); 2334 } 2335 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE); 2336 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); 2337 } else { 2338 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE); 2339 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); 2340 } 2341 /* 2342 * Write an arbitrary byte to the TX_STATUS register 2343 * to clear this interrupt/error and advance to the next. 2344 */ 2345 CSR_WRITE_1(sc, XL_TX_STATUS, 0x01); 2346 } 2347 2348 return; 2349 } 2350 2351 static void 2352 xl_intr(arg) 2353 void *arg; 2354 { 2355 struct xl_softc *sc; 2356 struct ifnet *ifp; 2357 u_int16_t status; 2358 2359 sc = arg; 2360 ifp = &sc->arpcom.ac_if; 2361 2362 while((status = CSR_READ_2(sc, XL_STATUS)) & XL_INTRS && status != 0xFFFF) { 2363 2364 CSR_WRITE_2(sc, XL_COMMAND, 2365 XL_CMD_INTR_ACK|(status & XL_INTRS)); 2366 2367 if (status & XL_STAT_UP_COMPLETE) { 2368 int curpkts; 2369 2370 curpkts = ifp->if_ipackets; 2371 xl_rxeof(sc); 2372 if (curpkts == ifp->if_ipackets) { 2373 while (xl_rx_resync(sc)) 2374 xl_rxeof(sc); 2375 } 2376 } 2377 2378 if (status & XL_STAT_DOWN_COMPLETE) { 2379 if (sc->xl_type == XL_TYPE_905B) 2380 xl_txeof_90xB(sc); 2381 else 2382 xl_txeof(sc); 2383 } 2384 2385 if (status & XL_STAT_TX_COMPLETE) { 2386 ifp->if_oerrors++; 2387 xl_txeoc(sc); 2388 } 2389 2390 if (status & XL_STAT_ADFAIL) { 2391 xl_reset(sc); 2392 xl_init(sc); 2393 } 2394 2395 if (status & XL_STAT_STATSOFLOW) { 2396 sc->xl_stats_no_timeout = 1; 2397 xl_stats_update(sc); 2398 sc->xl_stats_no_timeout = 0; 2399 } 2400 } 2401 2402 if (ifp->if_snd.ifq_head != NULL) 2403 (*ifp->if_start)(ifp); 2404 2405 return; 2406 } 2407 2408 static void 2409 xl_stats_update(xsc) 2410 void *xsc; 2411 { 2412 struct xl_softc *sc; 2413 struct ifnet *ifp; 2414 struct xl_stats xl_stats; 2415 u_int8_t *p; 2416 int i; 2417 struct mii_data *mii = NULL; 2418 2419 bzero((char *)&xl_stats, sizeof(struct xl_stats)); 2420 2421 sc = xsc; 2422 ifp = &sc->arpcom.ac_if; 2423 if (sc->xl_miibus != NULL) 2424 mii = device_get_softc(sc->xl_miibus); 2425 2426 p = (u_int8_t *)&xl_stats; 2427 2428 /* Read all the stats registers. */ 2429 XL_SEL_WIN(6); 2430 2431 for (i = 0; i < 16; i++) 2432 *p++ = CSR_READ_1(sc, XL_W6_CARRIER_LOST + i); 2433 2434 ifp->if_ierrors += xl_stats.xl_rx_overrun; 2435 2436 ifp->if_collisions += xl_stats.xl_tx_multi_collision + 2437 xl_stats.xl_tx_single_collision + 2438 xl_stats.xl_tx_late_collision; 2439 2440 /* 2441 * Boomerang and cyclone chips have an extra stats counter 2442 * in window 4 (BadSSD). We have to read this too in order 2443 * to clear out all the stats registers and avoid a statsoflow 2444 * interrupt. 2445 */ 2446 XL_SEL_WIN(4); 2447 CSR_READ_1(sc, XL_W4_BADSSD); 2448 2449 if ((mii != NULL) && (!sc->xl_stats_no_timeout)) 2450 mii_tick(mii); 2451 2452 XL_SEL_WIN(7); 2453 2454 if (!sc->xl_stats_no_timeout) 2455 callout_reset(&sc->xl_stat_timer, hz, xl_stats_update, sc); 2456 2457 return; 2458 } 2459 2460 /* 2461 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 2462 * pointers to the fragment pointers. 2463 */ 2464 static int 2465 xl_encap(sc, c, m_head) 2466 struct xl_softc *sc; 2467 struct xl_chain *c; 2468 struct mbuf *m_head; 2469 { 2470 int error; 2471 u_int32_t status; 2472 struct ifnet *ifp; 2473 2474 ifp = &sc->arpcom.ac_if; 2475 2476 /* 2477 * Start packing the mbufs in this chain into 2478 * the fragment pointers. Stop when we run out 2479 * of fragments or hit the end of the mbuf chain. 2480 */ 2481 error = bus_dmamap_load_mbuf(sc->xl_mtag, c->xl_map, m_head, 2482 xl_dma_map_txbuf, c->xl_ptr, BUS_DMA_NOWAIT); 2483 2484 if (error && error != EFBIG) { 2485 m_freem(m_head); 2486 printf("xl%d: can't map mbuf (error %d)\n", sc->xl_unit, error); 2487 return(1); 2488 } 2489 2490 /* 2491 * Handle special case: we used up all 63 fragments, 2492 * but we have more mbufs left in the chain. Copy the 2493 * data into an mbuf cluster. Note that we don't 2494 * bother clearing the values in the other fragment 2495 * pointers/counters; it wouldn't gain us anything, 2496 * and would waste cycles. 2497 */ 2498 if (error) { 2499 struct mbuf *m_new; 2500 2501 m_new = m_defrag(m_head, MB_DONTWAIT); 2502 if (m_new == NULL) { 2503 m_freem(m_head); 2504 return(1); 2505 } else { 2506 m_head = m_new; 2507 } 2508 2509 error = bus_dmamap_load_mbuf(sc->xl_mtag, c->xl_map, 2510 m_head, xl_dma_map_txbuf, c->xl_ptr, BUS_DMA_NOWAIT); 2511 if (error) { 2512 m_freem(m_head); 2513 printf("xl%d: can't map mbuf (error %d)\n", 2514 sc->xl_unit, error); 2515 return(1); 2516 } 2517 } 2518 2519 if (sc->xl_type == XL_TYPE_905B) { 2520 status = XL_TXSTAT_RND_DEFEAT; 2521 2522 if (m_head->m_pkthdr.csum_flags) { 2523 if (m_head->m_pkthdr.csum_flags & CSUM_IP) 2524 status |= XL_TXSTAT_IPCKSUM; 2525 if (m_head->m_pkthdr.csum_flags & CSUM_TCP) 2526 status |= XL_TXSTAT_TCPCKSUM; 2527 if (m_head->m_pkthdr.csum_flags & CSUM_UDP) 2528 status |= XL_TXSTAT_UDPCKSUM; 2529 } 2530 c->xl_ptr->xl_status = htole32(status); 2531 } 2532 2533 c->xl_mbuf = m_head; 2534 bus_dmamap_sync(sc->xl_mtag, c->xl_map, BUS_DMASYNC_PREWRITE); 2535 return(0); 2536 } 2537 2538 /* 2539 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 2540 * to the mbuf data regions directly in the transmit lists. We also save a 2541 * copy of the pointers since the transmit list fragment pointers are 2542 * physical addresses. 2543 */ 2544 static void 2545 xl_start(ifp) 2546 struct ifnet *ifp; 2547 { 2548 struct xl_softc *sc; 2549 struct mbuf *m_head = NULL; 2550 struct xl_chain *prev = NULL, *cur_tx = NULL, *start_tx; 2551 struct xl_chain *prev_tx; 2552 u_int32_t status; 2553 int error; 2554 2555 sc = ifp->if_softc; 2556 /* 2557 * Check for an available queue slot. If there are none, 2558 * punt. 2559 */ 2560 if (sc->xl_cdata.xl_tx_free == NULL) { 2561 xl_txeoc(sc); 2562 xl_txeof(sc); 2563 if (sc->xl_cdata.xl_tx_free == NULL) { 2564 ifp->if_flags |= IFF_OACTIVE; 2565 return; 2566 } 2567 } 2568 2569 start_tx = sc->xl_cdata.xl_tx_free; 2570 2571 while(sc->xl_cdata.xl_tx_free != NULL) { 2572 IF_DEQUEUE(&ifp->if_snd, m_head); 2573 if (m_head == NULL) 2574 break; 2575 2576 /* Pick a descriptor off the free list. */ 2577 prev_tx = cur_tx; 2578 cur_tx = sc->xl_cdata.xl_tx_free; 2579 2580 /* Pack the data into the descriptor. */ 2581 error = xl_encap(sc, cur_tx, m_head); 2582 if (error) { 2583 cur_tx = prev_tx; 2584 continue; 2585 } 2586 2587 sc->xl_cdata.xl_tx_free = cur_tx->xl_next; 2588 cur_tx->xl_next = NULL; 2589 2590 /* Chain it together. */ 2591 if (prev != NULL) { 2592 prev->xl_next = cur_tx; 2593 prev->xl_ptr->xl_next = htole32(cur_tx->xl_phys); 2594 } 2595 prev = cur_tx; 2596 2597 /* 2598 * If there's a BPF listener, bounce a copy of this frame 2599 * to him. 2600 */ 2601 if (ifp->if_bpf) 2602 bpf_mtap(ifp, cur_tx->xl_mbuf); 2603 } 2604 2605 /* 2606 * If there are no packets queued, bail. 2607 */ 2608 if (cur_tx == NULL) { 2609 return; 2610 } 2611 2612 /* 2613 * Place the request for the upload interrupt 2614 * in the last descriptor in the chain. This way, if 2615 * we're chaining several packets at once, we'll only 2616 * get an interupt once for the whole chain rather than 2617 * once for each packet. 2618 */ 2619 cur_tx->xl_ptr->xl_status = htole32(le32toh(cur_tx->xl_ptr->xl_status) | 2620 XL_TXSTAT_DL_INTR); 2621 bus_dmamap_sync(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_dmamap, 2622 BUS_DMASYNC_PREWRITE); 2623 2624 /* 2625 * Queue the packets. If the TX channel is clear, update 2626 * the downlist pointer register. 2627 */ 2628 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_STALL); 2629 xl_wait(sc); 2630 2631 if (sc->xl_cdata.xl_tx_head != NULL) { 2632 sc->xl_cdata.xl_tx_tail->xl_next = start_tx; 2633 sc->xl_cdata.xl_tx_tail->xl_ptr->xl_next = 2634 htole32(start_tx->xl_phys); 2635 status = sc->xl_cdata.xl_tx_tail->xl_ptr->xl_status; 2636 sc->xl_cdata.xl_tx_tail->xl_ptr->xl_status = 2637 htole32(le32toh(status) & ~XL_TXSTAT_DL_INTR); 2638 sc->xl_cdata.xl_tx_tail = cur_tx; 2639 } else { 2640 sc->xl_cdata.xl_tx_head = start_tx; 2641 sc->xl_cdata.xl_tx_tail = cur_tx; 2642 } 2643 if (!CSR_READ_4(sc, XL_DOWNLIST_PTR)) 2644 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, start_tx->xl_phys); 2645 2646 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); 2647 2648 XL_SEL_WIN(7); 2649 2650 /* 2651 * Set a timeout in case the chip goes out to lunch. 2652 */ 2653 ifp->if_timer = 5; 2654 2655 /* 2656 * XXX Under certain conditions, usually on slower machines 2657 * where interrupts may be dropped, it's possible for the 2658 * adapter to chew up all the buffers in the receive ring 2659 * and stall, without us being able to do anything about it. 2660 * To guard against this, we need to make a pass over the 2661 * RX queue to make sure there aren't any packets pending. 2662 * Doing it here means we can flush the receive ring at the 2663 * same time the chip is DMAing the transmit descriptors we 2664 * just gave it. 2665 * 2666 * 3Com goes to some lengths to emphasize the Parallel Tasking (tm) 2667 * nature of their chips in all their marketing literature; 2668 * we may as well take advantage of it. :) 2669 */ 2670 xl_rxeof(sc); 2671 2672 return; 2673 } 2674 2675 static void 2676 xl_start_90xB(ifp) 2677 struct ifnet *ifp; 2678 { 2679 struct xl_softc *sc; 2680 struct mbuf *m_head = NULL; 2681 struct xl_chain *prev = NULL, *cur_tx = NULL, *start_tx; 2682 struct xl_chain *prev_tx; 2683 int error, idx; 2684 2685 sc = ifp->if_softc; 2686 2687 if (ifp->if_flags & IFF_OACTIVE) { 2688 return; 2689 } 2690 2691 idx = sc->xl_cdata.xl_tx_prod; 2692 start_tx = &sc->xl_cdata.xl_tx_chain[idx]; 2693 2694 while (sc->xl_cdata.xl_tx_chain[idx].xl_mbuf == NULL) { 2695 2696 if ((XL_TX_LIST_CNT - sc->xl_cdata.xl_tx_cnt) < 3) { 2697 ifp->if_flags |= IFF_OACTIVE; 2698 break; 2699 } 2700 2701 IF_DEQUEUE(&ifp->if_snd, m_head); 2702 if (m_head == NULL) 2703 break; 2704 2705 prev_tx = cur_tx; 2706 cur_tx = &sc->xl_cdata.xl_tx_chain[idx]; 2707 2708 /* Pack the data into the descriptor. */ 2709 error = xl_encap(sc, cur_tx, m_head); 2710 if (error) { 2711 cur_tx = prev_tx; 2712 continue; 2713 } 2714 2715 /* Chain it together. */ 2716 if (prev != NULL) 2717 prev->xl_ptr->xl_next = htole32(cur_tx->xl_phys); 2718 prev = cur_tx; 2719 2720 /* 2721 * If there's a BPF listener, bounce a copy of this frame 2722 * to him. 2723 */ 2724 if (ifp->if_bpf) 2725 bpf_mtap(ifp, cur_tx->xl_mbuf); 2726 2727 XL_INC(idx, XL_TX_LIST_CNT); 2728 sc->xl_cdata.xl_tx_cnt++; 2729 } 2730 2731 /* 2732 * If there are no packets queued, bail. 2733 */ 2734 if (cur_tx == NULL) { 2735 return; 2736 } 2737 2738 /* 2739 * Place the request for the upload interrupt 2740 * in the last descriptor in the chain. This way, if 2741 * we're chaining several packets at once, we'll only 2742 * get an interupt once for the whole chain rather than 2743 * once for each packet. 2744 */ 2745 cur_tx->xl_ptr->xl_status = htole32(le32toh(cur_tx->xl_ptr->xl_status) | 2746 XL_TXSTAT_DL_INTR); 2747 bus_dmamap_sync(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_dmamap, 2748 BUS_DMASYNC_PREWRITE); 2749 2750 /* Start transmission */ 2751 sc->xl_cdata.xl_tx_prod = idx; 2752 start_tx->xl_prev->xl_ptr->xl_next = htole32(start_tx->xl_phys); 2753 2754 /* 2755 * Set a timeout in case the chip goes out to lunch. 2756 */ 2757 ifp->if_timer = 5; 2758 2759 return; 2760 } 2761 2762 static void 2763 xl_init(xsc) 2764 void *xsc; 2765 { 2766 struct xl_softc *sc = xsc; 2767 struct ifnet *ifp = &sc->arpcom.ac_if; 2768 int error, i; 2769 u_int16_t rxfilt = 0; 2770 struct mii_data *mii = NULL; 2771 int s; 2772 2773 s = splimp(); 2774 2775 /* 2776 * Cancel pending I/O and free all RX/TX buffers. 2777 */ 2778 xl_stop(sc); 2779 2780 if (sc->xl_miibus == NULL) { 2781 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET); 2782 xl_wait(sc); 2783 } 2784 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); 2785 xl_wait(sc); 2786 DELAY(10000); 2787 2788 if (sc->xl_miibus != NULL) 2789 mii = device_get_softc(sc->xl_miibus); 2790 2791 /* Init our MAC address */ 2792 XL_SEL_WIN(2); 2793 for (i = 0; i < ETHER_ADDR_LEN; i++) { 2794 CSR_WRITE_1(sc, XL_W2_STATION_ADDR_LO + i, 2795 sc->arpcom.ac_enaddr[i]); 2796 } 2797 2798 /* Clear the station mask. */ 2799 for (i = 0; i < 3; i++) 2800 CSR_WRITE_2(sc, XL_W2_STATION_MASK_LO + (i * 2), 0); 2801 #ifdef notdef 2802 /* Reset TX and RX. */ 2803 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET); 2804 xl_wait(sc); 2805 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); 2806 xl_wait(sc); 2807 #endif 2808 /* Init circular RX list. */ 2809 error = xl_list_rx_init(sc); 2810 if (error) { 2811 printf("xl%d: initialization of the rx ring failed (%d)\n", 2812 sc->xl_unit, error); 2813 xl_stop(sc); 2814 splx(s); 2815 return; 2816 } 2817 2818 /* Init TX descriptors. */ 2819 if (sc->xl_type == XL_TYPE_905B) 2820 error = xl_list_tx_init_90xB(sc); 2821 else 2822 error = xl_list_tx_init(sc); 2823 if (error) { 2824 printf("xl%d: initialization of the tx ring failed (%d)\n", 2825 sc->xl_unit, error); 2826 xl_stop(sc); 2827 splx(s); 2828 } 2829 2830 /* 2831 * Set the TX freethresh value. 2832 * Note that this has no effect on 3c905B "cyclone" 2833 * cards but is required for 3c900/3c905 "boomerang" 2834 * cards in order to enable the download engine. 2835 */ 2836 CSR_WRITE_1(sc, XL_TX_FREETHRESH, XL_PACKET_SIZE >> 8); 2837 2838 /* Set the TX start threshold for best performance. */ 2839 sc->xl_tx_thresh = XL_MIN_FRAMELEN; 2840 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_SET_START|sc->xl_tx_thresh); 2841 2842 /* 2843 * If this is a 3c905B, also set the tx reclaim threshold. 2844 * This helps cut down on the number of tx reclaim errors 2845 * that could happen on a busy network. The chip multiplies 2846 * the register value by 16 to obtain the actual threshold 2847 * in bytes, so we divide by 16 when setting the value here. 2848 * The existing threshold value can be examined by reading 2849 * the register at offset 9 in window 5. 2850 */ 2851 if (sc->xl_type == XL_TYPE_905B) { 2852 CSR_WRITE_2(sc, XL_COMMAND, 2853 XL_CMD_SET_TX_RECLAIM|(XL_PACKET_SIZE >> 4)); 2854 } 2855 2856 /* Set RX filter bits. */ 2857 XL_SEL_WIN(5); 2858 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER); 2859 2860 /* Set the individual bit to receive frames for this host only. */ 2861 rxfilt |= XL_RXFILTER_INDIVIDUAL; 2862 2863 /* If we want promiscuous mode, set the allframes bit. */ 2864 if (ifp->if_flags & IFF_PROMISC) { 2865 rxfilt |= XL_RXFILTER_ALLFRAMES; 2866 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 2867 } else { 2868 rxfilt &= ~XL_RXFILTER_ALLFRAMES; 2869 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 2870 } 2871 2872 /* 2873 * Set capture broadcast bit to capture broadcast frames. 2874 */ 2875 if (ifp->if_flags & IFF_BROADCAST) { 2876 rxfilt |= XL_RXFILTER_BROADCAST; 2877 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 2878 } else { 2879 rxfilt &= ~XL_RXFILTER_BROADCAST; 2880 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 2881 } 2882 2883 /* 2884 * Program the multicast filter, if necessary. 2885 */ 2886 if (sc->xl_type == XL_TYPE_905B) 2887 xl_setmulti_hash(sc); 2888 else 2889 xl_setmulti(sc); 2890 2891 /* 2892 * Load the address of the RX list. We have to 2893 * stall the upload engine before we can manipulate 2894 * the uplist pointer register, then unstall it when 2895 * we're finished. We also have to wait for the 2896 * stall command to complete before proceeding. 2897 * Note that we have to do this after any RX resets 2898 * have completed since the uplist register is cleared 2899 * by a reset. 2900 */ 2901 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_STALL); 2902 xl_wait(sc); 2903 CSR_WRITE_4(sc, XL_UPLIST_PTR, sc->xl_ldata.xl_rx_dmaaddr); 2904 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_UNSTALL); 2905 xl_wait(sc); 2906 2907 2908 if (sc->xl_type == XL_TYPE_905B) { 2909 /* Set polling interval */ 2910 CSR_WRITE_1(sc, XL_DOWN_POLL, 64); 2911 /* Load the address of the TX list */ 2912 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_STALL); 2913 xl_wait(sc); 2914 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, 2915 sc->xl_cdata.xl_tx_chain[0].xl_phys); 2916 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); 2917 xl_wait(sc); 2918 } 2919 2920 /* 2921 * If the coax transceiver is on, make sure to enable 2922 * the DC-DC converter. 2923 */ 2924 XL_SEL_WIN(3); 2925 if (sc->xl_xcvr == XL_XCVR_COAX) 2926 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_START); 2927 else 2928 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP); 2929 2930 /* 2931 * increase packet size to allow reception of 802.1q or ISL packets. 2932 * For the 3c90x chip, set the 'allow large packets' bit in the MAC 2933 * control register. For 3c90xB/C chips, use the RX packet size 2934 * register. 2935 */ 2936 2937 if (sc->xl_type == XL_TYPE_905B) 2938 CSR_WRITE_2(sc, XL_W3_MAXPKTSIZE, XL_PACKET_SIZE); 2939 else { 2940 u_int8_t macctl; 2941 macctl = CSR_READ_1(sc, XL_W3_MAC_CTRL); 2942 macctl |= XL_MACCTRL_ALLOW_LARGE_PACK; 2943 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, macctl); 2944 } 2945 2946 /* Clear out the stats counters. */ 2947 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_DISABLE); 2948 sc->xl_stats_no_timeout = 1; 2949 xl_stats_update(sc); 2950 sc->xl_stats_no_timeout = 0; 2951 XL_SEL_WIN(4); 2952 CSR_WRITE_2(sc, XL_W4_NET_DIAG, XL_NETDIAG_UPPER_BYTES_ENABLE); 2953 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_ENABLE); 2954 2955 /* 2956 * Enable interrupts. 2957 */ 2958 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ACK|0xFF); 2959 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STAT_ENB|XL_INTRS); 2960 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|XL_INTRS); 2961 if (sc->xl_flags & XL_FLAG_FUNCREG) 2962 bus_space_write_4(sc->xl_ftag, sc->xl_fhandle, 4, 0x8000); 2963 2964 /* Set the RX early threshold */ 2965 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_THRESH|(XL_PACKET_SIZE >>2)); 2966 CSR_WRITE_2(sc, XL_DMACTL, XL_DMACTL_UP_RX_EARLY); 2967 2968 /* Enable receiver and transmitter. */ 2969 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE); 2970 xl_wait(sc); 2971 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_ENABLE); 2972 xl_wait(sc); 2973 2974 if (mii != NULL) 2975 mii_mediachg(mii); 2976 2977 /* Select window 7 for normal operations. */ 2978 XL_SEL_WIN(7); 2979 2980 ifp->if_flags |= IFF_RUNNING; 2981 ifp->if_flags &= ~IFF_OACTIVE; 2982 2983 callout_reset(&sc->xl_stat_timer, hz, xl_stats_update, sc); 2984 2985 splx(s); 2986 2987 return; 2988 } 2989 2990 /* 2991 * Set media options. 2992 */ 2993 static int 2994 xl_ifmedia_upd(ifp) 2995 struct ifnet *ifp; 2996 { 2997 struct xl_softc *sc; 2998 struct ifmedia *ifm = NULL; 2999 struct mii_data *mii = NULL; 3000 3001 sc = ifp->if_softc; 3002 if (sc->xl_miibus != NULL) 3003 mii = device_get_softc(sc->xl_miibus); 3004 if (mii == NULL) 3005 ifm = &sc->ifmedia; 3006 else 3007 ifm = &mii->mii_media; 3008 3009 switch(IFM_SUBTYPE(ifm->ifm_media)) { 3010 case IFM_100_FX: 3011 case IFM_10_FL: 3012 case IFM_10_2: 3013 case IFM_10_5: 3014 xl_setmode(sc, ifm->ifm_media); 3015 return(0); 3016 break; 3017 default: 3018 break; 3019 } 3020 3021 if (sc->xl_media & XL_MEDIAOPT_MII || sc->xl_media & XL_MEDIAOPT_BTX 3022 || sc->xl_media & XL_MEDIAOPT_BT4) { 3023 xl_init(sc); 3024 } else { 3025 xl_setmode(sc, ifm->ifm_media); 3026 } 3027 3028 return(0); 3029 } 3030 3031 /* 3032 * Report current media status. 3033 */ 3034 static void 3035 xl_ifmedia_sts(ifp, ifmr) 3036 struct ifnet *ifp; 3037 struct ifmediareq *ifmr; 3038 { 3039 struct xl_softc *sc; 3040 u_int32_t icfg; 3041 struct mii_data *mii = NULL; 3042 3043 sc = ifp->if_softc; 3044 if (sc->xl_miibus != NULL) 3045 mii = device_get_softc(sc->xl_miibus); 3046 3047 XL_SEL_WIN(3); 3048 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG) & XL_ICFG_CONNECTOR_MASK; 3049 icfg >>= XL_ICFG_CONNECTOR_BITS; 3050 3051 ifmr->ifm_active = IFM_ETHER; 3052 3053 switch(icfg) { 3054 case XL_XCVR_10BT: 3055 ifmr->ifm_active = IFM_ETHER|IFM_10_T; 3056 if (CSR_READ_1(sc, XL_W3_MAC_CTRL) & XL_MACCTRL_DUPLEX) 3057 ifmr->ifm_active |= IFM_FDX; 3058 else 3059 ifmr->ifm_active |= IFM_HDX; 3060 break; 3061 case XL_XCVR_AUI: 3062 if (sc->xl_type == XL_TYPE_905B && 3063 sc->xl_media == XL_MEDIAOPT_10FL) { 3064 ifmr->ifm_active = IFM_ETHER|IFM_10_FL; 3065 if (CSR_READ_1(sc, XL_W3_MAC_CTRL) & XL_MACCTRL_DUPLEX) 3066 ifmr->ifm_active |= IFM_FDX; 3067 else 3068 ifmr->ifm_active |= IFM_HDX; 3069 } else 3070 ifmr->ifm_active = IFM_ETHER|IFM_10_5; 3071 break; 3072 case XL_XCVR_COAX: 3073 ifmr->ifm_active = IFM_ETHER|IFM_10_2; 3074 break; 3075 /* 3076 * XXX MII and BTX/AUTO should be separate cases. 3077 */ 3078 3079 case XL_XCVR_100BTX: 3080 case XL_XCVR_AUTO: 3081 case XL_XCVR_MII: 3082 if (mii != NULL) { 3083 mii_pollstat(mii); 3084 ifmr->ifm_active = mii->mii_media_active; 3085 ifmr->ifm_status = mii->mii_media_status; 3086 } 3087 break; 3088 case XL_XCVR_100BFX: 3089 ifmr->ifm_active = IFM_ETHER|IFM_100_FX; 3090 break; 3091 default: 3092 printf("xl%d: unknown XCVR type: %d\n", sc->xl_unit, icfg); 3093 break; 3094 } 3095 3096 return; 3097 } 3098 3099 static int 3100 xl_ioctl(ifp, command, data, cr) 3101 struct ifnet *ifp; 3102 u_long command; 3103 caddr_t data; 3104 struct ucred *cr; 3105 { 3106 struct xl_softc *sc = ifp->if_softc; 3107 struct ifreq *ifr = (struct ifreq *) data; 3108 int error = 0; 3109 struct mii_data *mii = NULL; 3110 u_int8_t rxfilt; 3111 int s; 3112 3113 s = splimp(); 3114 3115 switch(command) { 3116 case SIOCSIFADDR: 3117 case SIOCGIFADDR: 3118 case SIOCSIFMTU: 3119 error = ether_ioctl(ifp, command, data); 3120 break; 3121 case SIOCSIFFLAGS: 3122 XL_SEL_WIN(5); 3123 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER); 3124 if (ifp->if_flags & IFF_UP) { 3125 if (ifp->if_flags & IFF_RUNNING && 3126 ifp->if_flags & IFF_PROMISC && 3127 !(sc->xl_if_flags & IFF_PROMISC)) { 3128 rxfilt |= XL_RXFILTER_ALLFRAMES; 3129 CSR_WRITE_2(sc, XL_COMMAND, 3130 XL_CMD_RX_SET_FILT|rxfilt); 3131 XL_SEL_WIN(7); 3132 } else if (ifp->if_flags & IFF_RUNNING && 3133 !(ifp->if_flags & IFF_PROMISC) && 3134 sc->xl_if_flags & IFF_PROMISC) { 3135 rxfilt &= ~XL_RXFILTER_ALLFRAMES; 3136 CSR_WRITE_2(sc, XL_COMMAND, 3137 XL_CMD_RX_SET_FILT|rxfilt); 3138 XL_SEL_WIN(7); 3139 } else 3140 xl_init(sc); 3141 } else { 3142 if (ifp->if_flags & IFF_RUNNING) 3143 xl_stop(sc); 3144 } 3145 sc->xl_if_flags = ifp->if_flags; 3146 error = 0; 3147 break; 3148 case SIOCADDMULTI: 3149 case SIOCDELMULTI: 3150 if (sc->xl_type == XL_TYPE_905B) 3151 xl_setmulti_hash(sc); 3152 else 3153 xl_setmulti(sc); 3154 error = 0; 3155 break; 3156 case SIOCGIFMEDIA: 3157 case SIOCSIFMEDIA: 3158 if (sc->xl_miibus != NULL) 3159 mii = device_get_softc(sc->xl_miibus); 3160 if (mii == NULL) 3161 error = ifmedia_ioctl(ifp, ifr, 3162 &sc->ifmedia, command); 3163 else 3164 error = ifmedia_ioctl(ifp, ifr, 3165 &mii->mii_media, command); 3166 break; 3167 case SIOCSIFCAP: 3168 ifp->if_capenable = ifr->ifr_reqcap; 3169 if (ifp->if_capenable & IFCAP_TXCSUM) 3170 ifp->if_hwassist = XL905B_CSUM_FEATURES; 3171 else 3172 ifp->if_hwassist = 0; 3173 break; 3174 default: 3175 error = EINVAL; 3176 break; 3177 } 3178 3179 splx(s); 3180 return(error); 3181 } 3182 3183 static void 3184 xl_watchdog(ifp) 3185 struct ifnet *ifp; 3186 { 3187 struct xl_softc *sc; 3188 u_int16_t status = 0; 3189 3190 sc = ifp->if_softc; 3191 3192 ifp->if_oerrors++; 3193 XL_SEL_WIN(4); 3194 status = CSR_READ_2(sc, XL_W4_MEDIA_STATUS); 3195 printf("xl%d: watchdog timeout\n", sc->xl_unit); 3196 3197 if (status & XL_MEDIASTAT_CARRIER) 3198 printf("xl%d: no carrier - transceiver cable problem?\n", 3199 sc->xl_unit); 3200 xl_txeoc(sc); 3201 xl_txeof(sc); 3202 xl_rxeof(sc); 3203 xl_reset(sc); 3204 xl_init(sc); 3205 3206 if (ifp->if_snd.ifq_head != NULL) 3207 (*ifp->if_start)(ifp); 3208 3209 return; 3210 } 3211 3212 /* 3213 * Stop the adapter and free any mbufs allocated to the 3214 * RX and TX lists. 3215 */ 3216 static void 3217 xl_stop(sc) 3218 struct xl_softc *sc; 3219 { 3220 int i; 3221 struct ifnet *ifp; 3222 3223 ifp = &sc->arpcom.ac_if; 3224 ifp->if_timer = 0; 3225 3226 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_DISABLE); 3227 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_DISABLE); 3228 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB); 3229 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_DISCARD); 3230 xl_wait(sc); 3231 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_DISABLE); 3232 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP); 3233 DELAY(800); 3234 3235 #ifdef foo 3236 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET); 3237 xl_wait(sc); 3238 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); 3239 xl_wait(sc); 3240 #endif 3241 3242 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ACK|XL_STAT_INTLATCH); 3243 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STAT_ENB|0); 3244 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|0); 3245 if (sc->xl_flags & XL_FLAG_FUNCREG) bus_space_write_4 (sc->xl_ftag, sc->xl_fhandle, 4, 0x8000); 3246 3247 /* Stop the stats updater. */ 3248 callout_stop(&sc->xl_stat_timer); 3249 3250 /* 3251 * Free data in the RX lists. 3252 */ 3253 for (i = 0; i < XL_RX_LIST_CNT; i++) { 3254 if (sc->xl_cdata.xl_rx_chain[i].xl_mbuf != NULL) { 3255 bus_dmamap_unload(sc->xl_mtag, 3256 sc->xl_cdata.xl_rx_chain[i].xl_map); 3257 bus_dmamap_destroy(sc->xl_mtag, 3258 sc->xl_cdata.xl_rx_chain[i].xl_map); 3259 m_freem(sc->xl_cdata.xl_rx_chain[i].xl_mbuf); 3260 sc->xl_cdata.xl_rx_chain[i].xl_mbuf = NULL; 3261 } 3262 } 3263 bzero(sc->xl_ldata.xl_rx_list, XL_RX_LIST_SZ); 3264 /* 3265 * Free the TX list buffers. 3266 */ 3267 for (i = 0; i < XL_TX_LIST_CNT; i++) { 3268 if (sc->xl_cdata.xl_tx_chain[i].xl_mbuf != NULL) { 3269 bus_dmamap_unload(sc->xl_mtag, 3270 sc->xl_cdata.xl_tx_chain[i].xl_map); 3271 bus_dmamap_destroy(sc->xl_mtag, 3272 sc->xl_cdata.xl_tx_chain[i].xl_map); 3273 m_freem(sc->xl_cdata.xl_tx_chain[i].xl_mbuf); 3274 sc->xl_cdata.xl_tx_chain[i].xl_mbuf = NULL; 3275 } 3276 } 3277 bzero(sc->xl_ldata.xl_tx_list, XL_TX_LIST_SZ); 3278 3279 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 3280 3281 return; 3282 } 3283 3284 /* 3285 * Stop all chip I/O so that the kernel's probe routines don't 3286 * get confused by errant DMAs when rebooting. 3287 */ 3288 static void 3289 xl_shutdown(dev) 3290 device_t dev; 3291 { 3292 struct xl_softc *sc; 3293 3294 sc = device_get_softc(dev); 3295 3296 xl_reset(sc); 3297 xl_stop(sc); 3298 3299 return; 3300 } 3301 3302 static int 3303 xl_suspend(dev) 3304 device_t dev; 3305 { 3306 struct xl_softc *sc; 3307 int s; 3308 3309 s = splimp(); 3310 3311 sc = device_get_softc(dev); 3312 3313 xl_stop(sc); 3314 3315 splx(s); 3316 3317 return(0); 3318 } 3319 3320 static int 3321 xl_resume(dev) 3322 device_t dev; 3323 { 3324 struct xl_softc *sc; 3325 struct ifnet *ifp; 3326 int s; 3327 3328 s = splimp(); 3329 3330 sc = device_get_softc(dev); 3331 ifp = &sc->arpcom.ac_if; 3332 3333 xl_reset(sc); 3334 if (ifp->if_flags & IFF_UP) 3335 xl_init(sc); 3336 3337 splx(s); 3338 return(0); 3339 } 3340