1 /* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: src/sys/pci/if_xl.c,v 1.72.2.28 2003/10/08 06:01:57 murray Exp $ 33 * $DragonFly: src/sys/dev/netif/xl/if_xl.c,v 1.31 2005/08/03 16:01:11 hmp Exp $ 34 */ 35 36 /* 37 * 3Com 3c90x Etherlink XL PCI NIC driver 38 * 39 * Supports the 3Com "boomerang", "cyclone" and "hurricane" PCI 40 * bus-master chips (3c90x cards and embedded controllers) including 41 * the following: 42 * 43 * 3Com 3c900-TPO 10Mbps/RJ-45 44 * 3Com 3c900-COMBO 10Mbps/RJ-45,AUI,BNC 45 * 3Com 3c905-TX 10/100Mbps/RJ-45 46 * 3Com 3c905-T4 10/100Mbps/RJ-45 47 * 3Com 3c900B-TPO 10Mbps/RJ-45 48 * 3Com 3c900B-COMBO 10Mbps/RJ-45,AUI,BNC 49 * 3Com 3c900B-TPC 10Mbps/RJ-45,BNC 50 * 3Com 3c900B-FL 10Mbps/Fiber-optic 51 * 3Com 3c905B-COMBO 10/100Mbps/RJ-45,AUI,BNC 52 * 3Com 3c905B-TX 10/100Mbps/RJ-45 53 * 3Com 3c905B-FL/FX 10/100Mbps/Fiber-optic 54 * 3Com 3c905C-TX 10/100Mbps/RJ-45 (Tornado ASIC) 55 * 3Com 3c980-TX 10/100Mbps server adapter (Hurricane ASIC) 56 * 3Com 3c980C-TX 10/100Mbps server adapter (Tornado ASIC) 57 * 3Com 3cSOHO100-TX 10/100Mbps/RJ-45 (Hurricane ASIC) 58 * 3Com 3c450-TX 10/100Mbps/RJ-45 (Tornado ASIC) 59 * 3Com 3c555 10/100Mbps/RJ-45 (MiniPCI, Laptop Hurricane) 60 * 3Com 3c556 10/100Mbps/RJ-45 (MiniPCI, Hurricane ASIC) 61 * 3Com 3c556B 10/100Mbps/RJ-45 (MiniPCI, Hurricane ASIC) 62 * 3Com 3c575TX 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC) 63 * 3Com 3c575B 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC) 64 * 3Com 3c575C 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC) 65 * 3Com 3cxfem656 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC) 66 * 3Com 3cxfem656b 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC) 67 * 3Com 3cxfem656c 10/100Mbps/RJ-45 (Cardbus, Tornado ASIC) 68 * Dell Optiplex GX1 on-board 3c918 10/100Mbps/RJ-45 69 * Dell on-board 3c920 10/100Mbps/RJ-45 70 * Dell Precision on-board 3c905B 10/100Mbps/RJ-45 71 * Dell Latitude laptop docking station embedded 3c905-TX 72 * 73 * Written by Bill Paul <wpaul@ctr.columbia.edu> 74 * Electrical Engineering Department 75 * Columbia University, New York City 76 */ 77 78 /* 79 * The 3c90x series chips use a bus-master DMA interface for transfering 80 * packets to and from the controller chip. Some of the "vortex" cards 81 * (3c59x) also supported a bus master mode, however for those chips 82 * you could only DMA packets to/from a contiguous memory buffer. For 83 * transmission this would mean copying the contents of the queued mbuf 84 * chain into an mbuf cluster and then DMAing the cluster. This extra 85 * copy would sort of defeat the purpose of the bus master support for 86 * any packet that doesn't fit into a single mbuf. 87 * 88 * By contrast, the 3c90x cards support a fragment-based bus master 89 * mode where mbuf chains can be encapsulated using TX descriptors. 90 * This is similar to other PCI chips such as the Texas Instruments 91 * ThunderLAN and the Intel 82557/82558. 92 * 93 * The "vortex" driver (if_vx.c) happens to work for the "boomerang" 94 * bus master chips because they maintain the old PIO interface for 95 * backwards compatibility, but starting with the 3c905B and the 96 * "cyclone" chips, the compatibility interface has been dropped. 97 * Since using bus master DMA is a big win, we use this driver to 98 * support the PCI "boomerang" chips even though they work with the 99 * "vortex" driver in order to obtain better performance. 100 */ 101 102 #include <sys/param.h> 103 #include <sys/systm.h> 104 #include <sys/sockio.h> 105 #include <sys/endian.h> 106 #include <sys/mbuf.h> 107 #include <sys/kernel.h> 108 #include <sys/socket.h> 109 #include <sys/thread2.h> 110 111 #include <net/if.h> 112 #include <net/ifq_var.h> 113 #include <net/if_arp.h> 114 #include <net/ethernet.h> 115 #include <net/if_dl.h> 116 #include <net/if_media.h> 117 #include <net/vlan/if_vlan_var.h> 118 119 #include <net/bpf.h> 120 121 #include <machine/bus_memio.h> 122 #include <machine/bus_pio.h> 123 #include <machine/bus.h> 124 #include <machine/resource.h> 125 #include <sys/bus.h> 126 #include <sys/rman.h> 127 128 #include "../mii_layer/mii.h" 129 #include "../mii_layer/miivar.h" 130 131 #include <bus/pci/pcireg.h> 132 #include <bus/pci/pcivar.h> 133 134 /* "controller miibus0" required. See GENERIC if you get errors here. */ 135 #include "miibus_if.h" 136 137 #include "if_xlreg.h" 138 139 #define XL905B_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 140 141 /* 142 * Various supported device vendors/types and their names. 143 */ 144 static struct xl_type xl_devs[] = { 145 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10BT, 146 "3Com 3c900-TPO Etherlink XL" }, 147 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10BT_COMBO, 148 "3Com 3c900-COMBO Etherlink XL" }, 149 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10_100BT, 150 "3Com 3c905-TX Fast Etherlink XL" }, 151 { TC_VENDORID, TC_DEVICEID_BOOMERANG_100BT4, 152 "3Com 3c905-T4 Fast Etherlink XL" }, 153 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT, 154 "3Com 3c900B-TPO Etherlink XL" }, 155 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT_COMBO, 156 "3Com 3c900B-COMBO Etherlink XL" }, 157 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT_TPC, 158 "3Com 3c900B-TPC Etherlink XL" }, 159 { TC_VENDORID, TC_DEVICEID_CYCLONE_10FL, 160 "3Com 3c900B-FL Etherlink XL" }, 161 { TC_VENDORID, TC_DEVICEID_HURRICANE_10_100BT, 162 "3Com 3c905B-TX Fast Etherlink XL" }, 163 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100BT4, 164 "3Com 3c905B-T4 Fast Etherlink XL" }, 165 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100FX, 166 "3Com 3c905B-FX/SC Fast Etherlink XL" }, 167 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100_COMBO, 168 "3Com 3c905B-COMBO Fast Etherlink XL" }, 169 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT, 170 "3Com 3c905C-TX Fast Etherlink XL" }, 171 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT_920B, 172 "3Com 3c920B-EMB Integrated Fast Etherlink XL" }, 173 { TC_VENDORID, TC_DEVICEID_HURRICANE_10_100BT_SERV, 174 "3Com 3c980 Fast Etherlink XL" }, 175 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT_SERV, 176 "3Com 3c980C Fast Etherlink XL" }, 177 { TC_VENDORID, TC_DEVICEID_HURRICANE_SOHO100TX, 178 "3Com 3cSOHO100-TX OfficeConnect" }, 179 { TC_VENDORID, TC_DEVICEID_TORNADO_HOMECONNECT, 180 "3Com 3c450-TX HomeConnect" }, 181 { TC_VENDORID, TC_DEVICEID_HURRICANE_555, 182 "3Com 3c555 Fast Etherlink XL" }, 183 { TC_VENDORID, TC_DEVICEID_HURRICANE_556, 184 "3Com 3c556 Fast Etherlink XL" }, 185 { TC_VENDORID, TC_DEVICEID_HURRICANE_556B, 186 "3Com 3c556B Fast Etherlink XL" }, 187 { TC_VENDORID, TC_DEVICEID_HURRICANE_575A, 188 "3Com 3c575TX Fast Etherlink XL" }, 189 { TC_VENDORID, TC_DEVICEID_HURRICANE_575B, 190 "3Com 3c575B Fast Etherlink XL" }, 191 { TC_VENDORID, TC_DEVICEID_HURRICANE_575C, 192 "3Com 3c575C Fast Etherlink XL" }, 193 { TC_VENDORID, TC_DEVICEID_HURRICANE_656, 194 "3Com 3c656 Fast Etherlink XL" }, 195 { TC_VENDORID, TC_DEVICEID_HURRICANE_656B, 196 "3Com 3c656B Fast Etherlink XL" }, 197 { TC_VENDORID, TC_DEVICEID_TORNADO_656C, 198 "3Com 3c656C Fast Etherlink XL" }, 199 { 0, 0, NULL } 200 }; 201 202 static int xl_probe (device_t); 203 static int xl_attach (device_t); 204 static int xl_detach (device_t); 205 206 static int xl_newbuf (struct xl_softc *, struct xl_chain_onefrag *); 207 static void xl_stats_update (void *); 208 static int xl_encap (struct xl_softc *, struct xl_chain *, 209 struct mbuf *); 210 static void xl_rxeof (struct xl_softc *); 211 static int xl_rx_resync (struct xl_softc *); 212 static void xl_txeof (struct xl_softc *); 213 static void xl_txeof_90xB (struct xl_softc *); 214 static void xl_txeoc (struct xl_softc *); 215 static void xl_intr (void *); 216 static void xl_start (struct ifnet *); 217 static void xl_start_90xB (struct ifnet *); 218 static int xl_ioctl (struct ifnet *, u_long, caddr_t, 219 struct ucred *); 220 static void xl_init (void *); 221 static void xl_stop (struct xl_softc *); 222 static void xl_watchdog (struct ifnet *); 223 static void xl_shutdown (device_t); 224 static int xl_suspend (device_t); 225 static int xl_resume (device_t); 226 227 static int xl_ifmedia_upd (struct ifnet *); 228 static void xl_ifmedia_sts (struct ifnet *, struct ifmediareq *); 229 230 static int xl_eeprom_wait (struct xl_softc *); 231 static int xl_read_eeprom (struct xl_softc *, caddr_t, int, int, int); 232 static void xl_mii_sync (struct xl_softc *); 233 static void xl_mii_send (struct xl_softc *, u_int32_t, int); 234 static int xl_mii_readreg (struct xl_softc *, struct xl_mii_frame *); 235 static int xl_mii_writereg (struct xl_softc *, struct xl_mii_frame *); 236 237 static void xl_setcfg (struct xl_softc *); 238 static void xl_setmode (struct xl_softc *, int); 239 static void xl_setmulti (struct xl_softc *); 240 static void xl_setmulti_hash (struct xl_softc *); 241 static void xl_reset (struct xl_softc *); 242 static int xl_list_rx_init (struct xl_softc *); 243 static int xl_list_tx_init (struct xl_softc *); 244 static int xl_list_tx_init_90xB (struct xl_softc *); 245 static void xl_wait (struct xl_softc *); 246 static void xl_mediacheck (struct xl_softc *); 247 static void xl_choose_xcvr (struct xl_softc *, int); 248 static void xl_dma_map_addr (void *, bus_dma_segment_t *, int, int); 249 static void xl_dma_map_rxbuf (void *, bus_dma_segment_t *, int, bus_size_t, 250 int); 251 static void xl_dma_map_txbuf (void *, bus_dma_segment_t *, int, bus_size_t, 252 int); 253 #ifdef notdef 254 static void xl_testpacket (struct xl_softc *); 255 #endif 256 257 static int xl_miibus_readreg (device_t, int, int); 258 static int xl_miibus_writereg (device_t, int, int, int); 259 static void xl_miibus_statchg (device_t); 260 static void xl_miibus_mediainit (device_t); 261 262 static device_method_t xl_methods[] = { 263 /* Device interface */ 264 DEVMETHOD(device_probe, xl_probe), 265 DEVMETHOD(device_attach, xl_attach), 266 DEVMETHOD(device_detach, xl_detach), 267 DEVMETHOD(device_shutdown, xl_shutdown), 268 DEVMETHOD(device_suspend, xl_suspend), 269 DEVMETHOD(device_resume, xl_resume), 270 271 /* bus interface */ 272 DEVMETHOD(bus_print_child, bus_generic_print_child), 273 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 274 275 /* MII interface */ 276 DEVMETHOD(miibus_readreg, xl_miibus_readreg), 277 DEVMETHOD(miibus_writereg, xl_miibus_writereg), 278 DEVMETHOD(miibus_statchg, xl_miibus_statchg), 279 DEVMETHOD(miibus_mediainit, xl_miibus_mediainit), 280 281 { 0, 0 } 282 }; 283 284 static driver_t xl_driver = { 285 "xl", 286 xl_methods, 287 sizeof(struct xl_softc) 288 }; 289 290 static devclass_t xl_devclass; 291 292 DECLARE_DUMMY_MODULE(if_xl); 293 MODULE_DEPEND(if_xl, miibus, 1, 1, 1); 294 DRIVER_MODULE(if_xl, pci, xl_driver, xl_devclass, 0, 0); 295 DRIVER_MODULE(if_xl, cardbus, xl_driver, xl_devclass, 0, 0); 296 DRIVER_MODULE(miibus, xl, miibus_driver, miibus_devclass, 0, 0); 297 298 static void 299 xl_dma_map_addr(arg, segs, nseg, error) 300 void *arg; 301 bus_dma_segment_t *segs; 302 int nseg, error; 303 { 304 u_int32_t *paddr; 305 306 paddr = arg; 307 *paddr = segs->ds_addr; 308 } 309 310 static void 311 xl_dma_map_rxbuf(arg, segs, nseg, mapsize, error) 312 void *arg; 313 bus_dma_segment_t *segs; 314 int nseg; 315 bus_size_t mapsize; 316 int error; 317 { 318 u_int32_t *paddr; 319 320 if (error) 321 return; 322 KASSERT(nseg == 1, ("xl_dma_map_rxbuf: too many DMA segments")); 323 paddr = arg; 324 *paddr = segs->ds_addr; 325 } 326 327 static void 328 xl_dma_map_txbuf(arg, segs, nseg, mapsize, error) 329 void *arg; 330 bus_dma_segment_t *segs; 331 int nseg; 332 bus_size_t mapsize; 333 int error; 334 { 335 struct xl_list *l; 336 int i, total_len; 337 338 if (error) 339 return; 340 341 KASSERT(nseg <= XL_MAXFRAGS, ("too many DMA segments")); 342 343 total_len = 0; 344 l = arg; 345 for (i = 0; i < nseg; i++) { 346 KASSERT(segs[i].ds_len <= MCLBYTES, ("segment size too large")); 347 l->xl_frag[i].xl_addr = htole32(segs[i].ds_addr); 348 l->xl_frag[i].xl_len = htole32(segs[i].ds_len); 349 total_len += segs[i].ds_len; 350 } 351 l->xl_frag[nseg - 1].xl_len = htole32(segs[nseg - 1].ds_len | 352 XL_LAST_FRAG); 353 l->xl_status = htole32(total_len); 354 l->xl_next = 0; 355 } 356 357 /* 358 * Murphy's law says that it's possible the chip can wedge and 359 * the 'command in progress' bit may never clear. Hence, we wait 360 * only a finite amount of time to avoid getting caught in an 361 * infinite loop. Normally this delay routine would be a macro, 362 * but it isn't called during normal operation so we can afford 363 * to make it a function. 364 */ 365 static void 366 xl_wait(sc) 367 struct xl_softc *sc; 368 { 369 int i; 370 371 for (i = 0; i < XL_TIMEOUT; i++) { 372 if (!(CSR_READ_2(sc, XL_STATUS) & XL_STAT_CMDBUSY)) 373 break; 374 } 375 376 if (i == XL_TIMEOUT) 377 if_printf(&sc->arpcom.ac_if, "command never completed!"); 378 379 return; 380 } 381 382 /* 383 * MII access routines are provided for adapters with external 384 * PHYs (3c905-TX, 3c905-T4, 3c905B-T4) and those with built-in 385 * autoneg logic that's faked up to look like a PHY (3c905B-TX). 386 * Note: if you don't perform the MDIO operations just right, 387 * it's possible to end up with code that works correctly with 388 * some chips/CPUs/processor speeds/bus speeds/etc but not 389 * with others. 390 */ 391 #define MII_SET(x) \ 392 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, \ 393 CSR_READ_2(sc, XL_W4_PHY_MGMT) | (x)) 394 395 #define MII_CLR(x) \ 396 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, \ 397 CSR_READ_2(sc, XL_W4_PHY_MGMT) & ~(x)) 398 399 /* 400 * Sync the PHYs by setting data bit and strobing the clock 32 times. 401 */ 402 static void 403 xl_mii_sync(sc) 404 struct xl_softc *sc; 405 { 406 int i; 407 408 XL_SEL_WIN(4); 409 MII_SET(XL_MII_DIR|XL_MII_DATA); 410 411 for (i = 0; i < 32; i++) { 412 MII_SET(XL_MII_CLK); 413 MII_SET(XL_MII_DATA); 414 MII_SET(XL_MII_DATA); 415 MII_CLR(XL_MII_CLK); 416 MII_SET(XL_MII_DATA); 417 MII_SET(XL_MII_DATA); 418 } 419 420 return; 421 } 422 423 /* 424 * Clock a series of bits through the MII. 425 */ 426 static void 427 xl_mii_send(sc, bits, cnt) 428 struct xl_softc *sc; 429 u_int32_t bits; 430 int cnt; 431 { 432 int i; 433 434 XL_SEL_WIN(4); 435 MII_CLR(XL_MII_CLK); 436 437 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 438 if (bits & i) { 439 MII_SET(XL_MII_DATA); 440 } else { 441 MII_CLR(XL_MII_DATA); 442 } 443 MII_CLR(XL_MII_CLK); 444 MII_SET(XL_MII_CLK); 445 } 446 } 447 448 /* 449 * Read an PHY register through the MII. 450 */ 451 static int 452 xl_mii_readreg(sc, frame) 453 struct xl_softc *sc; 454 struct xl_mii_frame *frame; 455 456 { 457 int i, ack; 458 459 crit_enter(); 460 461 /* 462 * Set up frame for RX. 463 */ 464 frame->mii_stdelim = XL_MII_STARTDELIM; 465 frame->mii_opcode = XL_MII_READOP; 466 frame->mii_turnaround = 0; 467 frame->mii_data = 0; 468 469 /* 470 * Select register window 4. 471 */ 472 473 XL_SEL_WIN(4); 474 475 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, 0); 476 /* 477 * Turn on data xmit. 478 */ 479 MII_SET(XL_MII_DIR); 480 481 xl_mii_sync(sc); 482 483 /* 484 * Send command/address info. 485 */ 486 xl_mii_send(sc, frame->mii_stdelim, 2); 487 xl_mii_send(sc, frame->mii_opcode, 2); 488 xl_mii_send(sc, frame->mii_phyaddr, 5); 489 xl_mii_send(sc, frame->mii_regaddr, 5); 490 491 /* Idle bit */ 492 MII_CLR((XL_MII_CLK|XL_MII_DATA)); 493 MII_SET(XL_MII_CLK); 494 495 /* Turn off xmit. */ 496 MII_CLR(XL_MII_DIR); 497 498 /* Check for ack */ 499 MII_CLR(XL_MII_CLK); 500 ack = CSR_READ_2(sc, XL_W4_PHY_MGMT) & XL_MII_DATA; 501 MII_SET(XL_MII_CLK); 502 503 /* 504 * Now try reading data bits. If the ack failed, we still 505 * need to clock through 16 cycles to keep the PHY(s) in sync. 506 */ 507 if (ack) { 508 for(i = 0; i < 16; i++) { 509 MII_CLR(XL_MII_CLK); 510 MII_SET(XL_MII_CLK); 511 } 512 goto fail; 513 } 514 515 for (i = 0x8000; i; i >>= 1) { 516 MII_CLR(XL_MII_CLK); 517 if (!ack) { 518 if (CSR_READ_2(sc, XL_W4_PHY_MGMT) & XL_MII_DATA) 519 frame->mii_data |= i; 520 } 521 MII_SET(XL_MII_CLK); 522 } 523 524 fail: 525 526 MII_CLR(XL_MII_CLK); 527 MII_SET(XL_MII_CLK); 528 529 crit_exit(); 530 531 if (ack) 532 return(1); 533 return(0); 534 } 535 536 /* 537 * Write to a PHY register through the MII. 538 */ 539 static int 540 xl_mii_writereg(sc, frame) 541 struct xl_softc *sc; 542 struct xl_mii_frame *frame; 543 544 { 545 crit_enter(); 546 547 /* 548 * Set up frame for TX. 549 */ 550 551 frame->mii_stdelim = XL_MII_STARTDELIM; 552 frame->mii_opcode = XL_MII_WRITEOP; 553 frame->mii_turnaround = XL_MII_TURNAROUND; 554 555 /* 556 * Select the window 4. 557 */ 558 XL_SEL_WIN(4); 559 560 /* 561 * Turn on data output. 562 */ 563 MII_SET(XL_MII_DIR); 564 565 xl_mii_sync(sc); 566 567 xl_mii_send(sc, frame->mii_stdelim, 2); 568 xl_mii_send(sc, frame->mii_opcode, 2); 569 xl_mii_send(sc, frame->mii_phyaddr, 5); 570 xl_mii_send(sc, frame->mii_regaddr, 5); 571 xl_mii_send(sc, frame->mii_turnaround, 2); 572 xl_mii_send(sc, frame->mii_data, 16); 573 574 /* Idle bit. */ 575 MII_SET(XL_MII_CLK); 576 MII_CLR(XL_MII_CLK); 577 578 /* 579 * Turn off xmit. 580 */ 581 MII_CLR(XL_MII_DIR); 582 583 crit_exit(); 584 585 return(0); 586 } 587 588 static int 589 xl_miibus_readreg(dev, phy, reg) 590 device_t dev; 591 int phy, reg; 592 { 593 struct xl_softc *sc; 594 struct xl_mii_frame frame; 595 596 sc = device_get_softc(dev); 597 598 /* 599 * Pretend that PHYs are only available at MII address 24. 600 * This is to guard against problems with certain 3Com ASIC 601 * revisions that incorrectly map the internal transceiver 602 * control registers at all MII addresses. This can cause 603 * the miibus code to attach the same PHY several times over. 604 */ 605 if ((!(sc->xl_flags & XL_FLAG_PHYOK)) && phy != 24) 606 return(0); 607 608 bzero((char *)&frame, sizeof(frame)); 609 610 frame.mii_phyaddr = phy; 611 frame.mii_regaddr = reg; 612 xl_mii_readreg(sc, &frame); 613 614 return(frame.mii_data); 615 } 616 617 static int 618 xl_miibus_writereg(dev, phy, reg, data) 619 device_t dev; 620 int phy, reg, data; 621 { 622 struct xl_softc *sc; 623 struct xl_mii_frame frame; 624 625 sc = device_get_softc(dev); 626 627 if ((!(sc->xl_flags & XL_FLAG_PHYOK)) && phy != 24) 628 return(0); 629 630 bzero((char *)&frame, sizeof(frame)); 631 632 frame.mii_phyaddr = phy; 633 frame.mii_regaddr = reg; 634 frame.mii_data = data; 635 636 xl_mii_writereg(sc, &frame); 637 638 return(0); 639 } 640 641 static void 642 xl_miibus_statchg(dev) 643 device_t dev; 644 { 645 struct xl_softc *sc; 646 struct mii_data *mii; 647 648 649 sc = device_get_softc(dev); 650 mii = device_get_softc(sc->xl_miibus); 651 652 xl_setcfg(sc); 653 654 /* Set ASIC's duplex mode to match the PHY. */ 655 XL_SEL_WIN(3); 656 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) 657 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, XL_MACCTRL_DUPLEX); 658 else 659 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, 660 (CSR_READ_1(sc, XL_W3_MAC_CTRL) & ~XL_MACCTRL_DUPLEX)); 661 662 return; 663 } 664 665 /* 666 * Special support for the 3c905B-COMBO. This card has 10/100 support 667 * plus BNC and AUI ports. This means we will have both an miibus attached 668 * plus some non-MII media settings. In order to allow this, we have to 669 * add the extra media to the miibus's ifmedia struct, but we can't do 670 * that during xl_attach() because the miibus hasn't been attached yet. 671 * So instead, we wait until the miibus probe/attach is done, at which 672 * point we will get a callback telling is that it's safe to add our 673 * extra media. 674 */ 675 static void 676 xl_miibus_mediainit(dev) 677 device_t dev; 678 { 679 struct xl_softc *sc; 680 struct mii_data *mii; 681 struct ifmedia *ifm; 682 683 sc = device_get_softc(dev); 684 mii = device_get_softc(sc->xl_miibus); 685 ifm = &mii->mii_media; 686 687 if (sc->xl_media & (XL_MEDIAOPT_AUI|XL_MEDIAOPT_10FL)) { 688 /* 689 * Check for a 10baseFL board in disguise. 690 */ 691 if (sc->xl_type == XL_TYPE_905B && 692 sc->xl_media == XL_MEDIAOPT_10FL) { 693 if (bootverbose) 694 device_printf(dev, "found 10baseFL\n"); 695 ifmedia_add(ifm, IFM_ETHER|IFM_10_FL, 0, NULL); 696 ifmedia_add(ifm, IFM_ETHER|IFM_10_FL|IFM_HDX, 0, NULL); 697 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX) 698 ifmedia_add(ifm, 699 IFM_ETHER|IFM_10_FL|IFM_FDX, 0, NULL); 700 } else { 701 if (bootverbose) 702 device_printf(dev, "found AUI\n"); 703 ifmedia_add(ifm, IFM_ETHER|IFM_10_5, 0, NULL); 704 } 705 } 706 707 if (sc->xl_media & XL_MEDIAOPT_BNC) { 708 if (bootverbose) 709 device_printf(dev, "found BNC\n"); 710 ifmedia_add(ifm, IFM_ETHER|IFM_10_2, 0, NULL); 711 } 712 713 return; 714 } 715 716 /* 717 * The EEPROM is slow: give it time to come ready after issuing 718 * it a command. 719 */ 720 static int 721 xl_eeprom_wait(sc) 722 struct xl_softc *sc; 723 { 724 int i; 725 726 for (i = 0; i < 100; i++) { 727 if (CSR_READ_2(sc, XL_W0_EE_CMD) & XL_EE_BUSY) 728 DELAY(162); 729 else 730 break; 731 } 732 733 if (i == 100) { 734 if_printf(&sc->arpcom.ac_if, "eeprom failed to come ready\n"); 735 return(1); 736 } 737 738 return(0); 739 } 740 741 /* 742 * Read a sequence of words from the EEPROM. Note that ethernet address 743 * data is stored in the EEPROM in network byte order. 744 */ 745 static int 746 xl_read_eeprom(sc, dest, off, cnt, swap) 747 struct xl_softc *sc; 748 caddr_t dest; 749 int off; 750 int cnt; 751 int swap; 752 { 753 int err = 0, i; 754 u_int16_t word = 0, *ptr; 755 #define EEPROM_5BIT_OFFSET(A) ((((A) << 2) & 0x7F00) | ((A) & 0x003F)) 756 #define EEPROM_8BIT_OFFSET(A) ((A) & 0x003F) 757 /* WARNING! DANGER! 758 * It's easy to accidentally overwrite the rom content! 759 * Note: the 3c575 uses 8bit EEPROM offsets. 760 */ 761 XL_SEL_WIN(0); 762 763 if (xl_eeprom_wait(sc)) 764 return(1); 765 766 if (sc->xl_flags & XL_FLAG_EEPROM_OFFSET_30) 767 off += 0x30; 768 769 for (i = 0; i < cnt; i++) { 770 if (sc->xl_flags & XL_FLAG_8BITROM) 771 CSR_WRITE_2(sc, XL_W0_EE_CMD, 772 XL_EE_8BIT_READ | EEPROM_8BIT_OFFSET(off + i)); 773 else 774 CSR_WRITE_2(sc, XL_W0_EE_CMD, 775 XL_EE_READ | EEPROM_5BIT_OFFSET(off + i)); 776 err = xl_eeprom_wait(sc); 777 if (err) 778 break; 779 word = CSR_READ_2(sc, XL_W0_EE_DATA); 780 ptr = (u_int16_t *)(dest + (i * 2)); 781 if (swap) 782 *ptr = ntohs(word); 783 else 784 *ptr = word; 785 } 786 787 return(err ? 1 : 0); 788 } 789 790 /* 791 * NICs older than the 3c905B have only one multicast option, which 792 * is to enable reception of all multicast frames. 793 */ 794 static void 795 xl_setmulti(sc) 796 struct xl_softc *sc; 797 { 798 struct ifnet *ifp; 799 struct ifmultiaddr *ifma; 800 u_int8_t rxfilt; 801 int mcnt = 0; 802 803 ifp = &sc->arpcom.ac_if; 804 805 XL_SEL_WIN(5); 806 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER); 807 808 if (ifp->if_flags & IFF_ALLMULTI) { 809 rxfilt |= XL_RXFILTER_ALLMULTI; 810 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 811 return; 812 } 813 814 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) 815 mcnt++; 816 817 if (mcnt) 818 rxfilt |= XL_RXFILTER_ALLMULTI; 819 else 820 rxfilt &= ~XL_RXFILTER_ALLMULTI; 821 822 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 823 824 return; 825 } 826 827 /* 828 * 3c905B adapters have a hash filter that we can program. 829 */ 830 static void 831 xl_setmulti_hash(sc) 832 struct xl_softc *sc; 833 { 834 struct ifnet *ifp; 835 int h = 0, i; 836 struct ifmultiaddr *ifma; 837 u_int8_t rxfilt; 838 int mcnt = 0; 839 840 ifp = &sc->arpcom.ac_if; 841 842 XL_SEL_WIN(5); 843 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER); 844 845 if (ifp->if_flags & IFF_ALLMULTI) { 846 rxfilt |= XL_RXFILTER_ALLMULTI; 847 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 848 return; 849 } else 850 rxfilt &= ~XL_RXFILTER_ALLMULTI; 851 852 853 /* first, zot all the existing hash bits */ 854 for (i = 0; i < XL_HASHFILT_SIZE; i++) 855 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_HASH|i); 856 857 /* now program new ones */ 858 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 859 if (ifma->ifma_addr->sa_family != AF_LINK) 860 continue; 861 862 /* 863 * Note: the 3c905B currently only supports a 64-bit 864 * hash table, which means we really only need 6 bits, 865 * but the manual indicates that future chip revisions 866 * will have a 256-bit hash table, hence the routine is 867 * set up to calculate 8 bits of position info in case 868 * we need it some day. 869 * Note II, The Sequel: _CURRENT_ versions of the 3c905B 870 * have a 256 bit hash table. This means we have to use 871 * all 8 bits regardless. On older cards, the upper 2 872 * bits will be ignored. Grrrr.... 873 */ 874 h = ether_crc32_be( 875 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 876 ETHER_ADDR_LEN) & 0xff; 877 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_HASH|XL_HASH_SET|h); 878 mcnt++; 879 } 880 881 if (mcnt) 882 rxfilt |= XL_RXFILTER_MULTIHASH; 883 else 884 rxfilt &= ~XL_RXFILTER_MULTIHASH; 885 886 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 887 888 return; 889 } 890 891 #ifdef notdef 892 static void 893 xl_testpacket(sc) 894 struct xl_softc *sc; 895 { 896 struct mbuf *m; 897 struct ifnet *ifp; 898 899 ifp = &sc->arpcom.ac_if; 900 901 MGETHDR(m, MB_DONTWAIT, MT_DATA); 902 903 if (m == NULL) 904 return; 905 906 bcopy(&sc->arpcom.ac_enaddr, 907 mtod(m, struct ether_header *)->ether_dhost, ETHER_ADDR_LEN); 908 bcopy(&sc->arpcom.ac_enaddr, 909 mtod(m, struct ether_header *)->ether_shost, ETHER_ADDR_LEN); 910 mtod(m, struct ether_header *)->ether_type = htons(3); 911 mtod(m, unsigned char *)[14] = 0; 912 mtod(m, unsigned char *)[15] = 0; 913 mtod(m, unsigned char *)[16] = 0xE3; 914 m->m_len = m->m_pkthdr.len = sizeof(struct ether_header) + 3; 915 IF_ENQUEUE(&ifp->if_snd, m); 916 xl_start(ifp); 917 918 return; 919 } 920 #endif 921 922 static void 923 xl_setcfg(sc) 924 struct xl_softc *sc; 925 { 926 u_int32_t icfg; 927 928 XL_SEL_WIN(3); 929 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG); 930 icfg &= ~XL_ICFG_CONNECTOR_MASK; 931 if (sc->xl_media & XL_MEDIAOPT_MII || 932 sc->xl_media & XL_MEDIAOPT_BT4) 933 icfg |= (XL_XCVR_MII << XL_ICFG_CONNECTOR_BITS); 934 if (sc->xl_media & XL_MEDIAOPT_BTX) 935 icfg |= (XL_XCVR_AUTO << XL_ICFG_CONNECTOR_BITS); 936 937 CSR_WRITE_4(sc, XL_W3_INTERNAL_CFG, icfg); 938 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP); 939 940 return; 941 } 942 943 static void 944 xl_setmode(sc, media) 945 struct xl_softc *sc; 946 int media; 947 { 948 struct ifnet *ifp = &sc->arpcom.ac_if; 949 u_int32_t icfg; 950 u_int16_t mediastat; 951 952 if_printf(ifp, "selecting "); 953 954 XL_SEL_WIN(4); 955 mediastat = CSR_READ_2(sc, XL_W4_MEDIA_STATUS); 956 XL_SEL_WIN(3); 957 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG); 958 959 if (sc->xl_media & XL_MEDIAOPT_BT) { 960 if (IFM_SUBTYPE(media) == IFM_10_T) { 961 printf("10baseT transceiver, "); 962 sc->xl_xcvr = XL_XCVR_10BT; 963 icfg &= ~XL_ICFG_CONNECTOR_MASK; 964 icfg |= (XL_XCVR_10BT << XL_ICFG_CONNECTOR_BITS); 965 mediastat |= XL_MEDIASTAT_LINKBEAT| 966 XL_MEDIASTAT_JABGUARD; 967 mediastat &= ~XL_MEDIASTAT_SQEENB; 968 } 969 } 970 971 if (sc->xl_media & XL_MEDIAOPT_BFX) { 972 if (IFM_SUBTYPE(media) == IFM_100_FX) { 973 printf("100baseFX port, "); 974 sc->xl_xcvr = XL_XCVR_100BFX; 975 icfg &= ~XL_ICFG_CONNECTOR_MASK; 976 icfg |= (XL_XCVR_100BFX << XL_ICFG_CONNECTOR_BITS); 977 mediastat |= XL_MEDIASTAT_LINKBEAT; 978 mediastat &= ~XL_MEDIASTAT_SQEENB; 979 } 980 } 981 982 if (sc->xl_media & (XL_MEDIAOPT_AUI|XL_MEDIAOPT_10FL)) { 983 if (IFM_SUBTYPE(media) == IFM_10_5) { 984 printf("AUI port, "); 985 sc->xl_xcvr = XL_XCVR_AUI; 986 icfg &= ~XL_ICFG_CONNECTOR_MASK; 987 icfg |= (XL_XCVR_AUI << XL_ICFG_CONNECTOR_BITS); 988 mediastat &= ~(XL_MEDIASTAT_LINKBEAT| 989 XL_MEDIASTAT_JABGUARD); 990 mediastat |= ~XL_MEDIASTAT_SQEENB; 991 } 992 if (IFM_SUBTYPE(media) == IFM_10_FL) { 993 printf("10baseFL transceiver, "); 994 sc->xl_xcvr = XL_XCVR_AUI; 995 icfg &= ~XL_ICFG_CONNECTOR_MASK; 996 icfg |= (XL_XCVR_AUI << XL_ICFG_CONNECTOR_BITS); 997 mediastat &= ~(XL_MEDIASTAT_LINKBEAT| 998 XL_MEDIASTAT_JABGUARD); 999 mediastat |= ~XL_MEDIASTAT_SQEENB; 1000 } 1001 } 1002 1003 if (sc->xl_media & XL_MEDIAOPT_BNC) { 1004 if (IFM_SUBTYPE(media) == IFM_10_2) { 1005 printf("BNC port, "); 1006 sc->xl_xcvr = XL_XCVR_COAX; 1007 icfg &= ~XL_ICFG_CONNECTOR_MASK; 1008 icfg |= (XL_XCVR_COAX << XL_ICFG_CONNECTOR_BITS); 1009 mediastat &= ~(XL_MEDIASTAT_LINKBEAT| 1010 XL_MEDIASTAT_JABGUARD| 1011 XL_MEDIASTAT_SQEENB); 1012 } 1013 } 1014 1015 if ((media & IFM_GMASK) == IFM_FDX || 1016 IFM_SUBTYPE(media) == IFM_100_FX) { 1017 printf("full duplex\n"); 1018 XL_SEL_WIN(3); 1019 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, XL_MACCTRL_DUPLEX); 1020 } else { 1021 printf("half duplex\n"); 1022 XL_SEL_WIN(3); 1023 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, 1024 (CSR_READ_1(sc, XL_W3_MAC_CTRL) & ~XL_MACCTRL_DUPLEX)); 1025 } 1026 1027 if (IFM_SUBTYPE(media) == IFM_10_2) 1028 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_START); 1029 else 1030 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP); 1031 CSR_WRITE_4(sc, XL_W3_INTERNAL_CFG, icfg); 1032 XL_SEL_WIN(4); 1033 CSR_WRITE_2(sc, XL_W4_MEDIA_STATUS, mediastat); 1034 DELAY(800); 1035 XL_SEL_WIN(7); 1036 } 1037 1038 static void 1039 xl_reset(sc) 1040 struct xl_softc *sc; 1041 { 1042 int i; 1043 1044 XL_SEL_WIN(0); 1045 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RESET | 1046 ((sc->xl_flags & XL_FLAG_WEIRDRESET) ? 1047 XL_RESETOPT_DISADVFD:0)); 1048 1049 /* 1050 * If we're using memory mapped register mode, pause briefly 1051 * after issuing the reset command before trying to access any 1052 * other registers. With my 3c575C cardbus card, failing to do 1053 * this results in the system locking up while trying to poll 1054 * the command busy bit in the status register. 1055 */ 1056 if (sc->xl_flags & XL_FLAG_USE_MMIO) 1057 DELAY(100000); 1058 1059 for (i = 0; i < XL_TIMEOUT; i++) { 1060 DELAY(10); 1061 if (!(CSR_READ_2(sc, XL_STATUS) & XL_STAT_CMDBUSY)) 1062 break; 1063 } 1064 1065 if (i == XL_TIMEOUT) 1066 if_printf(&sc->arpcom.ac_if, "reset didn't complete\n"); 1067 1068 /* Reset TX and RX. */ 1069 /* Note: the RX reset takes an absurd amount of time 1070 * on newer versions of the Tornado chips such as those 1071 * on the 3c905CX and newer 3c908C cards. We wait an 1072 * extra amount of time so that xl_wait() doesn't complain 1073 * and annoy the users. 1074 */ 1075 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET); 1076 DELAY(100000); 1077 xl_wait(sc); 1078 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); 1079 xl_wait(sc); 1080 1081 if (sc->xl_flags & XL_FLAG_INVERT_LED_PWR || 1082 sc->xl_flags & XL_FLAG_INVERT_MII_PWR) { 1083 XL_SEL_WIN(2); 1084 CSR_WRITE_2(sc, XL_W2_RESET_OPTIONS, CSR_READ_2(sc, 1085 XL_W2_RESET_OPTIONS) 1086 | ((sc->xl_flags & XL_FLAG_INVERT_LED_PWR)?XL_RESETOPT_INVERT_LED:0) 1087 | ((sc->xl_flags & XL_FLAG_INVERT_MII_PWR)?XL_RESETOPT_INVERT_MII:0) 1088 ); 1089 } 1090 1091 /* Wait a little while for the chip to get its brains in order. */ 1092 DELAY(100000); 1093 return; 1094 } 1095 1096 /* 1097 * Probe for a 3Com Etherlink XL chip. Check the PCI vendor and device 1098 * IDs against our list and return a device name if we find a match. 1099 */ 1100 static int 1101 xl_probe(device_t dev) 1102 { 1103 struct xl_type *t; 1104 uint16_t vid, did; 1105 1106 vid = pci_get_vendor(dev); 1107 did = pci_get_device(dev); 1108 for (t = xl_devs; t->xl_name != NULL; t++) { 1109 if (vid == t->xl_vid && did == t->xl_did) { 1110 device_set_desc(dev, t->xl_name); 1111 return(0); 1112 } 1113 } 1114 return(ENXIO); 1115 } 1116 1117 /* 1118 * This routine is a kludge to work around possible hardware faults 1119 * or manufacturing defects that can cause the media options register 1120 * (or reset options register, as it's called for the first generation 1121 * 3c90x adapters) to return an incorrect result. I have encountered 1122 * one Dell Latitude laptop docking station with an integrated 3c905-TX 1123 * which doesn't have any of the 'mediaopt' bits set. This screws up 1124 * the attach routine pretty badly because it doesn't know what media 1125 * to look for. If we find ourselves in this predicament, this routine 1126 * will try to guess the media options values and warn the user of a 1127 * possible manufacturing defect with his adapter/system/whatever. 1128 */ 1129 static void 1130 xl_mediacheck(sc) 1131 struct xl_softc *sc; 1132 { 1133 struct ifnet *ifp = &sc->arpcom.ac_if; 1134 1135 /* 1136 * If some of the media options bits are set, assume they are 1137 * correct. If not, try to figure it out down below. 1138 * XXX I should check for 10baseFL, but I don't have an adapter 1139 * to test with. 1140 */ 1141 if (sc->xl_media & (XL_MEDIAOPT_MASK & ~XL_MEDIAOPT_VCO)) { 1142 /* 1143 * Check the XCVR value. If it's not in the normal range 1144 * of values, we need to fake it up here. 1145 */ 1146 if (sc->xl_xcvr <= XL_XCVR_AUTO) 1147 return; 1148 else { 1149 if_printf(ifp, "bogus xcvr value in EEPROM (%x)\n", 1150 sc->xl_xcvr); 1151 if_printf(ifp, 1152 "choosing new default based on card type\n"); 1153 } 1154 } else { 1155 if (sc->xl_type == XL_TYPE_905B && 1156 sc->xl_media & XL_MEDIAOPT_10FL) 1157 return; 1158 if_printf(ifp, "WARNING: no media options bits set in " 1159 "the media options register!!\n"); 1160 if_printf(ifp, "this could be a manufacturing defect in " 1161 "your adapter or system\n"); 1162 if_printf(ifp, "attempting to guess media type; you " 1163 "should probably consult your vendor\n"); 1164 } 1165 1166 xl_choose_xcvr(sc, 1); 1167 } 1168 1169 static void 1170 xl_choose_xcvr(sc, verbose) 1171 struct xl_softc *sc; 1172 int verbose; 1173 { 1174 struct ifnet *ifp = &sc->arpcom.ac_if; 1175 u_int16_t devid; 1176 1177 /* 1178 * Read the device ID from the EEPROM. 1179 * This is what's loaded into the PCI device ID register, so it has 1180 * to be correct otherwise we wouldn't have gotten this far. 1181 */ 1182 xl_read_eeprom(sc, (caddr_t)&devid, XL_EE_PRODID, 1, 0); 1183 1184 switch(devid) { 1185 case TC_DEVICEID_BOOMERANG_10BT: /* 3c900-TPO */ 1186 case TC_DEVICEID_KRAKATOA_10BT: /* 3c900B-TPO */ 1187 sc->xl_media = XL_MEDIAOPT_BT; 1188 sc->xl_xcvr = XL_XCVR_10BT; 1189 if (verbose) 1190 if_printf(ifp, "guessing 10BaseT transceiver\n"); 1191 break; 1192 case TC_DEVICEID_BOOMERANG_10BT_COMBO: /* 3c900-COMBO */ 1193 case TC_DEVICEID_KRAKATOA_10BT_COMBO: /* 3c900B-COMBO */ 1194 sc->xl_media = XL_MEDIAOPT_BT|XL_MEDIAOPT_BNC|XL_MEDIAOPT_AUI; 1195 sc->xl_xcvr = XL_XCVR_10BT; 1196 if (verbose) 1197 if_printf(ifp, "guessing COMBO (AUI/BNC/TP)\n"); 1198 break; 1199 case TC_DEVICEID_KRAKATOA_10BT_TPC: /* 3c900B-TPC */ 1200 sc->xl_media = XL_MEDIAOPT_BT|XL_MEDIAOPT_BNC; 1201 sc->xl_xcvr = XL_XCVR_10BT; 1202 if (verbose) 1203 if_printf(ifp, "guessing TPC (BNC/TP)\n"); 1204 break; 1205 case TC_DEVICEID_CYCLONE_10FL: /* 3c900B-FL */ 1206 sc->xl_media = XL_MEDIAOPT_10FL; 1207 sc->xl_xcvr = XL_XCVR_AUI; 1208 if (verbose) 1209 if_printf(ifp, "guessing 10baseFL\n"); 1210 break; 1211 case TC_DEVICEID_BOOMERANG_10_100BT: /* 3c905-TX */ 1212 case TC_DEVICEID_HURRICANE_555: /* 3c555 */ 1213 case TC_DEVICEID_HURRICANE_556: /* 3c556 */ 1214 case TC_DEVICEID_HURRICANE_556B: /* 3c556B */ 1215 case TC_DEVICEID_HURRICANE_575A: /* 3c575TX */ 1216 case TC_DEVICEID_HURRICANE_575B: /* 3c575B */ 1217 case TC_DEVICEID_HURRICANE_575C: /* 3c575C */ 1218 case TC_DEVICEID_HURRICANE_656: /* 3c656 */ 1219 case TC_DEVICEID_HURRICANE_656B: /* 3c656B */ 1220 case TC_DEVICEID_TORNADO_656C: /* 3c656C */ 1221 case TC_DEVICEID_TORNADO_10_100BT_920B: /* 3c920B-EMB */ 1222 sc->xl_media = XL_MEDIAOPT_MII; 1223 sc->xl_xcvr = XL_XCVR_MII; 1224 if (verbose) 1225 if_printf(ifp, "guessing MII\n"); 1226 break; 1227 case TC_DEVICEID_BOOMERANG_100BT4: /* 3c905-T4 */ 1228 case TC_DEVICEID_CYCLONE_10_100BT4: /* 3c905B-T4 */ 1229 sc->xl_media = XL_MEDIAOPT_BT4; 1230 sc->xl_xcvr = XL_XCVR_MII; 1231 if (verbose) 1232 if_printf(ifp, "guessing 100BaseT4/MII\n"); 1233 break; 1234 case TC_DEVICEID_HURRICANE_10_100BT: /* 3c905B-TX */ 1235 case TC_DEVICEID_HURRICANE_10_100BT_SERV:/*3c980-TX */ 1236 case TC_DEVICEID_TORNADO_10_100BT_SERV: /* 3c980C-TX */ 1237 case TC_DEVICEID_HURRICANE_SOHO100TX: /* 3cSOHO100-TX */ 1238 case TC_DEVICEID_TORNADO_10_100BT: /* 3c905C-TX */ 1239 case TC_DEVICEID_TORNADO_HOMECONNECT: /* 3c450-TX */ 1240 sc->xl_media = XL_MEDIAOPT_BTX; 1241 sc->xl_xcvr = XL_XCVR_AUTO; 1242 if (verbose) 1243 if_printf(ifp, "guessing 10/100 internal\n"); 1244 break; 1245 case TC_DEVICEID_CYCLONE_10_100_COMBO: /* 3c905B-COMBO */ 1246 sc->xl_media = XL_MEDIAOPT_BTX|XL_MEDIAOPT_BNC|XL_MEDIAOPT_AUI; 1247 sc->xl_xcvr = XL_XCVR_AUTO; 1248 if (verbose) 1249 if_printf(ifp, "guessing 10/100 plus BNC/AUI\n"); 1250 break; 1251 default: 1252 if_printf(ifp, 1253 "unknown device ID: %x -- defaulting to 10baseT\n", devid); 1254 sc->xl_media = XL_MEDIAOPT_BT; 1255 break; 1256 } 1257 1258 return; 1259 } 1260 1261 /* 1262 * Attach the interface. Allocate softc structures, do ifmedia 1263 * setup and ethernet/BPF attach. 1264 */ 1265 static int 1266 xl_attach(dev) 1267 device_t dev; 1268 { 1269 u_char eaddr[ETHER_ADDR_LEN]; 1270 u_int16_t xcvr[2]; 1271 struct xl_softc *sc; 1272 struct ifnet *ifp; 1273 int media = IFM_ETHER|IFM_100_TX|IFM_FDX; 1274 int error = 0, rid, res; 1275 1276 sc = device_get_softc(dev); 1277 1278 ifmedia_init(&sc->ifmedia, 0, xl_ifmedia_upd, xl_ifmedia_sts); 1279 1280 sc->xl_flags = 0; 1281 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_555) 1282 sc->xl_flags |= XL_FLAG_EEPROM_OFFSET_30 | XL_FLAG_PHYOK; 1283 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_556 || 1284 pci_get_device(dev) == TC_DEVICEID_HURRICANE_556B) 1285 sc->xl_flags |= XL_FLAG_FUNCREG | XL_FLAG_PHYOK | 1286 XL_FLAG_EEPROM_OFFSET_30 | XL_FLAG_WEIRDRESET | 1287 XL_FLAG_INVERT_LED_PWR | XL_FLAG_INVERT_MII_PWR; 1288 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_555 || 1289 pci_get_device(dev) == TC_DEVICEID_HURRICANE_556) 1290 sc->xl_flags |= XL_FLAG_8BITROM; 1291 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_556B) 1292 sc->xl_flags |= XL_FLAG_NO_XCVR_PWR; 1293 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_575B || 1294 pci_get_device(dev) == TC_DEVICEID_HURRICANE_575C || 1295 pci_get_device(dev) == TC_DEVICEID_HURRICANE_656B || 1296 pci_get_device(dev) == TC_DEVICEID_TORNADO_656C) 1297 sc->xl_flags |= XL_FLAG_FUNCREG; 1298 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_575A || 1299 pci_get_device(dev) == TC_DEVICEID_HURRICANE_575B || 1300 pci_get_device(dev) == TC_DEVICEID_HURRICANE_575C || 1301 pci_get_device(dev) == TC_DEVICEID_HURRICANE_656B || 1302 pci_get_device(dev) == TC_DEVICEID_TORNADO_656C) 1303 sc->xl_flags |= XL_FLAG_PHYOK | XL_FLAG_EEPROM_OFFSET_30 | 1304 XL_FLAG_8BITROM; 1305 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_656) 1306 sc->xl_flags |= XL_FLAG_FUNCREG | XL_FLAG_PHYOK; 1307 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_575B) 1308 sc->xl_flags |= XL_FLAG_INVERT_LED_PWR; 1309 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_575C) 1310 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR; 1311 if (pci_get_device(dev) == TC_DEVICEID_TORNADO_656C) 1312 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR; 1313 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_656 || 1314 pci_get_device(dev) == TC_DEVICEID_HURRICANE_656B) 1315 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR | 1316 XL_FLAG_INVERT_LED_PWR; 1317 if (pci_get_device(dev) == TC_DEVICEID_TORNADO_10_100BT_920B) 1318 sc->xl_flags |= XL_FLAG_PHYOK; 1319 #ifndef BURN_BRIDGES 1320 /* 1321 * If this is a 3c905B, we have to check one extra thing. 1322 * The 905B supports power management and may be placed in 1323 * a low-power mode (D3 mode), typically by certain operating 1324 * systems which shall not be named. The PCI BIOS is supposed 1325 * to reset the NIC and bring it out of low-power mode, but 1326 * some do not. Consequently, we have to see if this chip 1327 * supports power management, and if so, make sure it's not 1328 * in low-power mode. If power management is available, the 1329 * capid byte will be 0x01. 1330 * 1331 * I _think_ that what actually happens is that the chip 1332 * loses its PCI configuration during the transition from 1333 * D3 back to D0; this means that it should be possible for 1334 * us to save the PCI iobase, membase and IRQ, put the chip 1335 * back in the D0 state, then restore the PCI config ourselves. 1336 */ 1337 1338 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 1339 u_int32_t iobase, membase, irq; 1340 1341 /* Save important PCI config data. */ 1342 iobase = pci_read_config(dev, XL_PCI_LOIO, 4); 1343 membase = pci_read_config(dev, XL_PCI_LOMEM, 4); 1344 irq = pci_read_config(dev, XL_PCI_INTLINE, 4); 1345 1346 /* Reset the power state. */ 1347 device_printf(dev, "chip is in D%d power mode " 1348 "-- setting to D0\n", pci_get_powerstate(dev)); 1349 1350 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 1351 1352 /* Restore PCI config data. */ 1353 pci_write_config(dev, XL_PCI_LOIO, iobase, 4); 1354 pci_write_config(dev, XL_PCI_LOMEM, membase, 4); 1355 pci_write_config(dev, XL_PCI_INTLINE, irq, 4); 1356 } 1357 #endif 1358 /* 1359 * Map control/status registers. 1360 */ 1361 pci_enable_busmaster(dev); 1362 1363 rid = XL_PCI_LOMEM; 1364 res = SYS_RES_MEMORY; 1365 1366 #if 0 1367 sc->xl_res = bus_alloc_resource_any(dev, res, &rid, RF_ACTIVE); 1368 #endif 1369 1370 if (sc->xl_res != NULL) { 1371 sc->xl_flags |= XL_FLAG_USE_MMIO; 1372 if (bootverbose) 1373 device_printf(dev, "using memory mapped I/O\n"); 1374 } else { 1375 rid = XL_PCI_LOIO; 1376 res = SYS_RES_IOPORT; 1377 sc->xl_res = bus_alloc_resource_any(dev, res, &rid, RF_ACTIVE); 1378 if (sc->xl_res == NULL) { 1379 device_printf(dev, "couldn't map ports/memory\n"); 1380 error = ENXIO; 1381 goto fail; 1382 } 1383 if (bootverbose) 1384 device_printf(dev, "using port I/O\n"); 1385 } 1386 1387 sc->xl_btag = rman_get_bustag(sc->xl_res); 1388 sc->xl_bhandle = rman_get_bushandle(sc->xl_res); 1389 1390 if (sc->xl_flags & XL_FLAG_FUNCREG) { 1391 rid = XL_PCI_FUNCMEM; 1392 sc->xl_fres = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 1393 RF_ACTIVE); 1394 1395 if (sc->xl_fres == NULL) { 1396 device_printf(dev, "couldn't map funcreg memory\n"); 1397 error = ENXIO; 1398 goto fail; 1399 } 1400 1401 sc->xl_ftag = rman_get_bustag(sc->xl_fres); 1402 sc->xl_fhandle = rman_get_bushandle(sc->xl_fres); 1403 } 1404 1405 /* Allocate interrupt */ 1406 rid = 0; 1407 sc->xl_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1408 RF_SHAREABLE | RF_ACTIVE); 1409 if (sc->xl_irq == NULL) { 1410 device_printf(dev, "couldn't map interrupt\n"); 1411 error = ENXIO; 1412 goto fail; 1413 } 1414 1415 sc->xl_flags |= XL_FLAG_ATTACH_MAPPED; 1416 1417 ifp = &sc->arpcom.ac_if; 1418 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1419 1420 /* Reset the adapter. */ 1421 xl_reset(sc); 1422 1423 /* 1424 * Get station address from the EEPROM. 1425 */ 1426 if (xl_read_eeprom(sc, (caddr_t)&eaddr, XL_EE_OEM_ADR0, 3, 1)) { 1427 device_printf(dev, "failed to read station address\n"); 1428 error = ENXIO; 1429 goto fail; 1430 } 1431 1432 callout_init(&sc->xl_stat_timer); 1433 1434 /* 1435 * Now allocate a tag for the DMA descriptor lists and a chunk 1436 * of DMA-able memory based on the tag. Also obtain the DMA 1437 * addresses of the RX and TX ring, which we'll need later. 1438 * All of our lists are allocated as a contiguous block 1439 * of memory. 1440 */ 1441 error = bus_dma_tag_create(NULL, 8, 0, 1442 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 1443 XL_RX_LIST_SZ, 1, XL_RX_LIST_SZ, 0, 1444 &sc->xl_ldata.xl_rx_tag); 1445 if (error) { 1446 device_printf(dev, "failed to allocate rx dma tag\n"); 1447 goto fail; 1448 } 1449 1450 error = bus_dmamem_alloc(sc->xl_ldata.xl_rx_tag, 1451 (void **)&sc->xl_ldata.xl_rx_list, BUS_DMA_NOWAIT, 1452 &sc->xl_ldata.xl_rx_dmamap); 1453 if (error) { 1454 device_printf(dev, "no memory for rx list buffers!\n"); 1455 bus_dma_tag_destroy(sc->xl_ldata.xl_rx_tag); 1456 sc->xl_ldata.xl_rx_tag = NULL; 1457 goto fail; 1458 } 1459 1460 error = bus_dmamap_load(sc->xl_ldata.xl_rx_tag, 1461 sc->xl_ldata.xl_rx_dmamap, sc->xl_ldata.xl_rx_list, 1462 XL_RX_LIST_SZ, xl_dma_map_addr, 1463 &sc->xl_ldata.xl_rx_dmaaddr, BUS_DMA_NOWAIT); 1464 if (error) { 1465 device_printf(dev, "cannot get dma address of the rx ring!\n"); 1466 bus_dmamem_free(sc->xl_ldata.xl_rx_tag, sc->xl_ldata.xl_rx_list, 1467 sc->xl_ldata.xl_rx_dmamap); 1468 bus_dma_tag_destroy(sc->xl_ldata.xl_rx_tag); 1469 sc->xl_ldata.xl_rx_tag = NULL; 1470 goto fail; 1471 } 1472 1473 error = bus_dma_tag_create(NULL, 8, 0, 1474 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 1475 XL_TX_LIST_SZ, 1, XL_TX_LIST_SZ, 0, 1476 &sc->xl_ldata.xl_tx_tag); 1477 if (error) { 1478 device_printf(dev, "failed to allocate tx dma tag\n"); 1479 goto fail; 1480 } 1481 1482 error = bus_dmamem_alloc(sc->xl_ldata.xl_tx_tag, 1483 (void **)&sc->xl_ldata.xl_tx_list, BUS_DMA_NOWAIT, 1484 &sc->xl_ldata.xl_tx_dmamap); 1485 if (error) { 1486 device_printf(dev, "no memory for list buffers!\n"); 1487 bus_dma_tag_destroy(sc->xl_ldata.xl_tx_tag); 1488 sc->xl_ldata.xl_tx_tag = NULL; 1489 goto fail; 1490 } 1491 1492 error = bus_dmamap_load(sc->xl_ldata.xl_tx_tag, 1493 sc->xl_ldata.xl_tx_dmamap, sc->xl_ldata.xl_tx_list, 1494 XL_TX_LIST_SZ, xl_dma_map_addr, 1495 &sc->xl_ldata.xl_tx_dmaaddr, BUS_DMA_NOWAIT); 1496 if (error) { 1497 device_printf(dev, "cannot get dma address of the tx ring!\n"); 1498 bus_dmamem_free(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_list, 1499 sc->xl_ldata.xl_tx_dmamap); 1500 bus_dma_tag_destroy(sc->xl_ldata.xl_tx_tag); 1501 sc->xl_ldata.xl_tx_tag = NULL; 1502 goto fail; 1503 } 1504 1505 /* 1506 * Allocate a DMA tag for the mapping of mbufs. 1507 */ 1508 error = bus_dma_tag_create(NULL, 1, 0, 1509 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 1510 MCLBYTES * XL_MAXFRAGS, XL_MAXFRAGS, MCLBYTES, 0, 1511 &sc->xl_mtag); 1512 if (error) { 1513 device_printf(dev, "failed to allocate mbuf dma tag\n"); 1514 goto fail; 1515 } 1516 1517 bzero(sc->xl_ldata.xl_tx_list, XL_TX_LIST_SZ); 1518 bzero(sc->xl_ldata.xl_rx_list, XL_RX_LIST_SZ); 1519 1520 /* We need a spare DMA map for the RX ring. */ 1521 error = bus_dmamap_create(sc->xl_mtag, 0, &sc->xl_tmpmap); 1522 if (error) 1523 goto fail; 1524 1525 /* 1526 * Figure out the card type. 3c905B adapters have the 1527 * 'supportsNoTxLength' bit set in the capabilities 1528 * word in the EEPROM. 1529 * Note: my 3c575C cardbus card lies. It returns a value 1530 * of 0x1578 for its capabilities word, which is somewhat 1531 * nonsensical. Another way to distinguish a 3c90x chip 1532 * from a 3c90xB/C chip is to check for the 'supportsLargePackets' 1533 * bit. This will only be set for 3c90x boomerage chips. 1534 */ 1535 xl_read_eeprom(sc, (caddr_t)&sc->xl_caps, XL_EE_CAPS, 1, 0); 1536 if (sc->xl_caps & XL_CAPS_NO_TXLENGTH || 1537 !(sc->xl_caps & XL_CAPS_LARGE_PKTS)) 1538 sc->xl_type = XL_TYPE_905B; 1539 else 1540 sc->xl_type = XL_TYPE_90X; 1541 1542 ifp->if_softc = sc; 1543 ifp->if_mtu = ETHERMTU; 1544 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1545 ifp->if_ioctl = xl_ioctl; 1546 ifp->if_capabilities = 0; 1547 if (sc->xl_type == XL_TYPE_905B) { 1548 ifp->if_start = xl_start_90xB; 1549 ifp->if_capabilities |= IFCAP_HWCSUM; 1550 } else { 1551 ifp->if_start = xl_start; 1552 } 1553 ifp->if_watchdog = xl_watchdog; 1554 ifp->if_init = xl_init; 1555 ifp->if_baudrate = 10000000; 1556 ifq_set_maxlen(&ifp->if_snd, XL_TX_LIST_CNT - 1); 1557 ifq_set_ready(&ifp->if_snd); 1558 /* 1559 * NOTE: features disabled by default. This seems to corrupt 1560 * tx packet data one out of a million packets or so and then 1561 * generates a good checksum so the receiver doesn't 1562 * know the packet is bad 1563 */ 1564 ifp->if_capenable = 0; /*ifp->if_capabilities;*/ 1565 if (ifp->if_capenable & IFCAP_TXCSUM) 1566 ifp->if_hwassist = XL905B_CSUM_FEATURES; 1567 1568 /* 1569 * Now we have to see what sort of media we have. 1570 * This includes probing for an MII interace and a 1571 * possible PHY. 1572 */ 1573 XL_SEL_WIN(3); 1574 sc->xl_media = CSR_READ_2(sc, XL_W3_MEDIA_OPT); 1575 if (bootverbose) 1576 if_printf(ifp, "media options word: %x\n", sc->xl_media); 1577 1578 xl_read_eeprom(sc, (char *)&xcvr, XL_EE_ICFG_0, 2, 0); 1579 sc->xl_xcvr = xcvr[0] | xcvr[1] << 16; 1580 sc->xl_xcvr &= XL_ICFG_CONNECTOR_MASK; 1581 sc->xl_xcvr >>= XL_ICFG_CONNECTOR_BITS; 1582 1583 xl_mediacheck(sc); 1584 1585 if (sc->xl_media & XL_MEDIAOPT_MII || sc->xl_media & XL_MEDIAOPT_BTX 1586 || sc->xl_media & XL_MEDIAOPT_BT4) { 1587 if (bootverbose) 1588 if_printf(ifp, "found MII/AUTO\n"); 1589 xl_setcfg(sc); 1590 if (mii_phy_probe(dev, &sc->xl_miibus, 1591 xl_ifmedia_upd, xl_ifmedia_sts)) { 1592 if_printf(ifp, "no PHY found!\n"); 1593 error = ENXIO; 1594 goto fail; 1595 } 1596 1597 goto done; 1598 } 1599 1600 /* 1601 * Sanity check. If the user has selected "auto" and this isn't 1602 * a 10/100 card of some kind, we need to force the transceiver 1603 * type to something sane. 1604 */ 1605 if (sc->xl_xcvr == XL_XCVR_AUTO) 1606 xl_choose_xcvr(sc, bootverbose); 1607 1608 /* 1609 * Do ifmedia setup. 1610 */ 1611 if (sc->xl_media & XL_MEDIAOPT_BT) { 1612 if (bootverbose) 1613 if_printf(ifp, "found 10baseT\n"); 1614 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL); 1615 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T|IFM_HDX, 0, NULL); 1616 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX) 1617 ifmedia_add(&sc->ifmedia, 1618 IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL); 1619 } 1620 1621 if (sc->xl_media & (XL_MEDIAOPT_AUI|XL_MEDIAOPT_10FL)) { 1622 /* 1623 * Check for a 10baseFL board in disguise. 1624 */ 1625 if (sc->xl_type == XL_TYPE_905B && 1626 sc->xl_media == XL_MEDIAOPT_10FL) { 1627 if (bootverbose) 1628 if_printf(ifp, "found 10baseFL\n"); 1629 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_FL, 0, NULL); 1630 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_FL|IFM_HDX, 1631 0, NULL); 1632 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX) 1633 ifmedia_add(&sc->ifmedia, 1634 IFM_ETHER|IFM_10_FL|IFM_FDX, 0, NULL); 1635 } else { 1636 if (bootverbose) 1637 if_printf(ifp, "found AUI\n"); 1638 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_5, 0, NULL); 1639 } 1640 } 1641 1642 if (sc->xl_media & XL_MEDIAOPT_BNC) { 1643 if (bootverbose) 1644 if_printf(ifp, "found BNC\n"); 1645 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_2, 0, NULL); 1646 } 1647 1648 if (sc->xl_media & XL_MEDIAOPT_BFX) { 1649 if (bootverbose) 1650 if_printf(ifp, "found 100baseFX\n"); 1651 ifp->if_baudrate = 100000000; 1652 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_FX, 0, NULL); 1653 } 1654 1655 /* Choose a default media. */ 1656 switch(sc->xl_xcvr) { 1657 case XL_XCVR_10BT: 1658 media = IFM_ETHER|IFM_10_T; 1659 xl_setmode(sc, media); 1660 break; 1661 case XL_XCVR_AUI: 1662 if (sc->xl_type == XL_TYPE_905B && 1663 sc->xl_media == XL_MEDIAOPT_10FL) { 1664 media = IFM_ETHER|IFM_10_FL; 1665 xl_setmode(sc, media); 1666 } else { 1667 media = IFM_ETHER|IFM_10_5; 1668 xl_setmode(sc, media); 1669 } 1670 break; 1671 case XL_XCVR_COAX: 1672 media = IFM_ETHER|IFM_10_2; 1673 xl_setmode(sc, media); 1674 break; 1675 case XL_XCVR_AUTO: 1676 case XL_XCVR_100BTX: 1677 case XL_XCVR_MII: 1678 /* Chosen by miibus */ 1679 break; 1680 case XL_XCVR_100BFX: 1681 media = IFM_ETHER|IFM_100_FX; 1682 break; 1683 default: 1684 if_printf(ifp, "unknown XCVR type: %d\n", sc->xl_xcvr); 1685 /* 1686 * This will probably be wrong, but it prevents 1687 * the ifmedia code from panicking. 1688 */ 1689 media = IFM_ETHER|IFM_10_T; 1690 break; 1691 } 1692 1693 if (sc->xl_miibus == NULL) 1694 ifmedia_set(&sc->ifmedia, media); 1695 1696 done: 1697 1698 if (sc->xl_flags & XL_FLAG_NO_XCVR_PWR) { 1699 XL_SEL_WIN(0); 1700 CSR_WRITE_2(sc, XL_W0_MFG_ID, XL_NO_XCVR_PWR_MAGICBITS); 1701 } 1702 1703 /* 1704 * Call MI attach routine. 1705 */ 1706 ether_ifattach(ifp, eaddr); 1707 1708 /* 1709 * Tell the upper layer(s) we support long frames. 1710 */ 1711 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1712 1713 /* Hook interrupt last to avoid having to lock softc */ 1714 error = bus_setup_intr(dev, sc->xl_irq, INTR_TYPE_NET, 1715 xl_intr, sc, &sc->xl_intrhand, NULL); 1716 if (error) { 1717 if_printf(ifp, "couldn't set up irq\n"); 1718 ether_ifdetach(ifp); 1719 goto fail; 1720 } 1721 1722 fail: 1723 if (error) 1724 xl_detach(dev); 1725 1726 return(error); 1727 } 1728 1729 /* 1730 * Shutdown hardware and free up resources. This can be called any 1731 * time after the mutex has been initialized. It is called in both 1732 * the error case in attach and the normal detach case so it needs 1733 * to be careful about only freeing resources that have actually been 1734 * allocated. 1735 */ 1736 static int 1737 xl_detach(dev) 1738 device_t dev; 1739 { 1740 struct xl_softc *sc; 1741 struct ifnet *ifp; 1742 int rid, res; 1743 1744 sc = device_get_softc(dev); 1745 ifp = &sc->arpcom.ac_if; 1746 1747 if (sc->xl_flags & XL_FLAG_USE_MMIO) { 1748 rid = XL_PCI_LOMEM; 1749 res = SYS_RES_MEMORY; 1750 } else { 1751 rid = XL_PCI_LOIO; 1752 res = SYS_RES_IOPORT; 1753 } 1754 1755 crit_enter(); 1756 1757 /* 1758 * Only try to communicate with the device if we were able to map 1759 * the ports. This flag is set before ether_ifattach() so it also 1760 * governs our call to ether_ifdetach(). 1761 */ 1762 if (sc->xl_flags & XL_FLAG_ATTACH_MAPPED) { 1763 xl_reset(sc); 1764 xl_stop(sc); 1765 ether_ifdetach(ifp); 1766 } 1767 1768 if (sc->xl_miibus) 1769 device_delete_child(dev, sc->xl_miibus); 1770 bus_generic_detach(dev); 1771 ifmedia_removeall(&sc->ifmedia); 1772 1773 if (sc->xl_intrhand) 1774 bus_teardown_intr(dev, sc->xl_irq, sc->xl_intrhand); 1775 1776 crit_exit(); 1777 1778 if (sc->xl_irq) 1779 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->xl_irq); 1780 if (sc->xl_fres != NULL) 1781 bus_release_resource(dev, SYS_RES_MEMORY, 1782 XL_PCI_FUNCMEM, sc->xl_fres); 1783 if (sc->xl_res) 1784 bus_release_resource(dev, res, rid, sc->xl_res); 1785 1786 if (sc->xl_mtag) { 1787 bus_dmamap_destroy(sc->xl_mtag, sc->xl_tmpmap); 1788 bus_dma_tag_destroy(sc->xl_mtag); 1789 } 1790 if (sc->xl_ldata.xl_rx_tag) { 1791 bus_dmamap_unload(sc->xl_ldata.xl_rx_tag, 1792 sc->xl_ldata.xl_rx_dmamap); 1793 bus_dmamem_free(sc->xl_ldata.xl_rx_tag, sc->xl_ldata.xl_rx_list, 1794 sc->xl_ldata.xl_rx_dmamap); 1795 bus_dma_tag_destroy(sc->xl_ldata.xl_rx_tag); 1796 } 1797 if (sc->xl_ldata.xl_tx_tag) { 1798 bus_dmamap_unload(sc->xl_ldata.xl_tx_tag, 1799 sc->xl_ldata.xl_tx_dmamap); 1800 bus_dmamem_free(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_list, 1801 sc->xl_ldata.xl_tx_dmamap); 1802 bus_dma_tag_destroy(sc->xl_ldata.xl_tx_tag); 1803 } 1804 1805 return(0); 1806 } 1807 1808 /* 1809 * Initialize the transmit descriptors. 1810 */ 1811 static int 1812 xl_list_tx_init(sc) 1813 struct xl_softc *sc; 1814 { 1815 struct xl_chain_data *cd; 1816 struct xl_list_data *ld; 1817 int error, i; 1818 1819 cd = &sc->xl_cdata; 1820 ld = &sc->xl_ldata; 1821 for (i = 0; i < XL_TX_LIST_CNT; i++) { 1822 cd->xl_tx_chain[i].xl_ptr = &ld->xl_tx_list[i]; 1823 error = bus_dmamap_create(sc->xl_mtag, 0, 1824 &cd->xl_tx_chain[i].xl_map); 1825 if (error) 1826 return(error); 1827 cd->xl_tx_chain[i].xl_phys = ld->xl_tx_dmaaddr + 1828 i * sizeof(struct xl_list); 1829 if (i == (XL_TX_LIST_CNT - 1)) 1830 cd->xl_tx_chain[i].xl_next = NULL; 1831 else 1832 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[i + 1]; 1833 } 1834 1835 cd->xl_tx_free = &cd->xl_tx_chain[0]; 1836 cd->xl_tx_tail = cd->xl_tx_head = NULL; 1837 1838 bus_dmamap_sync(ld->xl_tx_tag, ld->xl_tx_dmamap, BUS_DMASYNC_PREWRITE); 1839 return(0); 1840 } 1841 1842 /* 1843 * Initialize the transmit descriptors. 1844 */ 1845 static int 1846 xl_list_tx_init_90xB(sc) 1847 struct xl_softc *sc; 1848 { 1849 struct xl_chain_data *cd; 1850 struct xl_list_data *ld; 1851 int error, i; 1852 1853 cd = &sc->xl_cdata; 1854 ld = &sc->xl_ldata; 1855 for (i = 0; i < XL_TX_LIST_CNT; i++) { 1856 cd->xl_tx_chain[i].xl_ptr = &ld->xl_tx_list[i]; 1857 error = bus_dmamap_create(sc->xl_mtag, 0, 1858 &cd->xl_tx_chain[i].xl_map); 1859 if (error) 1860 return(error); 1861 cd->xl_tx_chain[i].xl_phys = ld->xl_tx_dmaaddr + 1862 i * sizeof(struct xl_list); 1863 if (i == (XL_TX_LIST_CNT - 1)) 1864 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[0]; 1865 else 1866 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[i + 1]; 1867 if (i == 0) 1868 cd->xl_tx_chain[i].xl_prev = 1869 &cd->xl_tx_chain[XL_TX_LIST_CNT - 1]; 1870 else 1871 cd->xl_tx_chain[i].xl_prev = 1872 &cd->xl_tx_chain[i - 1]; 1873 } 1874 1875 bzero(ld->xl_tx_list, XL_TX_LIST_SZ); 1876 ld->xl_tx_list[0].xl_status = htole32(XL_TXSTAT_EMPTY); 1877 1878 cd->xl_tx_prod = 1; 1879 cd->xl_tx_cons = 1; 1880 cd->xl_tx_cnt = 0; 1881 1882 bus_dmamap_sync(ld->xl_tx_tag, ld->xl_tx_dmamap, BUS_DMASYNC_PREWRITE); 1883 return(0); 1884 } 1885 1886 /* 1887 * Initialize the RX descriptors and allocate mbufs for them. Note that 1888 * we arrange the descriptors in a closed ring, so that the last descriptor 1889 * points back to the first. 1890 */ 1891 static int 1892 xl_list_rx_init(sc) 1893 struct xl_softc *sc; 1894 { 1895 struct xl_chain_data *cd; 1896 struct xl_list_data *ld; 1897 int error, i, next; 1898 u_int32_t nextptr; 1899 1900 cd = &sc->xl_cdata; 1901 ld = &sc->xl_ldata; 1902 1903 for (i = 0; i < XL_RX_LIST_CNT; i++) { 1904 cd->xl_rx_chain[i].xl_ptr = &ld->xl_rx_list[i]; 1905 error = bus_dmamap_create(sc->xl_mtag, 0, 1906 &cd->xl_rx_chain[i].xl_map); 1907 if (error) 1908 return(error); 1909 error = xl_newbuf(sc, &cd->xl_rx_chain[i]); 1910 if (error) 1911 return(error); 1912 if (i == (XL_RX_LIST_CNT - 1)) 1913 next = 0; 1914 else 1915 next = i + 1; 1916 nextptr = ld->xl_rx_dmaaddr + 1917 next * sizeof(struct xl_list_onefrag); 1918 cd->xl_rx_chain[i].xl_next = &cd->xl_rx_chain[next]; 1919 ld->xl_rx_list[i].xl_next = htole32(nextptr); 1920 } 1921 1922 bus_dmamap_sync(ld->xl_rx_tag, ld->xl_rx_dmamap, BUS_DMASYNC_PREWRITE); 1923 cd->xl_rx_head = &cd->xl_rx_chain[0]; 1924 1925 return(0); 1926 } 1927 1928 /* 1929 * Initialize an RX descriptor and attach an MBUF cluster. 1930 * If we fail to do so, we need to leave the old mbuf and 1931 * the old DMA map untouched so that it can be reused. 1932 */ 1933 static int 1934 xl_newbuf(sc, c) 1935 struct xl_softc *sc; 1936 struct xl_chain_onefrag *c; 1937 { 1938 struct mbuf *m_new = NULL; 1939 bus_dmamap_t map; 1940 int error; 1941 u_int32_t baddr; 1942 1943 m_new = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR); 1944 if (m_new == NULL) 1945 return(ENOBUFS); 1946 1947 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1948 1949 /* Force longword alignment for packet payload. */ 1950 m_adj(m_new, ETHER_ALIGN); 1951 1952 error = bus_dmamap_load_mbuf(sc->xl_mtag, sc->xl_tmpmap, m_new, 1953 xl_dma_map_rxbuf, &baddr, BUS_DMA_NOWAIT); 1954 if (error) { 1955 m_freem(m_new); 1956 if_printf(&sc->arpcom.ac_if, "can't map mbuf (error %d)\n", 1957 error); 1958 return(error); 1959 } 1960 1961 bus_dmamap_unload(sc->xl_mtag, c->xl_map); 1962 map = c->xl_map; 1963 c->xl_map = sc->xl_tmpmap; 1964 sc->xl_tmpmap = map; 1965 c->xl_mbuf = m_new; 1966 c->xl_ptr->xl_frag.xl_len = htole32(m_new->m_len | XL_LAST_FRAG); 1967 c->xl_ptr->xl_status = 0; 1968 c->xl_ptr->xl_frag.xl_addr = htole32(baddr); 1969 bus_dmamap_sync(sc->xl_mtag, c->xl_map, BUS_DMASYNC_PREREAD); 1970 return(0); 1971 } 1972 1973 static int 1974 xl_rx_resync(sc) 1975 struct xl_softc *sc; 1976 { 1977 struct xl_chain_onefrag *pos; 1978 int i; 1979 1980 pos = sc->xl_cdata.xl_rx_head; 1981 1982 for (i = 0; i < XL_RX_LIST_CNT; i++) { 1983 if (pos->xl_ptr->xl_status) 1984 break; 1985 pos = pos->xl_next; 1986 } 1987 1988 if (i == XL_RX_LIST_CNT) 1989 return(0); 1990 1991 sc->xl_cdata.xl_rx_head = pos; 1992 1993 return(EAGAIN); 1994 } 1995 1996 /* 1997 * A frame has been uploaded: pass the resulting mbuf chain up to 1998 * the higher level protocols. 1999 */ 2000 static void 2001 xl_rxeof(sc) 2002 struct xl_softc *sc; 2003 { 2004 struct mbuf *m; 2005 struct ifnet *ifp; 2006 struct xl_chain_onefrag *cur_rx; 2007 int total_len = 0; 2008 u_int32_t rxstat; 2009 2010 ifp = &sc->arpcom.ac_if; 2011 2012 again: 2013 2014 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag, sc->xl_ldata.xl_rx_dmamap, 2015 BUS_DMASYNC_POSTREAD); 2016 while((rxstat = le32toh(sc->xl_cdata.xl_rx_head->xl_ptr->xl_status))) { 2017 cur_rx = sc->xl_cdata.xl_rx_head; 2018 sc->xl_cdata.xl_rx_head = cur_rx->xl_next; 2019 total_len = rxstat & XL_RXSTAT_LENMASK; 2020 2021 /* 2022 * Since we have told the chip to allow large frames, 2023 * we need to trap giant frame errors in software. We allow 2024 * a little more than the normal frame size to account for 2025 * frames with VLAN tags. 2026 */ 2027 if (total_len > XL_MAX_FRAMELEN) 2028 rxstat |= (XL_RXSTAT_UP_ERROR|XL_RXSTAT_OVERSIZE); 2029 2030 /* 2031 * If an error occurs, update stats, clear the 2032 * status word and leave the mbuf cluster in place: 2033 * it should simply get re-used next time this descriptor 2034 * comes up in the ring. 2035 */ 2036 if (rxstat & XL_RXSTAT_UP_ERROR) { 2037 ifp->if_ierrors++; 2038 cur_rx->xl_ptr->xl_status = 0; 2039 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag, 2040 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE); 2041 continue; 2042 } 2043 2044 /* 2045 * If the error bit was not set, the upload complete 2046 * bit should be set which means we have a valid packet. 2047 * If not, something truly strange has happened. 2048 */ 2049 if (!(rxstat & XL_RXSTAT_UP_CMPLT)) { 2050 if_printf(ifp, 2051 "bad receive status -- packet dropped\n"); 2052 ifp->if_ierrors++; 2053 cur_rx->xl_ptr->xl_status = 0; 2054 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag, 2055 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE); 2056 continue; 2057 } 2058 2059 /* No errors; receive the packet. */ 2060 bus_dmamap_sync(sc->xl_mtag, cur_rx->xl_map, 2061 BUS_DMASYNC_POSTREAD); 2062 m = cur_rx->xl_mbuf; 2063 2064 /* 2065 * Try to conjure up a new mbuf cluster. If that 2066 * fails, it means we have an out of memory condition and 2067 * should leave the buffer in place and continue. This will 2068 * result in a lost packet, but there's little else we 2069 * can do in this situation. 2070 */ 2071 if (xl_newbuf(sc, cur_rx)) { 2072 ifp->if_ierrors++; 2073 cur_rx->xl_ptr->xl_status = 0; 2074 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag, 2075 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE); 2076 continue; 2077 } 2078 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag, 2079 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE); 2080 2081 ifp->if_ipackets++; 2082 m->m_pkthdr.rcvif = ifp; 2083 m->m_pkthdr.len = m->m_len = total_len; 2084 2085 if (ifp->if_capenable & IFCAP_RXCSUM) { 2086 /* Do IP checksum checking. */ 2087 if (rxstat & XL_RXSTAT_IPCKOK) 2088 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 2089 if (!(rxstat & XL_RXSTAT_IPCKERR)) 2090 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 2091 if ((rxstat & XL_RXSTAT_TCPCOK && 2092 !(rxstat & XL_RXSTAT_TCPCKERR)) || 2093 (rxstat & XL_RXSTAT_UDPCKOK && 2094 !(rxstat & XL_RXSTAT_UDPCKERR))) { 2095 m->m_pkthdr.csum_flags |= 2096 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 2097 m->m_pkthdr.csum_data = 0xffff; 2098 } 2099 } 2100 2101 (*ifp->if_input)(ifp, m); 2102 } 2103 2104 /* 2105 * Handle the 'end of channel' condition. When the upload 2106 * engine hits the end of the RX ring, it will stall. This 2107 * is our cue to flush the RX ring, reload the uplist pointer 2108 * register and unstall the engine. 2109 * XXX This is actually a little goofy. With the ThunderLAN 2110 * chip, you get an interrupt when the receiver hits the end 2111 * of the receive ring, which tells you exactly when you 2112 * you need to reload the ring pointer. Here we have to 2113 * fake it. I'm mad at myself for not being clever enough 2114 * to avoid the use of a goto here. 2115 */ 2116 if (CSR_READ_4(sc, XL_UPLIST_PTR) == 0 || 2117 CSR_READ_4(sc, XL_UPLIST_STATUS) & XL_PKTSTAT_UP_STALLED) { 2118 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_STALL); 2119 xl_wait(sc); 2120 CSR_WRITE_4(sc, XL_UPLIST_PTR, sc->xl_ldata.xl_rx_dmaaddr); 2121 sc->xl_cdata.xl_rx_head = &sc->xl_cdata.xl_rx_chain[0]; 2122 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_UNSTALL); 2123 goto again; 2124 } 2125 2126 return; 2127 } 2128 2129 /* 2130 * A frame was downloaded to the chip. It's safe for us to clean up 2131 * the list buffers. 2132 */ 2133 static void 2134 xl_txeof(sc) 2135 struct xl_softc *sc; 2136 { 2137 struct xl_chain *cur_tx; 2138 struct ifnet *ifp; 2139 2140 ifp = &sc->arpcom.ac_if; 2141 2142 /* Clear the timeout timer. */ 2143 ifp->if_timer = 0; 2144 2145 /* 2146 * Go through our tx list and free mbufs for those 2147 * frames that have been uploaded. Note: the 3c905B 2148 * sets a special bit in the status word to let us 2149 * know that a frame has been downloaded, but the 2150 * original 3c900/3c905 adapters don't do that. 2151 * Consequently, we have to use a different test if 2152 * xl_type != XL_TYPE_905B. 2153 */ 2154 while(sc->xl_cdata.xl_tx_head != NULL) { 2155 cur_tx = sc->xl_cdata.xl_tx_head; 2156 2157 if (CSR_READ_4(sc, XL_DOWNLIST_PTR)) 2158 break; 2159 2160 sc->xl_cdata.xl_tx_head = cur_tx->xl_next; 2161 bus_dmamap_sync(sc->xl_mtag, cur_tx->xl_map, 2162 BUS_DMASYNC_POSTWRITE); 2163 bus_dmamap_unload(sc->xl_mtag, cur_tx->xl_map); 2164 m_freem(cur_tx->xl_mbuf); 2165 cur_tx->xl_mbuf = NULL; 2166 ifp->if_opackets++; 2167 2168 cur_tx->xl_next = sc->xl_cdata.xl_tx_free; 2169 sc->xl_cdata.xl_tx_free = cur_tx; 2170 } 2171 2172 if (sc->xl_cdata.xl_tx_head == NULL) { 2173 ifp->if_flags &= ~IFF_OACTIVE; 2174 sc->xl_cdata.xl_tx_tail = NULL; 2175 } else { 2176 if (CSR_READ_4(sc, XL_DMACTL) & XL_DMACTL_DOWN_STALLED || 2177 !CSR_READ_4(sc, XL_DOWNLIST_PTR)) { 2178 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, 2179 sc->xl_cdata.xl_tx_head->xl_phys); 2180 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); 2181 } 2182 } 2183 2184 return; 2185 } 2186 2187 static void 2188 xl_txeof_90xB(sc) 2189 struct xl_softc *sc; 2190 { 2191 struct xl_chain *cur_tx = NULL; 2192 struct ifnet *ifp; 2193 int idx; 2194 2195 ifp = &sc->arpcom.ac_if; 2196 2197 bus_dmamap_sync(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_dmamap, 2198 BUS_DMASYNC_POSTREAD); 2199 idx = sc->xl_cdata.xl_tx_cons; 2200 while(idx != sc->xl_cdata.xl_tx_prod) { 2201 2202 cur_tx = &sc->xl_cdata.xl_tx_chain[idx]; 2203 2204 if (!(le32toh(cur_tx->xl_ptr->xl_status) & 2205 XL_TXSTAT_DL_COMPLETE)) 2206 break; 2207 2208 if (cur_tx->xl_mbuf != NULL) { 2209 bus_dmamap_sync(sc->xl_mtag, cur_tx->xl_map, 2210 BUS_DMASYNC_POSTWRITE); 2211 bus_dmamap_unload(sc->xl_mtag, cur_tx->xl_map); 2212 m_freem(cur_tx->xl_mbuf); 2213 cur_tx->xl_mbuf = NULL; 2214 } 2215 2216 ifp->if_opackets++; 2217 2218 sc->xl_cdata.xl_tx_cnt--; 2219 XL_INC(idx, XL_TX_LIST_CNT); 2220 ifp->if_timer = 0; 2221 } 2222 2223 sc->xl_cdata.xl_tx_cons = idx; 2224 2225 if (cur_tx != NULL) 2226 ifp->if_flags &= ~IFF_OACTIVE; 2227 2228 return; 2229 } 2230 2231 /* 2232 * TX 'end of channel' interrupt handler. Actually, we should 2233 * only get a 'TX complete' interrupt if there's a transmit error, 2234 * so this is really TX error handler. 2235 */ 2236 static void 2237 xl_txeoc(sc) 2238 struct xl_softc *sc; 2239 { 2240 struct ifnet *ifp = &sc->arpcom.ac_if; 2241 u_int8_t txstat; 2242 2243 while((txstat = CSR_READ_1(sc, XL_TX_STATUS))) { 2244 if (txstat & XL_TXSTATUS_UNDERRUN || 2245 txstat & XL_TXSTATUS_JABBER || 2246 txstat & XL_TXSTATUS_RECLAIM) { 2247 if_printf(ifp, "transmission error: %x\n", txstat); 2248 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); 2249 xl_wait(sc); 2250 if (sc->xl_type == XL_TYPE_905B) { 2251 if (sc->xl_cdata.xl_tx_cnt) { 2252 int i; 2253 struct xl_chain *c; 2254 i = sc->xl_cdata.xl_tx_cons; 2255 c = &sc->xl_cdata.xl_tx_chain[i]; 2256 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, 2257 c->xl_phys); 2258 CSR_WRITE_1(sc, XL_DOWN_POLL, 64); 2259 } 2260 } else { 2261 if (sc->xl_cdata.xl_tx_head != NULL) 2262 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, 2263 sc->xl_cdata.xl_tx_head->xl_phys); 2264 } 2265 /* 2266 * Remember to set this for the 2267 * first generation 3c90X chips. 2268 */ 2269 CSR_WRITE_1(sc, XL_TX_FREETHRESH, XL_PACKET_SIZE >> 8); 2270 if (txstat & XL_TXSTATUS_UNDERRUN && 2271 sc->xl_tx_thresh < XL_PACKET_SIZE) { 2272 sc->xl_tx_thresh += XL_MIN_FRAMELEN; 2273 if_printf(ifp, "tx underrun, increasing tx start" 2274 " threshold to %d bytes\n", 2275 sc->xl_tx_thresh); 2276 } 2277 CSR_WRITE_2(sc, XL_COMMAND, 2278 XL_CMD_TX_SET_START|sc->xl_tx_thresh); 2279 if (sc->xl_type == XL_TYPE_905B) { 2280 CSR_WRITE_2(sc, XL_COMMAND, 2281 XL_CMD_SET_TX_RECLAIM|(XL_PACKET_SIZE >> 4)); 2282 } 2283 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE); 2284 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); 2285 } else { 2286 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE); 2287 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); 2288 } 2289 /* 2290 * Write an arbitrary byte to the TX_STATUS register 2291 * to clear this interrupt/error and advance to the next. 2292 */ 2293 CSR_WRITE_1(sc, XL_TX_STATUS, 0x01); 2294 } 2295 2296 return; 2297 } 2298 2299 static void 2300 xl_intr(arg) 2301 void *arg; 2302 { 2303 struct xl_softc *sc; 2304 struct ifnet *ifp; 2305 u_int16_t status; 2306 2307 sc = arg; 2308 ifp = &sc->arpcom.ac_if; 2309 2310 while((status = CSR_READ_2(sc, XL_STATUS)) & XL_INTRS && status != 0xFFFF) { 2311 2312 CSR_WRITE_2(sc, XL_COMMAND, 2313 XL_CMD_INTR_ACK|(status & XL_INTRS)); 2314 2315 if (status & XL_STAT_UP_COMPLETE) { 2316 int curpkts; 2317 2318 curpkts = ifp->if_ipackets; 2319 xl_rxeof(sc); 2320 if (curpkts == ifp->if_ipackets) { 2321 while (xl_rx_resync(sc)) 2322 xl_rxeof(sc); 2323 } 2324 } 2325 2326 if (status & XL_STAT_DOWN_COMPLETE) { 2327 if (sc->xl_type == XL_TYPE_905B) 2328 xl_txeof_90xB(sc); 2329 else 2330 xl_txeof(sc); 2331 } 2332 2333 if (status & XL_STAT_TX_COMPLETE) { 2334 ifp->if_oerrors++; 2335 xl_txeoc(sc); 2336 } 2337 2338 if (status & XL_STAT_ADFAIL) { 2339 xl_reset(sc); 2340 xl_init(sc); 2341 } 2342 2343 if (status & XL_STAT_STATSOFLOW) { 2344 sc->xl_stats_no_timeout = 1; 2345 xl_stats_update(sc); 2346 sc->xl_stats_no_timeout = 0; 2347 } 2348 } 2349 2350 if (!ifq_is_empty(&ifp->if_snd)) 2351 (*ifp->if_start)(ifp); 2352 2353 return; 2354 } 2355 2356 static void 2357 xl_stats_update(xsc) 2358 void *xsc; 2359 { 2360 struct xl_softc *sc; 2361 struct ifnet *ifp; 2362 struct xl_stats xl_stats; 2363 u_int8_t *p; 2364 int i; 2365 struct mii_data *mii = NULL; 2366 2367 bzero((char *)&xl_stats, sizeof(struct xl_stats)); 2368 2369 sc = xsc; 2370 ifp = &sc->arpcom.ac_if; 2371 if (sc->xl_miibus != NULL) 2372 mii = device_get_softc(sc->xl_miibus); 2373 2374 p = (u_int8_t *)&xl_stats; 2375 2376 /* Read all the stats registers. */ 2377 XL_SEL_WIN(6); 2378 2379 for (i = 0; i < 16; i++) 2380 *p++ = CSR_READ_1(sc, XL_W6_CARRIER_LOST + i); 2381 2382 ifp->if_ierrors += xl_stats.xl_rx_overrun; 2383 2384 ifp->if_collisions += xl_stats.xl_tx_multi_collision + 2385 xl_stats.xl_tx_single_collision + 2386 xl_stats.xl_tx_late_collision; 2387 2388 /* 2389 * Boomerang and cyclone chips have an extra stats counter 2390 * in window 4 (BadSSD). We have to read this too in order 2391 * to clear out all the stats registers and avoid a statsoflow 2392 * interrupt. 2393 */ 2394 XL_SEL_WIN(4); 2395 CSR_READ_1(sc, XL_W4_BADSSD); 2396 2397 if ((mii != NULL) && (!sc->xl_stats_no_timeout)) 2398 mii_tick(mii); 2399 2400 XL_SEL_WIN(7); 2401 2402 if (!sc->xl_stats_no_timeout) 2403 callout_reset(&sc->xl_stat_timer, hz, xl_stats_update, sc); 2404 2405 return; 2406 } 2407 2408 /* 2409 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 2410 * pointers to the fragment pointers. 2411 */ 2412 static int 2413 xl_encap(sc, c, m_head) 2414 struct xl_softc *sc; 2415 struct xl_chain *c; 2416 struct mbuf *m_head; 2417 { 2418 int error; 2419 u_int32_t status; 2420 struct ifnet *ifp; 2421 2422 ifp = &sc->arpcom.ac_if; 2423 2424 /* 2425 * Start packing the mbufs in this chain into 2426 * the fragment pointers. Stop when we run out 2427 * of fragments or hit the end of the mbuf chain. 2428 */ 2429 error = bus_dmamap_load_mbuf(sc->xl_mtag, c->xl_map, m_head, 2430 xl_dma_map_txbuf, c->xl_ptr, BUS_DMA_NOWAIT); 2431 2432 if (error && error != EFBIG) { 2433 m_freem(m_head); 2434 if_printf(ifp, "can't map mbuf (error %d)\n", error); 2435 return(1); 2436 } 2437 2438 /* 2439 * Handle special case: we used up all 63 fragments, 2440 * but we have more mbufs left in the chain. Copy the 2441 * data into an mbuf cluster. Note that we don't 2442 * bother clearing the values in the other fragment 2443 * pointers/counters; it wouldn't gain us anything, 2444 * and would waste cycles. 2445 */ 2446 if (error) { 2447 struct mbuf *m_new; 2448 2449 m_new = m_defrag(m_head, MB_DONTWAIT); 2450 if (m_new == NULL) { 2451 m_freem(m_head); 2452 return(1); 2453 } else { 2454 m_head = m_new; 2455 } 2456 2457 error = bus_dmamap_load_mbuf(sc->xl_mtag, c->xl_map, 2458 m_head, xl_dma_map_txbuf, c->xl_ptr, BUS_DMA_NOWAIT); 2459 if (error) { 2460 m_freem(m_head); 2461 if_printf(ifp, "can't map mbuf (error %d)\n", error); 2462 return(1); 2463 } 2464 } 2465 2466 if (sc->xl_type == XL_TYPE_905B) { 2467 status = XL_TXSTAT_RND_DEFEAT; 2468 2469 if (m_head->m_pkthdr.csum_flags) { 2470 if (m_head->m_pkthdr.csum_flags & CSUM_IP) 2471 status |= XL_TXSTAT_IPCKSUM; 2472 if (m_head->m_pkthdr.csum_flags & CSUM_TCP) 2473 status |= XL_TXSTAT_TCPCKSUM; 2474 if (m_head->m_pkthdr.csum_flags & CSUM_UDP) 2475 status |= XL_TXSTAT_UDPCKSUM; 2476 } 2477 c->xl_ptr->xl_status = htole32(status); 2478 } 2479 2480 c->xl_mbuf = m_head; 2481 bus_dmamap_sync(sc->xl_mtag, c->xl_map, BUS_DMASYNC_PREWRITE); 2482 return(0); 2483 } 2484 2485 /* 2486 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 2487 * to the mbuf data regions directly in the transmit lists. We also save a 2488 * copy of the pointers since the transmit list fragment pointers are 2489 * physical addresses. 2490 */ 2491 static void 2492 xl_start(ifp) 2493 struct ifnet *ifp; 2494 { 2495 struct xl_softc *sc; 2496 struct mbuf *m_head = NULL; 2497 struct xl_chain *prev = NULL, *cur_tx = NULL, *start_tx; 2498 struct xl_chain *prev_tx; 2499 u_int32_t status; 2500 int error; 2501 2502 sc = ifp->if_softc; 2503 /* 2504 * Check for an available queue slot. If there are none, 2505 * punt. 2506 */ 2507 if (sc->xl_cdata.xl_tx_free == NULL) { 2508 xl_txeoc(sc); 2509 xl_txeof(sc); 2510 if (sc->xl_cdata.xl_tx_free == NULL) { 2511 ifp->if_flags |= IFF_OACTIVE; 2512 return; 2513 } 2514 } 2515 2516 start_tx = sc->xl_cdata.xl_tx_free; 2517 2518 while(sc->xl_cdata.xl_tx_free != NULL) { 2519 m_head = ifq_dequeue(&ifp->if_snd); 2520 if (m_head == NULL) 2521 break; 2522 2523 /* Pick a descriptor off the free list. */ 2524 prev_tx = cur_tx; 2525 cur_tx = sc->xl_cdata.xl_tx_free; 2526 2527 /* Pack the data into the descriptor. */ 2528 error = xl_encap(sc, cur_tx, m_head); 2529 if (error) { 2530 cur_tx = prev_tx; 2531 continue; 2532 } 2533 2534 sc->xl_cdata.xl_tx_free = cur_tx->xl_next; 2535 cur_tx->xl_next = NULL; 2536 2537 /* Chain it together. */ 2538 if (prev != NULL) { 2539 prev->xl_next = cur_tx; 2540 prev->xl_ptr->xl_next = htole32(cur_tx->xl_phys); 2541 } 2542 prev = cur_tx; 2543 2544 BPF_MTAP(ifp, cur_tx->xl_mbuf); 2545 } 2546 2547 /* 2548 * If there are no packets queued, bail. 2549 */ 2550 if (cur_tx == NULL) { 2551 return; 2552 } 2553 2554 /* 2555 * Place the request for the upload interrupt 2556 * in the last descriptor in the chain. This way, if 2557 * we're chaining several packets at once, we'll only 2558 * get an interupt once for the whole chain rather than 2559 * once for each packet. 2560 */ 2561 cur_tx->xl_ptr->xl_status = htole32(le32toh(cur_tx->xl_ptr->xl_status) | 2562 XL_TXSTAT_DL_INTR); 2563 bus_dmamap_sync(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_dmamap, 2564 BUS_DMASYNC_PREWRITE); 2565 2566 /* 2567 * Queue the packets. If the TX channel is clear, update 2568 * the downlist pointer register. 2569 */ 2570 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_STALL); 2571 xl_wait(sc); 2572 2573 if (sc->xl_cdata.xl_tx_head != NULL) { 2574 sc->xl_cdata.xl_tx_tail->xl_next = start_tx; 2575 sc->xl_cdata.xl_tx_tail->xl_ptr->xl_next = 2576 htole32(start_tx->xl_phys); 2577 status = sc->xl_cdata.xl_tx_tail->xl_ptr->xl_status; 2578 sc->xl_cdata.xl_tx_tail->xl_ptr->xl_status = 2579 htole32(le32toh(status) & ~XL_TXSTAT_DL_INTR); 2580 sc->xl_cdata.xl_tx_tail = cur_tx; 2581 } else { 2582 sc->xl_cdata.xl_tx_head = start_tx; 2583 sc->xl_cdata.xl_tx_tail = cur_tx; 2584 } 2585 if (!CSR_READ_4(sc, XL_DOWNLIST_PTR)) 2586 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, start_tx->xl_phys); 2587 2588 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); 2589 2590 XL_SEL_WIN(7); 2591 2592 /* 2593 * Set a timeout in case the chip goes out to lunch. 2594 */ 2595 ifp->if_timer = 5; 2596 2597 /* 2598 * XXX Under certain conditions, usually on slower machines 2599 * where interrupts may be dropped, it's possible for the 2600 * adapter to chew up all the buffers in the receive ring 2601 * and stall, without us being able to do anything about it. 2602 * To guard against this, we need to make a pass over the 2603 * RX queue to make sure there aren't any packets pending. 2604 * Doing it here means we can flush the receive ring at the 2605 * same time the chip is DMAing the transmit descriptors we 2606 * just gave it. 2607 * 2608 * 3Com goes to some lengths to emphasize the Parallel Tasking (tm) 2609 * nature of their chips in all their marketing literature; 2610 * we may as well take advantage of it. :) 2611 */ 2612 xl_rxeof(sc); 2613 2614 return; 2615 } 2616 2617 static void 2618 xl_start_90xB(ifp) 2619 struct ifnet *ifp; 2620 { 2621 struct xl_softc *sc; 2622 struct mbuf *m_head = NULL; 2623 struct xl_chain *prev = NULL, *cur_tx = NULL, *start_tx; 2624 struct xl_chain *prev_tx; 2625 int error, idx; 2626 2627 sc = ifp->if_softc; 2628 2629 if (ifp->if_flags & IFF_OACTIVE) { 2630 return; 2631 } 2632 2633 idx = sc->xl_cdata.xl_tx_prod; 2634 start_tx = &sc->xl_cdata.xl_tx_chain[idx]; 2635 2636 while (sc->xl_cdata.xl_tx_chain[idx].xl_mbuf == NULL) { 2637 2638 if ((XL_TX_LIST_CNT - sc->xl_cdata.xl_tx_cnt) < 3) { 2639 ifp->if_flags |= IFF_OACTIVE; 2640 break; 2641 } 2642 2643 m_head = ifq_dequeue(&ifp->if_snd); 2644 if (m_head == NULL) 2645 break; 2646 2647 prev_tx = cur_tx; 2648 cur_tx = &sc->xl_cdata.xl_tx_chain[idx]; 2649 2650 /* Pack the data into the descriptor. */ 2651 error = xl_encap(sc, cur_tx, m_head); 2652 if (error) { 2653 cur_tx = prev_tx; 2654 continue; 2655 } 2656 2657 /* Chain it together. */ 2658 if (prev != NULL) 2659 prev->xl_ptr->xl_next = htole32(cur_tx->xl_phys); 2660 prev = cur_tx; 2661 2662 BPF_MTAP(ifp, cur_tx->xl_mbuf); 2663 2664 XL_INC(idx, XL_TX_LIST_CNT); 2665 sc->xl_cdata.xl_tx_cnt++; 2666 } 2667 2668 /* 2669 * If there are no packets queued, bail. 2670 */ 2671 if (cur_tx == NULL) { 2672 return; 2673 } 2674 2675 /* 2676 * Place the request for the upload interrupt 2677 * in the last descriptor in the chain. This way, if 2678 * we're chaining several packets at once, we'll only 2679 * get an interupt once for the whole chain rather than 2680 * once for each packet. 2681 */ 2682 cur_tx->xl_ptr->xl_status = htole32(le32toh(cur_tx->xl_ptr->xl_status) | 2683 XL_TXSTAT_DL_INTR); 2684 bus_dmamap_sync(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_dmamap, 2685 BUS_DMASYNC_PREWRITE); 2686 2687 /* Start transmission */ 2688 sc->xl_cdata.xl_tx_prod = idx; 2689 start_tx->xl_prev->xl_ptr->xl_next = htole32(start_tx->xl_phys); 2690 2691 /* 2692 * Set a timeout in case the chip goes out to lunch. 2693 */ 2694 ifp->if_timer = 5; 2695 2696 return; 2697 } 2698 2699 static void 2700 xl_init(xsc) 2701 void *xsc; 2702 { 2703 struct xl_softc *sc = xsc; 2704 struct ifnet *ifp = &sc->arpcom.ac_if; 2705 int error, i; 2706 u_int16_t rxfilt = 0; 2707 struct mii_data *mii = NULL; 2708 2709 crit_enter(); 2710 2711 /* 2712 * Cancel pending I/O and free all RX/TX buffers. 2713 */ 2714 xl_stop(sc); 2715 2716 if (sc->xl_miibus == NULL) { 2717 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET); 2718 xl_wait(sc); 2719 } 2720 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); 2721 xl_wait(sc); 2722 DELAY(10000); 2723 2724 if (sc->xl_miibus != NULL) 2725 mii = device_get_softc(sc->xl_miibus); 2726 2727 /* Init our MAC address */ 2728 XL_SEL_WIN(2); 2729 for (i = 0; i < ETHER_ADDR_LEN; i++) { 2730 CSR_WRITE_1(sc, XL_W2_STATION_ADDR_LO + i, 2731 sc->arpcom.ac_enaddr[i]); 2732 } 2733 2734 /* Clear the station mask. */ 2735 for (i = 0; i < 3; i++) 2736 CSR_WRITE_2(sc, XL_W2_STATION_MASK_LO + (i * 2), 0); 2737 #ifdef notdef 2738 /* Reset TX and RX. */ 2739 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET); 2740 xl_wait(sc); 2741 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); 2742 xl_wait(sc); 2743 #endif 2744 /* Init circular RX list. */ 2745 error = xl_list_rx_init(sc); 2746 if (error) { 2747 if_printf(ifp, "initialization of the rx ring failed (%d)\n", 2748 error); 2749 xl_stop(sc); 2750 crit_exit(); 2751 return; 2752 } 2753 2754 /* Init TX descriptors. */ 2755 if (sc->xl_type == XL_TYPE_905B) 2756 error = xl_list_tx_init_90xB(sc); 2757 else 2758 error = xl_list_tx_init(sc); 2759 if (error) { 2760 if_printf(ifp, "initialization of the tx ring failed (%d)\n", 2761 error); 2762 xl_stop(sc); 2763 crit_exit(); 2764 return; 2765 } 2766 2767 /* 2768 * Set the TX freethresh value. 2769 * Note that this has no effect on 3c905B "cyclone" 2770 * cards but is required for 3c900/3c905 "boomerang" 2771 * cards in order to enable the download engine. 2772 */ 2773 CSR_WRITE_1(sc, XL_TX_FREETHRESH, XL_PACKET_SIZE >> 8); 2774 2775 /* Set the TX start threshold for best performance. */ 2776 sc->xl_tx_thresh = XL_MIN_FRAMELEN; 2777 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_SET_START|sc->xl_tx_thresh); 2778 2779 /* 2780 * If this is a 3c905B, also set the tx reclaim threshold. 2781 * This helps cut down on the number of tx reclaim errors 2782 * that could happen on a busy network. The chip multiplies 2783 * the register value by 16 to obtain the actual threshold 2784 * in bytes, so we divide by 16 when setting the value here. 2785 * The existing threshold value can be examined by reading 2786 * the register at offset 9 in window 5. 2787 */ 2788 if (sc->xl_type == XL_TYPE_905B) { 2789 CSR_WRITE_2(sc, XL_COMMAND, 2790 XL_CMD_SET_TX_RECLAIM|(XL_PACKET_SIZE >> 4)); 2791 } 2792 2793 /* Set RX filter bits. */ 2794 XL_SEL_WIN(5); 2795 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER); 2796 2797 /* Set the individual bit to receive frames for this host only. */ 2798 rxfilt |= XL_RXFILTER_INDIVIDUAL; 2799 2800 /* If we want promiscuous mode, set the allframes bit. */ 2801 if (ifp->if_flags & IFF_PROMISC) { 2802 rxfilt |= XL_RXFILTER_ALLFRAMES; 2803 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 2804 } else { 2805 rxfilt &= ~XL_RXFILTER_ALLFRAMES; 2806 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 2807 } 2808 2809 /* 2810 * Set capture broadcast bit to capture broadcast frames. 2811 */ 2812 if (ifp->if_flags & IFF_BROADCAST) { 2813 rxfilt |= XL_RXFILTER_BROADCAST; 2814 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 2815 } else { 2816 rxfilt &= ~XL_RXFILTER_BROADCAST; 2817 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 2818 } 2819 2820 /* 2821 * Program the multicast filter, if necessary. 2822 */ 2823 if (sc->xl_type == XL_TYPE_905B) 2824 xl_setmulti_hash(sc); 2825 else 2826 xl_setmulti(sc); 2827 2828 /* 2829 * Load the address of the RX list. We have to 2830 * stall the upload engine before we can manipulate 2831 * the uplist pointer register, then unstall it when 2832 * we're finished. We also have to wait for the 2833 * stall command to complete before proceeding. 2834 * Note that we have to do this after any RX resets 2835 * have completed since the uplist register is cleared 2836 * by a reset. 2837 */ 2838 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_STALL); 2839 xl_wait(sc); 2840 CSR_WRITE_4(sc, XL_UPLIST_PTR, sc->xl_ldata.xl_rx_dmaaddr); 2841 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_UNSTALL); 2842 xl_wait(sc); 2843 2844 2845 if (sc->xl_type == XL_TYPE_905B) { 2846 /* Set polling interval */ 2847 CSR_WRITE_1(sc, XL_DOWN_POLL, 64); 2848 /* Load the address of the TX list */ 2849 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_STALL); 2850 xl_wait(sc); 2851 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, 2852 sc->xl_cdata.xl_tx_chain[0].xl_phys); 2853 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); 2854 xl_wait(sc); 2855 } 2856 2857 /* 2858 * If the coax transceiver is on, make sure to enable 2859 * the DC-DC converter. 2860 */ 2861 XL_SEL_WIN(3); 2862 if (sc->xl_xcvr == XL_XCVR_COAX) 2863 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_START); 2864 else 2865 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP); 2866 2867 /* 2868 * increase packet size to allow reception of 802.1q or ISL packets. 2869 * For the 3c90x chip, set the 'allow large packets' bit in the MAC 2870 * control register. For 3c90xB/C chips, use the RX packet size 2871 * register. 2872 */ 2873 2874 if (sc->xl_type == XL_TYPE_905B) 2875 CSR_WRITE_2(sc, XL_W3_MAXPKTSIZE, XL_PACKET_SIZE); 2876 else { 2877 u_int8_t macctl; 2878 macctl = CSR_READ_1(sc, XL_W3_MAC_CTRL); 2879 macctl |= XL_MACCTRL_ALLOW_LARGE_PACK; 2880 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, macctl); 2881 } 2882 2883 /* Clear out the stats counters. */ 2884 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_DISABLE); 2885 sc->xl_stats_no_timeout = 1; 2886 xl_stats_update(sc); 2887 sc->xl_stats_no_timeout = 0; 2888 XL_SEL_WIN(4); 2889 CSR_WRITE_2(sc, XL_W4_NET_DIAG, XL_NETDIAG_UPPER_BYTES_ENABLE); 2890 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_ENABLE); 2891 2892 /* 2893 * Enable interrupts. 2894 */ 2895 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ACK|0xFF); 2896 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STAT_ENB|XL_INTRS); 2897 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|XL_INTRS); 2898 if (sc->xl_flags & XL_FLAG_FUNCREG) 2899 bus_space_write_4(sc->xl_ftag, sc->xl_fhandle, 4, 0x8000); 2900 2901 /* Set the RX early threshold */ 2902 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_THRESH|(XL_PACKET_SIZE >>2)); 2903 CSR_WRITE_2(sc, XL_DMACTL, XL_DMACTL_UP_RX_EARLY); 2904 2905 /* Enable receiver and transmitter. */ 2906 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE); 2907 xl_wait(sc); 2908 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_ENABLE); 2909 xl_wait(sc); 2910 2911 if (mii != NULL) 2912 mii_mediachg(mii); 2913 2914 /* Select window 7 for normal operations. */ 2915 XL_SEL_WIN(7); 2916 2917 ifp->if_flags |= IFF_RUNNING; 2918 ifp->if_flags &= ~IFF_OACTIVE; 2919 2920 callout_reset(&sc->xl_stat_timer, hz, xl_stats_update, sc); 2921 2922 crit_exit(); 2923 } 2924 2925 /* 2926 * Set media options. 2927 */ 2928 static int 2929 xl_ifmedia_upd(ifp) 2930 struct ifnet *ifp; 2931 { 2932 struct xl_softc *sc; 2933 struct ifmedia *ifm = NULL; 2934 struct mii_data *mii = NULL; 2935 2936 sc = ifp->if_softc; 2937 if (sc->xl_miibus != NULL) 2938 mii = device_get_softc(sc->xl_miibus); 2939 if (mii == NULL) 2940 ifm = &sc->ifmedia; 2941 else 2942 ifm = &mii->mii_media; 2943 2944 switch(IFM_SUBTYPE(ifm->ifm_media)) { 2945 case IFM_100_FX: 2946 case IFM_10_FL: 2947 case IFM_10_2: 2948 case IFM_10_5: 2949 xl_setmode(sc, ifm->ifm_media); 2950 return(0); 2951 break; 2952 default: 2953 break; 2954 } 2955 2956 if (sc->xl_media & XL_MEDIAOPT_MII || sc->xl_media & XL_MEDIAOPT_BTX 2957 || sc->xl_media & XL_MEDIAOPT_BT4) { 2958 xl_init(sc); 2959 } else { 2960 xl_setmode(sc, ifm->ifm_media); 2961 } 2962 2963 return(0); 2964 } 2965 2966 /* 2967 * Report current media status. 2968 */ 2969 static void 2970 xl_ifmedia_sts(ifp, ifmr) 2971 struct ifnet *ifp; 2972 struct ifmediareq *ifmr; 2973 { 2974 struct xl_softc *sc; 2975 u_int32_t icfg; 2976 struct mii_data *mii = NULL; 2977 2978 sc = ifp->if_softc; 2979 if (sc->xl_miibus != NULL) 2980 mii = device_get_softc(sc->xl_miibus); 2981 2982 XL_SEL_WIN(3); 2983 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG) & XL_ICFG_CONNECTOR_MASK; 2984 icfg >>= XL_ICFG_CONNECTOR_BITS; 2985 2986 ifmr->ifm_active = IFM_ETHER; 2987 2988 switch(icfg) { 2989 case XL_XCVR_10BT: 2990 ifmr->ifm_active = IFM_ETHER|IFM_10_T; 2991 if (CSR_READ_1(sc, XL_W3_MAC_CTRL) & XL_MACCTRL_DUPLEX) 2992 ifmr->ifm_active |= IFM_FDX; 2993 else 2994 ifmr->ifm_active |= IFM_HDX; 2995 break; 2996 case XL_XCVR_AUI: 2997 if (sc->xl_type == XL_TYPE_905B && 2998 sc->xl_media == XL_MEDIAOPT_10FL) { 2999 ifmr->ifm_active = IFM_ETHER|IFM_10_FL; 3000 if (CSR_READ_1(sc, XL_W3_MAC_CTRL) & XL_MACCTRL_DUPLEX) 3001 ifmr->ifm_active |= IFM_FDX; 3002 else 3003 ifmr->ifm_active |= IFM_HDX; 3004 } else 3005 ifmr->ifm_active = IFM_ETHER|IFM_10_5; 3006 break; 3007 case XL_XCVR_COAX: 3008 ifmr->ifm_active = IFM_ETHER|IFM_10_2; 3009 break; 3010 /* 3011 * XXX MII and BTX/AUTO should be separate cases. 3012 */ 3013 3014 case XL_XCVR_100BTX: 3015 case XL_XCVR_AUTO: 3016 case XL_XCVR_MII: 3017 if (mii != NULL) { 3018 mii_pollstat(mii); 3019 ifmr->ifm_active = mii->mii_media_active; 3020 ifmr->ifm_status = mii->mii_media_status; 3021 } 3022 break; 3023 case XL_XCVR_100BFX: 3024 ifmr->ifm_active = IFM_ETHER|IFM_100_FX; 3025 break; 3026 default: 3027 if_printf(ifp, "unknown XCVR type: %d\n", icfg); 3028 break; 3029 } 3030 3031 return; 3032 } 3033 3034 static int 3035 xl_ioctl(ifp, command, data, cr) 3036 struct ifnet *ifp; 3037 u_long command; 3038 caddr_t data; 3039 struct ucred *cr; 3040 { 3041 struct xl_softc *sc = ifp->if_softc; 3042 struct ifreq *ifr = (struct ifreq *) data; 3043 int error = 0; 3044 struct mii_data *mii = NULL; 3045 u_int8_t rxfilt; 3046 3047 crit_enter(); 3048 3049 switch(command) { 3050 case SIOCSIFFLAGS: 3051 XL_SEL_WIN(5); 3052 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER); 3053 if (ifp->if_flags & IFF_UP) { 3054 if (ifp->if_flags & IFF_RUNNING && 3055 ifp->if_flags & IFF_PROMISC && 3056 !(sc->xl_if_flags & IFF_PROMISC)) { 3057 rxfilt |= XL_RXFILTER_ALLFRAMES; 3058 CSR_WRITE_2(sc, XL_COMMAND, 3059 XL_CMD_RX_SET_FILT|rxfilt); 3060 XL_SEL_WIN(7); 3061 } else if (ifp->if_flags & IFF_RUNNING && 3062 !(ifp->if_flags & IFF_PROMISC) && 3063 sc->xl_if_flags & IFF_PROMISC) { 3064 rxfilt &= ~XL_RXFILTER_ALLFRAMES; 3065 CSR_WRITE_2(sc, XL_COMMAND, 3066 XL_CMD_RX_SET_FILT|rxfilt); 3067 XL_SEL_WIN(7); 3068 } else 3069 xl_init(sc); 3070 } else { 3071 if (ifp->if_flags & IFF_RUNNING) 3072 xl_stop(sc); 3073 } 3074 sc->xl_if_flags = ifp->if_flags; 3075 error = 0; 3076 break; 3077 case SIOCADDMULTI: 3078 case SIOCDELMULTI: 3079 if (sc->xl_type == XL_TYPE_905B) 3080 xl_setmulti_hash(sc); 3081 else 3082 xl_setmulti(sc); 3083 error = 0; 3084 break; 3085 case SIOCGIFMEDIA: 3086 case SIOCSIFMEDIA: 3087 if (sc->xl_miibus != NULL) 3088 mii = device_get_softc(sc->xl_miibus); 3089 if (mii == NULL) 3090 error = ifmedia_ioctl(ifp, ifr, 3091 &sc->ifmedia, command); 3092 else 3093 error = ifmedia_ioctl(ifp, ifr, 3094 &mii->mii_media, command); 3095 break; 3096 case SIOCSIFCAP: 3097 ifp->if_capenable = ifr->ifr_reqcap; 3098 if (ifp->if_capenable & IFCAP_TXCSUM) 3099 ifp->if_hwassist = XL905B_CSUM_FEATURES; 3100 else 3101 ifp->if_hwassist = 0; 3102 break; 3103 default: 3104 error = ether_ioctl(ifp, command, data); 3105 break; 3106 } 3107 3108 crit_exit(); 3109 3110 return(error); 3111 } 3112 3113 static void 3114 xl_watchdog(ifp) 3115 struct ifnet *ifp; 3116 { 3117 struct xl_softc *sc; 3118 u_int16_t status = 0; 3119 3120 sc = ifp->if_softc; 3121 3122 ifp->if_oerrors++; 3123 XL_SEL_WIN(4); 3124 status = CSR_READ_2(sc, XL_W4_MEDIA_STATUS); 3125 if_printf(ifp, "watchdog timeout\n"); 3126 3127 if (status & XL_MEDIASTAT_CARRIER) 3128 if_printf(ifp, "no carrier - transceiver cable problem?\n"); 3129 xl_txeoc(sc); 3130 xl_txeof(sc); 3131 xl_rxeof(sc); 3132 xl_reset(sc); 3133 xl_init(sc); 3134 3135 if (!ifq_is_empty(&ifp->if_snd)) 3136 (*ifp->if_start)(ifp); 3137 } 3138 3139 /* 3140 * Stop the adapter and free any mbufs allocated to the 3141 * RX and TX lists. 3142 */ 3143 static void 3144 xl_stop(sc) 3145 struct xl_softc *sc; 3146 { 3147 int i; 3148 struct ifnet *ifp; 3149 3150 ifp = &sc->arpcom.ac_if; 3151 ifp->if_timer = 0; 3152 3153 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_DISABLE); 3154 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_DISABLE); 3155 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB); 3156 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_DISCARD); 3157 xl_wait(sc); 3158 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_DISABLE); 3159 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP); 3160 DELAY(800); 3161 3162 #ifdef foo 3163 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET); 3164 xl_wait(sc); 3165 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); 3166 xl_wait(sc); 3167 #endif 3168 3169 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ACK|XL_STAT_INTLATCH); 3170 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STAT_ENB|0); 3171 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|0); 3172 if (sc->xl_flags & XL_FLAG_FUNCREG) bus_space_write_4 (sc->xl_ftag, sc->xl_fhandle, 4, 0x8000); 3173 3174 /* Stop the stats updater. */ 3175 callout_stop(&sc->xl_stat_timer); 3176 3177 /* 3178 * Free data in the RX lists. 3179 */ 3180 for (i = 0; i < XL_RX_LIST_CNT; i++) { 3181 if (sc->xl_cdata.xl_rx_chain[i].xl_mbuf != NULL) { 3182 bus_dmamap_unload(sc->xl_mtag, 3183 sc->xl_cdata.xl_rx_chain[i].xl_map); 3184 bus_dmamap_destroy(sc->xl_mtag, 3185 sc->xl_cdata.xl_rx_chain[i].xl_map); 3186 m_freem(sc->xl_cdata.xl_rx_chain[i].xl_mbuf); 3187 sc->xl_cdata.xl_rx_chain[i].xl_mbuf = NULL; 3188 } 3189 } 3190 bzero(sc->xl_ldata.xl_rx_list, XL_RX_LIST_SZ); 3191 /* 3192 * Free the TX list buffers. 3193 */ 3194 for (i = 0; i < XL_TX_LIST_CNT; i++) { 3195 if (sc->xl_cdata.xl_tx_chain[i].xl_mbuf != NULL) { 3196 bus_dmamap_unload(sc->xl_mtag, 3197 sc->xl_cdata.xl_tx_chain[i].xl_map); 3198 bus_dmamap_destroy(sc->xl_mtag, 3199 sc->xl_cdata.xl_tx_chain[i].xl_map); 3200 m_freem(sc->xl_cdata.xl_tx_chain[i].xl_mbuf); 3201 sc->xl_cdata.xl_tx_chain[i].xl_mbuf = NULL; 3202 } 3203 } 3204 bzero(sc->xl_ldata.xl_tx_list, XL_TX_LIST_SZ); 3205 3206 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 3207 3208 return; 3209 } 3210 3211 /* 3212 * Stop all chip I/O so that the kernel's probe routines don't 3213 * get confused by errant DMAs when rebooting. 3214 */ 3215 static void 3216 xl_shutdown(dev) 3217 device_t dev; 3218 { 3219 struct xl_softc *sc; 3220 3221 sc = device_get_softc(dev); 3222 3223 xl_reset(sc); 3224 xl_stop(sc); 3225 3226 return; 3227 } 3228 3229 static int 3230 xl_suspend(dev) 3231 device_t dev; 3232 { 3233 struct xl_softc *sc = device_get_softc(dev); 3234 3235 crit_enter(); 3236 3237 xl_stop(sc); 3238 3239 crit_exit(); 3240 3241 return(0); 3242 } 3243 3244 static int 3245 xl_resume(dev) 3246 device_t dev; 3247 { 3248 struct xl_softc *sc; 3249 struct ifnet *ifp; 3250 3251 sc = device_get_softc(dev); 3252 ifp = &sc->arpcom.ac_if; 3253 3254 crit_enter(); 3255 3256 xl_reset(sc); 3257 if (ifp->if_flags & IFF_UP) 3258 xl_init(sc); 3259 3260 crit_exit(); 3261 3262 return(0); 3263 } 3264