1 /* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: src/sys/pci/if_xl.c,v 1.72.2.25 2003/02/05 22:03:58 mbr Exp $ 33 * $DragonFly: src/sys/dev/netif/xl/if_xl.c,v 1.3 2003/07/26 21:56:10 rob Exp $ 34 * 35 * $FreeBSD: src/sys/pci/if_xl.c,v 1.72.2.25 2003/02/05 22:03:58 mbr Exp $ 36 */ 37 38 /* 39 * 3Com 3c90x Etherlink XL PCI NIC driver 40 * 41 * Supports the 3Com "boomerang", "cyclone" and "hurricane" PCI 42 * bus-master chips (3c90x cards and embedded controllers) including 43 * the following: 44 * 45 * 3Com 3c900-TPO 10Mbps/RJ-45 46 * 3Com 3c900-COMBO 10Mbps/RJ-45,AUI,BNC 47 * 3Com 3c905-TX 10/100Mbps/RJ-45 48 * 3Com 3c905-T4 10/100Mbps/RJ-45 49 * 3Com 3c900B-TPO 10Mbps/RJ-45 50 * 3Com 3c900B-COMBO 10Mbps/RJ-45,AUI,BNC 51 * 3Com 3c900B-TPC 10Mbps/RJ-45,BNC 52 * 3Com 3c900B-FL 10Mbps/Fiber-optic 53 * 3Com 3c905B-COMBO 10/100Mbps/RJ-45,AUI,BNC 54 * 3Com 3c905B-TX 10/100Mbps/RJ-45 55 * 3Com 3c905B-FL/FX 10/100Mbps/Fiber-optic 56 * 3Com 3c905C-TX 10/100Mbps/RJ-45 (Tornado ASIC) 57 * 3Com 3c980-TX 10/100Mbps server adapter (Hurricane ASIC) 58 * 3Com 3c980C-TX 10/100Mbps server adapter (Tornado ASIC) 59 * 3Com 3cSOHO100-TX 10/100Mbps/RJ-45 (Hurricane ASIC) 60 * 3Com 3c450-TX 10/100Mbps/RJ-45 (Tornado ASIC) 61 * 3Com 3c555 10/100Mbps/RJ-45 (MiniPCI, Laptop Hurricane) 62 * 3Com 3c556 10/100Mbps/RJ-45 (MiniPCI, Hurricane ASIC) 63 * 3Com 3c556B 10/100Mbps/RJ-45 (MiniPCI, Hurricane ASIC) 64 * 3Com 3c575TX 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC) 65 * 3Com 3c575B 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC) 66 * 3Com 3c575C 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC) 67 * 3Com 3cxfem656 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC) 68 * 3Com 3cxfem656b 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC) 69 * 3Com 3cxfem656c 10/100Mbps/RJ-45 (Cardbus, Tornado ASIC) 70 * Dell Optiplex GX1 on-board 3c918 10/100Mbps/RJ-45 71 * Dell on-board 3c920 10/100Mbps/RJ-45 72 * Dell Precision on-board 3c905B 10/100Mbps/RJ-45 73 * Dell Latitude laptop docking station embedded 3c905-TX 74 * 75 * Written by Bill Paul <wpaul@ctr.columbia.edu> 76 * Electrical Engineering Department 77 * Columbia University, New York City 78 */ 79 80 /* 81 * The 3c90x series chips use a bus-master DMA interface for transfering 82 * packets to and from the controller chip. Some of the "vortex" cards 83 * (3c59x) also supported a bus master mode, however for those chips 84 * you could only DMA packets to/from a contiguous memory buffer. For 85 * transmission this would mean copying the contents of the queued mbuf 86 * chain into a an mbuf cluster and then DMAing the cluster. This extra 87 * copy would sort of defeat the purpose of the bus master support for 88 * any packet that doesn't fit into a single mbuf. 89 * 90 * By contrast, the 3c90x cards support a fragment-based bus master 91 * mode where mbuf chains can be encapsulated using TX descriptors. 92 * This is similar to other PCI chips such as the Texas Instruments 93 * ThunderLAN and the Intel 82557/82558. 94 * 95 * The "vortex" driver (if_vx.c) happens to work for the "boomerang" 96 * bus master chips because they maintain the old PIO interface for 97 * backwards compatibility, but starting with the 3c905B and the 98 * "cyclone" chips, the compatibility interface has been dropped. 99 * Since using bus master DMA is a big win, we use this driver to 100 * support the PCI "boomerang" chips even though they work with the 101 * "vortex" driver in order to obtain better performance. 102 * 103 * This driver is in the /sys/pci directory because it only supports 104 * PCI-based NICs. 105 */ 106 107 #include <sys/param.h> 108 #include <sys/systm.h> 109 #include <sys/sockio.h> 110 #include <sys/mbuf.h> 111 #include <sys/malloc.h> 112 #include <sys/kernel.h> 113 #include <sys/socket.h> 114 115 #include <net/if.h> 116 #include <net/if_arp.h> 117 #include <net/ethernet.h> 118 #include <net/if_dl.h> 119 #include <net/if_media.h> 120 121 #include <net/bpf.h> 122 123 #include <vm/vm.h> /* for vtophys */ 124 #include <vm/pmap.h> /* for vtophys */ 125 #include <machine/clock.h> /* for DELAY */ 126 #include <machine/bus_memio.h> 127 #include <machine/bus_pio.h> 128 #include <machine/bus.h> 129 #include <machine/resource.h> 130 #include <sys/bus.h> 131 #include <sys/rman.h> 132 133 #include <dev/mii/mii.h> 134 #include <dev/mii/miivar.h> 135 136 #include <pci/pcireg.h> 137 #include <pci/pcivar.h> 138 139 MODULE_DEPEND(xl, miibus, 1, 1, 1); 140 141 /* "controller miibus0" required. See GENERIC if you get errors here. */ 142 #include "miibus_if.h" 143 144 /* 145 * The following #define causes the code to use PIO to access the 146 * chip's registers instead of memory mapped mode. The reason PIO mode 147 * is on by default is that the Etherlink XL manual seems to indicate 148 * that only the newer revision chips (3c905B) support both PIO and 149 * memory mapped access. Since we want to be compatible with the older 150 * bus master chips, we use PIO here. If you comment this out, the 151 * driver will use memory mapped I/O, which may be faster but which 152 * might not work on some devices. 153 */ 154 #define XL_USEIOSPACE 155 156 #include <pci/if_xlreg.h> 157 158 #define XL905B_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 159 160 /* 161 * Various supported device vendors/types and their names. 162 */ 163 static struct xl_type xl_devs[] = { 164 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10BT, 165 "3Com 3c900-TPO Etherlink XL" }, 166 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10BT_COMBO, 167 "3Com 3c900-COMBO Etherlink XL" }, 168 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10_100BT, 169 "3Com 3c905-TX Fast Etherlink XL" }, 170 { TC_VENDORID, TC_DEVICEID_BOOMERANG_100BT4, 171 "3Com 3c905-T4 Fast Etherlink XL" }, 172 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT, 173 "3Com 3c900B-TPO Etherlink XL" }, 174 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT_COMBO, 175 "3Com 3c900B-COMBO Etherlink XL" }, 176 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT_TPC, 177 "3Com 3c900B-TPC Etherlink XL" }, 178 { TC_VENDORID, TC_DEVICEID_CYCLONE_10FL, 179 "3Com 3c900B-FL Etherlink XL" }, 180 { TC_VENDORID, TC_DEVICEID_HURRICANE_10_100BT, 181 "3Com 3c905B-TX Fast Etherlink XL" }, 182 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100BT4, 183 "3Com 3c905B-T4 Fast Etherlink XL" }, 184 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100FX, 185 "3Com 3c905B-FX/SC Fast Etherlink XL" }, 186 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100_COMBO, 187 "3Com 3c905B-COMBO Fast Etherlink XL" }, 188 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT, 189 "3Com 3c905C-TX Fast Etherlink XL" }, 190 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT_920B, 191 "3Com 3c920B-EMB Integrated Fast Etherlink XL" }, 192 { TC_VENDORID, TC_DEVICEID_HURRICANE_10_100BT_SERV, 193 "3Com 3c980 Fast Etherlink XL" }, 194 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT_SERV, 195 "3Com 3c980C Fast Etherlink XL" }, 196 { TC_VENDORID, TC_DEVICEID_HURRICANE_SOHO100TX, 197 "3Com 3cSOHO100-TX OfficeConnect" }, 198 { TC_VENDORID, TC_DEVICEID_TORNADO_HOMECONNECT, 199 "3Com 3c450-TX HomeConnect" }, 200 { TC_VENDORID, TC_DEVICEID_HURRICANE_555, 201 "3Com 3c555 Fast Etherlink XL" }, 202 { TC_VENDORID, TC_DEVICEID_HURRICANE_556, 203 "3Com 3c556 Fast Etherlink XL" }, 204 { TC_VENDORID, TC_DEVICEID_HURRICANE_556B, 205 "3Com 3c556B Fast Etherlink XL" }, 206 { TC_VENDORID, TC_DEVICEID_HURRICANE_575A, 207 "3Com 3c575TX Fast Etherlink XL" }, 208 { TC_VENDORID, TC_DEVICEID_HURRICANE_575B, 209 "3Com 3c575B Fast Etherlink XL" }, 210 { TC_VENDORID, TC_DEVICEID_HURRICANE_575C, 211 "3Com 3c575C Fast Etherlink XL" }, 212 { TC_VENDORID, TC_DEVICEID_HURRICANE_656, 213 "3Com 3c656 Fast Etherlink XL" }, 214 { TC_VENDORID, TC_DEVICEID_HURRICANE_656B, 215 "3Com 3c656B Fast Etherlink XL" }, 216 { TC_VENDORID, TC_DEVICEID_TORNADO_656C, 217 "3Com 3c656C Fast Etherlink XL" }, 218 { 0, 0, NULL } 219 }; 220 221 static int xl_probe (device_t); 222 static int xl_attach (device_t); 223 static int xl_detach (device_t); 224 225 static int xl_newbuf (struct xl_softc *, struct xl_chain_onefrag *); 226 static void xl_stats_update (void *); 227 static int xl_encap (struct xl_softc *, struct xl_chain *, 228 struct mbuf *); 229 static void xl_rxeof (struct xl_softc *); 230 static int xl_rx_resync (struct xl_softc *); 231 static void xl_txeof (struct xl_softc *); 232 static void xl_txeof_90xB (struct xl_softc *); 233 static void xl_txeoc (struct xl_softc *); 234 static void xl_intr (void *); 235 static void xl_start (struct ifnet *); 236 static void xl_start_90xB (struct ifnet *); 237 static int xl_ioctl (struct ifnet *, u_long, caddr_t); 238 static void xl_init (void *); 239 static void xl_stop (struct xl_softc *); 240 static void xl_watchdog (struct ifnet *); 241 static void xl_shutdown (device_t); 242 static int xl_suspend (device_t); 243 static int xl_resume (device_t); 244 245 static int xl_ifmedia_upd (struct ifnet *); 246 static void xl_ifmedia_sts (struct ifnet *, struct ifmediareq *); 247 248 static int xl_eeprom_wait (struct xl_softc *); 249 static int xl_read_eeprom (struct xl_softc *, caddr_t, int, int, int); 250 static void xl_mii_sync (struct xl_softc *); 251 static void xl_mii_send (struct xl_softc *, u_int32_t, int); 252 static int xl_mii_readreg (struct xl_softc *, struct xl_mii_frame *); 253 static int xl_mii_writereg (struct xl_softc *, struct xl_mii_frame *); 254 255 static void xl_setcfg (struct xl_softc *); 256 static void xl_setmode (struct xl_softc *, int); 257 static u_int8_t xl_calchash (caddr_t); 258 static void xl_setmulti (struct xl_softc *); 259 static void xl_setmulti_hash (struct xl_softc *); 260 static void xl_reset (struct xl_softc *); 261 static int xl_list_rx_init (struct xl_softc *); 262 static int xl_list_tx_init (struct xl_softc *); 263 static int xl_list_tx_init_90xB (struct xl_softc *); 264 static void xl_wait (struct xl_softc *); 265 static void xl_mediacheck (struct xl_softc *); 266 static void xl_choose_xcvr (struct xl_softc *, int); 267 #ifdef notdef 268 static void xl_testpacket (struct xl_softc *); 269 #endif 270 271 static int xl_miibus_readreg (device_t, int, int); 272 static int xl_miibus_writereg (device_t, int, int, int); 273 static void xl_miibus_statchg (device_t); 274 static void xl_miibus_mediainit (device_t); 275 276 #ifdef XL_USEIOSPACE 277 #define XL_RES SYS_RES_IOPORT 278 #define XL_RID XL_PCI_LOIO 279 #else 280 #define XL_RES SYS_RES_MEMORY 281 #define XL_RID XL_PCI_LOMEM 282 #endif 283 284 static device_method_t xl_methods[] = { 285 /* Device interface */ 286 DEVMETHOD(device_probe, xl_probe), 287 DEVMETHOD(device_attach, xl_attach), 288 DEVMETHOD(device_detach, xl_detach), 289 DEVMETHOD(device_shutdown, xl_shutdown), 290 DEVMETHOD(device_suspend, xl_suspend), 291 DEVMETHOD(device_resume, xl_resume), 292 293 /* bus interface */ 294 DEVMETHOD(bus_print_child, bus_generic_print_child), 295 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 296 297 /* MII interface */ 298 DEVMETHOD(miibus_readreg, xl_miibus_readreg), 299 DEVMETHOD(miibus_writereg, xl_miibus_writereg), 300 DEVMETHOD(miibus_statchg, xl_miibus_statchg), 301 DEVMETHOD(miibus_mediainit, xl_miibus_mediainit), 302 303 { 0, 0 } 304 }; 305 306 static driver_t xl_driver = { 307 "xl", 308 xl_methods, 309 sizeof(struct xl_softc) 310 }; 311 312 static devclass_t xl_devclass; 313 314 DRIVER_MODULE(if_xl, pci, xl_driver, xl_devclass, 0, 0); 315 DRIVER_MODULE(miibus, xl, miibus_driver, miibus_devclass, 0, 0); 316 317 /* 318 * Murphy's law says that it's possible the chip can wedge and 319 * the 'command in progress' bit may never clear. Hence, we wait 320 * only a finite amount of time to avoid getting caught in an 321 * infinite loop. Normally this delay routine would be a macro, 322 * but it isn't called during normal operation so we can afford 323 * to make it a function. 324 */ 325 static void 326 xl_wait(sc) 327 struct xl_softc *sc; 328 { 329 int i; 330 331 for (i = 0; i < XL_TIMEOUT; i++) { 332 if (!(CSR_READ_2(sc, XL_STATUS) & XL_STAT_CMDBUSY)) 333 break; 334 } 335 336 if (i == XL_TIMEOUT) 337 printf("xl%d: command never completed!\n", sc->xl_unit); 338 339 return; 340 } 341 342 /* 343 * MII access routines are provided for adapters with external 344 * PHYs (3c905-TX, 3c905-T4, 3c905B-T4) and those with built-in 345 * autoneg logic that's faked up to look like a PHY (3c905B-TX). 346 * Note: if you don't perform the MDIO operations just right, 347 * it's possible to end up with code that works correctly with 348 * some chips/CPUs/processor speeds/bus speeds/etc but not 349 * with others. 350 */ 351 #define MII_SET(x) \ 352 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, \ 353 CSR_READ_2(sc, XL_W4_PHY_MGMT) | x) 354 355 #define MII_CLR(x) \ 356 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, \ 357 CSR_READ_2(sc, XL_W4_PHY_MGMT) & ~x) 358 359 /* 360 * Sync the PHYs by setting data bit and strobing the clock 32 times. 361 */ 362 static void 363 xl_mii_sync(sc) 364 struct xl_softc *sc; 365 { 366 int i; 367 368 XL_SEL_WIN(4); 369 MII_SET(XL_MII_DIR|XL_MII_DATA); 370 371 for (i = 0; i < 32; i++) { 372 MII_SET(XL_MII_CLK); 373 DELAY(1); 374 MII_CLR(XL_MII_CLK); 375 DELAY(1); 376 } 377 378 return; 379 } 380 381 /* 382 * Clock a series of bits through the MII. 383 */ 384 static void 385 xl_mii_send(sc, bits, cnt) 386 struct xl_softc *sc; 387 u_int32_t bits; 388 int cnt; 389 { 390 int i; 391 392 XL_SEL_WIN(4); 393 MII_CLR(XL_MII_CLK); 394 395 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 396 if (bits & i) { 397 MII_SET(XL_MII_DATA); 398 } else { 399 MII_CLR(XL_MII_DATA); 400 } 401 DELAY(1); 402 MII_CLR(XL_MII_CLK); 403 DELAY(1); 404 MII_SET(XL_MII_CLK); 405 } 406 } 407 408 /* 409 * Read an PHY register through the MII. 410 */ 411 static int 412 xl_mii_readreg(sc, frame) 413 struct xl_softc *sc; 414 struct xl_mii_frame *frame; 415 416 { 417 int i, ack, s; 418 419 s = splimp(); 420 421 /* 422 * Set up frame for RX. 423 */ 424 frame->mii_stdelim = XL_MII_STARTDELIM; 425 frame->mii_opcode = XL_MII_READOP; 426 frame->mii_turnaround = 0; 427 frame->mii_data = 0; 428 429 /* 430 * Select register window 4. 431 */ 432 433 XL_SEL_WIN(4); 434 435 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, 0); 436 /* 437 * Turn on data xmit. 438 */ 439 MII_SET(XL_MII_DIR); 440 441 xl_mii_sync(sc); 442 443 /* 444 * Send command/address info. 445 */ 446 xl_mii_send(sc, frame->mii_stdelim, 2); 447 xl_mii_send(sc, frame->mii_opcode, 2); 448 xl_mii_send(sc, frame->mii_phyaddr, 5); 449 xl_mii_send(sc, frame->mii_regaddr, 5); 450 451 /* Idle bit */ 452 MII_CLR((XL_MII_CLK|XL_MII_DATA)); 453 DELAY(1); 454 MII_SET(XL_MII_CLK); 455 DELAY(1); 456 457 /* Turn off xmit. */ 458 MII_CLR(XL_MII_DIR); 459 460 /* Check for ack */ 461 MII_CLR(XL_MII_CLK); 462 DELAY(1); 463 ack = CSR_READ_2(sc, XL_W4_PHY_MGMT) & XL_MII_DATA; 464 MII_SET(XL_MII_CLK); 465 DELAY(1); 466 467 /* 468 * Now try reading data bits. If the ack failed, we still 469 * need to clock through 16 cycles to keep the PHY(s) in sync. 470 */ 471 if (ack) { 472 for(i = 0; i < 16; i++) { 473 MII_CLR(XL_MII_CLK); 474 DELAY(1); 475 MII_SET(XL_MII_CLK); 476 DELAY(1); 477 } 478 goto fail; 479 } 480 481 for (i = 0x8000; i; i >>= 1) { 482 MII_CLR(XL_MII_CLK); 483 DELAY(1); 484 if (!ack) { 485 if (CSR_READ_2(sc, XL_W4_PHY_MGMT) & XL_MII_DATA) 486 frame->mii_data |= i; 487 DELAY(1); 488 } 489 MII_SET(XL_MII_CLK); 490 DELAY(1); 491 } 492 493 fail: 494 495 MII_CLR(XL_MII_CLK); 496 DELAY(1); 497 MII_SET(XL_MII_CLK); 498 DELAY(1); 499 500 splx(s); 501 502 if (ack) 503 return(1); 504 return(0); 505 } 506 507 /* 508 * Write to a PHY register through the MII. 509 */ 510 static int 511 xl_mii_writereg(sc, frame) 512 struct xl_softc *sc; 513 struct xl_mii_frame *frame; 514 515 { 516 int s; 517 518 s = splimp(); 519 /* 520 * Set up frame for TX. 521 */ 522 523 frame->mii_stdelim = XL_MII_STARTDELIM; 524 frame->mii_opcode = XL_MII_WRITEOP; 525 frame->mii_turnaround = XL_MII_TURNAROUND; 526 527 /* 528 * Select the window 4. 529 */ 530 XL_SEL_WIN(4); 531 532 /* 533 * Turn on data output. 534 */ 535 MII_SET(XL_MII_DIR); 536 537 xl_mii_sync(sc); 538 539 xl_mii_send(sc, frame->mii_stdelim, 2); 540 xl_mii_send(sc, frame->mii_opcode, 2); 541 xl_mii_send(sc, frame->mii_phyaddr, 5); 542 xl_mii_send(sc, frame->mii_regaddr, 5); 543 xl_mii_send(sc, frame->mii_turnaround, 2); 544 xl_mii_send(sc, frame->mii_data, 16); 545 546 /* Idle bit. */ 547 MII_SET(XL_MII_CLK); 548 DELAY(1); 549 MII_CLR(XL_MII_CLK); 550 DELAY(1); 551 552 /* 553 * Turn off xmit. 554 */ 555 MII_CLR(XL_MII_DIR); 556 557 splx(s); 558 559 return(0); 560 } 561 562 static int 563 xl_miibus_readreg(dev, phy, reg) 564 device_t dev; 565 int phy, reg; 566 { 567 struct xl_softc *sc; 568 struct xl_mii_frame frame; 569 570 sc = device_get_softc(dev); 571 572 /* 573 * Pretend that PHYs are only available at MII address 24. 574 * This is to guard against problems with certain 3Com ASIC 575 * revisions that incorrectly map the internal transceiver 576 * control registers at all MII addresses. This can cause 577 * the miibus code to attach the same PHY several times over. 578 */ 579 if ((!(sc->xl_flags & XL_FLAG_PHYOK)) && phy != 24) 580 return(0); 581 582 bzero((char *)&frame, sizeof(frame)); 583 584 frame.mii_phyaddr = phy; 585 frame.mii_regaddr = reg; 586 xl_mii_readreg(sc, &frame); 587 588 return(frame.mii_data); 589 } 590 591 static int 592 xl_miibus_writereg(dev, phy, reg, data) 593 device_t dev; 594 int phy, reg, data; 595 { 596 struct xl_softc *sc; 597 struct xl_mii_frame frame; 598 599 sc = device_get_softc(dev); 600 601 if ((!(sc->xl_flags & XL_FLAG_PHYOK)) && phy != 24) 602 return(0); 603 604 bzero((char *)&frame, sizeof(frame)); 605 606 frame.mii_phyaddr = phy; 607 frame.mii_regaddr = reg; 608 frame.mii_data = data; 609 610 xl_mii_writereg(sc, &frame); 611 612 return(0); 613 } 614 615 static void 616 xl_miibus_statchg(dev) 617 device_t dev; 618 { 619 struct xl_softc *sc; 620 struct mii_data *mii; 621 622 623 sc = device_get_softc(dev); 624 mii = device_get_softc(sc->xl_miibus); 625 626 xl_setcfg(sc); 627 628 /* Set ASIC's duplex mode to match the PHY. */ 629 XL_SEL_WIN(3); 630 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) 631 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, XL_MACCTRL_DUPLEX); 632 else 633 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, 634 (CSR_READ_1(sc, XL_W3_MAC_CTRL) & ~XL_MACCTRL_DUPLEX)); 635 636 return; 637 } 638 639 /* 640 * Special support for the 3c905B-COMBO. This card has 10/100 support 641 * plus BNC and AUI ports. This means we will have both an miibus attached 642 * plus some non-MII media settings. In order to allow this, we have to 643 * add the extra media to the miibus's ifmedia struct, but we can't do 644 * that during xl_attach() because the miibus hasn't been attached yet. 645 * So instead, we wait until the miibus probe/attach is done, at which 646 * point we will get a callback telling is that it's safe to add our 647 * extra media. 648 */ 649 static void 650 xl_miibus_mediainit(dev) 651 device_t dev; 652 { 653 struct xl_softc *sc; 654 struct mii_data *mii; 655 struct ifmedia *ifm; 656 657 sc = device_get_softc(dev); 658 mii = device_get_softc(sc->xl_miibus); 659 ifm = &mii->mii_media; 660 661 if (sc->xl_media & (XL_MEDIAOPT_AUI|XL_MEDIAOPT_10FL)) { 662 /* 663 * Check for a 10baseFL board in disguise. 664 */ 665 if (sc->xl_type == XL_TYPE_905B && 666 sc->xl_media == XL_MEDIAOPT_10FL) { 667 if (bootverbose) 668 printf("xl%d: found 10baseFL\n", sc->xl_unit); 669 ifmedia_add(ifm, IFM_ETHER|IFM_10_FL, 0, NULL); 670 ifmedia_add(ifm, IFM_ETHER|IFM_10_FL|IFM_HDX, 0, NULL); 671 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX) 672 ifmedia_add(ifm, 673 IFM_ETHER|IFM_10_FL|IFM_FDX, 0, NULL); 674 } else { 675 if (bootverbose) 676 printf("xl%d: found AUI\n", sc->xl_unit); 677 ifmedia_add(ifm, IFM_ETHER|IFM_10_5, 0, NULL); 678 } 679 } 680 681 if (sc->xl_media & XL_MEDIAOPT_BNC) { 682 if (bootverbose) 683 printf("xl%d: found BNC\n", sc->xl_unit); 684 ifmedia_add(ifm, IFM_ETHER|IFM_10_2, 0, NULL); 685 } 686 687 return; 688 } 689 690 /* 691 * The EEPROM is slow: give it time to come ready after issuing 692 * it a command. 693 */ 694 static int 695 xl_eeprom_wait(sc) 696 struct xl_softc *sc; 697 { 698 int i; 699 700 for (i = 0; i < 100; i++) { 701 if (CSR_READ_2(sc, XL_W0_EE_CMD) & XL_EE_BUSY) 702 DELAY(162); 703 else 704 break; 705 } 706 707 if (i == 100) { 708 printf("xl%d: eeprom failed to come ready\n", sc->xl_unit); 709 return(1); 710 } 711 712 return(0); 713 } 714 715 /* 716 * Read a sequence of words from the EEPROM. Note that ethernet address 717 * data is stored in the EEPROM in network byte order. 718 */ 719 static int 720 xl_read_eeprom(sc, dest, off, cnt, swap) 721 struct xl_softc *sc; 722 caddr_t dest; 723 int off; 724 int cnt; 725 int swap; 726 { 727 int err = 0, i; 728 u_int16_t word = 0, *ptr; 729 #define EEPROM_5BIT_OFFSET(A) ((((A) << 2) & 0x7F00) | ((A) & 0x003F)) 730 #define EEPROM_8BIT_OFFSET(A) ((A) & 0x003F) 731 /* WARNING! DANGER! 732 * It's easy to accidentally overwrite the rom content! 733 * Note: the 3c575 uses 8bit EEPROM offsets. 734 */ 735 XL_SEL_WIN(0); 736 737 if (xl_eeprom_wait(sc)) 738 return(1); 739 740 if (sc->xl_flags & XL_FLAG_EEPROM_OFFSET_30) 741 off += 0x30; 742 743 for (i = 0; i < cnt; i++) { 744 if (sc->xl_flags & XL_FLAG_8BITROM) 745 CSR_WRITE_2(sc, XL_W0_EE_CMD, 746 XL_EE_8BIT_READ | EEPROM_8BIT_OFFSET(off + i)); 747 else 748 CSR_WRITE_2(sc, XL_W0_EE_CMD, 749 XL_EE_READ | EEPROM_5BIT_OFFSET(off + i)); 750 err = xl_eeprom_wait(sc); 751 if (err) 752 break; 753 word = CSR_READ_2(sc, XL_W0_EE_DATA); 754 ptr = (u_int16_t *)(dest + (i * 2)); 755 if (swap) 756 *ptr = ntohs(word); 757 else 758 *ptr = word; 759 } 760 761 return(err ? 1 : 0); 762 } 763 764 /* 765 * This routine is taken from the 3Com Etherlink XL manual, 766 * page 10-7. It calculates a CRC of the supplied multicast 767 * group address and returns the lower 8 bits, which are used 768 * as the multicast filter position. 769 * Note: the 3c905B currently only supports a 64-bit hash table, 770 * which means we really only need 6 bits, but the manual indicates 771 * that future chip revisions will have a 256-bit hash table, 772 * hence the routine is set up to calculate 8 bits of position 773 * info in case we need it some day. 774 * Note II, The Sequel: _CURRENT_ versions of the 3c905B have a 775 * 256 bit hash table. This means we have to use all 8 bits regardless. 776 * On older cards, the upper 2 bits will be ignored. Grrrr.... 777 */ 778 static u_int8_t xl_calchash(addr) 779 caddr_t addr; 780 { 781 u_int32_t crc, carry; 782 int i, j; 783 u_int8_t c; 784 785 /* Compute CRC for the address value. */ 786 crc = 0xFFFFFFFF; /* initial value */ 787 788 for (i = 0; i < 6; i++) { 789 c = *(addr + i); 790 for (j = 0; j < 8; j++) { 791 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 792 crc <<= 1; 793 c >>= 1; 794 if (carry) 795 crc = (crc ^ 0x04c11db6) | carry; 796 } 797 } 798 799 /* return the filter bit position */ 800 return(crc & 0x000000FF); 801 } 802 803 /* 804 * NICs older than the 3c905B have only one multicast option, which 805 * is to enable reception of all multicast frames. 806 */ 807 static void 808 xl_setmulti(sc) 809 struct xl_softc *sc; 810 { 811 struct ifnet *ifp; 812 struct ifmultiaddr *ifma; 813 u_int8_t rxfilt; 814 int mcnt = 0; 815 816 ifp = &sc->arpcom.ac_if; 817 818 XL_SEL_WIN(5); 819 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER); 820 821 if (ifp->if_flags & IFF_ALLMULTI) { 822 rxfilt |= XL_RXFILTER_ALLMULTI; 823 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 824 return; 825 } 826 827 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 828 ifma = ifma->ifma_link.le_next) 829 mcnt++; 830 831 if (mcnt) 832 rxfilt |= XL_RXFILTER_ALLMULTI; 833 else 834 rxfilt &= ~XL_RXFILTER_ALLMULTI; 835 836 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 837 838 return; 839 } 840 841 /* 842 * 3c905B adapters have a hash filter that we can program. 843 */ 844 static void 845 xl_setmulti_hash(sc) 846 struct xl_softc *sc; 847 { 848 struct ifnet *ifp; 849 int h = 0, i; 850 struct ifmultiaddr *ifma; 851 u_int8_t rxfilt; 852 int mcnt = 0; 853 854 ifp = &sc->arpcom.ac_if; 855 856 XL_SEL_WIN(5); 857 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER); 858 859 if (ifp->if_flags & IFF_ALLMULTI) { 860 rxfilt |= XL_RXFILTER_ALLMULTI; 861 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 862 return; 863 } else 864 rxfilt &= ~XL_RXFILTER_ALLMULTI; 865 866 867 /* first, zot all the existing hash bits */ 868 for (i = 0; i < XL_HASHFILT_SIZE; i++) 869 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_HASH|i); 870 871 /* now program new ones */ 872 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 873 ifma = ifma->ifma_link.le_next) { 874 if (ifma->ifma_addr->sa_family != AF_LINK) 875 continue; 876 h = xl_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 877 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_HASH|XL_HASH_SET|h); 878 mcnt++; 879 } 880 881 if (mcnt) 882 rxfilt |= XL_RXFILTER_MULTIHASH; 883 else 884 rxfilt &= ~XL_RXFILTER_MULTIHASH; 885 886 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 887 888 return; 889 } 890 891 #ifdef notdef 892 static void 893 xl_testpacket(sc) 894 struct xl_softc *sc; 895 { 896 struct mbuf *m; 897 struct ifnet *ifp; 898 899 ifp = &sc->arpcom.ac_if; 900 901 MGETHDR(m, M_DONTWAIT, MT_DATA); 902 903 if (m == NULL) 904 return; 905 906 bcopy(&sc->arpcom.ac_enaddr, 907 mtod(m, struct ether_header *)->ether_dhost, ETHER_ADDR_LEN); 908 bcopy(&sc->arpcom.ac_enaddr, 909 mtod(m, struct ether_header *)->ether_shost, ETHER_ADDR_LEN); 910 mtod(m, struct ether_header *)->ether_type = htons(3); 911 mtod(m, unsigned char *)[14] = 0; 912 mtod(m, unsigned char *)[15] = 0; 913 mtod(m, unsigned char *)[16] = 0xE3; 914 m->m_len = m->m_pkthdr.len = sizeof(struct ether_header) + 3; 915 IF_ENQUEUE(&ifp->if_snd, m); 916 xl_start(ifp); 917 918 return; 919 } 920 #endif 921 922 static void 923 xl_setcfg(sc) 924 struct xl_softc *sc; 925 { 926 u_int32_t icfg; 927 928 XL_SEL_WIN(3); 929 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG); 930 icfg &= ~XL_ICFG_CONNECTOR_MASK; 931 if (sc->xl_media & XL_MEDIAOPT_MII || 932 sc->xl_media & XL_MEDIAOPT_BT4) 933 icfg |= (XL_XCVR_MII << XL_ICFG_CONNECTOR_BITS); 934 if (sc->xl_media & XL_MEDIAOPT_BTX) 935 icfg |= (XL_XCVR_AUTO << XL_ICFG_CONNECTOR_BITS); 936 937 CSR_WRITE_4(sc, XL_W3_INTERNAL_CFG, icfg); 938 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP); 939 940 return; 941 } 942 943 static void 944 xl_setmode(sc, media) 945 struct xl_softc *sc; 946 int media; 947 { 948 u_int32_t icfg; 949 u_int16_t mediastat; 950 951 printf("xl%d: selecting ", sc->xl_unit); 952 953 XL_SEL_WIN(4); 954 mediastat = CSR_READ_2(sc, XL_W4_MEDIA_STATUS); 955 XL_SEL_WIN(3); 956 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG); 957 958 if (sc->xl_media & XL_MEDIAOPT_BT) { 959 if (IFM_SUBTYPE(media) == IFM_10_T) { 960 printf("10baseT transceiver, "); 961 sc->xl_xcvr = XL_XCVR_10BT; 962 icfg &= ~XL_ICFG_CONNECTOR_MASK; 963 icfg |= (XL_XCVR_10BT << XL_ICFG_CONNECTOR_BITS); 964 mediastat |= XL_MEDIASTAT_LINKBEAT| 965 XL_MEDIASTAT_JABGUARD; 966 mediastat &= ~XL_MEDIASTAT_SQEENB; 967 } 968 } 969 970 if (sc->xl_media & XL_MEDIAOPT_BFX) { 971 if (IFM_SUBTYPE(media) == IFM_100_FX) { 972 printf("100baseFX port, "); 973 sc->xl_xcvr = XL_XCVR_100BFX; 974 icfg &= ~XL_ICFG_CONNECTOR_MASK; 975 icfg |= (XL_XCVR_100BFX << XL_ICFG_CONNECTOR_BITS); 976 mediastat |= XL_MEDIASTAT_LINKBEAT; 977 mediastat &= ~XL_MEDIASTAT_SQEENB; 978 } 979 } 980 981 if (sc->xl_media & (XL_MEDIAOPT_AUI|XL_MEDIAOPT_10FL)) { 982 if (IFM_SUBTYPE(media) == IFM_10_5) { 983 printf("AUI port, "); 984 sc->xl_xcvr = XL_XCVR_AUI; 985 icfg &= ~XL_ICFG_CONNECTOR_MASK; 986 icfg |= (XL_XCVR_AUI << XL_ICFG_CONNECTOR_BITS); 987 mediastat &= ~(XL_MEDIASTAT_LINKBEAT| 988 XL_MEDIASTAT_JABGUARD); 989 mediastat |= ~XL_MEDIASTAT_SQEENB; 990 } 991 if (IFM_SUBTYPE(media) == IFM_10_FL) { 992 printf("10baseFL transceiver, "); 993 sc->xl_xcvr = XL_XCVR_AUI; 994 icfg &= ~XL_ICFG_CONNECTOR_MASK; 995 icfg |= (XL_XCVR_AUI << XL_ICFG_CONNECTOR_BITS); 996 mediastat &= ~(XL_MEDIASTAT_LINKBEAT| 997 XL_MEDIASTAT_JABGUARD); 998 mediastat |= ~XL_MEDIASTAT_SQEENB; 999 } 1000 } 1001 1002 if (sc->xl_media & XL_MEDIAOPT_BNC) { 1003 if (IFM_SUBTYPE(media) == IFM_10_2) { 1004 printf("BNC port, "); 1005 sc->xl_xcvr = XL_XCVR_COAX; 1006 icfg &= ~XL_ICFG_CONNECTOR_MASK; 1007 icfg |= (XL_XCVR_COAX << XL_ICFG_CONNECTOR_BITS); 1008 mediastat &= ~(XL_MEDIASTAT_LINKBEAT| 1009 XL_MEDIASTAT_JABGUARD| 1010 XL_MEDIASTAT_SQEENB); 1011 } 1012 } 1013 1014 if ((media & IFM_GMASK) == IFM_FDX || 1015 IFM_SUBTYPE(media) == IFM_100_FX) { 1016 printf("full duplex\n"); 1017 XL_SEL_WIN(3); 1018 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, XL_MACCTRL_DUPLEX); 1019 } else { 1020 printf("half duplex\n"); 1021 XL_SEL_WIN(3); 1022 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, 1023 (CSR_READ_1(sc, XL_W3_MAC_CTRL) & ~XL_MACCTRL_DUPLEX)); 1024 } 1025 1026 if (IFM_SUBTYPE(media) == IFM_10_2) 1027 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_START); 1028 else 1029 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP); 1030 CSR_WRITE_4(sc, XL_W3_INTERNAL_CFG, icfg); 1031 XL_SEL_WIN(4); 1032 CSR_WRITE_2(sc, XL_W4_MEDIA_STATUS, mediastat); 1033 DELAY(800); 1034 XL_SEL_WIN(7); 1035 1036 return; 1037 } 1038 1039 static void 1040 xl_reset(sc) 1041 struct xl_softc *sc; 1042 { 1043 int i; 1044 1045 XL_SEL_WIN(0); 1046 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RESET | 1047 ((sc->xl_flags & XL_FLAG_WEIRDRESET) ? 1048 XL_RESETOPT_DISADVFD:0)); 1049 1050 for (i = 0; i < XL_TIMEOUT; i++) { 1051 DELAY(10); 1052 if (!(CSR_READ_2(sc, XL_STATUS) & XL_STAT_CMDBUSY)) 1053 break; 1054 } 1055 1056 if (i == XL_TIMEOUT) 1057 printf("xl%d: reset didn't complete\n", sc->xl_unit); 1058 1059 /* Reset TX and RX. */ 1060 /* Note: the RX reset takes an absurd amount of time 1061 * on newer versions of the Tornado chips such as those 1062 * on the 3c905CX and newer 3c908C cards. We wait an 1063 * extra amount of time so that xl_wait() doesn't complain 1064 * and annoy the users. 1065 */ 1066 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET); 1067 DELAY(100000); 1068 xl_wait(sc); 1069 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); 1070 xl_wait(sc); 1071 1072 if (sc->xl_flags & XL_FLAG_INVERT_LED_PWR || 1073 sc->xl_flags & XL_FLAG_INVERT_MII_PWR) { 1074 XL_SEL_WIN(2); 1075 CSR_WRITE_2(sc, XL_W2_RESET_OPTIONS, CSR_READ_2(sc, 1076 XL_W2_RESET_OPTIONS) 1077 | ((sc->xl_flags & XL_FLAG_INVERT_LED_PWR)?XL_RESETOPT_INVERT_LED:0) 1078 | ((sc->xl_flags & XL_FLAG_INVERT_MII_PWR)?XL_RESETOPT_INVERT_MII:0) 1079 ); 1080 } 1081 1082 /* Wait a little while for the chip to get its brains in order. */ 1083 DELAY(100000); 1084 return; 1085 } 1086 1087 /* 1088 * Probe for a 3Com Etherlink XL chip. Check the PCI vendor and device 1089 * IDs against our list and return a device name if we find a match. 1090 */ 1091 static int 1092 xl_probe(dev) 1093 device_t dev; 1094 { 1095 struct xl_type *t; 1096 1097 t = xl_devs; 1098 1099 while(t->xl_name != NULL) { 1100 if ((pci_get_vendor(dev) == t->xl_vid) && 1101 (pci_get_device(dev) == t->xl_did)) { 1102 device_set_desc(dev, t->xl_name); 1103 return(0); 1104 } 1105 t++; 1106 } 1107 1108 return(ENXIO); 1109 } 1110 1111 /* 1112 * This routine is a kludge to work around possible hardware faults 1113 * or manufacturing defects that can cause the media options register 1114 * (or reset options register, as it's called for the first generation 1115 * 3c90x adapters) to return an incorrect result. I have encountered 1116 * one Dell Latitude laptop docking station with an integrated 3c905-TX 1117 * which doesn't have any of the 'mediaopt' bits set. This screws up 1118 * the attach routine pretty badly because it doesn't know what media 1119 * to look for. If we find ourselves in this predicament, this routine 1120 * will try to guess the media options values and warn the user of a 1121 * possible manufacturing defect with his adapter/system/whatever. 1122 */ 1123 static void 1124 xl_mediacheck(sc) 1125 struct xl_softc *sc; 1126 { 1127 1128 /* 1129 * If some of the media options bits are set, assume they are 1130 * correct. If not, try to figure it out down below. 1131 * XXX I should check for 10baseFL, but I don't have an adapter 1132 * to test with. 1133 */ 1134 if (sc->xl_media & (XL_MEDIAOPT_MASK & ~XL_MEDIAOPT_VCO)) { 1135 /* 1136 * Check the XCVR value. If it's not in the normal range 1137 * of values, we need to fake it up here. 1138 */ 1139 if (sc->xl_xcvr <= XL_XCVR_AUTO) 1140 return; 1141 else { 1142 printf("xl%d: bogus xcvr value " 1143 "in EEPROM (%x)\n", sc->xl_unit, sc->xl_xcvr); 1144 printf("xl%d: choosing new default based " 1145 "on card type\n", sc->xl_unit); 1146 } 1147 } else { 1148 if (sc->xl_type == XL_TYPE_905B && 1149 sc->xl_media & XL_MEDIAOPT_10FL) 1150 return; 1151 printf("xl%d: WARNING: no media options bits set in " 1152 "the media options register!!\n", sc->xl_unit); 1153 printf("xl%d: this could be a manufacturing defect in " 1154 "your adapter or system\n", sc->xl_unit); 1155 printf("xl%d: attempting to guess media type; you " 1156 "should probably consult your vendor\n", sc->xl_unit); 1157 } 1158 1159 xl_choose_xcvr(sc, 1); 1160 1161 return; 1162 } 1163 1164 static void 1165 xl_choose_xcvr(sc, verbose) 1166 struct xl_softc *sc; 1167 int verbose; 1168 { 1169 u_int16_t devid; 1170 1171 /* 1172 * Read the device ID from the EEPROM. 1173 * This is what's loaded into the PCI device ID register, so it has 1174 * to be correct otherwise we wouldn't have gotten this far. 1175 */ 1176 xl_read_eeprom(sc, (caddr_t)&devid, XL_EE_PRODID, 1, 0); 1177 1178 switch(devid) { 1179 case TC_DEVICEID_BOOMERANG_10BT: /* 3c900-TPO */ 1180 case TC_DEVICEID_KRAKATOA_10BT: /* 3c900B-TPO */ 1181 sc->xl_media = XL_MEDIAOPT_BT; 1182 sc->xl_xcvr = XL_XCVR_10BT; 1183 if (verbose) 1184 printf("xl%d: guessing 10BaseT " 1185 "transceiver\n", sc->xl_unit); 1186 break; 1187 case TC_DEVICEID_BOOMERANG_10BT_COMBO: /* 3c900-COMBO */ 1188 case TC_DEVICEID_KRAKATOA_10BT_COMBO: /* 3c900B-COMBO */ 1189 sc->xl_media = XL_MEDIAOPT_BT|XL_MEDIAOPT_BNC|XL_MEDIAOPT_AUI; 1190 sc->xl_xcvr = XL_XCVR_10BT; 1191 if (verbose) 1192 printf("xl%d: guessing COMBO " 1193 "(AUI/BNC/TP)\n", sc->xl_unit); 1194 break; 1195 case TC_DEVICEID_KRAKATOA_10BT_TPC: /* 3c900B-TPC */ 1196 sc->xl_media = XL_MEDIAOPT_BT|XL_MEDIAOPT_BNC; 1197 sc->xl_xcvr = XL_XCVR_10BT; 1198 if (verbose) 1199 printf("xl%d: guessing TPC (BNC/TP)\n", sc->xl_unit); 1200 break; 1201 case TC_DEVICEID_CYCLONE_10FL: /* 3c900B-FL */ 1202 sc->xl_media = XL_MEDIAOPT_10FL; 1203 sc->xl_xcvr = XL_XCVR_AUI; 1204 if (verbose) 1205 printf("xl%d: guessing 10baseFL\n", sc->xl_unit); 1206 break; 1207 case TC_DEVICEID_BOOMERANG_10_100BT: /* 3c905-TX */ 1208 case TC_DEVICEID_HURRICANE_555: /* 3c555 */ 1209 case TC_DEVICEID_HURRICANE_556: /* 3c556 */ 1210 case TC_DEVICEID_HURRICANE_556B: /* 3c556B */ 1211 case TC_DEVICEID_HURRICANE_575A: /* 3c575TX */ 1212 case TC_DEVICEID_HURRICANE_575B: /* 3c575B */ 1213 case TC_DEVICEID_HURRICANE_575C: /* 3c575C */ 1214 case TC_DEVICEID_HURRICANE_656: /* 3c656 */ 1215 case TC_DEVICEID_HURRICANE_656B: /* 3c656B */ 1216 case TC_DEVICEID_TORNADO_656C: /* 3c656C */ 1217 case TC_DEVICEID_TORNADO_10_100BT_920B: /* 3c920B-EMB */ 1218 sc->xl_media = XL_MEDIAOPT_MII; 1219 sc->xl_xcvr = XL_XCVR_MII; 1220 if (verbose) 1221 printf("xl%d: guessing MII\n", sc->xl_unit); 1222 break; 1223 case TC_DEVICEID_BOOMERANG_100BT4: /* 3c905-T4 */ 1224 case TC_DEVICEID_CYCLONE_10_100BT4: /* 3c905B-T4 */ 1225 sc->xl_media = XL_MEDIAOPT_BT4; 1226 sc->xl_xcvr = XL_XCVR_MII; 1227 if (verbose) 1228 printf("xl%d: guessing 100BaseT4/MII\n", sc->xl_unit); 1229 break; 1230 case TC_DEVICEID_HURRICANE_10_100BT: /* 3c905B-TX */ 1231 case TC_DEVICEID_HURRICANE_10_100BT_SERV:/*3c980-TX */ 1232 case TC_DEVICEID_TORNADO_10_100BT_SERV: /* 3c980C-TX */ 1233 case TC_DEVICEID_HURRICANE_SOHO100TX: /* 3cSOHO100-TX */ 1234 case TC_DEVICEID_TORNADO_10_100BT: /* 3c905C-TX */ 1235 case TC_DEVICEID_TORNADO_HOMECONNECT: /* 3c450-TX */ 1236 sc->xl_media = XL_MEDIAOPT_BTX; 1237 sc->xl_xcvr = XL_XCVR_AUTO; 1238 if (verbose) 1239 printf("xl%d: guessing 10/100 internal\n", sc->xl_unit); 1240 break; 1241 case TC_DEVICEID_CYCLONE_10_100_COMBO: /* 3c905B-COMBO */ 1242 sc->xl_media = XL_MEDIAOPT_BTX|XL_MEDIAOPT_BNC|XL_MEDIAOPT_AUI; 1243 sc->xl_xcvr = XL_XCVR_AUTO; 1244 if (verbose) 1245 printf("xl%d: guessing 10/100 " 1246 "plus BNC/AUI\n", sc->xl_unit); 1247 break; 1248 default: 1249 printf("xl%d: unknown device ID: %x -- " 1250 "defaulting to 10baseT\n", sc->xl_unit, devid); 1251 sc->xl_media = XL_MEDIAOPT_BT; 1252 break; 1253 } 1254 1255 return; 1256 } 1257 1258 /* 1259 * Attach the interface. Allocate softc structures, do ifmedia 1260 * setup and ethernet/BPF attach. 1261 */ 1262 static int 1263 xl_attach(dev) 1264 device_t dev; 1265 { 1266 int s; 1267 u_char eaddr[ETHER_ADDR_LEN]; 1268 u_int32_t command; 1269 struct xl_softc *sc; 1270 struct ifnet *ifp; 1271 int media = IFM_ETHER|IFM_100_TX|IFM_FDX; 1272 int unit, error = 0, rid; 1273 1274 s = splimp(); 1275 1276 sc = device_get_softc(dev); 1277 unit = device_get_unit(dev); 1278 1279 sc->xl_flags = 0; 1280 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_555) 1281 sc->xl_flags |= XL_FLAG_EEPROM_OFFSET_30 | XL_FLAG_PHYOK; 1282 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_556 || 1283 pci_get_device(dev) == TC_DEVICEID_HURRICANE_556B) 1284 sc->xl_flags |= XL_FLAG_FUNCREG | XL_FLAG_PHYOK | 1285 XL_FLAG_EEPROM_OFFSET_30 | XL_FLAG_WEIRDRESET | 1286 XL_FLAG_INVERT_LED_PWR | XL_FLAG_INVERT_MII_PWR; 1287 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_555 || 1288 pci_get_device(dev) == TC_DEVICEID_HURRICANE_556) 1289 sc->xl_flags |= XL_FLAG_8BITROM; 1290 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_556B) 1291 sc->xl_flags |= XL_FLAG_NO_XCVR_PWR; 1292 1293 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_575A || 1294 pci_get_device(dev) == TC_DEVICEID_HURRICANE_575B || 1295 pci_get_device(dev) == TC_DEVICEID_HURRICANE_575C || 1296 pci_get_device(dev) == TC_DEVICEID_HURRICANE_656B || 1297 pci_get_device(dev) == TC_DEVICEID_TORNADO_656C) 1298 sc->xl_flags |= XL_FLAG_FUNCREG | XL_FLAG_PHYOK | 1299 XL_FLAG_EEPROM_OFFSET_30 | XL_FLAG_8BITROM; 1300 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_656) 1301 sc->xl_flags |= XL_FLAG_FUNCREG | XL_FLAG_PHYOK; 1302 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_575B) 1303 sc->xl_flags |= XL_FLAG_INVERT_LED_PWR; 1304 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_575C) 1305 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR; 1306 if (pci_get_device(dev) == TC_DEVICEID_TORNADO_656C) 1307 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR; 1308 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_656 || 1309 pci_get_device(dev) == TC_DEVICEID_HURRICANE_656B) 1310 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR | 1311 XL_FLAG_INVERT_LED_PWR; 1312 if (pci_get_device(dev) == TC_DEVICEID_TORNADO_10_100BT_920B) 1313 sc->xl_flags |= XL_FLAG_PHYOK; 1314 1315 /* 1316 * If this is a 3c905B, we have to check one extra thing. 1317 * The 905B supports power management and may be placed in 1318 * a low-power mode (D3 mode), typically by certain operating 1319 * systems which shall not be named. The PCI BIOS is supposed 1320 * to reset the NIC and bring it out of low-power mode, but 1321 * some do not. Consequently, we have to see if this chip 1322 * supports power management, and if so, make sure it's not 1323 * in low-power mode. If power management is available, the 1324 * capid byte will be 0x01. 1325 * 1326 * I _think_ that what actually happens is that the chip 1327 * loses its PCI configuration during the transition from 1328 * D3 back to D0; this means that it should be possible for 1329 * us to save the PCI iobase, membase and IRQ, put the chip 1330 * back in the D0 state, then restore the PCI config ourselves. 1331 */ 1332 1333 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 1334 u_int32_t iobase, membase, irq; 1335 1336 /* Save important PCI config data. */ 1337 iobase = pci_read_config(dev, XL_PCI_LOIO, 4); 1338 membase = pci_read_config(dev, XL_PCI_LOMEM, 4); 1339 irq = pci_read_config(dev, XL_PCI_INTLINE, 4); 1340 1341 /* Reset the power state. */ 1342 printf("xl%d: chip is in D%d power mode " 1343 "-- setting to D0\n", unit, 1344 pci_get_powerstate(dev)); 1345 1346 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 1347 1348 /* Restore PCI config data. */ 1349 pci_write_config(dev, XL_PCI_LOIO, iobase, 4); 1350 pci_write_config(dev, XL_PCI_LOMEM, membase, 4); 1351 pci_write_config(dev, XL_PCI_INTLINE, irq, 4); 1352 } 1353 1354 /* 1355 * Map control/status registers. 1356 */ 1357 pci_enable_busmaster(dev); 1358 pci_enable_io(dev, SYS_RES_IOPORT); 1359 pci_enable_io(dev, SYS_RES_MEMORY); 1360 command = pci_read_config(dev, PCIR_COMMAND, 4); 1361 1362 #ifdef XL_USEIOSPACE 1363 if (!(command & PCIM_CMD_PORTEN)) { 1364 printf("xl%d: failed to enable I/O ports!\n", unit); 1365 error = ENXIO; 1366 goto fail; 1367 } 1368 #else 1369 if (!(command & PCIM_CMD_MEMEN)) { 1370 printf("xl%d: failed to enable memory mapping!\n", unit); 1371 error = ENXIO; 1372 goto fail; 1373 } 1374 #endif 1375 1376 rid = XL_RID; 1377 sc->xl_res = bus_alloc_resource(dev, XL_RES, &rid, 1378 0, ~0, 1, RF_ACTIVE); 1379 1380 if (sc->xl_res == NULL) { 1381 printf ("xl%d: couldn't map ports/memory\n", unit); 1382 error = ENXIO; 1383 goto fail; 1384 } 1385 1386 sc->xl_btag = rman_get_bustag(sc->xl_res); 1387 sc->xl_bhandle = rman_get_bushandle(sc->xl_res); 1388 1389 if (sc->xl_flags & XL_FLAG_FUNCREG) { 1390 rid = XL_PCI_FUNCMEM; 1391 sc->xl_fres = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 1392 0, ~0, 1, RF_ACTIVE); 1393 1394 if (sc->xl_fres == NULL) { 1395 printf ("xl%d: couldn't map ports/memory\n", unit); 1396 bus_release_resource(dev, XL_RES, XL_RID, sc->xl_res); 1397 error = ENXIO; 1398 goto fail; 1399 } 1400 1401 sc->xl_ftag = rman_get_bustag(sc->xl_fres); 1402 sc->xl_fhandle = rman_get_bushandle(sc->xl_fres); 1403 } 1404 1405 rid = 0; 1406 sc->xl_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 1407 RF_SHAREABLE | RF_ACTIVE); 1408 1409 if (sc->xl_irq == NULL) { 1410 printf("xl%d: couldn't map interrupt\n", unit); 1411 if (sc->xl_fres != NULL) 1412 bus_release_resource(dev, SYS_RES_MEMORY, 1413 XL_PCI_FUNCMEM, sc->xl_fres); 1414 bus_release_resource(dev, XL_RES, XL_RID, sc->xl_res); 1415 error = ENXIO; 1416 goto fail; 1417 } 1418 1419 error = bus_setup_intr(dev, sc->xl_irq, INTR_TYPE_NET, 1420 xl_intr, sc, &sc->xl_intrhand); 1421 1422 if (error) { 1423 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->xl_irq); 1424 if (sc->xl_fres != NULL) 1425 bus_release_resource(dev, SYS_RES_MEMORY, 1426 XL_PCI_FUNCMEM, sc->xl_fres); 1427 bus_release_resource(dev, XL_RES, XL_RID, sc->xl_res); 1428 printf("xl%d: couldn't set up irq\n", unit); 1429 goto fail; 1430 } 1431 1432 /* Reset the adapter. */ 1433 xl_reset(sc); 1434 1435 /* 1436 * Get station address from the EEPROM. 1437 */ 1438 if (xl_read_eeprom(sc, (caddr_t)&eaddr, XL_EE_OEM_ADR0, 3, 1)) { 1439 printf("xl%d: failed to read station address\n", sc->xl_unit); 1440 bus_teardown_intr(dev, sc->xl_irq, sc->xl_intrhand); 1441 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->xl_irq); 1442 if (sc->xl_fres != NULL) 1443 bus_release_resource(dev, SYS_RES_MEMORY, 1444 XL_PCI_FUNCMEM, sc->xl_fres); 1445 bus_release_resource(dev, XL_RES, XL_RID, sc->xl_res); 1446 error = ENXIO; 1447 goto fail; 1448 } 1449 1450 /* 1451 * A 3Com chip was detected. Inform the world. 1452 */ 1453 printf("xl%d: Ethernet address: %6D\n", unit, eaddr, ":"); 1454 1455 sc->xl_unit = unit; 1456 callout_handle_init(&sc->xl_stat_ch); 1457 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 1458 1459 sc->xl_ldata = contigmalloc(sizeof(struct xl_list_data), M_DEVBUF, 1460 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 1461 1462 if (sc->xl_ldata == NULL) { 1463 printf("xl%d: no memory for list buffers!\n", unit); 1464 bus_teardown_intr(dev, sc->xl_irq, sc->xl_intrhand); 1465 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->xl_irq); 1466 if (sc->xl_fres != NULL) 1467 bus_release_resource(dev, SYS_RES_MEMORY, 1468 XL_PCI_FUNCMEM, sc->xl_fres); 1469 bus_release_resource(dev, XL_RES, XL_RID, sc->xl_res); 1470 error = ENXIO; 1471 goto fail; 1472 } 1473 1474 bzero(sc->xl_ldata, sizeof(struct xl_list_data)); 1475 1476 /* 1477 * Figure out the card type. 3c905B adapters have the 1478 * 'supportsNoTxLength' bit set in the capabilities 1479 * word in the EEPROM. 1480 */ 1481 xl_read_eeprom(sc, (caddr_t)&sc->xl_caps, XL_EE_CAPS, 1, 0); 1482 if (sc->xl_caps & XL_CAPS_NO_TXLENGTH) 1483 sc->xl_type = XL_TYPE_905B; 1484 else 1485 sc->xl_type = XL_TYPE_90X; 1486 1487 ifp = &sc->arpcom.ac_if; 1488 ifp->if_softc = sc; 1489 ifp->if_unit = unit; 1490 ifp->if_name = "xl"; 1491 ifp->if_mtu = ETHERMTU; 1492 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1493 ifp->if_ioctl = xl_ioctl; 1494 ifp->if_output = ether_output; 1495 if (sc->xl_type == XL_TYPE_905B) { 1496 ifp->if_start = xl_start_90xB; 1497 ifp->if_hwassist = XL905B_CSUM_FEATURES; 1498 ifp->if_capabilities = IFCAP_HWCSUM; 1499 } else 1500 ifp->if_start = xl_start; 1501 ifp->if_watchdog = xl_watchdog; 1502 ifp->if_init = xl_init; 1503 ifp->if_baudrate = 10000000; 1504 ifp->if_snd.ifq_maxlen = XL_TX_LIST_CNT - 1; 1505 ifp->if_capenable = ifp->if_capabilities; 1506 1507 /* 1508 * Now we have to see what sort of media we have. 1509 * This includes probing for an MII interace and a 1510 * possible PHY. 1511 */ 1512 XL_SEL_WIN(3); 1513 sc->xl_media = CSR_READ_2(sc, XL_W3_MEDIA_OPT); 1514 if (bootverbose) 1515 printf("xl%d: media options word: %x\n", sc->xl_unit, 1516 sc->xl_media); 1517 1518 xl_read_eeprom(sc, (char *)&sc->xl_xcvr, XL_EE_ICFG_0, 2, 0); 1519 sc->xl_xcvr &= XL_ICFG_CONNECTOR_MASK; 1520 sc->xl_xcvr >>= XL_ICFG_CONNECTOR_BITS; 1521 1522 xl_mediacheck(sc); 1523 1524 if (sc->xl_media & XL_MEDIAOPT_MII || sc->xl_media & XL_MEDIAOPT_BTX 1525 || sc->xl_media & XL_MEDIAOPT_BT4) { 1526 if (bootverbose) 1527 printf("xl%d: found MII/AUTO\n", sc->xl_unit); 1528 xl_setcfg(sc); 1529 if (mii_phy_probe(dev, &sc->xl_miibus, 1530 xl_ifmedia_upd, xl_ifmedia_sts)) { 1531 printf("xl%d: no PHY found!\n", sc->xl_unit); 1532 bus_teardown_intr(dev, sc->xl_irq, sc->xl_intrhand); 1533 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->xl_irq); 1534 bus_release_resource(dev, XL_RES, XL_RID, sc->xl_res); 1535 contigfree(sc->xl_ldata, 1536 sizeof(struct xl_list_data), M_DEVBUF); 1537 error = ENXIO; 1538 goto fail; 1539 } 1540 1541 goto done; 1542 } 1543 1544 /* 1545 * Sanity check. If the user has selected "auto" and this isn't 1546 * a 10/100 card of some kind, we need to force the transceiver 1547 * type to something sane. 1548 */ 1549 if (sc->xl_xcvr == XL_XCVR_AUTO) 1550 xl_choose_xcvr(sc, bootverbose); 1551 1552 /* 1553 * Do ifmedia setup. 1554 */ 1555 1556 ifmedia_init(&sc->ifmedia, 0, xl_ifmedia_upd, xl_ifmedia_sts); 1557 1558 if (sc->xl_media & XL_MEDIAOPT_BT) { 1559 if (bootverbose) 1560 printf("xl%d: found 10baseT\n", sc->xl_unit); 1561 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL); 1562 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T|IFM_HDX, 0, NULL); 1563 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX) 1564 ifmedia_add(&sc->ifmedia, 1565 IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL); 1566 } 1567 1568 if (sc->xl_media & (XL_MEDIAOPT_AUI|XL_MEDIAOPT_10FL)) { 1569 /* 1570 * Check for a 10baseFL board in disguise. 1571 */ 1572 if (sc->xl_type == XL_TYPE_905B && 1573 sc->xl_media == XL_MEDIAOPT_10FL) { 1574 if (bootverbose) 1575 printf("xl%d: found 10baseFL\n", sc->xl_unit); 1576 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_FL, 0, NULL); 1577 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_FL|IFM_HDX, 1578 0, NULL); 1579 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX) 1580 ifmedia_add(&sc->ifmedia, 1581 IFM_ETHER|IFM_10_FL|IFM_FDX, 0, NULL); 1582 } else { 1583 if (bootverbose) 1584 printf("xl%d: found AUI\n", sc->xl_unit); 1585 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_5, 0, NULL); 1586 } 1587 } 1588 1589 if (sc->xl_media & XL_MEDIAOPT_BNC) { 1590 if (bootverbose) 1591 printf("xl%d: found BNC\n", sc->xl_unit); 1592 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_2, 0, NULL); 1593 } 1594 1595 if (sc->xl_media & XL_MEDIAOPT_BFX) { 1596 if (bootverbose) 1597 printf("xl%d: found 100baseFX\n", sc->xl_unit); 1598 ifp->if_baudrate = 100000000; 1599 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_FX, 0, NULL); 1600 } 1601 1602 /* Choose a default media. */ 1603 switch(sc->xl_xcvr) { 1604 case XL_XCVR_10BT: 1605 media = IFM_ETHER|IFM_10_T; 1606 xl_setmode(sc, media); 1607 break; 1608 case XL_XCVR_AUI: 1609 if (sc->xl_type == XL_TYPE_905B && 1610 sc->xl_media == XL_MEDIAOPT_10FL) { 1611 media = IFM_ETHER|IFM_10_FL; 1612 xl_setmode(sc, media); 1613 } else { 1614 media = IFM_ETHER|IFM_10_5; 1615 xl_setmode(sc, media); 1616 } 1617 break; 1618 case XL_XCVR_COAX: 1619 media = IFM_ETHER|IFM_10_2; 1620 xl_setmode(sc, media); 1621 break; 1622 case XL_XCVR_AUTO: 1623 case XL_XCVR_100BTX: 1624 case XL_XCVR_MII: 1625 /* Chosen by miibus */ 1626 break; 1627 case XL_XCVR_100BFX: 1628 media = IFM_ETHER|IFM_100_FX; 1629 break; 1630 default: 1631 printf("xl%d: unknown XCVR type: %d\n", sc->xl_unit, 1632 sc->xl_xcvr); 1633 /* 1634 * This will probably be wrong, but it prevents 1635 * the ifmedia code from panicking. 1636 */ 1637 media = IFM_ETHER|IFM_10_T; 1638 break; 1639 } 1640 1641 if (sc->xl_miibus == NULL) 1642 ifmedia_set(&sc->ifmedia, media); 1643 1644 done: 1645 1646 if (sc->xl_flags & XL_FLAG_NO_XCVR_PWR) { 1647 XL_SEL_WIN(0); 1648 CSR_WRITE_2(sc, XL_W0_MFG_ID, XL_NO_XCVR_PWR_MAGICBITS); 1649 } 1650 1651 /* 1652 * Call MI attach routine. 1653 */ 1654 ether_ifattach(ifp, ETHER_BPF_SUPPORTED); 1655 1656 fail: 1657 splx(s); 1658 return(error); 1659 } 1660 1661 static int 1662 xl_detach(dev) 1663 device_t dev; 1664 { 1665 struct xl_softc *sc; 1666 struct ifnet *ifp; 1667 int s; 1668 1669 s = splimp(); 1670 1671 sc = device_get_softc(dev); 1672 ifp = &sc->arpcom.ac_if; 1673 1674 xl_reset(sc); 1675 xl_stop(sc); 1676 ether_ifdetach(ifp, ETHER_BPF_SUPPORTED); 1677 1678 /* Delete any miibus and phy devices attached to this interface */ 1679 if (sc->xl_miibus != NULL) { 1680 bus_generic_detach(dev); 1681 device_delete_child(dev, sc->xl_miibus); 1682 } 1683 1684 bus_teardown_intr(dev, sc->xl_irq, sc->xl_intrhand); 1685 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->xl_irq); 1686 if (sc->xl_fres != NULL) 1687 bus_release_resource(dev, SYS_RES_MEMORY, 1688 XL_PCI_FUNCMEM, sc->xl_fres); 1689 bus_release_resource(dev, XL_RES, XL_RID, sc->xl_res); 1690 1691 ifmedia_removeall(&sc->ifmedia); 1692 contigfree(sc->xl_ldata, sizeof(struct xl_list_data), M_DEVBUF); 1693 1694 splx(s); 1695 1696 return(0); 1697 } 1698 1699 /* 1700 * Initialize the transmit descriptors. 1701 */ 1702 static int 1703 xl_list_tx_init(sc) 1704 struct xl_softc *sc; 1705 { 1706 struct xl_chain_data *cd; 1707 struct xl_list_data *ld; 1708 int i; 1709 1710 cd = &sc->xl_cdata; 1711 ld = sc->xl_ldata; 1712 for (i = 0; i < XL_TX_LIST_CNT; i++) { 1713 cd->xl_tx_chain[i].xl_ptr = &ld->xl_tx_list[i]; 1714 if (i == (XL_TX_LIST_CNT - 1)) 1715 cd->xl_tx_chain[i].xl_next = NULL; 1716 else 1717 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[i + 1]; 1718 } 1719 1720 cd->xl_tx_free = &cd->xl_tx_chain[0]; 1721 cd->xl_tx_tail = cd->xl_tx_head = NULL; 1722 1723 return(0); 1724 } 1725 1726 /* 1727 * Initialize the transmit descriptors. 1728 */ 1729 static int xl_list_tx_init_90xB(sc) 1730 struct xl_softc *sc; 1731 { 1732 struct xl_chain_data *cd; 1733 struct xl_list_data *ld; 1734 int i; 1735 1736 cd = &sc->xl_cdata; 1737 ld = sc->xl_ldata; 1738 for (i = 0; i < XL_TX_LIST_CNT; i++) { 1739 cd->xl_tx_chain[i].xl_ptr = &ld->xl_tx_list[i]; 1740 cd->xl_tx_chain[i].xl_phys = vtophys(&ld->xl_tx_list[i]); 1741 if (i == (XL_TX_LIST_CNT - 1)) 1742 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[0]; 1743 else 1744 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[i + 1]; 1745 if (i == 0) 1746 cd->xl_tx_chain[i].xl_prev = 1747 &cd->xl_tx_chain[XL_TX_LIST_CNT - 1]; 1748 else 1749 cd->xl_tx_chain[i].xl_prev = 1750 &cd->xl_tx_chain[i - 1]; 1751 } 1752 1753 bzero((char *)ld->xl_tx_list, 1754 sizeof(struct xl_list) * XL_TX_LIST_CNT); 1755 ld->xl_tx_list[0].xl_status = XL_TXSTAT_EMPTY; 1756 1757 cd->xl_tx_prod = 1; 1758 cd->xl_tx_cons = 1; 1759 cd->xl_tx_cnt = 0; 1760 1761 return(0); 1762 } 1763 1764 /* 1765 * Initialize the RX descriptors and allocate mbufs for them. Note that 1766 * we arrange the descriptors in a closed ring, so that the last descriptor 1767 * points back to the first. 1768 */ 1769 static int 1770 xl_list_rx_init(sc) 1771 struct xl_softc *sc; 1772 { 1773 struct xl_chain_data *cd; 1774 struct xl_list_data *ld; 1775 int i; 1776 1777 cd = &sc->xl_cdata; 1778 ld = sc->xl_ldata; 1779 1780 for (i = 0; i < XL_RX_LIST_CNT; i++) { 1781 cd->xl_rx_chain[i].xl_ptr = 1782 (struct xl_list_onefrag *)&ld->xl_rx_list[i]; 1783 if (xl_newbuf(sc, &cd->xl_rx_chain[i]) == ENOBUFS) 1784 return(ENOBUFS); 1785 if (i == (XL_RX_LIST_CNT - 1)) { 1786 cd->xl_rx_chain[i].xl_next = &cd->xl_rx_chain[0]; 1787 ld->xl_rx_list[i].xl_next = 1788 vtophys(&ld->xl_rx_list[0]); 1789 } else { 1790 cd->xl_rx_chain[i].xl_next = &cd->xl_rx_chain[i + 1]; 1791 ld->xl_rx_list[i].xl_next = 1792 vtophys(&ld->xl_rx_list[i + 1]); 1793 } 1794 } 1795 1796 cd->xl_rx_head = &cd->xl_rx_chain[0]; 1797 1798 return(0); 1799 } 1800 1801 /* 1802 * Initialize an RX descriptor and attach an MBUF cluster. 1803 */ 1804 static int 1805 xl_newbuf(sc, c) 1806 struct xl_softc *sc; 1807 struct xl_chain_onefrag *c; 1808 { 1809 struct mbuf *m_new = NULL; 1810 1811 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1812 if (m_new == NULL) 1813 return(ENOBUFS); 1814 1815 MCLGET(m_new, M_DONTWAIT); 1816 if (!(m_new->m_flags & M_EXT)) { 1817 m_freem(m_new); 1818 return(ENOBUFS); 1819 } 1820 1821 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1822 1823 /* Force longword alignment for packet payload. */ 1824 m_adj(m_new, ETHER_ALIGN); 1825 1826 c->xl_mbuf = m_new; 1827 c->xl_ptr->xl_frag.xl_addr = vtophys(mtod(m_new, caddr_t)); 1828 c->xl_ptr->xl_frag.xl_len = MCLBYTES | XL_LAST_FRAG; 1829 c->xl_ptr->xl_status = 0; 1830 1831 return(0); 1832 } 1833 1834 static int 1835 xl_rx_resync(sc) 1836 struct xl_softc *sc; 1837 { 1838 struct xl_chain_onefrag *pos; 1839 int i; 1840 1841 pos = sc->xl_cdata.xl_rx_head; 1842 1843 for (i = 0; i < XL_RX_LIST_CNT; i++) { 1844 if (pos->xl_ptr->xl_status) 1845 break; 1846 pos = pos->xl_next; 1847 } 1848 1849 if (i == XL_RX_LIST_CNT) 1850 return(0); 1851 1852 sc->xl_cdata.xl_rx_head = pos; 1853 1854 return(EAGAIN); 1855 } 1856 1857 /* 1858 * A frame has been uploaded: pass the resulting mbuf chain up to 1859 * the higher level protocols. 1860 */ 1861 static void 1862 xl_rxeof(sc) 1863 struct xl_softc *sc; 1864 { 1865 struct ether_header *eh; 1866 struct mbuf *m; 1867 struct ifnet *ifp; 1868 struct xl_chain_onefrag *cur_rx; 1869 int total_len = 0; 1870 u_int32_t rxstat; 1871 1872 ifp = &sc->arpcom.ac_if; 1873 1874 again: 1875 1876 while((rxstat = sc->xl_cdata.xl_rx_head->xl_ptr->xl_status)) { 1877 cur_rx = sc->xl_cdata.xl_rx_head; 1878 sc->xl_cdata.xl_rx_head = cur_rx->xl_next; 1879 1880 /* 1881 * If an error occurs, update stats, clear the 1882 * status word and leave the mbuf cluster in place: 1883 * it should simply get re-used next time this descriptor 1884 * comes up in the ring. 1885 */ 1886 if (rxstat & XL_RXSTAT_UP_ERROR) { 1887 ifp->if_ierrors++; 1888 cur_rx->xl_ptr->xl_status = 0; 1889 continue; 1890 } 1891 1892 /* 1893 * If there error bit was not set, the upload complete 1894 * bit should be set which means we have a valid packet. 1895 * If not, something truly strange has happened. 1896 */ 1897 if (!(rxstat & XL_RXSTAT_UP_CMPLT)) { 1898 printf("xl%d: bad receive status -- " 1899 "packet dropped", sc->xl_unit); 1900 ifp->if_ierrors++; 1901 cur_rx->xl_ptr->xl_status = 0; 1902 continue; 1903 } 1904 1905 /* No errors; receive the packet. */ 1906 m = cur_rx->xl_mbuf; 1907 total_len = cur_rx->xl_ptr->xl_status & XL_RXSTAT_LENMASK; 1908 1909 /* 1910 * Try to conjure up a new mbuf cluster. If that 1911 * fails, it means we have an out of memory condition and 1912 * should leave the buffer in place and continue. This will 1913 * result in a lost packet, but there's little else we 1914 * can do in this situation. 1915 */ 1916 if (xl_newbuf(sc, cur_rx) == ENOBUFS) { 1917 ifp->if_ierrors++; 1918 cur_rx->xl_ptr->xl_status = 0; 1919 continue; 1920 } 1921 1922 ifp->if_ipackets++; 1923 eh = mtod(m, struct ether_header *); 1924 m->m_pkthdr.rcvif = ifp; 1925 m->m_pkthdr.len = m->m_len = total_len; 1926 1927 /* Remove header from mbuf and pass it on. */ 1928 m_adj(m, sizeof(struct ether_header)); 1929 1930 if (sc->xl_type == XL_TYPE_905B) { 1931 /* Do IP checksum checking. */ 1932 if (rxstat & XL_RXSTAT_IPCKOK) 1933 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 1934 if (!(rxstat & XL_RXSTAT_IPCKERR)) 1935 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1936 if ((rxstat & XL_RXSTAT_TCPCOK && 1937 !(rxstat & XL_RXSTAT_TCPCKERR)) || 1938 (rxstat & XL_RXSTAT_UDPCKOK && 1939 !(rxstat & XL_RXSTAT_UDPCKERR))) { 1940 m->m_pkthdr.csum_flags |= 1941 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 1942 m->m_pkthdr.csum_data = 0xffff; 1943 } 1944 } 1945 ether_input(ifp, eh, m); 1946 } 1947 1948 /* 1949 * Handle the 'end of channel' condition. When the upload 1950 * engine hits the end of the RX ring, it will stall. This 1951 * is our cue to flush the RX ring, reload the uplist pointer 1952 * register and unstall the engine. 1953 * XXX This is actually a little goofy. With the ThunderLAN 1954 * chip, you get an interrupt when the receiver hits the end 1955 * of the receive ring, which tells you exactly when you 1956 * you need to reload the ring pointer. Here we have to 1957 * fake it. I'm mad at myself for not being clever enough 1958 * to avoid the use of a goto here. 1959 */ 1960 if (CSR_READ_4(sc, XL_UPLIST_PTR) == 0 || 1961 CSR_READ_4(sc, XL_UPLIST_STATUS) & XL_PKTSTAT_UP_STALLED) { 1962 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_STALL); 1963 xl_wait(sc); 1964 CSR_WRITE_4(sc, XL_UPLIST_PTR, 1965 vtophys(&sc->xl_ldata->xl_rx_list[0])); 1966 sc->xl_cdata.xl_rx_head = &sc->xl_cdata.xl_rx_chain[0]; 1967 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_UNSTALL); 1968 goto again; 1969 } 1970 1971 return; 1972 } 1973 1974 /* 1975 * A frame was downloaded to the chip. It's safe for us to clean up 1976 * the list buffers. 1977 */ 1978 static void 1979 xl_txeof(sc) 1980 struct xl_softc *sc; 1981 { 1982 struct xl_chain *cur_tx; 1983 struct ifnet *ifp; 1984 1985 ifp = &sc->arpcom.ac_if; 1986 1987 /* Clear the timeout timer. */ 1988 ifp->if_timer = 0; 1989 1990 /* 1991 * Go through our tx list and free mbufs for those 1992 * frames that have been uploaded. Note: the 3c905B 1993 * sets a special bit in the status word to let us 1994 * know that a frame has been downloaded, but the 1995 * original 3c900/3c905 adapters don't do that. 1996 * Consequently, we have to use a different test if 1997 * xl_type != XL_TYPE_905B. 1998 */ 1999 while(sc->xl_cdata.xl_tx_head != NULL) { 2000 cur_tx = sc->xl_cdata.xl_tx_head; 2001 2002 if (CSR_READ_4(sc, XL_DOWNLIST_PTR)) 2003 break; 2004 2005 sc->xl_cdata.xl_tx_head = cur_tx->xl_next; 2006 m_freem(cur_tx->xl_mbuf); 2007 cur_tx->xl_mbuf = NULL; 2008 ifp->if_opackets++; 2009 2010 cur_tx->xl_next = sc->xl_cdata.xl_tx_free; 2011 sc->xl_cdata.xl_tx_free = cur_tx; 2012 } 2013 2014 if (sc->xl_cdata.xl_tx_head == NULL) { 2015 ifp->if_flags &= ~IFF_OACTIVE; 2016 sc->xl_cdata.xl_tx_tail = NULL; 2017 } else { 2018 if (CSR_READ_4(sc, XL_DMACTL) & XL_DMACTL_DOWN_STALLED || 2019 !CSR_READ_4(sc, XL_DOWNLIST_PTR)) { 2020 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, 2021 vtophys(sc->xl_cdata.xl_tx_head->xl_ptr)); 2022 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); 2023 } 2024 } 2025 2026 return; 2027 } 2028 2029 static void xl_txeof_90xB(sc) 2030 struct xl_softc *sc; 2031 { 2032 struct xl_chain *cur_tx = NULL; 2033 struct ifnet *ifp; 2034 int idx; 2035 2036 ifp = &sc->arpcom.ac_if; 2037 2038 idx = sc->xl_cdata.xl_tx_cons; 2039 while(idx != sc->xl_cdata.xl_tx_prod) { 2040 2041 cur_tx = &sc->xl_cdata.xl_tx_chain[idx]; 2042 2043 if (!(cur_tx->xl_ptr->xl_status & XL_TXSTAT_DL_COMPLETE)) 2044 break; 2045 2046 if (cur_tx->xl_mbuf != NULL) { 2047 m_freem(cur_tx->xl_mbuf); 2048 cur_tx->xl_mbuf = NULL; 2049 } 2050 2051 ifp->if_opackets++; 2052 2053 sc->xl_cdata.xl_tx_cnt--; 2054 XL_INC(idx, XL_TX_LIST_CNT); 2055 ifp->if_timer = 0; 2056 } 2057 2058 sc->xl_cdata.xl_tx_cons = idx; 2059 2060 if (cur_tx != NULL) 2061 ifp->if_flags &= ~IFF_OACTIVE; 2062 2063 return; 2064 } 2065 2066 /* 2067 * TX 'end of channel' interrupt handler. Actually, we should 2068 * only get a 'TX complete' interrupt if there's a transmit error, 2069 * so this is really TX error handler. 2070 */ 2071 static void 2072 xl_txeoc(sc) 2073 struct xl_softc *sc; 2074 { 2075 u_int8_t txstat; 2076 2077 while((txstat = CSR_READ_1(sc, XL_TX_STATUS))) { 2078 if (txstat & XL_TXSTATUS_UNDERRUN || 2079 txstat & XL_TXSTATUS_JABBER || 2080 txstat & XL_TXSTATUS_RECLAIM) { 2081 printf("xl%d: transmission error: %x\n", 2082 sc->xl_unit, txstat); 2083 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); 2084 xl_wait(sc); 2085 if (sc->xl_type == XL_TYPE_905B) { 2086 if (sc->xl_cdata.xl_tx_cnt) { 2087 int i; 2088 struct xl_chain *c; 2089 i = sc->xl_cdata.xl_tx_cons; 2090 c = &sc->xl_cdata.xl_tx_chain[i]; 2091 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, 2092 c->xl_phys); 2093 CSR_WRITE_1(sc, XL_DOWN_POLL, 64); 2094 } 2095 } else { 2096 if (sc->xl_cdata.xl_tx_head != NULL) 2097 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, 2098 vtophys(sc->xl_cdata.xl_tx_head->xl_ptr)); 2099 } 2100 /* 2101 * Remember to set this for the 2102 * first generation 3c90X chips. 2103 */ 2104 CSR_WRITE_1(sc, XL_TX_FREETHRESH, XL_PACKET_SIZE >> 8); 2105 if (txstat & XL_TXSTATUS_UNDERRUN && 2106 sc->xl_tx_thresh < XL_PACKET_SIZE) { 2107 sc->xl_tx_thresh += XL_MIN_FRAMELEN; 2108 printf("xl%d: tx underrun, increasing tx start" 2109 " threshold to %d bytes\n", sc->xl_unit, 2110 sc->xl_tx_thresh); 2111 } 2112 CSR_WRITE_2(sc, XL_COMMAND, 2113 XL_CMD_TX_SET_START|sc->xl_tx_thresh); 2114 if (sc->xl_type == XL_TYPE_905B) { 2115 CSR_WRITE_2(sc, XL_COMMAND, 2116 XL_CMD_SET_TX_RECLAIM|(XL_PACKET_SIZE >> 4)); 2117 } 2118 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE); 2119 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); 2120 } else { 2121 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE); 2122 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); 2123 } 2124 /* 2125 * Write an arbitrary byte to the TX_STATUS register 2126 * to clear this interrupt/error and advance to the next. 2127 */ 2128 CSR_WRITE_1(sc, XL_TX_STATUS, 0x01); 2129 } 2130 2131 return; 2132 } 2133 2134 static void 2135 xl_intr(arg) 2136 void *arg; 2137 { 2138 struct xl_softc *sc; 2139 struct ifnet *ifp; 2140 u_int16_t status; 2141 2142 sc = arg; 2143 ifp = &sc->arpcom.ac_if; 2144 2145 while((status = CSR_READ_2(sc, XL_STATUS)) & XL_INTRS && status != 0xFFFF) { 2146 2147 CSR_WRITE_2(sc, XL_COMMAND, 2148 XL_CMD_INTR_ACK|(status & XL_INTRS)); 2149 2150 if (status & XL_STAT_UP_COMPLETE) { 2151 int curpkts; 2152 2153 curpkts = ifp->if_ipackets; 2154 xl_rxeof(sc); 2155 if (curpkts == ifp->if_ipackets) { 2156 while (xl_rx_resync(sc)) 2157 xl_rxeof(sc); 2158 } 2159 } 2160 2161 if (status & XL_STAT_DOWN_COMPLETE) { 2162 if (sc->xl_type == XL_TYPE_905B) 2163 xl_txeof_90xB(sc); 2164 else 2165 xl_txeof(sc); 2166 } 2167 2168 if (status & XL_STAT_TX_COMPLETE) { 2169 ifp->if_oerrors++; 2170 xl_txeoc(sc); 2171 } 2172 2173 if (status & XL_STAT_ADFAIL) { 2174 xl_reset(sc); 2175 xl_init(sc); 2176 } 2177 2178 if (status & XL_STAT_STATSOFLOW) { 2179 sc->xl_stats_no_timeout = 1; 2180 xl_stats_update(sc); 2181 sc->xl_stats_no_timeout = 0; 2182 } 2183 } 2184 2185 if (ifp->if_snd.ifq_head != NULL) 2186 (*ifp->if_start)(ifp); 2187 2188 return; 2189 } 2190 2191 static void 2192 xl_stats_update(xsc) 2193 void *xsc; 2194 { 2195 struct xl_softc *sc; 2196 struct ifnet *ifp; 2197 struct xl_stats xl_stats; 2198 u_int8_t *p; 2199 int i; 2200 struct mii_data *mii = NULL; 2201 2202 bzero((char *)&xl_stats, sizeof(struct xl_stats)); 2203 2204 sc = xsc; 2205 ifp = &sc->arpcom.ac_if; 2206 if (sc->xl_miibus != NULL) 2207 mii = device_get_softc(sc->xl_miibus); 2208 2209 p = (u_int8_t *)&xl_stats; 2210 2211 /* Read all the stats registers. */ 2212 XL_SEL_WIN(6); 2213 2214 for (i = 0; i < 16; i++) 2215 *p++ = CSR_READ_1(sc, XL_W6_CARRIER_LOST + i); 2216 2217 ifp->if_ierrors += xl_stats.xl_rx_overrun; 2218 2219 ifp->if_collisions += xl_stats.xl_tx_multi_collision + 2220 xl_stats.xl_tx_single_collision + 2221 xl_stats.xl_tx_late_collision; 2222 2223 /* 2224 * Boomerang and cyclone chips have an extra stats counter 2225 * in window 4 (BadSSD). We have to read this too in order 2226 * to clear out all the stats registers and avoid a statsoflow 2227 * interrupt. 2228 */ 2229 XL_SEL_WIN(4); 2230 CSR_READ_1(sc, XL_W4_BADSSD); 2231 2232 if ((mii != NULL) && (!sc->xl_stats_no_timeout)) 2233 mii_tick(mii); 2234 2235 XL_SEL_WIN(7); 2236 2237 if (!sc->xl_stats_no_timeout) 2238 sc->xl_stat_ch = timeout(xl_stats_update, sc, hz); 2239 2240 return; 2241 } 2242 2243 /* 2244 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 2245 * pointers to the fragment pointers. 2246 */ 2247 static int 2248 xl_encap(sc, c, m_head) 2249 struct xl_softc *sc; 2250 struct xl_chain *c; 2251 struct mbuf *m_head; 2252 { 2253 int frag; 2254 struct xl_frag *f = NULL; 2255 int total_len; 2256 struct mbuf *m; 2257 2258 /* 2259 * Start packing the mbufs in this chain into 2260 * the fragment pointers. Stop when we run out 2261 * of fragments or hit the end of the mbuf chain. 2262 */ 2263 m = m_head; 2264 total_len = 0; 2265 2266 for (m = m_head, frag = 0; m != NULL; m = m->m_next) { 2267 if (m->m_len != 0) { 2268 if (frag == XL_MAXFRAGS) 2269 break; 2270 total_len += m->m_len; 2271 f = &c->xl_ptr->xl_frag[frag]; 2272 f->xl_addr = vtophys(mtod(m, vm_offset_t)); 2273 f->xl_len = m->m_len; 2274 frag++; 2275 } 2276 } 2277 2278 /* 2279 * Handle special case: we used up all 63 fragments, 2280 * but we have more mbufs left in the chain. Copy the 2281 * data into an mbuf cluster. Note that we don't 2282 * bother clearing the values in the other fragment 2283 * pointers/counters; it wouldn't gain us anything, 2284 * and would waste cycles. 2285 */ 2286 if (m != NULL) { 2287 struct mbuf *m_new = NULL; 2288 2289 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 2290 if (m_new == NULL) { 2291 printf("xl%d: no memory for tx list", sc->xl_unit); 2292 return(1); 2293 } 2294 if (m_head->m_pkthdr.len > MHLEN) { 2295 MCLGET(m_new, M_DONTWAIT); 2296 if (!(m_new->m_flags & M_EXT)) { 2297 m_freem(m_new); 2298 printf("xl%d: no memory for tx list", 2299 sc->xl_unit); 2300 return(1); 2301 } 2302 } 2303 m_copydata(m_head, 0, m_head->m_pkthdr.len, 2304 mtod(m_new, caddr_t)); 2305 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 2306 m_freem(m_head); 2307 m_head = m_new; 2308 f = &c->xl_ptr->xl_frag[0]; 2309 f->xl_addr = vtophys(mtod(m_new, caddr_t)); 2310 f->xl_len = total_len = m_new->m_len; 2311 } 2312 2313 if (sc->xl_type == XL_TYPE_905B) { 2314 c->xl_ptr->xl_status = XL_TXSTAT_RND_DEFEAT; 2315 2316 if (m_head->m_pkthdr.csum_flags) { 2317 if (m_head->m_pkthdr.csum_flags & CSUM_IP) 2318 c->xl_ptr->xl_status |= XL_TXSTAT_IPCKSUM; 2319 if (m_head->m_pkthdr.csum_flags & CSUM_TCP) 2320 c->xl_ptr->xl_status |= XL_TXSTAT_TCPCKSUM; 2321 if (m_head->m_pkthdr.csum_flags & CSUM_UDP) 2322 c->xl_ptr->xl_status |= XL_TXSTAT_UDPCKSUM; 2323 } 2324 } else 2325 c->xl_ptr->xl_status = total_len; 2326 2327 c->xl_mbuf = m_head; 2328 f->xl_len |= XL_LAST_FRAG; 2329 c->xl_ptr->xl_next = 0; 2330 2331 return(0); 2332 } 2333 2334 /* 2335 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 2336 * to the mbuf data regions directly in the transmit lists. We also save a 2337 * copy of the pointers since the transmit list fragment pointers are 2338 * physical addresses. 2339 */ 2340 static void 2341 xl_start(ifp) 2342 struct ifnet *ifp; 2343 { 2344 struct xl_softc *sc; 2345 struct mbuf *m_head = NULL; 2346 struct xl_chain *prev = NULL, *cur_tx = NULL, *start_tx; 2347 2348 sc = ifp->if_softc; 2349 2350 /* 2351 * Check for an available queue slot. If there are none, 2352 * punt. 2353 */ 2354 if (sc->xl_cdata.xl_tx_free == NULL) { 2355 xl_txeoc(sc); 2356 xl_txeof(sc); 2357 if (sc->xl_cdata.xl_tx_free == NULL) { 2358 ifp->if_flags |= IFF_OACTIVE; 2359 return; 2360 } 2361 } 2362 2363 start_tx = sc->xl_cdata.xl_tx_free; 2364 2365 while(sc->xl_cdata.xl_tx_free != NULL) { 2366 IF_DEQUEUE(&ifp->if_snd, m_head); 2367 if (m_head == NULL) 2368 break; 2369 2370 /* Pick a descriptor off the free list. */ 2371 cur_tx = sc->xl_cdata.xl_tx_free; 2372 sc->xl_cdata.xl_tx_free = cur_tx->xl_next; 2373 2374 cur_tx->xl_next = NULL; 2375 2376 /* Pack the data into the descriptor. */ 2377 xl_encap(sc, cur_tx, m_head); 2378 2379 /* Chain it together. */ 2380 if (prev != NULL) { 2381 prev->xl_next = cur_tx; 2382 prev->xl_ptr->xl_next = vtophys(cur_tx->xl_ptr); 2383 } 2384 prev = cur_tx; 2385 2386 /* 2387 * If there's a BPF listener, bounce a copy of this frame 2388 * to him. 2389 */ 2390 if (ifp->if_bpf) 2391 bpf_mtap(ifp, cur_tx->xl_mbuf); 2392 } 2393 2394 /* 2395 * If there are no packets queued, bail. 2396 */ 2397 if (cur_tx == NULL) 2398 return; 2399 2400 /* 2401 * Place the request for the upload interrupt 2402 * in the last descriptor in the chain. This way, if 2403 * we're chaining several packets at once, we'll only 2404 * get an interupt once for the whole chain rather than 2405 * once for each packet. 2406 */ 2407 cur_tx->xl_ptr->xl_status |= XL_TXSTAT_DL_INTR; 2408 2409 /* 2410 * Queue the packets. If the TX channel is clear, update 2411 * the downlist pointer register. 2412 */ 2413 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_STALL); 2414 xl_wait(sc); 2415 2416 if (sc->xl_cdata.xl_tx_head != NULL) { 2417 sc->xl_cdata.xl_tx_tail->xl_next = start_tx; 2418 sc->xl_cdata.xl_tx_tail->xl_ptr->xl_next = 2419 vtophys(start_tx->xl_ptr); 2420 sc->xl_cdata.xl_tx_tail->xl_ptr->xl_status &= 2421 ~XL_TXSTAT_DL_INTR; 2422 sc->xl_cdata.xl_tx_tail = cur_tx; 2423 } else { 2424 sc->xl_cdata.xl_tx_head = start_tx; 2425 sc->xl_cdata.xl_tx_tail = cur_tx; 2426 } 2427 if (!CSR_READ_4(sc, XL_DOWNLIST_PTR)) 2428 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, vtophys(start_tx->xl_ptr)); 2429 2430 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); 2431 2432 XL_SEL_WIN(7); 2433 2434 /* 2435 * Set a timeout in case the chip goes out to lunch. 2436 */ 2437 ifp->if_timer = 5; 2438 2439 /* 2440 * XXX Under certain conditions, usually on slower machines 2441 * where interrupts may be dropped, it's possible for the 2442 * adapter to chew up all the buffers in the receive ring 2443 * and stall, without us being able to do anything about it. 2444 * To guard against this, we need to make a pass over the 2445 * RX queue to make sure there aren't any packets pending. 2446 * Doing it here means we can flush the receive ring at the 2447 * same time the chip is DMAing the transmit descriptors we 2448 * just gave it. 2449 * 2450 * 3Com goes to some lengths to emphasize the Parallel Tasking (tm) 2451 * nature of their chips in all their marketing literature; 2452 * we may as well take advantage of it. :) 2453 */ 2454 xl_rxeof(sc); 2455 2456 return; 2457 } 2458 2459 static void xl_start_90xB(ifp) 2460 struct ifnet *ifp; 2461 { 2462 struct xl_softc *sc; 2463 struct mbuf *m_head = NULL; 2464 struct xl_chain *prev = NULL, *cur_tx = NULL, *start_tx; 2465 int idx; 2466 2467 sc = ifp->if_softc; 2468 2469 if (ifp->if_flags & IFF_OACTIVE) 2470 return; 2471 2472 idx = sc->xl_cdata.xl_tx_prod; 2473 start_tx = &sc->xl_cdata.xl_tx_chain[idx]; 2474 2475 while (sc->xl_cdata.xl_tx_chain[idx].xl_mbuf == NULL) { 2476 2477 if ((XL_TX_LIST_CNT - sc->xl_cdata.xl_tx_cnt) < 3) { 2478 ifp->if_flags |= IFF_OACTIVE; 2479 break; 2480 } 2481 2482 IF_DEQUEUE(&ifp->if_snd, m_head); 2483 if (m_head == NULL) 2484 break; 2485 2486 cur_tx = &sc->xl_cdata.xl_tx_chain[idx]; 2487 2488 /* Pack the data into the descriptor. */ 2489 xl_encap(sc, cur_tx, m_head); 2490 2491 /* Chain it together. */ 2492 if (prev != NULL) 2493 prev->xl_ptr->xl_next = cur_tx->xl_phys; 2494 prev = cur_tx; 2495 2496 /* 2497 * If there's a BPF listener, bounce a copy of this frame 2498 * to him. 2499 */ 2500 if (ifp->if_bpf) 2501 bpf_mtap(ifp, cur_tx->xl_mbuf); 2502 2503 XL_INC(idx, XL_TX_LIST_CNT); 2504 sc->xl_cdata.xl_tx_cnt++; 2505 } 2506 2507 /* 2508 * If there are no packets queued, bail. 2509 */ 2510 if (cur_tx == NULL) 2511 return; 2512 2513 /* 2514 * Place the request for the upload interrupt 2515 * in the last descriptor in the chain. This way, if 2516 * we're chaining several packets at once, we'll only 2517 * get an interupt once for the whole chain rather than 2518 * once for each packet. 2519 */ 2520 cur_tx->xl_ptr->xl_status |= XL_TXSTAT_DL_INTR; 2521 2522 /* Start transmission */ 2523 sc->xl_cdata.xl_tx_prod = idx; 2524 start_tx->xl_prev->xl_ptr->xl_next = start_tx->xl_phys; 2525 2526 /* 2527 * Set a timeout in case the chip goes out to lunch. 2528 */ 2529 ifp->if_timer = 5; 2530 2531 return; 2532 } 2533 2534 static void 2535 xl_init(xsc) 2536 void *xsc; 2537 { 2538 struct xl_softc *sc = xsc; 2539 struct ifnet *ifp = &sc->arpcom.ac_if; 2540 int s, i; 2541 u_int16_t rxfilt = 0; 2542 struct mii_data *mii = NULL; 2543 2544 s = splimp(); 2545 2546 /* 2547 * Cancel pending I/O and free all RX/TX buffers. 2548 */ 2549 xl_stop(sc); 2550 2551 if (sc->xl_miibus == NULL) { 2552 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET); 2553 xl_wait(sc); 2554 } 2555 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); 2556 xl_wait(sc); 2557 DELAY(10000); 2558 2559 if (sc->xl_miibus != NULL) 2560 mii = device_get_softc(sc->xl_miibus); 2561 2562 /* Init our MAC address */ 2563 XL_SEL_WIN(2); 2564 for (i = 0; i < ETHER_ADDR_LEN; i++) { 2565 CSR_WRITE_1(sc, XL_W2_STATION_ADDR_LO + i, 2566 sc->arpcom.ac_enaddr[i]); 2567 } 2568 2569 /* Clear the station mask. */ 2570 for (i = 0; i < 3; i++) 2571 CSR_WRITE_2(sc, XL_W2_STATION_MASK_LO + (i * 2), 0); 2572 #ifdef notdef 2573 /* Reset TX and RX. */ 2574 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET); 2575 xl_wait(sc); 2576 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); 2577 xl_wait(sc); 2578 #endif 2579 /* Init circular RX list. */ 2580 if (xl_list_rx_init(sc) == ENOBUFS) { 2581 printf("xl%d: initialization failed: no " 2582 "memory for rx buffers\n", sc->xl_unit); 2583 xl_stop(sc); 2584 splx(s); 2585 return; 2586 } 2587 2588 /* Init TX descriptors. */ 2589 if (sc->xl_type == XL_TYPE_905B) 2590 xl_list_tx_init_90xB(sc); 2591 else 2592 xl_list_tx_init(sc); 2593 2594 /* 2595 * Set the TX freethresh value. 2596 * Note that this has no effect on 3c905B "cyclone" 2597 * cards but is required for 3c900/3c905 "boomerang" 2598 * cards in order to enable the download engine. 2599 */ 2600 CSR_WRITE_1(sc, XL_TX_FREETHRESH, XL_PACKET_SIZE >> 8); 2601 2602 /* Set the TX start threshold for best performance. */ 2603 sc->xl_tx_thresh = XL_MIN_FRAMELEN; 2604 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_SET_START|sc->xl_tx_thresh); 2605 2606 /* 2607 * If this is a 3c905B, also set the tx reclaim threshold. 2608 * This helps cut down on the number of tx reclaim errors 2609 * that could happen on a busy network. The chip multiplies 2610 * the register value by 16 to obtain the actual threshold 2611 * in bytes, so we divide by 16 when setting the value here. 2612 * The existing threshold value can be examined by reading 2613 * the register at offset 9 in window 5. 2614 */ 2615 if (sc->xl_type == XL_TYPE_905B) { 2616 CSR_WRITE_2(sc, XL_COMMAND, 2617 XL_CMD_SET_TX_RECLAIM|(XL_PACKET_SIZE >> 4)); 2618 } 2619 2620 /* Set RX filter bits. */ 2621 XL_SEL_WIN(5); 2622 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER); 2623 2624 /* Set the individual bit to receive frames for this host only. */ 2625 rxfilt |= XL_RXFILTER_INDIVIDUAL; 2626 2627 /* If we want promiscuous mode, set the allframes bit. */ 2628 if (ifp->if_flags & IFF_PROMISC) { 2629 rxfilt |= XL_RXFILTER_ALLFRAMES; 2630 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 2631 } else { 2632 rxfilt &= ~XL_RXFILTER_ALLFRAMES; 2633 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 2634 } 2635 2636 /* 2637 * Set capture broadcast bit to capture broadcast frames. 2638 */ 2639 if (ifp->if_flags & IFF_BROADCAST) { 2640 rxfilt |= XL_RXFILTER_BROADCAST; 2641 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 2642 } else { 2643 rxfilt &= ~XL_RXFILTER_BROADCAST; 2644 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 2645 } 2646 2647 /* 2648 * Program the multicast filter, if necessary. 2649 */ 2650 if (sc->xl_type == XL_TYPE_905B) 2651 xl_setmulti_hash(sc); 2652 else 2653 xl_setmulti(sc); 2654 2655 /* 2656 * Load the address of the RX list. We have to 2657 * stall the upload engine before we can manipulate 2658 * the uplist pointer register, then unstall it when 2659 * we're finished. We also have to wait for the 2660 * stall command to complete before proceeding. 2661 * Note that we have to do this after any RX resets 2662 * have completed since the uplist register is cleared 2663 * by a reset. 2664 */ 2665 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_STALL); 2666 xl_wait(sc); 2667 CSR_WRITE_4(sc, XL_UPLIST_PTR, vtophys(&sc->xl_ldata->xl_rx_list[0])); 2668 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_UNSTALL); 2669 xl_wait(sc); 2670 2671 2672 if (sc->xl_type == XL_TYPE_905B) { 2673 /* Set polling interval */ 2674 CSR_WRITE_1(sc, XL_DOWN_POLL, 64); 2675 /* Load the address of the TX list */ 2676 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_STALL); 2677 xl_wait(sc); 2678 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, 2679 vtophys(&sc->xl_ldata->xl_tx_list[0])); 2680 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); 2681 xl_wait(sc); 2682 } 2683 2684 /* 2685 * If the coax transceiver is on, make sure to enable 2686 * the DC-DC converter. 2687 */ 2688 XL_SEL_WIN(3); 2689 if (sc->xl_xcvr == XL_XCVR_COAX) 2690 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_START); 2691 else 2692 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP); 2693 2694 /* increase packet size to allow reception of 802.1q or ISL packets */ 2695 if (sc->xl_type == XL_TYPE_905B) 2696 CSR_WRITE_2(sc, XL_W3_MAXPKTSIZE, XL_PACKET_SIZE); 2697 /* Clear out the stats counters. */ 2698 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_DISABLE); 2699 sc->xl_stats_no_timeout = 1; 2700 xl_stats_update(sc); 2701 sc->xl_stats_no_timeout = 0; 2702 XL_SEL_WIN(4); 2703 CSR_WRITE_2(sc, XL_W4_NET_DIAG, XL_NETDIAG_UPPER_BYTES_ENABLE); 2704 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_ENABLE); 2705 2706 /* 2707 * Enable interrupts. 2708 */ 2709 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ACK|0xFF); 2710 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STAT_ENB|XL_INTRS); 2711 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|XL_INTRS); 2712 if (sc->xl_flags & XL_FLAG_FUNCREG) bus_space_write_4 (sc->xl_ftag, sc->xl_fhandle, 4, 0x8000); 2713 2714 /* Set the RX early threshold */ 2715 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_THRESH|(XL_PACKET_SIZE >>2)); 2716 CSR_WRITE_2(sc, XL_DMACTL, XL_DMACTL_UP_RX_EARLY); 2717 2718 /* Enable receiver and transmitter. */ 2719 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE); 2720 xl_wait(sc); 2721 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_ENABLE); 2722 xl_wait(sc); 2723 2724 if (mii != NULL) 2725 mii_mediachg(mii); 2726 2727 /* Select window 7 for normal operations. */ 2728 XL_SEL_WIN(7); 2729 2730 ifp->if_flags |= IFF_RUNNING; 2731 ifp->if_flags &= ~IFF_OACTIVE; 2732 2733 (void)splx(s); 2734 2735 sc->xl_stat_ch = timeout(xl_stats_update, sc, hz); 2736 2737 return; 2738 } 2739 2740 /* 2741 * Set media options. 2742 */ 2743 static int 2744 xl_ifmedia_upd(ifp) 2745 struct ifnet *ifp; 2746 { 2747 struct xl_softc *sc; 2748 struct ifmedia *ifm = NULL; 2749 struct mii_data *mii = NULL; 2750 2751 sc = ifp->if_softc; 2752 if (sc->xl_miibus != NULL) 2753 mii = device_get_softc(sc->xl_miibus); 2754 if (mii == NULL) 2755 ifm = &sc->ifmedia; 2756 else 2757 ifm = &mii->mii_media; 2758 2759 switch(IFM_SUBTYPE(ifm->ifm_media)) { 2760 case IFM_100_FX: 2761 case IFM_10_FL: 2762 case IFM_10_2: 2763 case IFM_10_5: 2764 xl_setmode(sc, ifm->ifm_media); 2765 return(0); 2766 break; 2767 default: 2768 break; 2769 } 2770 2771 if (sc->xl_media & XL_MEDIAOPT_MII || sc->xl_media & XL_MEDIAOPT_BTX 2772 || sc->xl_media & XL_MEDIAOPT_BT4) { 2773 xl_init(sc); 2774 } else { 2775 xl_setmode(sc, ifm->ifm_media); 2776 } 2777 2778 return(0); 2779 } 2780 2781 /* 2782 * Report current media status. 2783 */ 2784 static void 2785 xl_ifmedia_sts(ifp, ifmr) 2786 struct ifnet *ifp; 2787 struct ifmediareq *ifmr; 2788 { 2789 struct xl_softc *sc; 2790 u_int32_t icfg; 2791 struct mii_data *mii = NULL; 2792 2793 sc = ifp->if_softc; 2794 if (sc->xl_miibus != NULL) 2795 mii = device_get_softc(sc->xl_miibus); 2796 2797 XL_SEL_WIN(3); 2798 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG) & XL_ICFG_CONNECTOR_MASK; 2799 icfg >>= XL_ICFG_CONNECTOR_BITS; 2800 2801 ifmr->ifm_active = IFM_ETHER; 2802 2803 switch(icfg) { 2804 case XL_XCVR_10BT: 2805 ifmr->ifm_active = IFM_ETHER|IFM_10_T; 2806 if (CSR_READ_1(sc, XL_W3_MAC_CTRL) & XL_MACCTRL_DUPLEX) 2807 ifmr->ifm_active |= IFM_FDX; 2808 else 2809 ifmr->ifm_active |= IFM_HDX; 2810 break; 2811 case XL_XCVR_AUI: 2812 if (sc->xl_type == XL_TYPE_905B && 2813 sc->xl_media == XL_MEDIAOPT_10FL) { 2814 ifmr->ifm_active = IFM_ETHER|IFM_10_FL; 2815 if (CSR_READ_1(sc, XL_W3_MAC_CTRL) & XL_MACCTRL_DUPLEX) 2816 ifmr->ifm_active |= IFM_FDX; 2817 else 2818 ifmr->ifm_active |= IFM_HDX; 2819 } else 2820 ifmr->ifm_active = IFM_ETHER|IFM_10_5; 2821 break; 2822 case XL_XCVR_COAX: 2823 ifmr->ifm_active = IFM_ETHER|IFM_10_2; 2824 break; 2825 /* 2826 * XXX MII and BTX/AUTO should be separate cases. 2827 */ 2828 2829 case XL_XCVR_100BTX: 2830 case XL_XCVR_AUTO: 2831 case XL_XCVR_MII: 2832 if (mii != NULL) { 2833 mii_pollstat(mii); 2834 ifmr->ifm_active = mii->mii_media_active; 2835 ifmr->ifm_status = mii->mii_media_status; 2836 } 2837 break; 2838 case XL_XCVR_100BFX: 2839 ifmr->ifm_active = IFM_ETHER|IFM_100_FX; 2840 break; 2841 default: 2842 printf("xl%d: unknown XCVR type: %d\n", sc->xl_unit, icfg); 2843 break; 2844 } 2845 2846 return; 2847 } 2848 2849 static int 2850 xl_ioctl(ifp, command, data) 2851 struct ifnet *ifp; 2852 u_long command; 2853 caddr_t data; 2854 { 2855 struct xl_softc *sc = ifp->if_softc; 2856 struct ifreq *ifr = (struct ifreq *) data; 2857 int s, error = 0; 2858 struct mii_data *mii = NULL; 2859 u_int8_t rxfilt; 2860 2861 s = splimp(); 2862 2863 switch(command) { 2864 case SIOCSIFADDR: 2865 case SIOCGIFADDR: 2866 case SIOCSIFMTU: 2867 error = ether_ioctl(ifp, command, data); 2868 break; 2869 case SIOCSIFFLAGS: 2870 XL_SEL_WIN(5); 2871 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER); 2872 if (ifp->if_flags & IFF_UP) { 2873 if (ifp->if_flags & IFF_RUNNING && 2874 ifp->if_flags & IFF_PROMISC && 2875 !(sc->xl_if_flags & IFF_PROMISC)) { 2876 rxfilt |= XL_RXFILTER_ALLFRAMES; 2877 CSR_WRITE_2(sc, XL_COMMAND, 2878 XL_CMD_RX_SET_FILT|rxfilt); 2879 XL_SEL_WIN(7); 2880 } else if (ifp->if_flags & IFF_RUNNING && 2881 !(ifp->if_flags & IFF_PROMISC) && 2882 sc->xl_if_flags & IFF_PROMISC) { 2883 rxfilt &= ~XL_RXFILTER_ALLFRAMES; 2884 CSR_WRITE_2(sc, XL_COMMAND, 2885 XL_CMD_RX_SET_FILT|rxfilt); 2886 XL_SEL_WIN(7); 2887 } else 2888 xl_init(sc); 2889 } else { 2890 if (ifp->if_flags & IFF_RUNNING) 2891 xl_stop(sc); 2892 } 2893 sc->xl_if_flags = ifp->if_flags; 2894 error = 0; 2895 break; 2896 case SIOCADDMULTI: 2897 case SIOCDELMULTI: 2898 if (sc->xl_type == XL_TYPE_905B) 2899 xl_setmulti_hash(sc); 2900 else 2901 xl_setmulti(sc); 2902 error = 0; 2903 break; 2904 case SIOCGIFMEDIA: 2905 case SIOCSIFMEDIA: 2906 if (sc->xl_miibus != NULL) 2907 mii = device_get_softc(sc->xl_miibus); 2908 if (mii == NULL) 2909 error = ifmedia_ioctl(ifp, ifr, 2910 &sc->ifmedia, command); 2911 else 2912 error = ifmedia_ioctl(ifp, ifr, 2913 &mii->mii_media, command); 2914 break; 2915 default: 2916 error = EINVAL; 2917 break; 2918 } 2919 2920 (void)splx(s); 2921 2922 return(error); 2923 } 2924 2925 static void 2926 xl_watchdog(ifp) 2927 struct ifnet *ifp; 2928 { 2929 struct xl_softc *sc; 2930 u_int16_t status = 0; 2931 2932 sc = ifp->if_softc; 2933 2934 ifp->if_oerrors++; 2935 XL_SEL_WIN(4); 2936 status = CSR_READ_2(sc, XL_W4_MEDIA_STATUS); 2937 printf("xl%d: watchdog timeout\n", sc->xl_unit); 2938 2939 if (status & XL_MEDIASTAT_CARRIER) 2940 printf("xl%d: no carrier - transceiver cable problem?\n", 2941 sc->xl_unit); 2942 xl_txeoc(sc); 2943 xl_txeof(sc); 2944 xl_rxeof(sc); 2945 xl_reset(sc); 2946 xl_init(sc); 2947 2948 if (ifp->if_snd.ifq_head != NULL) 2949 (*ifp->if_start)(ifp); 2950 2951 return; 2952 } 2953 2954 /* 2955 * Stop the adapter and free any mbufs allocated to the 2956 * RX and TX lists. 2957 */ 2958 static void 2959 xl_stop(sc) 2960 struct xl_softc *sc; 2961 { 2962 int i; 2963 struct ifnet *ifp; 2964 2965 ifp = &sc->arpcom.ac_if; 2966 ifp->if_timer = 0; 2967 2968 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_DISABLE); 2969 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_DISABLE); 2970 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB); 2971 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_DISCARD); 2972 xl_wait(sc); 2973 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_DISABLE); 2974 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP); 2975 DELAY(800); 2976 2977 #ifdef foo 2978 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET); 2979 xl_wait(sc); 2980 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); 2981 xl_wait(sc); 2982 #endif 2983 2984 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ACK|XL_STAT_INTLATCH); 2985 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STAT_ENB|0); 2986 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|0); 2987 if (sc->xl_flags & XL_FLAG_FUNCREG) bus_space_write_4 (sc->xl_ftag, sc->xl_fhandle, 4, 0x8000); 2988 2989 /* Stop the stats updater. */ 2990 untimeout(xl_stats_update, sc, sc->xl_stat_ch); 2991 2992 /* 2993 * Free data in the RX lists. 2994 */ 2995 for (i = 0; i < XL_RX_LIST_CNT; i++) { 2996 if (sc->xl_cdata.xl_rx_chain[i].xl_mbuf != NULL) { 2997 m_freem(sc->xl_cdata.xl_rx_chain[i].xl_mbuf); 2998 sc->xl_cdata.xl_rx_chain[i].xl_mbuf = NULL; 2999 } 3000 } 3001 bzero((char *)&sc->xl_ldata->xl_rx_list, 3002 sizeof(sc->xl_ldata->xl_rx_list)); 3003 /* 3004 * Free the TX list buffers. 3005 */ 3006 for (i = 0; i < XL_TX_LIST_CNT; i++) { 3007 if (sc->xl_cdata.xl_tx_chain[i].xl_mbuf != NULL) { 3008 m_freem(sc->xl_cdata.xl_tx_chain[i].xl_mbuf); 3009 sc->xl_cdata.xl_tx_chain[i].xl_mbuf = NULL; 3010 } 3011 } 3012 bzero((char *)&sc->xl_ldata->xl_tx_list, 3013 sizeof(sc->xl_ldata->xl_tx_list)); 3014 3015 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 3016 3017 return; 3018 } 3019 3020 /* 3021 * Stop all chip I/O so that the kernel's probe routines don't 3022 * get confused by errant DMAs when rebooting. 3023 */ 3024 static void 3025 xl_shutdown(dev) 3026 device_t dev; 3027 { 3028 struct xl_softc *sc; 3029 3030 sc = device_get_softc(dev); 3031 3032 xl_reset(sc); 3033 xl_stop(sc); 3034 3035 return; 3036 } 3037 3038 static int 3039 xl_suspend(dev) 3040 device_t dev; 3041 { 3042 struct xl_softc *sc; 3043 int s; 3044 3045 sc = device_get_softc(dev); 3046 3047 s = splimp(); 3048 xl_stop(sc); 3049 splx(s); 3050 3051 return(0); 3052 } 3053 3054 static int 3055 xl_resume(dev) 3056 device_t dev; 3057 { 3058 struct xl_softc *sc; 3059 struct ifnet *ifp; 3060 int s; 3061 3062 s = splimp(); 3063 sc = device_get_softc(dev); 3064 ifp = &sc->arpcom.ac_if; 3065 3066 xl_reset(sc); 3067 if (ifp->if_flags & IFF_UP) 3068 xl_init(sc); 3069 3070 splx(s); 3071 return(0); 3072 } 3073